Re: [PATCH 2/6] usb: xhci: Set up endpoints for the first 2 interfaces
Hej, On Sun, Feb 25, 2024, at 22:47, Marek Vasut wrote: > On 2/25/24 4:28 PM, Janne Grunau wrote: >> >> >> On Wed, Feb 21, 2024, at 13:39, Marek Vasut wrote: >>> On 2/21/24 08:25, Janne Grunau via B4 Relay wrote: From: Janne Grunau Apple USB keyboards carry the HID keyboard boot protocol on the second interface. Using the second interface in the USB keyboard driver does not work since the xhci has not allocated a transfer ring. >>> >>> So, what does this patch do ? That is not clear from the commit message. >> >> rewritten for v2: >> | usb: xhci: Set up endpoints for the first 2 interfaces >> | >> | The xhci driver currently only does the necessary initialization for >> | endpoints found in the first interface descriptor. Apple USB keyboards >> | (released 2021) use the second interface descriptor for the HID keyboard >> | boot protocol. To allow USB drivers to use endpoints from other >> | interface descriptors the xhci driver needs to ensure these endpoints >> | are initialized as well. >> | Use USB_MAX_ACTIVE_INTERFACES to control how many interface descriptors >> | are initialized and useable. Currently defined to 2 as that is enough to >> | make the Apple keyboard usable. > > Would it make sense to make this a tunable Kconfig option ? I thought about that but I don't think it's worth it. We would have to default it to 2 (at least when the USB keyboard driver is enabled) since we can't predict which devices will be connected. Why would anyone chose a different value than the fixed value? I can't think of convincing reasons. Janne
Re: [PATCH 4/6] usb: kbd: Ignore Yubikeys
Hej,
On Mon, Feb 26, 2024, at 21:47, Mark Kettenis wrote:
>> Date: Sun, 25 Feb 2024 22:57:23 +0100
>> From: Marek Vasut
>>
>> On 2/25/24 5:07 PM, Janne Grunau wrote:
>> > Hej,
>> >
>> > On Wed, Feb 21, 2024, at 13:41, Marek Vasut wrote:
>> >> On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
>> >>> From: Hector Martin
>> >>>
>> >>> We currently only support one USB keyboard device, but some devices
>> >>> emulate keyboards for other purposes. Most commonly, people run into
>> >>> this with Yubikeys, so let's ignore those.
>> >>>
>> >>> Even if we end up supporting multiple keyboards in the future, it's
>> >>> safer to ignore known non-keyboard devices.
>> >>>
>> >>> Signed-off-by: Hector Martin
>> >>> ---
>> >>>common/usb_kbd.c | 19 +++
>> >>>1 file changed, 19 insertions(+)
>> >>>
>> >>> diff --git a/common/usb_kbd.c b/common/usb_kbd.c
>> >>> index 4cbc9acb73..774d3555d9 100644
>> >>> --- a/common/usb_kbd.c
>> >>> +++ b/common/usb_kbd.c
>> >>> @@ -120,6 +120,15 @@ struct usb_kbd_pdata {
>> >>>
>> >>>extern int __maybe_unused net_busy_flag;
>> >>>
>> >>> +/*
>> >>> + * Since we only support one usbkbd device in the iomux,
>> >>> + * ignore common keyboard-emulating devices that aren't
>> >>> + * real keyboards.
>> >>> + */
>> >>> +const uint16_t vid_blocklist[] = {
>> >>> +0x1050, /* Yubico */
>> >>> +};
>> >>> +
>> >>>/* The period of time between two calls of usb_kbd_testc(). */
>> >>>static unsigned long kbd_testc_tms;
>> >>>
>> >>> @@ -465,6 +474,7 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
>> >>> unsigned int ifnum)
>> >>> struct usb_endpoint_descriptor *ep;
>> >>> struct usb_kbd_pdata *data;
>> >>> int epNum;
>> >>> +int i;
>> >>>
>> >>> if (dev->descriptor.bNumConfigurations != 1)
>> >>> return 0;
>> >>> @@ -480,6 +490,15 @@ static int usb_kbd_probe_dev(struct usb_device
>> >>> *dev, unsigned int ifnum)
>> >>> if (iface->desc.bInterfaceProtocol != USB_PROT_HID_KEYBOARD)
>> >>> return 0;
>> >>>
>> >>> +for (i = 0; i < ARRAY_SIZE(vid_blocklist); i++) {
>> >>> +if (dev->descriptor.idVendor == vid_blocklist[i]) {
>> >>> +printf("Ignoring keyboard device 0x%x:0x%x\n",
>> >>> + dev->descriptor.idVendor,
>> >>> + dev->descriptor.idProduct);
>> >>> +return 0;
>> >>> +}
>> >>> +}
>> >>
>> >> I vaguely recall a discussion about previous version of this, I think
>> >> the suggestion was to make the list of ignored devices configurable via
>> >> environment variable, so users can add to that list from U-Boot shell.
>> >> Would it be possible to make it work this way ?
>> >
>> > oh, I completely forgot that this patch was already submitted. I briefly
>> > looked through asahi tree for related patches and did not check whether
>> > this was previously submitted.
>> > I've added environment based blocking as separate patch with blocking
>> > either complete vendor IDs or vendor, product ID combinations. A separate
>> > patch to simplify authorship tracking and the implementation doesn't share
>> > any code.
>>
>> It would be better to have only one patch which does not hard-code any
>> USB IDs, and then add those blocked IDs via U-Boot default environment
>> for this specific machine. We cannot predict what yubico will do in the
>> future, whether they might make a device that shouldn't be blocked for
>> example. If they do, the user should be able to unblock their device by
>> running e.g. '=> setenv usb_blocklist' instead of updating their bootloader.
>>
>> I think a simple list of blocked VID:PID pairs, maybe with wildcards,
>> would be nice, i.e. something like 'usb_blocklist=1234:5678,1050:*' to
>> block device 0x1234:0x5678 and all devices with VID 0x1050 . That should
>> be easy to parse with strtok()/strtol() or some such and the code should
>> not be too complex.
>
> I do like the idea of having a configurable list of usb devices to
> ignore. The U-Boot USB stack is still not perfect and there are still
> USB devices that will prevent us from booting when connected. The
> list will provide a nice workaround for that issue.
That sounds like we should ignore USB devices in usb_scan_device() and not in
the keyboard driver.
> But the yubikeys will cause the same problem on other boards as well.
> So I think it makes sense to put those in a default list.
We could move the list to a CONFIG symbol which has Yubikey's vendor ID as
default value now that we do string parsing anyway.
Janne
[PATCH v1 3/3] board: amlogic: jethubj100: update docs
Improove documentation, add new revision. Signed-off-by: Viacheslav Bocharov --- doc/board/amlogic/jethub-j100.rst | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/doc/board/amlogic/jethub-j100.rst b/doc/board/amlogic/jethub-j100.rst index 86acdafa06f..80bed6e919e 100644 --- a/doc/board/amlogic/jethub-j100.rst +++ b/doc/board/amlogic/jethub-j100.rst @@ -1,9 +1,9 @@ .. SPDX-License-Identifier: GPL-2.0+ -U-Boot for JetHub J100 (A113X) +U-Boot for JetHub J100/J110 (A113X) == -JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller device +JetHome Jethub D1/D1+ (http://jethome.ru/jethub-d1p) is a home automation controller device manufactured by JetHome with the following specifications: - Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz @@ -23,7 +23,10 @@ manufactured by JetHome with the following specifications: The basic version also has: - - TI CC2538 + CC2592 Zigbee Wireless with upto 20dBm output power and Zigbee 3.0 + - Zigbee module one from: + - TI CC2538 + CC2592 Zigbee 3.0 Wireless + - TI CC2652P1 Zigbee 3.0 Wireless + - Silicon Labs EFT32MG21 Zigbee 3.0/Thread Wireless - 1 x 1-Wire - 2 x RS-485 - 4 x dry contact digital GPIO inputs -- 2.43.2
[PATCH v1 2/3] board: amlogic: jethubj100: update MAINTAINERS
Fix mispell in maintainer name for jethub j100 board files Signed-off-by: Viacheslav Bocharov --- board/amlogic/jethub-j100/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/amlogic/jethub-j100/MAINTAINERS b/board/amlogic/jethub-j100/MAINTAINERS index 43f6a5fc86b..3edc5d8865c 100644 --- a/board/amlogic/jethub-j100/MAINTAINERS +++ b/board/amlogic/jethub-j100/MAINTAINERS @@ -1,5 +1,5 @@ JetHome JetHub -M: Vyacheslav Bocharov +M: Viacheslav Bocharov S: Maintained L: u-boot-amlo...@groups.io F: board/amlogic/jethub-j100/ -- 2.43.2
[PATCH v1 1/3] board: amlogic: jethubj100: fix common config header
Fix JetHub board sequence to read correct gpio for rescue button Signed-off-by: Viacheslav Bocharov --- include/configs/jethub.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/jethub.h b/include/configs/jethub.h index e22db4991de..2c44bfc853e 100644 --- a/include/configs/jethub.h +++ b/include/configs/jethub.h @@ -11,7 +11,7 @@ #if defined(CONFIG_MESON_AXG) #define BOOTENV_DEV_RESCUE(devtypeu, devtypel, instance) \ "bootcmd_rescue=" \ - "if gpio input 10; then " \ + "if gpio input periphs-banks10; then " \ "run bootcmd_mmc0; " \ "run bootcmd_usb0;" \ "fi;\0" -- 2.43.2
[PATCH v1 0/3] board: amlogic: jethubj100: small updates
Update JetHub D1/D1+ board support files. Viacheslav Bocharov (3): board: amlogic: jethubj100: fix common config header board: amlogic: jethubj100: update MAINTAINERS board: amlogic: jethubj100: update docs board/amlogic/jethub-j100/MAINTAINERS | 2 +- doc/board/amlogic/jethub-j100.rst | 9 ++--- include/configs/jethub.h | 2 +- 3 files changed, 8 insertions(+), 5 deletions(-) base-commit: d49fa3defa50c6d3f04acbb52fd486c13c14ab6a -- 2.43.2
Re: [PATCH v5 07/39] serial: msm: add debug UART
On Mon, 26 Feb 2024 at 22:56, Caleb Connolly wrote:
>
> Introduce support for early debugging. This relies on the previous stage
> bootloader to initialise the UART clocks, when running with U-Boot as
> the primary bootloader this feature doesn't work. It will require a way
> to configure the clocks before the driver model is available.
>
> Reviewed-by: Neil Armstrong
> Signed-off-by: Caleb Connolly
> ---
> drivers/serial/Kconfig | 8
> drivers/serial/serial_msm.c | 37 +
> 2 files changed, 45 insertions(+)
>
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
> index 26460c4e0cab..fbd351a47859 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -318,8 +318,16 @@ config DEBUG_UART_S5P
> Select this to enable a debug UART using the serial_s5p driver. You
> will need to provide parameters to make this work. The driver will
> be available until the real driver-model serial is running.
>
> +config DEBUG_UART_MSM
> + bool "Qualcomm QUP UART debug"
> + depends on ARCH_SNAPDRAGON
> + help
> + Select this to enable a debug UART using the serial_msm driver. You
> + will need to provide parameters to make this work. The driver will
> + be available until the real driver-model serial is running.
> +
> config DEBUG_UART_MSM_GENI
> bool "Qualcomm snapdragon"
> depends on ARCH_SNAPDRAGON
> help
> diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
> index f4d96313b931..44b93bd7ff21 100644
> --- a/drivers/serial/serial_msm.c
> +++ b/drivers/serial/serial_msm.c
> @@ -251,4 +251,41 @@ U_BOOT_DRIVER(serial_msm) = {
> .priv_auto = sizeof(struct msm_serial_data),
> .probe = msm_serial_probe,
> .ops= _serial_ops,
> };
> +
> +#ifdef CONFIG_DEBUG_UART_MSM
> +
> +static struct msm_serial_data init_serial_data = {
> + .base = CONFIG_VAL(DEBUG_UART_BASE),
> + .clk_rate = 7372800,
> +};
> +
> +#include
> +
> +/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on
> MSM8916 */
> +//int apq8016_clk_init_uart(phys_addr_t gcc_base);
> +
Okay I can live with these comments such that the user is aware before
enabling debug UART on db410c.
Reviewed-by: Sumit Garg
-Sumit
> +static inline void _debug_uart_init(void)
> +{
> + /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on
> MSM8916 */
> + //apq8016_clk_init_uart(0x180);
> + uart_dm_init(_serial_data);
> +}
> +
> +static inline void _debug_uart_putc(int ch)
> +{
> + struct msm_serial_data *priv = _serial_data;
> +
> + while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
> + !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
> + ;
> +
> + writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
> +
> + writel(1, priv->base + UARTDM_NCF_TX);
> + writel(ch, priv->base + UARTDM_TF);
> +}
> +
> +DEBUG_UART_FUNCS
> +
> +#endif
>
> --
> 2.43.1
>
Re: [PATCH v5 23/39] mach-snapdragon: carve out no-map regions
On Mon, 26 Feb 2024 at 22:56, Caleb Connolly wrote:
>
> On Qualcomm platforms, the TZ may already have certain memory regions
> under protection by the time U-Boot starts. There is a rare case on some
> platforms where the prefetcher might speculatively access one of these
> regions resulting in a board crash (TZ traps and then resets the board).
>
> We shouldn't be accessing these regions from within U-Boot anyway, so
> let's mark them all with PTE_TYPE_FAULT to prevent any speculative
> access and correctly trap in EL1 rather than EL3.
>
> This is quite costly with caches off (takes ~2 seconds on SDM845 vs 35ms
> with caches on). So to minimise the impact this is only enabled on
> QCS404 for now (where the issue is known to occur).
>
> In the future, we should try to find a more efficient way to handle
> this, perhaps by turning on the MMU in stages.
>
> Reviewed-by: Sumit Garg
> Tested-by: Sumit Garg #qcs404
> Signed-off-by: Caleb Connolly
> ---
> arch/arm/mach-snapdragon/board.c | 162
> +--
> 1 file changed, 140 insertions(+), 22 deletions(-)
>
I still can't see commit message updates as per [1], probably you can
take care of them while applying this patch-set.
[1]
https://lore.kernel.org/all/CAFA6WYPg=mbrvlqtdaq1omzeku6wcbnt_dwbqv4h36swb3-...@mail.gmail.com/#t
-Sumit
> diff --git a/arch/arm/mach-snapdragon/board.c
> b/arch/arm/mach-snapdragon/board.c
> index 5a859aabd5c4..f12f5791a136 100644
> --- a/arch/arm/mach-snapdragon/board.c
> +++ b/arch/arm/mach-snapdragon/board.c
> @@ -24,8 +24,9 @@
> #include
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
> @@ -295,9 +296,9 @@ int board_late_init(void)
> }
>
> static void build_mem_map(void)
> {
> - int i;
> + int i, j;
>
> /*
> * Ensure the peripheral block is sized to correctly cover the
> address range
> * up to the first memory bank.
> @@ -311,40 +312,157 @@ static void build_mem_map(void)
> mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> PTE_BLOCK_NON_SHARE |
> PTE_BLOCK_PXN | PTE_BLOCK_UXN;
>
> - debug("Configured memory map:\n");
> - debug(" 0x%016llx - 0x%016llx: Peripheral block\n",
> - mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
> -
> - /*
> -* Now add memory map entries for each DRAM bank, ensuring we don't
> -* overwrite the list terminator
> -*/
> - for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 &&
> gd->bd->bi_dram[i].size; i++) {
> - if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
> - log_warning("Too many DRAM banks!\n");
> - break;
> - }
> - mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
> - mem_map[i + 1].virt = mem_map[i + 1].phys;
> - mem_map[i + 1].size = gd->bd->bi_dram[i].size;
> - mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -PTE_BLOCK_INNER_SHARE;
> -
> - debug(" 0x%016llx - 0x%016llx: DDR bank %d\n",
> - mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i +
> 1].size, i);
> + for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 &&
> gd->bd->bi_dram[j].size; i++, j++) {
> + mem_map[i].phys = gd->bd->bi_dram[j].start;
> + mem_map[i].virt = mem_map[i].phys;
> + mem_map[i].size = gd->bd->bi_dram[j].size;
> + mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
> + PTE_BLOCK_INNER_SHARE;
> }
> +
> + mem_map[i].phys = UINT64_MAX;
> + mem_map[i].size = 0;
> +
> +#ifdef DEBUG
> + debug("Configured memory map:\n");
> + for (i = 0; mem_map[i].size; i++)
> + debug(" 0x%016llx - 0x%016llx: entry %d\n",
> + mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i);
> +#endif
> }
>
> u64 get_page_table_size(void)
> {
> return SZ_64K;
> }
>
> +static int fdt_cmp_res(const void *v1, const void *v2)
> +{
> + const struct fdt_resource *res1 = v1, *res2 = v2;
> +
> + return res1->start - res2->start;
> +}
> +
> +#define N_RESERVED_REGIONS 32
> +
> +/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access.
> + * On some platforms this is enough to trigger a security violation and trap
> + * to EL3.
> + */
> +static void carve_out_reserved_memory(void)
> +{
> + static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 };
> + int parent, rmem, count, i = 0;
> + phys_addr_t start;
> + size_t size;
> +
> + /* Some reserved nodes must be carved out, as the cache-prefetcher
> may otherwise
> +* attempt to access them, causing a security exception.
> +*/
> + parent =
Re: [PATCH v5 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration
On Mon, 26 Feb 2024 at 22:56, Caleb Connolly wrote:
>
> Some platforms hard reset when attempting to configure PMIC GPIOs. Add
> support for quirks specified in match data with a single quirk to skip
> this configuration. We rely on the GPIO already be configured correctly,
> which is always the case for volume up (the only current user of these
> GPIOs).
>
> This is not expected behaviour but appears to be due to a U-Boot
> specific bug. This quirk at least allows for the volume buttons to be
> used on platforms where this bug is apparent.
>
> Signed-off-by: Caleb Connolly
> ---
> drivers/gpio/qcom_pmic_gpio.c | 20 ++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>
Reviewed-by: Sumit Garg
-Sumit
> diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
> index 2a4fef8d28cb..63b512725ad9 100644
> --- a/drivers/gpio/qcom_pmic_gpio.c
> +++ b/drivers/gpio/qcom_pmic_gpio.c
> @@ -63,8 +63,19 @@
>
> #define REG_EN_CTL 0x46
> #define REG_EN_CTL_ENABLE (1 << 7)
>
> +/**
> + * pmic_gpio_match_data - platform specific configuration
> + *
> + * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to
> configure them.
> + * This is a workaround for an unknown bug on some platforms where trying to
> write the
> + * GPIO configuration registers causes the board to hang.
> + */
> +enum pmic_gpio_quirks {
> + QCOM_PMIC_QUIRK_READONLY = (1 << 0),
> +};
> +
> struct qcom_gpio_bank {
> uint32_t pid; /* Peripheral ID on SPMI bus */
> bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11)
> */
> };
> @@ -74,9 +85,14 @@ static int qcom_gpio_set_direction(struct udevice *dev,
> unsigned offset,
> {
> struct qcom_gpio_bank *priv = dev_get_priv(dev);
> uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
> uint32_t reg_ctl_val;
> - int ret;
> + ulong quirks = dev_get_driver_data(dev);
> + int ret = 0;
> +
> + /* Some PMICs don't like their GPIOs being configured */
> + if (quirks & QCOM_PMIC_QUIRK_READONLY)
> + return 0;
>
> /* Disable the GPIO */
> ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
> REG_EN_CTL_ENABLE, 0);
> @@ -303,9 +319,9 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
>
> static const struct udevice_id qcom_gpio_ids[] = {
> { .compatible = "qcom,pm8916-gpio" },
> { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
> - { .compatible = "qcom,pm8998-gpio" },
> + { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY
> },
> { .compatible = "qcom,pms405-gpio" },
> { }
> };
>
>
> --
> 2.43.1
>
Re: [PATCH v3 05/13] arm: mach-k3: invert logic for split DM firmware config
On 27/02/24 02:49, Bryan Brattlof wrote: Currently, for the K3 generation of SoCs, there are more SoCs that utilize the split firmware approach than the combined DMSC firmware. Invert the logic to avoid adding more and more SoCs to this list. Acked-by: Andrew Davis Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 03898424c9546..ffceb6428d42e 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -130,7 +130,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on CPU_V7R && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM Reviewed-by: Neha Malcom Francis -- Thanking You Neha Malcom Francis
Re: [PATCH v3 04/13] ram: k3-ddrss: enable the am62ax's DDR controller for am62px
On 27/02/24 02:49, Bryan Brattlof wrote: The am62px family of SoCs uses the same DDR controller as found on the am62ax family. Enable this option when building for the am62px family Signed-off-by: Bryan Brattlof --- drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 5b07e92030142..56391058567bb 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,7 +65,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 - default K3_AM62A_DDRSS if SOC_K3_AM62A7 + default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 config K3_J721E_DDRSS bool "Enable J721E DDRSS support" Reviewed-by: Neha Malcom Francis -- Thanking You Neha Malcom Francis
Re: [PATCH v3 03/13] arm: mach-k3: am62px: introduce clock and device files for wkup spl
Hi Bryan,
On 27/02/24 02:49, Bryan Brattlof wrote:
Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
Signed-off-by: Bryan Brattlof
---
arch/arm/mach-k3/r5/Makefile | 1 +
arch/arm/mach-k3/r5/am62px/Makefile| 6 +
arch/arm/mach-k3/r5/am62px/clk-data.c | 325 +
arch/arm/mach-k3/r5/am62px/dev-data.c | 71 +++
drivers/clk/ti/clk-k3.c| 6 +
drivers/power/domain/ti-power-domain.c | 6 +
include/k3-clk.h | 1 +
include/k3-dev.h | 1 +
8 files changed, 417 insertions(+)
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index b99199d337411..d1cd96d459bc4 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-y += lowlevel_init.o
obj-y += r5_mpu.o
diff --git a/arch/arm/mach-k3/r5/am62px/Makefile
b/arch/arm/mach-k3/r5/am62px/Makefile
new file mode 100644
index 0..50b0df20a3d1a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
Weirdly this gap before "GPL-2.0+" is there in all
arch/arm/mach-k3/r5/*/Makefile
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c
b/arch/arm/mach-k3/r5/am62px/clk-data.c
new file mode 100644
index 0..4b9892fe05167
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AM62PX specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof .
+ *
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ NULL,
+ NULL,
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ NULL,
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_hfosc0_clkout",
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+ "board_0_ospi0_dqs_out",
+ "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const main_usb1_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] =
{
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout1_clk",
+ "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const main_timerclkn_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "clk_32k_rc_sel_out0",
+ "postdiv4_16ff_main_0_hsdivout7_clk",
+ "gluelogic_rcosc_clkout",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ "hsdiv4_16fft_main_1_hsdivout3_clk",
+ "postdiv4_16ff_main_2_hsdivout6_clk",
+ NULL,
+
Re: [PATCH v3 01/13] soc: add info to identify the am62p SoC family
Hi Bryan, On 27/02/24 02:49, Bryan Brattlof wrote: Include the part number for TI's am62px family of SoCs so we can properly identify it during boot Reviewed-by: Igor Opaniuk Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/include/mach/hardware.h | 2 ++ drivers/soc/soc_ti_k3.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index a1a9dfbde66c8..040288150b12f 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -46,6 +46,7 @@ #define JTAG_ID_PARTNO_J721S2 0xbb75 #define JTAG_ID_PARTNO_AM62X 0xbb7e #define JTAG_ID_PARTNO_AM62AX 0xbb8d +#define JTAG_ID_PARTNO_AM62PX 0xbb9d #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ @@ -61,6 +62,7 @@ K3_SOC_ID(am64x, AM64X) K3_SOC_ID(j721s2, J721S2) K3_SOC_ID(am62x, AM62X) K3_SOC_ID(am62ax, AM62AX) +K3_SOC_ID(am62px, AM62PX) #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 355a5368dd45a..d7d0152b115fa 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -45,6 +45,9 @@ static const char *get_family_string(u32 idreg) case JTAG_ID_PARTNO_AM62AX: family = "AM62AX"; break; + case JTAG_ID_PARTNO_AM62PX: + family = "AM62PX"; + break; default: family = "Unknown Silicon"; }; Reviewed-by: Neha Malcom Francis -- Thanking You Neha Malcom Francis
Re: [PATCH 01/10] mach-snapdragon: Add support for IPQ9574
Hi,
As Ilias said, please describe what this patch does and why, especially
things which are different to existing boards.
For the next revision, please split this patch up into something like
the following:
* clock driver
* pinctrl driver
* changes to mach-snapdragon
* board code / defconfig
* dt-bindings (which should be imported from Linux and mention the tag
they're taken from in the commit message)
* devicetree (also imported from Linux)
* U-Boot specific devicetree additions
This makes it much easier to review and generally individual components
and leaves us with a nicer git history at the end too.
Qualcomm platforms in U-Boot are switching over to using upstream
devicetree (from Linux), in the next revision you should also adopt
this. Both the SoC dtsi file and the board dts should be cut/paste from
Linux with no modifications. Any U-Boot specific additions must go in a
"ipq9574-rdp433-mht-phy-u-boot.dtsi" file, the build system will
automatically include it. If there are additional DT features that
aren't yet merged in upstream, those should be added in a separate
patch, ideally linking to an upstream patch series. This is part of a
wider effort to adopt upstream DT in U-Boot.
I've left some further comments and questions in-line below.
On 26/02/2024 10:07, Varadarajan Narayanan wrote:
> Signed-off-by: Varadarajan Narayanan
> ---
>
> arch/arm/dts/Makefile |2 +
> arch/arm/dts/ipq9574-default.dts | 167 +++
> arch/arm/dts/ipq9574-rdp433-mht-phy.dts | 208 +++
> arch/arm/dts/ipq9574.dtsi | 771 ++
> .../include/mach/sysmap-ipq9574.h | 252
> arch/arm/mach-snapdragon/init_ipq9574.c | 81 +
> board/qualcomm/ipq9574/Kconfig| 15 +
> board/qualcomm/ipq9574/Makefile |4 +
> board/qualcomm/ipq9574/board_init.c | 326
> board/qualcomm/ipq9574/ipq9574.c | 170 +++
> board/qualcomm/ipq9574/ipq9574.h | 75 +
> board/qualcomm/ipq9574/u-boot-x32.lds | 250
> board/qualcomm/ipq9574/u-boot-x64.lds | 188 +++
> drivers/clk/qcom/clock-ipq9574.c | 1320 +
> drivers/pinctrl/qcom/pinctrl-ipq9574.c| 77 +
> include/configs/ipq9574.h | 111 ++
> include/dt-bindings/clock/gcc-ipq9574.h | 156 ++
> include/dt-bindings/net/qti-ipqsoc.h | 20 +
> include/dt-bindings/pinctrl/pinctrl-ipqsoc.h | 19 +
> include/dt-bindings/reset/ipq9574-reset.h | 54 +
> 20 files changed, 4266 insertions(+)
> create mode 100644 arch/arm/dts/ipq9574-default.dts
> create mode 100644 arch/arm/dts/ipq9574-rdp433-mht-phy.dts
> create mode 100644 arch/arm/dts/ipq9574.dtsi
> create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-ipq9574.h
> create mode 100644 arch/arm/mach-snapdragon/init_ipq9574.c
> create mode 100644 board/qualcomm/ipq9574/Kconfig
> create mode 100644 board/qualcomm/ipq9574/Makefile
> create mode 100644 board/qualcomm/ipq9574/board_init.c
> create mode 100644 board/qualcomm/ipq9574/ipq9574.c
> create mode 100644 board/qualcomm/ipq9574/ipq9574.h
> create mode 100644 board/qualcomm/ipq9574/u-boot-x32.lds
> create mode 100644 board/qualcomm/ipq9574/u-boot-x64.lds
> create mode 100644 drivers/clk/qcom/clock-ipq9574.c
> create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
> create mode 100644 include/configs/ipq9574.h
> create mode 100644 include/dt-bindings/clock/gcc-ipq9574.h
> create mode 100644 include/dt-bindings/net/qti-ipqsoc.h
> create mode 100644 include/dt-bindings/pinctrl/pinctrl-ipqsoc.h
> create mode 100644 include/dt-bindings/reset/ipq9574-reset.h
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index d9725030d5..8931dfa2aa 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -1523,6 +1523,8 @@ dtb-$(CONFIG_ARCH_QEMU) += qemu-arm.dtb qemu-arm64.dtb
> dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \
> corstone1000-fvp.dtb
>
> +dtb-$(CONFIG_TARGET_IPQ9574) += ipq9574-rdp433-mht-phy.dtb
> +
> include $(srctree)/scripts/Makefile.dts
>
> targets += $(dtb-y)
> diff --git a/arch/arm/dts/ipq9574-default.dts
> b/arch/arm/dts/ipq9574-default.dts
> new file mode 100644
> index 00..501c9492df
> --- /dev/null
> +++ b/arch/arm/dts/ipq9574-default.dts
> @@ -0,0 +1,167 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq9574.dtsi"
> +
> +/ {
> + config_name = "config-default";
> +
> + aliases {
> + console = _uart2_console;
> + uart2 = _uart3_additional;
> + sdhci =
> + };
> +
> + soc: soc {
> + tlmm: pinctrl@100 {
> +
> + sdhci_pinmux: mmc {
> + pinconfig;
> +
Re: [PATCH 10/10] board: qualcomm: Add support for IPQ9574 RDP433
On 26/02/2024 10:08, Varadarajan Narayanan wrote: > Provide the defconfig and include IPQ9574/RDP433 into the build > framework. Please squash this into a common patch along with the other board code in your next revision. > > Signed-off-by: Varadarajan Narayanan > --- > > arch/arm/mach-snapdragon/Kconfig | 15 > arch/arm/mach-snapdragon/Makefile | 1 + > configs/ipq9574_mmc_defconfig | 118 ++ > 3 files changed, 134 insertions(+) > create mode 100644 configs/ipq9574_mmc_defconfig > > diff --git a/arch/arm/mach-snapdragon/Kconfig > b/arch/arm/mach-snapdragon/Kconfig > index ad66710819..a4552028c1 100644 > --- a/arch/arm/mach-snapdragon/Kconfig > +++ b/arch/arm/mach-snapdragon/Kconfig > @@ -90,6 +90,20 @@ config TARGET_QCS404EVB > - 1GiB RAM > - 8GiB eMMC, uSD slot > > +config TARGET_IPQ9574 > + bool "QTI IPQ9574 SOC" > + select OF_BOARD_SETUP > + select CLK_QCOM_IPQ9574 > + select PINCTRL_QCOM_IPQ9574 > + help > + Support for IPQ95xx SoC. > + - Board Open Platform Specifications. > + - Quad Cores A73, max@2.2G, L1@32KB L2@512KB > + - DDR3L/DDR4 > + - QSPI NAND / NOR / eMMC > + - USB 3.0/I2C/UART/PCIe Gen3 2Lane > + - 1G/2.5G/10G Ethernet Ports > + > endchoice > > source "board/qualcomm/dragonboard410c/Kconfig" > @@ -97,5 +111,6 @@ source "board/qualcomm/dragonboard820c/Kconfig" > source "board/qualcomm/dragonboard845c/Kconfig" > source "board/samsung/starqltechn/Kconfig" > source "board/qualcomm/qcs404-evb/Kconfig" > +source "board/qualcomm/ipq9574/Kconfig" > > endif > diff --git a/arch/arm/mach-snapdragon/Makefile > b/arch/arm/mach-snapdragon/Makefile > index 3a3a297c17..a9af8d9ee0 100644 > --- a/arch/arm/mach-snapdragon/Makefile > +++ b/arch/arm/mach-snapdragon/Makefile > @@ -4,6 +4,7 @@ > > obj-$(CONFIG_SDM845) += sysmap-sdm845.o > obj-$(CONFIG_SDM845) += init_sdm845.o > +obj-$(CONFIG_TARGET_IPQ9574) += init_ipq9574.o > obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o > obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o > obj-y += misc.o > diff --git a/configs/ipq9574_mmc_defconfig b/configs/ipq9574_mmc_defconfig > new file mode 100644 > index 00..0001bd8eae > --- /dev/null > +++ b/configs/ipq9574_mmc_defconfig > @@ -0,0 +1,118 @@ > +CONFIG_ARM=y > +CONFIG_ARCH_SNAPDRAGON=y > +CONFIG_ARCH_64BIT_SUPPORT=y > +# CONFIG_ARM64_SUPPORT_AARCH32 is not set > +CONFIG_ARM_SMCCC=y > +CONFIG_HAS_VBAR=y > +CONFIG_SKIP_LOWLEVEL_INIT=y > +CONFIG_COUNTER_FREQUENCY=2400 > +CONFIG_IPQ9574=y > +CONFIG_TARGET_IPQ9574=y > +CONFIG_SYS_MALLOC_F_LEN=0x1000 > +CONFIG_SYS_MALLOC_F=y > +CONFIG_SYS_LOAD_ADDR=0x5000 > +CONFIG_TEXT_BASE=0x4A24 > +CONFIG_SMEM_BASE_ADDR=0x4AA0 > +CONFIG_NR_DRAM_BANKS=1 > +CONFIG_SMEM=y > +CONFIG_SYS_MALLOC_LEN=0x18 > +CONFIG_DM_SERIAL=y > +CONFIG_DEFAULT_DEVICE_TREE="ipq9574-rdp433-mht-phy" > +CONFIG_LOCALVERSION="" > +CONFIG_LOCALVERSION_AUTO=y > +CONFIG_CC_OPTIMIZE_FOR_SIZE=y > +CONFIG_EXPERT=y > +CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y > +CONFIG_FIT=y > +CONFIG_FIT_VERBOSE=y > +CONFIG_OF_LIBFDT=y > +CONFIG_OF_LIBFDT_OVERLAY=y > +# CONFIG_BOOTSTD_BOOTCOMMAND is not set > +# CONFIG_PSCI_RESET is not set > +CONFIG_FIRMWARE=y > +CONFIG_DM=y > +CONFIG_OF_CONTROL=y > +CONFIG_FIT_SIGNATURE=n > +CONFIG_TOOLS_LIBCRYPTO=y > +CONFIG_TOOLS_FIT_RSASSA_PSS=n > +CONFIG_TOOLS_FIT_SIGNATURE=n > +CONFIG_TOOLS_SHA1=n > +CONFIG_TOOLS_SHA256=n > +CONFIG_TOOLS_SHA384=n > +CONFIG_TOOLS_SHA512=n > +CONFIG_SYS_EXTRA_OPTIONS="" > +CONFIG_SYS_PROMPT="IPQ9574# " > +# CONFIG_USE_PREBOOT is not set > +CONFIG_BOOTDELAY=5 > +CONFIG_USE_BOOTARGS=y > +CONFIG_USE_BOOTCOMMAND=y > +CONFIG_BOOTCOMMAND="" > +CONFIG_BOOTARGS="console=ttyMSM0,115200n8" > +# CONFIG_BOOTSTD is not set > +CONFIG_HUSH_PARSER=y > +CONFIG_SYS_MAXARGS=64 > +CONFIG_OF_BOARD_FIXUP=y > +CONFIG_STACKPROTECTOR=y > +CONFIG_MSM_SMEM=y > +CONFIG_SYS_CUSTOM_LDSCRIPT=y > +CONFIG_SYS_LDSCRIPT="board/qualcomm/ipq9574/u-boot-x64.lds" > +CONFIG_OF_LIST="ipq9574-rdp433-mht-phy" > +CONFIG_DTB_RESELECT=y > +CONFIG_MULTI_DTB_FIT=y > +CONFIG_MULTI_DTB_FIT_LZO=y > +CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y > +CONFIG_MULTI_DTB_FIT_USER_DEF_ADDR=0x4A40 > +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x10 > +# CONFIG_CMD_BOOTI is not set > +CONFIG_ENV_OVERWRITE=y > +CONFIG_CLK=y > +CONFIG_CLK_QCOM=y > +CONFIG_CLK_IPQ9574=y > +# CONFIG_OF_EMBED is not set > +CONFIG_PINCTRL=y > +CONFIG_PINCTRL_QCOM=y > +CONFIG_PINCTRL_QCOM_IPQ9574=y > +CONFIG_IPQ_MMC=y > +CONFIG_MMC_SDHCI=y > +CONFIG_GPIO=y > +# CONFIG_CONFIG_GPIO_EXTRA_HEADER is not set > +CONFIG_DM_GPIO=y > +CONFIG_MMC_SDHCI_MSM=y > +# CONFIG_EFI_LOADER is not set > +# CONFIG_MMC_HS200_SUPPORT is not set > +CONFIG_EFI_PARTITION=y > +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 > +CONFIG_MSM_GPIO=y > +CONFIG_PINCONF=y > +# CONFIG_CMD_GPIO is not set > +CONFIG_MSM_SERIAL=y > +CONFIG_STACK_SIZE=0x8 > +CONFIG_SYS_BOOTM_LEN=0x400 > +CONFIG_DM_RESET=y >
Re: [PATCH 09/10] mmc: msm_sdhci: Reset clocks before reconfiguration
On 26/02/2024 10:08, Varadarajan Narayanan wrote:
> U-Boot has to reconfigure the clocks that were set in the boot
> loaders. However, in IPQ9574, the clocks have to be reset before
> they can be reconfigured. Hence add code to do the relevant
> resets.
>
> Signed-off-by: Varadarajan Narayanan
With below feedback addressed, please add
Reviewed-by: Caleb Connolly
> ---
>
> drivers/mmc/msm_sdhci.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
> index 9285d412fe..2e9d521159 100644
> --- a/drivers/mmc/msm_sdhci.c
> +++ b/drivers/mmc/msm_sdhci.c
> @@ -16,6 +16,7 @@
> #include
> #include
> #include
> +#include
>
> /* Non-standard registers needed for SDHCI startup */
> #define SDCC_MCI_POWER 0x0
> @@ -122,10 +123,19 @@ static int msm_sdc_probe(struct udevice *dev)
> struct msm_sdhc *prv = dev_get_priv(dev);
> const struct msm_sdhc_variant_info *var_info;
> struct sdhci_host *host = >host;
> + struct reset_ctl bcr_rst;
> u32 core_version, core_minor, core_major;
> u32 caps;
> int ret;
>
> + ret = reset_get_by_name(dev, "bcr_rst", _rst);
reset-names is not not valid according to the DT bindings, please use
reset_get_by_index() instead.
> + if (!ret) {
> + reset_assert(_rst);
> + mdelay(10);
Is 10ms really necessary here? The equivalent code in Linux suggests
that only 125us are needed (with a 32.7KHz sleep clock) and uses 200us
to be "on the safe side". So maybe udelay(200) here instead?
> + reset_deassert(_rst);
> + mdelay(10);
> + }
> +
> host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
>
> host->max_clk = 0;
--
// Caleb (they/them)
Re: [PATCH 08/10] mmc: msm_sdhci: Handle different vendor cap register offsets
On 26/02/2024 10:08, Varadarajan Narayanan wrote:
> In the IPQ9574, the vendor capabilities register is at a
> different offset than in other SoCs. Hence add a vendor_cap
> field to msm_sdhc_variant_info structure to get the correct
> register offset.
>
> Signed-off-by: Varadarajan Narayanan
With below feedback addressed, please add
Reviewed-by: Caleb Connolly
> ---
>
> drivers/mmc/msm_sdhci.c | 11 ++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
> index fe1e754bfd..9285d412fe 100644
> --- a/drivers/mmc/msm_sdhci.c
> +++ b/drivers/mmc/msm_sdhci.c
> @@ -48,6 +48,7 @@ struct msm_sdhc {
>
> struct msm_sdhc_variant_info {
> bool mci_removed;
> + u32 vendor_cap;/* Non standard (?) SDHCI register */
> };
>
> DECLARE_GLOBAL_DATA_PTR;
> @@ -158,7 +159,7 @@ static int msm_sdc_probe(struct udevice *dev)
> if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
> caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
> caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
> - writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
> + writel(caps, host->ioaddr + var_info->vendor_cap);
> }
>
> ret = mmc_of_parse(dev, >cfg);
> @@ -219,15 +220,23 @@ static int msm_sdc_bind(struct udevice *dev)
>
> static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
> .mci_removed = false,
> + .vendor_cap = SDHCI_VENDOR_SPEC_CAPABILITIES0,
> };
>
> static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
> .mci_removed = true,
> + .vendor_cap = SDHCI_VENDOR_SPEC_CAPABILITIES0,
This is wrong, it should be 0x21c for all v5 controllers (see
drivers/mmc/host/sdhci-msm.c in Linux).
> +};
> +
> +static const struct msm_sdhc_variant_info msm_sdhc_v5_ipq_var = {
So this can be dropped
> + .mci_removed = true,
> + .vendor_cap = 0x21c,
> };
>
> static const struct udevice_id msm_mmc_ids[] = {
> { .compatible = "qcom,sdhci-msm-v4", .data = (ulong)_sdhc_mci_var },
> { .compatible = "qcom,sdhci-msm-v5", .data = (ulong)_sdhc_v5_var },
> + { .compatible = "qti,sdhci-msm-v5", .data = (ulong)_sdhc_v5_ipq_var
> },
This can be dropped too.
For future reference as I really don't want to deal with these, please
never submit a patch using or otherwise referencing a compatible string
starting with "qti,". There is never a reason such a compatible should
appear in upstream code or DT.
> { }
> };
>
--
// Caleb (they/them)
Re: [PATCH 07/10] pinctrl: qcom: Include IPQ9574
On 26/02/2024 10:08, Varadarajan Narayanan wrote: > Add support for IPQ9574 under pinctrl/qcom. Likewise, squash this into a patch introducing the whole pinctrl driver. There isn't much to review here while all the actual code is in one huge patch. > > Signed-off-by: Varadarajan Narayanan > --- > > drivers/pinctrl/qcom/Kconfig | 7 +++ > drivers/pinctrl/qcom/Makefile | 1 + > 2 files changed, 8 insertions(+) > > diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig > index 2fe6398147..558a4d9bbd 100644 > --- a/drivers/pinctrl/qcom/Kconfig > +++ b/drivers/pinctrl/qcom/Kconfig > @@ -27,6 +27,13 @@ config PINCTRL_QCOM_IPQ4019 > Say Y here to enable support for pinctrl on the IPQ4019 SoC, > as well as the associated GPIO driver. > > +config PINCTRL_QCOM_IPQ9574 > + bool "Qualcomm IPQ9574 GCC" > + select PINCTRL_QCOM > + help > + Say Y here to enable support for pinctrl on the IPQ9574 SoC, > + as well as the associated GPIO driver. > + > config PINCTRL_QCOM_QCS404 > bool "Qualcomm QCS404 GCC" > select PINCTRL_QCOM > diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile > index 6d9aca6d7b..90e85510fa 100644 > --- a/drivers/pinctrl/qcom/Makefile > +++ b/drivers/pinctrl/qcom/Makefile > @@ -5,6 +5,7 @@ > obj-$(CONFIG_PINCTRL_QCOM) += pinctrl-qcom.o > obj-$(CONFIG_PINCTRL_QCOM_APQ8016) += pinctrl-apq8016.o > obj-$(CONFIG_PINCTRL_QCOM_IPQ4019) += pinctrl-ipq4019.o > +obj-$(CONFIG_PINCTRL_QCOM_IPQ9574) += pinctrl-ipq9574.o > obj-$(CONFIG_PINCTRL_QCOM_APQ8096) += pinctrl-apq8096.o > obj-$(CONFIG_PINCTRL_QCOM_QCS404) += pinctrl-qcs404.o > obj-$(CONFIG_PINCTRL_QCOM_SDM845) += pinctrl-sdm845.o -- // Caleb (they/them)
Re: [PATCH 06/10] pinctrl: qcom: Add support for 'pull-down'
On 26/02/2024 10:08, Varadarajan Narayanan wrote:
> Add support for 'pull-down' needed for IPQ9574.
'bias-pull-down'
>
> Signed-off-by: Varadarajan Narayanan
Reviewed-by: Caleb Connolly
> ---
>
> drivers/pinctrl/qcom/pinctrl-qcom.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c
> b/drivers/pinctrl/qcom/pinctrl-qcom.c
> index dc3d8c4d90..ba53b6f290 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qcom.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c
> @@ -37,6 +37,7 @@ static const struct pinconf_param msm_conf_params[] = {
> { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 2 },
> { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
> { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 3 },
> + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
> };
>
> static int msm_get_functions_count(struct udevice *dev)
> @@ -104,6 +105,7 @@ static int msm_pinconf_set(struct udevice *dev, unsigned
> int pin_selector,
> clrbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector),
>TLMM_GPIO_PULL_MASK);
> break;
> + case PIN_CONFIG_BIAS_PULL_DOWN:
> case PIN_CONFIG_BIAS_PULL_UP:
> clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv,
> pin_selector),
> TLMM_GPIO_PULL_MASK, argument);
--
// Caleb (they/them)
Re: [PATCH 04/10] clk/qcom: Include IPQ9574
On 26/02/2024 10:08, Varadarajan Narayanan wrote: > Include the IPQ9574 clock driver into build framework Please squash this patch into your patch adding the clock driver on the next revision. > > Signed-off-by: Varadarajan Narayanan > --- > > drivers/clk/qcom/Kconfig | 8 > drivers/clk/qcom/Makefile | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 0df0d1881a..73947e1659 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -47,6 +47,14 @@ config CLK_QCOM_SDM845 > on the Snapdragon 845 SoC. This driver supports the clocks > and resets exposed by the GCC hardware block. > > +config CLK_QCOM_IPQ9574 > + select CLK_QCOM > + bool "Clock controller driver for QTI IPQ9574" > + help > + Say Y here to enable support for the Global Clock Controller > + on the IPQ9574 SoC. This driver supports the clocks > + and resets exposed by the GCC hardware block. > + > endmenu > > endif > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index cb179fdac5..c68abeea9c 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_QCOM_APQ8016) += clock-apq8016.o > obj-$(CONFIG_CLK_QCOM_APQ8096) += clock-apq8096.o > obj-$(CONFIG_CLK_QCOM_IPQ4019) += clock-ipq4019.o > obj-$(CONFIG_CLK_QCOM_QCS404) += clock-qcs404.o > +obj-$(CONFIG_CLK_QCOM_IPQ9574) += clock-ipq9574.o -- // Caleb (they/them)
Re: [PATCH 03/10] clk/qcom: Add support for clock registers in IPQ9574
On 26/02/2024 10:08, Varadarajan Narayanan wrote:
> The BCR registers in IPQ9574 are different and have
> different fields. Add function to program these
> clocks accordingly.
>
> Signed-off-by: Varadarajan Narayanan
> ---
>
> drivers/clk/qcom/clock-qcom.c | 32
> drivers/clk/qcom/clock-qcom.h | 8
> 2 files changed, 40 insertions(+)
>
> diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
> index 7c683e5192..fe60490186 100644
> --- a/drivers/clk/qcom/clock-qcom.c
> +++ b/drivers/clk/qcom/clock-qcom.c
> @@ -156,6 +156,38 @@ void clk_rcg_set_rate(phys_addr_t base, const struct
> bcr_regs *regs, int div,
> clk_bcr_update(base + regs->cmd_rcgr);
> }
>
> +#define CFG_MASK 0x3FFF
Please define this in terms of the individual register fields.
> +
> +#define CFG_DIVIDER_MASK 0x1F
This is just CFG_SRC_DIV_MASK, please use that instead.
> +
> +/* root set rate for clocks without the MND divider */
Please adjust this comment to explain what's different about v2 and
where it's relevant (is it just IPQ SoCs? Or "some IPQ SoCs"?).
> +void clk_rcg_set_rate_v2(phys_addr_t base, const struct bcr_regs_v2 *regs,
> + int div, int cdiv, int source)
As far as I can tell, this is like the RCG clocks in that the cfg
register is always cmd + 4 and div_cdivr is always cfg + 4.
In this case let's simplify this and save a whole lot of lines by just
passing in the cmd register address and using offsets for the others.
There's no need to specify all these manually. See
https://lore.kernel.org/u-boot/20240131-b4-qcom-livetree-v1-4-4071c0787...@linaro.org/
> +{
> + u32 cfg;
> +
> + /* setup src select and divider */
> + cfg = readl(base + regs->cfg_rcgr);
> + cfg &= ~CFG_MASK;
> + cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */
> +
> + /*
> + * Set the divider; HW permits fraction dividers (+0.5), but
> + * for simplicity, we will support integers only
> + */
> + if (div)
> + cfg |= div & CFG_DIVIDER_MASK;
> +
> + writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */
> +
> + /* Write the common divider clock configuration */
> + if (regs->div_cdivr)
> + writel(cdiv, base + regs->div_cdivr);
> +
> + /* Inform h/w to start using the new config. */
> + clk_bcr_update(base + regs->cmd_rcgr);
> +}
> +
> const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
> {
> if (!f)
> diff --git a/drivers/clk/qcom/clock-qcom.h b/drivers/clk/qcom/clock-qcom.h
> index 01088c1901..95f6162ea4 100644
> --- a/drivers/clk/qcom/clock-qcom.h
> +++ b/drivers/clk/qcom/clock-qcom.h
> @@ -32,6 +32,12 @@ struct bcr_regs {
> uintptr_t D;
> };
>
> +struct bcr_regs_v2 {
> + uintptr_t cfg_rcgr;
> + uintptr_t cmd_rcgr;
> + uintptr_t div_cdivr;
> +};> +
> struct freq_tbl {
> uint freq;
> uint src;
> @@ -86,6 +92,8 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct
> bcr_regs *regs,
> int div, int m, int n, int source, u8 mnd_width);
> void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div,
> int source);
> +void clk_rcg_set_rate_v2(phys_addr_t base, const struct bcr_regs_v2 *regs,
> + int div, int cdiv, int source);
>
> static inline void qcom_gate_clk_en(const struct msm_clk_priv *priv,
> unsigned long id)
> {
--
// Caleb (they/them)
Re: [PATCH 00/10] Add initial support for IPQ9574 based boards
HI Varada, On 26/02/2024 10:07, Varadarajan Narayanan wrote: > These patches introduce the initial support code needed > for the QTI IPQ9574 SoC and RDP433 board. Awesome! > > SoC : QTI IPQ9574 > RAM : 2GB DDR4 > Flash : eMMC 8GB > WiFi: 1 x 2.4GHz, 1 x 5GHz, 1 x 6GHz > > New to both patman and posting to U-Boot. Please let > me know if something is not correct, will try to > rectify to the best of my abilities. Patches came through just fine, thanks! I haven't used patman personally, but I have used the b4 tool, I'd recommend giving it a spin if you haven't yet. Your get_maintainers.pl options might need some tweaking too (the defaults from b4 seem to work better ime). I've spent some time going through your series and there's a lot to go over, so apologies if this gets a bit long. I'm planning to pick up this[1] patch series this week and I'm sorry to say it has some fairly major conflicts with your work here. My series makes some fairly significant changes to Qualcomm support in U-Boot (moving to upstream Linux DT and getting rid of most of the compile time board configuration among other things). The thing I'm mostly concerned with is the totally custom init code and linker script. I discovered this branch[2] which seems to have a fairly complete git history, but there's still a lot of unknowns. * What is the custom linker script for (which isn't handled by the default one)? * Why do you skip U-Boot relocation (GD_FLG_SKIP_RELOC)? * How is U-Boot expected to be flashed and consequently loaded on this platform? I get the impression that SBL1 jumps to it directly? Is it built into an XBL image like on the mobile/IoT platforms, or flashed to it's own partition, or to SPI flash? In general there is very little context around the code being added here, and as a result it's hard to understand what exactly is going on and why things have been done a certain way. I'll leave some more detailed comments in line, but I think initially I would just like to get a better understanding of the situation here, so answers to the questions above would be most helpful! Please also have a look at reworking this series on top of my patches linked at [1], if you have any issues or questions then please do get in touch with me via email, or better via the #u-boot IRC channel on OFTC, my nick there is calebccff. Regarding my series, the notable changes are in how mach-snapdragon is handled: the target specific memory maps have been dropped in favour of reading the memory map from DT. The sysmap headers are also gone, instead the defines are moved to the relevant driver (mostly clock/pinctrl). I think it would be sensible to (for example) introduce mach-snapdragon/smem.c for handling stuff like your env_get_location() implementation (it would provide smem_env_get_location() which would be called from env_get_location() in board.c). You'll probably also want to skip the carve_out_reserved_memory() call for now. [1]: https://lore.kernel.org/u-boot/20240226-b4-qcom-common-target-v5-0-10c8e078b...@linaro.org/ [2]: https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot/-/tree/NHSS.QSDK.12.4.5 > > Thanks > Varada Kind regards, > > > Varadarajan Narayanan (10): > mach-snapdragon: Add support for IPQ9574 > mach-snapdragon: ipq9574: Add SMEM defines needed for IPQ9574 > clk/qcom: Add support for clock registers in IPQ9574 > clk/qcom: Include IPQ9574 > mach-snapdragon: Update gd->ram_size in msm_fixup_memory > pinctrl: qcom: Add support for 'pull-down' > pinctrl: qcom: Include IPQ9574 > mmc: msm_sdhci: Handle different vendor cap register offsets > mmc: msm_sdhci: Reset clocks before reconfiguration > board: qualcomm: Add support for IPQ9574 RDP433 > > arch/arm/dts/Makefile |2 + > arch/arm/dts/ipq9574-default.dts | 167 +++ > arch/arm/dts/ipq9574-rdp433-mht-phy.dts | 208 +++ > arch/arm/dts/ipq9574.dtsi | 771 ++ > arch/arm/mach-snapdragon/Kconfig | 15 + > arch/arm/mach-snapdragon/Makefile |1 + > arch/arm/mach-snapdragon/dram.c | 10 +- > .../include/mach/sysmap-ipq9574.h | 252 > arch/arm/mach-snapdragon/init_ipq9574.c | 81 + > board/qualcomm/ipq9574/Kconfig| 15 + > board/qualcomm/ipq9574/Makefile |4 + > board/qualcomm/ipq9574/board_init.c | 326 > board/qualcomm/ipq9574/ipq9574.c | 170 +++ > board/qualcomm/ipq9574/ipq9574.h | 75 + > board/qualcomm/ipq9574/u-boot-x32.lds | 250 > board/qualcomm/ipq9574/u-boot-x64.lds | 188 +++ > configs/ipq9574_mmc_defconfig | 118 ++ > drivers/clk/qcom/Kconfig |8 + > drivers/cl
[ANN] U-Boot v2024.04-rc3 released
Hey all, It's late in the day, but still release day and so here's -rc3. I've also pushed this to the next branch and that is now open. In terms of a changelog, git log --merges v2024.04-rc2..v2024.04-rc3 contains what I've pulled but as always, better PR messages and tags will provide better results here. I hope to get back on schedule and that means the rest of the rcs every other Monday, and with final release on Tuesday, April 2nd, 2024. Thanks all! -- Tom signature.asc Description: PGP signature
Re: [PATCH 4/6] usb: kbd: Ignore Yubikeys
On 2/26/24 9:47 PM, Mark Kettenis wrote:
Date: Sun, 25 Feb 2024 22:57:23 +0100
From: Marek Vasut
On 2/25/24 5:07 PM, Janne Grunau wrote:
Hej,
On Wed, Feb 21, 2024, at 13:41, Marek Vasut wrote:
On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
From: Hector Martin
We currently only support one USB keyboard device, but some devices
emulate keyboards for other purposes. Most commonly, people run into
this with Yubikeys, so let's ignore those.
Even if we end up supporting multiple keyboards in the future, it's
safer to ignore known non-keyboard devices.
Signed-off-by: Hector Martin
---
common/usb_kbd.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/common/usb_kbd.c b/common/usb_kbd.c
index 4cbc9acb73..774d3555d9 100644
--- a/common/usb_kbd.c
+++ b/common/usb_kbd.c
@@ -120,6 +120,15 @@ struct usb_kbd_pdata {
extern int __maybe_unused net_busy_flag;
+/*
+ * Since we only support one usbkbd device in the iomux,
+ * ignore common keyboard-emulating devices that aren't
+ * real keyboards.
+ */
+const uint16_t vid_blocklist[] = {
+ 0x1050, /* Yubico */
+};
+
/* The period of time between two calls of usb_kbd_testc(). */
static unsigned long kbd_testc_tms;
@@ -465,6 +474,7 @@ static int usb_kbd_probe_dev(struct usb_device *dev, unsigned int ifnum)
struct usb_endpoint_descriptor *ep;
struct usb_kbd_pdata *data;
int epNum;
+ int i;
if (dev->descriptor.bNumConfigurations != 1)
return 0;
@@ -480,6 +490,15 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
unsigned int ifnum)
if (iface->desc.bInterfaceProtocol != USB_PROT_HID_KEYBOARD)
return 0;
+ for (i = 0; i < ARRAY_SIZE(vid_blocklist); i++) {
+ if (dev->descriptor.idVendor == vid_blocklist[i]) {
+ printf("Ignoring keyboard device 0x%x:0x%x\n",
+ dev->descriptor.idVendor,
+ dev->descriptor.idProduct);
+ return 0;
+ }
+ }
I vaguely recall a discussion about previous version of this, I think
the suggestion was to make the list of ignored devices configurable via
environment variable, so users can add to that list from U-Boot shell.
Would it be possible to make it work this way ?
oh, I completely forgot that this patch was already submitted. I briefly looked
through asahi tree for related patches and did not check whether this was
previously submitted.
I've added environment based blocking as separate patch with blocking either
complete vendor IDs or vendor, product ID combinations. A separate patch to
simplify authorship tracking and the implementation doesn't share any code.
It would be better to have only one patch which does not hard-code any
USB IDs, and then add those blocked IDs via U-Boot default environment
for this specific machine. We cannot predict what yubico will do in the
future, whether they might make a device that shouldn't be blocked for
example. If they do, the user should be able to unblock their device by
running e.g. '=> setenv usb_blocklist' instead of updating their bootloader.
I think a simple list of blocked VID:PID pairs, maybe with wildcards,
would be nice, i.e. something like 'usb_blocklist=1234:5678,1050:*' to
block device 0x1234:0x5678 and all devices with VID 0x1050 . That should
be easy to parse with strtok()/strtol() or some such and the code should
not be too complex.
I do like the idea of having a configurable list of usb devices to
ignore. The U-Boot USB stack is still not perfect
Very far from perfect, yes.
and there are still
USB devices that will prevent us from booting when connected. The
list will provide a nice workaround for that issue.
But the yubikeys will cause the same problem on other boards as well.
So I think it makes sense to put those in a default list.
I agree.
Re: [PATCH RESEND] serial: pl01x: set baudrate when probing
On 2/26/2024 4:23 PM, Dan Carpenter wrote:
> On Sun, Feb 25, 2024 at 08:38:33AM +0800, Yang Xiwen via B4 Relay wrote:
>> #if CONFIG_IS_ENABLED(OF_PLATDATA)
>> struct dtd_serial_pl01x *dtplat = >dtplat;
>> @@ -301,10 +302,14 @@ int pl01x_serial_probe(struct udevice *dev)
>> #endif
>> priv->type = plat->type;
>>
>> -if (!plat->skip_init)
>> -return pl01x_generic_serial_init(priv->regs, priv->type);
>> -else
>> +if (!plat->skip_init) {
>> +ret = pl01x_generic_serial_init(priv->regs, priv->type);
>> +if (!ret)
>
> This if statement seems to be reversed.
Seems correct. Maybe i sent the wrong version.
>
> regards,
> dan carpenter
>
>> +return ret;
>> +return pl01x_serial_setbrg(dev, gd->baudrate);
>> +} else {
>> return 0;
>> +}
>> }
>
--
Best regards,
Yang Xiwen
[PATCH 4/4] rockchip: Migrate to use DM_USB_GADGET on RK3328
USB gadget is not working fully as expected on RK3328, it uses a
board_usb_init() function to initialize the DWC2 OTG port.
The board_usb_init() function does not intgrate with the generic phy
framework and as a result the USB phy is not properly configured before
or after USB gadget use.
Having both USB_DWC2 and DWC2_OTG enabled for the same board is also
causing some issues.
Trying to use rockusb or ums command after usb stop result in a freeze
due to usb stop is putting the phy in a suspended state.
=> usb start
=> usb stop
=> ums 0 mmc 0
--> freeze due to usb phy is suspended <--
Fix this by only using one of USB_DWC2 (host) or DWC2_OTG (peripheral)
depending on the most likely usage of the otg port.
The nanopi-r2 and orangepi-r1-plus variants share OTG and power using a
Type-C connector, mark these boards dr_mode as peripheral, the most
likely usage is for recovery and image download.
The rock64 and roc-cc currently use dr_mode as host, remove the DWC2_OTG
driver from these boards to ensure that the USB_DWC2 driver is used.
The rock-pi-e board does not enable the usb20_otg node so both USB_DWC2
and DWC2_OTG is removed from this board.
Enable RockUSB and UMS on all boards with a otg port in peripheral mode.
Also with the migration to DM_USB_GADGET completed the U-Boot specific
change to reorder usb nodes in the device tree can be reverted.
Signed-off-by: Jonas Karlman
---
arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi| 4 ++
.../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 4 ++
.../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 4 ++
arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 4 ++
arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 9
arch/arm/dts/rk3328-rock64-u-boot.dtsi| 4 ++
arch/arm/dts/rk3328-u-boot.dtsi | 4 --
arch/arm/dts/rk3328.dtsi | 41 ---
configs/evb-rk3328_defconfig | 5 ++-
configs/nanopi-r2c-plus-rk3328_defconfig | 5 ++-
configs/nanopi-r2c-rk3328_defconfig | 5 ++-
configs/nanopi-r2s-rk3328_defconfig | 5 ++-
configs/orangepi-r1-plus-lts-rk3328_defconfig | 5 ++-
configs/orangepi-r1-plus-rk3328_defconfig | 5 ++-
configs/roc-cc-rk3328_defconfig | 7
configs/rock-pi-e-rk3328_defconfig| 7
configs/rock64-rk3328_defconfig | 6 ---
17 files changed, 69 insertions(+), 55 deletions(-)
diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
index cca4f06145cf..4fa170eeaf8d 100644
--- a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
@@ -15,6 +15,10 @@
bootph-all;
};
+_otg {
+ dr_mode = "peripheral";
+};
+
_io_sdio {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
index 0dbe5a01f986..0a9423cd9c7e 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-lts-u-boot.dtsi
@@ -33,6 +33,10 @@
bootph-pre-ram;
};
+_otg {
+ dr_mode = "peripheral";
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
index 1af75ada1a62..1096821fc5d3 100644
--- a/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-orangepi-r1-plus-u-boot.dtsi
@@ -33,6 +33,10 @@
bootph-pre-ram;
};
+_otg {
+ dr_mode = "peripheral";
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
index 47d74964fd0c..582d6ba49b4e 100644
--- a/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-roc-cc-u-boot.dtsi
@@ -29,6 +29,10 @@
};
};
+_otg {
+ hnp-srp-disable;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
index 9ed0aef1ecc9..d314bfad6fc0 100644
--- a/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi
@@ -29,6 +29,15 @@
};
};
+_host {
+ phy-supply = <_host_5v>;
+};
+
+_host_5v {
+ /delete-property/ regulator-always-on;
+ /delete-property/ regulator-boot-on;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
index 85426495c3d8..551cff6f24f6 100644
--- a/arch/arm/dts/rk3328-rock64-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi
@@ -55,6 +55,10 @@
bootph-pre-ram;
};
+_otg {
+ hnp-srp-disable;
+};
+
_sd {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi
index 4d43fe2fb51a..e0c6aee58aba 100644
--- a/arch/arm/dts/rk3328-u-boot.dtsi
+++ b/arch/arm/dts/rk3328-u-boot.dtsi
@@ -130,10 +130,6 @@
bootph-all;
};
[PATCH 3/4] rockchip: board: Use a common USB Product ID for UMS
Change to use the common Product ID 0x0010 when the ums command is used.
This matches downstream vendor U-Boot and is a Product ID that tools
such as rkdeveloptool and RKDevTool will identify as MSC mode.
Signed-off-by: Jonas Karlman
---
arch/arm/mach-rockchip/board.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index f84ff542aea9..e9cfba756639 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -221,8 +221,23 @@ void enable_caches(void)
#endif
#if IS_ENABLED(CONFIG_USB_GADGET)
-#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET)
#include
+
+#if IS_ENABLED(CONFIG_USB_GADGET_DOWNLOAD)
+#define ROCKCHIP_G_DNL_UMS_PRODUCT_NUM 0x0010
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+ if (!strcmp(name, "usb_dnl_ums"))
+ put_unaligned(ROCKCHIP_G_DNL_UMS_PRODUCT_NUM, >idProduct);
+ else
+ put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, >idProduct);
+
+ return 0;
+}
+#endif /* CONFIG_USB_GADGET_DOWNLOAD */
+
+#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET)
#include
#include
--
2.43.0
[PATCH 1/4] rockchip: Update the default USB Product ID value
RK3036 is using the USB product id normally used by RK3066B, and RK3328 is using the product id normally used by RK3368. Fix this and update the default USB_GADGET_PRODUCT_NUM Kconfig option for remaining supported Rockchip SoCs to match the product id used in Mask ROM mode. Also remove a reference to the unknown ROCKCHIP_RK3229 symbol. Signed-off-by: Jonas Karlman --- drivers/usb/gadget/Kconfig | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index c72a8047635c..4621a6fd5e64 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -70,12 +70,21 @@ config USB_GADGET_PRODUCT_NUM hex "Product ID of the USB device" default 0x701a if ARCH_TEGRA default 0x1010 if ARCH_SUNXI - default 0x310a if ROCKCHIP_RK3036 + default 0x110a if ROCKCHIP_RV1108 + default 0x110b if ROCKCHIP_RV1126 default 0x300a if ROCKCHIP_RK3066 + default 0x301a if ROCKCHIP_RK3036 + default 0x310b if ROCKCHIP_RK3188 default 0x310c if ROCKCHIP_RK3128 - default 0x320a if ROCKCHIP_RK3229 || ROCKCHIP_RK3288 - default 0x330a if ROCKCHIP_RK3328 + default 0x320a if ROCKCHIP_RK3288 + default 0x320b if ROCKCHIP_RK322X + default 0x320c if ROCKCHIP_RK3328 + default 0x330a if ROCKCHIP_RK3368 default 0x330c if ROCKCHIP_RK3399 + default 0x330d if ROCKCHIP_PX30 + default 0x330e if ROCKCHIP_RK3308 + default 0x350a if ROCKCHIP_RK3568 + default 0x350b if ROCKCHIP_RK3588 default 0x0 help Product ID of the USB device emulated, reported to the host device. -- 2.43.0
[PATCH 2/4] rockchip: board: Prepare for use of DM_USB_GADGET with DWC2_OTG
The board_usb_init() and board_usb_cleanup() functions is always included when USB_GADGET and USB_GADGET_DWC2_OTG is enabled. Prepare for a change to use DM_USB_GADGET with DWC2_OTG by adding an extra ifdef condition. The extra separate ifdef for USB_GADGET prepare for next patch that adds a g_dnl_bind_fixup() function. Signed-off-by: Jonas Karlman --- arch/arm/mach-rockchip/board.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index dea5805c4665..f84ff542aea9 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -220,7 +220,8 @@ void enable_caches(void) } #endif -#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#if IS_ENABLED(CONFIG_USB_GADGET) +#if IS_ENABLED(CONFIG_USB_GADGET_DWC2_OTG) && !IS_ENABLED(CONFIG_DM_USB_GADGET) #include #include #include @@ -296,6 +297,7 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif /* CONFIG_USB_GADGET_DWC2_OTG */ +#endif /* CONFIG_USB_GADGET */ #if IS_ENABLED(CONFIG_FASTBOOT) int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) -- 2.43.0
[PATCH 0/4] rockchip: Migrate to use DM_USB_GADGET on RK3328
USB gadget is not working fully as expected on RK3328, it uses a board_usb_init() function to initialize the DWC2 OTG port, as a result the USB2PHY driver never gets invoked. An issue is that the USB_DWC2 driver is enabled and also gets loaded for the OTG port. A side effect of that is that the board will freeze if USB gadget is started after USB host have been stopped, the USB2PHY driver puts the OTG port in suspend mode on exit. To improve the situation this series changes to only enable one of USB_DWC2 (host) or DWC2_OTG (peripheral) depending on most likely usage of the port. It also migrates to use DM_USB_GADGET instead of board_usb_init(). First patch fixes and add Product ID for supported Rockchip SoCs. Second patch prepare board.c for use of DM_USB_GADGET with DWC2_OTG. Third patch add a g_dnl_bind_fixup() to configure a different Product ID when UMS is used. Final patch updates u-boot.dtsi and defconfigs to only use USB_DWC2 for host or migrate to use DM_USB_GADGET with DWC2_OTG for peripheral. UMS and ROCKUSB is enabled for all boards with otg port in peripheral mode. Hopefully current incompatibility between having USB_DWC2, DWC2_OTG and USB_DWC3_GADGET enabled together is something that could be improved on in a future series. Following have been tested on a Rock64, ROC-RK3328-CC, Rock Pi E and Orange Pi R1 Plus LTS: - USB host on all host ports: usb start && usb tree && usb stop - UMS on otg port: ums 0 mmc 1 - RockUSB on otg port: rockusb 0 mmc 1 This series depends on the following series and patches: - rockchip: rk3328: Update defconfigs, DTs and enable boot from SPI [1] - rockchip: Read cpuid and generate MAC address from efuse for RK3328 and RK3399 [2] - usb: dwc3-generic: Fix build errors when USB_DWC3_GADGET is disabled [3] - phy: rockchip-inno-usb2: Write to correct GRF [4] The copy of the series and all its depends can also be found at [5]. [1] https://patchwork.ozlabs.org/cover/1900345/ [2] https://patchwork.ozlabs.org/cover/1897743/ [3] https://patchwork.ozlabs.org/patch/1903946/ [4] https://patchwork.ozlabs.org/cover/1903987/ [5] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3328-gadget-v1 Jonas Karlman (4): rockchip: Update the default USB Product ID Kconfig option rockchip: board: Prepare for use of DM_USB_GADGET with DWC2_OTG rockchip: board: Use a common USB Product ID for UMS rockchip: Migrate to use DM_USB_GADGET on RK3328 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi| 4 ++ .../rk3328-orangepi-r1-plus-lts-u-boot.dtsi | 4 ++ .../dts/rk3328-orangepi-r1-plus-u-boot.dtsi | 4 ++ arch/arm/dts/rk3328-roc-cc-u-boot.dtsi| 4 ++ arch/arm/dts/rk3328-rock-pi-e-u-boot.dtsi | 9 arch/arm/dts/rk3328-rock64-u-boot.dtsi| 4 ++ arch/arm/dts/rk3328-u-boot.dtsi | 4 -- arch/arm/dts/rk3328.dtsi | 41 --- arch/arm/mach-rockchip/board.c| 19 - configs/evb-rk3328_defconfig | 5 ++- configs/nanopi-r2c-plus-rk3328_defconfig | 5 ++- configs/nanopi-r2c-rk3328_defconfig | 5 ++- configs/nanopi-r2s-rk3328_defconfig | 5 ++- configs/orangepi-r1-plus-lts-rk3328_defconfig | 5 ++- configs/orangepi-r1-plus-rk3328_defconfig | 5 ++- configs/roc-cc-rk3328_defconfig | 7 configs/rock-pi-e-rk3328_defconfig| 7 configs/rock64-rk3328_defconfig | 6 --- drivers/usb/gadget/Kconfig| 15 +-- 19 files changed, 99 insertions(+), 59 deletions(-) -- 2.43.0
[PATCH v3 10/13] arm: dts: introduce am62p5 U-Boot dts files
Include the U-Boot device tree files needed to boot the board. Signed-off-by: Bryan Brattlof --- arch/arm/dts/Makefile |2 + arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi | 2800 arch/arm/dts/k3-am62p-sk-binman.dtsi | 173 ++ arch/arm/dts/k3-am62p5-r5-sk.dts | 101 + arch/arm/dts/k3-am62p5-sk-u-boot.dtsi | 23 + 5 files changed, 3099 insertions(+) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7c2681eb93779..c8fd41d4a816e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1429,6 +1429,8 @@ dtb-$(CONFIG_SOC_K3_AM625) += k3-am625-sk.dtb \ dtb-$(CONFIG_SOC_K3_AM62A7) += k3-am62a7-sk.dtb \ k3-am62a7-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb + dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi new file mode 100644 index 0..f66435201530f --- /dev/null +++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi @@ -0,0 +1,2800 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02 + * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHzF1 = NA F2 = 1600MHz + * Density (per channel): 16Gb + * Number of Ranks: 2 + */ + +#define DDRSS_PLL_FHS_CNT 5 +#define DDRSS_PLL_FREQUENCY_1 8 +#define DDRSS_PLL_FREQUENCY_2 8 +#define DDRSS_SDRAM_IDX 17 +#define DDRSS_REGION_IDX 17 + +#define DDRSS_CTL_0_DATA 0x0B00 +#define DDRSS_CTL_1_DATA 0x +#define DDRSS_CTL_2_DATA 0x +#define DDRSS_CTL_3_DATA 0x +#define DDRSS_CTL_4_DATA 0x +#define DDRSS_CTL_5_DATA 0x +#define DDRSS_CTL_6_DATA 0x +#define DDRSS_CTL_7_DATA 0x2710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x0005 +#define DDRSS_CTL_10_DATA 0x0064 +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 +#define DDRSS_CTL_13_DATA 0x0005 +#define DDRSS_CTL_14_DATA 0x0C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 +#define DDRSS_CTL_17_DATA 0x0005 +#define DDRSS_CTL_18_DATA 0x0C80 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x +#define DDRSS_CTL_26_DATA 0x +#define DDRSS_CTL_27_DATA 0x +#define DDRSS_CTL_28_DATA 0x +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x +#define DDRSS_CTL_31_DATA 0x +#define DDRSS_CTL_32_DATA 0x +#define DDRSS_CTL_33_DATA 0x +#define DDRSS_CTL_34_DATA 0x0810 +#define DDRSS_CTL_35_DATA 0x4040 +#define DDRSS_CTL_36_DATA 0x +#define DDRSS_CTL_37_DATA 0x +#define DDRSS_CTL_38_DATA 0x +#define DDRSS_CTL_39_DATA 0x +#define DDRSS_CTL_40_DATA 0x040C +#define DDRSS_CTL_41_DATA 0x +#define DDRSS_CTL_42_DATA 0x0E38 +#define DDRSS_CTL_43_DATA 0x +#define DDRSS_CTL_44_DATA 0x0E38 +#define DDRSS_CTL_45_DATA 0x +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x0700 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x0303 +#define DDRSS_CTL_50_DATA 0x00620011 +#define DDRSS_CTL_51_DATA 0x09110045 +#define DDRSS_CTL_52_DATA 0x421D +#define DDRSS_CTL_53_DATA 0x00620011 +#define DDRSS_CTL_54_DATA 0x09110045 +#define DDRSS_CTL_55_DATA 0x0900421D +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040006DB +#define DDRSS_CTL_58_DATA 0x090D2005 +#define DDRSS_CTL_59_DATA 0x1710 +#define DDRSS_CTL_60_DATA 0x0C00DB60 +#define DDRSS_CTL_61_DATA 0x090D200D +#define DDRSS_CTL_62_DATA 0x1710 +#define DDRSS_CTL_63_DATA 0x0C00DB60 +#define DDRSS_CTL_64_DATA 0x0304200D +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x1F1E1F1E +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x043C3C07 +#define DDRSS_CTL_69_DATA 0x0303 +#define DDRSS_CTL_70_DATA 0x +#define DDRSS_CTL_71_DATA 0x0101 +#define DDRSS_CTL_72_DATA 0x +#define DDRSS_CTL_73_DATA 0x0100 +#define DDRSS_CTL_74_DATA 0x00130803 +#define DDRSS_CTL_75_DATA 0x00BB +#define DDRSS_CTL_76_DATA 0x0260 +#define DDRSS_CTL_77_DATA 0x1858 +#define DDRSS_CTL_78_DATA 0x0260 +#define DDRSS_CTL_79_DATA 0x1858 +#define DDRSS_CTL_80_DATA 0x0005 +#define DDRSS_CTL_81_DATA 0x000A +#define DDRSS_CTL_82_DATA 0x0010 +#define DDRSS_CTL_83_DATA 0x0130 +#define DDRSS_CTL_84_DATA 0x0304 +#define DDRSS_CTL_85_DATA 0x0130 +#define DDRSS_CTL_86_DATA 0x0304 +#define DDRSS_CTL_87_DATA
[PATCH] imx9: Update to mx93 A1 chip revision.
Use the latest, mx93a1-ahab-container.img that is compatible with the i.MX93 A1 revision. Using mx93a1-ahab-container.img on an A0 chip and conversely causes a boot failure without any traces on the UART. Signed-off-by: Mathieu Othacehe --- arch/arm/mach-imx/imx9/imximage.cfg | 2 +- doc/board/nxp/imx93_11x11_evk.rst | 8 doc/board/phytec/imx93-phyboard-segin.rst | 8 doc/board/variscite/imx93_var_som.rst | 8 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/mach-imx/imx9/imximage.cfg b/arch/arm/mach-imx/imx9/imximage.cfg index 3e440465b23..d327d6a6ef4 100644 --- a/arch/arm/mach-imx/imx9/imximage.cfg +++ b/arch/arm/mach-imx/imx9/imximage.cfg @@ -5,6 +5,6 @@ BOOT_FROM SD 0x400 SOC_TYPE IMX9 -APPEND mx93a0-ahab-container.img +APPEND mx93a1-ahab-container.img CONTAINER IMAGE A55 u-boot-spl-ddr.bin 0x2049A000 \ No newline at end of file diff --git a/doc/board/nxp/imx93_11x11_evk.rst b/doc/board/nxp/imx93_11x11_evk.rst index fb0ecf8af58..171645ad06c 100644 --- a/doc/board/nxp/imx93_11x11_evk.rst +++ b/doc/board/nxp/imx93_11x11_evk.rst @@ -42,10 +42,10 @@ Get ahab-container.img .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin - $ chmod +x firmware-sentinel-0.10.bin - $ ./firmware-sentinel-0.10.bin - $ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin + $ chmod +x firmware-sentinel-0.11.bin + $ ./firmware-sentinel-0.11.bin + $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) Build U-Boot diff --git a/doc/board/phytec/imx93-phyboard-segin.rst b/doc/board/phytec/imx93-phyboard-segin.rst index da8772ecd5c..ce17fbec78d 100644 --- a/doc/board/phytec/imx93-phyboard-segin.rst +++ b/doc/board/phytec/imx93-phyboard-segin.rst @@ -41,10 +41,10 @@ Get ahab-container.img .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin - $ chmod +x firmware-sentinel-0.10.bin - $ ./firmware-sentinel-0.10.bin - $ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin + $ chmod +x firmware-sentinel-0.11.bin + $ ./firmware-sentinel-0.11.bin + $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) Build U-Boot diff --git a/doc/board/variscite/imx93_var_som.rst b/doc/board/variscite/imx93_var_som.rst index 4951afd2dad..02309f2ad87 100644 --- a/doc/board/variscite/imx93_var_som.rst +++ b/doc/board/variscite/imx93_var_som.rst @@ -42,10 +42,10 @@ Get ahab-container.img .. code-block:: bash - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.10.bin - $ chmod +x firmware-sentinel-0.10.bin - $ ./firmware-sentinel-0.10.bin - $ cp firmware-sentinel-0.10/mx93a0-ahab-container.img $(srctree) + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin + $ chmod +x firmware-sentinel-0.11.bin + $ ./firmware-sentinel-0.11.bin + $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) Build U-Boot -- 2.41.0
[PATCH v2 2/2] arm: separate .data and .text sections of EFI binaries
EFI binaries should not contain sections that are both writable and
executable. Separate the RX .text section from the RW .data section.
We currently don't created relocation sections (.rel.*) for our EFI
binaries. Anyway these would have to be converted to PE/COFF relocations.
Enumerate them under DISCARD and add a comment.
Correct the characteristics of the sections.
Signed-off-by: Heinrich Schuchardt
---
v2:
Consider that 32-bit arm uses .rel and not .rela relocations
and discard them as they are cannot be used in EFI binaries.
Correct the characteristics of the .reloc section.
---
arch/arm/lib/crt0_arm_efi.S | 40
arch/arm/lib/elf_arm_efi.lds | 28 ++---
2 files changed, 52 insertions(+), 16 deletions(-)
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
index 7a4e5dff75..7219c0f2fe 100644
--- a/arch/arm/lib/crt0_arm_efi.S
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -23,7 +23,7 @@ pe_header:
.long IMAGE_NT_SIGNATURE /* 'PE' */
coff_header:
.short IMAGE_FILE_MACHINE_THUMB/* Mixed ARM/Thumb */
- .short 2 /* nr_sections */
+ .short 3 /* nr_sections */
.long 0 /* TimeDateStamp */
.long 0 /* PointerToSymbolTable */
.long 0 /* NumberOfSymbols */
@@ -98,22 +98,44 @@ section_table:
.long 0 /* PointerToLineNumbers */
.short 0 /* NumberOfRelocations */
.short 0 /* NumberOfLineNumbers */
- .long 0x42100040 /* Characteristics (section flags) */
+ /* Characteristics (section flags) */
+ .long (IMAGE_SCN_MEM_READ | \
+IMAGE_SCN_MEM_DISCARDABLE | \
+IMAGE_SCN_CNT_INITIALIZED_DATA)
.ascii ".text"
.byte 0
.byte 0
.byte 0 /* end of 0 padding of section name */
- .long _edata - _start /* VirtualSize */
+ .long _text_size /* VirtualSize */
.long _start - image_base /* VirtualAddress */
- .long _edata - _start /* SizeOfRawData */
+ .long _text_size /* SizeOfRawData */
.long _start - image_base /* PointerToRawData */
+ .long 0 /* PointerToRelocations */
+ .long 0 /* PointerToLineNumbers */
+ .short 0 /* NumberOfRelocations */
+ .short 0 /* NumberOfLineNumbers */
+ /* Characteristics (section flags) */
+ .long (IMAGE_SCN_MEM_READ | \
+IMAGE_SCN_MEM_EXECUTE | \
+IMAGE_SCN_CNT_CODE)
- .long 0 /* PointerToRelocations (0 for executables) */
- .long 0 /* PointerToLineNumbers (0 for executables) */
- .short 0 /* NumberOfRelocations (0 for executables) */
- .short 0 /* NumberOfLineNumbers (0 for executables) */
- .long 0xe0500020 /* Characteristics (section flags) */
+ .ascii ".data"
+ .byte 0
+ .byte 0
+ .byte 0 /* end of 0 padding of section name */
+ .long _data_size /* VirtualSize */
+ .long _data - image_base /* VirtualAddress */
+ .long _data_size /* SizeOfRawData */
+ .long _data - image_base /* PointerToRawData */
+ .long 0 /* PointerToRelocations */
+ .long 0 /* PointerToLineNumbers */
+ .short 0 /* NumberOfRelocations */
+ .short 0 /* NumberOfLineNumbers */
+ /* Characteristics (section flags) */
+ .long (IMAGE_SCN_MEM_WRITE | \
+IMAGE_SCN_MEM_READ | \
+IMAGE_SCN_CNT_INITIALIZED_DATA)
.align 12
_start:
diff --git a/arch/arm/lib/elf_arm_efi.lds b/arch/arm/lib/elf_arm_efi.lds
index 767ebda635..41440594aa 100644
--- a/arch/arm/lib/elf_arm_efi.lds
+++ b/arch/arm/lib/elf_arm_efi.lds
@@ -7,6 +7,12 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
+
+PHDRS
+{
+ data PT_LOAD FLAGS(3); /* PF_W | PF_X */
+}
+
ENTRY(_start)
SECTIONS
{
@@ -18,11 +24,13 @@ SECTIONS
*(.gnu.linkonce.t.*)
*(.srodata)
*(.rodata*)
+ . = ALIGN(16);
+ *(.dynamic);
. = ALIGN(512);
}
_etext = .;
_text_size = . - _text;
- .dynamic : { *(.dynamic) }
+ . = ALIGN(4096);
.data : {
_data = .;
*(.sdata)
@@ -47,14 +55,20 @@ SECTIONS
[PATCH v2 1/2] arm: page align EFI binary section
Change the alignment of the relocation code in EFI binaries to match page
boundaries.
Signed-off-by: Heinrich Schuchardt
---
v2:
new patch
---
arch/arm/lib/crt0_arm_efi.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/lib/crt0_arm_efi.S b/arch/arm/lib/crt0_arm_efi.S
index 75ee37b7d3..7a4e5dff75 100644
--- a/arch/arm/lib/crt0_arm_efi.S
+++ b/arch/arm/lib/crt0_arm_efi.S
@@ -115,14 +115,14 @@ section_table:
.short 0 /* NumberOfLineNumbers (0 for executables) */
.long 0xe0500020 /* Characteristics (section flags) */
- .align 9
+ .align 12
_start:
stmfd sp!, {r0-r2, lr}
adr r1, .L_DYNAMIC
ldr r0, [r1]
add r1, r0, r1
- adr r0, image_base
+ adrlr0, image_base
bl _relocate
teq r0, #0
bne 0f
--
2.43.0
[PATCH v2 0/2] arm: separate .data and .text sections of EFI binaries
For security it is preferable that memory pages for executable code are not writable. So there should be only RX and RW pages. To enable this sections of EFI binaries must be page aligned. Furthermore .text and .data sections must be separated. We already made the necessary changes for arm64 and riscv64. This series addresses the arm32 architecture. v2: New patch to page align EFI binary section. Consider that 32-bit arm uses .rel and not .rela relocations and discard them as they are cannot be used in EFI binaries. Heinrich Schuchardt (2): arm: page align EFI binary section arm: separate .data and .text sections of EFI binaries arch/arm/lib/crt0_arm_efi.S | 44 +++- arch/arm/lib/elf_arm_efi.lds | 28 +-- 2 files changed, 54 insertions(+), 18 deletions(-) -- 2.43.0
[PATCH v3 06/13] arch: mach-k3: introduce basic files to support the am62px SoC family
Introduce the basic functions and definitions needed to properly
initialize TI's am62p family of SoCs
Signed-off-by: Bryan Brattlof
---
arch/arm/mach-k3/Kconfig | 7 +-
arch/arm/mach-k3/Makefile | 1 +
arch/arm/mach-k3/am62p5_init.c | 280 +
arch/arm/mach-k3/am62px/Kconfig| 32 +++
arch/arm/mach-k3/include/mach/am62p_hardware.h | 83
arch/arm/mach-k3/include/mach/am62p_spl.h | 49 +
arch/arm/mach-k3/include/mach/hardware.h | 4 +
arch/arm/mach-k3/include/mach/spl.h| 4 +
8 files changed, 459 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index ffceb6428d42e..3200418db9e2a 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -22,6 +22,9 @@ config SOC_K3_AM625
config SOC_K3_AM62A7
bool "TI's K3 based AM62A7 SoC Family Support"
+config SOC_K3_AM62P5
+ bool "TI's K3 based AM62P5 SoC Family Support"
+
endchoice
if SOC_K3_J721E
@@ -34,7 +37,7 @@ config SYS_SOC
config SYS_K3_NON_SECURE_MSRAM_SIZE
hex
- default 0x8 if SOC_K3_AM654
+ default 0x8 if SOC_K3_AM654 || SOC_K3_AM62P5
default 0x10 if SOC_K3_J721E || SOC_K3_J721S2
default 0x1c if SOC_K3_AM642
default 0x3c000 if SOC_K3_AM625 || SOC_K3_AM62A7
@@ -78,6 +81,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
default 0x43c3f290 if SOC_K3_AM625
default 0x43c3f290 if SOC_K3_AM62A7 && CPU_V7R
default 0x7000f290 if SOC_K3_AM62A7 && ARM64
+ default 0x43c4f290 if SOC_K3_AM62P5
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@@ -153,6 +157,7 @@ source "arch/arm/mach-k3/am65x/Kconfig"
source "arch/arm/mach-k3/am64x/Kconfig"
source "arch/arm/mach-k3/am62x/Kconfig"
source "arch/arm/mach-k3/am62ax/Kconfig"
+source "arch/arm/mach-k3/am62px/Kconfig"
source "arch/arm/mach-k3/j721e/Kconfig"
source "arch/arm/mach-k3/j721s2/Kconfig"
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 42161376469e2..820b313a83c23 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -20,5 +20,6 @@ obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
obj-$(CONFIG_SOC_K3_AM62A7) += am62a7_init.o
+obj-$(CONFIG_SOC_K3_AM62P5) += am62p5_init.o
endif
obj-y += common.o security.o
diff --git a/arch/arm/mach-k3/am62p5_init.c b/arch/arm/mach-k3/am62p5_init.c
new file mode 100644
index 0..9ff877d5d26e8
--- /dev/null
+++ b/arch/arm/mach-k3/am62p5_init.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM62P5: SoC specific initialization
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include
+#include
+#include "sysfw-loader.h"
+#include "common.h"
+#include
+#include
+#include
+
+struct fwl_data cbass_main_fwls[] = {
+ { "FSS_DAT_REG3", 7, 8 },
+};
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(, (uintptr_t *)ROM_EXTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all WKUP_CTRL_MMR0 module registers */
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 5);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
+ mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 4);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+
+ /* Unlock all MCU_CTRL_MMR0 module registers */
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
+ mmr_unlock(MCU_CTRL_MMR0_BASE, 6);
+
+ /* Unlock PADCFG_CTRL_MMR padconf registers */
+ mmr_unlock(PADCFG_MMR0_BASE, 1);
+ mmr_unlock(PADCFG_MMR1_BASE, 1);
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (IS_ENABLED(CONFIG_CPU_V7R))
+
[PATCH v3 12/13] configs: introduce configs needed for the am62px
Introduce the initial configs needed to support the am62px SoC family Signed-off-by: Bryan Brattlof --- configs/am62px_evm_a53_defconfig | 178 +++ configs/am62px_evm_r5_defconfig | 137 ++ include/configs/am62px_evm.h | 14 +++ 3 files changed, 329 insertions(+) diff --git a/configs/am62px_evm_a53_defconfig b/configs/am62px_evm_a53_defconfig new file mode 100644 index 0..bd8002108b10c --- /dev/null +++ b/configs/am62px_evm_a53_defconfig @@ -0,0 +1,178 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SOC_K3_AM62P5=y +CONFIG_K3_ATF_LOAD_ADDR=0x9e78 +CONFIG_TARGET_AM62P5_A53_EVM=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8048 +CONFIG_SF_DEFAULT_SPEED=2500 +CONFIG_ENV_SIZE=0x4 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_OF_UPSTREAM=y +CONFIG_DEFAULT_DEVICE_TREE="ti/k3-am62p5-sk" +CONFIG_SPL_TEXT_BASE=0x8008 +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100 +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTSTD_DEFAULTS=y +CONFIG_BOOTCOMMAND="run envboot; bootflow scan -lb" +CONFIG_SPL_MAX_SIZE=0x58000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80a0 +CONFIG_SPL_BSS_MAX_SIZE=0x8 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_STACK_R=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x28 +CONFIG_SPL_THERMAL=y +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_SYS_MAXARGS=64 +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_DEVICE_REMOVE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_MTD=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC000 +CONFIG_FASTBOOT_BUF_SIZE=0x2F00 +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_I2C_EEPROM=y +CONFIG_SPL_I2C_EEPROM=y +CONFIG_FS_LOADER=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HX_T=y +CONFIG_PHY_TI_DP83867=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y
[PATCH v3 07/13] board: ti: introduce basic board files for the am62px family
Introduce the basic files needed to support the am62px family of SoCs
Co-developed-by: Hari Nagalla
Signed-off-by: Hari Nagalla
Signed-off-by: Bryan Brattlof
---
board/ti/am62px/Kconfig | 26 ++
board/ti/am62px/MAINTAINERS | 9 +
board/ti/am62px/Makefile | 7 +
board/ti/am62px/am62px.env | 15 +
board/ti/am62px/board-cfg.yaml | 37 ++
board/ti/am62px/evm.c| 29 ++
board/ti/am62px/pm-cfg.yaml | 12 +
board/ti/am62px/rm-cfg.yaml | 987 +++
board/ti/am62px/sec-cfg.yaml | 378 +++
board/ti/am62px/tifs-rm-cfg.yaml | 879 ++
10 files changed, 2379 insertions(+)
diff --git a/board/ti/am62px/Kconfig b/board/ti/am62px/Kconfig
new file mode 100644
index 0..9d95ffd9b2908
--- /dev/null
+++ b/board/ti/am62px/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+
+if TARGET_AM62P5_R5_EVM || TARGET_AM62P5_A53_EVM
+
+config SYS_BOARD
+ default "am62px"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am62px_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM62P5_R5_EVM
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+endif
diff --git a/board/ti/am62px/MAINTAINERS b/board/ti/am62px/MAINTAINERS
new file mode 100644
index 0..57c86ddbc4aef
--- /dev/null
+++ b/board/ti/am62px/MAINTAINERS
@@ -0,0 +1,9 @@
+AM62Px BOARD
+M: Vignesh Raghavendra
+M: Bryan Brattlof
+M: Tom Rini
+S: Maintained
+F: board/ti/am62px/
+F: include/configs/am62p5_evm.h
+F: configs/am62px_evm_r5_defconfig
+F: configs/am62px_evm_a53_defconfig
diff --git a/board/ti/am62px/Makefile b/board/ti/am62px/Makefile
new file mode 100644
index 0..921afdff27a24
--- /dev/null
+++ b/board/ti/am62px/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/am62px/am62px.env b/board/ti/am62px/am62px.env
new file mode 100644
index 0..f8b6aff2c2fdf
--- /dev/null
+++ b/board/ti/am62px/am62px.env
@@ -0,0 +1,15 @@
+#include
+#include
+
+name_kern=Image
+console=ttyS2,115200n8
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x0280
+ ${mtdparts}
+run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
+
+boot_targets=mmc1 mmc0 pxe dhcp
+boot=mmc
+mmcdev=1
+bootpart=1:2
+bootdir=/boot
+rd_spec=-
diff --git a/board/ti/am62px/board-cfg.yaml b/board/ti/am62px/board-cfg.yaml
new file mode 100644
index 0..d539011aff9f3
--- /dev/null
+++ b/board/ti/am62px/board-cfg.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Board configuration for AM62Px SoCs
+#
+
+---
+
+board-cfg:
+rev:
+boardcfg_abi_maj: 0x0
+boardcfg_abi_min: 0x1
+control:
+subhdr:
+magic: 0xC1D3
+size: 7
+main_isolation_enable: 0x5A
+main_isolation_hostid: 0x2
+secproxy:
+subhdr:
+magic: 0x1207
+size: 7
+scaling_factor: 0x1
+scaling_profile: 0x1
+disable_main_nav_secure_proxy: 0
+msmc:
+subhdr:
+magic: 0xA5C3
+size: 5
+msmc_cache_size: 0x10
+debug_cfg:
+subhdr:
+magic: 0x020C
+size: 8
+trace_dst_enables: 0x00
+trace_src_enables: 0x00
diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c
new file mode 100644
index 0..97a95ce8cc2d5
--- /dev/null
+++ b/board/ti/am62px/evm.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM62Px platforms
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/ti/am62px/pm-cfg.yaml b/board/ti/am62px/pm-cfg.yaml
new file mode 100644
index 0..3ff27ce702c26
--- /dev/null
+++ b/board/ti/am62px/pm-cfg.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Power management configuration for AM62Px
+#
+#
+---
+pm-cfg:
+rev:
+boardcfg_abi_maj: 0x0
+boardcfg_abi_min: 0x1
diff --git a/board/ti/am62px/rm-cfg.yaml b/board/ti/am62px/rm-cfg.yaml
new file mode 100644
index 0..caa2f7a5a83e1
--- /dev/null
+++ b/board/ti/am62px/rm-cfg.yaml
@@ -0,0 +1,987 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2022-2023
[PATCH v3 08/13] firmware: ti_sci_static_data: add static DMA channel data
From: Hari Nagalla
Include the static DMA channel data for ti_sci
Signed-off-by: Hari Nagalla
Signed-off-by: Bryan Brattlof
---
drivers/firmware/ti_sci_static_data.h | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/ti_sci_static_data.h
b/drivers/firmware/ti_sci_static_data.h
index 567ce8911a7da..135ec01bda460 100644
--- a/drivers/firmware/ti_sci_static_data.h
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -84,7 +84,8 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
};
#endif /* CONFIG_SOC_K3_J721S2 */
-#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7)
+#if IS_ENABLED(CONFIG_SOC_K3_AM625) || IS_ENABLED(CONFIG_SOC_K3_AM62A7) || \
+ IS_ENABLED(CONFIG_SOC_K3_AM62P5)
static struct ti_sci_resource_static_data rm_static_data[] = {
/* BC channels */
{
@@ -95,7 +96,7 @@ static struct ti_sci_resource_static_data rm_static_data[] = {
},
{ },
};
-#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */
+#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 || CONFIG_SOC_K3_AM62P5
*/
#else
static struct ti_sci_resource_static_data rm_static_data[] = {
--
2.43.2
[PATCH v3 02/13] power: domain: ti: use IS_ENABLED macro
Cleanup this list and standardize on using the IS_ENABLED macro for the
power domain data list.
Reviewed-by: Igor Opaniuk
Signed-off-by: Bryan Brattlof
---
drivers/power/domain/ti-power-domain.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/power/domain/ti-power-domain.c
b/drivers/power/domain/ti-power-domain.c
index b34c982f4f5fa..dc5d74539edcf 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -81,19 +81,20 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.family = "J7200",
.data = _pd_platdata,
},
-#elif CONFIG_SOC_K3_J721S2
+#endif
+#if IS_ENABLED(CONFIG_SOC_K3_J721S2)
{
.family = "J721S2",
.data = _pd_platdata,
},
#endif
-#ifdef CONFIG_SOC_K3_AM625
+#if IS_ENABLED(CONFIG_SOC_K3_AM625)
{
.family = "AM62X",
.data = _pd_platdata,
},
#endif
-#ifdef CONFIG_SOC_K3_AM62A7
+#if IS_ENABLED(CONFIG_SOC_K3_AM62A7)
{
.family = "AM62AX",
.data = _pd_platdata,
--
2.43.2
[PATCH v3 03/13] arm: mach-k3: am62px: introduce clock and device files for wkup spl
Include the clock and lpsc tree files needed for the wkup spl to
initialize the proper PLLs and power domains to boot the SoC.
Signed-off-by: Bryan Brattlof
---
arch/arm/mach-k3/r5/Makefile | 1 +
arch/arm/mach-k3/r5/am62px/Makefile| 6 +
arch/arm/mach-k3/r5/am62px/clk-data.c | 325 +
arch/arm/mach-k3/r5/am62px/dev-data.c | 71 +++
drivers/clk/ti/clk-k3.c| 6 +
drivers/power/domain/ti-power-domain.c | 6 +
include/k3-clk.h | 1 +
include/k3-dev.h | 1 +
8 files changed, 417 insertions(+)
diff --git a/arch/arm/mach-k3/r5/Makefile b/arch/arm/mach-k3/r5/Makefile
index b99199d337411..d1cd96d459bc4 100644
--- a/arch/arm/mach-k3/r5/Makefile
+++ b/arch/arm/mach-k3/r5/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_SOC_K3_J721E) += j7200/
obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
obj-$(CONFIG_SOC_K3_AM625) += am62x/
obj-$(CONFIG_SOC_K3_AM62A7) += am62ax/
+obj-$(CONFIG_SOC_K3_AM62P5) += am62px/
obj-y += lowlevel_init.o
obj-y += r5_mpu.o
diff --git a/arch/arm/mach-k3/r5/am62px/Makefile
b/arch/arm/mach-k3/r5/am62px/Makefile
new file mode 100644
index 0..50b0df20a3d1a
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/r5/am62px/clk-data.c
b/arch/arm/mach-k3/r5/am62px/clk-data.c
new file mode 100644
index 0..4b9892fe05167
--- /dev/null
+++ b/arch/arm/mach-k3/r5/am62px/clk-data.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * AM62PX specific clock platform data
+ *
+ * This file is auto generated. Please do not hand edit and report any issues
+ * to Bryan Brattlof .
+ *
+ * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ NULL,
+ NULL,
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ NULL,
+};
+
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_hfosc0_clkout",
+ "gluelogic_rcosc_clk_1p0v_97p65k",
+ "gluelogic_lfosc0_clkout",
+};
+
+static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
+ "board_0_mmc1_clklb_out",
+ "board_0_mmc1_clk_out",
+};
+
+static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
+ "board_0_ospi0_dqs_out",
+ "board_0_ospi0_lbclko_out",
+};
+
+static const char * const main_usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const main_usb1_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "postdiv4_16ff_main_0_hsdivout8_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] =
{
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "hsdiv4_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const clkout0_ctrl_out0_parents[] = {
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+};
+
+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_0_hsdivout5_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
+static const char * const main_gtcclk_sel_out0_parents[] = {
+ "postdiv4_16ff_main_2_hsdivout5_clk",
+ "postdiv4_16ff_main_0_hsdivout6_clk",
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ NULL,
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
+ "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout1_clk",
+ "postdiv1_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const main_timerclkn_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "clk_32k_rc_sel_out0",
+ "postdiv4_16ff_main_0_hsdivout7_clk",
+ "gluelogic_rcosc_clkout",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ "board_0_cp_gemac_cpts0_rft_clk_out",
+ "hsdiv4_16fft_main_1_hsdivout3_clk",
+ "postdiv4_16ff_main_2_hsdivout6_clk",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * const wkup_clkout_sel_out0_parents[] = {
+ NULL,
+
[PATCH v3 04/13] ram: k3-ddrss: enable the am62ax's DDR controller for am62px
The am62px family of SoCs uses the same DDR controller as found on the am62ax family. Enable this option when building for the am62px family Signed-off-by: Bryan Brattlof --- drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 5b07e92030142..56391058567bb 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -65,7 +65,7 @@ choice default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 default K3_AM64_DDRSS if SOC_K3_AM642 default K3_AM64_DDRSS if SOC_K3_AM625 - default K3_AM62A_DDRSS if SOC_K3_AM62A7 + default K3_AM62A_DDRSS if SOC_K3_AM62A7 || SOC_K3_AM62P5 config K3_J721E_DDRSS bool "Enable J721E DDRSS support" -- 2.43.2
[PATCH v3 09/13] dma: ti: k3-udma: Add DMA PSIL mappings for AM62P and J722S
From: Vignesh Raghavendra
Add PSIL data for the AM62P and the J722S SoC family. The PSIL mapping
for the J722S is the same except for the extra instances of the CSI-RX.
So let's reuse the same file for both the AM62P and J722S.
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Ravi Gunasekaran
Signed-off-by: Vaishnav Achath
Signed-off-by: Jayesh Choudhary
[b...@ti.com: rebased to U-Boot v2024.01]
Signed-off-by: Bryan Brattlof
---
drivers/dma/ti/Makefile| 2 +
drivers/dma/ti/k3-psil-am62p.c | 325 +
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 4 +
4 files changed, 332 insertions(+)
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index f4e0271efbf32..17223b20432da 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -9,3 +9,5 @@ k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
k3-psil-data-$(CONFIG_SOC_K3_AM625) += k3-psil-am62.o
k3-psil-data-$(CONFIG_SOC_K3_AM62A7) += k3-psil-am62a.o
+k3-psil-data-$(CONFIG_SOC_K3_AM62P5) += k3-psil-am62p.o
+k3-psil-data-$(CONFIG_SOC_K3_J722S) += k3-psil-am62p.o
diff --git a/drivers/dma/ti/k3-psil-am62p.c b/drivers/dma/ti/k3-psil-am62p.c
new file mode 100644
index 0..8739bf41b5b7c
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am62p.c
@@ -0,0 +1,325 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1,\
+ .default_flow_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1,\
+ .default_flow_id = -1, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 16, \
+ .mapped_channel_id = ch,\
+ .flow_start = flow_base,\
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 64, \
+ .mapped_channel_id = ch,\
+ .flow_start = flow_base,\
+ .flow_num = flow_cnt, \
+ .default_flow_id = default_flow,\
+ .notdpkt = tx, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1,\
+ .pdma_burst = 1,\
+ }, \
+ }
[PATCH v3 05/13] arm: mach-k3: invert logic for split DM firmware config
Currently, for the K3 generation of SoCs, there are more SoCs that utilize the split firmware approach than the combined DMSC firmware. Invert the logic to avoid adding more and more SoCs to this list. Acked-by: Andrew Davis Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 03898424c9546..ffceb6428d42e 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -130,7 +130,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2 || SOC_K3_AM625 || SOC_K3_AM62A7) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on CPU_V7R && !SOC_K3_AM642 && !SOC_K3_AM654 && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM -- 2.43.2
[PATCH v3 00/13] Hello Again Everyone!
**Note:** This series depends on the v6 OF_UPSTREAM work from Sumit[0]. Patch #11 was added to fix some Makefile.spl targets to allow SPL builds to complete with the OF_UPSTREAM series. The AM62Px is an extension of the existing Sitara AM62x low-cost family of application processors built for Automotive and Linux Application development. Scalable Arm Cortex-A53 performance and embedded features, such as: multi high-definition display support, 3D-graphics acceleration, 4K video acceleration, and extensive peripherals make the AM62Px well-suited for a broad range of automation and industrial application, including automotive digital instrumentation, automotive displays, industrial HMI, and more. Some highlights of AM62P SoC are: * Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single core variants are provided in the same package to allow HW compatible designs. * One Device manager Cortex-R5F for system power and resource management, and one Cortex-R5F for Functional Safety or general-purpose usage. * One 3D GPU up to 50 GLFOPS * H.264/H.265 Video Encode/Decode. * Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution * Integrated Giga-bit Ethernet switch supporting up to a total of two external ports (TSN capable). * 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. * Dedicated Centralized Hardware Security Module with support for secure boot, debug security and crypto acceleration and trusted execution environment. * One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. * Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling battery powered system design. For those interested, more details about this SoC can be found in the Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 Proof-of-Life: https://paste.sr.ht/~bryanb/af2ac108a9362549aa326f182e87918d52bf2d71 Currently, while more peripherals are being added in Linux[0], this series will only support UART boot. Thanks for reviewing! ~Bryan Changes from v2: [2] - dropped the extra ARCH_K3 not needed for the K3_DM_FW option - removed the extra _pktdma and _bcdma nodes already present in the kernel dtbs - corrected a few patch fixup errors - rebased ontop op OF_UPSTREAM v5 [0] - %s/uboot/U-Boot/g Changes from v1: [1] - squashed all clk and lpsc tree updates into a single commit - corrected SOC_K3_AM642 typo with DM firmware Kconfig option - updated RM configs and dma nodes to enable IP that need DMA - added the dtb targets to the dts/Makefile - rebased the series on top of v2024.01-rc1 - switched to bootstd rather than use distro boot scripts. - enabled OF_UPSTREAM instead of using the arch/arm/dts directory [0] https://lore.kernel.org/u-boot/20240222093607.3085545-1-sumit.g...@linaro.org/ [1] https://lore.kernel.org/all/20231012230616.2101992-13...@ti.com/ [2] https://lore.kernel.org/u-boot/20240201030634.1120963-17...@ti.com/ --- Bryan Brattlof (11): soc: add info to identify the am62p SoC family power: domain: ti: use IS_ENABLED macro arm: mach-k3: am62px: introduce clock and device files for wkup spl ram: k3-ddrss: enable the am62ax's DDR controller for am62px arm: mach-k3: invert logic for split DM firmware config arch: mach-k3: introduce basic files to support the am62px SoC family board: ti: introduce basic board files for the am62px family arm: dts: introduce am62p5 U-Boot dts files Makefile: remove hardcoded device tree source directory configs: introduce configs needed for the am62px doc: board: ti: introduce am62px documentation Hari Nagalla (1): firmware: ti_sci_static_data: add static DMA channel data Vignesh Raghavendra (1): dma: ti: k3-udma: Add DMA PSIL mappings for AM62P and J722S Makefile | 18 +- arch/arm/dts/Makefile |2 + arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi | 2800 arch/arm/dts/k3-am62p-sk-binman.dtsi | 173 ++ arch/arm/dts/k3-am62p5-r5-sk.dts | 101 + arch/arm/dts/k3-am62p5-sk-u-boot.dtsi | 23 + arch/arm/mach-k3/Kconfig |9 +- arch/arm/mach-k3/Makefile |1 + arch/arm/mach-k3/am62p5_init.c | 280 +++ arch/arm/mach-k3/am62px/Kconfig| 32 + arch/arm/mach-k3/include/mach/am62p_hardware.h | 83 + arch/arm/mach-k3/include/mach/am62p_spl.h | 49 + arch/arm/mach-k3/include/mach/hardware.h |6 + arch/arm/mach-k3/include/mach/spl.h|4 + arch/arm/mach-k3/r5/Makefile |1 + arch/arm/mach-k3/r5/am62px/Makefile|6 +
[PATCH v3 13/13] doc: board: ti: introduce am62px documentation
Introduce basic documentation for the am62p family of SoCs. Signed-off-by: Bryan Brattlof --- doc/board/ti/am62px_sk.rst | 289 + doc/board/ti/k3.rst| 1 + 2 files changed, 290 insertions(+) diff --git a/doc/board/ti/am62px_sk.rst b/doc/board/ti/am62px_sk.rst new file mode 100644 index 0..1f2982c36f9e4 --- /dev/null +++ b/doc/board/ti/am62px_sk.rst @@ -0,0 +1,289 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Bryan Brattlof + +AM62Px Platforms + + +The AM62Px is an extension of the existing Sitara AM62x low-cost family +of application processors built for Automotive and Linux Application +development. Scalable Arm Cortex-A53 performance and embedded features, +such as: multi high-definition display support, 3D-graphics +acceleration, 4K video acceleration, and extensive peripherals make the +AM62Px well-suited for a broad range of automation and industrial +application, including automotive digital instrumentation, automotive +displays, industrial HMI, and more. + +Some highlights of AM62P SoC are: + +* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. + Dual/Single core variants are provided in the same package to allow HW + compatible designs. + +* One Device manager Cortex-R5F for system power and resource + management, and one Cortex-R5F for Functional Safety or + general-purpose usage. + +* One 3D GPU up to 50 GLFOPS + +* H.264/H.265 Video Encode/Decode. + +* Display support: 3x display support over OLDI/LVDS (1x OLDI-DL, 1x or + 2x OLDI-SL), DSI, or DPI. Up to 3840x1080 @ 60fps resolution + +* Integrated Giga-bit Ethernet switch supporting up to a total of two + external ports (TSN capable). + +* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3xMMC and SD, GPMC for + NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio, + 1xCSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals. + +* Dedicated Centralized Hardware Security Module with support for secure + boot, debug security and crypto acceleration and trusted execution + environment. + +* One 32-bit DDR Subsystem that supports LPDDR4, DDR4 memory types. + +* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, + enabling battery powered system design. + +For those interested, more details about this SoC can be found in the +Technical Reference Manual here: https://www.ti.com/lit/pdf/spruj83 + +Boot Flow: +-- + +The bootflow is exactly the same as all SoCs in the am62xxx extended SoC +family. Below is the pictorial representation: + +.. image:: img/boot_diagram_k3_current.svg + :alt: Boot flow diagram + +- Here TIFS acts as master and provides all the critical services. R5/A53 + requests TIFS to get these services done as shown in the above diagram. + +Sources: + + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_boot_sources +:end-before: .. k3_rst_include_end_boot_sources + +Build procedure: + + +0. Setup the environment variables: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_desc +:end-before: .. k3_rst_include_end_common_env_vars_desc + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_board_env_vars_desc +:end-before: .. k3_rst_include_end_board_env_vars_desc + +Set the variables corresponding to this platform: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_common_env_vars_defn +:end-before: .. k3_rst_include_end_common_env_vars_defn + +.. code-block:: bash + + $ export UBOOT_CFG_CORTEXR=am62px_evm_r5_defconfig + $ export UBOOT_CFG_CORTEXA=am62px_evm_a53_defconfig + $ export TFA_BOARD=lite + $ # we dont use any extra TFA parameters + $ unset TFA_EXTRA_ARGS + $ export OPTEE_PLATFORM=k3-am62x + $ export OPTEE_EXTRA_ARGS="CFG_WITH_SOFTWARE_PRNG=y" + +.. am62px_evm_rst_include_start_build_steps + +1. Trusted Firmware-A: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_tfa +:end-before: .. k3_rst_include_end_build_steps_tfa + + +2. OP-TEE: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_optee +:end-before: .. k3_rst_include_end_build_steps_optee + +3. U-Boot: + +* 3.1 R5: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_spl_r5 +:end-before: .. k3_rst_include_end_build_steps_spl_r5 + +* 3.2 A53: + +.. include:: ../ti/k3.rst +:start-after: .. k3_rst_include_start_build_steps_uboot +:end-before: .. k3_rst_include_end_build_steps_uboot +.. am62px_evm_rst_include_end_build_steps + +Target Images +-- + +In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC +variant (HS-FS, HS-SE) requires a different source for these files. + + - HS-FS + +* tiboot3-am62px-hs-fs-evm.bin from step 3.1 +* tispl.bin, u-boot.img from step 3.2 + + - HS-SE + +*
[PATCH v3 11/13] Makefile: remove hardcoded device tree source directory
Some boards that choose to utilize the OF_UPSTREAM directory for their device tree files will need to specify that directory instead of the traditional arch/$(ARCH)/dts/* path. Include the correct path to the board's dtbs depending on if OF_UPSTREAM is selected or not. Reviewed-by: Sumit Garg Signed-off-by: Bryan Brattlof --- Makefile | 18 ++ scripts/Makefile.spl | 17 + 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 0f0c7f30d2717..51b57d26857f1 100644 --- a/Makefile +++ b/Makefile @@ -1184,6 +1184,16 @@ dt_binding_check: scripts_dtc quiet_cmd_copy = COPY$@ cmd_copy = cp $< $@ +ifeq ($(CONFIG_OF_UPSTREAM),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := dts/upstream/src/arm64 +else +dt_dir := dts/upstream/src/$(ARCH) +endif +else +dt_dir := arch/$(ARCH)/dts +endif + ifeq ($(CONFIG_MULTI_DTB_FIT),y) ifeq ($(CONFIG_MULTI_DTB_FIT_LZO),y) @@ -1209,7 +1219,7 @@ endif MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -a 0 -e 0 -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null + $(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -d /dev/null MKIMAGEFLAGS_fit-dtb.blob += -B 0x8 @@ -1407,9 +1417,9 @@ MKIMAGEFLAGS_u-boot.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ -p $(CONFIG_FIT_EXTERNAL_OFFSET) \ -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(DEVICE_TREE))) \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) + $(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(DEVICE_TREE))) \ + $(patsubst %,-b $(dt_dir)/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) \ + $(patsubst %,-b $(dt_dir)/%.dtbo,$(subst ",,$(CONFIG_OF_OVERLAY_LIST))) else MKIMAGEFLAGS_u-boot.img = -A $(ARCH) -T firmware -C none -O u-boot \ -a $(CONFIG_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 407fc52376a50..d074ba2350065 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -559,9 +559,15 @@ FORCE: $(obj)/dts/dt-$(SPL_NAME).dtb: dts/dt.dtb $(Q)$(MAKE) $(build)=$(obj)/dts spl_dtbs -PHONY += dts_dir -dts_dir: - $(shell [ -d $(obj)/dts ] || mkdir -p $(obj)/dts) +ifeq ($(CONFIG_OF_UPSTREAM),y) +ifeq ($(CONFIG_ARM64),y) +dt_dir := dts/upstream/src/arm64 +else +dt_dir := dts/upstream/src/$(ARCH) +endif +else +dt_dir := arch/$(ARCH)/dts +endif # Declare the contents of the .PHONY variable as phony. We keep that # information in a variable so we can use it in if_changed and friends. @@ -569,8 +575,11 @@ dts_dir: SPL_OF_LIST_TARGETS = $(patsubst %,dts/%.dtb,$(subst ",,$(CONFIG_SPL_OF_LIST))) SHRUNK_ARCH_DTB = $(addprefix $(obj)/,$(SPL_OF_LIST_TARGETS)) +$(dir $(SHRUNK_ARCH_DTB)): + $(shell [ -d $@ ] || mkdir -p $@) + .SECONDEXPANSION: -$(SHRUNK_ARCH_DTB): $$(patsubst $(obj)/dts/%, arch/$(ARCH)/dts/%, $$@) dts_dir +$(SHRUNK_ARCH_DTB): $$(patsubst $(obj)/dts/%, $(dt_dir)/%, $$@) $(dir $(SHRUNK_ARCH_DTB)) $(call if_changed,fdtgrep) targets += $(SPL_OF_LIST_TARGETS) -- 2.43.2
[PATCH v3 01/13] soc: add info to identify the am62p SoC family
Include the part number for TI's am62px family of SoCs so we can properly identify it during boot Reviewed-by: Igor Opaniuk Signed-off-by: Bryan Brattlof --- arch/arm/mach-k3/include/mach/hardware.h | 2 ++ drivers/soc/soc_ti_k3.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h index a1a9dfbde66c8..040288150b12f 100644 --- a/arch/arm/mach-k3/include/mach/hardware.h +++ b/arch/arm/mach-k3/include/mach/hardware.h @@ -46,6 +46,7 @@ #define JTAG_ID_PARTNO_J721S2 0xbb75 #define JTAG_ID_PARTNO_AM62X 0xbb7e #define JTAG_ID_PARTNO_AM62AX 0xbb8d +#define JTAG_ID_PARTNO_AM62PX 0xbb9d #define K3_SOC_ID(id, ID) \ static inline bool soc_is_##id(void) \ @@ -61,6 +62,7 @@ K3_SOC_ID(am64x, AM64X) K3_SOC_ID(j721s2, J721S2) K3_SOC_ID(am62x, AM62X) K3_SOC_ID(am62ax, AM62AX) +K3_SOC_ID(am62px, AM62PX) #define K3_SEC_MGR_SYS_STATUS 0x44234100 #define SYS_STATUS_DEV_TYPE_SHIFT 0 diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 355a5368dd45a..d7d0152b115fa 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -45,6 +45,9 @@ static const char *get_family_string(u32 idreg) case JTAG_ID_PARTNO_AM62AX: family = "AM62AX"; break; + case JTAG_ID_PARTNO_AM62PX: + family = "AM62PX"; + break; default: family = "Unknown Silicon"; }; -- 2.43.2
Re: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family
On 26/02/2024 17:43, Biju Das wrote: > > >> -Original Message- >> From: U-Boot On Behalf Of Paul Barker >> Sent: Monday, February 26, 2024 3:06 PM >> To: Marek Vasut ; Nobuhiro Iwamatsu >> >> Cc: Paul Barker ; u-boot@lists.denx.de >> Subject: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family >> >> This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC, >> also known as the RIIC module. >> >> This patch is based on both the u-boot driver in the Renesas RZ BSP >> 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit >> 0dd3ee311255). >> >> Support for deblocking the I2C bus is included as this may be needed after >> triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC >> asserts the reset line before the SoC completes the I2C write transaction >> with obvious bus locking effects). If the SDA line is observed to be low >> during initialisation, we automatically attempt to deblock. >> >> [1]: >> >> Signed-off-by: Paul Barker >> eviewed-by: Marek Vasut > > Typo. R is missing in the Rb tag. Good catch - I pasted it right in the first patch but messed it up here somehow. Hopefully Marek can fix this when applying if there's nothing else that needs changing. > > Also change log is missing. The changelog is in the cover letter [1]. [1]: https://lore.kernel.org/u-boot/20240226150536.1690-1-paul.barker...@bp.renesas.com/ Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 4/6] usb: kbd: Ignore Yubikeys
> Date: Sun, 25 Feb 2024 22:57:23 +0100
> From: Marek Vasut
>
> On 2/25/24 5:07 PM, Janne Grunau wrote:
> > Hej,
> >
> > On Wed, Feb 21, 2024, at 13:41, Marek Vasut wrote:
> >> On 2/21/24 08:25, Janne Grunau via B4 Relay wrote:
> >>> From: Hector Martin
> >>>
> >>> We currently only support one USB keyboard device, but some devices
> >>> emulate keyboards for other purposes. Most commonly, people run into
> >>> this with Yubikeys, so let's ignore those.
> >>>
> >>> Even if we end up supporting multiple keyboards in the future, it's
> >>> safer to ignore known non-keyboard devices.
> >>>
> >>> Signed-off-by: Hector Martin
> >>> ---
> >>>common/usb_kbd.c | 19 +++
> >>>1 file changed, 19 insertions(+)
> >>>
> >>> diff --git a/common/usb_kbd.c b/common/usb_kbd.c
> >>> index 4cbc9acb73..774d3555d9 100644
> >>> --- a/common/usb_kbd.c
> >>> +++ b/common/usb_kbd.c
> >>> @@ -120,6 +120,15 @@ struct usb_kbd_pdata {
> >>>
> >>>extern int __maybe_unused net_busy_flag;
> >>>
> >>> +/*
> >>> + * Since we only support one usbkbd device in the iomux,
> >>> + * ignore common keyboard-emulating devices that aren't
> >>> + * real keyboards.
> >>> + */
> >>> +const uint16_t vid_blocklist[] = {
> >>> + 0x1050, /* Yubico */
> >>> +};
> >>> +
> >>>/* The period of time between two calls of usb_kbd_testc(). */
> >>>static unsigned long kbd_testc_tms;
> >>>
> >>> @@ -465,6 +474,7 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
> >>> unsigned int ifnum)
> >>> struct usb_endpoint_descriptor *ep;
> >>> struct usb_kbd_pdata *data;
> >>> int epNum;
> >>> + int i;
> >>>
> >>> if (dev->descriptor.bNumConfigurations != 1)
> >>> return 0;
> >>> @@ -480,6 +490,15 @@ static int usb_kbd_probe_dev(struct usb_device *dev,
> >>> unsigned int ifnum)
> >>> if (iface->desc.bInterfaceProtocol != USB_PROT_HID_KEYBOARD)
> >>> return 0;
> >>>
> >>> + for (i = 0; i < ARRAY_SIZE(vid_blocklist); i++) {
> >>> + if (dev->descriptor.idVendor == vid_blocklist[i]) {
> >>> + printf("Ignoring keyboard device 0x%x:0x%x\n",
> >>> +dev->descriptor.idVendor,
> >>> +dev->descriptor.idProduct);
> >>> + return 0;
> >>> + }
> >>> + }
> >>
> >> I vaguely recall a discussion about previous version of this, I think
> >> the suggestion was to make the list of ignored devices configurable via
> >> environment variable, so users can add to that list from U-Boot shell.
> >> Would it be possible to make it work this way ?
> >
> > oh, I completely forgot that this patch was already submitted. I briefly
> > looked through asahi tree for related patches and did not check whether
> > this was previously submitted.
> > I've added environment based blocking as separate patch with blocking
> > either complete vendor IDs or vendor, product ID combinations. A separate
> > patch to simplify authorship tracking and the implementation doesn't share
> > any code.
>
> It would be better to have only one patch which does not hard-code any
> USB IDs, and then add those blocked IDs via U-Boot default environment
> for this specific machine. We cannot predict what yubico will do in the
> future, whether they might make a device that shouldn't be blocked for
> example. If they do, the user should be able to unblock their device by
> running e.g. '=> setenv usb_blocklist' instead of updating their bootloader.
>
> I think a simple list of blocked VID:PID pairs, maybe with wildcards,
> would be nice, i.e. something like 'usb_blocklist=1234:5678,1050:*' to
> block device 0x1234:0x5678 and all devices with VID 0x1050 . That should
> be easy to parse with strtok()/strtol() or some such and the code should
> not be too complex.
I do like the idea of having a configurable list of usb devices to
ignore. The U-Boot USB stack is still not perfect and there are still
USB devices that will prevent us from booting when connected. The
list will provide a nice workaround for that issue.
But the yubikeys will cause the same problem on other boards as well.
So I think it makes sense to put those in a default list.
Re: [PATCH 2/6] usb: xhci: Set up endpoints for the first 2 interfaces
> Date: Sun, 25 Feb 2024 22:47:41 +0100 > From: Marek Vasut > > On 2/25/24 4:28 PM, Janne Grunau wrote: > > > > > > On Wed, Feb 21, 2024, at 13:39, Marek Vasut wrote: > >> On 2/21/24 08:25, Janne Grunau via B4 Relay wrote: > >>> From: Janne Grunau > >>> > >>> Apple USB keyboards carry the HID keyboard boot protocol on the second > >>> interface. Using the second interface in the USB keyboard driver does > >>> not work since the xhci has not allocated a transfer ring. > >> > >> So, what does this patch do ? That is not clear from the commit message. > > > > rewritten for v2: > > | usb: xhci: Set up endpoints for the first 2 interfaces > > | > > | The xhci driver currently only does the necessary initialization for > > | endpoints found in the first interface descriptor. Apple USB keyboards > > | (released 2021) use the second interface descriptor for the HID keyboard > > | boot protocol. To allow USB drivers to use endpoints from other > > | interface descriptors the xhci driver needs to ensure these endpoints > > | are initialized as well. > > | Use USB_MAX_ACTIVE_INTERFACES to control how many interface descriptors > > | are initialized and useable. Currently defined to 2 as that is enough to > > | make the Apple keyboard usable. > > Would it make sense to make this a tunable Kconfig option ? Maybe, but it should probably be enabled everywhere where CONFIG_USB_KEYBOARD as folks will connect their Apple keyboard to non-Apple hardware as well. And I think someone mentioned on the #asahi irc channel that there are othe keyboards that have the boot protocol on the second interface descriptor. Cheers, Mark
Re: [PATCH] efi_loader: Don't carve out memory reservations too early
> Date: Sat, 17 Feb 2024 12:02:56 +0100
> From: Heinrich Schuchardt
Hi Heinrich,
> On 2/16/24 3:17 PM, Mark Kettenis wrote:
> >> Date: Fri, 16 Feb 2024 00:38:25 +0100
> >> From: Heinrich Schuchardt
> >>
> >> Am 16. Februar 2024 00:25:34 MEZ schrieb Mark Kettenis
> >> :
> >>> Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b2d
> >>> ("efi_loader: create memory reservations in ACPI case")
> >>> broke boards that create additional memory reservations in
> >>> ft_board_setup() since it is now called before those additional
> >>> memory reservations are made. This is the case for the rk3588
> >>> boards and breaks booting OpenBSD on those boards.
> >>>
> >>> Move the call back to its original location and add a call in
> >>> the code path used for ACPI.
> >>>
> >>> Fixes: 1be415b21b2d ("efi_loader: create memory reservations in ACPI
> >>> case")
> >>> Signed-off-by: Mark Kettenis
> >>> ---
> >>> lib/efi_loader/efi_helper.c | 11 +++
> >>> 1 file changed, 7 insertions(+), 4 deletions(-)
> >>>
> >>> diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
> >>> index 5dd9cc876e..58761fae78 100644
> >>> --- a/lib/efi_loader/efi_helper.c
> >>> +++ b/lib/efi_loader/efi_helper.c
> >>> @@ -456,11 +456,11 @@ efi_status_t efi_install_fdt(void *fdt)
> >>> return EFI_LOAD_ERROR;
> >>> }
> >>>
> >>> - /* Create memory reservations as indicated by the device tree */
> >>> - efi_carve_out_dt_rsv(fdt);
> >>> -
> >>> - if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
> >>> + if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) {
> >>> + /* Create memory reservations as indicated by the device tree */
> >>
> >> Imagine booting the rk3588 board with ACPI.
> >
> > I'd rather not, thank you ;)
> >
> >> Wouldn't we miss creating the ft_board_setup() reservations before
> >> efi_carve_out_dt_rsv(fdt)?
> >
> > Yes. And arguably the these memory reservations should be made way
> > earlier, at the the time that efi_memory_init() runs. I think we're
> > just lucky that efi_allocate_pages() doesn't hand us memory from these
> > areas in copy_fdt().
> >
> > Better ideas?
> >
>
> image_setup_libfdt(, fdt, NULL) must be called before
> efi_carve_out_dt_rsv().
>
> Could you, please, add this call in this path, too. Otherwise the patch
> looks correct.
Yes I can. Just sent out v2.
Thanks,
Mark
> >
> >>> + efi_carve_out_dt_rsv(fdt);
> >>> return EFI_SUCCESS;
> >>> + }
> >>>
> >>> /* Prepare device tree for payload */
> >>> ret = copy_fdt();
> >>> @@ -474,6 +474,9 @@ efi_status_t efi_install_fdt(void *fdt)
> >>> return EFI_LOAD_ERROR;
> >>> }
> >>>
> >>> + /* Create memory reservations as indicated by the device tree */
> >>> + efi_carve_out_dt_rsv(fdt);
> >>> +
> >>> efi_try_purge_kaslr_seed(fdt);
> >>>
> >>> if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
> >>
> >
>
>
[PATCH v2] efi_loader: Don't carve out memory reservations too early
Moving the efi_carve_out_dt_rsv() call in commit 1be415b21b2d
("efi_loader: create memory reservations in ACPI case")
broke boards that create additional memory reservations in
ft_board_setup() since it is now called before those additional
memory reservations are made. This is the case for the rk3588
boards and breaks booting OpenBSD on those boards.
Move the call back to its original location and add a call in
the code path used for ACPI after calling image_setup_libfdt()
such that memory reservations made by ft_board_setup() are
applied when booting with ACPI too.
Fixes: 1be415b21b2d ("efi_loader: create memory reservations in ACPI case")
Signed-off-by: Mark Kettenis
---
ChangeLog:
v2: - Call image_setup_libfdt() in the ACPI code path
lib/efi_loader/efi_helper.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/lib/efi_loader/efi_helper.c b/lib/efi_loader/efi_helper.c
index 5dd9cc876e..5f8d9a17fd 100644
--- a/lib/efi_loader/efi_helper.c
+++ b/lib/efi_loader/efi_helper.c
@@ -456,11 +456,16 @@ efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
- /* Create memory reservations as indicated by the device tree */
- efi_carve_out_dt_rsv(fdt);
+ if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE)) {
+ if (image_setup_libfdt(, fdt, NULL)) {
+ log_err("ERROR: failed to process device tree\n");
+ return EFI_LOAD_ERROR;
+ }
- if (CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE))
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
return EFI_SUCCESS;
+ }
/* Prepare device tree for payload */
ret = copy_fdt();
@@ -474,6 +479,9 @@ efi_status_t efi_install_fdt(void *fdt)
return EFI_LOAD_ERROR;
}
+ /* Create memory reservations as indicated by the device tree */
+ efi_carve_out_dt_rsv(fdt);
+
efi_try_purge_kaslr_seed(fdt);
if (CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL_MEASURE_DTB)) {
--
2.43.0
[PATCH v4] cmd: add FDT setup for bootelf by flag
From: Maxim Moskalets
Added the ability to use FDT for ELF applications, required to run some
OS. To make FDT setup, you need to set the -d fdt_addr_r cmd option for
bootelf command.
Signed-off-by: Maxim Moskalets
Cc: Tom Rini
---
cmd/elf.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/cmd/elf.c b/cmd/elf.c
index b7b9f506a5..2fa28448c0 100644
--- a/cmd/elf.c
+++ b/cmd/elf.c
@@ -38,6 +38,8 @@ static unsigned long do_bootelf_exec(ulong (*entry)(int, char
* const[]),
/* Interpreter command to boot an arbitrary ELF image from memory */
int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
+ struct bootm_headers img = {0};
+ unsigned long fdt_addr = 0; /* Address of the FDT */
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
char *sload = NULL;
@@ -46,13 +48,23 @@ int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
/* Consume 'bootelf' */
argc--; argv++;
- /* Check for flag. */
+ /* Check for [-p|-s] flag. */
if (argc >= 1 && (argv[0][0] == '-' && \
(argv[0][1] == 'p' || argv[0][1] == 's'))) {
sload = argv[0];
/* Consume flag. */
argc--; argv++;
}
+
+ /* Check for [-d fdt_addr_r] option. */
+ if ((argc >= 2) && (argv[0][0] == '-') && (argv[0][1] == 'd')) {
+ if (strict_strtoul(argv[1], 16, _addr) != 0)
+ return CMD_RET_USAGE;
+ /* Consume option. */
+ argc -= 2;
+ argv += 2;
+ }
+
/* Check for address. */
if (argc >= 1 && strict_strtoul(argv[0], 16, ) != -EINVAL) {
/* Consume address */
@@ -68,6 +80,14 @@ int do_bootelf(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
else
addr = load_elf_image_shdr(addr);
+ if (fdt_addr) {
+ printf("## Setting up FDT at 0x%08lx ...\n", fdt_addr);
+ flush();
+
+ if (image_setup_libfdt(, (void *)fdt_addr, NULL))
+ return 1;
+ }
+
if (!env_get_autostart())
return rcode;
@@ -298,9 +318,10 @@ int do_bootvx(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
U_BOOT_CMD(
bootelf, CONFIG_SYS_MAXARGS, 0, do_bootelf,
"Boot from an ELF image in memory",
- "[-p|-s] [address]\n"
+ "[-p|-s] [-d fdt_addr_r] [address]\n"
"\t- load ELF image at [address] via program headers (-p)\n"
- "\t or via section headers (-s)"
+ "\t or via section headers (-s)\n"
+ "\t- setup FDT image at [fdt_addr_r] (-d)"
);
U_BOOT_CMD(
--
2.39.2
Re: [PATCH 1/1] serial: move sbi_dbcn_available to .data section
On 2024-02-26 17:32, Heinrich Schuchardt wrote:
> U-Boot SPL loads the device-tree directly behind main U-Boot overlapping
> the .bss section. reserve_fdt() is called in board_init_f() to relocate the
> device-tree to a safe location.
>
> Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in
> the .bss section the device-tree is corrupted when _debug_uart_init() is
> called in the SBI serial driver. Move the variable to the .data section.
>
> Link: https://bugs.launchpad.net/ubuntu/+source/u-boot/+bug/2054091
> Fixes: dfe08374943c ("risc-v: implement DBCN based debug console")
> Signed-off-by: Heinrich Schuchardt
> ---
> drivers/serial/serial_sbi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c
> index a51a96c1ef0..f3ecfccab43 100644
> --- a/drivers/serial/serial_sbi.c
> +++ b/drivers/serial/serial_sbi.c
> @@ -17,7 +17,7 @@ static inline void _debug_uart_putc(int c)
>
> #else
>
> -static int sbi_dbcn_available;
> +static int sbi_dbcn_available __section(".data");
>
> static inline void _debug_uart_init(void)
> {
Tested-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://aurel32.net
[PATCH 2/2] tools: imx9_image: Reword warning message.
If the optional `tee.bin` OP-TEE binary is missing, the image will still be functional. Adapt the warning message accordingly. Signed-off-by: Mathieu Othacehe --- tools/imx9_image.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/imx9_image.sh b/tools/imx9_image.sh index 88dfcfe606c..ca78a57a19a 100755 --- a/tools/imx9_image.sh +++ b/tools/imx9_image.sh @@ -19,7 +19,7 @@ for f in $blobs; do fi if [ ! -f $tmp ]; then - echo "WARNING '$tmp' not found, resulting binary is not-functional" >&2 + echo "WARNING '$tmp' not found, resulting binary may be not-functional" >&2 # Comment-out the lines for un-existing files. This way, # mkimage can keep working. This allows CI tests to pass even -- 2.41.0
[PATCH 1/2] imx9: Fix OP-TEE support
This fixes OP-TEE support by:
- Adding tee.bin to container.cfg
- Starting ELE RNG in SPL
Signed-off-by: Mathieu Othacehe
---
arch/arm/mach-imx/imx9/container.cfg | 3 ++-
board/freescale/imx93_evk/spl.c | 7 +++
board/phytec/phycore_imx93/spl.c | 7 +++
board/variscite/imx93_var_som/spl.c | 6 ++
4 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/container.cfg
b/arch/arm/mach-imx/imx9/container.cfg
index f268bc9eb2c..72fe791eae6 100644
--- a/arch/arm/mach-imx/imx9/container.cfg
+++ b/arch/arm/mach-imx/imx9/container.cfg
@@ -7,4 +7,5 @@ BOOT_FROM SD 0x400
SOC_TYPE IMX9
CONTAINER
IMAGE A55 bl31.bin 0x204E
-IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
\ No newline at end of file
+IMAGE A55 u-boot.bin CONFIG_TEXT_BASE
+IMAGE A55 tee.bin 0x9600
\ No newline at end of file
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index a98ed69db88..2fd5559195e 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -43,6 +44,12 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
void spl_board_init(void)
{
+ int ret;
+
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+
puts("Normal Boot\n");
}
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index dabc5316f33..16303fc187a 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -34,6 +35,12 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
void spl_board_init(void)
{
+ int ret;
+
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+
puts("Normal Boot\n");
}
diff --git a/board/variscite/imx93_var_som/spl.c
b/board/variscite/imx93_var_som/spl.c
index e6db4eb562b..36e17219d63 100644
--- a/board/variscite/imx93_var_som/spl.c
+++ b/board/variscite/imx93_var_som/spl.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -47,9 +48,14 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
void spl_board_init(void)
{
struct var_eeprom *ep = VAR_EEPROM_DATA;
+ int ret;
puts("Normal Boot\n");
+ ret = ele_start_rng();
+ if (ret)
+ printf("Fail to start RNG: %d\n", ret);
+
/* Copy EEPROM contents to DRAM */
memcpy(ep, , sizeof(*ep));
}
--
2.41.0
[PATCH 0/2] Fix OP-TEE support
Hello, This series fixes OP-TEE support on all imx9 boards by starting the ELE RNG and adding the optional tee.bin binary to the ATF container. Thanks, Mathieu Mathieu Othacehe (2): imx9: Fix OP-TEE support tools: imx9_image: Reword warning message. arch/arm/mach-imx/imx9/container.cfg | 3 ++- board/freescale/imx93_evk/spl.c | 7 +++ board/phytec/phycore_imx93/spl.c | 7 +++ board/variscite/imx93_var_som/spl.c | 6 ++ tools/imx9_image.sh | 2 +- 5 files changed, 23 insertions(+), 2 deletions(-) -- 2.41.0
[PATCH v5 36/39] dts: msm8996: replace with upstream DTS
Drop the U-Boot specific dragonboard820c.dts file in favour of the
upstream apq8096-db820c.dts and an additional -u-boot.dtsi with the
U-Boot specific additions.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/Makefile |2 +-
arch/arm/dts/apq8096-db820c-u-boot.dtsi | 14 +
arch/arm/dts/apq8096-db820c.dts | 1137 +
arch/arm/dts/dragonboard820c-uboot.dtsi | 32 -
arch/arm/dts/dragonboard820c.dts| 153 --
arch/arm/dts/msm8996.dtsi | 3884 +++
configs/dragonboard820c_defconfig |2 +-
7 files changed, 5037 insertions(+), 187 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c2bc6296ead0..0193833845f3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -632,9 +632,9 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
- dragonboard820c.dtb \
+ apq8096-db820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
qcs404-evb.dtb
diff --git a/arch/arm/dts/apq8096-db820c-u-boot.dtsi
b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
new file mode 100644
index ..be61ea262b90
--- /dev/null
+++ b/arch/arm/dts/apq8096-db820c-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/ {
+ /* Ensure that the fdtfile variable is generated properly */
+ compatible = "qcom,apq8096-db820c", "qcom,apq8096";
+};
+
+ {
+ status = "okay";
+ clock-frequency = <1>;
+};
diff --git a/arch/arm/dts/apq8096-db820c.dts b/arch/arm/dts/apq8096-db820c.dts
new file mode 100644
index ..e8148b3d6c50
--- /dev/null
+++ b/arch/arm/dts/apq8096-db820c.dts
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "msm8996.dtsi"
+#include "pm8994.dtsi"
+#include "pmi8994.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/*
+ * GPIO name legend: proper name = the GPIO line is used as GPIO
+ * NC = not connected (pin out but not routed from the chip to
+ * anything the board)
+ * "[PER]" = pin is muxed for [peripheral] (not GPIO)
+ * LSEC= Low Speed External Connector
+ * P HSEC = Primary High Speed External Connector
+ * S HSEC = Secondary High Speed External Connector
+ * J14 = Camera Connector
+ * TP = Test Points
+ *
+ * Line names are taken from the schematic "DragonBoard 820c",
+ * drawing no: LM25-P2751-1
+ *
+ * For the lines routed to the external connectors the
+ * lines are named after the 96Boards CE Specification 1.0,
+ * Appendix "Expansion Connector Signal Description".
+ *
+ * When the 96Board naming of a line and the schematic name of
+ * the same line are in conflict, the 96Board specification
+ * takes precedence, which means that the external UART on the
+ * LSEC is named UART0 while the schematic and SoC names this
+ * UART3. This is only for the informational lines i.e. "[FOO]",
+ * the GPIO named lines "GPIO-A" thru "GPIO-L" are the only
+ * ones actually used for GPIO.
+ */
+
+/ {
+ model = "Qualcomm Technologies, Inc. DB820c";
+ compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
+
+ aliases {
+ serial0 = _uart2;
+ serial1 = _uart3;
+ serial2 = _uart2;
+ i2c0 = _i2c3;
+ i2c1 = _i2c1;
+ i2c2 = _i2c1;
+ spi0 = _spi1;
+ spi1 = _spi6;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ div1_mclk: divclk1 {
+ compatible = "gpio-gate-clock";
+ pinctrl-0 = <_mclk>;
+ pinctrl-names = "default";
+ clocks = < RPM_SMD_DIV_CLK1>;
+ #clock-cells = <0>;
+ enable-gpios = <_gpios 15 0>;
+ };
+
+ divclk4: divclk4 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "divclk4";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_pin_a>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_up_gpio>;
+
+ button {
+ label = "Volume Up";
+ linux,code = ;
+ gpios = <_gpios 2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ usb2_id: usb2-id {
+ compatible = "linux,extcon-usb-gpio";
+
RE: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family
> -Original Message- > From: U-Boot On Behalf Of Paul Barker > Sent: Monday, February 26, 2024 3:06 PM > To: Marek Vasut ; Nobuhiro Iwamatsu > > Cc: Paul Barker ; u-boot@lists.denx.de > Subject: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family > > This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC, > also known as the RIIC module. > > This patch is based on both the u-boot driver in the Renesas RZ BSP > 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit > 0dd3ee311255). > > Support for deblocking the I2C bus is included as this may be needed after > triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC > asserts the reset line before the SoC completes the I2C write transaction > with obvious bus locking effects). If the SDA line is observed to be low > during initialisation, we automatically attempt to deblock. > > [1]: > > Signed-off-by: Paul Barker > eviewed-by: Marek Vasut Typo. R is missing in the Rb tag. Also change log is missing. > --- > arch/arm/mach-rmobile/Kconfig | 1 + > configs/renesas_rzg2l_smarc_defconfig | 2 + > drivers/i2c/Kconfig | 7 + > drivers/i2c/Makefile | 1 + > drivers/i2c/rz_riic.c | 624 ++ > 5 files changed, 635 insertions(+) > create mode 100644 drivers/i2c/rz_riic.c > > diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig > index 2bb96749fc0d..38ede6e0b5b5 100644 > --- a/arch/arm/mach-rmobile/Kconfig > +++ b/arch/arm/mach-rmobile/Kconfig > @@ -78,6 +78,7 @@ config RZG2L > imply RENESAS_SDHI > imply RZG2L_GPIO > imply SCIF_CONSOLE > + imply SYS_I2C_RZ_RIIC > imply SYS_MALLOC_F > help > Enable support for the Renesas RZ/G2L family of SoCs. Currently > diff --git a/configs/renesas_rzg2l_smarc_defconfig > b/configs/renesas_rzg2l_smarc_defconfig > index e45579ae6b98..ad46297c6619 100644 > --- a/configs/renesas_rzg2l_smarc_defconfig > +++ b/configs/renesas_rzg2l_smarc_defconfig > @@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y > CONFIG_SYS_MAXARGS=64 > CONFIG_CMD_CLK=y > CONFIG_CMD_GPIO=y > +CONFIG_CMD_I2C=y > CONFIG_CMD_MMC=y > CONFIG_CMD_PART=y > CONFIG_CMD_EXT2=y > @@ -44,6 +45,7 @@ CONFIG_CLK=y > CONFIG_CLK_RENESAS=y > # CONFIG_CLK_RCAR_GEN3 is not set > CONFIG_GPIO_HOG=y > +CONFIG_DM_I2C=y > CONFIG_MMC_IO_VOLTAGE=y > CONFIG_MMC_UHS_SUPPORT=y > CONFIG_MMC_HS400_SUPPORT=y > diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index > 4f42200f3923..d2a3a13493aa 100644 > --- a/drivers/i2c/Kconfig > +++ b/drivers/i2c/Kconfig > @@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP > have several I2C ports and all are provided, controlled by the > device tree. > > +config SYS_I2C_RZ_RIIC > + bool "Renesas RZ/G2L RIIC driver" > + depends on RZG2L && DM_I2C > + help > + Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC > + family. > + > config SYS_I2C_SANDBOX > bool "Sandbox I2C driver" > depends on SANDBOX && DM_I2C > diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index > a96a8c7e955e..692f63bafd02 100644 > --- a/drivers/i2c/Makefile > +++ b/drivers/i2c/Makefile > @@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o > obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o > obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o > obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o > +obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o > obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o > obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o > obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o > diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c new file mode > 100644 index ..5f3f8d1b24b7 > --- /dev/null > +++ b/drivers/i2c/rz_riic.c > @@ -0,0 +1,624 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * RZ/G2L I2C (RIIC) driver > + * > + * Copyright (C) 2021-2023 Renesas Electronics Corp. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define RIIC_ICCR1 0x00 > +#define RIIC_ICCR2 0x04 > +#define RIIC_ICMR1 0x08 > +#define RIIC_ICMR2 0x0c > +#define RIIC_ICMR3 0x10 > +#define RIIC_ICFER 0x14 > +#define RIIC_ICSER 0x18 > +#define RIIC_ICIER 0x1c > +#define RIIC_ICSR1 0x20 > +#define RIIC_ICSR2 0x24 > +#define RIIC_ICSAR0 0x28 > +#define RIIC_ICBRL 0x34 > +#define RIIC_ICBRH 0x38 > +#define RIIC_ICDRT 0x3c > +#define RIIC_ICDRR 0x40 > + > +/* ICCR1 */ > +#define ICCR1_ICEBIT(7) > +#define ICCR1_IICRST BIT(6) > +#define ICCR1_CLOBIT(5) > +#define ICCR1_SOWP BIT(4) > +#define ICCR1_SCLO BIT(3) > +#define ICCR1_SDAO BIT(2) > +#define ICCR1_SCLI BIT(1) > +#define ICCR1_SDAI BIT(0) > + > +/* ICCR2 */ > +#define ICCR2_BBSY BIT(7) > +#define ICCR2_MSTBIT(6) > +#define ICCR2_TRSBIT(5) > +#define ICCR2_SP
[PATCH v5 38/39] dts: qcs404-evb: replace with upstream DT
Drop the U-Boot specific DTS in favour of upstream. We'll only include
the -4000 variant as that is what U-Boot already supported.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/Makefile|2 +-
arch/arm/dts/pms405.dtsi | 149 +++
arch/arm/dts/qcs404-evb-4000-u-boot.dtsi | 48 +
arch/arm/dts/qcs404-evb-4000.dts | 96 ++
arch/arm/dts/qcs404-evb-uboot.dtsi | 30 -
arch/arm/dts/qcs404-evb.dts | 390 ---
arch/arm/dts/qcs404-evb.dtsi | 389 +++
arch/arm/dts/qcs404.dtsi | 1829 ++
8 files changed, 2512 insertions(+), 421 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0193833845f3..cab3bb832dbc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -635,9 +635,9 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
apq8096-db820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
- qcs404-evb.dtb
+ qcs404-evb-4000.dtb
dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \
diff --git a/arch/arm/dts/pms405.dtsi b/arch/arm/dts/pms405.dtsi
new file mode 100644
index ..461ad97032f7
--- /dev/null
+++ b/arch/arm/dts/pms405.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ thermal-zones {
+ pms405-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <_temp>;
+
+ trips {
+ pms405_alert0: pms405-alert0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pms405_crit: pms405-crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+_bus {
+ pms405_0: pms405@0 {
+ compatible = "qcom,pms405", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pms405_gpios: gpio@c000 {
+ compatible = "qcom,pms405-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <_gpios 0 0 12>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pon@800 {
+ compatible = "qcom,pms405-pon";
+ reg = <0x0800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = ;
+ };
+ };
+
+ pms405_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pms405_adc: adc@3100 {
+ compatible = "qcom,pms405-adc", "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@0 {
+ reg = ;
+ qcom,pre-scaling = <1 1>;
+ label = "ref_gnd";
+ };
+
+ channel@1 {
+ reg = ;
+ qcom,pre-scaling = <1 1>;
+ label = "vref_1p25";
+ };
+
+ channel@131 {
+ reg = ;
+
[PATCH v5 39/39] MAINTAINERS: Qualcomm: add some missing paths
Add drivers and DTS files, as well as regex matches for qcom/qualcomm/snapdragon. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- MAINTAINERS | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 0b08ca192397..22e807d36b6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -602,20 +602,24 @@ ARM SNAPDRAGON M: Caleb Connolly M: Neil Armstrong R: Sumit Garg S: Maintained -F: arch/arm/mach-snapdragon/ -F: drivers/button/button-qcom-pmic.c -F: drivers/clk/qcom/ +F: arch/arm/dts/msm8*.dtsi +F: arch/arm/dts/pm8???.dtsi +F: arch/arm/dts/pms405.dtsi +F: arch/arm/dts/sdm845.dtsi +F: drivers/*/*/pm8???-* F: drivers/gpio/msm_gpio.c F: drivers/mmc/msm_sdhci.c F: drivers/phy/msm8916-usbh-phy.c -F: drivers/pinctrl/qcom/ F: drivers/serial/serial_msm.c F: drivers/serial/serial_msm_geni.c F: drivers/smem/msm_smem.c F: drivers/spmi/spmi-msm.c F: drivers/usb/host/ehci-msm.c +N: qcom +N: snapdragon +N: qualcomm ARM STI M: Patrice Chotard S: Maintained -- 2.43.1
[PATCH v5 37/39] dt-bindings: import headers for qcs404
Import the headers needed for QCS404-evb. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- include/dt-bindings/clock/qcom,turingcc-qcs404.h | 15 +++ 1 file changed, 15 insertions(+) diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h new file mode 100644 index ..838faef57c67 --- /dev/null +++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Linaro Ltd + */ + +#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H +#define _DT_BINDINGS_CLK_TURING_QCS404_H + +#define TURING_Q6SS_Q6_AXIM_CLK0 +#define TURING_Q6SS_AHBM_AON_CLK 1 +#define TURING_WRAPPER_AON_CLK 2 +#define TURING_Q6SS_AHBS_AON_CLK 3 +#define TURING_WRAPPER_QOS_AHBS_AON_CLK4 + +#endif -- 2.43.1
[PATCH v5 35/39] dts: dragonboard820c: use correct bindings for clocks
Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be
compatible with upstream.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard820c.dts | 5 +++--
drivers/clk/qcom/clock-apq8096.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 86b7f83d36d6..282c37e28f42 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -7,8 +7,9 @@
/dts-v1/;
#include "skeleton64.dtsi"
+#include
/ {
model = "Qualcomm Technologies, Inc. DB820c";
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
@@ -77,9 +78,9 @@
blsp2_uart2: serial@75b {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b 0x1000>;
- clocks = < 4>;
+ clocks = < GCC_BLSP2_UART2_APPS_CLK>;
clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <_uart>;
};
@@ -88,9 +89,9 @@
compatible = "qcom,sdhci-msm-v4";
reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
index = <0x0>;
bus-width = <4>;
- clock = < 0>;
+ clock = < GCC_SDCC1_APPS_CLK>;
clock-frequency = <2>;
};
spmi_bus: spmi@400f000 {
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index 1e6fdb5cd42d..a4731613c5e0 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -12,8 +12,9 @@
#include
#include
#include
#include
+#include
#include "clock-qcom.h"
/* Clocks: (from CLK_CTL_BASE) */
@@ -106,12 +107,12 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong
rate)
{
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
- case 0: /* SDC1 */
+ case GCC_SDCC1_APPS_CLK: /* SDC1 */
return clk_init_sdc(priv, rate);
break;
- case 4: /*UART2*/
+ case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/
return clk_init_uart(priv);
default:
return 0;
}
--
2.43.1
[PATCH v5 34/39] dts: msm8996: import PMIC dtsi files
Import PM8994 and PMI8994 DTSI files in preparation for switching
MSM8996 boards to upstream DTS.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/pm8994.dtsi | 152 ++
arch/arm/dts/pmi8994.dtsi | 65
2 files changed, 217 insertions(+)
diff --git a/arch/arm/dts/pm8994.dtsi b/arch/arm/dts/pm8994.dtsi
new file mode 100644
index ..d44a95caf04a
--- /dev/null
+++ b/arch/arm/dts/pm8994.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+
+/ {
+ thermal-zones {
+ pm8994-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <_temp>;
+
+ trips {
+ pm8994_alert0: pm8994-alert0 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pm8994_crit: pm8994-crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+_bus {
+
+ pmic@0 {
+ compatible = "qcom,pm8994", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pm8994_pon: pon@800 {
+ compatible = "qcom,pm8916-pon";
+ reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = ;
+ };
+
+ pm8994_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
+ };
+
+ pm8994_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <_vadc VADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8994_vadc: adc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@7 {
+ reg = ;
+ qcom,pre-scaling = <1 3>;
+ label = "vph_pwr";
+ };
+ channel@8 {
+ reg = ;
+ label = "die_temp";
+ };
+ channel@9 {
+ reg = ;
+ label = "ref_625mv";
+ };
+ channel@a {
+ reg = ;
+ label = "ref_1250mv";
+ };
+ channel@e {
+ reg = ;
+ };
+ channel@f {
+ reg = ;
+ };
+ };
+
+ pm8994_gpios: gpio@c000 {
+ compatible = "qcom,pm8994-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <_gpios 0 0 22>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+
[PATCH v5 32/39] dts: msm8916: replace with upstream DTS
Drop the U-Boot specific dragonboard410c.dts in favour of the upstream
msm8916-sbc.dts. No additional changes are needed to this DTS for U-Boot
support.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/Makefile |2 +-
arch/arm/dts/apq8016-sbc-u-boot.dtsi| 20 +
arch/arm/dts/apq8016-sbc.dts| 729 +
arch/arm/dts/dragonboard410c-uboot.dtsi | 44 -
arch/arm/dts/dragonboard410c.dts| 221 ---
arch/arm/dts/msm8916.dtsi | 2702 +++
configs/dragonboard410c_defconfig |2 +-
7 files changed, 3453 insertions(+), 267 deletions(-)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 38d9c6f0855d..c2bc6296ead0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -631,9 +631,9 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \
fsl-ls1028a-kontron-sl28-var4.dtb \
dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
-dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \
+dtb-$(CONFIG_ARCH_SNAPDRAGON) += apq8016-sbc.dtb \
dragonboard820c.dtb \
sdm845-db845c.dtb \
sdm845-samsung-starqltechn.dtb \
qcs404-evb.dtb
diff --git a/arch/arm/dts/apq8016-sbc-u-boot.dtsi
b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
new file mode 100644
index ..585d54d29623
--- /dev/null
+++ b/arch/arm/dts/apq8016-sbc-u-boot.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024, Linaro Ltd.
+ */
+
+/ {
+ /* When running as a first-stage bootloader this isn't filled in
automatically */
+ memory@8000 {
+ reg = <0 0x8000 0 0x3da0>;
+ };
+};
+
+/*
+ * When running as a first-stage bootloader, we need to re-configure the UART
pins
+ * because SBL de-initialises them. Indicate that the UART pins should be
configured
+ * during all boot stages.
+ */
+_uart2_default {
+ bootph-all;
+};
diff --git a/arch/arm/dts/apq8016-sbc.dts b/arch/arm/dts/apq8016-sbc.dts
new file mode 100644
index ..9ffad7d1f2b6
--- /dev/null
+++ b/arch/arm/dts/apq8016-sbc.dts
@@ -0,0 +1,729 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "msm8916-pm8916.dtsi"
+#include
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ model = "Qualcomm Technologies, Inc. APQ 8016 SBC";
+ compatible = "qcom,apq8016-sbc", "qcom,apq8016";
+
+ aliases {
+ mmc0 = _1; /* eMMC */
+ mmc1 = _2; /* SD card */
+ serial0 = _uart2;
+ serial1 = _uart1;
+ usid0 = _0;
+ i2c0 = _i2c2;
+ i2c1 = _i2c6;
+ i2c3 = _i2c4;
+ spi0 = _spi5;
+ spi1 = _spi3;
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ reserved-memory {
+ ramoops@bff0 {
+ compatible = "ramoops";
+ reg = <0x0 0xbff0 0x0 0x10>;
+
+ record-size = <0x2>;
+ console-size = <0x2>;
+ ftrace-size = <0x2>;
+ };
+ };
+
+ usb2513 {
+ compatible = "smsc,usb3503";
+ reset-gpios = <_gpios 3 GPIO_ACTIVE_LOW>;
+ initial-mode = <1>;
+ };
+
+ usb_id: usb-id {
+ compatible = "linux,extcon-usb-gpio";
+ id-gpios = < 121 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_id_default>;
+ };
+
+ hdmi-out {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con: endpoint {
+ remote-endpoint = <_out>;
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <_key_volp_n_default>;
+
+ button {
+ label = "Volume Up";
+ linux,code = ;
+ gpios = < 107 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <_leds>,
+ <_gpios_leds>,
+ <_mpps_leds>;
+
+ compatible = "gpio-leds";
+
+ led@1 {
+ label = "apq8016-sbc:green:user1";
+ function = LED_FUNCTION_HEARTBEAT;
+ color = ;
+ gpios = < 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+
[PATCH v5 33/39] dt-bindings: import headers for MSM8996
Import dt-binding headers for MSM8996/APQ8096 from Linux. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- include/dt-bindings/clock/qcom,gcc-msm8996.h | 362 + include/dt-bindings/clock/qcom,mmcc-msm8996.h | 295 + .../dt-bindings/interconnect/qcom,msm8996-cbf.h| 12 + include/dt-bindings/interconnect/qcom,msm8996.h| 163 ++ include/dt-bindings/sound/qcom,wcd9335.h | 15 + 5 files changed, 847 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-msm8996.h b/include/dt-bindings/clock/qcom,gcc-msm8996.h new file mode 100644 index ..ddfd6fd73081 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8996.h @@ -0,0 +1,362 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MSM_GCC_8996_H +#define _DT_BINDINGS_CLK_MSM_GCC_8996_H + +#define GPLL0_EARLY0 +#define GPLL0 1 +#define GPLL1_EARLY2 +#define GPLL1 3 +#define GPLL2_EARLY4 +#define GPLL2 5 +#define GPLL3_EARLY6 +#define GPLL3 7 +#define GPLL4_EARLY8 +#define GPLL4 9 +#define SYSTEM_NOC_CLK_SRC 10 +/* U-Boot: KConfig check in CI erroneously picks this up, it's unused + * anyway so comment it out for now + */ +//#define CONFIG _NOC_CLK_SRC 11 +#define PERIPH_NOC_CLK_SRC 12 +#define MMSS_BIMC_GFX_CLK_SRC 13 +#define USB30_MASTER_CLK_SRC 14 +#define USB30_MOCK_UTMI_CLK_SRC15 +#define USB3_PHY_AUX_CLK_SRC 16 +#define USB20_MASTER_CLK_SRC 17 +#define USB20_MOCK_UTMI_CLK_SRC18 +#define SDCC1_APPS_CLK_SRC 19 +#define SDCC1_ICE_CORE_CLK_SRC 20 +#define SDCC2_APPS_CLK_SRC 21 +#define SDCC3_APPS_CLK_SRC 22 +#define SDCC4_APPS_CLK_SRC 23 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC24 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC25 +#define BLSP1_UART1_APPS_CLK_SRC 26 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC27 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC28 +#define BLSP1_UART2_APPS_CLK_SRC 29 +#define BLSP1_QUP3_SPI_APPS_CLK_SRC30 +#define BLSP1_QUP3_I2C_APPS_CLK_SRC31 +#define BLSP1_UART3_APPS_CLK_SRC 32 +#define BLSP1_QUP4_SPI_APPS_CLK_SRC33 +#define BLSP1_QUP4_I2C_APPS_CLK_SRC34 +#define BLSP1_UART4_APPS_CLK_SRC 35 +#define BLSP1_QUP5_SPI_APPS_CLK_SRC36 +#define BLSP1_QUP5_I2C_APPS_CLK_SRC37 +#define BLSP1_UART5_APPS_CLK_SRC 38 +#define BLSP1_QUP6_SPI_APPS_CLK_SRC39 +#define BLSP1_QUP6_I2C_APPS_CLK_SRC40 +#define BLSP1_UART6_APPS_CLK_SRC 41 +#define BLSP2_QUP1_SPI_APPS_CLK_SRC42 +#define BLSP2_QUP1_I2C_APPS_CLK_SRC43 +#define BLSP2_UART1_APPS_CLK_SRC 44 +#define BLSP2_QUP2_SPI_APPS_CLK_SRC45 +#define BLSP2_QUP2_I2C_APPS_CLK_SRC46 +#define BLSP2_UART2_APPS_CLK_SRC 47 +#define BLSP2_QUP3_SPI_APPS_CLK_SRC48 +#define BLSP2_QUP3_I2C_APPS_CLK_SRC49 +#define BLSP2_UART3_APPS_CLK_SRC 50 +#define BLSP2_QUP4_SPI_APPS_CLK_SRC51 +#define BLSP2_QUP4_I2C_APPS_CLK_SRC52 +#define BLSP2_UART4_APPS_CLK_SRC 53 +#define BLSP2_QUP5_SPI_APPS_CLK_SRC54 +#define BLSP2_QUP5_I2C_APPS_CLK_SRC55 +#define BLSP2_UART5_APPS_CLK_SRC 56 +#define BLSP2_QUP6_SPI_APPS_CLK_SRC
[PATCH v5 31/39] dts: msm8916: import PMIC dtsi files
Import the supporting pm8916.dtsi and msm8916-pm8916.dtsi files from
upstream in preparation for switching boards over.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/msm8916-pm8916.dtsi | 157 ++
arch/arm/dts/pm8916.dtsi | 178 +++
2 files changed, 335 insertions(+)
diff --git a/arch/arm/dts/msm8916-pm8916.dtsi b/arch/arm/dts/msm8916-pm8916.dtsi
new file mode 100644
index ..b1a7eafbee31
--- /dev/null
+++ b/arch/arm/dts/msm8916-pm8916.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * msm8916-pm8916.dtsi describes common properties (e.g. regulator connections)
+ * that apply to most devices that make use of the MSM8916 SoC and PM8916 PMIC.
+ * Many regulators have a fixed purpose in the original reference design and
+ * were rarely re-used for different purposes. Devices that deviate from the
+ * typical reference design should not make use of this include and instead add
+ * the necessary properties in the board-specific device tree.
+ */
+
+#include "msm8916.dtsi"
+#include "pm8916.dtsi"
+
+ {
+ vdda-supply = <_l2>;
+};
+
+_dsi0 {
+ vdda-supply = <_l2>;
+ vddio-supply = <_l6>;
+};
+
+_dsi0_phy {
+ vddio-supply = <_l6>;
+};
+
+ {
+ pll-supply = <_l7>;
+};
+
+_codec {
+ vdd-cdc-io-supply = <_l5>;
+ vdd-cdc-tx-rx-cx-supply = <_l5>;
+ vdd-micbias-supply = <_l13>;
+};
+
+_1 {
+ vmmc-supply = <_l8>;
+ vqmmc-supply = <_l5>;
+};
+
+_2 {
+ vmmc-supply = <_l11>;
+ vqmmc-supply = <_l12>;
+};
+
+_hs_phy {
+ v1p8-supply = <_l7>;
+ v3p3-supply = <_l13>;
+};
+
+ {
+ vddpx-supply = <_l7>;
+};
+
+_iris {
+ vddxo-supply = <_l7>;
+ vddrfa-supply = <_s3>;
+ vddpa-supply = <_l9>;
+ vdddig-supply = <_l5>;
+};
+
+_requests {
+ pm8916_rpm_regulators: regulators {
+ compatible = "qcom,rpm-pm8916-regulators";
+ vdd_l1_l2_l3-supply = <_s3>;
+ vdd_l4_l5_l6-supply = <_s4>;
+ vdd_l7-supply = <_s4>;
+
+ /* pm8916_s1 is managed by rpmpd (MSM8916_VDDCX) */
+
+ pm8916_s3: s3 {
+ regulator-min-microvolt = <125>;
+ regulator-max-microvolt = <135>;
+ regulator-always-on; /* Needed for L2 */
+ };
+
+ pm8916_s4: s4 {
+ regulator-min-microvolt = <185>;
+ regulator-max-microvolt = <215>;
+ regulator-always-on; /* Needed for L5/L7 */
+ };
+
+ /*
+* Some of the regulators are unused or managed by another
+* processor (e.g. the modem). We should still define nodes for
+* them to ensure the vote from the application processor can be
+* dropped in case the regulators are already on during boot.
+*
+* The labels for these nodes are omitted on purpose because
+* boards should configure a proper voltage before using them.
+*/
+ l1 {};
+
+ pm8916_l2: l2 {
+ regulator-min-microvolt = <120>;
+ regulator-max-microvolt = <120>;
+ regulator-always-on; /* Needed for LPDDR RAM */
+ };
+
+ /* pm8916_l3 is managed by rpmpd (MSM8916_VDDMX) */
+
+ l4 {};
+
+ pm8916_l5: l5 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on; /* Needed for most digital I/O */
+ };
+
+ pm8916_l6: l6 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ };
+
+ pm8916_l7: l7 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-always-on; /* Needed for CPU PLL */
+ };
+
+ pm8916_l8: l8 {
+ regulator-min-microvolt = <290>;
+ regulator-max-microvolt = <290>;
+ };
+
+ pm8916_l9: l9 {
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ l10 {};
+
+ pm8916_l11: l11 {
+ regulator-min-microvolt = <295>;
+ regulator-max-microvolt = <295>;
+ regulator-allow-set-load;
+ regulator-system-load = <20>;
+ };
+
+ pm8916_l12: l12 {
+
[PATCH v5 30/39] dt-bindings: import headers for MSM8916
Import the dt-bindings headers in preparation for switching to upstream DTS for MSM8916. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- include/dt-bindings/arm/coresight-cti-dt.h | 37 + include/dt-bindings/clock/qcom,rpmcc.h | 174 include/dt-bindings/interconnect/qcom,msm8916.h | 100 ++ include/dt-bindings/pinctrl/qcom,pmic-mpp.h | 106 +++ include/dt-bindings/reset/qcom,gcc-msm8916.h| 100 ++ include/dt-bindings/sound/apq8016-lpass.h | 9 ++ include/dt-bindings/sound/qcom,lpass.h | 46 +++ 7 files changed, 572 insertions(+) diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h new file mode 100644 index ..61e7bdf8ea6e --- /dev/null +++ b/include/dt-bindings/arm/coresight-cti-dt.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for the defined trigger signal + * types on CoreSight CTI. + */ + +#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H + +#define GEN_IO 0 +#define GEN_INTREQ 1 +#define GEN_INTACK 2 +#define GEN_HALTREQ3 +#define GEN_RESTARTREQ 4 +#define PE_EDBGREQ 5 +#define PE_DBGRESTART 6 +#define PE_CTIIRQ 7 +#define PE_PMUIRQ 8 +#define PE_DBGTRIGGER 9 +#define ETM_EXTOUT 10 +#define ETM_EXTIN 11 +#define SNK_FULL 12 +#define SNK_ACQCOMP13 +#define SNK_FLUSHCOMP 14 +#define SNK_FLUSHIN15 +#define SNK_TRIGIN 16 +#define STM_ASYNCOUT 17 +#define STM_TOUT_SPTE 18 +#define STM_TOUT_SW19 +#define STM_TOUT_HETE 20 +#define STM_HWEVENT21 +#define ELA_TSTART 22 +#define ELA_TSTOP 23 +#define ELA_DBGREQ 24 +#define CTI_TRIG_MAX 25 + +#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h new file mode 100644 index ..46309c9953b2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2015 Linaro Limited + */ + +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H +#define _DT_BINDINGS_CLK_MSM_RPMCC_H + +/* RPM clocks */ +#define RPM_PXO_CLK0 +#define RPM_PXO_A_CLK 1 +#define RPM_CXO_CLK2 +#define RPM_CXO_A_CLK 3 +#define RPM_APPS_FABRIC_CLK4 +#define RPM_APPS_FABRIC_A_CLK 5 +#define RPM_CFPB_CLK 6 +#define RPM_CFPB_A_CLK 7 +#define RPM_QDSS_CLK 8 +#define RPM_QDSS_A_CLK 9 +#define RPM_DAYTONA_FABRIC_CLK 10 +#define RPM_DAYTONA_FABRIC_A_CLK 11 +#define RPM_EBI1_CLK 12 +#define RPM_EBI1_A_CLK 13 +#define RPM_MM_FABRIC_CLK 14 +#define RPM_MM_FABRIC_A_CLK15 +#define RPM_MMFPB_CLK 16 +#define RPM_MMFPB_A_CLK17 +#define RPM_SYS_FABRIC_CLK 18 +#define RPM_SYS_FABRIC_A_CLK 19 +#define RPM_SFPB_CLK 20 +#define RPM_SFPB_A_CLK 21 +#define RPM_SMI_CLK22 +#define RPM_SMI_A_CLK 23 +#define RPM_PLL4_CLK 24 +#define RPM_XO_D0 25 +#define RPM_XO_D1 26 +#define RPM_XO_A0 27 +#define RPM_XO_A1 28 +#define RPM_XO_A2 29 +#define RPM_NSS_FABRIC_0_CLK 30 +#define RPM_NSS_FABRIC_0_A_CLK 31 +#define RPM_NSS_FABRIC_1_CLK 32 +#define RPM_NSS_FABRIC_1_A_CLK 33 + +/* SMD RPM clocks */ +#define RPM_SMD_XO_CLK_SRC 0 +#define RPM_SMD_XO_A_CLK_SRC 1 +#define RPM_SMD_PCNOC_CLK 2 +#define RPM_SMD_PCNOC_A_CLK3 +#define RPM_SMD_SNOC_CLK 4 +#define RPM_SMD_SNOC_A_CLK 5 +#define RPM_SMD_BIMC_CLK 6 +#define RPM_SMD_BIMC_A_CLK 7 +#define RPM_SMD_QDSS_CLK 8 +#define RPM_SMD_QDSS_A_CLK 9 +#define RPM_SMD_BB_CLK110 +#define RPM_SMD_BB_CLK1_A 11 +#define RPM_SMD_BB_CLK212 +#define RPM_SMD_BB_CLK2_A 13 +#define RPM_SMD_RF_CLK114 +#define RPM_SMD_RF_CLK1_A
[PATCH v5 28/39] dts: sdm845: import supporting dtsi files
Import the PM8998 and PMI8998 PMIC DTSI files from Linux as well
as the common audio codec in preperation for replacing board DTS files
with upstream.
Taken from kernel tag v6.7
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/pm8998.dtsi | 130 +++
arch/arm/dts/pmi8998.dtsi| 98 +
arch/arm/dts/sdm845-wcd9340.dtsi | 86 ++
3 files changed, 314 insertions(+)
diff --git a/arch/arm/dts/pm8998.dtsi b/arch/arm/dts/pm8998.dtsi
new file mode 100644
index ..3f82715392c6
--- /dev/null
+++ b/arch/arm/dts/pm8998.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/* Copyright 2018 Google LLC. */
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ thermal-zones {
+ pm8998-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <_temp>;
+
+ trips {
+ pm8998_alert0: pm8998-alert0 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ pm8998_crit: pm8998-crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+};
+
+_bus {
+ pm8998_lsid0: pmic@0 {
+ compatible = "qcom,pm8998", "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pm8998_pon: pon@800 {
+ compatible = "qcom,pm8998-pon";
+
+ reg = <0x800>;
+ mode-bootloader = <0x2>;
+ mode-recovery = <0x1>;
+
+ pm8998_pwrkey: pwrkey {
+ compatible = "qcom,pm8941-pwrkey";
+ interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ linux,code = ;
+ };
+
+ pm8998_resin: resin {
+ compatible = "qcom,pm8941-resin";
+ interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
+ debounce = <15625>;
+ bias-pull-up;
+ status = "disabled";
+ };
+ };
+
+ pm8998_temp: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <_adc ADC5_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8998_coincell: charger@2800 {
+ compatible = "qcom,pm8998-coincell",
"qcom,pm8941-coincell";
+ reg = <0x2800>;
+
+ status = "disabled";
+ };
+
+ pm8998_adc: adc@3100 {
+ compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ channel@6 {
+ reg = ;
+ label = "die_temp";
+ };
+ };
+
+ pm8998_adc_tm: adc-tm@3400 {
+ compatible = "qcom,spmi-adc-tm-hc";
+ reg = <0x3400>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rtc@6000 {
+ compatible = "qcom,pm8941-rtc";
+ reg = <0x6000>, <0x6100>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pm8998_gpios: gpio@c000 {
+ compatible = "qcom,pm8998-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+
[PATCH v5 27/39] dt-bindings: import headers for SDM845
Import the DT bindings headers that are used by SDM845 from Linux. Taken from kernel tag v6.7 Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- include/dt-bindings/clock/qcom,camcc-sdm845.h | 116 ++ include/dt-bindings/clock/qcom,dispcc-sdm845.h | 56 +++ include/dt-bindings/clock/qcom,gpucc-sdm845.h | 24 ++ include/dt-bindings/clock/qcom,lpass-sdm845.h | 15 + include/dt-bindings/clock/qcom,rpmh.h | 37 ++ include/dt-bindings/clock/qcom,videocc-sdm845.h| 35 ++ include/dt-bindings/dma/qcom-gpi.h | 11 + include/dt-bindings/firmware/qcom,scm.h| 39 ++ include/dt-bindings/iio/qcom,spmi-vadc.h | 300 +++ include/dt-bindings/interconnect/qcom,osm-l3.h | 15 + include/dt-bindings/interconnect/qcom,sdm845.h | 150 include/dt-bindings/phy/phy-qcom-qmp.h | 20 + include/dt-bindings/phy/phy-qcom-qusb2.h | 37 ++ include/dt-bindings/pinctrl/qcom,pmic-gpio.h | 164 include/dt-bindings/power/qcom-rpmpd.h | 412 + .../dt-bindings/regulator/qcom,rpmh-regulator.h| 36 ++ include/dt-bindings/reset/qcom,sdm845-aoss.h | 17 + include/dt-bindings/reset/qcom,sdm845-pdc.h| 22 ++ include/dt-bindings/soc/qcom,apr.h | 28 ++ include/dt-bindings/soc/qcom,rpmh-rsc.h| 14 + include/dt-bindings/sound/qcom,q6afe.h | 9 + include/dt-bindings/sound/qcom,q6asm.h | 26 ++ include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 234 23 files changed, 1817 insertions(+) diff --git a/include/dt-bindings/clock/qcom,camcc-sdm845.h b/include/dt-bindings/clock/qcom,camcc-sdm845.h new file mode 100644 index ..4f7a2d2320bf --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-sdm845.h @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H + +/* CAM_CC clock registers */ +#define CAM_CC_BPS_AHB_CLK 0 +#define CAM_CC_BPS_AREG_CLK1 +#define CAM_CC_BPS_AXI_CLK 2 +#define CAM_CC_BPS_CLK 3 +#define CAM_CC_BPS_CLK_SRC 4 +#define CAM_CC_CAMNOC_ATB_CLK 5 +#define CAM_CC_CAMNOC_AXI_CLK 6 +#define CAM_CC_CCI_CLK 7 +#define CAM_CC_CCI_CLK_SRC 8 +#define CAM_CC_CPAS_AHB_CLK9 +#define CAM_CC_CPHY_RX_CLK_SRC 10 +#define CAM_CC_CSI0PHYTIMER_CLK11 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC12 +#define CAM_CC_CSI1PHYTIMER_CLK13 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC14 +#define CAM_CC_CSI2PHYTIMER_CLK15 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC16 +#define CAM_CC_CSI3PHYTIMER_CLK17 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC18 +#define CAM_CC_CSIPHY0_CLK 19 +#define CAM_CC_CSIPHY1_CLK 20 +#define CAM_CC_CSIPHY2_CLK 21 +#define CAM_CC_CSIPHY3_CLK 22 +#define CAM_CC_FAST_AHB_CLK_SRC23 +#define CAM_CC_FD_CORE_CLK 24 +#define CAM_CC_FD_CORE_CLK_SRC 25 +#define CAM_CC_FD_CORE_UAR_CLK 26 +#define CAM_CC_ICP_APB_CLK 27 +#define CAM_CC_ICP_ATB_CLK 28 +#define CAM_CC_ICP_CLK 29 +#define CAM_CC_ICP_CLK_SRC 30 +#define CAM_CC_ICP_CTI_CLK 31 +#define CAM_CC_ICP_TS_CLK 32 +#define CAM_CC_IFE_0_AXI_CLK 33 +#define CAM_CC_IFE_0_CLK 34 +#define CAM_CC_IFE_0_CLK_SRC 35 +#define CAM_CC_IFE_0_CPHY_RX_CLK 36 +#define CAM_CC_IFE_0_CSID_CLK 37 +#define CAM_CC_IFE_0_CSID_CLK_SRC 38 +#define CAM_CC_IFE_0_DSP_CLK 39 +#define CAM_CC_IFE_1_AXI_CLK 40 +#define CAM_CC_IFE_1_CLK 41 +#define CAM_CC_IFE_1_CLK_SRC 42 +#define CAM_CC_IFE_1_CPHY_RX_CLK 43 +#define CAM_CC_IFE_1_CSID_CLK 44 +#define CAM_CC_IFE_1_CSID_CLK_SRC 45 +#define CAM_CC_IFE_1_DSP_CLK 46 +#define CAM_CC_IFE_LITE_CLK
[PATCH v5 26/39] doc: board/qualcomm: link to APQ8016 TRM
The MSM8916/APQ8016 Technical Reference Manual is publicly available and contains a lot of useful register maps for many core parts of the SoC. Include an archive.org link to it in the dragonboard410c documentation. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- doc/board/qualcomm/dragonboard410c.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/board/qualcomm/dragonboard410c.rst b/doc/board/qualcomm/dragonboard410c.rst index d0de9dbcbc9a..34629241110c 100644 --- a/doc/board/qualcomm/dragonboard410c.rst +++ b/doc/board/qualcomm/dragonboard410c.rst @@ -13,8 +13,10 @@ partition. Note that the U-Boot port used to be loaded as an Android boot image through LK. This is no longer the case, now U-Boot can replace LK entirely. .. _96Boards product page: https://www.96boards.org/product/dragonboard410c/ +.. _MSM8916/SD410/APQ8016 Technical Reference Manual: https://web.archive.org/web/20210525022203/https://developer.qualcomm.com/qfile/35259/lm80-p0436-100_d_snapdragon_410e_apq8016e_tech_reference_manual_revd.pdf + Installation First, setup ``CROSS_COMPILE`` for aarch64. Then, build U-Boot for ``dragonboard410c``:: -- 2.43.1
[PATCH v5 25/39] doc: board/qualcomm: document generic targets
Replace the board specific docs with a generic board.rst file which documents the build/boot process for the sdm845 and qcs404 boards now that the only differences are the DTB in use. At the same time, create a debugging page to document some useful snippets and tips for working with Qualcomm platforms. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Signed-off-by: Caleb Connolly --- doc/board/qualcomm/board.rst | 125 + doc/board/qualcomm/debugging.rst | 61 ++ doc/board/qualcomm/index.rst | 4 +- doc/board/qualcomm/qcs404.rst| 79 -- doc/board/qualcomm/sdm845.rst| 167 --- 5 files changed, 188 insertions(+), 248 deletions(-) diff --git a/doc/board/qualcomm/board.rst b/doc/board/qualcomm/board.rst new file mode 100644 index ..4d793209f9e3 --- /dev/null +++ b/doc/board/qualcomm/board.rst @@ -0,0 +1,125 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Dzmitry Sankouski + +Qualcomm generic boards +=== + +About this +-- +This document describes how to build and run U-Boot for Qualcomm generic +boards. Right now the generic target supports the Snapdragon 845 SoC, however +it's expected to support more SoCs going forward. + +SDM845 - high-end qualcomm chip, introduced in late 2017. +Mostly used in flagship phones and tablets of 2018. + +The current boot flow support loading u-boot as an Android boot image via +Qualcomm's UEFI-based ABL (Android) Bootloader. The DTB used by U-Boot will +be appended to the U-Boot image the same way as when booting Linux. U-Boot +will then retrieve the DTB during init. This way the memory layout and KASLR +offset will be populated by ABL. + +Installation + +Build +^ + + $ ./tools/buildman/buildman -o .output qcom + +This will build ``.output/u-boot-nodtb.bin`` using the ``qcom_defconfig``. + +Generate FIT image (optional) +^ +See doc/uImage.FIT for more details + +Pack android boot image +^^^ +We'll assemble android boot image with ``u-boot-nodtb.bin`` instead of linux kernel, +and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel +with appended dtb, so let's mimic linux to satisfy stock bootloader. + +Boards +-- + +starqlte + + +The starqltechn is a production board for Samsung S9 (SM-G9600) phone, +based on the Qualcomm SDM845 SoC. + +This device is supported by the common qcom_defconfig. + +The DTB is called "sdm845-samsung-starqltechn.dtb" + +More information can be found on the `Samsung S9 page`_. + +dragonboard845c +^^^ + +The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on +the Qualcomm SDM845 SoC. + +This device is supported by the common qcom_defconfig + +The DTB is called "sdm845-db845c.dtb" + +More information can be found on the `DragonBoard 845c page`_. + +qcs404-evb +^^ + +The QCS404 EvB is a Qualcomm Development Platform, based on the Qualcomm QCS404 SoC. + +This device is supported by the common qcom_defconfig + +The DTB is called "qcs404-evb-4000.dtb" + +Building steps +-- + +Steps: + +- Build u-boot + +As above:: + + ./tools/buildman/buildman -o .output qcom + +Or for db410c (and other boards not supported by the generic target):: + + make CROSS_COMPILE=aarch64-linux-gnu- O=.output dragonboard410c_defconfig + make O=.output -j$(nproc) + +- gzip u-boot:: + + gzip u-boot-nodtb.bin + +- Append dtb to gzipped u-boot:: + + cat u-boot-nodtb.bin.gz arch/arm/dts/your-board.dtb > u-boot-nodtb.bin.gz-dtb + +- If you chose to build a FIT image, A ``qcom.its`` file can be found in ``board/qualcomm/generic/`` + directory. It expects a folder as ``qcom_imgs/`` in the main directory containing pre-built kernel, + dts and ramdisk images. See ``qcom.its`` for full path to images:: + + mkimage -f qcom.its qcom.itb + +- Now we've got everything to build android boot image:: + + mkbootimg --kernel u-boot-nodtb.bin.gz-dtb --ramdisk db845c.itb \ + --output boot.img --pagesize 4096 --base 0x8000 + +Or with no FIT image:: + + mkbootimg --kernel u-boot-nodtb.bin.gz-dtb \ + --output boot.img --pagesize 4096 --base 0x8000 + +- Flash boot.img using fastboot and erase dtbo to avoid conflicts with our DTB: + + .. code-block:: bash + + fastboot flash boot boot.img + fastboot erase dtbo + +.. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9 +.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/ diff --git a/doc/board/qualcomm/debugging.rst b/doc/board/qualcomm/debugging.rst new file mode 100644 index ..1c35d1909d12 --- /dev/null +++ b/doc/board/qualcomm/debugging.rst @@ -0,0 +1,61 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Caleb Connolly + +Qualcomm debugging +== + +About this
[PATCH v5 24/39] board: qcs404-evb: drop board code
This board is entirely supported by the generic arch code and DTS. The
board code used to handle turning on the vbus regulator, however this is
now handled via DT.
With this, the board specific defconfig is also no longer needed, so
drop it as well.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
board/qualcomm/qcs404-evb/Makefile | 6
board/qualcomm/qcs404-evb/qcs404-evb.c | 49 -
configs/qcs404evb_defconfig| 56 --
3 files changed, 111 deletions(-)
diff --git a/board/qualcomm/qcs404-evb/Makefile
b/board/qualcomm/qcs404-evb/Makefile
deleted file mode 100644
index 4665827e0859..
--- a/board/qualcomm/qcs404-evb/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2022 Sumit Garg
-#
-
-obj-y += qcs404-evb.o
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c
b/board/qualcomm/qcs404-evb/qcs404-evb.c
deleted file mode 100644
index 1a4b1f97a3ae..
--- a/board/qualcomm/qcs404-evb/qcs404-evb.c
+++ /dev/null
@@ -1,49 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Board init file for QCS404-EVB
- *
- * (C) Copyright 2022 Sumit Garg
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void qcom_board_init(void)
-{
- struct udevice *pmic_gpio;
- struct gpio_desc usb_vbus_boost_pin;
- int ret, node;
-
- ret = uclass_get_device_by_name(UCLASS_GPIO,
- "pms405_gpios@c000",
- _gpio);
- if (ret < 0) {
- printf("Failed to find pms405_gpios@c000 node.\n");
- return;
- }
-
- node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
- "usb_vbus_boost_pin");
- if (node < 0) {
- printf("Failed to find usb_hub_reset_pm dt node.\n");
- return;
- }
- ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
-_vbus_boost_pin, 0);
- if (ret < 0) {
- printf("Failed to request usb_hub_reset_pm gpio.\n");
- return;
- }
-
- dm_gpio_set_dir_flags(_vbus_boost_pin,
- GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
-}
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
deleted file mode 100644
index d85d193895b0..
--- a/configs/qcs404evb_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SYS_BOARD="qcs404-evb"
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_COUNTER_FREQUENCY=1900
-CONFIG_POSITION_INDEPENDENT=y
-CONFIG_ARCH_SNAPDRAGON=y
-CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
-CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
-CONFIG_SYS_LOAD_ADDR=0x8000
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_BOOTDELAY=5
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
-CONFIG_SAVE_PREV_BL_FDT_ADDR=y
-CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
-CONFIG_SYS_CBSIZE=512
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_EXT4=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_NET is not set
-CONFIG_CLK=y
-CONFIG_CLK_QCOM_QCS404=y
-CONFIG_MSM_GPIO=y
-CONFIG_QCOM_PMIC_GPIO=y
-CONFIG_MISC=y
-CONFIG_MMC_HS400_SUPPORT=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ADMA=y
-CONFIG_MMC_SDHCI_MSM=y
-CONFIG_PHY=y
-CONFIG_PHY_QCOM_USB_HS_28NM=y
-CONFIG_PHY_QCOM_USB_SS=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_QCOM_QCS404=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_QCOM=y
-CONFIG_MSM_SERIAL=y
-CONFIG_SPMI_MSM=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_USB_STORAGE=y
-CONFIG_LMB_MAX_REGIONS=64
--
2.43.1
[PATCH v5 23/39] mach-snapdragon: carve out no-map regions
On Qualcomm platforms, the TZ may already have certain memory regions
under protection by the time U-Boot starts. There is a rare case on some
platforms where the prefetcher might speculatively access one of these
regions resulting in a board crash (TZ traps and then resets the board).
We shouldn't be accessing these regions from within U-Boot anyway, so
let's mark them all with PTE_TYPE_FAULT to prevent any speculative
access and correctly trap in EL1 rather than EL3.
This is quite costly with caches off (takes ~2 seconds on SDM845 vs 35ms
with caches on). So to minimise the impact this is only enabled on
QCS404 for now (where the issue is known to occur).
In the future, we should try to find a more efficient way to handle
this, perhaps by turning on the MMU in stages.
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/board.c | 162 +--
1 file changed, 140 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 5a859aabd5c4..f12f5791a136 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -24,8 +24,9 @@
#include
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
@@ -295,9 +296,9 @@ int board_late_init(void)
}
static void build_mem_map(void)
{
- int i;
+ int i, j;
/*
* Ensure the peripheral block is sized to correctly cover the address
range
* up to the first memory bank.
@@ -311,40 +312,157 @@ static void build_mem_map(void)
mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE |
PTE_BLOCK_PXN | PTE_BLOCK_UXN;
- debug("Configured memory map:\n");
- debug(" 0x%016llx - 0x%016llx: Peripheral block\n",
- mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
-
- /*
-* Now add memory map entries for each DRAM bank, ensuring we don't
-* overwrite the list terminator
-*/
- for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size;
i++) {
- if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
- log_warning("Too many DRAM banks!\n");
- break;
- }
- mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
- mem_map[i + 1].virt = mem_map[i + 1].phys;
- mem_map[i + 1].size = gd->bd->bi_dram[i].size;
- mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
-PTE_BLOCK_INNER_SHARE;
-
- debug(" 0x%016llx - 0x%016llx: DDR bank %d\n",
- mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i +
1].size, i);
+ for (i = 1, j = 0; i < ARRAY_SIZE(rbx_mem_map) - 1 &&
gd->bd->bi_dram[j].size; i++, j++) {
+ mem_map[i].phys = gd->bd->bi_dram[j].start;
+ mem_map[i].virt = mem_map[i].phys;
+ mem_map[i].size = gd->bd->bi_dram[j].size;
+ mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | \
+ PTE_BLOCK_INNER_SHARE;
}
+
+ mem_map[i].phys = UINT64_MAX;
+ mem_map[i].size = 0;
+
+#ifdef DEBUG
+ debug("Configured memory map:\n");
+ for (i = 0; mem_map[i].size; i++)
+ debug(" 0x%016llx - 0x%016llx: entry %d\n",
+ mem_map[i].phys, mem_map[i].phys + mem_map[i].size, i);
+#endif
}
u64 get_page_table_size(void)
{
return SZ_64K;
}
+static int fdt_cmp_res(const void *v1, const void *v2)
+{
+ const struct fdt_resource *res1 = v1, *res2 = v2;
+
+ return res1->start - res2->start;
+}
+
+#define N_RESERVED_REGIONS 32
+
+/* Mark all no-map regions as PTE_TYPE_FAULT to prevent speculative access.
+ * On some platforms this is enough to trigger a security violation and trap
+ * to EL3.
+ */
+static void carve_out_reserved_memory(void)
+{
+ static struct fdt_resource res[N_RESERVED_REGIONS] = { 0 };
+ int parent, rmem, count, i = 0;
+ phys_addr_t start;
+ size_t size;
+
+ /* Some reserved nodes must be carved out, as the cache-prefetcher may
otherwise
+* attempt to access them, causing a security exception.
+*/
+ parent = fdt_path_offset(gd->fdt_blob, "/reserved-memory");
+ if (parent <= 0) {
+ log_err("No reserved memory regions found\n");
+ return;
+ }
+
+ /* Collect the reserved memory regions */
+ fdt_for_each_subnode(rmem, gd->fdt_blob, parent) {
+ const fdt32_t *ptr;
+ int len;
+ if (!fdt_getprop(gd->fdt_blob, rmem, "no-map", NULL))
+ continue;
+
+ if (i == N_RESERVED_REGIONS) {
+
[PATCH v5 22/39] mach-snapdragon: generate fdtfile automatically
With just a few basic rules, we can generate the $fdtfile environment
variable to match the format used in Linux. This uses the root
compatible property inside u-boot, with specific handling for the
Dragonboard845c which is a special case, and for the qrb robotics
boards.
This is known to work on supported platforms, and lets us avoid having a
big lookup table.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/board.c | 101 +++
1 file changed, 101 insertions(+)
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index f445bed3af00..5a859aabd5c4 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -159,8 +159,108 @@ int board_init(void)
qcom_board_init();
return 0;
}
+/* Sets up the "board", and "soc" environment variables as well as
constructing the devicetree
+ * path, with a few quirks to handle non-standard dtb filenames. This is not
meant to be a
+ * comprehensive solution to automatically picking the DTB, but aims to be
correct for the
+ * majority case. For most devices it should be possible to make this
algorithm work by
+ * adjusting the root compatible property in the U-Boot DTS. Handling devices
with multiple
+ * variants that are all supported by a single U-Boot image will require
implementing device-
+ * specific detection.
+ */
+static void configure_env(void)
+{
+ const char *first_compat, *last_compat;
+ char *tmp;
+ char buf[32] = { 0 };
+ /*
+* Most DTB filenames follow the scheme: qcom/-[vendor]-.dtb
+* The vendor is skipped when it's a Qualcomm reference board, or the
+* db845c.
+*/
+ char dt_path[64] = { 0 };
+ int compat_count, ret;
+ ofnode root;
+
+ root = ofnode_root();
+ /* This is almost always 2, but be explicit that we want the first and
last compatibles
+* not the first and second.
+*/
+ compat_count = ofnode_read_string_count(root, "compatible");
+ if (compat_count < 2) {
+ log_warning("%s: only one root compatible bailing!\n",
__func__);
+ return;
+ }
+
+ /* The most specific device compatible (e.g. "thundercomm,db845c") */
+ ret = ofnode_read_string_index(root, "compatible", 0, _compat);
+ if (ret < 0) {
+ log_warning("Can't read first compatible\n");
+ return;
+ }
+
+ /* The last compatible is always the SoC compatible */
+ ret = ofnode_read_string_index(root, "compatible", compat_count - 1,
_compat);
+ if (ret < 0) {
+ log_warning("Can't read second compatible\n");
+ return;
+ }
+
+ /* Copy the second compat (e.g. "qcom,sdm845") into buf */
+ strlcpy(buf, last_compat, sizeof(buf) - 1);
+ tmp = buf;
+
+ /* strsep() is destructive, it replaces the comma with a \0 */
+ if (!strsep(, ",")) {
+ log_warning("second compatible '%s' has no ','\n", buf);
+ return;
+ }
+
+ /* tmp now points to just the "sdm845" part of the string */
+ env_set("soc", tmp);
+
+ /* Now figure out the "board" part from the first compatible */
+ memset(buf, 0, sizeof(buf));
+ strlcpy(buf, first_compat, sizeof(buf) - 1);
+ tmp = buf;
+
+ /* The Qualcomm reference boards (RBx, HDK, etc) */
+ if (!strncmp("qcom", buf, strlen("qcom"))) {
+ /*
+* They all have the first compatible as "qcom,-"
+* (e.g. "qcom,qrb5165-rb5"). We extract just the part after
+* the dash.
+*/
+ if (!strsep(, "-")) {
+ log_warning("compatible '%s' has no '-'\n", buf);
+ return;
+ }
+ /* tmp is now "rb5" */
+ env_set("board", tmp);
+ } else {
+ if (!strsep(, ",")) {
+ log_warning("compatible '%s' has no ','\n", buf);
+ return;
+ }
+ /* for thundercomm we just want the bit after the comma (e.g.
"db845c"),
+* for all other boards we replace the comma with a '-' and
take both
+* (e.g. "oneplus-enchilada")
+*/
+ if (!strncmp("thundercomm", buf, strlen("thundercomm"))) {
+ env_set("board", tmp);
+ } else {
+ *(tmp - 1) = '-';
+ env_set("board", buf);
+ }
+ }
+
+ /* Now build the full path name */
+ snprintf(dt_path, sizeof(dt_path), "qcom/%s-%s.dtb",
+env_get("soc"), env_get("board"));
+ env_set("fdtfile", dt_path);
+}
+
void __weak qcom_late_init(void)
{
}
@@ -187,8 +287,9 @@ int
[PATCH v5 20/39] mach-snapdragon: generalise board support
Historically, Qualcomm boards have relied on heavy hardcoding in U-Boot, in many cases to the specific SoC but also to the board itself (e.g. memory map). This has been largely resolved by modernising the Qualcomm drivers in U-Boot, however the board code still largely follows this model. This patch removes the board specific memory maps and duplicated board init code, replacing it with generic init code. The memory map is now built at runtime based on data read from DT, this allows for the memory map to be provided without having to recompile U-Boot. Support is also added for booting with appended DTBs, so that the first-stage bootloader can populate the memory map for us. The sdm845 specific init code is dropped entirely, it set an environment variable depending on if a button was pressed, but this variable wasn't used in U-Boot, and could be written to use the button command instead. The KASLR detection is also dropped as with appended dtb, the kaslr seed can be read directly from the DTB passed to U-Boot. A new qcom_defconfig is added, with the aim of providing a generic U-Boot configuration that will work on as many Qualcomm boards as possible. It replaces the defconfig files for the Dragonboard 845c, Galaxy S9, and QCS404 EVB. For now the db410c and 820c are excluded as they still have some board code left. Similarly, the config headers for db845c, starqltechn, and qcs404-evb are replaced by a single qcom header. The previously db410c-specific board_usb_init() function is made to be generic and is added to mach-snapdragon. While we lack proper modelling for USB configuration, using a well-known named pinctrl state is a reasonably generic middleground, and works using upstream DT. This function will do nothing unless the USB node has a pinctrl state named "device", in which case it will be set when entering USB peripheral mode. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Tested-by: Sumit Garg #qcs404 Signed-off-by: Caleb Connolly --- arch/arm/Kconfig | 3 + arch/arm/dts/Makefile| 9 +- arch/arm/mach-snapdragon/Kconfig | 96 ++ arch/arm/mach-snapdragon/Makefile| 6 +- arch/arm/mach-snapdragon/board.c | 215 +++ arch/arm/mach-snapdragon/init_sdm845.c | 73 arch/arm/mach-snapdragon/sysmap-apq8016.c| 31 arch/arm/mach-snapdragon/sysmap-apq8096.c| 31 arch/arm/mach-snapdragon/sysmap-qcs404.c | 43 - arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 board/qualcomm/dragonboard410c/Kconfig | 15 -- board/qualcomm/dragonboard410c/dragonboard410c.c | 41 - board/qualcomm/dragonboard820c/Kconfig | 15 -- board/qualcomm/dragonboard820c/dragonboard820c.c | 39 +--- board/qualcomm/dragonboard845c/Kconfig | 12 -- board/qualcomm/qcs404-evb/Kconfig| 15 -- board/qualcomm/qcs404-evb/qcs404-evb.c | 21 +-- configs/dragonboard410c_defconfig| 6 +- configs/dragonboard820c_defconfig| 6 +- configs/dragonboard845c_defconfig| 29 --- configs/qcom_defconfig | 67 +++ configs/qcs404evb_defconfig | 5 +- configs/starqltechn_defconfig| 41 - include/configs/dragonboard845c.h| 20 --- include/configs/qcom.h | 21 +++ include/configs/qcs404-evb.h | 20 --- include/configs/sdm845.h | 26 --- 27 files changed, 345 insertions(+), 592 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fde85dc0d537..0c78c1b8e6b4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1095,8 +1095,11 @@ config ARCH_SNAPDRAGON select OF_CONTROL select OF_SEPARATE select SMEM select SPMI + select OF_BOARD + select SAVE_PREV_BL_FDT_ADDR + select LINUX_KERNEL_IMAGE_HEADER imply CMD_DM config ARCH_SOCFPGA bool "Altera SOCFPGA family" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d9725030d5a0..c51db2db10b1 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -631,12 +631,13 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \ fsl-ls1028a-kontron-sl28-var4.dtb \ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb -dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb -dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb -dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb -dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb +dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \ + dragonboard820c.dtb \ + dragonboard845c.dtb \ + starqltechn.dtb \ + qcs404-evb.dtb dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb dtb-$(CONFIG_STM32F4) +=
[PATCH v5 21/39] mach-snapdragon: dynamic load addresses
Heavily inspired by Apple board code. Use the LMB allocator to configure
load addresses at runtime, and implement a lookup table for selecting a
devicetree.
As some Qualcomm RBx boards have different RAM capacities and base
addresses, it isn't possible to hardcode these regions.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/Kconfig | 1 +
arch/arm/mach-snapdragon/board.c | 34
board/qualcomm/dragonboard410c/dragonboard410c.c | 2 +-
3 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0c78c1b8e6b4..c7c236bada7a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1095,8 +1095,9 @@ config ARCH_SNAPDRAGON
select OF_CONTROL
select OF_SEPARATE
select SMEM
select SPMI
+ select BOARD_LATE_INIT
select OF_BOARD
select SAVE_PREV_BL_FDT_ADDR
select LINUX_KERNEL_IMAGE_HEADER
imply CMD_DM
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index a1867852bcca..f445bed3af00 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -21,8 +21,9 @@
#include
#include
#include
#include
+#include
#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -158,8 +159,41 @@ int board_init(void)
qcom_board_init();
return 0;
}
+void __weak qcom_late_init(void)
+{
+}
+
+#define KERNEL_COMP_SIZE SZ_64M
+
+#define addr_alloc(lmb, size) lmb_alloc(lmb, size, SZ_2M)
+
+/* Stolen from arch/arm/mach-apple/board.c */
+int board_late_init(void)
+{
+ struct lmb lmb;
+ u32 status = 0;
+
+ lmb_init_and_reserve(, gd->bd, (void *)gd->fdt_blob);
+
+ /* We need to be fairly conservative here as we support boards with
just 1G of TOTAL RAM */
+ status |= env_set_hex("kernel_addr_r", addr_alloc(, SZ_128M));
+ status |= env_set_hex("ramdisk_addr_r", addr_alloc(, SZ_128M));
+ status |= env_set_hex("kernel_comp_addr_r", addr_alloc(,
KERNEL_COMP_SIZE));
+ status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE);
+ status |= env_set_hex("scriptaddr", addr_alloc(, SZ_4M));
+ status |= env_set_hex("pxefile_addr_r", addr_alloc(, SZ_4M));
+ status |= env_set_hex("fdt_addr_r", addr_alloc(, SZ_2M));
+
+ if (status)
+ log_warning("%s: Failed to set run time variables\n", __func__);
+
+ qcom_late_init();
+
+ return 0;
+}
+
static void build_mem_map(void)
{
int i;
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 0136cc2237de..fbbfc0e65e24 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -87,9 +87,9 @@ int misc_init_r(void)
return 0;
}
-int board_late_init(void)
+int qcom_late_init(void)
{
char serial[16];
memset(serial, 0, 16);
--
2.43.1
[PATCH v5 19/39] board: dragonboard820c: use LINUX_KERNEL_IMAGE_HEADER
db820c predated support for prepending the kernel image header
automatically, drop it's custom linker script and head.S in favour of
this generic support.
Reviewed-by: Neil Armstrong
Reviewed-by: Ilias Apalodimas
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/Kconfig | 1 +
board/qualcomm/dragonboard820c/Makefile | 1 -
board/qualcomm/dragonboard820c/head.S | 33 -
board/qualcomm/dragonboard820c/u-boot.lds | 111 --
4 files changed, 1 insertion(+), 145 deletions(-)
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index ad6671081910..f897c393464f 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -44,8 +44,9 @@ config TARGET_DRAGONBOARD410C
- 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
config TARGET_DRAGONBOARD820C
bool "96Boards Dragonboard 820C"
+ select LINUX_KERNEL_IMAGE_HEADER
imply CLK_QCOM_APQ8096
imply PINCTRL_QCOM_APQ8096
imply BUTTON_QCOM_PMIC
help
diff --git a/board/qualcomm/dragonboard820c/Makefile
b/board/qualcomm/dragonboard820c/Makefile
index 643311f5b3ba..2ae6d16364aa 100644
--- a/board/qualcomm/dragonboard820c/Makefile
+++ b/board/qualcomm/dragonboard820c/Makefile
@@ -2,5 +2,4 @@
#
# (C) Copyright 2017 Jorge Ramirez-Ortiz
obj-y := dragonboard820c.o
-extra-y += head.o
diff --git a/board/qualcomm/dragonboard820c/head.S
b/board/qualcomm/dragonboard820c/head.S
deleted file mode 100644
index b052a858fd32..
--- a/board/qualcomm/dragonboard820c/head.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * ARM64 header for proper chain-loading with Little Kernel.
- *
- * Little Kernel shipped with Dragonboard820C boots standard Linux images for
- * ARM64. This file adds header that is required to boot U-Boot properly.
- *
- * For details see:
- * https://www.kernel.org/doc/Documentation/arm64/booting.txt
- *
- * (C) Copyright 2015 Mateusz Kulikowski
- */
-
-#include
-
-/*
- * per document in linux/Doc/arm64/booting.text
- */
-.global _arm64_header
-_arm64_header:
- b _start
- .word 0
- .quad CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
- .quad 0/* Effective size of kernel image, little-endian */
- .quad 0/* kernel flags, little-endian */
- .quad 0/* reserved */
- .quad 0/* reserved */
- .quad 0/* reserved */
- .byte 0x41 /* Magic number, "ARM\x64" */
- .byte 0x52
- .byte 0x4d
- .byte 0x64
- .word 0/* reserved (used for PE COFF offset) */
diff --git a/board/qualcomm/dragonboard820c/u-boot.lds
b/board/qualcomm/dragonboard820c/u-boot.lds
deleted file mode 100644
index 5251b59fbe76..
--- a/board/qualcomm/dragonboard820c/u-boot.lds
+++ /dev/null
@@ -1,111 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Override linker script for fastboot-readable images
- *
- * (C) Copyright 2015 Mateusz Kulikowski
- *
- * Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
- */
-
-OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64",
"elf64-littleaarch64")
-OUTPUT_ARCH(aarch64)
-ENTRY(_arm64_header)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(8);
- .text :
- {
- *(.__image_copy_start)
- board/qualcomm/dragonboard820c/head.o (.text*)
- CPUDIR/start.o (.text*)
- }
-
- /* This needs to come before *(.text*) */
- .efi_runtime : {
-__efi_runtime_start = .;
- *(.text.efi_runtime*)
- *(.rodata.efi_runtime*)
- *(.data.efi_runtime*)
-__efi_runtime_stop = .;
- }
-
- .text_rest :
- {
- *(.text*)
- }
-
- . = ALIGN(8);
- .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
- . = ALIGN(8);
- .data : {
- *(.data*)
- }
-
- . = ALIGN(8);
-
- . = .;
-
- . = ALIGN(8);
- __u_boot_list : {
- KEEP(*(SORT(__u_boot_list*)));
- }
-
- . = ALIGN(8);
-
- .efi_runtime_rel : {
-__efi_runtime_rel_start = .;
- *(.rel*.efi_runtime)
- *(.rel*.efi_runtime.*)
-__efi_runtime_rel_stop = .;
- }
-
- . = ALIGN(8);
-
- .image_copy_end :
- {
- *(.__image_copy_end)
- }
-
- . = ALIGN(8);
-
- .rel_dyn_start :
- {
- *(.__rel_dyn_start)
- }
-
- .rela.dyn : {
- *(.rela*)
- }
-
- .rel_dyn_end :
- {
- *(.__rel_dyn_end)
- }
-
- _end = .;
-
- . = ALIGN(8);
-
- .bss_start : {
- KEEP(*(.__bss_start));
- }
-
- .bss : {
-
[PATCH v5 18/39] board: dragonboard410c: import board code from mach-snapdragon
Some of the db410c board support code was written to be generic and
placed in mach-snapdragon. However, as the db410c is the only board
using this, move the code out of mach-snapdragon. This makes is more
obvious what code is relevant for which targets and helps tidy things up
a little more.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/Makefile| 2 -
arch/arm/mach-snapdragon/dram.c | 99
arch/arm/mach-snapdragon/include/mach/dram.h | 12 ---
arch/arm/mach-snapdragon/include/mach/misc.h | 13
arch/arm/mach-snapdragon/misc.c | 55 -
board/qualcomm/dragonboard410c/Makefile | 2 +-
board/qualcomm/dragonboard410c/dragonboard410c.c | 48 +++-
7 files changed, 45 insertions(+), 186 deletions(-)
diff --git a/arch/arm/mach-snapdragon/Makefile
b/arch/arm/mach-snapdragon/Makefile
index 3a3a297c1768..d02432df8b04 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -5,7 +5,5 @@
obj-$(CONFIG_SDM845) += sysmap-sdm845.o
obj-$(CONFIG_SDM845) += init_sdm845.o
obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
-obj-y += misc.o
-obj-y += dram.o
obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/dram.c b/arch/arm/mach-snapdragon/dram.c
deleted file mode 100644
index 499dfdf0da6e..
--- a/arch/arm/mach-snapdragon/dram.c
+++ /dev/null
@@ -1,99 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Onboard memory detection for Snapdragon boards
- *
- * (C) Copyright 2018 Ramon Fried
- *
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#define SMEM_USABLE_RAM_PARTITION_TABLE 402
-#define RAM_PART_NAME_LENGTH16
-#define RAM_NUM_PART_ENTRIES32
-#define CATEGORY_SDRAM 0x0E
-#define TYPE_SYSMEM 0x01
-
-struct smem_ram_ptable_hdr {
- u32 magic[2];
- u32 version;
- u32 reserved;
- u32 len;
-} __attribute__ ((__packed__));
-
-struct smem_ram_ptn {
- char name[RAM_PART_NAME_LENGTH];
- u64 start;
- u64 size;
- u32 attr;
- u32 category;
- u32 domain;
- u32 type;
- u32 num_partitions;
- u32 reserved[3];
-} __attribute__ ((__packed__));
-
-struct smem_ram_ptable {
- struct smem_ram_ptable_hdr hdr;
- u32 reserved; /* Added for 8 bytes alignment of header */
- struct smem_ram_ptn parts[RAM_NUM_PART_ENTRIES];
-} __attribute__ ((__packed__));
-
-#ifndef MEMORY_BANKS_MAX
-#define MEMORY_BANKS_MAX 4
-#endif
-
-int msm_fixup_memory(void *blob)
-{
- u64 bank_start[MEMORY_BANKS_MAX];
- u64 bank_size[MEMORY_BANKS_MAX];
- size_t size;
- int i;
- int count = 0;
- struct udevice *smem;
- int ret;
- struct smem_ram_ptable *ram_ptable;
- struct smem_ram_ptn *p;
-
- ret = uclass_get_device_by_name(UCLASS_SMEM, "smem", );
- if (ret < 0) {
- printf("Failed to find SMEM node. Check device tree\n");
- return 0;
- }
-
- ram_ptable = smem_get(smem, -1, SMEM_USABLE_RAM_PARTITION_TABLE, );
-
- if (!ram_ptable) {
- printf("Failed to find SMEM partition.\n");
- return -ENODEV;
- }
-
- /* Check validy of RAM */
- for (i = 0; i < RAM_NUM_PART_ENTRIES; i++) {
- p = _ptable->parts[i];
- if (p->category == CATEGORY_SDRAM && p->type == TYPE_SYSMEM) {
- bank_start[count] = p->start;
- bank_size[count] = p->size;
- debug("Detected memory bank %u: start: 0x%llx size:
0x%llx\n",
- count, p->start, p->size);
- count++;
- }
- }
-
- if (!count) {
- printf("Failed to detect any memory bank\n");
- return -ENODEV;
- }
-
- ret = fdt_fixup_memory_banks(blob, bank_start, bank_size, count);
- if (ret)
- return ret;
-
- return 0;
-}
diff --git a/arch/arm/mach-snapdragon/include/mach/dram.h
b/arch/arm/mach-snapdragon/include/mach/dram.h
deleted file mode 100644
index 0a9eedda414c..
--- a/arch/arm/mach-snapdragon/include/mach/dram.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Snapdragon DRAM
- * Copyright (C) 2018 Ramon Fried
- */
-
-#ifndef DRAM_H
-#define DRAM_H
-
-int msm_fixup_memory(void *blob);
-
-#endif
diff --git a/arch/arm/mach-snapdragon/include/mach/misc.h
b/arch/arm/mach-snapdragon/include/mach/misc.h
deleted file mode 100644
index c60e3e472470..
--- a/arch/arm/mach-snapdragon/include/mach/misc.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Snapdragon DRAM
[PATCH v5 17/39] board: dragonboard410c: upstream DT compat
Use the root compatible strings from upstream Linux, add missing
'#clock-cells' property to the gcc node.
Adjust some of the msm8916/apq8016 drivers to use the correct upstream
compatible properties and DT bindings.
This prepares us to switch to upstream DT in a future patch.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 25 +++-
board/qualcomm/dragonboard410c/dragonboard410c.c | 93 +++-
doc/device-tree-bindings/usb/ehci-msm.txt| 10 --
drivers/clk/qcom/clock-apq8016.c | 7 +-
drivers/phy/qcom/msm8916-usbh-phy.c | 4 +-
drivers/pinctrl/qcom/pinctrl-apq8016.c | 2 +-
drivers/usb/host/ehci-msm.c | 22 ++-
include/dt-bindings/clock/qcom,gcc-msm8916.h | 179 +++
8 files changed, 246 insertions(+), 96 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index c395e6cc0427..453642b25705 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -11,9 +11,9 @@
#include
/ {
model = "Qualcomm Technologies, Inc. Dragonboard 410c";
- compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
+ compatible = "qcom,apq8016-sbc", "qcom,apq8016";
qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
qcom,board-id = <0x10018 0x0>;
#address-cells = <0x2>;
#size-cells = <0x2>;
@@ -78,8 +78,9 @@
compatible = "qcom,gcc-msm8916";
reg = <0x180 0x8>;
#address-cells = <0x1>;
#size-cells = <0x0>;
+ #clock-cells = <0x1>;
};
serial@78b {
compatible = "qcom,msm-uartdm-v1.4";
@@ -90,17 +91,27 @@
pinctrl-0 = <_uart>;
};
ehci@78d9000 {
- compatible = "qcom,ehci-host";
+ compatible = "qcom,ci-hdrc";
reg = <0x78d9000 0x400>;
phys = <_phy>;
- };
- ehci_phy: ehci_phy@78d9000 {
- compatible = "qcom,apq8016-usbphy";
- reg = <0x78d9000 0x400>;
- #phy-cells = <0>;
+ ulpi {
+ usb_hs_phy: phy {
+ compatible = "qcom,usb-hs-phy-msm8916",
+"qcom,usb-hs-phy";
+ #phy-cells = <0>;
+ clocks = <_board>, <
GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "sleep";
+ resets = < GCC_USB2A_PHY_BCR>,
< 0>;
+ reset-names = "phy", "por";
+ qcom,init-seq = /bits/ 8 <0x0 0x44>,
+<0x1 0x6b>,
+<0x2 0x24>,
+<0x3 0x13>;
+ };
+ };
};
sdhci@07824000 {
compatible = "qcom,sdhci-msm-v4";
diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c
b/board/qualcomm/dragonboard410c/dragonboard410c.c
index 350e0e9e20aa..1adac07569ae 100644
--- a/board/qualcomm/dragonboard410c/dragonboard410c.c
+++ b/board/qualcomm/dragonboard410c/dragonboard410c.c
@@ -8,8 +8,9 @@
#include
#include
#include
#include
+#include
#include
#include
#include
#include
@@ -22,86 +23,34 @@
#include
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
- return 0;
-}
+#define USB_HUB_RESET_GPIO 2
+#define USB_SW_SELECT_GPIO 3
int board_usb_init(int index, enum usb_init_type init)
{
- static struct udevice *pmic_gpio;
- static struct gpio_desc hub_reset, usb_sel;
- int ret = 0, node;
+ struct udevice *usb;
+ int ret = 0;
- if (!pmic_gpio) {
- ret = uclass_get_device_by_name(UCLASS_GPIO,
- "pm8916_gpios@c000",
- _gpio);
- if (ret < 0) {
- printf("Failed to find pm8916_gpios@c000 node.\n");
- return ret;
- }
+ /* USB device */
+ ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), );
+ if
[PATCH v5 16/39] board: dragonboard410c: add chainloaded config fragment
Add a config fragment for building U-Boot such that it can be chainloaded by aboot/LK rather than being flashed directly to the aboot partition. Reviewed-by: Neil Armstrong Reviewed-by: Sumit Garg Tested-by: Sumit Garg #qcs404 Signed-off-by: Caleb Connolly --- board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++ 1 file changed, 7 insertions(+) diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config new file mode 100644 index ..3fd064924a1f --- /dev/null +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config @@ -0,0 +1,7 @@ +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set +CONFIG_TEXT_BASE=0x0 +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set +# CONFIG_REMAKE_ELF is not set +CONFIG_POSITION_INDEPENDENT=y +CONFIG_INIT_SP_RELATIVE=y +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288 -- 2.43.1
[PATCH v5 15/39] pinctrl: qcom: apq8016: init pre-reloaction
On the DB410c we support running as a first stage bootloader. This
requires initialising the GPIOs which are muxed to UART before they can
be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure
that we do this early enough.
This is required to prevent the first few lines of UART log from being
dropped.
Reported-by: Sumit Garg
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 796c4b49d578..eb9bf87b6c2e 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -75,5 +75,6 @@ U_BOOT_DRIVER(pinctrl_apq8016) = {
.id = UCLASS_NOP,
.of_match = msm_pinctrl_ids,
.ops= _pinctrl_ops,
.bind = msm_pinctrl_bind,
+ .flags = DM_FLAG_PRE_RELOC,
};
--
2.43.1
[PATCH v5 14/39] pinctrl: qcom: fix DT compatibility
Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this
for SoCs where we're now using upstream DT.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
drivers/pinctrl/qcom/pinctrl-apq8016.c | 26
drivers/pinctrl/qcom/pinctrl-apq8096.c | 16 +-
drivers/pinctrl/qcom/pinctrl-qcs404.c | 57 --
3 files changed, 69 insertions(+), 30 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index c860b748e999..796c4b49d578 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -13,20 +13,20 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
- "SDC1_CLK",
- "SDC1_CMD",
- "SDC1_DATA",
- "SDC2_CLK",
- "SDC2_CMD",
- "SDC2_DATA",
- "QDSD_CLK",
- "QDSD_CMD",
- "QDSD_DATA0",
- "QDSD_DATA1",
- "QDSD_DATA2",
- "QDSD_DATA3",
+ "sdc1_clk",
+ "sdc1_cmd",
+ "sdc1_data",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ "qdsd_clk",
+ "qdsd_cmd",
+ "qdsd_data0",
+ "qdsd_data1",
+ "qdsd_data2",
+ "qdsd_data3",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
{"blsp1_uart", 2},
@@ -41,9 +41,9 @@ static const char *apq8016_get_function_name(struct udevice
*dev,
static const char *apq8016_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 122) {
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 122];
}
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c
b/drivers/pinctrl/qcom/pinctrl-apq8096.c
index 75d1d0956a30..880df8fe3c74 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8096.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c
@@ -13,15 +13,15 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
- "SDC1_CLK",
- "SDC1_CMD",
- "SDC1_DATA",
- "SDC2_CLK",
- "SDC2_CMD",
- "SDC2_DATA",
- "SDC1_RCLK",
+ "sdc1_clk",
+ "sdc1_cmd",
+ "sdc1_data",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
+ "sdc1_rclk",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
{"blsp_uart8", 2},
@@ -36,9 +36,9 @@ static const char *apq8096_get_function_name(struct udevice
*dev,
static const char *apq8096_get_pin_name(struct udevice *dev,
unsigned int selector)
{
if (selector < 150) {
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
} else {
return msm_pinctrl_pins[selector - 150];
}
diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c
b/drivers/pinctrl/qcom/pinctrl-qcs404.c
index b54c8d80b8df..3a2d4685997e 100644
--- a/drivers/pinctrl/qcom/pinctrl-qcs404.c
+++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c
@@ -9,22 +9,26 @@
#include
#include "pinctrl-qcom.h"
+#define NORTH 0x0030
+#define SOUTH 0x
+#define EAST 0x06b0
+
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
static const char * const msm_pinctrl_pins[] = {
- "SDC1_RCLK",
- "SDC1_CLK",
- "SDC1_CMD",
- "SDC1_DATA",
- "SDC2_CLK",
- "SDC2_CMD",
- "SDC2_DATA",
+ "sdc1_rclk",
+ "sdc1_clk",
+ "sdc1_cmd",
+ "sdc1_data",
+ "sdc2_clk",
+ "sdc2_cmd",
+ "sdc2_data",
};
static const struct pinctrl_function msm_pinctrl_functions[] = {
- {"blsp_uart2", 1},
+ {"gpio", 0},
{"rgmii_int", 1},
{"rgmii_ck", 1},
{"rgmii_tx", 1},
{"rgmii_ctl", 1},
@@ -36,8 +40,42 @@ static const struct pinctrl_function msm_pinctrl_functions[]
= {
{"blsp_i2c_sda_a2", 3},
{"blsp_i2c_scl_a2", 3},
{"blsp_i2c3", 2},
{"blsp_i2c4", 1},
+ {"blsp_uart_tx_a2", 1},
+ {"blsp_uart_rx_a2", 1},
+};
+
+static const unsigned int qcs404_pin_offsets[] = {
+ [0] = SOUTH,[1] = SOUTH,[2] = SOUTH,[3] = SOUTH,[4] =
SOUTH,
+ [5] = SOUTH, [6] = SOUTH, [7] = SOUTH, [8] = SOUTH,[9] =
SOUTH,
+ [10] = SOUTH, [11] = SOUTH, [12] = SOUTH, [13] = SOUTH, [14] =
SOUTH,
+ [15] = SOUTH, [16] = SOUTH, [17] = NORTH, [18] = NORTH, [19] =
NORTH,
+ [20] = NORTH, [21] = SOUTH, [22] = NORTH, [23] = NORTH,
[PATCH v5 13/39] pinctrl: qcom: stub support for special GPIOs
Most platforms have a handful of "special" GPIOs, like the MMC
clock/data lanes, UFS reset, etc. These don't follow the usual naming
scheme of "gpioX" and also have unique capabilities and registers. We
can get away without supporting them all for now, but DT compatibility
is still an issue.
Add support for allowing these to be specified after the other pins, and
make all pinmux/pinconf calls for them nop.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/mach-snapdragon/include/mach/gpio.h | 7 +++
drivers/gpio/msm_gpio.c | 20
drivers/pinctrl/qcom/pinctrl-apq8016.c | 5 -
drivers/pinctrl/qcom/pinctrl-apq8096.c | 5 -
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 5 -
drivers/pinctrl/qcom/pinctrl-qcom.c | 12
drivers/pinctrl/qcom/pinctrl-qcs404.c| 7 +--
drivers/pinctrl/qcom/pinctrl-sdm845.c| 5 +++--
8 files changed, 59 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h
b/arch/arm/mach-snapdragon/include/mach/gpio.h
index 8dac62f870b9..53c6ae064906 100644
--- a/arch/arm/mach-snapdragon/include/mach/gpio.h
+++ b/arch/arm/mach-snapdragon/include/mach/gpio.h
@@ -12,8 +12,10 @@
struct msm_pin_data {
int pin_count;
const unsigned int *pin_offsets;
+ /* Index of first special pin, these are ignored for now */
+ unsigned int special_pins_start;
};
static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int
selector)
{
@@ -24,5 +26,10 @@ static inline u32 qcom_pin_offset(const unsigned int *offs,
unsigned int selecto
return out;
}
+static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata,
unsigned int pin)
+{
+ return pindata->special_pins_start && pin >=
pindata->special_pins_start;
+}
+
#endif /* _QCOM_GPIO_H_ */
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index 80cd28bb231f..5e57b0cbde75 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -38,8 +38,12 @@ struct msm_gpio_bank {
static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (qcom_is_special_pin(priv->pin_data, gpio))
+ return 0;
+
/* Disable OE bit */
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
GPIO_OE_MASK, GPIO_OE_DISABLE);
@@ -49,8 +53,12 @@ static int msm_gpio_direction_input(struct udevice *dev,
unsigned int gpio)
static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int
value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (qcom_is_special_pin(priv->pin_data, gpio))
+ return 0;
+
value = !!value;
/* set value */
writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
@@ -61,8 +69,12 @@ static int msm_gpio_direction_output(struct udevice *dev,
unsigned int gpio,
int value)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (qcom_is_special_pin(priv->pin_data, gpio))
+ return 0;
+
value = !!value;
/* set value */
writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));
/* switch direction */
@@ -75,15 +87,23 @@ static int msm_gpio_direction_output(struct udevice *dev,
unsigned int gpio,
static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (qcom_is_special_pin(priv->pin_data, gpio))
+ return 0;
+
return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN);
}
static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio)
{
struct msm_gpio_bank *priv = dev_get_priv(dev);
+ /* Always NOP for special pins, assume they're in the correct state */
+ if (qcom_is_special_pin(priv->pin_data, gpio))
+ return 0;
+
if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE)
return GPIOF_OUTPUT;
return GPIOF_INPUT;
diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c
b/drivers/pinctrl/qcom/pinctrl-apq8016.c
index 8149ffd83cc4..c860b748e999 100644
--- a/drivers/pinctrl/qcom/pinctrl-apq8016.c
+++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c
@@ -54,9 +54,12 @@ static unsigned int apq8016_get_function_mux(unsigned int
selector)
return msm_pinctrl_functions[selector].val;
}
static const struct
[PATCH v5 12/39] sandbox: dts: fix qcom pmic gpio
Adjust the DT to match upstream bindings.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/sandbox/dts/sandbox.dtsi | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index 241f397ba6e7..c93ce7128942 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -418,19 +418,18 @@
#address-cells = <0x1>;
#size-cells = <0x1>;
pm8916@0 {
compatible = "qcom,spmi-pmic";
- reg = <0x0 0x1>;
+ reg = <0x0 0x0>;
#address-cells = <0x1>;
- #size-cells = <0x1>;
+ #size-cells = <0x0>;
spmi_gpios: gpios@c000 {
compatible = "qcom,pm8916-gpio";
- reg = <0xc000 0x400>;
+ reg = <0xc000>;
gpio-controller;
- gpio-count = <4>;
+ gpio-ranges = <_gpios 0 0 4>;
#gpio-cells = <2>;
- gpio-bank-name="spmi";
};
};
};
--
2.43.1
[PATCH v5 11/39] gpio: qcom_pmic: add pinctrl driver
Introduce a basic pinctrl driver for the SPMI PMIC GPIOs. This is
necessary to make proper use of upstream DT bindings specifically on the
dragonboard410c where they're used to switch between USB host and device
modes.
Only support for driving the pins as output low or high is enabled for
now.
To minimise duplicated code and allow for sharing common DT data, the
pinctrl driver is initialised as a child of the existing GPIO driver.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 257 +-
1 file changed, 176 insertions(+), 81 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 63b512725ad9..01f9b0d55f93 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -6,12 +6,16 @@
*/
#include
#include
+#include
+#include
+#include
#include
#include
#include
#include
+#include
#include
#include
/* Register offset for each gpio */
@@ -74,19 +78,56 @@
enum pmic_gpio_quirks {
QCOM_PMIC_QUIRK_READONLY = (1 << 0),
};
-struct qcom_gpio_bank {
+struct qcom_pmic_gpio_data {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
+ u32 pin_count;
+ struct udevice *pmic; /* Reference to pmic device for read/write */
};
-static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset,
+/* dev can be the GPIO or pinctrl device */
+static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool
input, int value)
+{
+ struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+ u32 gpio_base = plat->pid + REG_OFFSET(offset);
+ u32 reg_ctl_val;
+ int ret = 0;
+
+ /* Select the mode and output */
+ if (plat->lv_mv_type) {
+ if (input)
+ reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
+ else
+ reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
+ } else {
+ if (input)
+ reg_ctl_val = REG_CTL_MODE_INPUT;
+ else
+ reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
+ }
+
+ ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
+ if (ret < 0)
+ return ret;
+
+ if (plat->lv_mv_type && !input) {
+ ret = pmic_reg_write(plat->pmic,
+gpio_base + REG_LV_MV_OUTPUT_CTL,
+!!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset,
bool input, int value)
{
- struct qcom_gpio_bank *priv = dev_get_priv(dev);
- uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
- uint32_t reg_ctl_val;
+ struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
+ uint32_t gpio_base = plat->pid + REG_OFFSET(offset);
ulong quirks = dev_get_driver_data(dev);
int ret = 0;
/* Some PMICs don't like their GPIOs being configured */
@@ -98,49 +139,26 @@ static int qcom_gpio_set_direction(struct udevice *dev,
unsigned offset,
REG_EN_CTL_ENABLE, 0);
if (ret < 0)
return ret;
- /* Select the mode and output */
- if (priv->lv_mv_type) {
- if (input)
- reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
- else
- reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
- } else {
- if (input)
- reg_ctl_val = REG_CTL_MODE_INPUT;
- else
- reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
- }
-
- ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val);
- if (ret < 0)
- return ret;
-
- if (priv->lv_mv_type && !input) {
- ret = pmic_reg_write(dev->parent,
-gpio_base + REG_LV_MV_OUTPUT_CTL,
-!!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
- if (ret < 0)
- return ret;
- }
+ _qcom_gpio_set_direction(dev, offset, input, value);
/* Set the right pull (no pull) */
- ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,
+ ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL,
REG_DIG_PULL_NO_PU);
if (ret < 0)
return ret;
/* Configure output pin drivers if needed */
if (!input) {
/* Select the VIN - VIN0, pin is input so it doesn't matter */
- ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
+
[PATCH v5 10/39] gpio: qcom_pmic: add a quirk to skip GPIO configuration
Some platforms hard reset when attempting to configure PMIC GPIOs. Add
support for quirks specified in match data with a single quirk to skip
this configuration. We rely on the GPIO already be configured correctly,
which is always the case for volume up (the only current user of these
GPIOs).
This is not expected behaviour but appears to be due to a U-Boot
specific bug. This quirk at least allows for the volume buttons to be
used on platforms where this bug is apparent.
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 2a4fef8d28cb..63b512725ad9 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -63,8 +63,19 @@
#define REG_EN_CTL 0x46
#define REG_EN_CTL_ENABLE (1 << 7)
+/**
+ * pmic_gpio_match_data - platform specific configuration
+ *
+ * @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to
configure them.
+ * This is a workaround for an unknown bug on some platforms where trying to
write the
+ * GPIO configuration registers causes the board to hang.
+ */
+enum pmic_gpio_quirks {
+ QCOM_PMIC_QUIRK_READONLY = (1 << 0),
+};
+
struct qcom_gpio_bank {
uint32_t pid; /* Peripheral ID on SPMI bus */
bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */
};
@@ -74,9 +85,14 @@ static int qcom_gpio_set_direction(struct udevice *dev,
unsigned offset,
{
struct qcom_gpio_bank *priv = dev_get_priv(dev);
uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
uint32_t reg_ctl_val;
- int ret;
+ ulong quirks = dev_get_driver_data(dev);
+ int ret = 0;
+
+ /* Some PMICs don't like their GPIOs being configured */
+ if (quirks & QCOM_PMIC_QUIRK_READONLY)
+ return 0;
/* Disable the GPIO */
ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
REG_EN_CTL_ENABLE, 0);
@@ -303,9 +319,9 @@ static int qcom_gpio_of_to_plat(struct udevice *dev)
static const struct udevice_id qcom_gpio_ids[] = {
{ .compatible = "qcom,pm8916-gpio" },
{ .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */
- { .compatible = "qcom,pm8998-gpio" },
+ { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
{ .compatible = "qcom,pms405-gpio" },
{ }
};
--
2.43.1
[PATCH v5 09/39] gpio: qcom_pmic: 1-based GPIOs
Qualcomm PMICs number their GPIOs starting from 1, implement a custom
.xlate method to handle this.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c
index 6167c8411678..2a4fef8d28cb 100644
--- a/drivers/gpio/qcom_pmic_gpio.c
+++ b/drivers/gpio/qcom_pmic_gpio.c
@@ -208,14 +208,36 @@ static int qcom_gpio_set_value(struct udevice *dev,
unsigned offset,
return pmic_clrsetbits(dev->parent, gpio_base + REG_CTL,
REG_CTL_OUTPUT_MASK, !!value);
}
+static int qcom_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct ofnode_phandle_args *args)
+{
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ if (args->args_count < 1)
+ return -EINVAL;
+
+ /* GPIOs in DT are 1-based */
+ desc->offset = args->args[0] - 1;
+ if (desc->offset >= uc_priv->gpio_count)
+ return -EINVAL;
+
+ if (args->args_count < 2)
+ return 0;
+
+ desc->flags = gpio_flags_xlate(args->args[1]);
+
+ return 0;
+}
+
static const struct dm_gpio_ops qcom_gpio_ops = {
.direction_input= qcom_gpio_direction_input,
.direction_output = qcom_gpio_direction_output,
.get_value = qcom_gpio_get_value,
.set_value = qcom_gpio_set_value,
.get_function = qcom_gpio_get_function,
+ .xlate = qcom_gpio_xlate,
};
static int qcom_gpio_probe(struct udevice *dev)
{
--
2.43.1
[PATCH v5 08/39] serial: msm: fix clock handling and pinctrl
Use the modern helpers to fetch the clock and use the correct property
("clocks" instead of "clock"). Drop the call to pinctrl_select_state()
as no boards have a "uart" pinctrl state and this prints confusing
errors.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 3 ++-
arch/arm/dts/dragonboard820c.dts | 3 ++-
drivers/serial/serial_msm.c | 25 +
3 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 02c824d0226c..c395e6cc0427 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -83,9 +83,10 @@
serial@78b {
compatible = "qcom,msm-uartdm-v1.4";
reg = <0x78b 0x200>;
- clock = < 4>;
+ clocks = < 4>;
+ clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <_uart>;
};
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 146a0af8aafe..86b7f83d36d6 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -77,9 +77,10 @@
blsp2_uart2: serial@75b {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b 0x1000>;
- clock = < 4>;
+ clocks = < 4>;
+ clock-names = "core";
pinctrl-names = "uart";
pinctrl-0 = <_uart>;
};
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index 44b93bd7ff21..ac4280c6c4c2 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -159,31 +159,16 @@ static const struct dm_serial_ops msm_serial_ops = {
static int msm_uart_clk_init(struct udevice *dev)
{
uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
"clock-frequency", 115200);
- uint clkd[2]; /* clk_id and clk_no */
- int clk_offset;
- struct udevice *clk_dev;
struct clk clk;
int ret;
- ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
- clkd, 2);
- if (ret)
- return ret;
-
- clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
- if (clk_offset < 0)
- return clk_offset;
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, _dev);
- if (ret)
- return ret;
-
- clk.id = clkd[1];
- ret = clk_request(clk_dev, );
- if (ret < 0)
+ ret = clk_get_by_name(dev, "core", );
+ if (ret < 0) {
+ pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
return ret;
+ }
ret = clk_set_rate(, clk_rate);
if (ret < 0)
return ret;
@@ -217,9 +202,8 @@ static int msm_serial_probe(struct udevice *dev)
ret = msm_uart_clk_init(dev);
if (ret)
return ret;
- pinctrl_select_state(dev, "uart");
uart_dm_init(priv);
return 0;
}
@@ -250,8 +234,9 @@ U_BOOT_DRIVER(serial_msm) = {
.of_to_plat = msm_serial_of_to_plat,
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops= _serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_MSM
--
2.43.1
[PATCH v5 07/39] serial: msm: add debug UART
Introduce support for early debugging. This relies on the previous stage
bootloader to initialise the UART clocks, when running with U-Boot as
the primary bootloader this feature doesn't work. It will require a way
to configure the clocks before the driver model is available.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
drivers/serial/Kconfig | 8
drivers/serial/serial_msm.c | 37 +
2 files changed, 45 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 26460c4e0cab..fbd351a47859 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -318,8 +318,16 @@ config DEBUG_UART_S5P
Select this to enable a debug UART using the serial_s5p driver. You
will need to provide parameters to make this work. The driver will
be available until the real driver-model serial is running.
+config DEBUG_UART_MSM
+ bool "Qualcomm QUP UART debug"
+ depends on ARCH_SNAPDRAGON
+ help
+ Select this to enable a debug UART using the serial_msm driver. You
+ will need to provide parameters to make this work. The driver will
+ be available until the real driver-model serial is running.
+
config DEBUG_UART_MSM_GENI
bool "Qualcomm snapdragon"
depends on ARCH_SNAPDRAGON
help
diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c
index f4d96313b931..44b93bd7ff21 100644
--- a/drivers/serial/serial_msm.c
+++ b/drivers/serial/serial_msm.c
@@ -251,4 +251,41 @@ U_BOOT_DRIVER(serial_msm) = {
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops= _serial_ops,
};
+
+#ifdef CONFIG_DEBUG_UART_MSM
+
+static struct msm_serial_data init_serial_data = {
+ .base = CONFIG_VAL(DEBUG_UART_BASE),
+ .clk_rate = 7372800,
+};
+
+#include
+
+/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916
*/
+//int apq8016_clk_init_uart(phys_addr_t gcc_base);
+
+static inline void _debug_uart_init(void)
+{
+ /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on
MSM8916 */
+ //apq8016_clk_init_uart(0x180);
+ uart_dm_init(_serial_data);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+ struct msm_serial_data *priv = _serial_data;
+
+ while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
+ !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
+ ;
+
+ writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
+
+ writel(1, priv->base + UARTDM_NCF_TX);
+ writel(ch, priv->base + UARTDM_TF);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
--
2.43.1
[PATCH v5 05/39] clk/qcom: use upstream compatible properties
Adjust the apq8016 and apq8096 drivers to use the upstream compatible
properties, and adjust the associated dts files in U-Boot.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 2 +-
drivers/clk/qcom/clock-apq8016.c | 2 +-
drivers/clk/qcom/clock-apq8096.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 6a4e3ccf17b1..02c824d0226c 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -74,9 +74,9 @@
bias-disable;
};
};
clkc: qcom,gcc@180 {
- compatible = "qcom,gcc-apq8016";
+ compatible = "qcom,gcc-msm8916";
reg = <0x180 0x8>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index c0ce570edc79..0af7191cff52 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -144,9 +144,9 @@ static struct msm_clk_data apq8016_clk_data = {
};
static const struct udevice_id gcc_apq8016_of_match[] = {
{
- .compatible = "qcom,gcc-apq8016",
+ .compatible = "qcom,gcc-msm8916",
.data = (ulong)_clk_data,
},
{ }
};
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index cf1a347309a5..1e6fdb5cd42d 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -122,9 +122,9 @@ static struct msm_clk_data apq8096_clk_data = {
};
static const struct udevice_id gcc_apq8096_of_match[] = {
{
- .compatible = "qcom,gcc-apq8096",
+ .compatible = "qcom,gcc-msm8996",
.data = (ulong)_clk_data,
},
{ }
};
--
2.43.1
[PATCH v5 06/39] clock/qcom: qcs404: fix clk_set_rate
We should be returning the rate that we set the clock to, drivers like
MMC rely on this. So fix it.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
drivers/clk/qcom/clock-qcs404.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c
index f5b352803927..958312b88842 100644
--- a/drivers/clk/qcom/clock-qcs404.c
+++ b/drivers/clk/qcom/clock-qcs404.c
@@ -192,26 +192,20 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong
rate)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
case GCC_BLSP1_UART2_APPS_CLK:
- /* UART: 115200 */
+ /* UART: 1843200Hz for a fixed 115200 baudrate (1920 *
(12/125)) */
clk_rcg_set_rate_mnd(priv->base, _regs, 0, 12, 125,
CFG_CLK_SRC_CXO, 16);
clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
- break;
- case GCC_BLSP1_AHB_CLK:
- clk_enable_vote_clk(priv->base, _blsp1_ahb_clk);
- break;
+ return 1843200;
case GCC_SDCC1_APPS_CLK:
/* SDCC1: 200MHz */
clk_rcg_set_rate_mnd(priv->base, _regs, 7, 0, 0,
CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, _vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
- break;
- case GCC_SDCC1_AHB_CLK:
- clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
- break;
+ return rate;
case GCC_ETH_RGMII_CLK:
if (rate == 25000)
clk_rcg_set_rate_mnd(priv->base, _regs, 3, 0, 0,
CFG_CLK_SRC_GPLL1, 8);
@@ -223,13 +217,17 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong
rate)
CFG_CLK_SRC_GPLL1, 8);
else if (rate == 500)
clk_rcg_set_rate_mnd(priv->base, _regs, 3, 1, 50,
CFG_CLK_SRC_GPLL1, 8);
- break;
- default:
- return 0;
+ return rate;
}
+ /* There is a bug only seeming to affect this board where the MMC
driver somehow calls
+* clk_set_rate() on a clock with id 0 which is associated with the
qcom_clk device.
+* The only clock with ID 0 is the xo_board clock which should not be
associated with
+* this device...
+*/
+ log_debug("Unknown clock id %ld\n", clk->id);
return 0;
}
static int qcs404_clk_enable(struct clk *clk)
@@ -304,8 +302,11 @@ static int qcs404_clk_enable(struct clk *clk)
clk_enable_cbc(priv->base + BLSP1_QUP4_I2C_APPS_CBCR);
clk_rcg_set_rate(priv->base, _qup4_i2c_apps_regs, 0,
CFG_CLK_SRC_CXO);
break;
+ case GCC_SDCC1_AHB_CLK:
+ clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
+ break;
default:
return 0;
}
--
2.43.1
[PATCH v5 03/39] mmc: msm_sdhci: use modern clock handling
Use the clk_* helper functions and the correct property name for clocks.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
drivers/mmc/msm_sdhci.c | 69 +
1 file changed, 47 insertions(+), 22 deletions(-)
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index fe1e754bfde0..059cb3da77c5 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -43,8 +43,9 @@ struct msm_sdhc_plat {
struct msm_sdhc {
struct sdhci_host host;
void *base;
+ struct clk_bulk clks;
};
struct msm_sdhc_variant_info {
bool mci_removed;
@@ -53,37 +54,59 @@ struct msm_sdhc_variant_info {
DECLARE_GLOBAL_DATA_PTR;
static int msm_sdc_clk_init(struct udevice *dev)
{
- int node = dev_of_offset(dev);
- uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
- 40);
- uint clkd[2]; /* clk_id and clk_no */
- int clk_offset;
- struct udevice *clk_dev;
- struct clk clk;
- int ret;
+ struct msm_sdhc *prv = dev_get_priv(dev);
+ ofnode node = dev_ofnode(dev);
+ ulong clk_rate;
+ int ret, i = 0, n_clks;
+ const char *clk_name;
- ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
+ ret = ofnode_read_u32(node, "clock-frequency", (uint *)(_rate));
if (ret)
- return ret;
+ clk_rate = 40;
- clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
- if (clk_offset < 0)
- return clk_offset;
-
- ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, _dev);
- if (ret)
+ ret = clk_get_bulk(dev, >clks);
+ if (ret) {
+ log_warning("Couldn't get mmc clocks: %d\n", ret);
return ret;
+ }
- clk.id = clkd[1];
- ret = clk_request(clk_dev, );
- if (ret < 0)
+ ret = clk_enable_bulk(>clks);
+ if (ret) {
+ log_warning("Couldn't enable mmc clocks: %d\n", ret);
return ret;
+ }
- ret = clk_set_rate(, clk_rate);
- if (ret < 0)
- return ret;
+ /* If clock-names is unspecified, then the first clock is the core
clock */
+ if (!ofnode_get_property(node, "clock-names", _clks)) {
+ if (!clk_set_rate(>clks.clks[0], clk_rate)) {
+ log_warning("Couldn't set core clock rate: %d\n", ret);
+ return -EINVAL;
+ }
+ }
+
+ /* Find the index of the "core" clock */
+ while (i < n_clks) {
+ ofnode_read_string_index(node, "clock-names", i, _name);
+ if (!strcmp(clk_name, "core"))
+ break;
+ i++;
+ }
+
+ if (i >= prv->clks.count) {
+ log_warning("Couldn't find core clock (index %d but only have
%d clocks)\n", i,
+ prv->clks.count);
+ return -EINVAL;
+ }
+
+ /* The clock is already enabled by the clk_bulk above */
+ clk_rate = clk_set_rate(>clks.clks[i], clk_rate);
+ /* If we get a rate of 0 then something has probably gone wrong. */
+ if (clk_rate == 0 || IS_ERR((void *)clk_rate)) {
+ log_warning("Couldn't set MMC core clock rate: %dE\n", clk_rate
? (int)PTR_ERR((void *)clk_rate) : 0);
+ return -EINVAL;
+ }
return 0;
}
@@ -186,8 +209,10 @@ static int msm_sdc_remove(struct udevice *dev)
/* Disable host-controller mode */
if (!var_info->mci_removed)
writel(0, priv->base + SDCC_MCI_HC_MODE);
+ clk_release_bulk(>clks);
+
return 0;
}
static int msm_of_to_plat(struct udevice *dev)
--
2.43.1
[PATCH v5 04/39] dt-bindings: drop msm_sdhci binding
The upstream DT is supported here, so drop the U-Boot specific binding
docs.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
doc/device-tree-bindings/mmc/msm_sdhci.txt | 25 -
1 file changed, 25 deletions(-)
diff --git a/doc/device-tree-bindings/mmc/msm_sdhci.txt
b/doc/device-tree-bindings/mmc/msm_sdhci.txt
deleted file mode 100644
index 08a290c66931..
--- a/doc/device-tree-bindings/mmc/msm_sdhci.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm Snapdragon SDHCI controller
-
-Required properties:
-- compatible : "qcom,sdhci-msm-v4"
-- reg: Base address and length of registers:
- - Host controller registers (SDHCI)
- - SD Core registers
-- clock: interface clock (must accept SD bus clock as a frequency)
-
-Optional properties:
-- index: If there is more than one controller - controller index (required
- by generic SDHCI code).
-- bus_width: Width of SD/eMMC bus (default 4)
-- clock-frequency: Frequency of SD/eMMC bus (default 400 kHz)
-
-Example:
-
-sdhci@07864000 {
- compatible = "qcom,sdhci-msm-v4";
- reg = <0x7864900 0x11c 0x7864000 0x800>;
- index = <0x1>;
- bus-width = <0x4>;
- clock = < 1>;
- clock-frequency = <2>;
-};
--
2.43.1
[PATCH v5 00/39] Qualcomm generic board support
Historically, Qualcomm boards in U-Boot have all had their own
board/qualcomm/xyz directory, their own CONFIG_TARGET_XYZ option, their
own hardcoded sysmap-xyz.c file, and their own U-Boot specific
devicetree with little/no compatibility with upstream DT.
This series makes a few final prepatory changes, and then replaces
almost all of the board specific code with generic alternatives. The end
result is that all Qualcomm boards both current and future (with the
exception of the db410c and db820c) can be supported by a single U-Boot
binary by just providing the correct DT. New boards can be added without
introducing any addition mach/ or board/ code or config options.
Due to the nature of this change, the patch ("mach-snapdragon:
generalise board support") has become pretty big, I tried a few
different ways to represent this in git history, but the other methods
(e.g. adding a stub "generic" target and removing it again) were more
confusing and made for much messier git history. The current patch is
mostly atomic, but requires regenerating the config.
The QCS404 EVB board had some code to enable the USB VBUS regulator,
this is dropped in favour of a adding a new vbus-supply property to the
dwc3-generic driver. This will also be used by the dragonboard845c in a
future patch. This handles the common case of a board requiring some
regulator be enabled for USB host mode.
A more detailed description of the changes is below.
== Memory map ==
The memory map was historically hardcoded into U-Boot, this meant that
U-Boot had to be built for a specific variant of a device. This is
changed to instead read the memory map from the DT /memory node.
Additionally, most boards mapped addresss 0x0 as valid, as a result if a
null pointer access happens then it will cause a bus stall (and board
hang). This is fixed so that null pointer accesses will now correctly
throw an exception.
== DT loading ==
Previously, boards used the FDT blob embedded into U-Boot (via
OF_SEPARATE). However, most Qualcomm boards run U-Boot as a secondary
bootloader, so we can instead rely on the first-stage bootloader to
populate some useful FDT properties for us (notably the /memory node and
KASLR seed) and fetch the DTB that it provides. Combined with the memory
map changes above, this let's us entirely avoid configuring the memory
map explicitly.
== defconfig ==
Most of the board defconfigs and config headers were quite similar, to
simplify maintenance going forward, all the fully generic boards (sdm845
and qcs404-evb so far) are adapted to use the new qcom_defconfig. Going
forward, all new Qualcomm boards should be supported by this defconfig.
A notable exception is for specific usecases (like U-Boot as the primary
bootloader).
== The older dragonboards ==
The db410c and db820c both have some custom board init code, as a result
they aren't yet binary compatible. mach-snapdragon is adjusted so
that all the necessary config options (e.g. CONFIG_SYS_BOARD) can be set
from their defconfigs, this makes it possible to enable support for new
boards without introducing additional config options.
The db410c can run U-Boot either chainloaded like the other boards, or
as a first-stage bootloader replacing aboot. However it was hardcoded to
only build for the latter option. This series introduces a new
"chainloaded" defconfig to enable easier testing via fastboot.
== dynamic environment variables ==
This series also introduces runtime-allocated load addresses via the lmb
allocator. This allows for booting on boards with vastly different
memory layouts without any pre-calculation or macro magic in the config
header. This feature is based on similar code in mach-apple.
The soc, board, and fdtfile environment variables are also generated
automatically. Many Qualcomm boards follow a similar scheme for DTB
naming such that the name can often be derived from the root compatible
properties. This is intended to cover the most common cases and be a
simple solution for booting generic distro images without having to
explicitly choose the right DTB. The U-Boot DTS can be tweaked if
necessary to produce the correct name, the variable can be overwritten,
or a bootloader like GRUB can load the devicetree instead.
== Upstream DT ==
All Qualcomm boards have had their devicetree files replaced with the
upstream versions. Previous patch series made the necessary driver
adjustments to fully support the upstream DT format. All future
Qualcomm boards should use upstream DTS by default.
Once Sumit's work to import dt-rebasing has been merged, we will drop
the imported DT and bindings again.
---
I have tested this series on the Dragonboard410c, Dragonboard820c, and
Dragonboard845c. Sumit has tested this on the db410c and QCS404 EVB
board.
---
Changes in v5:
- Adjust msm_sdhci clock handling patch to have clearer error handling based on
feedback from Dan.
- Adjust dwc3 vbus-supply patch to be more readable and handle error
paths better based on feedback from
[PATCH v5 02/39] usb: dwc3-generic: support external vbus regulator
Add support for a vbus-supply regulator specified in devicetree. This
provides generic support to avoid hardcoded GPIO configuration in board
init code.
Reviewed-by: Neil Armstrong
Signed-off-by: Caleb Connolly
---
Cc: Marek Vasut
---
drivers/usb/dwc3/dwc3-generic.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 6fb2de8a5ace..a379a0002e77 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -20,8 +20,9 @@
#include
#include
#include
#include
+#include
#include
#include "core.h"
#include "gadget.h"
#include
@@ -46,8 +47,9 @@ struct dwc3_generic_priv {
struct dwc3_generic_host_priv {
struct xhci_ctrl xhci_ctrl;
struct dwc3_generic_priv gen_priv;
+ struct udevice *vbus_supply;
};
static int dwc3_generic_probe(struct udevice *dev,
struct dwc3_generic_priv *priv)
@@ -239,23 +241,39 @@ static int dwc3_generic_host_probe(struct udevice *dev)
rc = dwc3_generic_probe(dev, >gen_priv);
if (rc)
return rc;
+ rc = device_get_supply_regulator(dev, "vbus-supply",
>vbus_supply);
+ if (rc)
+ debug("%s: No vbus regulator found: %d\n", dev->name, rc);
+
+ /* Only returns an error if regulator is valid and failed to enable due
to a driver issue */
+ rc = regulator_set_enable_if_allowed(priv->vbus_supply, true);
+ if (rc)
+ return rc;
+
hccr = (struct xhci_hccr *)priv->gen_priv.base;
hcor = (struct xhci_hcor *)(priv->gen_priv.base +
HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
- return xhci_register(dev, hccr, hcor);
+ rc = xhci_register(dev, hccr, hcor);
+ if (rc)
+ regulator_set_enable_if_allowed(priv->vbus_supply, false);
+
+ return rc;
}
static int dwc3_generic_host_remove(struct udevice *dev)
{
struct dwc3_generic_host_priv *priv = dev_get_priv(dev);
int rc;
- rc = xhci_deregister(dev);
+ /* This function always returns 0 */
+ xhci_deregister(dev);
+
+ rc = regulator_set_enable_if_allowed(priv->vbus_supply, false);
if (rc)
- return rc;
+ debug("%s: Failed to disable vbus regulator: %d\n", dev->name,
rc);
return dwc3_generic_remove(dev, >gen_priv);
}
--
2.43.1
[PATCH v5 01/39] arm: init: export prev_bl_fdt_addr
When booting U-Boot on board with a locked down first-stage bootloader,
we emulate the Linux boot header. By passing the U-Boot FDT through this
first-stage bootloader and retrieving it afterwards we can pre-populate
the memory nodes and other info like the KASLR address.
Add a function to export the FDT addr so that boards can use it over the
built-in FDT.
Don't check is_addr_accessible() here because we might not yet have a
valid mem_map if it's going to be populated from the FDT, let the board
do their own validation instead.
Reviewed-by: Tom Rini
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg #qcs404
Signed-off-by: Caleb Connolly
---
arch/arm/lib/save_prev_bl_data.c | 5 +
include/init.h | 11 +++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c
index f7b23faf0d66..b286bac9bf00 100644
--- a/arch/arm/lib/save_prev_bl_data.c
+++ b/arch/arm/lib/save_prev_bl_data.c
@@ -44,8 +44,13 @@ bool is_addr_accessible(phys_addr_t addr)
return false;
}
+phys_addr_t get_prev_bl_fdt_addr(void)
+{
+ return reg0;
+}
+
int save_prev_bl_data(void)
{
struct fdt_header *fdt_blob;
int node;
diff --git a/include/init.h b/include/init.h
index 9a1951d10a01..630d86729c4e 100644
--- a/include/init.h
+++ b/include/init.h
@@ -167,8 +167,19 @@ defined(CONFIG_SAVE_PREV_BL_FDT_ADDR)
*
* Return: 0 if ok; -ENODATA on error
*/
int save_prev_bl_data(void);
+
+/**
+ * get_prev_bl_fdt_addr - When u-boot is chainloaded, get the address
+ * of the FDT passed by the previous bootloader.
+ *
+ * Return: the address of the FDT passed by the previous bootloader
+ * or 0 if not found.
+ */
+phys_addr_t get_prev_bl_fdt_addr(void);
+#else
+#define get_prev_bl_fdt_addr() 0LLU
#endif
/**
* cpu_secondary_init_r() - CPU-specific secondary initialization
--
2.43.1
[PATCH 1/1] serial: move sbi_dbcn_available to .data section
U-Boot SPL loads the device-tree directly behind main U-Boot overlapping
the .bss section. reserve_fdt() is called in board_init_f() to relocate the
device-tree to a safe location.
Debug UARTs are enabled before board_init_f(). With sbi_dbcn_available in
the .bss section the device-tree is corrupted when _debug_uart_init() is
called in the SBI serial driver. Move the variable to the .data section.
Link: https://bugs.launchpad.net/ubuntu/+source/u-boot/+bug/2054091
Fixes: dfe08374943c ("risc-v: implement DBCN based debug console")
Signed-off-by: Heinrich Schuchardt
---
drivers/serial/serial_sbi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c
index a51a96c1ef0..f3ecfccab43 100644
--- a/drivers/serial/serial_sbi.c
+++ b/drivers/serial/serial_sbi.c
@@ -17,7 +17,7 @@ static inline void _debug_uart_putc(int c)
#else
-static int sbi_dbcn_available;
+static int sbi_dbcn_available __section(".data");
static inline void _debug_uart_init(void)
{
--
2.43.0
[PATCH] arm64: zynqmp: Remove snps,enable_guctl1_ipd_quirk property
Remove undocumented DT property. Suggested solution was to apply quirk via glue logic driver that's why make no sense to have it listed in DT. Signed-off-by: Michal Simek --- For more information please take a look at: https://lore.kernel.org/r/1708023665-1441674-1-git-send-email-radhey.shyam.pan...@amd.com https://lore.kernel.org/r/1708717523-4006664-1-git-send-email-radhey.shyam.pan...@amd.com --- arch/arm/dts/zynqmp.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index b50b83b7723f..daae23c12b79 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1008,7 +1008,6 @@ /* iommus = < 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; @@ -1040,7 +1039,6 @@ /* iommus = < 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; clock-names = "ref"; - snps,enable_guctl1_ipd_quirk; snps,resume-hs-terminations; /* dma-coherent; */ }; -- 2.36.1
