RE: [PATCH 1/2] clk: clk-imx8qxp: Add LPUART IPG entries
On 09.03.2024 01:15, Peng Fan wrote:
> > Subject: [PATCH 1/2] clk: clk-imx8qxp: Add LPUART IPG entries
> >
> > Since commit cc7df0b9e8bc ("serial: lpuart: Enable IPG clock") the colibri-
> > imx8qxp board no longer boots.
> >
> > The reason is that the imx8qxp clock driver does not handle the LPUART IPG
> > clocks inside get_rate(), set_rate() and enable() functions.
> >
> > Fix the boot regression by adding the LPUART IPG entries.
> >
> > Fixes: cc7df0b9e8bc ("serial: lpuart: Enable IPG clock")
> > Reported-by: Marcel Ziswiler
> > Signed-off-by: Fabio Estevam
>
> Reviewed-by: Peng Fan
Tested-by: Hiago De Franco # Toradex Colibri iMX8X
> > ---
> > drivers/clk/imx/clk-imx8qxp.c | 13 -
> > 1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> > index 8bf7e325481..d900d4cd528 100644
> > --- a/drivers/clk/imx/clk-imx8qxp.c
> > +++ b/drivers/clk/imx/clk-imx8qxp.c
> > @@ -88,20 +88,23 @@ ulong imx8_clk_get_rate(struct clk *clk)
> > resource = SC_R_SDHC_1;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > - case IMX8QXP_UART0_IPG_CLK:
> > case IMX8QXP_UART0_CLK:
> > + case IMX8QXP_UART0_IPG_CLK:
> > resource = SC_R_UART_0;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART1_CLK:
> > + case IMX8QXP_UART1_IPG_CLK:
> > resource = SC_R_UART_1;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART2_CLK:
> > + case IMX8QXP_UART2_IPG_CLK:
> > resource = SC_R_UART_2;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART3_CLK:
> > + case IMX8QXP_UART3_IPG_CLK:
> > resource = SC_R_UART_3;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > @@ -170,18 +173,22 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned
> > long rate)
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART0_CLK:
> > + case IMX8QXP_UART0_IPG_CLK:
> > resource = SC_R_UART_0;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART1_CLK:
> > + case IMX8QXP_UART1_IPG_CLK:
> > resource = SC_R_UART_1;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART2_CLK:
> > + case IMX8QXP_UART2_IPG_CLK:
> > resource = SC_R_UART_2;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART3_CLK:
> > + case IMX8QXP_UART3_IPG_CLK:
> > resource = SC_R_UART_3;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > @@ -263,18 +270,22 @@ int __imx8_clk_enable(struct clk *clk, bool enable)
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART0_CLK:
> > + case IMX8QXP_UART0_IPG_CLK:
> > resource = SC_R_UART_0;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART1_CLK:
> > + case IMX8QXP_UART1_IPG_CLK:
> > resource = SC_R_UART_1;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART2_CLK:
> > + case IMX8QXP_UART2_IPG_CLK:
> > resource = SC_R_UART_2;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > case IMX8QXP_UART3_CLK:
> > + case IMX8QXP_UART3_IPG_CLK:
> > resource = SC_R_UART_3;
> > pm_clk = SC_PM_CLK_PER;
> > break;
> > --
> > 2.34.1
>
[PATCH] sunxi: h616: add initial support for T95 AXP313 TV Box
T95 is a most commonly known for being a box with a pre-installed malware.
It uses Allwinner H616 and comes with eMMC and DDR3 memory.
This device comes with two versions - one with AXP305 PMIC and another with
AXP313 PMIC.
The AXP313 version comes with Secure Boot enabled and locked bootloader, so the
u-boot has to be built with TOC0.
DRAM settings are taken from Allwinner's boot0 for this box.
Cc: Andre Przywara
Signed-off-by: Kamil Kasperski
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/sun50i-h616-t95-axp313.dts | 148
configs/t95_axp313_defconfig| 27 +
3 files changed, 177 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun50i-h616-t95-axp313.dts
create mode 100644 configs/t95_axp313_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b102ffb5f6..144daf6c48 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -842,7 +842,8 @@ dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h618-orangepi-zero2w.dtb \
sun50i-h618-orangepi-zero3.dtb \
sun50i-h618-transpeed-8k618-t.dtb \
- sun50i-h616-x96-mate.dtb
+ sun50i-h616-x96-mate.dtb \
+ sun50i-h616-t95-axp313.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \
diff --git a/arch/arm/dts/sun50i-h616-t95-axp313.dts
b/arch/arm/dts/sun50i-h616-t95-axp313.dts
new file mode 100644
index 00..b006f363d5
--- /dev/null
+++ b/arch/arm/dts/sun50i-h616-t95-axp313.dts
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Arm Ltd.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h616.dtsi"
+
+#include
+#include
+
+/ {
+ model = "T95 (AXP313)";
+ compatible = "mbox,t95-axp313", "allwinner,sun50i-h616";
+
+ aliases {
+ serial0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc5v: vcc5v {
+ /* board wide 5V supply directly from the DC input */
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-5v";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ cd-gpios = < 8 16 GPIO_ACTIVE_LOW>; /* PI16 */
+ vmmc-supply = <_dldo1>;
+ status = "okay";
+};
+
+ {
+ vmmc-supply = <_dldo1>;
+ vqmmc-supply = <_aldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+_i2c {
+ status = "okay";
+
+ axp313: pmic@36 {
+ compatible = "x-powers,axp313a";
+ reg = <0x36>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>; /* PC9 */
+
+ vin1-supply = <_vcc5v>;
+ vin2-supply = <_vcc5v>;
+ vin3-supply = <_vcc5v>;
+
+ regulators {
+ /* Supplies VCC-PLL, so needs to be always on. */
+ reg_aldo1: aldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-name = "vcc1v8";
+ };
+
+ /* Supplies VCC-IO, so needs to be always on. */
+ reg_dldo1: dldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-name = "vcc3v3";
+ };
+
+ reg_dcdc1: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <81>;
+ regulator-max-microvolt = <99>;
+ regulator-name = "vdd-gpu-sys";
+ };
+
+ reg_dcdc2: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <81>;
+ regulator-max-microvolt = <110>;
+ regulator-name = "vdd-cpu";
+ };
+
+ reg_dcdc3: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <136>;
+ regulator-max-microvolt = <136>;
+
[PATCH v2 3/3] configs: milkv_duo: Add SD card configs
Add configs related to sdhci and mmc for Sophgo Milk-V Duo board Signed-off-by: Kongyang Liu --- (no changes since v1) configs/milkv_duo_defconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/configs/milkv_duo_defconfig b/configs/milkv_duo_defconfig index 548adf174c..e8413d7aa9 100644 --- a/configs/milkv_duo_defconfig +++ b/configs/milkv_duo_defconfig @@ -17,6 +17,16 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=544 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="milkv_duo# " +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y +CONFIG_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_CV1800B=y CONFIG_SYS_NS16550=y CONFIG_SYS_NS16550_MEM32=y -- 2.41.0
[PATCH v2 2/3] riscv: dts: sophgo: Add clk node and sdhci node
Add clk node and sdhci node for cv18xx SoCs according to patches from Linux
kernel.
clk:
https://lore.kernel.org/all/ia1pr20mb4953f9ad6792013b54636f05bb...@ia1pr20mb4953.namprd20.prod.outlook.com/
sdhci: https://lore.kernel.org/all/20240217144826.3944-1-jszh...@kernel.org/
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Sync device tree with ptaches from Linux kernel
arch/riscv/dts/cv1800b-milkv-duo.dts | 8
arch/riscv/dts/cv1800b.dtsi | 4
arch/riscv/dts/cv18xx.dtsi | 22 ++
3 files changed, 34 insertions(+)
diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts
b/arch/riscv/dts/cv1800b-milkv-duo.dts
index 3af9e34b3b..94e64ddce8 100644
--- a/arch/riscv/dts/cv1800b-milkv-duo.dts
+++ b/arch/riscv/dts/cv1800b-milkv-duo.dts
@@ -33,6 +33,14 @@
clock-frequency = <2500>;
};
+ {
+ status = "okay";
+ bus-width = <4>;
+ no-1-8-v;
+ no-mmc;
+ no-sdio;
+};
+
{
status = "okay";
};
diff --git a/arch/riscv/dts/cv1800b.dtsi b/arch/riscv/dts/cv1800b.dtsi
index 165e9e320a..baf641829e 100644
--- a/arch/riscv/dts/cv1800b.dtsi
+++ b/arch/riscv/dts/cv1800b.dtsi
@@ -16,3 +16,7 @@
{
compatible = "sophgo,cv1800b-clint", "thead,c900-clint";
};
+
+ {
+ compatible = "sophgo,cv1800-clk";
+};
diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi
index 2d6f4a4b1e..ec99c4deeb 100644
--- a/arch/riscv/dts/cv18xx.dtsi
+++ b/arch/riscv/dts/cv18xx.dtsi
@@ -45,6 +45,13 @@
#clock-cells = <0>;
};
+ sdhci_clk: sdhci-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <37500>;
+ clock-output-names = "sdhci_clk";
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <>;
@@ -53,6 +60,12 @@
dma-noncoherent;
ranges;
+ clk: clock-controller@3002000 {
+ reg = <0x03002000 0x1000>;
+ clocks = <>;
+ #clock-cells = <1>;
+ };
+
gpio0: gpio@302 {
compatible = "snps,dw-apb-gpio";
reg = <0x302 0x1000>;
@@ -175,6 +188,15 @@
status = "disabled";
};
+ sdhci0: mmc@431 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+ reg = <0x431 0x1000>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <_clk>;
+ clock-names = "core";
+ status = "disabled";
+ };
+
plic: interrupt-controller@7000 {
reg = <0x7000 0x400>;
interrupts-extended = <_intc 11>, <_intc 9>;
--
2.41.0
[PATCH v2 1/3] mmc: cv1800b: Add sdhci driver support for cv1800b SoC
Add sdhci driver for cv1800b SoC.
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Refactored and simplified some of the code.
drivers/mmc/Kconfig | 13
drivers/mmc/Makefile| 1 +
drivers/mmc/cv1800b_sdhci.c | 116
3 files changed, 130 insertions(+)
create mode 100644 drivers/mmc/cv1800b_sdhci.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index cef05790dd..f7fe6d1042 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -568,6 +568,19 @@ config MMC_SDHCI_CADENCE
If unsure, say N.
+config MMC_SDHCI_CV1800B
+ bool "SDHCI support for the CV1800B SD/SDIO/eMMC controller"
+ depends on BLK && DM_MMC
+ depends on MMC_SDHCI
+ depends on OF_CONTROL
+ help
+ This selects the CV1800B SD/SDIO/eMMC driver.
+
+ If you have a controller with this interface,
+ say Y here.
+
+ If unsure, say N.
+
config MMC_SDHCI_AM654
bool "SDHCI Controller on TI's Am654 devices"
depends on ARCH_K3
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index e9cf1fcc64..3374321e29 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_MMC_SDHCI_ATMEL) += atmel_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCM2835)+= bcm2835_sdhci.o
obj-$(CONFIG_MMC_SDHCI_BCMSTB) += bcmstb_sdhci.o
obj-$(CONFIG_MMC_SDHCI_CADENCE)+= sdhci-cadence.o
+obj-$(CONFIG_MMC_SDHCI_CV1800B)+= cv1800b_sdhci.o
obj-$(CONFIG_MMC_SDHCI_AM654) += am654_sdhci.o
obj-$(CONFIG_MMC_SDHCI_IPROC) += iproc_sdhci.o
obj-$(CONFIG_MMC_SDHCI_KONA) += kona_sdhci.o
diff --git a/drivers/mmc/cv1800b_sdhci.c b/drivers/mmc/cv1800b_sdhci.c
new file mode 100644
index 00..2275c53777
--- /dev/null
+++ b/drivers/mmc/cv1800b_sdhci.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+#include
+#include
+#include
+
+#define SDHCI_PHY_TX_RX_DLY 0x240
+#define MMC_MAX_CLOCK37500
+#define TUNE_MAX_PHCODE 128
+
+struct cv1800b_sdhci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+static void cv1800b_set_tap_delay(struct sdhci_host *host, u16 tap)
+{
+ sdhci_writel(host, tap << 16, SDHCI_PHY_TX_RX_DLY);
+}
+
+static void cv1800b_sdhci_reset(struct sdhci_host *host, u8 mask)
+{
+ sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
+ while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)
+ udelay(10);
+}
+
+static int cv1800b_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+ struct sdhci_host *host = dev_get_priv(mmc->dev);
+
+ u16 tap;
+
+ int current_size = 0;
+ int max_size = 0;
+ int max_window = 0;
+
+ for (tap = 0; tap < TUNE_MAX_PHCODE; tap++) {
+ cv1800b_set_tap_delay(host, tap);
+
+ if (mmc_send_tuning(host->mmc, opcode, NULL)) {
+ current_size = 0;
+ } else {
+ current_size++;
+ if (current_size > max_size) {
+ max_size = current_size;
+ max_window = tap;
+ }
+ }
+ }
+
+ cv1800b_sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+
+ cv1800b_set_tap_delay(host, max_window - max_size / 2);
+
+ return 0;
+}
+
+const struct sdhci_ops cv1800b_sdhci_sd_ops = {
+ .platform_execute_tuning = cv1800b_execute_tuning,
+};
+
+static int cv1800b_sdhci_bind(struct udevice *dev)
+{
+ struct cv1800b_sdhci_plat *plat = dev_get_plat(dev);
+
+ return sdhci_bind(dev, >mmc, >cfg);
+}
+
+static int cv1800b_sdhci_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct cv1800b_sdhci_plat *plat = dev_get_plat(dev);
+ struct sdhci_host *host = dev_get_priv(dev);
+ int ret;
+
+ host->name = dev->name;
+ host->ioaddr = devfdt_get_addr_ptr(dev);
+
+ upriv->mmc = >mmc;
+ host->mmc = >mmc;
+ host->mmc->priv = host;
+ host->mmc->dev = dev;
+ host->ops = _sdhci_sd_ops;
+ host->max_clk = MMC_MAX_CLOCK;
+
+ ret = mmc_of_parse(dev, >cfg);
+ if (ret)
+ return ret;
+
+ ret = sdhci_setup_cfg(>cfg, host, 0, 20);
+ if (ret)
+ return ret;
+
+ return sdhci_probe(dev);
+}
+
+static const struct udevice_id cv1800b_sdhci_match[] = {
+ { .compatible = "sophgo,cv1800b-dwcmshc" },
+ { }
+};
+
+U_BOOT_DRIVER(cv1800b_sdhci) = {
+ .name = "sdhci-cv1800b",
+ .id = UCLASS_MMC,
+ .of_match = cv1800b_sdhci_match,
+ .bind = cv1800b_sdhci_bind,
+ .probe = cv1800b_sdhci_probe,
+ .priv_auto = sizeof(struct sdhci_host),
+ .plat_auto = sizeof(struct cv1800b_sdhci_plat),
+ .ops = _ops,
+};
--
2.41.0
[PATCH v2 0/3] mmc: sophgo: milkv_duo: Add SD card support for Milk-V Duo board
This series add sdhci driver for cv1800b SoC and enable SD card support for Sophgo Milk-V Duo board. Changes in v2: - Refactored and simplified some of the code. - Sync device tree with ptaches from Linux kernel Kongyang Liu (3): mmc: cv1800b: Add sdhci driver support for cv1800b SoC riscv: dts: sophgo: Add clk node and sdhci node configs: milkv_duo: Add SD card configs arch/riscv/dts/cv1800b-milkv-duo.dts | 8 ++ arch/riscv/dts/cv1800b.dtsi | 4 + arch/riscv/dts/cv18xx.dtsi | 22 + configs/milkv_duo_defconfig | 10 +++ drivers/mmc/Kconfig | 13 +++ drivers/mmc/Makefile | 1 + drivers/mmc/cv1800b_sdhci.c | 116 +++ 7 files changed, 174 insertions(+) create mode 100644 drivers/mmc/cv1800b_sdhci.c -- 2.41.0
[PATCH v2 2/2] riscv: cache: Implement dcache for cv1800b
Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.
Signed-off-by: Kongyang Liu
---
(no changes since v1)
arch/riscv/cpu/cv1800b/Makefile | 1 +
arch/riscv/cpu/cv1800b/cache.c | 45 +
2 files changed, 46 insertions(+)
create mode 100644 arch/riscv/cpu/cv1800b/cache.c
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
index da12e0f64e..95beb34b51 100644
--- a/arch/riscv/cpu/cv1800b/Makefile
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -4,3 +4,4 @@
obj-y += dram.o
obj-y += cpu.o
+obj-y += cache.o
diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/cpu/cv1800b/cache.c
new file mode 100644
index 00..b8051e29e0
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cache.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+#include
+
+/*
+ * dcache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101010 rs1 000 0 0001011
+ *
+ * dcache.cpa rs1 (clean)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101001 rs1 000 0 0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00101011 rs1 000 0 0001011
+ *
+ * sync.s
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ * 00011001 0 000 0 0001011
+ */
+#define DCACHE_IPA_A0 ".long 0x02a5000b"
+#define DCACHE_CPA_A0 ".long 0x0295000b"
+#define DCACHE_CIPA_A0 ".long 0x02b5000b"
+
+#define SYNC_S ".long 0x019b"
+
+void invalidate_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start &
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_IPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
+
+void flush_dcache_range(unsigned long start, unsigned long end)
+{
+ register unsigned long i asm("a0") = start &
~(CONFIG_SYS_CACHELINE_SIZE - 1);
+ for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
+ __asm__ __volatile__(DCACHE_CPA_A0);
+ __asm__ __volatile__(SYNC_S);
+}
--
2.41.0
[PATCH v2 1/2] riscv: cpu: cv1800b: Add support for cv1800b SoC
Add Sophgo cv1800b SoC to support RISC-V arch.
Signed-off-by: Kongyang Liu
---
Changes in v2:
- Remove duplicate code in function cleanup_before_linux
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/cv1800b/Kconfig | 12
arch/riscv/cpu/cv1800b/Makefile | 6 ++
arch/riscv/cpu/cv1800b/cpu.c| 9 +
arch/riscv/cpu/cv1800b/dram.c | 21 +
board/sophgo/milkv_duo/Kconfig | 4 ++--
6 files changed, 51 insertions(+), 2 deletions(-)
create mode 100644 arch/riscv/cpu/cv1800b/Kconfig
create mode 100644 arch/riscv/cpu/cv1800b/Makefile
create mode 100644 arch/riscv/cpu/cv1800b/cpu.c
create mode 100644 arch/riscv/cpu/cv1800b/dram.c
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ac52c5e6da..2c92b0d9f6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -93,6 +93,7 @@ source "board/xilinx/mbv/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig
new file mode 100644
index 00..7225b1210c
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+config SOPHGO_CV1800B
+ bool
+ select ARCH_EARLY_INIT_R
+ select SYS_CACHE_SHIFT_6
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
+ imply CMD_CPU
diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile
new file mode 100644
index 00..da12e0f64e
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2024, Kongyang Liu
+
+obj-y += dram.o
+obj-y += cpu.o
diff --git a/arch/riscv/cpu/cv1800b/cpu.c b/arch/riscv/cpu/cv1800b/cpu.c
new file mode 100644
index 00..233a6a3d64
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/cpu.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2024, Kongyang Liu
+ */
+
+int cleanup_before_linux(void)
+{
+ return 0;
+}
diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c
new file mode 100644
index 00..91007c0a3d
--- /dev/null
+++ b/arch/riscv/cpu/cv1800b/dram.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
diff --git a/board/sophgo/milkv_duo/Kconfig b/board/sophgo/milkv_duo/Kconfig
index 2a458f291c..040a7487f1 100644
--- a/board/sophgo/milkv_duo/Kconfig
+++ b/board/sophgo/milkv_duo/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "sophgo"
config SYS_CPU
- default "generic"
+ default "cv1800b"
config SYS_CONFIG_NAME
default "milkv_duo"
@@ -23,6 +23,6 @@ config ENV_SECT_SIZE
config BOARD_SPECIFIC_OPTIONS
def_bool y
- select GENERIC_RISCV
+ select SOPHGO_CV1800B
endif
--
2.41.0
[PATCH v2 0/2] riscv: cpu: Add support for cv1800b SoC
This series add basic support for cv1800b SoC and enable dcache support. The cv1800b utilizes CSR instructions to manipulate the first and second bits in the MHCR register (0x7C1) to indicate the activation status of icache and dcache. As the icache and dcache are already enabled in the FSBL (first stage bootloader) provided by the vendor, and the U-Boot running in S-Mode is unable to manipulate CSR registers, support for operations related to enabling, disabling, or checking the status of the cache is not provided. Changes in v2: - Remove duplicate code in function cleanup_before_linux Kongyang Liu (2): riscv: cpu: cv1800b: Add support for cv1800b SoC riscv: cache: Implement dcache for cv1800b arch/riscv/Kconfig | 1 + arch/riscv/cpu/cv1800b/Kconfig | 12 + arch/riscv/cpu/cv1800b/Makefile | 7 + arch/riscv/cpu/cv1800b/cache.c | 45 + arch/riscv/cpu/cv1800b/cpu.c| 9 +++ arch/riscv/cpu/cv1800b/dram.c | 21 +++ board/sophgo/milkv_duo/Kconfig | 4 +-- 7 files changed, 97 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/cpu/cv1800b/Kconfig create mode 100644 arch/riscv/cpu/cv1800b/Makefile create mode 100644 arch/riscv/cpu/cv1800b/cache.c create mode 100644 arch/riscv/cpu/cv1800b/cpu.c create mode 100644 arch/riscv/cpu/cv1800b/dram.c -- 2.41.0
Re: [PULL] u-boot-usb/master
On Sat, Mar 09, 2024 at 05:08:37PM +0100, Marek Vasut wrote: > Singular quirk DT property rename. Fix for master branch. > > The following changes since commit eac52e4be4e234d563d6911737ee7ccdc0ada1f1: > > Merge patch series "ARM: renesas: Rename R-Mobile to Renesas" (2024-03-02 > 14:30:25 -0500) > > are available in the Git repository at: > > git://source.denx.de/u-boot-usb.git master > > for you to fetch changes up to 52378ba4963f5f4ab2786f3d0b4e929cd6cebe22: > > usb: xhci-dwc3: Fix support for dis_enblslpm_quirk (2024-03-05 01:04:21 > +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH v2] net: phy: Use PHY MDIO address from DT if available
On Sun, 28 Jan 2024 02:19:40 +0100, Marek Vasut wrote: > In case the PHY is fully described in DT, use PHY MDIO address > from DT directly instead of always using auto-detection. This > also fixes the behavior of 'mdio list' in such DT setup, which > now prints the PHY connected to the MAC correctly. > > Applied to u-boot/master, thanks! -- Tom
Re: [PATCH] clk: Fix error message in clk_get_bulk
On Sat, Mar 9, 2024 at 6:27 AM Jan Kiszka wrote:
>
> From: Jan Kiszka
>
> Fix a logical inversion of the printed text.
>
> Signed-off-by: Jan Kiszka
> ---
Reviewed-by: Sam Protsenko
> drivers/clk/clk-uclass.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
> index ed6e60bc484..78d8ea94c65 100644
> --- a/drivers/clk/clk-uclass.c
> +++ b/drivers/clk/clk-uclass.c
> @@ -180,7 +180,7 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk
> *bulk)
> bulk_get_err:
> err = clk_release_all(bulk->clks, bulk->count);
> if (err)
> - debug("%s: could release all clocks for %p\n",
> + debug("%s: could not release all clocks for %p\n",
> __func__, dev);
>
> return ret;
> --
> 2.35.3
[PULL] u-boot-usb/master
Singular quirk DT property rename. Fix for master branch. The following changes since commit eac52e4be4e234d563d6911737ee7ccdc0ada1f1: Merge patch series "ARM: renesas: Rename R-Mobile to Renesas" (2024-03-02 14:30:25 -0500) are available in the Git repository at: git://source.denx.de/u-boot-usb.git master for you to fetch changes up to 52378ba4963f5f4ab2786f3d0b4e929cd6cebe22: usb: xhci-dwc3: Fix support for dis_enblslpm_quirk (2024-03-05 01:04:21 +0100) Jonas Karlman (1): usb: xhci-dwc3: Fix support for dis_enblslpm_quirk drivers/usb/host/xhci-dwc3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Re: [PATCH 1/2] arm64: Reduce add_map() complexity
On Sat, Mar 9, 2024 at 9:39 AM Marc Zyngier wrote: > Can you figure out what memory access is triggering it? Even at > narrowing it to the subsystem level would be a good indication. The problem happens so early that I am not able to narrow it down at subsystem level. > You could just dump the entries as they are written. The order may not > be the same, but for a given VA you should observe the same entries > being written. Does the log below help? https://pastebin.com/raw/1i1VBA0a If not, please send me a debug patch and I will be glad to run it here. Thanks
Re: [PATCH v2 5/5] power: regulator: tps65941: Add TPS65224 PMIC regulator support
On Fri, Mar 08, 2024 at 02:40:11PM +0530, Dhruva Gole wrote: > > + > > + if (val < 0 || val > mask) > > + return -EINVAL; > > Probably combine this with below if's, eitherway is fine. > > > + > > + if (val <= reg_base) > > + return base; > > + > > + if (val >= reg_max) > > + return max; > > Why all these if's when they can be elifs? > > > + This was just a cut and paste of my suggested code. I really like my code... It's like a tortoise eating the three bears' food... This is invalid. This is low. This is high. This poridge is just right. regards, dan carpenter
Re: [PATCH 1/2] arm64: Reduce add_map() complexity
On Sat, 09 Mar 2024 12:29:10 +, Fabio Estevam wrote: > > Hi Marc, > > On Sat, Mar 9, 2024 at 6:53 AM Marc Zyngier wrote: > > > It would be good to narrow down which access is generating this. It is > > an asynchronous error, so the code above won't help. > > > > Alternatively, and if you are sure that this is due to this change, > > dumping the page tables and comparing them before and after would > > help. > > Yes, I am sure the error is due to this change. It is 100% reproducible. Can you figure out what memory access is triggering it? Even at narrowing it to the subsystem level would be a good indication. > I am not familiar with this part of the code, so I would appreciate > it if you could tell me how to dump the page tables so I can compare > them before and after. You could just dump the entries as they are written. The order may not be the same, but for a given VA you should observe the same entries being written. My hunch is that the new code is a lot more picky about the alignment of things, and that could result in something being similarly unaligned. But without access to the platform nor an idea of what gets mapped, it's a bit hard to have a clue. Thanks, M. -- Without deviation from the norm, progress is not possible.
Re: [PATCH 1/2] arm64: Reduce add_map() complexity
Hi Marc, On Sat, Mar 9, 2024 at 6:53 AM Marc Zyngier wrote: > It would be good to narrow down which access is generating this. It is > an asynchronous error, so the code above won't help. > > Alternatively, and if you are sure that this is due to this change, > dumping the page tables and comparing them before and after would > help. Yes, I am sure the error is due to this change. It is 100% reproducible. I am not familiar with this part of the code, so I would appreciate it if you could tell me how to dump the page tables so I can compare them before and after. Thanks, Fabio Estevam
[PATCH] clk: Fix error message in clk_get_bulk
From: Jan Kiszka
Fix a logical inversion of the printed text.
Signed-off-by: Jan Kiszka
---
drivers/clk/clk-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index ed6e60bc484..78d8ea94c65 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -180,7 +180,7 @@ int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
bulk_get_err:
err = clk_release_all(bulk->clks, bulk->count);
if (err)
- debug("%s: could release all clocks for %p\n",
+ debug("%s: could not release all clocks for %p\n",
__func__, dev);
return ret;
--
2.35.3
Re: [PATCH 1/2] arm64: Reduce add_map() complexity
On Fri, 08 Mar 2024 20:22:53 +, Fabio Estevam wrote: > > Hi Paul and Tom, > > On Tue, Feb 14, 2023 at 10:38 AM Ying-Chun Liu (PaulLiu) > wrote: > > > > From: Marc Zyngier > > > > In the add_map() function, for each level it populates, it iterates from > > the root of the PT tree, making it ineficient if a mapping needs to occur > > past level 1. > > > > Instead, replace it with a recursive (and much simpler) algorithm > > that keeps the complexity as low as possible. With this, mapping > > 512GB at level 2 goes from several seconds down to not measurable > > on an A55 machine. > > > > We keep the block mappings at level 1 for now though. > > > > Signed-off-by: Marc Zyngier > > Signed-off-by: Pierre-Clément Tosi > > [ Paul: pick from the Android tree. Fixup Pierre's commit. Rebase to the > > upstream ] > > Signed-off-by: Ying-Chun Liu (PaulLiu) > > Cc: Tom Rini > > Link: > > https://android.googlesource.com/platform/external/u-boot/+/96ad729cf4cab53bdff8222bb3eb256f38b5c3a6 > > Link: > > https://android.googlesource.com/platform/external/u-boot/+/6be9330601d81545c7c941e3609f35bf68a09059 > > I know this is an old thread, but this commit causes the following > boot regression on a colibri-imx8qxp board: > > U-Boot 2024.04-rc3-00070-gecc9298a893b (Mar 08 2024 - 17:15:31 -0300) > > CPU: NXP i.MX8QXP RevC A35 at 1200 MHz at 51C > > DRAM: 2 GiB > "Error" handler, esr 0xbf00 SError. Not good. > elr: 80020914 lr : 800209c0 (reloc) > elr: ffec4914 lr : ffec49c0 > x0 : 006070800401 x1 : 7000 > x2 : 1000 x3 : 0002 > x4 : 4000 x5 : 00600401 > x6 : 0c00 x7 : fff45140 > x8 : 0060 x9 : fff45100 > x10: 0a200023 x11: 0002 > x12: 0002 x13: 800a10e8 > x14: x15: ffec4cb8 > x16: 80056a88 x17: > x18: fd6c1d70 x19: 0f60 > x20: x21: 00600401 > x22: 70a0 x23: 0020 > x24: 4c28 x25: 001f > x26: 0003 x27: 70a0 > x28: 0002 x29: fd6bbfd0 > > Code: 1100047a a90573fb aa0103fb 2a0303fc (b5000113) > Resetting CPU ... > > resetting ... > > Reverting this commit on top of master fixes the boot regression. > > Any ideas? It would be good to narrow down which access is generating this. It is an asynchronous error, so the code above won't help. Alternatively, and if you are sure that this is due to this change, dumping the page tables and comparing them before and after would help. Thanks, M. -- Without deviation from the norm, progress is not possible.
Re: [PATCH] riscv: dts: jh7110: fix indentation
On Mon, Mar 04, 2024 at 09:51:47PM +0100, Leon M. Busch-George wrote: > From: "Leon M. Busch-George" > > Signed-off-by: Leon M. Busch-George > --- > arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Leo Yu-Chi Liang
