Re: [PATCH v1] doc: board: colibri-imx8x: Update and improve documentation

[Fabio Estevam]

Hi Hiago,

On Fri, Mar 15, 2024 at 11:39 AM Hiago De Franco  wrote:
>
> From: Hiago De Franco 
>
> Update and improve the building documentation of Colibri iMX8X.
> The following changes were made:
> - imx-atf repository changed to nxp-imx GitHub.
> - imx-atf branch updated to 'lf_v2.6'.
> - imx-seco updated to version 5.8.7.
> - nxp-imx mfgtools link updated to GitHub releases.
> - General writing improvements.

Thanks for improving the documentation.

One minor suggestion.

I have recently followed this document and noticed that the
instruction to copy the
mx8qm-apalis-scfw-tcm.bin to the U-Boot source is missing. Please add it.

Also, since you are updating several components, shouldn't
mx8qm-apalis-scfw-tcm.bin be updated?

Currently, the version is from toradex-sumo-4.14.78-1.0.0_ga-bringup
which looks quite ancient.

[PATCH 1/1] xilinx: zynq: add FDT_FIXUP_PARTITIONS support

[James Hilliard]

There are situations where we may want to let U-Boot modify the FDT
nand partitions for the kernel, such as when supporting multiple
sizes of NAND chips.

Lets also refactor xilinx common board support to have a
ft_common_board_setup which gets called by the ft_board_setup for each
specific board so that we can add non-common functionality to each
ft_board_setup like FDT_FIXUP_PARTITIONS as needed.

This pattern is modeled after the one used by tdx-common.c.

Signed-off-by: James Hilliard 
---
 board/xilinx/common/board.c |  2 +-
 board/xilinx/common/board.h |  2 ++
 board/xilinx/mbv/board.c|  9 +
 board/xilinx/versal-net/board.c |  7 +++
 board/xilinx/versal/board.c |  7 +++
 board/xilinx/zynq/board.c   | 17 +
 board/xilinx/zynqmp/zynqmp.c|  7 +++
 board/xilinx/zynqmp_r5/board.c  |  8 
 8 files changed, 58 insertions(+), 1 deletion(-)

diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 9641ed307b..629ba2b902 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -686,7 +686,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
 
 #ifdef CONFIG_OF_BOARD_SETUP
 #define MAX_RAND_SIZE 8
-int ft_board_setup(void *blob, struct bd_info *bd)
+int ft_common_board_setup(void *blob, struct bd_info *bd)
 {
size_t n = MAX_RAND_SIZE;
struct udevice *dev;
diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h
index 64d657673e..73f576952a 100644
--- a/board/xilinx/common/board.h
+++ b/board/xilinx/common/board.h
@@ -18,4 +18,6 @@ bool board_detection(void);
 char *soc_name_decode(void);
 
 bool soc_detection(void);
+
+int ft_common_board_setup(void *blob, struct bd_info *bd);
 #endif /* BOARD_XILINX_COMMON_BOARD_H */
diff --git a/board/xilinx/mbv/board.c b/board/xilinx/mbv/board.c
index ccf4395d6a..d8af1eaa90 100644
--- a/board/xilinx/mbv/board.c
+++ b/board/xilinx/mbv/board.c
@@ -5,7 +5,16 @@
  * Michal Simek 
  */
 
+#include "../common/board.h"
+
 int board_init(void)
 {
return 0;
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   return ft_common_board_setup(blob, bd);
+}
+#endif
diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c
index 990ca1650a..bd674e6739 100644
--- a/board/xilinx/versal-net/board.c
+++ b/board/xilinx/versal-net/board.c
@@ -371,3 +371,10 @@ int dram_init(void)
 void reset_cpu(void)
 {
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   return ft_common_board_setup(blob, bd);
+}
+#endif
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index 8c2e614ad8..944ef2d822 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -320,3 +320,10 @@ enum env_location env_get_location(enum env_operation op, 
int prio)
return ENVL_NOWHERE;
}
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   return ft_common_board_setup(blob, bd);
+}
+#endif
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 6c36591001..1ca1984c49 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -13,10 +13,12 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -201,3 +203,18 @@ void set_dfu_alt_info(char *interface, char *devstr)
puts("DFU alt info setting: done\n");
 }
 #endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+#ifdef CONFIG_FDT_FIXUP_PARTITIONS
+   static const struct node_info nodes[] = {
+   { "arm,pl353-nand-r2p1", MTD_DEV_TYPE_NAND, },
+   };
+
+   fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+#endif
+
+   return ft_common_board_setup(blob, bd);
+}
+#endif
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index ba49eb7be2..cd06396df0 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -700,3 +700,10 @@ unsigned int spl_spi_get_uboot_offs(struct spi_flash 
*flash)
return offset;
 }
 #endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   return ft_common_board_setup(blob, bd);
+}
+#endif
diff --git a/board/xilinx/zynqmp_r5/board.c b/board/xilinx/zynqmp_r5/board.c
index 5c5a2e9386..a512577260 100644
--- a/board/xilinx/zynqmp_r5/board.c
+++ b/board/xilinx/zynqmp_r5/board.c
@@ -6,6 +6,7 @@
 #include 
 #include 
 #include 
+#include "../common/board.h"
 
 int board_init(void)
 {
@@ -24,3 +25,10 @@ int dram_init(void)
 
return 0;
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+   return ft_common_board_setup(blob, bd);
+}
+#endif
-- 
2.34.1

Re: [PATCH] mmc: arm_pl180: Limit data transfer to U16_MAX

[Lean Sheng Tan]

+ @Simon

Best Regards,
*Lean Sheng Tan*



9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany
Email: sheng@9elements.com
Phone: *+49 234 68 94 188 <+492346894188>*
Mobile: *+49 176 76 113842 <+4917676113842>*

Registered office: Bochum
Commercial register: Amtsgericht Bochum, HRB 17519
Management: Sebastian German, Eray Bazaar

Data protection information according to Art. 13 GDPR



On Mon 4. Mar 2024 at 16:39, Lean Sheng Tan  wrote:

> Quick reminder:
> Can anyone help to review this?
> Thanks!
>
> Best Regards,
> *Lean Sheng Tan*
>
>
>
> 9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany
> Email: sheng@9elements.com
> Phone: *+49 234 68 94 188 <+492346894188>*
> Mobile: *+49 176 76 113842 <+4917676113842>*
>
> Registered office: Bochum
> Commercial register: Amtsgericht Bochum, HRB 17519
> Management: Sebastian German, Eray Bazaar
>
> Data protection information according to Art. 13 GDPR
> 
>
>
> On Tue, 27 Feb 2024 at 22:02,  wrote:
>
>> From: max 
>>
>> Currently fetching files bigger that cause a data transfer greater than
>> U16_MAX fails.
>>
>> The reason is that the specification defines the datalength register
>> as a 16 bit wide register, but in u-boot it is used as if it is an
>> 32 bit register. Therefore values greater than U16_MAX cause an
>> infinite loop inside u-boot. U-boot expects to get more data from
>> interface/hardware then it will ever get and therefore inifintely waits
>> for more data that will never come.
>>
>> Signed-off-by: max 
>> Cc: Peng Fan 
>> Cc: Jaehoon Chung 
>> ---
>>  drivers/mmc/arm_pl180_mmci.c | 11 +++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c
>> index 5cf5502ed5..af2f9a5a84 100644
>> --- a/drivers/mmc/arm_pl180_mmci.c
>> +++ b/drivers/mmc/arm_pl180_mmci.c
>> @@ -231,6 +231,7 @@ static int do_data_transfer(struct mmc *dev,
>> u32 blksz = 0;
>> u32 data_ctrl = 0;
>> u32 data_len = (u32) (data->blocks * data->blocksize);
>> +   assert(data_len < U16_MAX); // should be ensured by
>> arm_pl180_get_b_max
>>
>> if (!host->version2) {
>> blksz = (ffs(data->blocksize) - 1);
>> @@ -358,6 +359,14 @@ static int  host_set_ios(struct mmc *dev)
>> return 0;
>>  }
>>
>> +static int arm_pl180_get_b_max(struct udevice *dev, void *dst, lbaint_t
>> blkcnt)
>> +{
>> +   struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
>> +   struct mmc *mmc = upriv->mmc;
>> +
>> +   return U16_MAX / mmc->read_bl_len;
>> +}
>> +
>>  #ifndef CONFIG_DM_MMC
>>  /* MMC uses open drain drivers in the enumeration phase */
>>  static int mmc_host_reset(struct mmc *dev)
>> @@ -373,6 +382,7 @@ static const struct mmc_ops arm_pl180_mmci_ops = {
>> .send_cmd = host_request,
>> .set_ios = host_set_ios,
>> .init = mmc_host_reset,
>> +   .get_b_max = arm_pl180_get_b_max,
>>  };
>>
>>  /*
>> @@ -531,6 +541,7 @@ static const struct dm_mmc_ops arm_pl180_dm_mmc_ops =
>> {
>> .send_cmd = dm_host_request,
>> .set_ios = dm_host_set_ios,
>> .get_cd = dm_mmc_getcd,
>> +   .get_b_max = arm_pl180_get_b_max,
>>  };
>>
>>  static int arm_pl180_mmc_of_to_plat(struct udevice *dev)
>> --
>> 2.43.0
>>
>>

Re: [PATCH] cmd: sf: Fix sf probe crash

[Jonas Karlman]

Hi,

On 2024-01-04 12:46, Weizhao Ouyang wrote:
> Handle the return value of spi_flash_probe_bus_cs() to avoid sf probe
> crashes.
> 
> Signed-off-by: Weizhao Ouyang 

This fixes a null pointer dereference when running "sf probe" and there
are no spi devices enabled in the device tree for my boards, so:

Fixes: 3feea0ba196a ("spi: spi_flash_probe_bus_cs() rely on DT for spi speed 
and mode")

Reviewed-by: Jonas Karlman 

Regards,
Jonas

> ---
>  cmd/sf.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/cmd/sf.c b/cmd/sf.c
> index 730996c02b..e3866899f6 100644
> --- a/cmd/sf.c
> +++ b/cmd/sf.c
> @@ -135,8 +135,9 @@ static int do_spi_flash_probe(int argc, char *const 
> argv[])
>   }
>   flash = NULL;
>   if (use_dt) {
> - spi_flash_probe_bus_cs(bus, cs, );
> - flash = dev_get_uclass_priv(new);
> + ret = spi_flash_probe_bus_cs(bus, cs, );
> + if (!ret)
> + flash = dev_get_uclass_priv(new);
>   } else {
>   flash = spi_flash_probe(bus, cs, speed, mode);
>   }

[PATCH] rockchip: spl: Cache boot source id for later use

[Jonas Karlman]

Rockchip BROM write a boot source id at CFG_IRAM_BASE + 0x10, the id
indicate from what storage media TPL/SPL was loaded from.

SPL use this value to determine what device "same-as-spl" represent when
determining from where FIT should be loaded. This works as long as the
boot_devices array contain a matching id <-> node path entry.

However, SPL typically load a small part of TF-A into SRAM and on RK3399
this overwrites the CFG_IRAM_BASE + 0x10 addr used for boot source id.

Here boot source id is 3 before FIT images is loaded, and 0 after:

  U-Boot SPL 2024.04-rc4 (Mar 15 2024 - 17:26:19 +)
  board_spl_was_booted_from: brom_bootdevice_id 3 maps to 
'/spi@ff1d/flash@0'
  Trying to boot from SPI
  ## Checking hash(es) for config config-1 ... OK
  ## Checking hash(es) for Image atf-1 ... sha256+ OK
  ## Checking hash(es) for Image u-boot ... sha256+ OK
  ## Checking hash(es) for Image fdt-1 ... sha256+ OK
  ## Checking hash(es) for Image atf-2 ... sha256+ OK
  ## Checking hash(es) for Image atf-3 ... sha256+ OK
  board_spl_was_booted_from: failed to resolve brom_bootdevice_id 0
  spl_decode_boot_device: could not find udevice for /mmc@fe33
  spl_decode_boot_device: could not find udevice for /mmc@fe32
  spl_perform_fixups: could not map boot_device to ofpath: -19

Use a static bootdevice_brom_id to cache the boot source id after an
initial read from SRAM to fix this, this allow spl_perform_fixups() to
resolve correct boot source path for "same-as-spl" after SPL have loaded
TF-A related FIT images into memory.

With this the spl-boot-device prop can correctly be resolved to the
SPI flash node in the control FDT:

  => fdt addr ${fdtcontroladdr}
  Working FDT set to f1ee6710
  => fdt list /chosen
  chosen {
  u-boot,spl-boot-device = "/spi@ff1d/flash@0";
  stdout-path = "serial2:150n8";
  u-boot,spl-boot-order = "same-as-spl", "/mmc@fe33", "/mmc@fe32";
  };

Signed-off-by: Jonas Karlman 
---
 arch/arm/mach-rockchip/spl.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c
index 1586a093fc37..27e996b504e7 100644
--- a/arch/arm/mach-rockchip/spl.c
+++ b/arch/arm/mach-rockchip/spl.c
@@ -32,9 +32,17 @@ __weak const char * const boot_devices[BROM_LAST_BOOTSOURCE 
+ 1] = {
 
 const char *board_spl_was_booted_from(void)
 {
-   u32  bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+   static u32 bootdevice_brom_id;
const char *bootdevice_ofpath = NULL;
 
+   if (!bootdevice_brom_id)
+   bootdevice_brom_id = readl(BROM_BOOTSOURCE_ID_ADDR);
+   if (!bootdevice_brom_id) {
+   debug("%s: unknown brom_bootdevice_id %x\n",
+ __func__, bootdevice_brom_id);
+   return NULL;
+   }
+
if (bootdevice_brom_id < ARRAY_SIZE(boot_devices))
bootdevice_ofpath = boot_devices[bootdevice_brom_id];
 
-- 
2.43.2

Re: [PATCH v2 14/14] qcom_defconfig: enable USB

[Neil Armstrong]

On 15/03/2024 16:10, Caleb Connolly wrote:

Enable support for the DWC3 USB controller and required dependencies for
Qualcomm boards, specifically the DB845c:
* IOMMU / SMMU
* USB high-speed PHYs
* Mass storage and ACM gadgets


I don't see configs for ACM ?

Neil



Signed-off-by: Caleb Connolly 
---
  configs/qcom_defconfig | 12 
  1 file changed, 12 insertions(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index eebd0d74bd51..3979c19052db 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -12,8 +12,9 @@ CONFIG_BOOTSTD_FULL=y
  CONFIG_BOOTDELAY=1
  CONFIG_USE_PREBOOT=y
  CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
  CONFIG_SYS_CBSIZE=512
+# CONFIG_SYS_DEVICE_NULLDEV is not set
  CONFIG_LOG_MAX_LEVEL=9
  CONFIG_LOG_DEFAULT_LEVEL=4
  # CONFIG_DISPLAY_CPUINFO is not set
  CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -22,14 +23,17 @@ CONFIG_CMD_CLK=y
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_MMC=y
  CONFIG_CMD_UFS=y
  CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
  CONFIG_CMD_CAT=y
  CONFIG_CMD_BMP=y
  CONFIG_CMD_LOG=y
  CONFIG_OF_LIVE=y
  # CONFIG_NET is not set
  # CONFIG_OFNODE_MULTI_TREE is not set
+CONFIG_DM_WARN=y
  CONFIG_BUTTON_QCOM_PMIC=y
  CONFIG_CLK=y
  CONFIG_CLK_QCOM_QCS404=y
  CONFIG_CLK_QCOM_SDM845=y
@@ -37,17 +41,24 @@ CONFIG_MSM_GPIO=y
  CONFIG_QCOM_PMIC_GPIO=y
  CONFIG_DM_KEYBOARD=y
  CONFIG_BUTTON_KEYBOARD=y
  CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_IOMMU=y
+CONFIG_QCOM_HYP_SMMU=y
+CONFIG_MISC=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_ADMA=y
  CONFIG_MMC_SDHCI_MSM=y
  CONFIG_PHY=y
+CONFIG_PHY_QCOM_QUSB2=y
+CONFIG_PHY_QCOM_USB_HS_7NM=y
  CONFIG_PINCTRL=y
  CONFIG_PINCTRL_QCOM_QCS404=y
  CONFIG_PINCTRL_QCOM_SDM845=y
  CONFIG_DM_PMIC=y
  CONFIG_PMIC_QCOM=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
  CONFIG_SCSI=y
  CONFIG_MSM_SERIAL=y
  CONFIG_MSM_GENI_SERIAL=y
  CONFIG_SPMI_MSM=y
@@ -56,8 +67,9 @@ CONFIG_SYSINFO_SMBIOS=y
  CONFIG_USB=y
  CONFIG_USB_XHCI_HCD=y
  CONFIG_USB_XHCI_DWC3=y
  CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
  CONFIG_UFS=y
  CONFIG_VIDEO=y
  # CONFIG_VIDEO_FONT_8X16 is not set
  CONFIG_VIDEO_FONT_16X32=y

Re: [PATCH v2 13/14] qcom_defconfig: enable livetree

[Neil Armstrong]

On 15/03/2024 16:10, Caleb Connolly wrote:

Qualcomm FDTs are on the larger size, and with the addition of DT
modifications during board_init() it makes sense to enable OF_LIVE
globally. The cost of building the tree should be offset by the
increased efficiency at which we can walk it.

Some rough measurements with CONFIG_BOOTSTAGE suggests that this might
add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset
timer difference is in the range of 0.5ms so this could just be noise.

Suffice to say, no significant slow down.

Signed-off-by: Caleb Connolly 
---
  configs/qcom_defconfig | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index cbc612b44bd9..eebd0d74bd51 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -25,8 +25,11 @@ CONFIG_CMD_UFS=y
  CONFIG_CMD_USB=y
  CONFIG_CMD_CAT=y
  CONFIG_CMD_BMP=y
  CONFIG_CMD_LOG=y
+CONFIG_OF_LIVE=y
+# CONFIG_NET is not set
+# CONFIG_OFNODE_MULTI_TREE is not set
  CONFIG_BUTTON_QCOM_PMIC=y
  CONFIG_CLK=y
  CONFIG_CLK_QCOM_QCS404=y
  CONFIG_CLK_QCOM_SDM845=y



Reviewed-by: Neil Armstrong 

Re: [PATCH v2 09/14] serial: msm-geni: support livetree

[Neil Armstrong]

On 15/03/2024 16:10, Caleb Connolly wrote:

When using OF_LIVE, the debug UART driver won't be probed if it's a
subnode of the geni-se-qup controller. Add a NOP driver for the
controller to correctly discover its child nodes.

Signed-off-by: Caleb Connolly 
---
  drivers/serial/serial_msm_geni.c | 13 +
  1 file changed, 13 insertions(+)

diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 4aa0bc8c72bc..5260474fb9a4 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -605,8 +605,21 @@ U_BOOT_DRIVER(serial_msm_geni) = {
.ops = _serial_ops,
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
  };
  
+static const struct udevice_id geniqup_ids[] = {

+   { .compatible = "qcom,geni-se-qup" },
+   { }
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+   .name = "geni-se-qup",
+   .id = UCLASS_NOP,
+   .of_match = geniqup_ids,
+   .bind = dm_scan_fdt_dev,
+   .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+
  #ifdef CONFIG_DEBUG_UART_MSM_GENI
  
  static struct msm_serial_data init_serial_data = {

.base = CONFIG_VAL(DEBUG_UART_BASE)



Reviewed-by: Neil Armstrong 

Re: Pull request: u-boot-rockchip/for-next

[Tom Rini]

On Fri, Mar 15, 2024 at 08:57:34AM +0800, Kever Yang wrote:

> Hi Tom,
> 
> This is for next;
> Please pull the updates for rockchip platform:
> - Add board: rk3588 Generic, Cool Pi CM5, Theobroma-Systems RK3588 Jaguar SBC,
>Toybrick TB-RK3588X;
>rk3588s Cool Pi 4B;
>rk3566 Pine64 PineTab2;
> - Add saradc v2 support;
> - Add PMIC RK806 support;
> - rk3588 disable force_jtag by default;
> - Migrate to use IO-domain driver for all boards;
> - Use common bss and stack addresses for rk33xx and rk35xx boards;
> - Other updates for driver, config and dts;
> 
> CI:
> https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/19951
> 
> Thanks,
> - Kever
> 
> The following changes since commit 20a0ce574d6642e0dfe651467159039fac48cc4f:
> 
>   Merge tag 'v2024.04-rc4' into next (2024-03-11 15:27:20 -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-rockchip.git 
> tags/u-boot-rockchip-20240315
> 
> for you to fetch changes up to 12bc1a5462a22f6dc5b91ecbf092cbaf94e66820:
> 
>   rockchip: boot_mode: fix rockchip_dnl_key_pressed requiring ADC support 
> (2024-03-14 18:20:04 +0800)
> 

Applied to u-boot/next, thanks!

-- 
Tom


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Re: [PATCH v4 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end

[Richard Henderson]

On 3/14/24 20:43, Ilias Apalodimas wrote:

commit 3ebd1cbc49f0 ("arm: make __bss_start and __bss_end__ compiler-generated")
and
commit f84a7b8f54db ("ARM: Fix __bss_start and __bss_end in linker scripts")
were moving the bss_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
relocations for position independent code and linker bugs back then
prevented us from doing so [0].

However, the linker documentation pages states that symbols that are
defined within a section definition will create a relocatable type with
the value being a fixed offset from the base of a section [1].
So let's start cleaning this up starting with the bss_start and bss_end
variables. Convert them into symbols within the .bss section definition.

[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for 
shared object")
[1]https://sourceware.org/binutils/docs/ld/Expression-Section.html

Tested-by: Caleb Connolly  # Qualcomm sdm845
Tested-by: Sam Edwards  # Binary output identical
Signed-off-by: Ilias Apalodimas
---
  arch/arm/cpu/armv8/u-boot-spl.lds| 18 +++---
  arch/arm/cpu/armv8/u-boot.lds| 16 
  arch/arm/cpu/u-boot.lds  | 22 +++---
  arch/arm/lib/sections.c  |  2 --
  arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 15 ---
  arch/arm/mach-zynq/u-boot.lds| 22 +++---
  6 files changed, 29 insertions(+), 66 deletions(-)


Reviewed-by: Richard Henderson 

r~

Re: [PATCH v2 06/14] clk/qcom: sdm845: add gdscs

[Neil Armstrong]

On 15/03/2024 16:10, Caleb Connolly wrote:

Define the GDSC power domains for SDM845.

Signed-off-by: Caleb Connolly 
---
  drivers/clk/qcom/clock-sdm845.c | 18 ++
  1 file changed, 18 insertions(+)

diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index ccb0cf245d33..b7154360894a 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = {
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
  };
  
+static const struct qcom_power_map sdm845_gdscs[] = {

+   [PCIE_0_GDSC] = { 0x6b004 },
+   [PCIE_1_GDSC] = { 0x8d004 },
+   [UFS_CARD_GDSC] = { 0x75004 },
+   [UFS_PHY_GDSC] = { 0x77004 },
+   [USB30_PRIM_GDSC] = { 0xf004 },
+   [USB30_SEC_GDSC] = { 0x10004 },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 },
+   [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 },
+   [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 },
+   [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 },
+};
+
  static struct msm_clk_data sdm845_clk_data = {
.resets = sdm845_gcc_resets,
.num_resets = ARRAY_SIZE(sdm845_gcc_resets),
.clks = sdm845_clks,
.num_clks = ARRAY_SIZE(sdm845_clks),
+   .power_domains = sdm845_gdscs,
+   .num_power_domains = ARRAY_SIZE(sdm845_gdscs),
  
  	.enable = sdm845_clk_enable,

.set_rate = sdm845_clk_set_rate,
  };



Reviewed-by: Neil Armstrong 

Re: [PATCH v2 01/14] mailmap: update Bhupesh's email address

[Neil Armstrong]

On 15/03/2024 16:10, Caleb Connolly wrote:

Update Bhupesh's email to his new one.

Signed-off-by: Caleb Connolly 
---

Cc: Bhupesh Sharma 
---
  .mailmap | 1 +
  1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index d1f08f3eca8a..f6e0847b2168 100644
--- a/.mailmap
+++ b/.mailmap
@@ -29,8 +29,9 @@ Ashok Reddy Soma  

  Atish Patra  
  Bharat Kumar Gogada  

  Bharat Kumar Gogada  
  Bhargava Sreekantappa Gayathri  

+Bhupesh Sharma  
  Bin Meng  
  Boris Brezillon  
  Boris Brezillon  
  Christian Kohn  



Reviewed-by: Neil Armstrong 

Re: [PATCH v2 0/5] Qualcomm DWC3 USB support

[Neil Armstrong]

On 15/03/2024 16:05, Caleb Connolly wrote:

This series enables support for Qualcomm platforms in the DWC3 driver,
adds support for arbitrary sector sizes to the USB mass storage gadget,
and fixes an issue with the CDC ACM driver where it wouldn't initialise
the USB device.

Additionally, it fixes a syntax bug in the Qualcomm SMMU driver, and
makes USB_DWC3_GADGET select DM_USB_GADGET to fix compilation with
gadget mode.

This is part of a larger series enabling DWC3 USB support on Qualcomm
platforms, a feature branch with all patches can be found at [1].

[1]: 
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/tree/b4/qcom-livetree

---
Changes in v2:
- Drop custom set/clrbits implementation in qcom dwc3 glue.
- Additional minor cleanup based on Marek's comments.
- Link to v1: 
https://lore.kernel.org/r/20240131-b4-qcom-usb-v1-0-6438b2a22...@linaro.org

---
Caleb Connolly (5):
   usb: dwc3-generic: implement Qualcomm wrapper
   usb: dwc3: select DM_USB_GADGET
   usb: gadget: CDC ACM: call usb_gadget_initialize
   usb: gadget: UMS: support multiple sector sizes
   iommu: qcom-smmu: fix debugging

  cmd/usb_mass_storage.c  |   4 --
  drivers/iommu/qcom-hyp-smmu.c   |   2 +-
  drivers/usb/dwc3/Kconfig|   1 +
  drivers/usb/dwc3/dwc3-generic.c |  81 -
  drivers/usb/gadget/f_acm.c  |   9 
  drivers/usb/gadget/f_mass_storage.c | 101 
  drivers/usb/gadget/storage_common.c |  12 +++--
  include/usb_mass_storage.h  |   1 -
  8 files changed, 156 insertions(+), 55 deletions(-)
---
base-commit: e03a71b2cefd86ba58df166d4ea820a215ebb655

// Caleb (they/them)



LGTM

Reviewed-by: Neil Armstrong 

Re: [PATCH v1] doc: board: colibri-imx8x: Update and improve documentation

[Francesco Dolcini]

On Fri, Mar 15, 2024 at 11:39:30AM -0300, Hiago De Franco wrote:
> From: Hiago De Franco 
> 
> Update and improve the building documentation of Colibri iMX8X.
> The following changes were made:
> - imx-atf repository changed to nxp-imx GitHub.
> - imx-atf branch updated to 'lf_v2.6'.
> - imx-seco updated to version 5.8.7.
> - nxp-imx mfgtools link updated to GitHub releases.
> - General writing improvements.
> 
> Signed-off-by: Hiago De Franco 

Reviewed-by: Francesco Dolcini 

Francesco

Re: [PATCH v1] arm: imx: imx8m: soc: Fix NPU/VPU fdt disable fixup

[Francesco Dolcini]

On Fri, Mar 15, 2024 at 02:44:25PM +, Vitor Soares wrote:
> From: Vitor Soares 
> 
> On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
> IP block nodes. It leads variants without such HW block having it
> enabled by default.
> 
> This patch adds the upstream Linux node's paths to the disable list while
> keep the compatibility with downstream Linux.
> 
> Signed-off-by: Vitor Soares 

Reviewed-by: Francesco Dolcini 

Francesco

Re: [PATCH 1/2] arm64: Reduce add_map() complexity

[Pierre-Clément Tosi]

Hi Fabio,

On Fri, Mar 15, 2024 at 08:56:17AM -0300, Fabio Estevam wrote:
> Hi Marc,
> 
> On Sat, Mar 9, 2024 at 11:36 AM Fabio Estevam  wrote:
> 
> > Does the log below help?
> >
> > https://pastebin.com/raw/1i1VBA0a
> >
> > If not, please send me a debug patch and I will be glad to run it here.
> 
> I'm sorry to bother you, but have you had a chance to look at the log
> I shared with you?

I had a quick look through your logs and notice that U-Boot master attempts to
map addresses in the high VA range e.g.

  Checking if pte fits for virt=e400 [...]

while the logs that boot successfully only use the low VA range e.g.

  Checking if pte fits for virt=80193000 [...]

Unless that has recently changed (since I last worked with U-Boot), U-Boot on
AArch64 only supports identity mappings and therefore was only taught how to
program TTBR0_ELx (i.e. is only able to map low virtual addresses). This means
that the code - with or without 41e2787f5ec4 - would be unable to map addresses
such as 0xe400.

Now, given that 41e2787f5ec4 only affects implementation details of add_map(),
I am surprised that reverting that commit changes the arguments received by the
function such as virt. As a reminder, add_map() is exclusively used on mem_map:

  for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
  add_map(_map[i]);

> 
> That's the only issue preventing colibri-imx8x from booting mainline U-Boot.

If I read the U-Boot configs right i.e.

 - configs/colibri-imx8x_defconfig: CONFIG_ARCH_IMX8=y
 - arch/arm/mach-imx/imx8/Makefile: obj-y += cpu.o
 - arch/arm/mach-imx/imx8/cpu.c: struct mm_region *mem_map = imx8_mem_map;

There is a possibility that your mem_map is getting modified by MACH-specific
code. In particular, enable_caches() seems to dynamically get the MMU mappings
from some RPC mechanism (see get_owned_memreg() and sc_rm_get_memreg_info()).

Could it be that whatever services those requests might be returning unexpected
values? Instrumenting arch/arm/mach-imx/imx8/cpu.c and dumping mem_map (and
the RPC messages) with/without the patch would help clear this up.

HTH,

> 
> We would like to get this fixed for U-Boot 2024.04.
> 
> Thanks for your help

-- 
Pierre

[PATCH v2 14/14] qcom_defconfig: enable USB

[Caleb Connolly]

Enable support for the DWC3 USB controller and required dependencies for
Qualcomm boards, specifically the DB845c:
* IOMMU / SMMU
* USB high-speed PHYs
* Mass storage and ACM gadgets

Signed-off-by: Caleb Connolly 
---
 configs/qcom_defconfig | 12 
 1 file changed, 12 insertions(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index eebd0d74bd51..3979c19052db 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -12,8 +12,9 @@ CONFIG_BOOTSTD_FULL=y
 CONFIG_BOOTDELAY=1
 CONFIG_USE_PREBOOT=y
 CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
 CONFIG_SYS_CBSIZE=512
+# CONFIG_SYS_DEVICE_NULLDEV is not set
 CONFIG_LOG_MAX_LEVEL=9
 CONFIG_LOG_DEFAULT_LEVEL=4
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -22,14 +23,17 @@ CONFIG_CMD_CLK=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_UMS_ABORT_KEYED=y
 CONFIG_CMD_CAT=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_LOG=y
 CONFIG_OF_LIVE=y
 # CONFIG_NET is not set
 # CONFIG_OFNODE_MULTI_TREE is not set
+CONFIG_DM_WARN=y
 CONFIG_BUTTON_QCOM_PMIC=y
 CONFIG_CLK=y
 CONFIG_CLK_QCOM_QCS404=y
 CONFIG_CLK_QCOM_SDM845=y
@@ -37,17 +41,24 @@ CONFIG_MSM_GPIO=y
 CONFIG_QCOM_PMIC_GPIO=y
 CONFIG_DM_KEYBOARD=y
 CONFIG_BUTTON_KEYBOARD=y
 CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_IOMMU=y
+CONFIG_QCOM_HYP_SMMU=y
+CONFIG_MISC=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_MSM=y
 CONFIG_PHY=y
+CONFIG_PHY_QCOM_QUSB2=y
+CONFIG_PHY_QCOM_USB_HS_7NM=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_QCOM_QCS404=y
 CONFIG_PINCTRL_QCOM_SDM845=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_QCOM=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SCSI=y
 CONFIG_MSM_SERIAL=y
 CONFIG_MSM_GENI_SERIAL=y
 CONFIG_SPMI_MSM=y
@@ -56,8 +67,9 @@ CONFIG_SYSINFO_SMBIOS=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
 CONFIG_UFS=y
 CONFIG_VIDEO=y
 # CONFIG_VIDEO_FONT_8X16 is not set
 CONFIG_VIDEO_FONT_16X32=y

-- 
2.44.0

[PATCH v2 13/14] qcom_defconfig: enable livetree

[Caleb Connolly]

Qualcomm FDTs are on the larger size, and with the addition of DT
modifications during board_init() it makes sense to enable OF_LIVE
globally. The cost of building the tree should be offset by the
increased efficiency at which we can walk it.

Some rough measurements with CONFIG_BOOTSTAGE suggests that this might
add 0.1-0.2ms to the boot-to-console time. However the reset-to-reset
timer difference is in the range of 0.5ms so this could just be noise.

Suffice to say, no significant slow down.

Signed-off-by: Caleb Connolly 
---
 configs/qcom_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig
index cbc612b44bd9..eebd0d74bd51 100644
--- a/configs/qcom_defconfig
+++ b/configs/qcom_defconfig
@@ -25,8 +25,11 @@ CONFIG_CMD_UFS=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_CAT=y
 CONFIG_CMD_BMP=y
 CONFIG_CMD_LOG=y
+CONFIG_OF_LIVE=y
+# CONFIG_NET is not set
+# CONFIG_OFNODE_MULTI_TREE is not set
 CONFIG_BUTTON_QCOM_PMIC=y
 CONFIG_CLK=y
 CONFIG_CLK_QCOM_QCS404=y
 CONFIG_CLK_QCOM_SDM845=y

-- 
2.44.0

[PATCH v2 11/14] mach-snapdragon: fixup power-domains

[Caleb Connolly]

We don't support the RPM(h)PD power domains in U-Boot, and we don't need
to - the necessary resources are on, and we aren't going to enter any
low power modes.

We could try using a no-op device, but this requires adding a compatible
for every platform, and just pollutes the driver model. So instead let's
just remove every "power-domains" property that references the RPM(h)pd
power controller. This takes <1ms as we're using OF_LIVE.

Of note, this only applies to drivers which are loading post-relocation.
Drivers loaded pre-reloc that reference the rpm(h)pd still need
DM_FLAG_DEFAULT_PD_CTRL_OFF in their flags.

Signed-off-by: Caleb Connolly 
---
 arch/arm/mach-snapdragon/of_fixup.c | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/mach-snapdragon/of_fixup.c 
b/arch/arm/mach-snapdragon/of_fixup.c
index 6810c8617cc0..49f1fc1948f3 100644
--- a/arch/arm/mach-snapdragon/of_fixup.c
+++ b/arch/arm/mach-snapdragon/of_fixup.c
@@ -21,8 +21,9 @@
 #include 
 #include 
 #include 
 #include 
+#include 
 
 /* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
  * USB controllers. Rather than requiring source level DT changes, we fix up
  * DT here. This improves compatibility with upstream DT and simplifies the
@@ -108,8 +109,39 @@ static void fixup_usb_nodes(void)
log_warning("Failed to fixup node %s: %d\n", 
glue_np->name, ret);
}
 }
 
+/* Remove all references to the rpmhpd device */
+static void fixup_power_domains(void)
+{
+   struct device_node *pd = NULL, *np = NULL;
+   struct property *prop;
+   const __be32 *val;
+
+   /* All Qualcomm platforms name the rpm(h)pd "power-controller" */
+   for_each_of_allnodes(pd) {
+   if (pd->name && !strcmp("power-controller", pd->name))
+   break;
+   }
+
+   /* Sanity check that this is indeed a power domain controller */
+   if (!of_find_property(pd, "#power-domain-cells", NULL)) {
+   log_err("Found power-controller but it doesn't have 
#power-domain-cells\n");
+   return;
+   }
+
+   /* Remove all references to the power domain controller */
+   for_each_of_allnodes(np) {
+   if (!(prop = of_find_property(np, "power-domains", NULL)))
+   continue;
+
+   val = prop->value;
+   if (val[0] == cpu_to_fdt32(pd->phandle))
+   of_remove_property(np, prop);
+   }
+}
+
 void qcom_of_fixup_nodes(void)
 {
fixup_usb_nodes();
+   fixup_power_domains();
 }

-- 
2.44.0

[PATCH v2 12/14] dts: sdm845-db845c: add u-boot fixups

[Caleb Connolly]

The USB VBUS supply for the type-A port is enabled via a GPIO regulator.
This is incorrectly modelled in Linux where only the PCIe dependency is
expressed. Add a U-Boot specific dtsi snippet so that this supply will
get enabled when initialising USB.

Signed-off-by: Caleb Connolly 
---
 arch/arm/dts/sdm845-db845c-u-boot.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/sdm845-db845c-u-boot.dtsi 
b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
new file mode 100644
index ..3c83e21251c4
--- /dev/null
+++ b/arch/arm/dts/sdm845-db845c-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* This GPIO must be turned on to enable the 5v VBUS
+ * supply on the USB port.
+ */
+_2_dwc3 {
+   vbus-supply = <_3p3v_dual>;
+};

-- 
2.44.0

[PATCH v2 10/14] mach-snapdragon: fixup USB nodes

[Caleb Connolly]

We don't support USB super-speed in U-Boot yet, we lack the SS PHY
drivers, however from my testing even with a PHY driver there seem to be
other issues when talking to super-speed peripherals.

In pursuit of maintaining upstream DT compatibility, and simplifying
porting for new devices, let's implement the DT fixups necessary to
configure USB in high-speed only mode at runtime. The pattern is
identical for all Qualcomm boards that use the Synaptics DWC3
controller:

* Add an additional property on the Qualcomm wrapper node
* Remove the super-speed phy phandle and phy-name entries.

Signed-off-by: Caleb Connolly 
---
 arch/arm/mach-snapdragon/Makefile|   1 +
 arch/arm/mach-snapdragon/board.c |   3 +
 arch/arm/mach-snapdragon/of_fixup.c  | 115 +++
 arch/arm/mach-snapdragon/qcom-priv.h |  19 ++
 4 files changed, 138 insertions(+)

diff --git a/arch/arm/mach-snapdragon/Makefile 
b/arch/arm/mach-snapdragon/Makefile
index 857171e593da..7a4495c8108f 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -2,4 +2,5 @@
 #
 # (C) Copyright 2015 Mateusz Kulikowski 
 
 obj-y += board.o
+obj-$(CONFIG_OF_LIVE) += of_fixup.o
diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c
index 6f762fc948bf..65e4c61e866a 100644
--- a/arch/arm/mach-snapdragon/board.c
+++ b/arch/arm/mach-snapdragon/board.c
@@ -27,8 +27,10 @@
 #include 
 #include 
 #include 
 
+#include "qcom-priv.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };
 
@@ -159,8 +161,9 @@ void __weak qcom_board_init(void)
 
 int board_init(void)
 {
show_psci_version();
+   qcom_of_fixup_nodes();
qcom_board_init();
return 0;
 }
 
diff --git a/arch/arm/mach-snapdragon/of_fixup.c 
b/arch/arm/mach-snapdragon/of_fixup.c
new file mode 100644
index ..6810c8617cc0
--- /dev/null
+++ b/arch/arm/mach-snapdragon/of_fixup.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * OF_LIVE devicetree fixup.
+ *
+ * This file implements runtime fixups for Qualcomm DT to improve
+ * compatibility with U-Boot. This includes adjusting the USB nodes
+ * to only use USB high-speed, as well as remapping volume buttons
+ * to behave as up/down for navigating U-Boot.
+ *
+ * We use OF_LIVE for this rather than early FDT fixup for a couple
+ * of reasons: it has a much nicer API, is most likely more efficient,
+ * and our changes are only applied to U-Boot. This allows us to use a
+ * DT designed for Linux, run U-Boot with a modified version, and then
+ * boot Linux with the original FDT.
+ *
+ * Copyright (c) 2024 Linaro Ltd.
+ *   Author: Caleb Connolly 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* U-Boot only supports USB high-speed mode on Qualcomm platforms with DWC3
+ * USB controllers. Rather than requiring source level DT changes, we fix up
+ * DT here. This improves compatibility with upstream DT and simplifies the
+ * porting process for new devices.
+ */
+static int fixup_qcom_dwc3(struct device_node *glue_np)
+{
+   struct device_node *dwc3;
+   int ret, len, hsphy_idx = 1;
+   const __be32 *phandles;
+   const char *second_phy_name;
+
+   debug("Fixing up %s\n", glue_np->name);
+
+   /* Tell the glue driver to configure the wrapper for high-speed only 
operation */
+   ret = of_write_prop(glue_np, "qcom,select-utmi-as-pipe-clk", 0, NULL);
+   if (ret) {
+   log_err("Failed to add property 'qcom,select-utmi-as-pipe-clk': 
%d\n", ret);
+   return ret;
+   }
+
+   /* Find the DWC3 node itself */
+   dwc3 = of_find_compatible_node(glue_np, NULL, "snps,dwc3");
+   if (!dwc3) {
+   log_err("Failed to find dwc3 node\n");
+   return -ENOENT;
+   }
+
+   phandles = of_get_property(dwc3, "phys", );
+   len /= sizeof(*phandles);
+   if (len == 1) {
+   log_debug("Only one phy, not a superspeed controller\n");
+   return 0;
+   }
+
+   /* Figure out if the superspeed phy is present and if so then which phy 
is it? */
+   ret = of_property_read_string_index(dwc3, "phy-names", 1, 
_phy_name);
+   if (ret == -ENODATA) {
+   log_debug("Only one phy, not a super-speed controller\n");
+   return 0;
+   } else if (ret) {
+   log_err("Failed to read second phy name: %d\n", ret);
+   return ret;
+   }
+
+   if (!strncmp("usb3-phy", second_phy_name, strlen("usb3-phy"))) {
+   log_debug("Second phy isn't superspeed (is '%s') assuming first 
phy is SS\n",
+ second_phy_name);
+   hsphy_idx = 0;
+   }
+
+   /* Overwrite the "phys" property to only contain the high-speed phy */
+   ret = of_write_prop(dwc3, "phys", sizeof(*phandles), phandles + 
hsphy_idx);
+   if (ret) {
+   log_err("Failed to 

[PATCH v2 09/14] serial: msm-geni: support livetree

[Caleb Connolly]

When using OF_LIVE, the debug UART driver won't be probed if it's a
subnode of the geni-se-qup controller. Add a NOP driver for the
controller to correctly discover its child nodes.

Signed-off-by: Caleb Connolly 
---
 drivers/serial/serial_msm_geni.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 4aa0bc8c72bc..5260474fb9a4 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -605,8 +605,21 @@ U_BOOT_DRIVER(serial_msm_geni) = {
.ops = _serial_ops,
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
 };
 
+static const struct udevice_id geniqup_ids[] = {
+   { .compatible = "qcom,geni-se-qup" },
+   { }
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+   .name = "geni-se-qup",
+   .id = UCLASS_NOP,
+   .of_match = geniqup_ids,
+   .bind = dm_scan_fdt_dev,
+   .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
+
 #ifdef CONFIG_DEBUG_UART_MSM_GENI
 
 static struct msm_serial_data init_serial_data = {
.base = CONFIG_VAL(DEBUG_UART_BASE)

-- 
2.44.0

[PATCH v2 08/14] gpio: msm_gpio: add .set_flags op

[Caleb Connolly]

The .direction_input and .direction_output ops are deprecated, and don't
seem to behave properly for us. Implement our own .set_flags op to
handle this correctly.

Signed-off-by: Caleb Connolly 
---
 drivers/gpio/msm_gpio.c | 27 +--
 1 file changed, 21 insertions(+), 6 deletions(-)

diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index 5e57b0cbde75..f5d9ab54e817 100644
--- a/drivers/gpio/msm_gpio.c
+++ b/drivers/gpio/msm_gpio.c
@@ -34,21 +34,21 @@ struct msm_gpio_bank {
 
 #define GPIO_IN_OUT_REG(dev, x) \
(GPIO_CONFIG_REG(dev, x) + 0x4)
 
-static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
+static void msm_gpio_direction_input(struct udevice *dev, unsigned int gpio)
 {
struct msm_gpio_bank *priv = dev_get_priv(dev);
 
/* Always NOP for special pins, assume they're in the correct state */
if (qcom_is_special_pin(priv->pin_data, gpio))
-   return 0;
+   return;
 
/* Disable OE bit */
clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio),
GPIO_OE_MASK, GPIO_OE_DISABLE);
 
-   return 0;
+   return;
 }
 
 static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int 
value)
 {
@@ -83,8 +83,25 @@ static int msm_gpio_direction_output(struct udevice *dev, 
unsigned int gpio,
 
return 0;
 }
 
+static int msm_gpio_set_flags(struct udevice *dev, unsigned int gpio, ulong 
flags)
+{
+   if (flags & GPIOD_IS_OUT_ACTIVE) {
+   return msm_gpio_direction_output(dev, gpio, 1);
+   } else if (flags & GPIOD_IS_OUT) {
+   return msm_gpio_direction_output(dev, gpio, 0);
+   } else if (flags & GPIOD_IS_IN) {
+   msm_gpio_direction_input(dev, gpio);
+   if (flags & GPIOD_PULL_UP)
+   return msm_gpio_set_value(dev, gpio, 1);
+   else if (flags & GPIOD_PULL_DOWN)
+   return msm_gpio_set_value(dev, gpio, 0);
+   }
+
+   return 0;
+}
+
 static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio)
 {
struct msm_gpio_bank *priv = dev_get_priv(dev);
 
@@ -109,12 +126,10 @@ static int msm_gpio_get_function(struct udevice *dev, 
unsigned int gpio)
return GPIOF_INPUT;
 }
 
 static const struct dm_gpio_ops gpio_msm_ops = {
-   .direction_input= msm_gpio_direction_input,
-   .direction_output   = msm_gpio_direction_output,
+   .set_flags  = msm_gpio_set_flags,
.get_value  = msm_gpio_get_value,
-   .set_value  = msm_gpio_set_value,
.get_function   = msm_gpio_get_function,
 };
 
 static int msm_gpio_probe(struct udevice *dev)

-- 
2.44.0

[PATCH v2 06/14] clk/qcom: sdm845: add gdscs

[Caleb Connolly]

Define the GDSC power domains for SDM845.

Signed-off-by: Caleb Connolly 
---
 drivers/clk/qcom/clock-sdm845.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index ccb0cf245d33..b7154360894a 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -145,13 +145,31 @@ static const struct qcom_reset_map sdm845_gcc_resets[] = {
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
 };
 
+static const struct qcom_power_map sdm845_gdscs[] = {
+   [PCIE_0_GDSC] = { 0x6b004 },
+   [PCIE_1_GDSC] = { 0x8d004 },
+   [UFS_CARD_GDSC] = { 0x75004 },
+   [UFS_PHY_GDSC] = { 0x77004 },
+   [USB30_PRIM_GDSC] = { 0xf004 },
+   [USB30_SEC_GDSC] = { 0x10004 },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC] = { 0x7d030 },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC] = { 0x7d03c },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC] = { 0x7d034 },
+   [HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC] = { 0x7d038 },
+   [HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC] = { 0x7d040 },
+   [HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC] = { 0x7d048 },
+   [HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC] = { 0x7d044 },
+};
+
 static struct msm_clk_data sdm845_clk_data = {
.resets = sdm845_gcc_resets,
.num_resets = ARRAY_SIZE(sdm845_gcc_resets),
.clks = sdm845_clks,
.num_clks = ARRAY_SIZE(sdm845_clks),
+   .power_domains = sdm845_gdscs,
+   .num_power_domains = ARRAY_SIZE(sdm845_gdscs),
 
.enable = sdm845_clk_enable,
.set_rate = sdm845_clk_set_rate,
 };

-- 
2.44.0

[PATCH v2 07/14] clk/qcom: sdm845: add USB clocks

[Caleb Connolly]

Most devices only initialise the USB clocks for us if we boot via
"fastboot boot", add the missing clock configuration to get both USB
ports working regardless of the bootloader state.

Signed-off-by: Caleb Connolly 
---
 drivers/clk/qcom/clock-sdm845.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index b7154360894a..e9c61eb480de 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -20,8 +20,12 @@
 #include "clock-qcom.h"
 
 #define SE9_UART_APPS_CMD_RCGR 0x18148
 
+#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf018
+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf030
+#define USB3_PRIM_PHY_AUX_CMD_RCGR 0xf05c
+
 static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
F(1920, CFG_CLK_SRC_CXO, 1, 0, 0),
@@ -56,8 +60,10 @@ static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
}
 }
 
 static const struct gate_clk sdm845_clks[] = {
+   GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK,0x82020, 0x0001),
+   GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK,  0x05030, 0x0001),
GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK,0x5200c, 0x0400),
GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK,0x5200c, 0x0800),
GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK,0x5200c, 0x1000),
GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK,0x5200c, 0x2000),
@@ -120,8 +126,27 @@ static int sdm845_clk_enable(struct clk *clk)
struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
 
+   switch (clk->id) {
+   case GCC_USB30_PRIM_MASTER_CLK:
+   qcom_gate_clk_en(priv, GCC_USB_PHY_CFG_AHB2PHY_CLK);
+   /* These numbers are just pulled from the frequency tables in 
the Linux driver */
+   clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
+(4.5 * 2) - 1, 0, 0, 1 << 8, 8);
+   clk_rcg_set_rate_mnd(priv->base, 
USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR,
+1, 0, 0, 0, 8);
+   clk_rcg_set_rate_mnd(priv->base, USB3_PRIM_PHY_AUX_CMD_RCGR,
+1, 0, 0, 0, 8);
+   break;
+   case GCC_USB30_SEC_MASTER_CLK:
+   qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
+
+   qcom_gate_clk_en(priv, GCC_USB3_SEC_CLKREF_CLK);
+   qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
+   break;
+   }
+
qcom_gate_clk_en(priv, clk->id);
 
return 0;
 }

-- 
2.44.0

[PATCH v2 05/14] clk/qcom: use offsets for RCG registers

[Caleb Connolly]

The RCG registers always have the same offsets, so only store the base
CMD register address and calculate the others relative to that.

Signed-off-by: Caleb Connolly 
---
 drivers/clk/qcom/clock-apq8016.c |  39 +
 drivers/clk/qcom/clock-apq8096.c |  28 +
 drivers/clk/qcom/clock-qcom.c|  22 +++
 drivers/clk/qcom/clock-qcom.h|  16 +++---
 drivers/clk/qcom/clock-qcs404.c  | 121 +--
 drivers/clk/qcom/clock-sdm845.c  |  16 +-
 6 files changed, 39 insertions(+), 203 deletions(-)

diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c
index e6647f7c41dd..5a5868169c89 100644
--- a/drivers/clk/qcom/clock-apq8016.c
+++ b/drivers/clk/qcom/clock-apq8016.c
@@ -22,13 +22,9 @@
 #define APCS_GPLL_ENA_VOTE (0x45000)
 #define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
 
 #define SDCC_BCR(n)((n * 0x1000) + 0x41000)
-#define SDCC_CMD_RCGR(n)   ((n * 0x1000) + 0x41004)
-#define SDCC_CFG_RCGR(n)   ((n * 0x1000) + 0x41008)
-#define SDCC_M(n)  ((n * 0x1000) + 0x4100C)
-#define SDCC_N(n)  ((n * 0x1000) + 0x41010)
-#define SDCC_D(n)  ((n * 0x1000) + 0x41014)
+#define SDCC_CMD_RCGR(n)   (((n + 1) * 0x1000) + 0x41004)
 #define SDCC_APPS_CBCR(n)  ((n * 0x1000) + 0x41018)
 #define SDCC_AHB_CBCR(n)   ((n * 0x1000) + 0x4101C)
 
 /* BLSP1 AHB clock (root clock for BLSP) */
@@ -37,33 +33,12 @@
 /* Uart clock control registers */
 #define BLSP1_UART2_BCR(0x3028)
 #define BLSP1_UART2_APPS_CBCR  (0x302C)
 #define BLSP1_UART2_APPS_CMD_RCGR  (0x3034)
-#define BLSP1_UART2_APPS_CFG_RCGR  (0x3038)
-#define BLSP1_UART2_APPS_M (0x303C)
-#define BLSP1_UART2_APPS_N (0x3040)
-#define BLSP1_UART2_APPS_D (0x3044)
 
 /* GPLL0 clock control registers */
 #define GPLL0_STATUS_ACTIVE BIT(17)
 
-static const struct bcr_regs sdc_regs[] = {
-   {
-   .cfg_rcgr = SDCC_CFG_RCGR(1),
-   .cmd_rcgr = SDCC_CMD_RCGR(1),
-   .M = SDCC_M(1),
-   .N = SDCC_N(1),
-   .D = SDCC_D(1),
-   },
-   {
-   .cfg_rcgr = SDCC_CFG_RCGR(2),
-   .cmd_rcgr = SDCC_CMD_RCGR(2),
-   .M = SDCC_M(2),
-   .N = SDCC_N(2),
-   .D = SDCC_D(2),
-   }
-};
-
 static struct pll_vote_clk gpll0_vote_clk = {
.status = GPLL0_STATUS,
.status_bit = GPLL0_STATUS_ACTIVE,
.ena_vote = APCS_GPLL_ENA_VOTE,
@@ -85,32 +60,24 @@ static int clk_init_sdc(struct msm_clk_priv *priv, int 
slot, uint rate)
div = 4;
 
clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
/* 800Mhz/div, gpll0 */
-   clk_rcg_set_rate_mnd(priv->base, _regs[slot], div, 0, 0,
+   clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0,
 CFG_CLK_SRC_GPLL0, 8);
clk_enable_gpll0(priv->base, _vote_clk);
clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
 
return rate;
 }
 
-static const struct bcr_regs uart2_regs = {
-   .cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
-   .cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
-   .M = BLSP1_UART2_APPS_M,
-   .N = BLSP1_UART2_APPS_N,
-   .D = BLSP1_UART2_APPS_D,
-};
-
 /* UART: 115200 */
 int apq8016_clk_init_uart(phys_addr_t base)
 {
/* Enable AHB clock */
clk_enable_vote_clk(base, _blsp1_ahb_clk);
 
/* 7372800 uart block clock @ GPLL0 */
-   clk_rcg_set_rate_mnd(base, _regs, 1, 144, 15625,
+   clk_rcg_set_rate_mnd(base, BLSP1_UART2_APPS_CMD_RCGR, 1, 144, 15625,
 CFG_CLK_SRC_GPLL0, 16);
 
/* Vote for gpll0 clock */
clk_enable_gpll0(base, _vote_clk);
diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c
index a4731613c5e0..479f9771a464 100644
--- a/drivers/clk/qcom/clock-apq8096.c
+++ b/drivers/clk/qcom/clock-apq8096.c
@@ -25,33 +25,17 @@
 #define SDCC2_BCR  (0x14000) /* block reset */
 #define SDCC2_APPS_CBCR(0x14004) /* branch control */
 #define SDCC2_AHB_CBCR (0x14008)
 #define SDCC2_CMD_RCGR (0x14010)
-#define SDCC2_CFG_RCGR (0x14014)
-#define SDCC2_M(0x14018)
-#define SDCC2_N(0x1401C)
-#define SDCC2_D(0x14020)
 
 #define BLSP2_AHB_CBCR (0x25004)
 #define BLSP2_UART2_APPS_CBCR  (0x29004)
 #define BLSP2_UART2_APPS_CMD_RCGR  (0x2900C)
-#define BLSP2_UART2_APPS_CFG_RCGR  (0x29010)
-#define BLSP2_UART2_APPS_M (0x29014)
-#define BLSP2_UART2_APPS_N (0x29018)
-#define BLSP2_UART2_APPS_D (0x2901C)
 
 /* GPLL0 clock control registers */
 #define GPLL0_STATUS_ACTIVEBIT(30)
 #define APCS_GPLL_ENA_VOTE_GPLL0   BIT(0)
 
-static const struct bcr_regs 

[PATCH v2 03/14] phy: qcom: Add USB HS 7nm PHY driver

[Caleb Connolly]

From: Bhupesh Sharma 

Some Qualcomm SoCs newer than SDM845 feature a so-called "7nm phy"
driver, notable the SM8250 SoC which will gain U-Boot support in
upcoming patches.

Introduce a driver based on the Linux driver.

Signed-off-by: Bhupesh Sharma 
[code cleanup, switch to clk/reset_bulk APIs]
Signed-off-by: Caleb Connolly 
---
 drivers/phy/qcom/Kconfig   |   8 +
 drivers/phy/qcom/Makefile  |   1 +
 drivers/phy/qcom/phy-qcom-usb-hs-7nm.c | 295 +
 3 files changed, 304 insertions(+)

diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index 361dfb6e1126..3fc59dc65650 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -18,8 +18,16 @@ config PHY_QCOM_QUSB2
help
  Enable this to support the Super-Speed USB transceiver on various
  Qualcomm chipsets.
 
+config PHY_QCOM_USB_HS_7NM
+   tristate "Qualcomm 7nm High-Speed PHY"
+   depends on PHY && ARCH_SNAPDRAGON
+   help
+ Enable this to support the Qualcomm Synopsys DesignWare Core 7nm
+ High-Speed PHY driver. This driver supports the Hi-Speed PHY which
+ is usually paired with Synopsys DWC3 USB IPs on MSM SOCs.
+
 config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on PHY && ARCH_SNAPDRAGON
help
diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
index f6af985666a4..39219ecd24aa 100644
--- a/drivers/phy/qcom/Makefile
+++ b/drivers/phy/qcom/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
 obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
+obj-$(CONFIG_PHY_QCOM_USB_HS_7NM) += phy-qcom-usb-hs-7nm.o
 obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
 obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qcom/phy-qcom-usb-hs-7nm.c 
b/drivers/phy/qcom/phy-qcom-usb-hs-7nm.c
new file mode 100644
index ..65128b45937b
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-usb-hs-7nm.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Bhupesh Sharma 
+ *
+ * Based on Linux driver
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
+#define SLEEPM BIT(0)
+#define OPMODE_MASK GENMASK(4, 3)
+#define OPMODE_NORMAL (0x00)
+#define OPMODE_NONDRIVING BIT(3)
+#define TERMSEL BIT(5)
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40)
+#define XCVRSEL BIT(0)
+
+#define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50)
+#define POR BIT(1)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54)
+#define SIDDQ BIT(2)
+#define RETENABLEN BIT(3)
+#define FSEL_MASK GENMASK(6, 4)
+#define FSEL_DEFAULT (0x3 << 4)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58)
+#define VBUSVLDEXTSEL0 BIT(4)
+#define PLLBTUNE BIT(5)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c)
+#define VREGBYPASS BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60)
+#define VBUSVLDEXT0 BIT(0)
+
+#define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64)
+#define USB2_AUTO_RESUME BIT(0)
+#define USB2_SUSPEND_N BIT(2)
+#define USB2_SUSPEND_N_SEL BIT(3)
+
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74)
+#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78)
+#define PARAM_OVRD_MASK 0xFF
+
+#define USB2_PHY_USB_PHY_CFG0 (0x94)
+#define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0)
+#define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1)
+
+#define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0)
+#define REFCLK_SEL_MASK GENMASK(1, 0)
+#define REFCLK_SEL_DEFAULT (0x2 << 0)
+
+#define HS_DISCONNECT_MASK GENMASK(2, 0)
+#define SQUELCH_DETECTOR_MASK GENMASK(7, 5)
+
+#define HS_AMPLITUDE_MASK GENMASK(3, 0)
+#define PREEMPHASIS_DURATION_MASK BIT(5)
+#define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6)
+
+#define HS_RISE_FALL_MASK GENMASK(1, 0)
+#define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2)
+#define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4)
+
+#define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0)
+
+#define SNPS_HS_NUM_VREGS ARRAY_SIZE(hs_7nm_vreg_names)
+
+struct override_param {
+   s32 value;
+   u8 reg_val;
+};
+
+struct override_param_map {
+   const char *prop_name;
+   const struct override_param *param_table;
+   u8 table_size;
+   u8 reg_offset;
+   u8 param_mask;
+};
+
+struct phy_override_seq {
+   bool need_update;
+   u8 offset;
+   u8 value;
+   u8 mask;
+};
+
+#define NUM_HSPHY_TUNING_PARAMS (9)
+
+/* struct hs_7nm_phy_cfg - per-PHY initialization config */
+struct hs_7nm_phy_cfg {
+   /* resets to be requested */
+   struct reset_ctl *resets;
+   int num_resets;
+
+   struct override_param_map *map_cfg;
+   struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS];
+};
+
+/**
+ * struct 

[PATCH v2 04/14] mach-snapdragon: disable power-domains for pre-reloc drivers

[Caleb Connolly]

Some devices like the UART and clock controller reference an RPM(h)
power domain. We don't support this device in U-Boot, so add
DM_FLAG_DEFAULT_PD_CTRL_OFF to tell DM core not to try and enable the
power domain.

Signed-off-by: Caleb Connolly 
---
 drivers/clk/qcom/clock-qcom.c| 2 ++
 drivers/clk/qcom/clock-sdm845.c  | 2 +-
 drivers/serial/serial_msm_geni.c | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 7a5938a06a34..6303dcbf8461 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -226,8 +226,9 @@ U_BOOT_DRIVER(qcom_clk) = {
.id = UCLASS_CLK,
.ops= _clk_ops,
.priv_auto  = sizeof(struct msm_clk_priv),
.probe  = msm_clk_probe,
+   .flags  = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
 };
 
 int qcom_cc_bind(struct udevice *parent)
 {
@@ -410,5 +411,6 @@ U_BOOT_DRIVER(qcom_power) = {
.name = "qcom_power",
.id = UCLASS_POWER_DOMAIN,
.ops = _power_ops,
.probe = qcom_power_probe,
+   .flags = DM_FLAG_PRE_RELOC,
 };
diff --git a/drivers/clk/qcom/clock-sdm845.c b/drivers/clk/qcom/clock-sdm845.c
index 36ffee79d966..babd83119e2c 100644
--- a/drivers/clk/qcom/clock-sdm845.c
+++ b/drivers/clk/qcom/clock-sdm845.c
@@ -182,6 +182,6 @@ U_BOOT_DRIVER(gcc_sdm845) = {
.name   = "gcc_sdm845",
.id = UCLASS_NOP,
.of_match   = gcc_sdm845_of_match,
.bind   = qcom_cc_bind,
-   .flags  = DM_FLAG_PRE_RELOC,
+   .flags  = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
 };
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index e5c3dcffc1c6..4aa0bc8c72bc 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -602,9 +602,9 @@ U_BOOT_DRIVER(serial_msm_geni) = {
.of_to_plat = msm_serial_ofdata_to_platdata,
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops = _serial_ops,
-   .flags = DM_FLAG_PRE_RELOC,
+   .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
 };
 
 #ifdef CONFIG_DEBUG_UART_MSM_GENI
 

-- 
2.44.0

[PATCH v2 02/14] phy: qcom: add Qualcomm QUSB2 USB PHY driver

[Caleb Connolly]

From: Bhupesh Sharma 

The Snapdragon 845 and several other Qualcomm SoCs feature this
USB high-speed phy. Add a driver for it based on the Linux driver, with
support for the SDM845, and the QCM2290 and SM6115 SoCs which will gain
support in U-Boot in future patches.

Signed-off-by: Bhupesh Sharma 
[code cleanup, switch to clk_bulk]
Signed-off-by: Caleb Connolly 
---
 drivers/phy/qcom/Kconfig  |   7 +
 drivers/phy/qcom/Makefile |   1 +
 drivers/phy/qcom/phy-qcom-qusb2.c | 468 ++
 3 files changed, 476 insertions(+)

diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig
index f4ca174805a4..361dfb6e1126 100644
--- a/drivers/phy/qcom/Kconfig
+++ b/drivers/phy/qcom/Kconfig
@@ -11,8 +11,15 @@ config PHY_QCOM_IPQ4019_USB
depends on PHY && ARCH_IPQ40XX
help
  Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
 
+config PHY_QCOM_QUSB2
+   tristate "Qualcomm USB QUSB2 PHY driver"
+   depends on PHY && ARCH_SNAPDRAGON
+   help
+ Enable this to support the Super-Speed USB transceiver on various
+ Qualcomm chipsets.
+
 config PHY_QCOM_USB_HS_28NM
tristate "Qualcomm 28nm High-Speed PHY"
depends on PHY && ARCH_SNAPDRAGON
help
diff --git a/drivers/phy/qcom/Makefile b/drivers/phy/qcom/Makefile
index 2113f178c0c7..f6af985666a4 100644
--- a/drivers/phy/qcom/Makefile
+++ b/drivers/phy/qcom/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_PHY_QCOM_IPQ4019_USB) += phy-qcom-ipq4019-usb.o
 obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o
+obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
 obj-$(CONFIG_PHY_QCOM_USB_HS_28NM) += phy-qcom-usb-hs-28nm.o
 obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o
diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c 
b/drivers/phy/qcom/phy-qcom-qusb2.c
new file mode 100644
index ..5b654403a181
--- /dev/null
+++ b/drivers/phy/qcom/phy-qcom-qusb2.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Bhupesh Sharma 
+ *
+ * Based on Linux driver
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define QUSB2PHY_PLL 0x0
+#define QUSB2PHY_PLL_TEST 0x04
+#define CLK_REF_SEL BIT(7)
+
+#define QUSB2PHY_PLL_TUNE 0x08
+#define QUSB2PHY_PLL_USER_CTL1 0x0c
+#define QUSB2PHY_PLL_USER_CTL2 0x10
+#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
+#define QUSB2PHY_PLL_PWR_CTRL 0x18
+
+/* QUSB2PHY_PLL_STATUS register bits */
+#define PLL_LOCKED BIT(5)
+
+/* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
+#define CORE_READY_STATUS BIT(0)
+
+/* QUSB2PHY_PORT_POWERDOWN register bits */
+#define CLAMP_N_EN BIT(5)
+#define FREEZIO_N BIT(1)
+#define POWER_DOWN BIT(0)
+
+/* QUSB2PHY_PWR_CTRL1 register bits */
+#define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5)
+#define PWR_CTRL1_CLAMP_N_EN BIT(1)
+
+#define QUSB2PHY_REFCLK_ENABLE BIT(0)
+
+#define PHY_CLK_SCHEME_SEL BIT(0)
+
+/* QUSB2PHY_INTR_CTRL register bits */
+#define DMSE_INTR_HIGH_SEL BIT(4)
+#define DPSE_INTR_HIGH_SEL BIT(3)
+#define CHG_DET_INTR_EN BIT(2)
+#define DMSE_INTR_EN BIT(1)
+#define DPSE_INTR_EN BIT(0)
+
+/* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
+#define CORE_PLL_EN_FROM_RESET BIT(4)
+#define CORE_RESET BIT(5)
+#define CORE_RESET_MUX BIT(6)
+
+/* QUSB2PHY_IMP_CTRL1 register bits */
+#define IMP_RES_OFFSET_MASK GENMASK(5, 0)
+#define IMP_RES_OFFSET_SHIFT 0x0
+
+/* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */
+#define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0)
+#define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0
+
+/* QUSB2PHY_CHG_CONTROL_2 register bits */
+#define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4)
+#define CHG_CTRL2_OFFSET_SHIFT 0x4
+
+/* QUSB2PHY_PORT_TUNE1 register bits */
+#define HSTX_TRIM_MASK GENMASK(7, 4)
+#define HSTX_TRIM_SHIFT 0x4
+#define PREEMPH_WIDTH_HALF_BIT BIT(2)
+#define PREEMPHASIS_EN_MASK GENMASK(1, 0)
+#define PREEMPHASIS_EN_SHIFT 0x0
+
+/* QUSB2PHY_PORT_TUNE2 register bits */
+#define HSDISC_TRIM_MASK GENMASK(1, 0)
+#define HSDISC_TRIM_SHIFT 0x0
+
+#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04
+#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c
+#define QUSB2PHY_PLL_CMODE 0x2c
+#define QUSB2PHY_PLL_LOCK_DELAY 0x184
+#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4
+#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194
+#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198
+#define QUSB2PHY_PWR_CTRL2 0x214
+#define QUSB2PHY_IMP_CTRL1 0x220
+#define QUSB2PHY_IMP_CTRL2 0x224
+#define QUSB2PHY_CHG_CTRL2 0x23c
+
+struct qusb2_phy_init_tbl {
+   unsigned int offset;
+   unsigned int val;
+   /*
+* register part of layout ?
+* if yes, then offset gives index in the reg-layout
+*/
+   int in_layout;
+};
+
+struct qusb2_phy_cfg {
+   const struct qusb2_phy_init_tbl *tbl;
+   /* number of entries in the table */
+   unsigned int tbl_num;
+   /* offset to PHY_CLK_SCHEME register in TCSR map */
+   unsigned int clk_scheme_offset;
+
+   /* array of registers with different offsets */
+   const unsigned int 

[PATCH v2 01/14] mailmap: update Bhupesh's email address

[Caleb Connolly]

Update Bhupesh's email to his new one.

Signed-off-by: Caleb Connolly 
---

Cc: Bhupesh Sharma 
---
 .mailmap | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.mailmap b/.mailmap
index d1f08f3eca8a..f6e0847b2168 100644
--- a/.mailmap
+++ b/.mailmap
@@ -29,8 +29,9 @@ Ashok Reddy Soma  

 Atish Patra  
 Bharat Kumar Gogada  

 Bharat Kumar Gogada  
 Bhargava Sreekantappa Gayathri  

+Bhupesh Sharma  
 Bin Meng  
 Boris Brezillon  
 Boris Brezillon  
 Christian Kohn  

-- 
2.44.0

[PATCH v2 00/14] Qualcomm platform USB support

[Caleb Connolly]

This series enables USB on Qualcomm SDM845 platforms and lays the
foundation for future SoCs as well.

It introduces two new high-speed PHY drivers, one for SDM845 and one for
an upcoming platform. The SDM845 clock driver gains support for
configuring the USB clocks, and the GPIO driver is updated to use .set_flags
which fixes a strange bug where GPIOs would also be configured as input.

Support for super-speed USB modes is not currently available, however
configuring the device to be high-speed only requires modifications to
DT.

To improve compatibility with upstream DT, we switch Qualcomm platforms
over to OF_LIVE and apply fixups to the tree to remove references to the
super-speed phy, as well as configure the Qualcomm glue for high-speed
only mode.

The db845c requires a vbus-supply to be hooked up for its usb type-A
port. A U-Boot dtsi file is added to configure this.

With these patches, it is now also possible to run U-Boot on some SDM845
phones like the OnePlus 6 using a dtb from Linux, and access the U-Boot
shell via the CDC ACM USB serial gadget.

This series depends on the ("Qualcomm DWC3 USB support") series [1], as
well as Volodymyrs patches enabling power domain support [2].
A feature branch based on qcom-next with the necessary dependencies
for testing the Dragonboard845c can be found at [3].

[1]: 
https://lore.kernel.org/u-boot/20240315-b4-qcom-usb-v2-0-5467ec27c...@linaro.org
[2]: 
https://lore.kernel.org/u-boot/20240311213334.3567389-1-volodymyr_babc...@epam.com
[3]: https://git.codelinaro.org/linaro/qcomlt/u-boot/-/tree/b4/qcom-livetree

---
Changes in v2:
- Fix incorrect order of NULL/0 parameters to of_write_prob() in
  fixup_qcom_dwc3()
- Move fixup_usb_nodes() to a separate file in preparation for future
  additions.
- Add missing break to switch case in sdm845_clk_enable()
- Remove rogue return statement in msm_gpio_set_flags()
- Rebase on Volodymyrs power domain patches.
- Link to v1: 
https://lore.kernel.org/r/20240131-b4-qcom-livetree-v1-0-4071c0787...@linaro.org

---
Bhupesh Sharma (2):
  phy: qcom: add Qualcomm QUSB2 USB PHY driver
  phy: qcom: Add USB HS 7nm PHY driver

Caleb Connolly (12):
  mailmap: update Bhupesh's email address
  mach-snapdragon: disable power-domains for pre-reloc drivers
  clk/qcom: use offsets for RCG registers
  clk/qcom: sdm845: add gdscs
  clk/qcom: sdm845: add USB clocks
  gpio: msm_gpio: add .set_flags op
  serial: msm-geni: support livetree
  mach-snapdragon: fixup USB nodes
  mach-snapdragon: fixup power-domains
  dts: sdm845-db845c: add u-boot fixups
  qcom_defconfig: enable livetree
  qcom_defconfig: enable USB

 .mailmap   |   1 +
 arch/arm/dts/sdm845-db845c-u-boot.dtsi |   8 +
 arch/arm/mach-snapdragon/Makefile  |   1 +
 arch/arm/mach-snapdragon/board.c   |   3 +
 arch/arm/mach-snapdragon/of_fixup.c| 147 +++
 arch/arm/mach-snapdragon/qcom-priv.h   |  19 ++
 configs/qcom_defconfig |  15 ++
 drivers/clk/qcom/clock-apq8016.c   |  39 +--
 drivers/clk/qcom/clock-apq8096.c   |  28 +-
 drivers/clk/qcom/clock-qcom.c  |  24 +-
 drivers/clk/qcom/clock-qcom.h  |  16 +-
 drivers/clk/qcom/clock-qcs404.c| 121 ++---
 drivers/clk/qcom/clock-sdm845.c|  61 +++--
 drivers/gpio/msm_gpio.c|  27 +-
 drivers/phy/qcom/Kconfig   |  15 ++
 drivers/phy/qcom/Makefile  |   2 +
 drivers/phy/qcom/phy-qcom-qusb2.c  | 468 +
 drivers/phy/qcom/phy-qcom-usb-hs-7nm.c | 295 +
 drivers/serial/serial_msm_geni.c   |  15 +-
 19 files changed, 1094 insertions(+), 211 deletions(-)
---
base-commit: 6b65bdc55f5ddb1318d1f702f27d3f6d058d001d

// Caleb (they/them)

[PATCH v2 5/5] iommu: qcom-smmu: fix debugging

[Caleb Connolly]

The priv struct was wrong in dump_boot_mappings(). Causing errors when
compiling with -DDEBUG. Fix this.

Reviewed-by: Mattijs Korpershoek 
Signed-off-by: Caleb Connolly 
---
 drivers/iommu/qcom-hyp-smmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/qcom-hyp-smmu.c b/drivers/iommu/qcom-hyp-smmu.c
index 8e5cdb581550..f2b39de56f4a 100644
--- a/drivers/iommu/qcom-hyp-smmu.c
+++ b/drivers/iommu/qcom-hyp-smmu.c
@@ -318,9 +318,9 @@ static int qcom_smmu_connect(struct udevice *dev)
return 0;
 }
 
 #ifdef DEBUG
-static inline void dump_boot_mappings(struct arm_smmu_priv *priv)
+static inline void dump_boot_mappings(struct qcom_smmu_priv *priv)
 {
u32 val;
int i;
 

-- 
2.44.0

[PATCH v2 4/5] usb: gadget: UMS: support multiple sector sizes

[Caleb Connolly]

UFS storage often uses a 4096-byte sector size, add support for dynamic
sector sizes based loosely on the Linux implementation.

Reviewed-by: Mattijs Korpershoek 
Signed-off-by: Caleb Connolly 
---
 cmd/usb_mass_storage.c  |   4 --
 drivers/usb/gadget/f_mass_storage.c | 101 
 drivers/usb/gadget/storage_common.c |  12 +++--
 include/usb_mass_storage.h  |   1 -
 4 files changed, 65 insertions(+), 53 deletions(-)

diff --git a/cmd/usb_mass_storage.c b/cmd/usb_mass_storage.c
index a8ddeb494628..751701fe73af 100644
--- a/cmd/usb_mass_storage.c
+++ b/cmd/usb_mass_storage.c
@@ -87,12 +87,8 @@ static int ums_init(const char *devtype, const char 
*devnums_part_str)
 */
if (!strchr(devnum_part_str, ':'))
partnum = 0;
 
-   /* f_mass_storage.c assumes SECTOR_SIZE sectors */
-   if (block_dev->blksz != SECTOR_SIZE)
-   goto cleanup;
-
ums_new = realloc(ums, (ums_count + 1) * sizeof(*ums));
if (!ums_new)
goto cleanup;
ums = ums_new;
diff --git a/drivers/usb/gadget/f_mass_storage.c 
b/drivers/usb/gadget/f_mass_storage.c
index c725aed3f626..d880928044f4 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -723,14 +723,15 @@ static int do_read(struct fsg_common *common)
if (lba >= curlun->num_sectors) {
curlun->sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
return -EINVAL;
}
-   file_offset = ((loff_t) lba) << 9;
+   file_offset = ((loff_t)lba) << curlun->blkbits;
 
/* Carry out the file reads */
amount_left = common->data_size_from_cmnd;
-   if (unlikely(amount_left == 0))
+   if (unlikely(amount_left == 0)) {
return -EIO;/* No default reply */
+   }
 
for (;;) {
 
/* Figure out how much we need to read:
@@ -767,15 +768,15 @@ static int do_read(struct fsg_common *common)
}
 
/* Perform the read */
rc = ums[common->lun].read_sector([common->lun],
- file_offset / SECTOR_SIZE,
- amount / SECTOR_SIZE,
+ file_offset / curlun->blksize,
+ amount / curlun->blksize,
  (char __user *)bh->buf);
if (!rc)
return -EIO;
 
-   nread = rc * SECTOR_SIZE;
+   nread = rc * curlun->blksize;
 
VLDBG(curlun, "file read %u @ %llu -> %d\n", amount,
(unsigned long long) file_offset,
(int) nread);
@@ -786,9 +787,9 @@ static int do_read(struct fsg_common *common)
nread = 0;
} else if (nread < amount) {
LDBG(curlun, "partial file read: %d/%u\n",
(int) nread, amount);
-   nread -= (nread & 511); /* Round down to a block */
+   nread -= (nread & (curlun->blksize - 1));   /* 
Round down to a block */
}
file_offset  += nread;
amount_left  -= nread;
common->residue -= nread;
@@ -860,9 +861,9 @@ static int do_write(struct fsg_common *common)
}
 
/* Carry out the file writes */
get_some_more = 1;
-   file_offset = usb_offset = ((loff_t) lba) << 9;
+   file_offset = usb_offset = ((loff_t)lba) << curlun->blkbits;
amount_left_to_req = common->data_size_from_cmnd;
amount_left_to_write = common->data_size_from_cmnd;
 
while (amount_left_to_write > 0) {
@@ -892,9 +893,9 @@ static int do_write(struct fsg_common *common)
SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;
curlun->info_valid = 1;
continue;
}
-   amount -= (amount & 511);
+   amount -= (amount & (curlun->blksize - 1));
if (amount == 0) {
 
/* Why were we were asked to transfer a
 * partial block? */
@@ -941,14 +942,14 @@ static int do_write(struct fsg_common *common)
amount = bh->outreq->actual;
 
/* Perform the write */
rc = ums[common->lun].write_sector([common->lun],
-  file_offset / SECTOR_SIZE,
-  amount / SECTOR_SIZE,
+  file_offset / curlun->blksize,
+  amount / curlun->blksize,
  

[PATCH v2 3/5] usb: gadget: CDC ACM: call usb_gadget_initialize

[Caleb Connolly]

To actually use the gadget the peripheral driver must be probed and we
must call g_dnl_clear_detach(). Otherwise acm_stdio_start() will always
fail to find a UDC on DT platforms.

Reviewed-by: Mattijs Korpershoek 
Signed-off-by: Caleb Connolly 
---
 drivers/usb/gadget/f_acm.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/usb/gadget/f_acm.c b/drivers/usb/gadget/f_acm.c
index de42e0189e8d..ba216128ab27 100644
--- a/drivers/usb/gadget/f_acm.c
+++ b/drivers/usb/gadget/f_acm.c
@@ -622,14 +622,23 @@ static void acm_stdio_puts(struct stdio_dev *dev, const 
char *str)
 }
 
 static int acm_stdio_start(struct stdio_dev *dev)
 {
+   struct udevice *udc;
int ret;
 
if (dev->priv) { /* function already exist */
return 0;
}
 
+   ret = udc_device_get_by_index(0, );
+   if (ret) {
+   pr_err("USB init failed: %d\n", ret);
+   return ret;
+   }
+
+   g_dnl_clear_detach();
+
ret = g_dnl_register("usb_serial_acm");
if (ret)
return ret;
 

-- 
2.44.0

[PATCH v2 2/5] usb: dwc3: select DM_USB_GADGET

[Caleb Connolly]

DWC3 platforms depend on DM_USB_GADGET for gadget drivers to work,
otherwise compilation fails due to no implementation of
dm_usb_gadget_handle_interrupts().

Reviewed-by: Mattijs Korpershoek 
Signed-off-by: Caleb Connolly 
---
 drivers/usb/dwc3/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index c0c8c16fd9c2..8a70bc682322 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -10,8 +10,9 @@ if USB_DWC3
 config USB_DWC3_GADGET
bool "USB Gadget support for DWC3"
default y
depends on USB_GADGET
+   select DM_USB_GADGET
select USB_GADGET_DUALSPEED
 
 comment "Platform Glue Driver Support"
 

-- 
2.44.0

[PATCH v2 1/5] usb: dwc3-generic: implement Qualcomm wrapper

[Caleb Connolly]

The Qualcomm specific dwc3 wrapper isn't hugely complicated, implemented
the missing initialisation for host and gadget mode.

Reviewed-by: Mattijs Korpershoek 
Signed-off-by: Caleb Connolly 
---
 drivers/usb/dwc3/dwc3-generic.c | 81 -
 1 file changed, 80 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index a379a0002e77..5a355dd86c60 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -424,8 +424,79 @@ enum dwc3_omap_utmi_mode {
 struct dwc3_glue_ops ti_ops = {
.glue_configure = dwc3_ti_glue_configure,
 };
 
+/* USB QSCRATCH Hardware registers */
+#define QSCRATCH_HS_PHY_CTRL 0x10
+#define UTMI_OTG_VBUS_VALID BIT(20)
+#define SW_SESSVLD_SEL BIT(28)
+
+#define QSCRATCH_SS_PHY_CTRL 0x30
+#define LANE0_PWR_PRESENT BIT(24)
+
+#define QSCRATCH_GENERAL_CFG 0x08
+#define PIPE_UTMI_CLK_SEL BIT(0)
+#define PIPE3_PHYSTATUS_SW BIT(3)
+#define PIPE_UTMI_CLK_DIS BIT(8)
+
+#define PWR_EVNT_IRQ_STAT_REG 0x58
+#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
+#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
+
+#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
+#define SDM845_QSCRATCH_SIZE 0x400
+#define SDM845_DWC3_CORE_SIZE 0xcd00
+
+static void dwc3_qcom_vbus_override_enable(void __iomem *qscratch_base, bool 
enable)
+{
+   if (enable) {
+   setbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
+ LANE0_PWR_PRESENT);
+   setbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
+ UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
+   } else {
+   clrbits_le32(qscratch_base + QSCRATCH_SS_PHY_CTRL,
+ LANE0_PWR_PRESENT);
+   clrbits_le32(qscratch_base + QSCRATCH_HS_PHY_CTRL,
+ UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
+   }
+}
+
+/* For controllers running without superspeed PHYs */
+static void dwc3_qcom_select_utmi_clk(void __iomem *qscratch_base)
+{
+   /* Configure dwc3 to use UTMI clock as PIPE clock not present */
+   setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_DIS);
+
+   setbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
+
+   clrbits_le32(qscratch_base + QSCRATCH_GENERAL_CFG,
+ PIPE_UTMI_CLK_DIS);
+}
+
+static void dwc3_qcom_glue_configure(struct udevice *dev, int index,
+enum usb_dr_mode mode)
+{
+   struct dwc3_glue_data *glue = dev_get_plat(dev);
+   void __iomem *qscratch_base = (void __iomem *)glue->regs;
+   if (IS_ERR_OR_NULL(qscratch_base)) {
+   log_err("%s: Invalid qscratch base address\n", dev->name);
+   return;
+   }
+
+   if (dev_read_bool(dev, "qcom,select-utmi-as-pipe-clk"))
+   dwc3_qcom_select_utmi_clk(qscratch_base);
+
+   if (mode != USB_DR_MODE_HOST)
+   dwc3_qcom_vbus_override_enable(qscratch_base, true);
+}
+
+struct dwc3_glue_ops qcom_ops = {
+   .glue_configure = dwc3_qcom_glue_configure,
+};
+
 static int dwc3_rk_glue_get_ctrl_dev(struct udevice *dev, ofnode *node)
 {
*node = dev_ofnode(dev);
if (!ofnode_valid(*node))
@@ -511,8 +582,16 @@ static int dwc3_glue_reset_init(struct udevice *dev,
return 0;
else if (ret)
return ret;
 
+   if (device_is_compatible(dev, "qcom,dwc3")) {
+   reset_assert_bulk(>resets);
+   /* We should wait at least 6 sleep clock cycles, that's
+* (6 / 32764) * 100 ~= 200us. But some platforms
+* have slower sleep clocks so we'll play it safe.
+*/
+   udelay(500);
+   }
ret = reset_deassert_bulk(>resets);
if (ret) {
reset_release_bulk(>resets);
return ret;
@@ -628,9 +707,9 @@ static const struct udevice_id dwc3_glue_ids[] = {
{ .compatible = "rockchip,rk3328-dwc3", .data = (ulong)_ops },
{ .compatible = "rockchip,rk3399-dwc3" },
{ .compatible = "rockchip,rk3568-dwc3", .data = (ulong)_ops },
{ .compatible = "rockchip,rk3588-dwc3", .data = (ulong)_ops },
-   { .compatible = "qcom,dwc3" },
+   { .compatible = "qcom,dwc3", .data = (ulong)_ops },
{ .compatible = "fsl,imx8mp-dwc3", .data = (ulong)_ops },
{ .compatible = "fsl,imx8mq-dwc3" },
{ .compatible = "intel,tangier-dwc3" },
{ }

-- 
2.44.0

[PATCH v2 0/5] Qualcomm DWC3 USB support

[Caleb Connolly]

This series enables support for Qualcomm platforms in the DWC3 driver,
adds support for arbitrary sector sizes to the USB mass storage gadget,
and fixes an issue with the CDC ACM driver where it wouldn't initialise
the USB device.

Additionally, it fixes a syntax bug in the Qualcomm SMMU driver, and
makes USB_DWC3_GADGET select DM_USB_GADGET to fix compilation with
gadget mode.

This is part of a larger series enabling DWC3 USB support on Qualcomm
platforms, a feature branch with all patches can be found at [1].

[1]: 
https://source.denx.de/u-boot/custodians/u-boot-snapdragon/-/tree/b4/qcom-livetree

---
Changes in v2:
- Drop custom set/clrbits implementation in qcom dwc3 glue.
- Additional minor cleanup based on Marek's comments.
- Link to v1: 
https://lore.kernel.org/r/20240131-b4-qcom-usb-v1-0-6438b2a22...@linaro.org

---
Caleb Connolly (5):
  usb: dwc3-generic: implement Qualcomm wrapper
  usb: dwc3: select DM_USB_GADGET
  usb: gadget: CDC ACM: call usb_gadget_initialize
  usb: gadget: UMS: support multiple sector sizes
  iommu: qcom-smmu: fix debugging

 cmd/usb_mass_storage.c  |   4 --
 drivers/iommu/qcom-hyp-smmu.c   |   2 +-
 drivers/usb/dwc3/Kconfig|   1 +
 drivers/usb/dwc3/dwc3-generic.c |  81 -
 drivers/usb/gadget/f_acm.c  |   9 
 drivers/usb/gadget/f_mass_storage.c | 101 
 drivers/usb/gadget/storage_common.c |  12 +++--
 include/usb_mass_storage.h  |   1 -
 8 files changed, 156 insertions(+), 55 deletions(-)
---
base-commit: e03a71b2cefd86ba58df166d4ea820a215ebb655

// Caleb (they/them)

[PATCH v1] arm: imx: imx8m: soc: Fix NPU/VPU fdt disable fixup

[Vitor Soares]

From: Vitor Soares 

On imx8m[m|p|q].dtsi, upstream Linux uses different names for NPU/VPU
IP block nodes. It leads variants without such HW block having it
enabled by default.

This patch adds the upstream Linux node's paths to the disable list while
keep the compatibility with downstream Linux.

Signed-off-by: Vitor Soares 
---
 arch/arm/mach-imx/imx8m/soc.c | 18 ++
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 39802d6a79..0c49fb9cd4 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -933,19 +933,28 @@ int disable_vpu_nodes(void *blob)
 {
static const char * const nodes_path_8mq[] = {
"/vpu@3830",
-   "/soc@0/vpu@3830"
+   "/soc@0/vpu@3830",
+   "/soc@0/video-codec@3830",
+   "/soc@0/video-codec@3831",
+   "/soc@0/blk-ctrl@3832",
};
 
static const char * const nodes_path_8mm[] = {
"/vpu_g1@3830",
"/vpu_g2@3831",
-   "/vpu_h1@3832"
+   "/vpu_h1@3832",
+   "/soc@0/video-codec@3830",
+   "/soc@0/video-codec@3831",
+   "/soc@0/blk-ctrl@3833",
};
 
static const char * const nodes_path_8mp[] = {
"/vpu_g1@3830",
"/vpu_g2@3831",
-   "/vpu_vc8000e@3832"
+   "/vpu_vc8000e@3832",
+   "/soc@0/video-codec@3830",
+   "/soc@0/video-codec@3831",
+   "/soc@0/blk-ctrl@3833",
};
 
if (is_imx8mq())
@@ -1100,7 +1109,8 @@ int disable_gpu_nodes(void *blob)
 int disable_npu_nodes(void *blob)
 {
static const char * const nodes_path_8mp[] = {
-   "/vipsi@3850"
+   "/vipsi@3850",
+   "/soc@0/npu@3850",
};
 
return disable_fdt_nodes(blob, nodes_path_8mp, 
ARRAY_SIZE(nodes_path_8mp));
-- 
2.34.1

Re: [PATCH] CI: Move to latest container image

[Tom Rini]

On Thu, 14 Mar 2024 22:36:43 -0400, Tom Rini wrote:

> This moves us to our latest container image, which is now based on the
> current "Jammy" tag.
> 
> 

Applied to u-boot/next, thanks!

-- 
Tom

Re: [PATCH] CI: Cherry-pick reset support for m68k for QEMU

[Tom Rini]

On Mon, 11 Mar 2024 10:02:43 -0400, Tom Rini wrote:

> In order to support the reset pytest on QEMU on m68k platforms we need
> to grab this change from upstream.
> 
> 

Applied to u-boot/next, thanks!

-- 
Tom

Re: [PATCH] CI: Update to using clang-17

[Tom Rini]

On Sun, 10 Mar 2024 15:59:28 -0400, Tom Rini wrote:

> Currently, llvm-17 is the stable release. Update our container and CI to
> fetch and use that.
> 
> 

Applied to u-boot/next, thanks!

-- 
Tom

Re: [PATCH 1/1] Dockerfile: install xilinx-bootgen package

[Tom Rini]

On Wed, 28 Feb 2024 08:23:09 +0100, Heinrich Schuchardt wrote:

> Bootgen is used in a binman test. The test is skipped without the binary.
> 
> 

Applied to u-boot/next, thanks!

-- 
Tom

Re: [PATCH 1/1] Dockerfile: build fiptool

[Tom Rini]

On Wed, 28 Feb 2024 08:43:11 +0100, Heinrich Schuchardt wrote:

> Fiptool is used in a binman test. The test is skipped without the binary.
> 
> 

Applied to u-boot/next, thanks!

-- 
Tom

[PATCH v2 2/2] rockchip: rock-pi-4-rk3399: enable booting from SPI flash

[Christopher Obbard]

Some variants of the ROCK Pi 4 series have an SPI flash chip populated
which can be booted from. This patch enables support in U-Boot for
building the image for the SPI flash, support for booting U-Boot from the
SPI flash chip and support in U-Boot for accessing the SPI flash using
`sf` commands.

Not all variants (e.g. ROCK Pi 4B, ROCK 4 Model C Plus, ROCK 4SE) come
populated with an SPI flash chip, but have the footprint on the board so
a user could solder their own to the board. With this patchset applied,
these board variants without an SPI flash chip still boot from MMC.

I have enabled support for both Winbond and XTX SPI flash devices since
different hardware variants have different devices populated:

 - `rockpi4_v13_sch_20181112.pdf` contains a Winbond part `W25Q64FWZPIG`
 - `rockpi4_v14_sch_20210114.pdf` contains an XTX part `XT25F32BWOIGT`

The ROCK Pi 4 I have is marked as "ROCK PI 4 v1.48" and contains an SPI
flash chip from XTX:

=> sf probe
SF: Detected xt25f32 with page size 256 Bytes, erase size 4 KiB, total 4 MiB

In the interest of supporting all board variants and not regressing
existing users who boot from MMC, I have enabled support for booting from
both SPI flash chip variants in the defconfig and left the environment
storage location as MMC to not break existing users who have the
environment stored on MMC.

Signed-off-by: Christopher Obbard 

---

Changes in v2:
- Rebase on top of rockchip/for-next.
- Sync configuration changes with savedefconfig.
- Remove GigaDevice SPI flash chip support (suggested by Kever Y).
- Re-enable CONFIG_SPL_FIT_SIGNATURE=y (fixed in rockchip/for-next, solves
  multiple problems mentioned in v1. Thanks Jonas!).
- Remove spl-boot-order from rk3399-rock-pi-4a-u-boot.dtsi (suggested by
  Jonas K).
- Enable CONFIG_SPI_FLASH_SFDP_SUPPORT=y (suggested by Jonas K).

 arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi |  7 +++
 configs/rock-pi-4-rk3399_defconfig | 17 ++---
 2 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi 
b/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
index 85ee5770add..38385621deb 100644
--- a/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi
@@ -4,3 +4,10 @@
  */
 
 #include "rk3399-rock-pi-4-u-boot.dtsi"
+
+ {
+   flash@0 {
+   bootph-pre-ram;
+   bootph-some-ram;
+   };
+};
diff --git a/configs/rock-pi-4-rk3399_defconfig 
b/configs/rock-pi-4-rk3399_defconfig
index bca44beca12..315b8b853fc 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++ b/configs/rock-pi-4-rk3399_defconfig
@@ -3,25 +3,30 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_COUNTER_FREQUENCY=2400
 CONFIG_ARCH_ROCKCHIP=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_SF_DEFAULT_SPEED=1000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4a"
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_ROCKCHIP_RK3399=y
+CONFIG_ROCKCHIP_SPI_IMAGE=y
 CONFIG_TARGET_ROCKPI4_RK3399=y
 CONFIG_DEBUG_UART_BASE=0xFF1A
 CONFIG_DEBUG_UART_CLOCK=2400
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
 CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_PCI=y
 CONFIG_DEBUG_UART=y
 # CONFIG_ANDROID_BOOT_IMAGE is not set
 CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4a.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_MAX_SIZE=0x2e000
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_PAD_TO=0x7f8000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SYS_SPI_U_BOOT_OFFS=0xE
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
 CONFIG_TPL=y
 CONFIG_CMD_BOOTZ=y
@@ -40,14 +45,20 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names 
interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_ROCKCHIP_IODOMAIN=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_SF_DEFAULT_BUS=1
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XTX=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
 CONFIG_NVME_PCI=y
@@ -61,6 +72,7 @@ CONFIG_RAM_ROCKCHIP_LPDDR4=y
 CONFIG_BAUDRATE=150
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_ROCKCHIP_SPI=y
 CONFIG_SYSRESET=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
@@ -81,7 +93,6 @@ CONFIG_VIDEO=y
 CONFIG_DISPLAY=y
 CONFIG_VIDEO_ROCKCHIP=y
 CONFIG_DISPLAY_ROCKCHIP_HDMI=y
-CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
 CONFIG_EFI_CAPSULE_ON_DISK=y
 CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
-- 
2.43.0

[PATCH v2 1/2] arm: rockchip: sync ROCK Pi 4A DTS from Linux

[Christopher Obbard]

To prepare for ROCK Pi 4A SPI flash support, sync the DTS from Linux which
includes an SPI flash node.

Kernel tag: v6.6-rc1
Kernel commits:
 - eddf73029770 ("arm64: dts: rockchip: Enable internal SPI flash for ROCK \
  Pi 4A/B/C")

Reviewed-by: Kever Yang 
Signed-off-by: Christopher Obbard 
---

Changes in v2:
- Collect Reviewed-by tag from Kever Y.

 arch/arm/dts/rk3399-rock-pi-4a.dts | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/rk3399-rock-pi-4a.dts 
b/arch/arm/dts/rk3399-rock-pi-4a.dts
index 931334aa3d6..d5df8939a65 100644
--- a/arch/arm/dts/rk3399-rock-pi-4a.dts
+++ b/arch/arm/dts/rk3399-rock-pi-4a.dts
@@ -12,3 +12,13 @@
model = "Radxa ROCK Pi 4A";
compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399";
 };
+
+ {
+   status = "okay";
+
+   flash@0 {
+   compatible = "jedec,spi-nor";
+   reg = <0>;
+   spi-max-frequency = <1000>;
+   };
+};
-- 
2.43.0

[PATCH v2 0/2] Enable booting from SPI flash on ROCK Pi 4

[Christopher Obbard]

This series brings up and enables booting from the SPI flash present on
some variants of the ROCK Pi 4 in U-Boot.

The first patch syncs the ROCK Pi 4A devicetree from Linux, which contains
the SPI flash node.

The second patch enables support in U-Boot for the SPI flash chip and
booting U-Boot from the SPI flash on the Radxa ROCK Pi 4.

This series may be found at [0].

[0]: 
https://gitlab.collabora.com/obbardc/u-boot/-/tree/wip/obbardc/rockchip-rock4-enable-spi-boot-v2

Changes in v2:
- Collect Reviewed-by tags.
- Rebase on top of rockchip/for-next.
- Sync configuration changes with savedefconfig.
- Remove GigaDevice SPI flash chip support (suggested by Kever Y).
- Re-enable CONFIG_SPL_FIT_SIGNATURE=y (fixed in rockchip/for-next, solves
  multiple problems mentioned in v1. Thanks Jonas!).
- Remove spl-boot-order from rk3399-rock-pi-4a-u-boot.dtsi (suggested by
  Jonas K).
- Enable CONFIG_SPI_FLASH_SFDP_SUPPORT=y (suggested by Jonas K).
- v1: https://lists.denx.de/pipermail/u-boot/2024-March/547173.html

Christopher Obbard (2):
  arm: rockchip: sync ROCK Pi 4A DTS from Linux
  rockchip: rock-pi-4-rk3399: enable booting from SPI flash

 arch/arm/dts/rk3399-rock-pi-4a-u-boot.dtsi |  7 +++
 arch/arm/dts/rk3399-rock-pi-4a.dts | 10 ++
 configs/rock-pi-4-rk3399_defconfig | 17 ++---
 3 files changed, 31 insertions(+), 3 deletions(-)

-- 
2.43.0

Re: [PATCH 1/2] arm64: Reduce add_map() complexity

[Fabio Estevam]

Hi Marc,

On Sat, Mar 9, 2024 at 11:36 AM Fabio Estevam  wrote:

> Does the log below help?
>
> https://pastebin.com/raw/1i1VBA0a
>
> If not, please send me a debug patch and I will be glad to run it here.

I'm sorry to bother you, but have you had a chance to look at the log
I shared with you?

That's the only issue preventing colibri-imx8x from booting mainline U-Boot.

We would like to get this fixed for U-Boot 2024.04.

Thanks for your help

Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus

[Sumit Garg]

On Fri, 15 Mar 2024 at 14:53, Marek Vasut  wrote:
>
> On 3/15/24 6:31 AM, Sumit Garg wrote:
> > On Thu, 14 Mar 2024 at 09:45, Marek Vasut  wrote:
> >>
> >> On 3/12/24 8:03 AM, Sumit Garg wrote:
> >>> power_domain_on/off() isn't refcounted and power domain bus shouldn't be
> >>> turned off for a single peripheral domain as it would negatively affect
> >>> other peripheral domains. So lets just skip turning off bus power
> >>> domain.
> >>
> >> What exactly is the issue and how did you trigger it ?
> >>
> >> Details please.
> >
> > I suppose the issue can be triggered via the "=> usb start => usb
> > stop" sequence where one of the USB controllers is configured in
> > peripheral mode.
>
> 'usb start ; usb stop' causes no problems on MX8MP , maybe the test case
> is more extensive ?
>
> Please, write down the necessary steps to reproduce this problem, and
> what happens when that problem occurs.

After digging in more, it looks like dev_power_domain_off() is never
(U-Boot life-cycle) invoked for USB controller devices derived from
DT. So this USB power domain sequence is never reachable.

BTW, dev_power_domain_on() is invoked when USB controller devices are
added based on DT.

>
> >>> Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
> >>> Signed-off-by: Sumit Garg 
> >>> ---
> >>>drivers/power/domain/imx8mp-hsiomix.c | 6 +-
> >>>1 file changed, 1 insertion(+), 5 deletions(-)
> >>>
> >>> diff --git a/drivers/power/domain/imx8mp-hsiomix.c 
> >>> b/drivers/power/domain/imx8mp-hsiomix.c
> >>> index e2d772c5ec7..448746432a2 100644
> >>> --- a/drivers/power/domain/imx8mp-hsiomix.c
> >>> +++ b/drivers/power/domain/imx8mp-hsiomix.c
> >>> @@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain 
> >>> *power_domain)
> >>>
> >>>ret = power_domain_on(domain);
> >>>if (ret)
> >>> - goto err_pd;
> >>> + return ret;
> >>>
> >>>ret = clk_enable(>clk_usb);
> >>>if (ret)
> >>> @@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain 
> >>> *power_domain)
> >>>
> >>>err_clk:
> >>>power_domain_off(domain);
> >>> -err_pd:
> >>> - power_domain_off(>pd_bus);
> >>>return ret;
> >>
> >> Why not add counter into imx8mp_hsiomix_priv structure in this driver ?
> >
> > Sure I can do that but do you think the current approach can have any
> > side effects?
>
> Bus domain not getting cycled (which can leave it in some odd state),
> and increased power consumption if the next stage doesn't turn the
> domain off.

Given above, would you like me to drop power domain off path entirely
here? I think if people are concerned about power consumption then it
should be implemented properly in U-Boot to remove all the DT based
devices before passing on control to the next stage.

-Sumit

RE: [PATCH 2/5] mmc: zynq-sdhci: refactor tapdelay settings

[Abbarapu, Venkatesh]

Hi Steffen,
For mini u-boot cases ZYNQMP_FIRMWARE config is disabled as there won't be any 
ATF(TF-A) present.

Thanks
Venkatesh

> -Original Message-
> From: Steffen Dirkwinkel 
> Sent: Thursday, March 14, 2024 1:23 PM
> To: Kumar, Love ; u-boot@lists.denx.de
> Cc: Algapally Santosh Sagar ; Ashok
> Reddy Soma ; Jaehoon Chung
> ; Johan Jonker ; Simek,
> Michal ; Peng Fan ; Tom Rini
> ; Abbarapu, Venkatesh
> 
> Subject: Re: [PATCH 2/5] mmc: zynq-sdhci: refactor tapdelay settings
> 
> Hi Love,
> 
> On Thu, 2024-03-14 at 12:15 +0530, Love Kumar wrote:
> > Hi,
> >
> > When we run in el3 for zynqmp board, we are seeing below issue with
> > this
> > patch:
> >
> >
> > Model: ZynqMP MINI EMMC0
> > Board: Xilinx ZynqMP
> > DRAM:  512 MiB
> > EL Level:  EL3
> > Secure Boot:   not authenticated, not encrypted
> > Multiboot: 0
> > Core:  10 devices, 9 uclasses, devicetree: embed
> > MMC:   sdhci@ff16: 0
> > Loading Environment from ... OK
> > In:    dcc
> > Out:   dcc
> > Err:   dcc
> > ZynqMP> mmc list
> > sdhci@ff16: 0
> > ZynqMP> mmc dev 0 0
> > arasan_sdhci sdhci@ff16: Error setting Input Tap Delay
> > sdhci_set_clock: Error while setting tap delay
> > sdhci_send_command: Timeout for status update:  0001
> > ZynqMP>
> 
> Thank you for testing this.
> It looks like the zynqmp-mini-emmc0 device lacks the power-domain node
> and doesn't have a sd node id. The code before my change would have
> ignored the unknown node id, applied settings for sdhci1 instead of sdhci0
> and returned without an error. Maybe there's a different way to find out
> which sdhci we want to operate on?
> 
> Can you try setting the node id in device tree?
> Something like this:
> 
> diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-
> mini-emmc0.dts
> index 02e80bd85e1..87c4a1b6ad0 100644
> --- a/arch/arm/dts/zynqmp-mini-emmc0.dts
> +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
> @@ -7,6 +7,8 @@
>   * Siva Durga Prasad Paladugu 
>   */
> 
> +#include 
> +
>  /dts-v1/;
> 
>  / {
> @@ -41,6 +43,12 @@
> clock-frequency = <2>;
> };
> 
> +   firmware {
> +   zynqmp_firmware: zynqmp-firmware {
> +   #power-domain-cells = <1>;
> +   };
> +   };
> +
> amba: amba {
> compatible = "simple-bus";
> #address-cells = <2>;
> @@ -56,6 +64,7 @@
> reg = <0x0 0xff16 0x0 0x1000>;
> clock-names = "clk_xin", "clk_ahb";
> clocks = <_xin _xin>;
> +   power-domains = <_firmware PD_SD_0>;
> };
> };
>  };
> 
> Thanks,
> Steffen
> 
> >
> > Regards,
> > Love Kumar
> >
> > On 23/02/24 7:36 pm, Steffen Dirkwinkel wrote:
> > > From: Steffen Dirkwinkel 
> > >
> > > Previously we were setting in tapdelay for SD1 every time even if
> > > SD0 was requested.
> > > The SD tapdelay settings are shifted by 16 bits between SD0 and SD1.
> > > We can use that to make our tapdelay setup simpler. This is also how
> > > it currently works in arm-trusted-firmware.
> > >
> > > Signed-off-by: Steffen Dirkwinkel 
> > > ---
> > >
> > >   drivers/mmc/zynq_sdhci.c | 65
> > > +---
> > >   1 file changed, 28 insertions(+), 37 deletions(-)
> > >
> > > diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
> > > index 935540d1719..d4845245b2a 100644
> > > --- a/drivers/mmc/zynq_sdhci.c
> > > +++ b/drivers/mmc/zynq_sdhci.c
> > > @@ -42,14 +42,11 @@
> > >   #define SD_OTAP_DLY 0xFF180318
> > >   #define SD0_DLL_RST BIT(2)
> > >   #define SD1_DLL_RST BIT(18)
> > > +#define SD1_TAP_OFFSET   16
> > >   #define SD0_ITAPCHGWIN  BIT(9)
> > > -#define SD1_ITAPCHGWIN   BIT(25)
> > >   #define SD0_ITAPDLYENA  BIT(8)
> > > -#define SD1_ITAPDLYENA   BIT(24)
> > >   #define SD0_ITAPDLYSEL_MASK GENMASK(7, 0)
> > > -#define SD1_ITAPDLYSEL_MASK  GENMASK(23, 16)
> > >   #define SD0_OTAPDLYSEL_MASK GENMASK(5, 0)
> > > -#define SD1_OTAPDLYSEL_MASK  GENMASK(21, 16)
> > >
> > >   #define MIN_PHY_CLK_HZ  5000
> > >
> > > @@ -275,44 +272,32 @@ static int arasan_sdhci_config_dll(struct
> > > sdhci_host *host, unsigned int clock,
> > >   static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32
> > > itap_delay)
> > >   {
> > >   int ret;
> > > + u32 shift;
> > >
> > > - if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
> > > - if (node_id == NODE_SD_0) {
> > > - ret = zynqmp_mmio_write(SD_ITAP_DLY,
> SD0_ITAPCHGWIN,
> > > - SD0_ITAPCHGWIN);
> > > - if (ret)
> > > - return ret;
> > > -
> > > - ret = zynqmp_mmio_write(SD_ITAP_DLY,
> 

Re: [PATCH v3 04/11] imx8mp: power-domain: Don't power off pd_bus

[Marek Vasut]

On 3/15/24 6:31 AM, Sumit Garg wrote:

On Thu, 14 Mar 2024 at 09:45, Marek Vasut  wrote:


On 3/12/24 8:03 AM, Sumit Garg wrote:

power_domain_on/off() isn't refcounted and power domain bus shouldn't be
turned off for a single peripheral domain as it would negatively affect
other peripheral domains. So lets just skip turning off bus power
domain.


What exactly is the issue and how did you trigger it ?

Details please.


I suppose the issue can be triggered via the "=> usb start => usb
stop" sequence where one of the USB controllers is configured in
peripheral mode.


'usb start ; usb stop' causes no problems on MX8MP , maybe the test case 
is more extensive ?


Please, write down the necessary steps to reproduce this problem, and 
what happens when that problem occurs.



Fixes: 898e7610c62a ("imx: power-domain: Add i.MX8MP HSIOMIX driver")
Signed-off-by: Sumit Garg 
---
   drivers/power/domain/imx8mp-hsiomix.c | 6 +-
   1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/power/domain/imx8mp-hsiomix.c 
b/drivers/power/domain/imx8mp-hsiomix.c
index e2d772c5ec7..448746432a2 100644
--- a/drivers/power/domain/imx8mp-hsiomix.c
+++ b/drivers/power/domain/imx8mp-hsiomix.c
@@ -50,7 +50,7 @@ static int imx8mp_hsiomix_on(struct power_domain 
*power_domain)

   ret = power_domain_on(domain);
   if (ret)
- goto err_pd;
+ return ret;

   ret = clk_enable(>clk_usb);
   if (ret)
@@ -63,8 +63,6 @@ static int imx8mp_hsiomix_on(struct power_domain 
*power_domain)

   err_clk:
   power_domain_off(domain);
-err_pd:
- power_domain_off(>pd_bus);
   return ret;


Why not add counter into imx8mp_hsiomix_priv structure in this driver ?


Sure I can do that but do you think the current approach can have any
side effects?


Bus domain not getting cycled (which can leave it in some odd state), 
and increased power consumption if the next stage doesn't turn the 
domain off.

Re: [PATCH] mtd: nand: raw: mt7621-nand: allow writing ecc region in raw mode

[高惟杰]

On Wed, 2024-03-13 at 07:41 +0100, Michael Nazzareno Trimarchi wrote:
>
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>  Hi
> 
> On Wed, Mar 13, 2024 at 4:38 AM Weijie Gao 
> wrote:
> >
> > Allow writing ecc parity region in raw mode. This makes sure the
> > nand write.raw command can write the flash data as-is.
> >
> > Change-Id: Ibed3bdf13c9cf81e54041c5ac7a78192b97dcedc
> > Signed-off-by: Weijie Gao 
> > CR-Id: WCNCR00180092
> 
> I think this is for internal tracking
> 
> > ---
> >  drivers/mtd/nand/raw/mt7621_nand.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/mtd/nand/raw/mt7621_nand.c
> b/drivers/mtd/nand/raw/mt7621_nand.c
> > index f6eddb84a9..341ef0bf2d 100644
> > --- a/drivers/mtd/nand/raw/mt7621_nand.c
> > +++ b/drivers/mtd/nand/raw/mt7621_nand.c
> > @@ -1003,9 +1003,9 @@ static int mt7621_nfc_write_page_raw(struct
> mtd_info *mtd,
> > mt7621_nfc_write_data(nfc, oob_fdm_ptr(nand, i),
> >   NFI_FDM_SIZE);
> >
> > -   /* Write dummy ECC parity data */
> > -   mt7621_nfc_write_data_empty(nfc, nfc-
> >spare_per_sector -
> > -   NFI_FDM_SIZE);
> > +   /* Write ECC parity data */
> > +   mt7621_nfc_write_data(nfc, oob_ecc_ptr(nfc, i),
> > + nfc->spare_per_sector -
> NFI_FDM_SIZE);
> > }
> >
> 
> Please describe better what regression you are trying to fix in the
> commit message
> Reviewed-by: Michael Trimarchi 

In fact this patch is not fixing any regression. It just provide the
ability to read/write the whole NAND page with ECC disabled.
Users/developers can the be able to debug NAND related issue or do
anything they want.

> 
> Michael
> 
> > mt7621_nfc_wait_write_completion(nfc, nand);
> > --
> > 2.34.1
> >
> 
> 

Re: [PATCH] efi_loader: accept append write with valid size and data

[Heinrich Schuchardt]

On 3/15/24 08:03, Ilias Apalodimas wrote:

Hi Kojima-san

On Fri, 15 Mar 2024 at 02:10,  wrote:


Hi Ilias,


-Original Message-
From: Ilias Apalodimas 
Sent: Thursday, March 14, 2024 10:54 PM
To: Kojima, Masahisa/小島 雅久 
Cc: u-boot@lists.denx.de; Heinrich Schuchardt 
Subject: Re: [PATCH] efi_loader: accept append write with valid size and data

Hi Kojima-san

Apologies for the late reply

On Mon, 4 Mar 2024 at 08:10, Masahisa Kojima
 wrote:


Current "variables" efi_selftest result is inconsistent
between the U-Boot file storage and the tee-based StandaloneMM
RPMB secure storage.
U-Boot file storage implementation does not accept SetVariale
call to non-existent variable with EFI_VARIABLE_APPEND_WRITE
attribute and valid size and data, however it is accepted
in EDK II StandaloneMM implementation.


Yes,



Since UEFI specification does not clearly describe the behavior
of the append write to non-existent variable, let's update
the U-Boot file storage implementation to get aligned with
the EDK II reference implementation.

Signed-off-by: Masahisa Kojima 
---
  lib/efi_loader/efi_variable.c | 13 +-
  lib/efi_selftest/efi_selftest_variables.c | 30

+--

  2 files changed, 35 insertions(+), 8 deletions(-)

diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index 40f7a0fb10..1693c3387b 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -282,11 +282,8 @@ efi_status_t efi_set_variable_int(const u16

*variable_name,

 }
 time = var->time;
 } else {
-   if (delete || append)
-   /*
-* Trying to delete or to update a non-existent
-* variable.
-*/
+   if (delete)
+   /* Trying to delete a non-existent variable. */
 return EFI_NOT_FOUND;


I am not sure about this tbh. The UEFI spec says
"When the EFI_VARIABLE_APPEND_WRITE attribute is set, then a
SetVariable() call with a DataSize of zero will not cause any change
to the variable value (the timestamp
associated with the variable may be updated however, even if no new
data value is provided;see the description
of the EFI_VARIABLE_AUTHENTICATION_2 descriptor below). In this case
the DataSize will not be zero
since the EFI_VARIABLE_AUTHENTICATION_2 descriptor will be populated)"

I think this assumes the variable exists. Is there a different chapter
in the spec that describes the behavior?


No, I could not find it.
I'm also not sure what the UEFI spec expects.


I don't have any objections to aligning this with EDK2. But can we add
a comment about it as well?
Heinrich any preference here?

[...]


non-existent variable returns wrong code\n");

+   efi_st_error("Variable was not deleted\n");
 return EFI_ST_FAILURE;


This used to fail as well [0]. Does it work now?


Yes. With this patch applied, both U-Boot file storage and StMM
pass the efi selftest.


Yes, that's obviously a hack. The reason we didn't bother fixing it
back then is because stmm is not running in our CI, but I should have
added a comment on that instead of having it on email history...


Hello Kojima,

Thank you for pointing out the inconsistencies.

I have created https://mantis.uefi.org/mantis/view.php?id=2447 to
discuss the expected behavior.

The logic in MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c is:

If the variable does not exist and EFI_VARIABLE_APPEND_WRITE is set and
the size is non-zero, the variable is created.
If the variable does not exist and EFI_VARIABLE_APPEND_WRITE is set and
the size is zero, the variable is not created and EFI_SUCCESS is returned.

I am not able to derive this from the specification.

In our selftest we should test the following four cases of
EFI_VARIABLE_APPEND_WRITE:

variable existing, size non-zero
variable existing, size zero
variable non-existent, size non-zero
variable non-existent, size zero

Could you, please, check if the StMM logic matches
MdeModulePkg/Universal/Variable/RuntimeDxe/Variable.c for all four cases.

If yes, we should change the our file based implementation to match these.

Best regards

Heinrich




 }
 /* Enumerate variables */
--
2.34.1



[0]
https://lore.kernel.org/u-boot/CAC_iWjL2G2mvQb6WNGLTxr+xj64xrYuOKr8G
3-3z8lv7yx5...@mail.gmail.com/

Regards
/Ilias

Re: [PATCH] efi_loader: accept append write with valid size and data

[Ilias Apalodimas]

Hi Kojima-san

On Fri, 15 Mar 2024 at 02:10,  wrote:
>
> Hi Ilias,
>
> > -Original Message-
> > From: Ilias Apalodimas 
> > Sent: Thursday, March 14, 2024 10:54 PM
> > To: Kojima, Masahisa/小島 雅久 
> > Cc: u-boot@lists.denx.de; Heinrich Schuchardt 
> > Subject: Re: [PATCH] efi_loader: accept append write with valid size and 
> > data
> >
> > Hi Kojima-san
> >
> > Apologies for the late reply
> >
> > On Mon, 4 Mar 2024 at 08:10, Masahisa Kojima
> >  wrote:
> > >
> > > Current "variables" efi_selftest result is inconsistent
> > > between the U-Boot file storage and the tee-based StandaloneMM
> > > RPMB secure storage.
> > > U-Boot file storage implementation does not accept SetVariale
> > > call to non-existent variable with EFI_VARIABLE_APPEND_WRITE
> > > attribute and valid size and data, however it is accepted
> > > in EDK II StandaloneMM implementation.
> >
> > Yes,
> >
> > >
> > > Since UEFI specification does not clearly describe the behavior
> > > of the append write to non-existent variable, let's update
> > > the U-Boot file storage implementation to get aligned with
> > > the EDK II reference implementation.
> > >
> > > Signed-off-by: Masahisa Kojima 
> > > ---
> > >  lib/efi_loader/efi_variable.c | 13 +-
> > >  lib/efi_selftest/efi_selftest_variables.c | 30
> > +--
> > >  2 files changed, 35 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
> > > index 40f7a0fb10..1693c3387b 100644
> > > --- a/lib/efi_loader/efi_variable.c
> > > +++ b/lib/efi_loader/efi_variable.c
> > > @@ -282,11 +282,8 @@ efi_status_t efi_set_variable_int(const u16
> > *variable_name,
> > > }
> > > time = var->time;
> > > } else {
> > > -   if (delete || append)
> > > -   /*
> > > -* Trying to delete or to update a non-existent
> > > -* variable.
> > > -*/
> > > +   if (delete)
> > > +   /* Trying to delete a non-existent variable. */
> > > return EFI_NOT_FOUND;
> >
> > I am not sure about this tbh. The UEFI spec says
> > "When the EFI_VARIABLE_APPEND_WRITE attribute is set, then a
> > SetVariable() call with a DataSize of zero will not cause any change
> > to the variable value (the timestamp
> > associated with the variable may be updated however, even if no new
> > data value is provided;see the description
> > of the EFI_VARIABLE_AUTHENTICATION_2 descriptor below). In this case
> > the DataSize will not be zero
> > since the EFI_VARIABLE_AUTHENTICATION_2 descriptor will be populated)"
> >
> > I think this assumes the variable exists. Is there a different chapter
> > in the spec that describes the behavior?
>
> No, I could not find it.
> I'm also not sure what the UEFI spec expects.

I don't have any objections to aligning this with EDK2. But can we add
a comment about it as well?
Heinrich any preference here?

[...]

> > non-existent variable returns wrong code\n");
> > > +   efi_st_error("Variable was not deleted\n");
> > > return EFI_ST_FAILURE;
> >
> > This used to fail as well [0]. Does it work now?
>
> Yes. With this patch applied, both U-Boot file storage and StMM
> pass the efi selftest.

Yes, that's obviously a hack. The reason we didn't bother fixing it
back then is because stmm is not running in our CI, but I should have
added a comment on that instead of having it on email history...

Thanks
/Ilias
>
> Thanks,
> Masahisa Kojima
>
> >
> > > }
> > > /* Enumerate variables */
> > > --
> > > 2.34.1
> > >
> >
> > [0]
> > https://lore.kernel.org/u-boot/CAC_iWjL2G2mvQb6WNGLTxr+xj64xrYuOKr8G
> > 3-3z8lv7yx5...@mail.gmail.com/
> >
> > Regards
> > /Ilias

[PATCH v4 7/7] arm: remove redundant section alignments

[Ilias Apalodimas]

Previous patches cleaning up linker symbols, also merged any explicit
. = ALIGN(x); into section definitions -- e.g
.bss ALIGN(x) : instead of

. = ALIGN(x);
. bss : {...}

However, if the output address is not specified then one will be chosen
for the section. This address will be adjusted to fit the alignment
requirement of the output section following the strictest alignment of
any input section contained within the output section. So let's get rid
of the redundant ALIGN directives when they are not needed.

While at add comments for the alignment of __bss_start/end since our
C runtime setup assembly assumes that __bss_start - __bss_end will be
a multiple of 4/8 for armv7 and armv8 respectively.

It's worth noting that the alignment is preserved on .rel.dyn for
mach-zynq which was explicitly aligning that section on an 8b
boundary instead of 4b one.

Reviewed-by: Richard Henderson 
Signed-off-by: Ilias Apalodimas 
---
 arch/arm/cpu/armv8/u-boot.lds | 9 ++---
 arch/arm/cpu/u-boot.lds   | 8 ++--
 arch/arm/mach-zynq/u-boot.lds | 4 ++--
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 147a6e8028d5..857f44412e07 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -115,7 +115,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
 
-   .efi_runtime_rel ALIGN(8) : {
+   .efi_runtime_rel : {
 __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
@@ -125,7 +125,7 @@ SECTIONS
. = ALIGN(8);
__image_copy_end = .;
 
-   .rela.dyn ALIGN(8) : {
+   .rela.dyn : {
__rel_dyn_start = .;
*(.rela*)
__rel_dyn_end = .;
@@ -133,7 +133,10 @@ SECTIONS
 
_end = .;
 
-   .bss ALIGN(8): {
+   /*
+* arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0
+*/
+   .bss ALIGN(8) : {
__bss_start = .;
*(.bss*)
. = ALIGN(8);
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 798858e3ed6e..707b19795f08 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -43,7 +43,7 @@ SECTIONS
}
 
/* This needs to come before *(.text*) */
-   .efi_runtime ALIGN(4) : {
+   .efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
@@ -146,7 +146,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
 
-   .efi_runtime_rel ALIGN(4) : {
+   .efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
@@ -156,6 +156,10 @@ SECTIONS
. = ALIGN(4);
__image_copy_end = .;
 
+   /*
+* if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start
+* needs to be a multiple of 4 and we overlay .bss with .rel.dyn
+*/
.rel.dyn ALIGN(4) : {
__rel_dyn_start = .;
*(.rel*)
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index f6c99a8ce218..3e0c96c50556 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -22,7 +22,7 @@ SECTIONS
}
 
/* This needs to come before *(.text*) */
-   .efi_runtime ALIGN(4) : {
+   .efi_runtime : {
__efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
@@ -52,7 +52,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
 
-   .efi_runtime_rel ALIGN(4) : {
+   .efi_runtime_rel : {
__efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
-- 
2.37.2

[PATCH v4 6/7] arm: move image_copy_start/end to linker symbols

[Ilias Apalodimas]

image_copy_start/end are defined as c variables in order to force the compiler
emit relative references. However, defining those within a section definition
will do the same thing since [0].

So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and define them as a symbols within
a section.

[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for 
shared object")

Suggested-by: Sam Edwards 
Reviewed-by: Richard Henderson 
Tested-by: Sam Edwards  # Binary output identical
Signed-off-by: Ilias Apalodimas 
---
 arch/arm/cpu/armv8/u-boot-spl.lds   | 8 +++-
 arch/arm/cpu/armv8/u-boot.lds   | 8 ++--
 arch/arm/cpu/u-boot-spl.lds | 2 +-
 arch/arm/cpu/u-boot.lds | 8 ++--
 arch/arm/lib/sections.c | 2 --
 arch/arm/mach-aspeed/ast2600/u-boot-spl.lds | 2 +-
 arch/arm/mach-rockchip/u-boot-tpl-v8.lds| 8 +++-
 arch/arm/mach-zynq/u-boot-spl.lds   | 2 +-
 arch/arm/mach-zynq/u-boot.lds   | 7 ++-
 9 files changed, 15 insertions(+), 32 deletions(-)

diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds 
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 8998c4985eac..ef8af67e11c3 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -21,9 +21,9 @@ OUTPUT_ARCH(aarch64)
 ENTRY(_start)
 SECTIONS
 {
+   __image_copy_start = ADDR(.text);
.text : {
. = ALIGN(8);
-   __image_copy_start = .;
CPUDIR/start.o (.text*)
*(.text*)
} >.sram
@@ -51,10 +51,8 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
} >.sram
 
-   .image_copy_end : {
-   . = ALIGN(8);
-   *(.__image_copy_end)
-   } >.sram
+   . = ALIGN(8);
+   __image_copy_end = .;
 
.end : {
. = ALIGN(8);
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 5ba54dcedf24..147a6e8028d5 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -21,9 +21,9 @@ SECTIONS
. = 0x;
 
. = ALIGN(8);
+   __image_copy_start = ADDR(.text);
.text :
{
-   *(.__image_copy_start)
CPUDIR/start.o (.text*)
}
 
@@ -123,11 +123,7 @@ SECTIONS
}
 
. = ALIGN(8);
-
-   .image_copy_end :
-   {
-   *(.__image_copy_end)
-   }
+   __image_copy_end = .;
 
.rela.dyn ALIGN(8) : {
__rel_dyn_start = .;
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index fb2189d50dea..9ed62395a9c5 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -14,9 +14,9 @@ SECTIONS
. = 0x;
 
. = ALIGN(4);
+   __image_copy_start = ADDR(.text);
.text :
{
-   __image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 6813d8aeb838..798858e3ed6e 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -35,9 +35,9 @@ SECTIONS
. = 0x;
 
. = ALIGN(4);
+   __image_copy_start = ADDR(.text);
.text :
{
-   *(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
}
@@ -154,11 +154,7 @@ SECTIONS
}
 
. = ALIGN(4);
-
-   .image_copy_end :
-   {
-   *(.__image_copy_end)
-   }
+   __image_copy_end = .;
 
.rel.dyn ALIGN(4) : {
__rel_dyn_start = .;
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index a4d4202e99f5..db5463b2bbbc 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -19,8 +19,6 @@
  * aliasing warnings.
  */
 
-char __image_copy_start[0] __section(".__image_copy_start");
-char __image_copy_end[0] __section(".__image_copy_end");
 char __secure_start[0] __section(".__secure_start");
 char __secure_end[0] __section(".__secure_end");
 char __secure_stack_start[0] __section(".__secure_stack_start");
diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds 
b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
index 37f0ccd92201..ada6570d9712 100644
--- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
+++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds
@@ -22,9 +22,9 @@ SECTIONS
. = 0x;
 
. = ALIGN(4);
+   __image_copy_start = ADDR(.text);
.text :
{
-   __image_copy_start = .;
*(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds 
b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
index 712c485d4d0b..ad32654085b3 100644
--- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
@@ -22,9 +22,9 @@ 

[PATCH v4 5/7] arm: fix __efi_runtime_start/end definitions

[Ilias Apalodimas]

__efi_runtime_start/end are defined as c variables for arm7 only in
order to force the compiler emit relative references. However, defining
those within a section definition will do the same thing since [0].
On top of that the v8 linker scripts define it as a symbol.

So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and define them as a symbols within
the correct section.

[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for 
shared object")

Suggested-by: Sam Edwards 
Reviewed-by: Sam Edwards 
Reviewed-by: Richard Henderson 
Tested-by: Sam Edwards  # Binary output identical
Signed-off-by: Ilias Apalodimas 
---
 arch/arm/cpu/u-boot.lds| 12 +++-
 arch/arm/lib/sections.c|  2 --
 arch/arm/mach-zynq/u-boot.lds  | 12 +++-
 include/asm-generic/sections.h |  1 +
 4 files changed, 7 insertions(+), 20 deletions(-)

diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 0682d34207fa..6813d8aeb838 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -43,18 +43,12 @@ SECTIONS
}
 
/* This needs to come before *(.text*) */
-   .__efi_runtime_start : {
-   *(.__efi_runtime_start)
-   }
-
-   .efi_runtime : {
+   .efi_runtime ALIGN(4) : {
+   __efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
-   }
-
-   .__efi_runtime_stop : {
-   *(.__efi_runtime_stop)
+   __efi_runtime_stop = .;
}
 
.text_rest :
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 1ee3dd3667ba..a4d4202e99f5 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -25,6 +25,4 @@ char __secure_start[0] __section(".__secure_start");
 char __secure_end[0] __section(".__secure_end");
 char __secure_stack_start[0] __section(".__secure_stack_start");
 char __secure_stack_end[0] __section(".__secure_stack_end");
-char __efi_runtime_start[0] __section(".__efi_runtime_start");
-char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
 char _end[0] __section(".__end");
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 3b1f0d349356..9eac7de0dcbd 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -22,18 +22,12 @@ SECTIONS
}
 
/* This needs to come before *(.text*) */
-   .__efi_runtime_start : {
-   *(.__efi_runtime_start)
-   }
-
-   .efi_runtime : {
+   .efi_runtime ALIGN(4) : {
+   __efi_runtime_start = .;
*(.text.efi_runtime*)
*(.rodata.efi_runtime*)
*(.data.efi_runtime*)
-   }
-
-   .__efi_runtime_stop : {
-   *(.__efi_runtime_stop)
+   __efi_runtime_stop = .;
}
 
.text_rest :
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 60949200dd93..b6bca53db10d 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -35,6 +35,7 @@ extern char __priv_data_start[], __priv_data_end[];
 extern char __ctors_start[], __ctors_end[];
 
 extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
+extern char __efi_runtime_start[], __efi_runtime_stop[];
 
 /* function descriptor handling (if any).  Override
  * in asm/sections.h */
-- 
2.37.2

[PATCH v4 4/7] arm: clean up v7 and v8 linker scripts for __rel_dyn_start/end

[Ilias Apalodimas]

commit 47bd65ef057f ("arm: make __rel_dyn_{start, end} compiler-generated")
were moving the __rel_dyn_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
relocations for position independent code and linker bugs back then
prevented us from doing so [0].

However, the linker documentation pages states that symbols that are
defined within a section definition will create a relocatable
type with the value being a fixed offset from the base of a section [1].

[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for 
shared object")
[1] https://sourceware.org/binutils/docs/ld/Expression-Section.html

Suggested-by: Sam Edwards 
Reviewed-by: Sam Edwards 
Reviewed-by: Richard Henderson 
Tested-by: Sam Edwards  # Binary output identical
Signed-off-by: Ilias Apalodimas 
---
 arch/arm/cpu/armv8/u-boot.lds | 16 +++-
 arch/arm/cpu/u-boot.lds   | 14 +++---
 arch/arm/lib/sections.c   |  2 --
 arch/arm/mach-zynq/u-boot.lds | 14 +++---
 4 files changed, 9 insertions(+), 37 deletions(-)

diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 8561e1b3142e..5ba54dcedf24 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -129,20 +129,10 @@ SECTIONS
*(.__image_copy_end)
}
 
-   . = ALIGN(8);
-
-   .rel_dyn_start :
-   {
-   *(.__rel_dyn_start)
-   }
-
-   .rela.dyn : {
+   .rela.dyn ALIGN(8) : {
+   __rel_dyn_start = .;
*(.rela*)
-   }
-
-   .rel_dyn_end :
-   {
-   *(.__rel_dyn_end)
+   __rel_dyn_end = .;
}
 
_end = .;
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index f19f2812ee91..0682d34207fa 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -166,18 +166,10 @@ SECTIONS
*(.__image_copy_end)
}
 
-   .rel_dyn_start :
-   {
-   *(.__rel_dyn_start)
-   }
-
-   .rel.dyn : {
+   .rel.dyn ALIGN(4) : {
+   __rel_dyn_start = .;
*(.rel*)
-   }
-
-   .rel_dyn_end :
-   {
-   *(.__rel_dyn_end)
+   __rel_dyn_end = .;
}
 
.end :
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index ddfde52163fc..1ee3dd3667ba 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -21,8 +21,6 @@
 
 char __image_copy_start[0] __section(".__image_copy_start");
 char __image_copy_end[0] __section(".__image_copy_end");
-char __rel_dyn_start[0] __section(".__rel_dyn_start");
-char __rel_dyn_end[0] __section(".__rel_dyn_end");
 char __secure_start[0] __section(".__secure_start");
 char __secure_end[0] __section(".__secure_end");
 char __secure_stack_start[0] __section(".__secure_stack_start");
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index bb0e0ceb32ec..3b1f0d349356 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -71,18 +71,10 @@ SECTIONS
*(.__image_copy_end)
}
 
-   .rel_dyn_start :
-   {
-   *(.__rel_dyn_start)
-   }
-
-   .rel.dyn : {
+   .rel.dyn ALIGN(8) : {
+   __rel_dyn_start = .;
*(.rel*)
-   }
-
-   .rel_dyn_end :
-   {
-   *(.__rel_dyn_end)
+   __rel_dyn_end = .;
}
 
.end :
-- 
2.37.2

[PATCH v4 3/7] arm: fix __efi_runtime_rel_start/end definitions

[Ilias Apalodimas]

__efi_runtime_rel_start/end are defined as c variables for arm7 only in
order to force the compiler emit relative references. However, defining
those within a section definition will do the same thing since [0].
On top of that the v8 linker scripts define it as a symbol.

So let's remove the special sections from the linker scripts, the
variable definitions from sections.c and define them as a symbols within
the correct section.

[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for 
shared object")

Suggested-by: Sam Edwards 
Reviewed-by: Sam Edwards 
Tested-by: Sam Edwards  # Binary output identical
Reviewed-by: Richard Henderson 
Signed-off-by: Ilias Apalodimas 
---
 arch/arm/cpu/armv8/u-boot.lds  |  4 +---
 arch/arm/cpu/u-boot.lds| 16 +++-
 arch/arm/lib/sections.c|  2 --
 arch/arm/mach-zynq/u-boot.lds  | 16 +++-
 include/asm-generic/sections.h |  2 ++
 lib/efi_loader/efi_runtime.c   |  1 +
 6 files changed, 10 insertions(+), 31 deletions(-)

diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index 9640cc7a04b8..8561e1b3142e 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -115,9 +115,7 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
 
-   . = ALIGN(8);
-
-   .efi_runtime_rel : {
+   .efi_runtime_rel ALIGN(8) : {
 __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 0dfe5f633b16..f19f2812ee91 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -152,21 +152,11 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
 
-   . = ALIGN(4);
-
-   .efi_runtime_rel_start :
-   {
-   *(.__efi_runtime_rel_start)
-   }
-
-   .efi_runtime_rel : {
+   .efi_runtime_rel ALIGN(4) : {
+   __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
-   }
-
-   .efi_runtime_rel_stop :
-   {
-   *(.__efi_runtime_rel_stop)
+   __efi_runtime_rel_stop = .;
}
 
. = ALIGN(4);
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 8e8bd5797e16..ddfde52163fc 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -29,6 +29,4 @@ char __secure_stack_start[0] 
__section(".__secure_stack_start");
 char __secure_stack_end[0] __section(".__secure_stack_end");
 char __efi_runtime_start[0] __section(".__efi_runtime_start");
 char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
-char __efi_runtime_rel_start[0] __section(".__efi_runtime_rel_start");
-char __efi_runtime_rel_stop[0] __section(".__efi_runtime_rel_stop");
 char _end[0] __section(".__end");
diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 3c5008b57392..bb0e0ceb32ec 100644
--- a/arch/arm/mach-zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
@@ -58,21 +58,11 @@ SECTIONS
KEEP(*(SORT(__u_boot_list*)));
}
 
-   . = ALIGN(4);
-
-   .efi_runtime_rel_start :
-   {
-   *(.__efi_runtime_rel_start)
-   }
-
-   .efi_runtime_rel : {
+   .efi_runtime_rel ALIGN(4) : {
+   __efi_runtime_rel_start = .;
*(.rel*.efi_runtime)
*(.rel*.efi_runtime.*)
-   }
-
-   .efi_runtime_rel_stop :
-   {
-   *(.__efi_runtime_rel_stop)
+   __efi_runtime_rel_stop = .;
}
 
. = ALIGN(8);
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 1e1657a01673..60949200dd93 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -34,6 +34,8 @@ extern char __priv_data_start[], __priv_data_end[];
 /* Start and end of .ctors section - used for constructor calls. */
 extern char __ctors_start[], __ctors_end[];
 
+extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
+
 /* function descriptor handling (if any).  Override
  * in asm/sections.h */
 #ifndef dereference_function_descriptor
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 18da6892e796..9185f1894c47 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 /* For manual relocation support */
 DECLARE_GLOBAL_DATA_PTR;
-- 
2.37.2

[PATCH v4 2/7] arm: clean up v7 and v8 linker scripts for bss_start/end

[Ilias Apalodimas]

commit 3ebd1cbc49f0 ("arm: make __bss_start and __bss_end__ compiler-generated")
and
commit f84a7b8f54db ("ARM: Fix __bss_start and __bss_end in linker scripts")
were moving the bss_start/end on c generated variables that were
injected in their own sections. The reason was that we needed relative
relocations for position independent code and linker bugs back then
prevented us from doing so [0].

However, the linker documentation pages states that symbols that are
defined within a section definition will create a relocatable type with
the value being a fixed offset from the base of a section [1].
So let's start cleaning this up starting with the bss_start and bss_end
variables. Convert them into symbols within the .bss section definition.

[0] binutils commit 6b3b0ab89663 ("Make linker assigned symbol dynamic only for 
shared object")
[1] https://sourceware.org/binutils/docs/ld/Expression-Section.html

Tested-by: Caleb Connolly  # Qualcomm sdm845
Tested-by: Sam Edwards  # Binary output identical
Signed-off-by: Ilias Apalodimas 
---
 arch/arm/cpu/armv8/u-boot-spl.lds| 18 +++---
 arch/arm/cpu/armv8/u-boot.lds| 16 
 arch/arm/cpu/u-boot.lds  | 22 +++---
 arch/arm/lib/sections.c  |  2 --
 arch/arm/mach-rockchip/u-boot-tpl-v8.lds | 15 ---
 arch/arm/mach-zynq/u-boot.lds| 22 +++---
 6 files changed, 29 insertions(+), 66 deletions(-)

diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds 
b/arch/arm/cpu/armv8/u-boot-spl.lds
index 7cb9d731246d..8998c4985eac 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -63,18 +63,11 @@ SECTIONS
 
_image_binary_end = .;
 
-   .bss_start (NOLOAD) : {
-   . = ALIGN(8);
-   KEEP(*(.__bss_start));
-   } >.sdram
-
-   .bss (NOLOAD) : {
+   .bss : {
+   __bss_start = .;
*(.bss*)
-. = ALIGN(8);
-   } >.sdram
-
-   .bss_end (NOLOAD) : {
-   KEEP(*(.__bss_end));
+   . = ALIGN(8);
+   __bss_end = .;
} >.sdram
 
/DISCARD/ : { *(.rela*) }
@@ -89,3 +82,6 @@ SECTIONS
 #include "linux-kernel-image-header-vars.h"
 #endif
 }
+
+ASSERT(ADDR(.bss) % 8 == 0, \
+   ".bss must be 8-byte aligned");
diff --git a/arch/arm/cpu/armv8/u-boot.lds b/arch/arm/cpu/armv8/u-boot.lds
index fb6a30c922f7..9640cc7a04b8 100644
--- a/arch/arm/cpu/armv8/u-boot.lds
+++ b/arch/arm/cpu/armv8/u-boot.lds
@@ -149,19 +149,11 @@ SECTIONS
 
_end = .;
 
-   . = ALIGN(8);
-
-   .bss_start : {
-   KEEP(*(.__bss_start));
-   }
-
-   .bss : {
+   .bss ALIGN(8): {
+   __bss_start = .;
*(.bss*)
-. = ALIGN(8);
-   }
-
-   .bss_end : {
-   KEEP(*(.__bss_end));
+   . = ALIGN(8);
+   __bss_end = .;
}
 
/DISCARD/ : { *(.dynsym) }
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 7724c9332c3b..0dfe5f633b16 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -207,23 +207,15 @@ SECTIONS
}
 
 /*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
+ * These sections occupy the same memory, but their lifetimes do
+ * not overlap: U-Boot initializes .bss only after applying dynamic
+ * relocations and therefore after it doesn't need .rel.dyn any more.
  */
-
-   .bss_start __rel_dyn_start (OVERLAY) : {
-   KEEP(*(.__bss_start));
-   __bss_base = .;
-   }
-
-   .bss __bss_base (OVERLAY) : {
+   .bss ADDR(.rel.dyn) (OVERLAY): {
+   __bss_start = .;
*(.bss*)
-. = ALIGN(4);
-__bss_limit = .;
-   }
-
-   .bss_end __bss_limit (OVERLAY) : {
-   KEEP(*(.__bss_end));
+   . = ALIGN(4);
+   __bss_end = .;
}
 
.dynsym _image_binary_end : { *(.dynsym) }
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 857879711c6a..8e8bd5797e16 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -19,8 +19,6 @@
  * aliasing warnings.
  */
 
-char __bss_start[0] __section(".__bss_start");
-char __bss_end[0] __section(".__bss_end");
 char __image_copy_start[0] __section(".__image_copy_start");
 char __image_copy_end[0] __section(".__image_copy_end");
 char __rel_dyn_start[0] __section(".__rel_dyn_start");
diff --git a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds 
b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
index 74618eba591b..712c485d4d0b 100644
--- a/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
+++ b/arch/arm/mach-rockchip/u-boot-tpl-v8.lds
@@ -56,18 +56,11 @@ SECTIONS
 
_image_binary_end = .;
 
-   .bss_start (NOLOAD) : {
-   . = ALIGN(8);
-   

[PATCH v4 1/7] arm: baltos: remove custom linker script

[Ilias Apalodimas]

commit 3d74a0977f514 ("ti: am335x: Remove unused linker script") removed
the linker script for the TI variant. This linker script doesn't seem to
do anything special and on top of that, has no definitions for the EFI
runtime sections.

So let's get rid of it and use the generic linker script which defines
those correctly

Signed-off-by: Ilias Apalodimas 
Reviewed-by: Tom Rini 
---
 board/vscom/baltos/u-boot.lds | 128 --
 1 file changed, 128 deletions(-)
 delete mode 100644 board/vscom/baltos/u-boot.lds

diff --git a/board/vscom/baltos/u-boot.lds b/board/vscom/baltos/u-boot.lds
deleted file mode 100644
index cb2ee6769753..
--- a/board/vscom/baltos/u-boot.lds
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, 
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-   . = 0x;
-
-   . = ALIGN(4);
-   .text :
-   {
-   *(.__image_copy_start)
-   *(.vectors)
-   CPUDIR/start.o (.text*)
-   board/vscom/baltos/built-in.o (.text*)
-   *(.text*)
-   }
-
-   . = ALIGN(4);
-   .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
-
-   . = ALIGN(4);
-   .data : {
-   *(.data*)
-   }
-
-   . = ALIGN(4);
-
-   . = .;
-
-   . = ALIGN(4);
-   __u_boot_list : {
-   KEEP(*(SORT(__u_boot_list*)));
-   }
-
-   . = ALIGN(4);
-
-   .image_copy_end :
-   {
-   *(.__image_copy_end)
-   }
-
-   .rel_dyn_start :
-   {
-   *(.__rel_dyn_start)
-   }
-
-   .rel.dyn : {
-   *(.rel*)
-   }
-
-   .rel_dyn_end :
-   {
-   *(.__rel_dyn_end)
-   }
-
-   .hash : { *(.hash*) }
-
-   .end :
-   {
-   *(.__end)
-   }
-
-   _image_binary_end = .;
-
-   /*
-* Deprecated: this MMU section is used by pxa at present but
-* should not be used by new boards/CPUs.
-*/
-   . = ALIGN(4096);
-   .mmutable : {
-   *(.mmutable)
-   }
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-   .bss_start __rel_dyn_start (OVERLAY) : {
-   KEEP(*(.__bss_start));
-   __bss_base = .;
-   }
-
-   .bss __bss_base (OVERLAY) : {
-   *(.bss*)
-. = ALIGN(4);
-__bss_limit = .;
-   }
-
-   .bss_end __bss_limit (OVERLAY) : {
-   KEEP(*(.__bss_end));
-   }
-
-   .dynsym _image_binary_end : { *(.dynsym) }
-   .dynbss : { *(.dynbss) }
-   .dynstr : { *(.dynstr*) }
-   .dynamic : { *(.dynamic*) }
-   .gnu.hash : { *(.gnu.hash) }
-   .plt : { *(.plt*) }
-   .interp : { *(.interp*) }
-   .gnu : { *(.gnu*) }
-   .ARM.exidx : { *(.ARM.exidx*) }
-}
-- 
2.37.2

[PATCH v4 0/7] Clean up arm linker scripts

[Ilias Apalodimas]

The arm linker scripts had a mix of symbols and C defined variables in an
effort to emit relative references instead of absolute ones e.g [0]. A
linker bug prevented us from doing so [1] -- fixed since 2016.
This has led to confusion over the years, ending up with mixed section
definitions. Some sections are defined with overlays and different
definitions between v7 and v8 architectures.
For example __efi_runtime_rel_start/end is defined as a linker symbol for
armv8 and a C variable in armv7.

Linker scripts nowadays can emit relative references, as long as the symbol
definition is contained within the section definition. So let's switch most
of the C defined variables and clean up the arm sections.c file.
There's still a few symbols remaining -- __secure_start/end,
__secure_stack_start/end and __end which can be cleaned up
in a followup series.

For both QEMU v7/v8 bloat-o-meter shows now size difference
$~ ./scripts/bloat-o-meter u-boot u-boot.new
add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0)
Function old new   delta
Total: Before=798861, After=798861, chg +0.00%

The symbols seem largely unchanged apart from a difference in .bss
as well as the emited sections and object types of the affected variables.

On the output below the first value is from -next and the second comes from
-next + this patchset. The .bss_start/end sections have disappeared from
the newer binaries.

# For example on QEMU v8:
efi_runtime_start
  7945: 0178 0 OBJECT  GLOBAL DEFAULT2 __efi_runtime_start
  7942: 0178 0 NOTYPE  GLOBAL DEFAULT2 __efi_runtime_start
efi_runtime_stop
  9050: 0d38 0 OBJECT  GLOBAL DEFAULT2 __efi_runtime_stop
  9047: 0d38 0 NOTYPE  GLOBAL DEFAULT2 __efi_runtime_stop
__efi_runtime_rel_start
  7172: 000dc2f0 0 OBJECT  GLOBAL DEFAULT   10 
__efi_runtime_rel_start
  7169: 000dc2f0 0 NOTYPE  GLOBAL DEFAULT   10 
__efi_runtime_rel_start
__efi_runtime_rel_stop
  7954: 000dc4a0 0 OBJECT  GLOBAL DEFAULT   10 
__efi_runtime_rel_stop
  7951: 000dc4a0 0 NOTYPE  GLOBAL DEFAULT   10 
__efi_runtime_rel_stop
__rel_dyn_start
  7030: 000dc4a0 0 OBJECT  GLOBAL DEFAULT   11 __rel_dyn_start
  7027: 000dc4a0 0 NOTYPE  GLOBAL DEFAULT   11 __rel_dyn_start
__rel_dyn_end
  8959: 00102b10 0 OBJECT  GLOBAL DEFAULT   12 __rel_dyn_end
  8956: 00102b10 0 NOTYPE  GLOBAL DEFAULT   11 __rel_dyn_end
image_copy_start
  9051:  0 OBJECT  GLOBAL DEFAULT1 __image_copy_start
  9048:  0 NOTYPE  GLOBAL DEFAULT1 __image_copy_start
image_copy_end
  7467: 000dc4a0 0 OBJECT  GLOBAL DEFAULT   11 __image_copy_end
  7464: 000dc4a0 0 NOTYPE  GLOBAL DEFAULT   11 __image_copy_end
bss_start
12: 00102b10 0 SECTION LOCAL  DEFAULT   12 .bss_start
  8087: 0018 0 NOTYPE  GLOBAL DEFAULT1 _bss_start_ofs
  8375: 00102b10 0 OBJECT  GLOBAL DEFAULT   12 __bss_start
  8084: 0018 0 NOTYPE  GLOBAL DEFAULT1 _bss_start_ofs
  8372: 00102b10 0 NOTYPE  GLOBAL DEFAULT   12 __bss_start
bss_end
14: 0010bc30 0 SECTION LOCAL  DEFAULT   14 .bss_end
  7683: 0010bc30 0 OBJECT  GLOBAL DEFAULT   14 __bss_end
  8479: 0020 0 NOTYPE  GLOBAL DEFAULT1 _bss_end_ofs
  7680: 0010bbb0 0 NOTYPE  GLOBAL DEFAULT   12 __bss_end
  8476: 0020 0 NOTYPE  GLOBAL DEFAULT1 _bss_end_ofs

# For QEMU v7:
efi_runtime_start
 10703: 03bc 0 OBJECT  GLOBAL DEFAULT2 __efi_runtime_start
 10699: 03c0 0 NOTYPE  GLOBAL DEFAULT2 __efi_runtime_start
efi_runtime_stop
 11796: 12ec 0 OBJECT  GLOBAL DEFAULT2 __efi_runtime_stop
 11792: 12ec 0 NOTYPE  GLOBAL DEFAULT2 __efi_runtime_stop
__efi_runtime_rel_start
  9937: 000c40dc 0 OBJECT  GLOBAL DEFAULT8 __efi_runtime_rel_start
  9935: 000c40dc 0 NOTYPE  GLOBAL DEFAULT9 __efi_runtime_rel_start
__efi_runtime_rel_stop
 10712: 000c41dc 0 OBJECT  GLOBAL DEFAULT   10 __efi_runtime_rel_stop
 10708: 000c41dc 0 NOTYPE  GLOBAL DEFAULT9 __efi_runtime_rel_stop
__rel_dyn_start
  9791: 000c41dc 0 OBJECT  GLOBAL DEFAULT   10 __rel_dyn_start
  9789: 000c41dc 0 NOTYPE  GLOBAL DEFAULT   10 __rel_dyn_start
__rel_dyn_end
 11708: 000da5f4 0 OBJECT  GLOBAL DEFAULT   10 __rel_dyn_end
 11704: 000da5f4 0 NOTYPE  GLOBAL DEFAULT   10 __rel_dyn_end
image_copy_start
   448: 177c 0 NOTYPE  LOCAL  DEFAULT3 _image_copy_start_ofs
 11797:  0 OBJECT  GLOBAL DEFAULT1 __image_copy_start
   445: 177c 0 NOTYPE  LOCAL  DEFAULT3 _image_copy_start_ofs
 11793:  0 NOTYPE  GLOBAL DEFAULT1 __image_copy_start
image_copy_end
   450: 1780 0 NOTYPE  LOCAL  DEFAULT3 _image_copy_end_ofs
 10225: 000c41dc 0 OBJECT  GLOBAL DEFAULT