[PATCH] efi_loader: address coverity report 492766 for dead code
The check of the return code is already done a few lines above. Although it doesn't cause any functional issues, remove the superfluous checks Addresses-Coverity-ID: 492766 Control flow issues (DEADCODE) Signed-off-by: Ilias Apalodimas --- lib/efi_loader/efi_var_mem.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index 940ab6638823..139e16aad7c6 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -232,8 +232,6 @@ efi_status_t efi_var_mem_init(void) efi_var_buf->length = (uintptr_t)efi_var_buf->var - (uintptr_t)efi_var_buf; - if (ret != EFI_SUCCESS) - return ret; ret = efi_create_event(EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, TPL_CALLBACK, efi_var_mem_notify_virtual_address_map, NULL, NULL, ); -- 2.43.0
Re: RISC-V u-boot unable to boot QEMU using '-cpu max'
On Mon, Apr 22, 2024 at 04:43:59PM -0300, Daniel Henrique Barboza wrote:
> [EXTERNAL MAIL]
>
> Hi,
>
> In QEMU we have a 'max' type CPU that implements (almost) all extensions that
> QEMU
> is able to emulate. Recently, in QEMU commit 249e0905d05, we bumped the
> extensions
> for this CPU.
>
> And after this commit this CPU is now unable to boot a guest using upstream
> u-boot. Here's the error being thrown:
>
> qemu-system-riscv64 \
> -machine virt -nographic -m 8G -smp 8 \
> -cpu max -kernel uboot.elf (...)
> (...)
>
> initcall sequence 8027c3e8 failed at call 8021259e (err=-28)
> ### ERROR ### Please RESET the board ###
>
>
> I can get the guest to boot if I disable the following extensions from the
> 'max' CPU:
>
> -cpu max,zfbfmin=false,zvfbfmin=false,zvfbfwma=false
>
> Due to QEMU extension dependencies I'm not able to disable these
> individually. What I can
> say is that u-boot isn't playing ball to at least one of them.
>
> Is this an u-boot bug? Up to this point I was assuming that u-boot would
> silently ignore
> hart extensions that it doesn't support.
Hi Daniel,
Which u-boot version are you using?
I think this issue is fixed by the following patch set sent by Conor.
f39b1b77d8 riscv: support extension probing using riscv, isa-extensions
b90edde701 riscv: don't read riscv, isa in the riscv cpu's get_desc()
I've tested and can reproduce the issue you mentioned if these two patches are
reverted.
Could you try with the lastest u-boot master branch again?
For reference, my testing commands are as follows:
1. cd ${u-boot} && make qemu-riscv64_defconfig && make -j`nproc`
2. ./${qemu}/build/qemu-system-riscv64 -nographic -machine virt -cpu max -bios
u-boot.bin -m 8G -smp 8
- u-boot branch (commit): master (38ea74d6d5c0 "Prepare v2024.07-rc1")
- qemu branch (commit): master (62dbe54c24db "Update version for v9.0.0-rc4
release")
Best regards,
Leo
>
>
> Thanks,
>
>
> Daniel
[PATCH] mmc: Change the frequency to MMC_HS_52 when selecting hs400
Per JESD84-B51 P47, host need to change frequency to <=52MHz
after setting HS_TIMING to 0x1, and host need to set the
8-bit DDR buswidth. Currently setting the frequency to 26MHz
and trying to switch 8-bit DDR buswidth resulting timeouts.
mmc dev 1 0
Select HS400 failed -110
switch to partitions #0, OK
mmc1(part 0) is current device
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mmc/mmc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 7b068c71ff..a2ed99aefe 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -962,8 +962,8 @@ static int mmc_set_card_speed(struct mmc *mmc, enum
bus_mode mode,
* Extended CSD. Reconfigure the controller to run at HS mode.
*/
if (hsdowngrade) {
- mmc_select_mode(mmc, MMC_HS);
- mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
+ mmc_select_mode(mmc, MMC_HS_52);
+ mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS_52), false);
}
#endif
@@ -2043,7 +2043,7 @@ static int mmc_select_hs400(struct mmc *mmc)
}
/* Set back to HS */
- mmc_set_card_speed(mmc, MMC_HS, true);
+ mmc_set_card_speed(mmc, MMC_HS_52, true);
err = mmc_hs400_prepare_ddr(mmc);
if (err)
--
2.17.1
Re: BTRFS use-after-free bug at free_extent_buffer_internal
On Monday 22 April 2024 5:15:50 PM AEST Qu Wenruo wrote:
>
> 在 2024/4/22 16:07, Sachi King 写道:
> > Hi,
> >
> > I've hit a bug with u-boot on my BTRFS filesystem, and I'm fairly certain
> > it's a bug and not a corruption issue.
> >
> > A bit of history on the filesystem. It is a fairly new filesystem as it was
> > being used to give me access to test a wayland application on a
> > Raspberry Pi. The filesystem was about 3 days old when I hit the bug, and
> > I'm fairly certain it never had an unclean shutdown. I have checked the
> > filesystem with "btrfs check" which has found no errors. The filesystem
> > mounts on Linux and is functional.
> >
> >> # btrfs check --check-data-csum /dev/sda2
> >> Opening filesystem to check...
> >> Checking filesystem on /dev/sda2
> >> UUID: 18db6211-ac36-42c1-a22f-5e15e1486e0d
> >> [1/7] checking root items
> >> [2/7] checking extents
> >> [3/7] checking free space tree
> >> [4/7] checking fs roots
> >> [5/7] checking csums against data
> >> [6/7] checking root refs
> >> [7/7] checking quota groups skipped (not enabled on this FS)
> >> found 5070573568 bytes used, no error found
> >> total csum bytes: 4451620
> >> total tree bytes: 370458624
> >> total fs tree bytes: 353124352
> >> total extent tree bytes: 10010624
> >> btree space waste bytes: 62303284
> >> file data blocks allocated: 6786519040
> >> referenced 6328619008
>
> Since btrfs check reports no error, the fs must be valid.
>
> But considering how new it is, it may be related to some new features
> not properly implemented in Uboot.
>
> Is it possible to provide the whole binary dump of the fs?
Sure, here's a copy of the disk image. The BTRFS is at partition 2.
http://maribel.nakato.io/u-boot-newtest.img.zstd
> >
> >
> > I've made an image of the filesystem so I could reproduce the bug in an
> > environment that doesn't require the physical SBC, and have reproduced
> > the issue using the head of the master branch with "qemu-x86_64_defconfig".
> >
> > My testing qemu was produced with the following:
> >> # make qemu-x86_64_defconfig
> >> # cat << EOF >> .config
> >> CONFIG_AUTOBOOT=y
> >> CONFIG_BOOTDELAY=1
> >> CONFIG_USE_BOOTCOMMAND=y
> >> CONFIG_BOOTSTD_DEFAULTS=y
> >> CONFIG_BOOTSTD_FULL=y
> >> CONFIG_CMD_BOOTFLOW_FULL=y
> >> CONFIG_BOOTCOMMAND="bootflow scan -lb"
> >> CONFIG_ENV_IS_NOWHERE=y
> >> CONFIG_LZ4=y
> >> CONFIG_BZIP2=y
> >> CONFIG_ZSTD=y
> >> CONFIG_FS_BTRFS=y
> >> CONFIG_CMD_BTRFS=y
> >> CONFIG_GZIP=y
> >> CONFIG_DEVICE_TREE_INCLUDES="bootstd.dtsi"
> >> EOF
> >> # make -j24
> >
> > bootstd.dtsi is placed at "arch/x86/dts/bootstd.dtsi" and contains:
> >> / {
> >> bootstd {
> >> compatible = "u-boot,boot-std";
> >> filename-prefixes = "/@boot/", "/boot/", "/";
> >> bootdev-order = "scsi";
> >> extlinux {
> >> compatible = "u-boot,extlinux";
> >> };
> >> };
> >> };
> >
> >
> > The VM was run with
> >> qemu-system-x86_64 -bios u-boot.rom -nographic -M q35 -action
> >> reboot=shutdown -drive file=/mnt/dbg/u-boot-debug.img
> >
> > The error message I recive on boot is
> >> BUG at fs/btrfs/extent-io.c:629/free_extent_buffer_internal()!
> >> BUG!
> >> resetting ...
> >
> >
> > I added a print statement to free_extent_buffer_internal that prints the
> > start address of the extent_buffer as I'm not sure what to be looking for
> > here. This print statement is before the decrement.
> >> printf("free_extent_buffer_internal: eb->start[%llx] eb->refs[%i]\n",
> >> eb->start, eb->refs);
> >
> > The last message before the crash reported eb->start to be "0", with 0 refs.
> >> free_extent_buffer_internal: eb->start[0] eb->refs[0]
> >
> > The extent at 0 struck me as odd, so I tried commenting out the freeing, by
> > removing the call to free_extent_buffer_final, and this resulted in bootflow
> > succeeding and showing me the boot menu, which suprised me.
> > I expected to see the bug reproduce itself, with refs being zero, but
> > eb->start
> > pointing somewhere valid, but I instead got a valid address with refs at 2.
> >
> > I'm assuming that the order free_extent_buffer_internal is called is
> > deterministic, so by counting the print outputs the line that prior held
> > the extent_buffer with a 0 start was replaced with:
> >> free_extent_buffer_internal: eb->start[249c000] eb->refs[2]
> >
> > Interestingly, as can be seen in the full logs with my included print
> > messages, 249c000 is being used just before this, with a ref count of
> > 2. 249c000 does appear to reach a point where it should have been freed
> > in the past, before it gets used again as seen in both logs.
> >
> > The failing boot log:
> >> U-Boot SPL 2024.04-00949-g1dd659fd62-dirty (Apr 22 2024 - 11:32:37 +1000)
> >> Trying to boot from SPI
> >> Jumping to 64-bit U-Boot: Note many features are missing
> >>
> >>
> >> U-Boot 2024.04-00949-g1dd659fd62-dirty (Apr 22 2024 - 11:32:37 +1000)
> >>
> >> CPU:
Re: [PATCH] usb: dwc3: support USB 3.1 controllers
On 4/22/24 12:53 PM, Caleb Connolly wrote:
On 21/04/2024 22:38, Marek Vasut wrote:
On 4/11/24 6:05 PM, Caleb Connolly wrote:
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Signed-off-by: Caleb Connolly
Is there a matching Linux kernel patch , or does Linux do some other
check ?
I just took this change from the xhci-dwc3 driver tbh... But I did some
archeology and it seems the associated Linux patch would be 690fb3718a70
("usb: dwc3: Support Synopsys USB 3.1 IP").
Can you please mention it in the commit message, and send a V2 with my:
Reviewed-by: Marek Vasut
Thanks
Re: [PATCH] usb: dwc2: update reset method for host and device mode
On 4/22/24 7:31 AM, Kongyang Liu wrote:
[...]
@@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
dev_info(dev, "%s: Timeout!\n", __func__);
/* Core Soft Reset */
+ snpsid = readl(>gsnpsid);
writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
- ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
- false, 1000, false);
+ if ((snpsid & DWC2_SNPSID_VER_MASK) < (DWC2_SNPSID_DEVID_VER_420a &
DWC2_SNPSID_VER_MASK)) {
+ ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
+ false, 1000, false);
+ } else {
+ ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_GSFTRST_DONE,
+ true, 1000, false);
+ greset = readl(>grstctl);
+ greset &= ~DWC2_GRSTCTL_CSFTRST;
+ greset |= DWC2_GRSTCTL_GSFTRST_DONE;
+ writel(greset, >grstctl);
Same comments as above.
Maybe this should be pulled into dedicated function to avoid duplication?
For U-Boot, the dwc2 USB driver is split into two modules: host and gadget.
Each has its own register definitions and definitions for register bits,
which makes it difficult to extract a single function. Moreover, deciding
where to place this function is also an issue.
There is drivers/usb/common/ for such code. The register macros can
probably be unified into a single header too.
Re: [PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL
Hi Quentin,
On 2024/4/23 00:41, Quentin Schulz wrote:
From: Quentin Schulz
UART2 controller is the controller in the reference design for debug
console. The default mux is M0 in that reference design. Until now, all
boards seemed to be using UART2M0 but RK3588 Tiger for example will be
using UART2M2 instead.
This feature already been supported, please use CONFIG_DEBUG_UART_BASE and
CONFIG_ROCKCHIP_UART_MUX_SEL_M to select your output channel.
Thanks,
- Kever
Therefore, let's add support for UART2M1 and M2 as possible muxes for
the UART2 controller used as debug console. UART2M1 support was not
tested.
The default value is M0 to match the one used currently by all devices
and the reference design.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10 ++
arch/arm/mach-rockchip/rk3588/rk3588.c | 36 ++
2 files changed, 46 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index d7e4af31f24..cacdb0459c9 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -221,6 +221,16 @@ config ROCKCHIP_COMMON_STACK_ADDR
config TEXT_BASE
default 0x00a0
+config DEBUG_UART_CHANNEL
+ int "Mux channel to use for debug UART2"
+ depends on DEBUG_UART_BOARD_INIT
+ default 0
+ range 0 2
+ help
+ UART2 can use three different set of pins to route the output.
+ For using the UART for early debugging the route to use needs
+ to be declared (0, 1 or 2).
+
source board/edgeble/neural-compute-module-6/Kconfig
source board/friendlyelec/nanopc-t6-rk3588/Kconfig
source board/pine64/quartzpro64-rk3588/Kconfig
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index eb65dafe3a2..e330ad6a697 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -94,9 +94,32 @@ enum {
GPIO0B6_UART2_RX_M0 = 10,
};
+/* GPIO3B_IOMUX_SEL_L */
+enum {
+ GPIO3B1_SHIFT = 4,
+ GPIO3B1_MASK= GENMASK(7, 4),
+ GPIO3B1_UART2_TX_M2 = 10,
+
+ GPIO3B2_SHIFT = 8,
+ GPIO3B2_MASK= GENMASK(11, 8),
+ GPIO3B2_UART2_RX_M2 = 10,
+};
+
+/* GPIO4D_IOMUX_SEL_L */
+enum {
+ GPIO4D0_SHIFT = 0,
+ GPIO4D0_MASK= GENMASK(3, 0),
+ GPIO4D0_UART2_TX_M1 = 10,
+
+ GPIO4D1_SHIFT = 4,
+ GPIO4D1_MASK= GENMASK(7, 4),
+ GPIO4D1_UART2_RX_M1 = 10,
+};
+
void board_debug_uart_init(void)
{
__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void
*)BUS_IOC_BASE;
+#if (CONFIG_DEBUG_UART_CHANNEL == 0)
static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
/* Refer to BUS_IOC */
@@ -110,6 +133,19 @@ void board_debug_uart_init(void)
GPIO0B6_MASK | GPIO0B5_MASK,
GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
+#elif (CONFIG_DEBUG_UART_CHANNEL == 1)
+ /* UART2_M1 Switch iomux */
+ rk_clrsetreg(_ioc->gpio4d_iomux_sel_l,
+GPIO4D0_MASK | GPIO4D1_MASK,
+GPIO4D0_UART2_TX_M1 << GPIO4D0_UART2_TX_M1 |
+GPIO4D1_UART2_RX_M1 << GPIO4D1_SHIFT);
+#else
+ /* UART2_M2 Switch iomux */
+ rk_clrsetreg(_ioc->gpio3b_iomux_sel_l,
+GPIO3B1_MASK | GPIO3B2_MASK,
+GPIO3B1_UART2_TX_M2 << GPIO3B1_SHIFT |
+GPIO3B2_UART2_RX_M2 << GPIO3B2_SHIFT);
+#endif /* CONFIG_DEBUG_UART_CHANNEL */
}
#ifdef CONFIG_SPL_BUILD
Re: [PATCH 1/2] arm: dts: k3-j721e-binman: Add support for HSSE2.0 and HSFS1.1
Hi Andrew,
On 22-Apr-24 3:37 AM, Andrew Davis wrote:
On 4/22/24 4:40 PM, Neha Malcom Francis wrote:
J721E has SR1.1 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR2.0 and HS-FS SR1.1 so
add support for them.
Reported-by: Suman Anna
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j721e-binman.dtsi | 201 +-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi
b/arch/arm/dts/k3-j721e-binman.dtsi
index 75a6e9599b9..90e4a31329e 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated -
https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated -
https://www.ti.com/
*/
#include "k3-binman.dtsi"
@@ -129,6 +129,205 @@
};
};
+ {
+ tiboot3-j721e_sr2-hs-evm.bin {
This already seems to exist in this file, it is hidden up in the
first binman{} GP node at the top. Might just need split out from that.
Andrew
Oh thanks for catching that!
+ filename = "tiboot3-j721e_sr2-hs-evm.bin";
+ ti-secure-rom {
+ content = <_boot_spl_sr2>;
+ core = "public";
+ core-opts = <2>;
+ load = ;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_spl_sr2: u-boot-spl {
+ no-expanded;
+ };
+ };
+ sysfw_sr2 {
+ filename = "sysfw.bin_sr2";
+ ti-secure-rom {
+ content = <_fs_cert_sr2>;
+ core = "secure";
+ load = <0x4>;
+ keyfile = "custMpk.pem";
+ countersign;
+ };
+ ti_fs_cert_sr2: ti-fs-cert.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ ti-fs-firmware-j721e_sr2-hs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+ itb_sr2 {
+ filename = "sysfw-j721e_sr2-hs-evm.itb";
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_sr2";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ board_cfg_sr2: board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ pm_cfg_sr2: pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ rm_cfg_sr2: rm-cfg {
+ filename = "rm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ sec-cfg.bin {
+ description = "sec-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ sec_cfg_sr2: sec-cfg {
+ filename = "sec-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ };
+ };
+ };
+};
+
+ {
+ tiboot3-j721e_sr1_1-hs-fs-evm.bin {
+ filename = "tiboot3-j721e_sr1_1-hs-fs-evm.bin";
+ ti-secure-rom {
+ content = <_boot_spl_fs_sr1_1>;
Re: [PATCH 1/2] arm: dts: k3-j721e-binman: Add support for HSSE2.0 and HSFS1.1
On 4/22/24 4:40 PM, Neha Malcom Francis wrote:
J721E has SR1.1 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR2.0 and HS-FS SR1.1 so
add support for them.
Reported-by: Suman Anna
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j721e-binman.dtsi | 201 +-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi
b/arch/arm/dts/k3-j721e-binman.dtsi
index 75a6e9599b9..90e4a31329e 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
@@ -129,6 +129,205 @@
};
};
+ {
+ tiboot3-j721e_sr2-hs-evm.bin {
This already seems to exist in this file, it is hidden up in the
first binman{} GP node at the top. Might just need split out from that.
Andrew
+ filename = "tiboot3-j721e_sr2-hs-evm.bin";
+ ti-secure-rom {
+ content = <_boot_spl_sr2>;
+ core = "public";
+ core-opts = <2>;
+ load = ;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_spl_sr2: u-boot-spl {
+ no-expanded;
+ };
+ };
+ sysfw_sr2 {
+ filename = "sysfw.bin_sr2";
+ ti-secure-rom {
+ content = <_fs_cert_sr2>;
+ core = "secure";
+ load = <0x4>;
+ keyfile = "custMpk.pem";
+ countersign;
+ };
+ ti_fs_cert_sr2: ti-fs-cert.bin {
+ filename =
"ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ ti-fs-firmware-j721e_sr2-hs-enc.bin {
+ filename =
"ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+ itb_sr2 {
+ filename = "sysfw-j721e_sr2-hs-evm.itb";
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_sr2";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ board_cfg_sr2: board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ pm_cfg_sr2: pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+
Fwd: New Defects reported by Coverity Scan for Das U-Boot
Here's the latest report.
-- Forwarded message -
From:
Date: Mon, Apr 22, 2024 at 3:23 PM
Subject: New Defects reported by Coverity Scan for Das U-Boot
To:
Hi,
Please find the latest report on new defect(s) introduced to Das
U-Boot found with Coverity Scan.
2 new defect(s) introduced to Das U-Boot found with Coverity Scan.
7 defect(s), reported by Coverity Scan earlier, were marked fixed in
the recent build analyzed by Coverity Scan.
New defect(s) Reported-by: Coverity Scan
Showing 2 of 2 defect(s)
** CID 492766: Control flow issues (DEADCODE)
/lib/efi_loader/efi_var_mem.c: 236 in efi_var_mem_init()
*** CID 492766: Control flow issues (DEADCODE)
/lib/efi_loader/efi_var_mem.c: 236 in efi_var_mem_init()
230 memset(efi_var_buf, 0, EFI_VAR_BUF_SIZE);
231 efi_var_buf->magic = EFI_VAR_FILE_MAGIC;
232 efi_var_buf->length = (uintptr_t)efi_var_buf->var -
233 (uintptr_t)efi_var_buf;
234
235 if (ret != EFI_SUCCESS)
>>> CID 492766: Control flow issues (DEADCODE)
>>> Execution cannot reach this statement: "return ret;".
236 return ret;
237 ret =
efi_create_event(EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, TPL_CALLBACK,
238
efi_var_mem_notify_virtual_address_map, NULL,
239NULL, );
240 if (ret != EFI_SUCCESS)
241 return ret;
** CID 492765: Uninitialized variables (UNINIT)
*** CID 492765: Uninitialized variables (UNINIT)
/net/bootp.c: 888 in dhcp_process_options()
882 net_root_path[size] = 0;
883 break;
884 case 28:/* Ignore Broadcast Address Option */
885 break;
886 case 40:/* NIS Domain name */
887 if (net_nis_domain[0] == 0) {
>>> CID 492765: Uninitialized variables (UNINIT)
>>> Using uninitialized value "size" when calling "truncate_sz".
888 size = truncate_sz("NIS Domain Name",
889 sizeof(net_nis_domain), size);
890 memcpy(_nis_domain, popt + 2, size);
891 net_nis_domain[size] = 0;
892 }
893 break;
--
Tom
signature.asc
Description: PGP signature
[PATCH 2/2] arm: dts: k3-j7200-binman: Add support for HSSE1.0 and HSFS1.0
J7200 has SR1.0 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR1.0 and HS-FS SR1.0 so
add support for them.
Reported-by: Suman Anna
Reported-by: Aniket Limaye
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j7200-binman.dtsi | 95 ++-
1 file changed, 94 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j7200-binman.dtsi
b/arch/arm/dts/k3-j7200-binman.dtsi
index 06db8659876..e8020fec2dc 100644
--- a/arch/arm/dts/k3-j7200-binman.dtsi
+++ b/arch/arm/dts/k3-j7200-binman.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
@@ -47,6 +47,52 @@
config = "pm-cfg_j7200.yaml";
};
+ {
+ tiboot3-j7200-hs-evm.bin {
+ filename = "tiboot3-j7200-hs-evm.bin";
+ ti-secure-rom {
+ content = <_boot_spl_sr1>, <_fs_enc_sr1>,
<_tifs_cfg_sr1>,
+ <_dm_cfg_sr1>, <_inner_cert_sr1>;
+ combined;
+ dm-data;
+ core-opts = <2>;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <_boot_spl_sr1>;
+ content-sysfw = <_fs_enc_sr1>;
+ content-sysfw-data = <_tifs_cfg_sr1>;
+ content-sysfw-inner-cert = <_inner_cert_sr1>;
+ content-dm-data = <_dm_cfg_sr1>;
+ load = <0x41c0>;
+ load-sysfw = <0x4>;
+ load-sysfw-data = <0x7f000>;
+ load-dm-data = <0x41c8>;
+ };
+ u_boot_spl_sr1: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc_sr1: ti-fs-enc.bin {
+ filename = "ti-sysfw/ti-fs-firmware-j7200-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_sr1: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert_sr1: sysfw-inner-cert {
+ filename = "ti-sysfw/ti-fs-firmware-j7200-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg_sr1: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+};
+
{
tiboot3-j7200_sr2-hs-evm.bin {
filename = "tiboot3-j7200_sr2-hs-evm.bin";
@@ -92,6 +138,53 @@
};
};
+ {
+ tiboot3-j7200-hs-fs-evm.bin {
+ filename = "tiboot3-j7200-hs-fs-evm.bin";
+ ti-secure-rom {
+ content = <_boot_spl_fs_sr1>, <_fs_enc_fs_sr1>,
+ <_tifs_cfg_fs_sr1>,
<_dm_cfg_fs_sr1>,
+ <_inner_cert_fs_sr1>;
+ combined;
+ dm-data;
+ core-opts = <2>;
+ sysfw-inner-cert;
+ keyfile = "custMpk.pem";
+ sw-rev = <1>;
+ content-sbl = <_boot_spl_fs_sr1>;
+ content-sysfw = <_fs_enc_fs_sr1>;
+ content-sysfw-data = <_tifs_cfg_fs_sr1>;
+ content-sysfw-inner-cert = <_inner_cert_fs_sr1>;
+ content-dm-data = <_dm_cfg_fs_sr1>;
+ load = <0x41c0>;
+ load-sysfw = <0x4>;
+ load-sysfw-data = <0x7f000>;
+ load-dm-data = <0x41c8>;
+ };
+ u_boot_spl_fs_sr1: u-boot-spl {
+ no-expanded;
+ };
+ ti_fs_enc_fs_sr1: ti-fs-enc.bin {
+ filename =
"ti-sysfw/ti-fs-firmware-j7200-hs-fs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_tifs_cfg_fs_sr1: combined-tifs-cfg.bin {
+ filename = "combined-tifs-cfg.bin";
+ type = "blob-ext";
+ };
+ sysfw_inner_cert_fs_sr1: sysfw-inner-cert {
+ filename =
"ti-sysfw/ti-fs-firmware-j7200-hs-fs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ combined_dm_cfg_fs_sr1: combined-dm-cfg.bin {
+ filename = "combined-dm-cfg.bin";
+
[PATCH 0/2] Generate all SR boot binaries
Add support for missing HS SRs in the build for J721E and J7200. Boot logs: https://gist.github.com/nehamalcom/e652752623537aced8cf31308015d7c9 Neha Malcom Francis (2): arm: dts: k3-j721e-binman: Add support for HSSE2.0 and HSFS1.1 arm: dts: k3-j7200-binman: Add support for HSSE1.0 and HSFS1.0 arch/arm/dts/k3-j7200-binman.dtsi | 95 +- arch/arm/dts/k3-j721e-binman.dtsi | 201 +- 2 files changed, 294 insertions(+), 2 deletions(-) -- 2.34.1
[PATCH 1/2] arm: dts: k3-j721e-binman: Add support for HSSE2.0 and HSFS1.1
J721E has SR1.1 and SR2.0 having three variants of each GP, HS-FS and
HS-SE. Current build does not generate HS-SE SR2.0 and HS-FS SR1.1 so
add support for them.
Reported-by: Suman Anna
Signed-off-by: Neha Malcom Francis
---
arch/arm/dts/k3-j721e-binman.dtsi | 201 +-
1 file changed, 200 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-j721e-binman.dtsi
b/arch/arm/dts/k3-j721e-binman.dtsi
index 75a6e9599b9..90e4a31329e 100644
--- a/arch/arm/dts/k3-j721e-binman.dtsi
+++ b/arch/arm/dts/k3-j721e-binman.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
*/
#include "k3-binman.dtsi"
@@ -129,6 +129,205 @@
};
};
+ {
+ tiboot3-j721e_sr2-hs-evm.bin {
+ filename = "tiboot3-j721e_sr2-hs-evm.bin";
+ ti-secure-rom {
+ content = <_boot_spl_sr2>;
+ core = "public";
+ core-opts = <2>;
+ load = ;
+ keyfile = "custMpk.pem";
+ };
+ u_boot_spl_sr2: u-boot-spl {
+ no-expanded;
+ };
+ };
+ sysfw_sr2 {
+ filename = "sysfw.bin_sr2";
+ ti-secure-rom {
+ content = <_fs_cert_sr2>;
+ core = "secure";
+ load = <0x4>;
+ keyfile = "custMpk.pem";
+ countersign;
+ };
+ ti_fs_cert_sr2: ti-fs-cert.bin {
+ filename =
"ti-sysfw/ti-fs-firmware-j721e_sr2-hs-cert.bin";
+ type = "blob-ext";
+ optional;
+ };
+ ti-fs-firmware-j721e_sr2-hs-enc.bin {
+ filename =
"ti-sysfw/ti-fs-firmware-j721e_sr2-hs-enc.bin";
+ type = "blob-ext";
+ optional;
+ };
+ };
+ itb_sr2 {
+ filename = "sysfw-j721e_sr2-hs-evm.itb";
+ fit {
+ description = "SYSFW and Config fragments";
+ #address-cells = <1>;
+ images {
+ sysfw.bin {
+ description = "sysfw";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ blob-ext {
+ filename = "sysfw.bin_sr2";
+ };
+ };
+ board-cfg.bin {
+ description = "board-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ board_cfg_sr2: board-cfg {
+ filename = "board-cfg.bin";
+ type = "blob-ext";
+ };
+
+ };
+ pm-cfg.bin {
+ description = "pm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+ };
+ pm_cfg_sr2: pm-cfg {
+ filename = "pm-cfg.bin";
+ type = "blob-ext";
+ };
+ };
+ rm-cfg.bin {
+ description = "rm-cfg";
+ type = "firmware";
+ arch = "arm";
+ compression = "none";
+ ti-secure {
+ content = <_cfg_sr2>;
+ keyfile = "custMpk.pem";
+
[ANN] U-Boot v2024.07-rc1 released
Hey all, It's release day and here is -rc1. Looking at my own queue, I think things are overall good. There's a few changes I want to pull in still (mainly moving more things to OF_UPSTREAM) but since they were recently posted I'll wait a little bit. In terms of a changelog, git log --merges v2024.04..v2024.07-rc1 contains what I've pulled but as always, better PR messages and tags will provide better results here. I hope to remain on schedule and that means the rest of the rcs every other Monday, and with final release on Monday, July 1st, 2024. Thanks all! -- Tom signature.asc Description: PGP signature
RISC-V u-boot unable to boot QEMU using '-cpu max'
Hi, In QEMU we have a 'max' type CPU that implements (almost) all extensions that QEMU is able to emulate. Recently, in QEMU commit 249e0905d05, we bumped the extensions for this CPU. And after this commit this CPU is now unable to boot a guest using upstream u-boot. Here's the error being thrown: qemu-system-riscv64 \ -machine virt -nographic -m 8G -smp 8 \ -cpu max -kernel uboot.elf (...) (...) initcall sequence 8027c3e8 failed at call 8021259e (err=-28) ### ERROR ### Please RESET the board ### I can get the guest to boot if I disable the following extensions from the 'max' CPU: -cpu max,zfbfmin=false,zvfbfmin=false,zvfbfwma=false Due to QEMU extension dependencies I'm not able to disable these individually. What I can say is that u-boot isn't playing ball to at least one of them. Is this an u-boot bug? Up to this point I was assuming that u-boot would silently ignore hart extensions that it doesn't support. Thanks, Daniel
[PATCH 1/1] doc: correct description of 'env print -e'
If 'env print -e' is invoked without variable name, all UEFI variables are
listed.
Describe that 'env print -e' requires CONFIG_HEXDUMP=y to print content of
UEFI variables.
Signed-off-by: Heinrich Schuchardt
---
doc/usage/cmd/env.rst | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/doc/usage/cmd/env.rst b/doc/usage/cmd/env.rst
index 040076bcc03..5478c541776 100644
--- a/doc/usage/cmd/env.rst
+++ b/doc/usage/cmd/env.rst
@@ -226,7 +226,7 @@ in UEFI variables.
\-a
all U-Boot environment, when 'name' is absent.
\-e
-print UEFI variables, all by default when 'name'.
+print UEFI variables, all by default if 'name' is not provided.
\-guid guid
print only the UEFI variables matching this GUID (any by default)
with guid format = "----".
@@ -372,6 +372,10 @@ info
load
CONFIG_CMD_NVEDIT_LOAD
+print
+CONFIG_CMD_NVEDIT_EFI for UEFI variables support ('-e' option),
+additionally CONFIG_HEXDUMP to display content of UEFI variables
+
run
CONFIG_CMD_RUN
@@ -381,5 +385,5 @@ save
select
CONFIG_CMD_NVEDIT_SELECT
-set, print
-CONFIG_CMD_NVEDIT_EFI for '-e' option
+set
+CONFIG_CMD_NVEDIT_EFI for UEFI variables support ('-e' option)
--
2.43.0
Re: [PATCH v2 2/3] configs/rock5b: Set NET_PREFER_ROM_MAC_ADDR to y
On 4/22/24 3:56 PM, Detlev Casanova wrote: --- configs/rock5b-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) This patch seems to be missing commit message and SoB line
Re: [PATCH v2 1/3] net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR
On 4/22/24 3:56 PM, Detlev Casanova wrote: On some boards, a MAC address is set based on the CPU ID or other information. This is usually done in the misc_init_r() function. This becomes a problem for net devices that are probed after the call to misc_init_r(), for example, when the ethernet is on a PCI port, which needs to be enumerated. In this case, misc_init_r() will set the ethaddr variable, then, when the ethernet device is probed, if it has a ROM address, u-boot will warn about a MAC address mismatch and use the misc_init_r() address instead of the one in ROM. The operating system later will most likely use the ROM MAC address, which can be confusing. To avoid that, this commit introduces NET_PREFER_ROM_MAC_ADDR that can be set for boards that have such an interface. Signed-off-by: Detlev Casanova Won't the system pick ROM MAC if $ethaddr is not set ?
Re: [PATCH v2 0/5] Kconfig: some cleanups
On Tue, 16 Apr 2024 08:55:14 +0200, Michal Simek wrote: > I looked as cleaning up some dependencies and I found that qconfig is > reporting some issues. This series is fixing some of them. But there are > still some other pending. That's why please go and fix them if they are > related to your board. > > UTF-8: I am using uni2ascii -B < file to do conversion. When you run it in > a loop you will find some other issue with copyright chars or some issues > in files taken from the Linux kernel like DTs. They should be likely fixed > in the kernel first. > Based on discussion I am ignoring names too. > > [...] Applied to u-boot/master, thanks! -- Tom
Re: [PATCH v2 0/5] configs: apple: Switch to standard boot + small adjustments
On Thu, 18 Apr 2024 21:00:24 +0200, Janne Grunau wrote: > This series contains a few misc config changes for Apple silicon > systems: > - switch from the deprecated distro boot scripts to standard boot > - allows EFI console resizing based on the video console size > - enables 16x32 bitmap fonts as Apple devices come with high DPI > displays > - enables 64-bit LBA addressing > > [...] Applied to u-boot/master, thanks! -- Tom
Re: Pull request: u-boot-sunxi/master for v2024.07
On Mon, Apr 22, 2024 at 05:22:49PM +0100, Andre Przywara wrote: > Hi Tom, > > as per the usual late ;-) please pull the sunxi/master branch, containing > some 2024.07 changes for Allwinner. Not many and nothing really exciting > this time: there are more patches in fly, but they are not ready yet. > I will also send some DT updates and new board defconfig files later, once > they have seen the list. I am aware of the USB rebasing repo efforts, > but would like to see how this plays out, also we have one compatibility > issue that I painstakingly work around in the U-Boot tree for the last three > years or so. So for now I stick to the previous approach. > > So now just some easy changes: support for USB peripheral mode on the > Allwinner F1C100s, T113-s3 SPI boot support, and some SPL cleanup patches. > > The branch passed the gitlab CI run, and brief boot testing on some boards > didn't turn up any issues. > > Please pull! > > Cheers, > Andre > > == > The following changes since commit c08685289171e68afd4bae2eb2e279cdc49a407d: > > Merge tag 'u-boot-imx-master-20240420' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2024-04-20 15:16:17 > -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-sunxi.git master > > for you to fetch changes up to 192c5c9e51c1ef100c3d027d253ffad26ff75a68: > > sunxi: sun9i: make more clock functions SPL only (2024-04-22 01:12:26 +0100) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] doc: release_cycle: Note when next branch opens
On Mon, 22 Apr 2024 10:44:54 -0600, Tom Rini wrote: > While I have said this in various release emails, it should be > documented here as well that the next branch opens with the second > release candidate. > > Applied to u-boot/master, thanks! -- Tom
[PATCH v2] mmc: sdhci: introduce adma_write_desc() hook to struct sdhci_ops
From: Ian Roberts
Add this hook so that it can be overridden with driver specific
implementations. We also let the original sdhci_adma_write_desc()
accept so that the function can set its new value. Then export
the function so that it could be reused by driver's specific
implementations.
The above is a port of Linux kernel commit 54552e4948cbf
In addition, allow drivers to allocate their own ADMA descriptor
tables if additional space is required.
Finally, fix the assignment of adma_addr to fix compiler warning
on 64-bit platforms that still use 32-bit DMA addressing.
Co-developed-by: Nathan Barrett-Morrison
Signed-off-by: Nathan Barrett-Morrison
Co-developed-by: Greg Malysa
Signed-off-by: Greg Malysa
Signed-off-by: Ian Roberts
---
Changes in v2:
- Switch from #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA) to #ifdef
CONFIG_MMC_SDHCI_ADMA_HELPERS, as CONFIG_IS_ENABLED() causes a build
failure during SPL builds when CONFIG_SPL_MMC is set.
- Passed CI before submitting this time
---
drivers/mmc/fsl_esdhc.c | 2 +-
drivers/mmc/sdhci-adma.c | 41 +++-
drivers/mmc/sdhci.c | 8 +---
include/sdhci.h | 12 ++--
4 files changed, 44 insertions(+), 19 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index d50669..bd0671cc52 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -252,7 +252,7 @@ static void esdhc_setup_dma(struct fsl_esdhc_priv *priv,
struct mmc_data *data)
priv->adma_desc_table) {
debug("Using ADMA2\n");
/* prefer ADMA2 if it is available */
- sdhci_prepare_adma_table(priv->adma_desc_table, data,
+ sdhci_prepare_adma_table(NULL, priv->adma_desc_table, data,
priv->dma_addr);
adma_addr = virt_to_phys(priv->adma_desc_table);
diff --git a/drivers/mmc/sdhci-adma.c b/drivers/mmc/sdhci-adma.c
index 8213223d3f..8c38448b6a 100644
--- a/drivers/mmc/sdhci-adma.c
+++ b/drivers/mmc/sdhci-adma.c
@@ -9,9 +9,10 @@
#include
#include
-static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
- dma_addr_t addr, u16 len, bool end)
+void sdhci_adma_write_desc(struct sdhci_host *host, void **next_desc,
+ dma_addr_t addr, int len, bool end)
{
+ struct sdhci_adma_desc *desc = *next_desc;
u8 attr;
attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
@@ -19,17 +20,30 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
attr |= ADMA_DESC_ATTR_END;
desc->attr = attr;
- desc->len = len;
+ desc->len = len & 0x;
desc->reserved = 0;
desc->addr_lo = lower_32_bits(addr);
#ifdef CONFIG_DMA_ADDR_T_64BIT
desc->addr_hi = upper_32_bits(addr);
#endif
+
+ *next_desc += ADMA_DESC_LEN;
+}
+
+static inline void __sdhci_adma_write_desc(struct sdhci_host *host,
+ void **desc, dma_addr_t addr,
+ int len, bool end)
+{
+ if (host && host->ops && host->ops->adma_write_desc)
+ host->ops->adma_write_desc(host, desc, addr, len, end);
+ else
+ sdhci_adma_write_desc(host, desc, addr, len, end);
}
/**
* sdhci_prepare_adma_table() - Populate the ADMA table
*
+ * @host: Pointer to the sdhci_host
* @table: Pointer to the ADMA table
* @data: Pointer to MMC data
* @addr: DMA address to write to or read from
@@ -39,25 +53,26 @@ static void sdhci_adma_desc(struct sdhci_adma_desc *desc,
* Please note, that the table size depends on CONFIG_SYS_MMC_MAX_BLK_COUNT and
* we don't have to check for overflow.
*/
-void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
- struct mmc_data *data, dma_addr_t addr)
+void sdhci_prepare_adma_table(struct sdhci_host *host,
+ struct sdhci_adma_desc *table,
+ struct mmc_data *data, dma_addr_t start_addr)
{
+ dma_addr_t addr = start_addr;
uint trans_bytes = data->blocksize * data->blocks;
- uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
- struct sdhci_adma_desc *desc = table;
- int i = desc_count;
+ void *next_desc = table;
+ int i = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
while (--i) {
- sdhci_adma_desc(desc, addr, ADMA_MAX_LEN, false);
+ __sdhci_adma_write_desc(host, _desc, addr,
+ ADMA_MAX_LEN, false);
addr += ADMA_MAX_LEN;
trans_bytes -= ADMA_MAX_LEN;
- desc++;
}
- sdhci_adma_desc(desc, addr, trans_bytes, true);
+ __sdhci_adma_write_desc(host, _desc, addr, trans_bytes, true);
- flush_cache((dma_addr_t)table,
- ROUND(desc_count * sizeof(struct
[PATCH v2] cmd: gpt: initialize partition table
Change in v2: - Fix applies to all block devices, not just MMC. If partition init is not completed within the gpt write, the gpt partition list will not be updated. Signed-off-by: Kishan Dudhatra diff --git a/cmd/gpt.c b/cmd/gpt.c index d7e96529a6..7aaf1889a5 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -643,6 +643,10 @@ static int gpt_default(struct blk_desc *blk_dev_desc, const char *str_part) free(str_disk_guid); free(partitions); + /* initialize partition table */ + if (blk_enabled()) + part_init(blk_dev_desc); + return ret; } -- 2.34.1
Re: [PATCH 2/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
Hi Quentin,
On 2024-04-22 18:41, Quentin Schulz wrote:
> From: Quentin Schulz
>
> The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
> connector) system-on-module from Theobroma Systems, featuring the
> Rockchip RK3588.
>
> It provides the following feature set:
> * up to 16GB LPDDR4x
> * on-module eMMC
> * SD card (on a baseboard) via edge connector
> * Gigabit Ethernet with on-module GbE PHY
> * HDMI/eDP
> * MIPI-DSI
> * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
> * HDMI input over FPC connector
> * CAN
> * USB
>- 1x USB 3.0 dual-role (direct connection)
>- 2x USB 3.0 host + 1x USB 2.0 host
> * PCIe
>- 1x PCIe 2.1 Gen3, 4 lanes
>- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
> * on-module ATtiny816 companion controller, implementing:
>- low-power RTC functionality (ISL1208 emulation)
>- fan controller (AMC6821 emulation)
> * on-module Secure Element with Global Platform 2.2.1 compliant
> JavaCard environment
>
> The support is added for Tiger on Haikou devkit, similarly to RK3399
> Puma and PX30 Ringneck.
>
> The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.
>
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 54 ++
> arch/arm/dts/rk3588-tiger-haikou.dts | 266
> arch/arm/dts/rk3588-tiger.dtsi | 690
> +
> arch/arm/mach-rockchip/rk3588/Kconfig | 31 +
> board/theobroma-systems/tiger_rk3588/Kconfig | 16 +
> board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 +
> board/theobroma-systems/tiger_rk3588/Makefile | 10 +
> .../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++
> configs/tiger-rk3588_defconfig | 114
> doc/board/rockchip/rockchip.rst| 1 +
> doc/board/theobroma-systems/index.rst | 1 +
> doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++
> include/configs/tiger_rk3588.h | 15 +
> 14 files changed, 1367 insertions(+)
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index b1c9c6222e5..ef901642a0a 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
> rk3588-quartzpro64.dtb \
> rk3588s-rock-5a.dtb \
> rk3588-rock-5b.dtb \
> + rk3588-tiger-haikou.dtb \
> rk3588-turing-rk1.dtb
>
> dtb-$(CONFIG_ROCKCHIP_RV1108) += \
> diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
> b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
> new file mode 100644
> index 000..4259399193a
> --- /dev/null
> +++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
> @@ -0,0 +1,54 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
> + */
> +
> +#include "rk3588-u-boot.dtsi"
> +
> +/ {
> + chosen {
> + u-boot,spl-boot-order = "same-as-spl", ,
> + };
> +};
> +
> +_pwrseq {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> +_reset {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> + {
> + bootph-pre-ram;
> + bootph-some-ram;
> +};
> +
> + {
> + /* U-Boot currently cannot handle anything below HS200 for eMMC on
> RK3588 */
> + /delete-property/ mmc-ddr-1_8v;
> + /delete-property/ cap-mmc-highspeed;
> +};
> +
> +/* Q7 USB P0 */
> + {
> + status = "okay";
> +};
> +
> +_otg {
> + status = "okay";
> +};
> +
> +_phy1 {
> + status = "okay";
> +};
> +
> +_phy1_u3 {
> + status = "okay";
> +};
> +
> +_host1_xhci {
> + status = "okay";
> +};
Following should be added to possible fix uart2 pinctrl in SPL:
_xfer {
bootph-all;
};
[snip]
> diff --git a/configs/tiger-rk3588_defconfig b/configs/tiger-rk3588_defconfig
> new file mode 100644
> index 000..6545445bba1
> --- /dev/null
> +++ b/configs/tiger-rk3588_defconfig
> @@ -0,0 +1,114 @@
> +CONFIG_ARM=y
> +CONFIG_SKIP_LOWLEVEL_INIT=y
> +CONFIG_COUNTER_FREQUENCY=2400
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SPL_GPIO=y
> +CONFIG_SF_DEFAULT_SPEED=2400
> +CONFIG_SF_DEFAULT_MODE=0x2000
> +CONFIG_ENV_SIZE=0x1f000
> +CONFIG_DEFAULT_DEVICE_TREE="rk3588-tiger-haikou"
> +CONFIG_ROCKCHIP_RK3588=y
> +CONFIG_ROCKCHIP_BOOT_MODE_REG=0x0
> +CONFIG_SPL_SERIAL=y
> +CONFIG_DEBUG_UART_CHANNEL=2
> +CONFIG_TARGET_TIGER_RK3588=y
> +CONFIG_DEBUG_UART_BASE=0xfeb5
> +CONFIG_DEBUG_UART_CLOCK=2400
> +CONFIG_SYS_LOAD_ADDR=0xc00800
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_FIT_SIGNATURE=y
> +CONFIG_SPL_LOAD_FIT=y
> +# CONFIG_BOOTMETH_VBE is not set
> +CONFIG_LEGACY_IMAGE_FORMAT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-tiger-haikou.dtb"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_CYCLIC=y
> +CONFIG_SPL_MAX_SIZE=0x4
>
Re: [PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL
Hi Quentin,
On 2024-04-22 18:41, Quentin Schulz wrote:
> From: Quentin Schulz
>
> UART2 controller is the controller in the reference design for debug
> console. The default mux is M0 in that reference design. Until now, all
> boards seemed to be using UART2M0 but RK3588 Tiger for example will be
> using UART2M2 instead.
>
> Therefore, let's add support for UART2M1 and M2 as possible muxes for
> the UART2 controller used as debug console. UART2M1 support was not
> tested.
>
> The default value is M0 to match the one used currently by all devices
> and the reference design.
Is this really necessary?
Use of board_debug_uart_init() should typically only be needed in TPL on
Rockchip platform, and with ROCKCHIP_TPL being used it should be enough
to use rkbin/ddrbin_tool to change uart config and just ensure correct
pinctrl is used for uart node, and that the uart node is included in SPL
for correct serial console use.
May I suggest you try adding following to defconfig and drop this patch?
# CONFIG_DEBUG_UART_BOARD_INIT is not set
I would expect that should result in same/working behavior without
having to add any new code.
Regards,
Jonas
>
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
> arch/arm/mach-rockchip/rk3588/Kconfig | 10 ++
> arch/arm/mach-rockchip/rk3588/rk3588.c | 36
> ++
> 2 files changed, 46 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
> b/arch/arm/mach-rockchip/rk3588/Kconfig
> index d7e4af31f24..cacdb0459c9 100644
> --- a/arch/arm/mach-rockchip/rk3588/Kconfig
> +++ b/arch/arm/mach-rockchip/rk3588/Kconfig
> @@ -221,6 +221,16 @@ config ROCKCHIP_COMMON_STACK_ADDR
> config TEXT_BASE
> default 0x00a0
>
> +config DEBUG_UART_CHANNEL
> + int "Mux channel to use for debug UART2"
> + depends on DEBUG_UART_BOARD_INIT
> + default 0
> + range 0 2
> + help
> + UART2 can use three different set of pins to route the output.
> + For using the UART for early debugging the route to use needs
> + to be declared (0, 1 or 2).
> +
> source board/edgeble/neural-compute-module-6/Kconfig
> source board/friendlyelec/nanopc-t6-rk3588/Kconfig
> source board/pine64/quartzpro64-rk3588/Kconfig
> diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
> b/arch/arm/mach-rockchip/rk3588/rk3588.c
> index eb65dafe3a2..e330ad6a697 100644
> --- a/arch/arm/mach-rockchip/rk3588/rk3588.c
> +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
> @@ -94,9 +94,32 @@ enum {
> GPIO0B6_UART2_RX_M0 = 10,
> };
>
> +/* GPIO3B_IOMUX_SEL_L */
> +enum {
> + GPIO3B1_SHIFT = 4,
> + GPIO3B1_MASK= GENMASK(7, 4),
> + GPIO3B1_UART2_TX_M2 = 10,
> +
> + GPIO3B2_SHIFT = 8,
> + GPIO3B2_MASK= GENMASK(11, 8),
> + GPIO3B2_UART2_RX_M2 = 10,
> +};
> +
> +/* GPIO4D_IOMUX_SEL_L */
> +enum {
> + GPIO4D0_SHIFT = 0,
> + GPIO4D0_MASK= GENMASK(3, 0),
> + GPIO4D0_UART2_TX_M1 = 10,
> +
> + GPIO4D1_SHIFT = 4,
> + GPIO4D1_MASK= GENMASK(7, 4),
> + GPIO4D1_UART2_RX_M1 = 10,
> +};
> +
> void board_debug_uart_init(void)
> {
> __maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void
> *)BUS_IOC_BASE;
> +#if (CONFIG_DEBUG_UART_CHANNEL == 0)
> static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
>
> /* Refer to BUS_IOC */
> @@ -110,6 +133,19 @@ void board_debug_uart_init(void)
>GPIO0B6_MASK | GPIO0B5_MASK,
>GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
>GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
> +#elif (CONFIG_DEBUG_UART_CHANNEL == 1)
> + /* UART2_M1 Switch iomux */
> + rk_clrsetreg(_ioc->gpio4d_iomux_sel_l,
> + GPIO4D0_MASK | GPIO4D1_MASK,
> + GPIO4D0_UART2_TX_M1 << GPIO4D0_UART2_TX_M1 |
> + GPIO4D1_UART2_RX_M1 << GPIO4D1_SHIFT);
> +#else
> + /* UART2_M2 Switch iomux */
> + rk_clrsetreg(_ioc->gpio3b_iomux_sel_l,
> + GPIO3B1_MASK | GPIO3B2_MASK,
> + GPIO3B1_UART2_TX_M2 << GPIO3B1_SHIFT |
> + GPIO3B2_UART2_RX_M2 << GPIO3B2_SHIFT);
> +#endif /* CONFIG_DEBUG_UART_CHANNEL */
> }
>
> #ifdef CONFIG_SPL_BUILD
>
Re: [PATCH] cmd: gpt: initialize partition table
On Mon, Apr 22, 2024 at 10:53:35PM +0530, Kishan Dudhatra wrote: > If partition init is not completed within the gpt write, > the gpt partition list will not be updated. > > Signed-off-by: Kishan Dudhatra > > diff --git a/cmd/gpt.c b/cmd/gpt.c > index d7e96529a6..2d652f480a 100644 > --- a/cmd/gpt.c > +++ b/cmd/gpt.c > @@ -643,6 +643,10 @@ static int gpt_default(struct blk_desc *blk_dev_desc, > const char *str_part) > free(str_disk_guid); > free(partitions); > > + /* initialize partition table */ > + if ((blk_dev_desc)->uclass_id == UCLASS_MMC) > + part_init(blk_dev_desc); > + > return ret; > } Is there something more generic we can check for here? This sounds like a problem for any block device, not just MMC. Thanks. -- Tom signature.asc Description: PGP signature
[PATCH] cmd: gpt: initialize partition table
If partition init is not completed within the gpt write, the gpt partition list will not be updated. Signed-off-by: Kishan Dudhatra diff --git a/cmd/gpt.c b/cmd/gpt.c index d7e96529a6..2d652f480a 100644 --- a/cmd/gpt.c +++ b/cmd/gpt.c @@ -643,6 +643,10 @@ static int gpt_default(struct blk_desc *blk_dev_desc, const char *str_part) free(str_disk_guid); free(partitions); + /* initialize partition table */ + if ((blk_dev_desc)->uclass_id == UCLASS_MMC) + part_init(blk_dev_desc); + return ret; } -- 2.34.1
[PATCH] doc: release_cycle: Note when next branch opens
While I have said this in various release emails, it should be documented here as well that the next branch opens with the second release candidate. Signed-off-by: Tom Rini --- doc/develop/release_cycle.rst | 3 +++ 1 file changed, 3 insertions(+) diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 8d4c112f1493..7931521ad9bb 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -19,6 +19,9 @@ Cycle as follows: * After the merge window closes, no new features may be added to allow for a release candidate phase which is intended to fix bugs and regressions. +* To help with late pull requests, the **next** branch will open when the + second release candidate is published. + *Note:* While we try to adhere to the release schedule, we will not hesitate and take the liberty to delay a release if there are good reasons, for example if there are known bugs or other technical -- 2.34.1
[PATCH 2/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
From: Quentin Schulz
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3588.
It provides the following feature set:
* up to 16GB LPDDR4x
* on-module eMMC
* SD card (on a baseboard) via edge connector
* Gigabit Ethernet with on-module GbE PHY
* HDMI/eDP
* MIPI-DSI
* 4x MIPI-CSI (3x on FPC connectors, 1x over Q7)
* HDMI input over FPC connector
* CAN
* USB
- 1x USB 3.0 dual-role (direct connection)
- 2x USB 3.0 host + 1x USB 2.0 host
* PCIe
- 1x PCIe 2.1 Gen3, 4 lanes
- 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes
* on-module ATtiny816 companion controller, implementing:
- low-power RTC functionality (ISL1208 emulation)
- fan controller (AMC6821 emulation)
* on-module Secure Element with Global Platform 2.2.1 compliant
JavaCard environment
The support is added for Tiger on Haikou devkit, similarly to RK3399
Puma and PX30 Ringneck.
The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 54 ++
arch/arm/dts/rk3588-tiger-haikou.dts | 266
arch/arm/dts/rk3588-tiger.dtsi | 690 +
arch/arm/mach-rockchip/rk3588/Kconfig | 31 +
board/theobroma-systems/tiger_rk3588/Kconfig | 16 +
board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 +
board/theobroma-systems/tiger_rk3588/Makefile | 10 +
.../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++
configs/tiger-rk3588_defconfig | 114
doc/board/rockchip/rockchip.rst| 1 +
doc/board/theobroma-systems/index.rst | 1 +
doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++
include/configs/tiger_rk3588.h | 15 +
14 files changed, 1367 insertions(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b1c9c6222e5..ef901642a0a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -180,6 +180,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3588) += \
rk3588-quartzpro64.dtb \
rk3588s-rock-5a.dtb \
rk3588-rock-5b.dtb \
+ rk3588-tiger-haikou.dtb \
rk3588-turing-rk1.dtb
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
diff --git a/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
new file mode 100644
index 000..4259399193a
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2024 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include "rk3588-u-boot.dtsi"
+
+/ {
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+};
+
+_pwrseq {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+_reset {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
+ /* U-Boot currently cannot handle anything below HS200 for eMMC on
RK3588 */
+ /delete-property/ mmc-ddr-1_8v;
+ /delete-property/ cap-mmc-highspeed;
+};
+
+/* Q7 USB P0 */
+ {
+ status = "okay";
+};
+
+_otg {
+ status = "okay";
+};
+
+_phy1 {
+ status = "okay";
+};
+
+_phy1_u3 {
+ status = "okay";
+};
+
+_host1_xhci {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3588-tiger-haikou.dts
b/arch/arm/dts/rk3588-tiger-haikou.dts
new file mode 100644
index 000..d672198c6b6
--- /dev/null
+++ b/arch/arm/dts/rk3588-tiger-haikou.dts
@@ -0,0 +1,266 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH
+ */
+
+/dts-v1/;
+#include
+#include "rk3588-tiger.dtsi"
+
+/ {
+ model = "Theobroma Systems RK3588-Q7 SoM on Haikou devkit";
+ compatible = "tsd,rk3588-tiger-haikou", "tsd,rk3588-tiger",
"rockchip,rk3588";
+
+ aliases {
+ ethernet0 =
+ mmc1 =
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <_keys_pin>;
+
+ button-batlow-n {
+ label = "BATLOW#";
+ linux,code = ;
+ gpios = < RK_PB5 GPIO_ACTIVE_LOW>;
+ };
+
+ button-slp-btn-n {
+ label = "SLP_BTN#";
+ linux,code = ;
+
[PATCH 1/2] rockchip: rk3588: add support for UART2 M1 and M2 in SPL
From: Quentin Schulz
UART2 controller is the controller in the reference design for debug
console. The default mux is M0 in that reference design. Until now, all
boards seemed to be using UART2M0 but RK3588 Tiger for example will be
using UART2M2 instead.
Therefore, let's add support for UART2M1 and M2 as possible muxes for
the UART2 controller used as debug console. UART2M1 support was not
tested.
The default value is M0 to match the one used currently by all devices
and the reference design.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/rk3588/Kconfig | 10 ++
arch/arm/mach-rockchip/rk3588/rk3588.c | 36 ++
2 files changed, 46 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3588/Kconfig
b/arch/arm/mach-rockchip/rk3588/Kconfig
index d7e4af31f24..cacdb0459c9 100644
--- a/arch/arm/mach-rockchip/rk3588/Kconfig
+++ b/arch/arm/mach-rockchip/rk3588/Kconfig
@@ -221,6 +221,16 @@ config ROCKCHIP_COMMON_STACK_ADDR
config TEXT_BASE
default 0x00a0
+config DEBUG_UART_CHANNEL
+ int "Mux channel to use for debug UART2"
+ depends on DEBUG_UART_BOARD_INIT
+ default 0
+ range 0 2
+ help
+ UART2 can use three different set of pins to route the output.
+ For using the UART for early debugging the route to use needs
+ to be declared (0, 1 or 2).
+
source board/edgeble/neural-compute-module-6/Kconfig
source board/friendlyelec/nanopc-t6-rk3588/Kconfig
source board/pine64/quartzpro64-rk3588/Kconfig
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index eb65dafe3a2..e330ad6a697 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -94,9 +94,32 @@ enum {
GPIO0B6_UART2_RX_M0 = 10,
};
+/* GPIO3B_IOMUX_SEL_L */
+enum {
+ GPIO3B1_SHIFT = 4,
+ GPIO3B1_MASK= GENMASK(7, 4),
+ GPIO3B1_UART2_TX_M2 = 10,
+
+ GPIO3B2_SHIFT = 8,
+ GPIO3B2_MASK= GENMASK(11, 8),
+ GPIO3B2_UART2_RX_M2 = 10,
+};
+
+/* GPIO4D_IOMUX_SEL_L */
+enum {
+ GPIO4D0_SHIFT = 0,
+ GPIO4D0_MASK= GENMASK(3, 0),
+ GPIO4D0_UART2_TX_M1 = 10,
+
+ GPIO4D1_SHIFT = 4,
+ GPIO4D1_MASK= GENMASK(7, 4),
+ GPIO4D1_UART2_RX_M1 = 10,
+};
+
void board_debug_uart_init(void)
{
__maybe_unused static struct rk3588_bus_ioc * const bus_ioc = (void
*)BUS_IOC_BASE;
+#if (CONFIG_DEBUG_UART_CHANNEL == 0)
static struct rk3588_pmu2_ioc * const pmu2_ioc = (void *)PMU2_IOC_BASE;
/* Refer to BUS_IOC */
@@ -110,6 +133,19 @@ void board_debug_uart_init(void)
GPIO0B6_MASK | GPIO0B5_MASK,
GPIO0B6_UART2_RX_M0 << GPIO0B6_SHIFT |
GPIO0B5_UART2_TX_M0 << GPIO0B5_SHIFT);
+#elif (CONFIG_DEBUG_UART_CHANNEL == 1)
+ /* UART2_M1 Switch iomux */
+ rk_clrsetreg(_ioc->gpio4d_iomux_sel_l,
+GPIO4D0_MASK | GPIO4D1_MASK,
+GPIO4D0_UART2_TX_M1 << GPIO4D0_UART2_TX_M1 |
+GPIO4D1_UART2_RX_M1 << GPIO4D1_SHIFT);
+#else
+ /* UART2_M2 Switch iomux */
+ rk_clrsetreg(_ioc->gpio3b_iomux_sel_l,
+GPIO3B1_MASK | GPIO3B2_MASK,
+GPIO3B1_UART2_TX_M2 << GPIO3B1_SHIFT |
+GPIO3B2_UART2_RX_M2 << GPIO3B2_SHIFT);
+#endif /* CONFIG_DEBUG_UART_CHANNEL */
}
#ifdef CONFIG_SPL_BUILD
--
2.44.0
[PATCH 0/2] rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module
The RK3588-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230 connector) system-on-module from Theobroma Systems, featuring the Rockchip RK3588. It provides the following feature set: * up to 16GB LPDDR4x * on-module eMMC * SD card (on a baseboard) via edge connector * Gigabit Ethernet with on-module GbE PHY * HDMI/eDP * MIPI-DSI * 4x MIPI-CSI (3x on FPC connectors, 1x over Q7) * HDMI input over FPC connector * CAN * USB - 1x USB 3.0 dual-role (direct connection) - 2x USB 3.0 host + 1x USB 2.0 host * PCIe - 1x PCIe 2.1 Gen3, 4 lanes - 2xSATA / 2x PCIe 2.1 Gen1, 2 lanes * on-module ATtiny816 companion controller, implementing: - low-power RTC functionality (ISL1208 emulation) - fan controller (AMC6821 emulation) * on-module Secure Element with Global Platform 2.2.1 compliant JavaCard environment The support is added for Tiger on Haikou devkit, similarly to RK3399 Puma and PX30 Ringneck. The DTS and DTSI are taken from upstream Linux kernel v6.9-rc4. Because Tiger doesn't use the same mux for the debug console as all other RK3588 devices currently supported in U-Boot, an additional patch is required to be able to interact with the device properly. This has a light dependency on https://lore.kernel.org/u-boot/20240415-rk35xx-dram-atags-v3-0-5bc5475b3...@theobroma-systems.com/ (the Tiger defconfig can be updated to remove the dependency if required) Signed-off-by: Quentin Schulz --- Quentin Schulz (2): rockchip: rk3588: add support for UART2 M1 and M2 in SPL rockchip: add support for Theobroma Systems SOM-RK3588-Q7 Tiger module arch/arm/dts/Makefile | 1 + arch/arm/dts/rk3588-tiger-haikou-u-boot.dtsi | 54 ++ arch/arm/dts/rk3588-tiger-haikou.dts | 266 arch/arm/dts/rk3588-tiger.dtsi | 690 + arch/arm/mach-rockchip/rk3588/Kconfig | 41 ++ arch/arm/mach-rockchip/rk3588/rk3588.c | 36 ++ board/theobroma-systems/tiger_rk3588/Kconfig | 16 + board/theobroma-systems/tiger_rk3588/MAINTAINERS | 13 + board/theobroma-systems/tiger_rk3588/Makefile | 10 + .../theobroma-systems/tiger_rk3588/tiger_rk3588.c | 53 ++ configs/tiger-rk3588_defconfig | 114 doc/board/rockchip/rockchip.rst| 1 + doc/board/theobroma-systems/index.rst | 1 + doc/board/theobroma-systems/tiger_rk3588.rst | 102 +++ include/configs/tiger_rk3588.h | 15 + 15 files changed, 1413 insertions(+) --- base-commit: 5fb840ed8339cae3915ea1528a4bfa3e587540e6 change-id: 20240418-tiger-d1531308c9a0 Best regards, -- Quentin Schulz
Re: Please pull u-boot-tegra staging
On Mon, Apr 22, 2024 at 03:15:02PM +0300, Svyatoslav Ryhel wrote: > Dear Tom, > > The following changes since commit 1dd659fd626204bb6a6b4f330c27b11a7823bbb0: > > Merge tag 'video-20240421' of > https://source.denx.de/u-boot/custodians/u-boot-video (2024-04-21 08:54:20 > -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-tegra.git staging > > for you to fetch changes up to 6898cc823413ff01661e7db74ad764da58b682d9: > > board: tegra30: switch to button cmd (2024-04-22 12:17:21 +0300) > Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Pull request: u-boot-sunxi/master for v2024.07
Hi Tom, as per the usual late ;-) please pull the sunxi/master branch, containing some 2024.07 changes for Allwinner. Not many and nothing really exciting this time: there are more patches in fly, but they are not ready yet. I will also send some DT updates and new board defconfig files later, once they have seen the list. I am aware of the USB rebasing repo efforts, but would like to see how this plays out, also we have one compatibility issue that I painstakingly work around in the U-Boot tree for the last three years or so. So for now I stick to the previous approach. So now just some easy changes: support for USB peripheral mode on the Allwinner F1C100s, T113-s3 SPI boot support, and some SPL cleanup patches. The branch passed the gitlab CI run, and brief boot testing on some boards didn't turn up any issues. Please pull! Cheers, Andre == The following changes since commit c08685289171e68afd4bae2eb2e279cdc49a407d: Merge tag 'u-boot-imx-master-20240420' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2024-04-20 15:16:17 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-sunxi.git master for you to fetch changes up to 192c5c9e51c1ef100c3d027d253ffad26ff75a68: sunxi: sun9i: make more clock functions SPL only (2024-04-22 01:12:26 +0100) Andre Przywara (9): usb: musb-new: add Allwinner F1C100s support sunxi: move #ifdef guards around tzpc_init() to header file sunxi: remove unneeded i2c_init_board() call for U-Boot proper sunxi: compile clock.c for SPL only sunxi: sun4i: make more clock functions SPL only sunxi: sun6i: make more clock functions SPL only sunxi: sun50i_h6: make more clock functions SPL only sunxi: sun8i_a83t: make more clock functions SPL only sunxi: sun9i: make more clock functions SPL only Maksim Kiselev (1): sunxi: SPL SPI: Add SPI boot support for the Allwinner R528/T113 SoCs arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 3 - arch/arm/include/asm/arch-sunxi/tzpc.h| 6 ++ arch/arm/mach-sunxi/Kconfig | 2 +- arch/arm/mach-sunxi/Makefile | 2 +- arch/arm/mach-sunxi/board.c | 2 - arch/arm/mach-sunxi/clock.c | 2 - arch/arm/mach-sunxi/clock_sun4i.c | 5 +- arch/arm/mach-sunxi/clock_sun50i_h6.c | 57 arch/arm/mach-sunxi/clock_sun6i.c | 3 +- arch/arm/mach-sunxi/clock_sun8i_a83t.c| 5 +- arch/arm/mach-sunxi/clock_sun9i.c | 97 +-- arch/arm/mach-sunxi/spl_spi_sunxi.c | 78 +++-- board/sunxi/board.c | 9 +-- drivers/usb/musb-new/sunxi.c | 16 + 14 files changed, 163 insertions(+), 124 deletions(-)
[PATCH v2] stm32mp: Reserve OPTEE area in EFI memory map
Since commit 7b78d6438a2b3 ("efi_loader: Reserve unaccessible memory")
memory region above ram_top is tagged in EFI memory map as
EFI_BOOT_SERVICES_DATA.
In case of STM32MP1/STM32MP13 platforms, above ram_top, there is one
reserved-memory region tagged "no-map" dedicated to OP-TEE :
_ addr=de00 size=200 for stm32mp157x-dkx and stm32mp135f-dk
_ addr=fe00 size=200 for stm32mp157c-ev1
Before booting kernel, EFI memory map is first built, the OPTEE region is
tagged as EFI_BOOT_SERVICES_DATA and when reserving LMB, the tag LMB_NONE
is used.
Then after, the LMB are completed by boot_fdt_add_mem_rsv_regions()
which try to add again the same OPTEE region (addr=de00 size=200
in case of stm32mp157x-dkx / stm32mp135f-dk or addr=fe00 size=200
in case for stm2mp157c-ev1)
but now with LMB_NOMAP tag which produces the following error message :
_ for stm32mp157x-dkx / stm32mp135f-dk :
"ERROR: reserving fdt memory region failed (addr=de00 size=200
flags=4)"
_ for stm32mp157c-ev1 :
"ERROR: reserving fdt memory region failed (addr=fe00 size=200
flags=4)"
To avoid this, OPTEE area shouldn't be used by EFI, so we need to mark
it as reserved.
Signed-off-by: Patrice Chotard
---
Changes in v2:
_ update commit message by adding information about memory area
dedicated for OPTEE for various STM32MP1/STM32MP13 boards.
arch/arm/mach-stm32mp/dram_init.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-stm32mp/dram_init.c
b/arch/arm/mach-stm32mp/dram_init.c
index fb1208fc5d5..f67f54f2ae0 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -75,3 +76,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
return reg + size;
}
+
+void efi_add_known_memory(void)
+{
+ if (IS_ENABLED(CONFIG_EFI_LOADER))
+ /*
+* Memory over ram_top is reserved to OPTEE.
+* Declare to EFI only memory area below ram_top
+*/
+ efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
+ EFI_CONVENTIONAL_MEMORY);
+}
--
2.25.1
Re: [PATCH v1 2/3] board: sifive: Call spl_dram_init() for DRAM initialization
On Mon, Apr 22, 2024 at 6:16 AM wrote:
>
> From: Lukas Funke
>
> Call spl_dram_init() since this is commonly used for dram initialization
> in u-boot.
>
> Signed-off-by: Lukas Funke
> ---
>
> board/sifive/unleashed/spl.c | 4 ++--
> board/sifive/unmatched/spl.c | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/board/sifive/unleashed/spl.c b/board/sifive/unleashed/spl.c
> index fe27316b2d..d6725a0e0e 100644
> --- a/board/sifive/unleashed/spl.c
> +++ b/board/sifive/unleashed/spl.c
> @@ -27,9 +27,9 @@ int spl_board_init_f(void)
> {
> int ret;
>
> - ret = spl_soc_init();
> + ret = spl_dram_init();
> if (ret) {
> - debug("FU540 SPL init failed: %d\n", ret);
> + debug("FU540 dram init failed: %d\n", ret);
> return ret;
> }
>
> diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
> index e69bed9d99..500f484844 100644
> --- a/board/sifive/unmatched/spl.c
> +++ b/board/sifive/unmatched/spl.c
> @@ -134,9 +134,9 @@ int spl_board_init_f(void)
> {
> int ret;
>
> - ret = spl_soc_init();
> + ret = spl_dram_init();
> if (ret) {
> - debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
> + debug("HiFive Unmatched FU740 dram init failed: %d\n", ret);
> goto end;
> }
>
> --
> 2.30.2
>
Acronym DRAM should be all capitalized letters in strings.
-E
Re: [PATCH 01/10] board: ti: am62x: Init DRAM size in R5/A53 SPL
On Mon, Apr 22, 2024 at 04:46:04PM +0530, Chintan Vankar wrote: > > > On 17/04/24 21:34, Tom Rini wrote: > > On Wed, Apr 17, 2024 at 05:48:31PM +0530, Sughosh Ganu wrote: > > > hi Chintan, > > > > > > On Wed, 17 Apr 2024 at 13:21, Chintan Vankar wrote: > > > > > > > > > > > > > > > > On 16/04/24 22:30, Tom Rini wrote: > > > > > On Tue, Apr 16, 2024 at 05:52:58PM +0530, Chintan Vankar wrote: > > > > > > > > > > > > > > > > > > On 12/04/24 03:37, Tom Rini wrote: > > > > > > > On Wed, Apr 03, 2024 at 06:18:01PM +0530, Chintan Vankar wrote: > > > > > > > > > > > > > > > > > > > > > > > > On 22/01/24 10:11, Siddharth Vadapalli wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > On 20/01/24 22:11, Tom Rini wrote: > > > > > > > > > > On Mon, Jan 15, 2024 at 01:42:51PM +0530, Siddharth > > > > > > > > > > Vadapalli wrote: > > > > > > > > > > > Hello Tom, > > > > > > > > > > > > > > > > > > > > > > On 12/01/24 18:56, Tom Rini wrote: > > > > > > > > > > > > > > > > > > ... > > > > > > > > > > > > > > > > > > > > > The list of conditionals in > > > > > > > > > > > > common/spl/spl.c::board_init_r() should be > > > > > > > > > > > > updated and probably use SPL_NET as the option to check > > > > > > > > > > > > for. > > > > > > > > > > > > > > > > > > > > > > Thank you for reviewing the patch and pointing this out. > > > > > > > > > > > I wasn't aware of it. I > > > > > > > > > > > assume that you are referring to the following change: > > > > > > > > > > > > > > > > > > > > > > if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || > > > > > > > > > > > CONFIG_IS_ENABLED(HANDOFF) || > > > > > > > > > > > - IS_ENABLED(CONFIG_SPL_ATF)) > > > > > > > > > > > + IS_ENABLED(CONFIG_SPL_ATF) || > > > > > > > > > > > IS_ENABLED(CONFIG_SPL_NET)) > > > > > > > > > > > dram_init_banksize(); > > > > > > > > > > > > > > > > > > > > > > I shall replace the current patch with the above change > > > > > > > > > > > in the v2 series. Since > > > > > > > > > > > this is in the common section, is there a generic reason > > > > > > > > > > > I could provide in the > > > > > > > > > > > commit message rather than the existing commit message > > > > > > > > > > > which seems to be board > > > > > > > > > > > specific? Also, I hope that the above change will not > > > > > > > > > > > cause regressions for > > > > > > > > > > > other non-TI devices. Please let me know. > > > > > > > > > > > > > > > > > > > > Yes, that's the area, and just note that networking also > > > > > > > > > > requires the > > > > > > > > > > DDR to be initialized. > > > > > > > > > > > > > > > > > > > > > > > > > > > > Thank you for confirming and providing your suggestion for > > > > > > > > > the contents of the > > > > > > > > > commit message. > > > > > > > > > > > > > > > > > Following Tom's Suggestion of adding CONFIG_SPL_NET in > > > > > > > > common/spl/spl.c > > > > > > > > "dram_init_banksize()", the issue of fetching a file at SPL > > > > > > > > stage seemed > > > > > > > > to be fixed. However the commit "ba20b2443c29", which sets > > > > > > > > gd->ram_top > > > > > > > > for the very first time in "spl_enable_cache()" results in > > > > > > > > "arch_lmb_reserve()" function reserving memory region from > > > > > > > > Stack pointer > > > > > > > > at "0x81FFB820" to gd->ram_top pointing to "0x1". > > > > > > > > Previously > > > > > > > > when gd->ram_top was zero "arch_lmb_reserve()" was noop. Now > > > > > > > > using TFTP > > > > > > > > to fetch U-Boot image at SPL stage results in > > > > > > > > "tftp_init_load_addr()" > > > > > > > > function call that invokes "arch_lmb_reserve()" function, which > > > > > > > > reserves > > > > > > > > entire memory starting from Stack Pointer to gd->ram_top > > > > > > > > leaving no > > > > > > > > space to load U-Boot image via TFTP since TFTP loads files at > > > > > > > > pre > > > > > > > > configured memory address at "0x8200". > > > > > > > > > > > > > > > > As a workaround for this issue, one solution we can propose is > > > > > > > > to > > > > > > > > disable the checks "lmb_get_free_size()" at SPL and U-Boot > > > > > > > > stage. For > > > > > > > > that we can define a new config option for LMB reserve checks as > > > > > > > > "SPL_LMB". This config will be enable by default for the > > > > > > > > backword > > > > > > > > compatibility and disable for our use case at SPL and U-Boot > > > > > > > > stage. > > > > > > > > > > > > > > The problem here is that we need LMB for booting an OS, which is > > > > > > > something we'll want in SPL in non-cortex-R cases too, which > > > > > > > means this > > > > > > > platform, so that's a no-go. I think you need to dig harder and > > > > > > > see if > > > > > > > you can correct the logic somewhere so that we don't over reserve? > > > > > > > > > > > > > Since this issue is due to function call "lmb_init_and_reserve()" > > > > > > function
Re: [PATCH v1] tee: sandbox: check for buffer size
On Sun, Apr 21, 2024 at 11:48 PM Igor Opaniuk wrote:
>
> Add additional check for buffer size when reading out persistent
> storage value and provide back actual value size.
>
> Signed-off-by: Igor Opaniuk
Reviewed-by: Oleksandr Suvorov
> ---
>
> drivers/tee/sandbox.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/tee/sandbox.c b/drivers/tee/sandbox.c
> index 8ad7c09efdd..86b16a3bb8d 100644
> --- a/drivers/tee/sandbox.c
> +++ b/drivers/tee/sandbox.c
> @@ -174,7 +174,7 @@ static u32 ta_avb_invoke_func(struct udevice *dev, u32
> func, uint num_params,
> uint slot;
> u64 val;
> char *value;
> - u32 value_sz;
> + u32 value_sz, tmp_sz;
>
> switch (func) {
> case TA_AVB_CMD_READ_ROLLBACK_INDEX:
> @@ -267,8 +267,12 @@ static u32 ta_avb_invoke_func(struct udevice *dev, u32
> func, uint num_params,
> if (!ep)
> return TEE_ERROR_ITEM_NOT_FOUND;
>
> - value_sz = strlen(ep->data) + 1;
> - memcpy(value, ep->data, value_sz);
> + tmp_sz = strlen(ep->data) + 1;
> + if (value_sz < tmp_sz)
> + return TEE_ERROR_SHORT_BUFFER;
> +
> + memcpy(value, ep->data, tmp_sz);
> + params[1].u.memref.size = tmp_sz;
>
> return TEE_SUCCESS;
> case TA_AVB_CMD_WRITE_PERSIST_VALUE:
> --
> 2.34.1
>
--
Best regards,
Oleksandr Suvorov
Software Engineer
T: +380 63 8489656
E: oleksandr.suvo...@foundries.io
W: www.foundries.io
Re: [Uboot-stm32] [PATCH] stm32mp: Reserve OPTEE area in EFI memory map
On 4/19/24 09:44, Patrice CHOTARD wrote:
>
>
> On 4/17/24 09:45, Heinrich Schuchardt wrote:
>> On 17.04.24 09:25, Patrick DELAUNAY wrote:
>>> Hi,
>>>
>>> On 3/8/24 11:12, Patrice Chotard wrote:
Since commit 7b78d6438a2b3 ("efi_loader: Reserve unaccessible memory")
memory region above ram_top is tagged in EFI memory map as
EFI_BOOT_SERVICES_DATA.
In case of STM32MP1 platform, above ram_top, there is one reserved-memory
region tagged "no-map" dedicated to OP-TEE (addr=de00 size=200).
Before booting kernel, EFI memory map is first built, the OPTEE region is
tagged as EFI_BOOT_SERVICES_DATA and when reserving LMB, the tag LMB_NONE
is used.
Then after, the LMB are completed by boot_fdt_add_mem_rsv_regions()
which try to add again the same OPTEE region (addr=de00 size=200)
but now with LMB_NOMAP tag which produces the following error message :
"ERROR: reserving fdt memory region failed (addr=de00 size=200
flags=4)"
To avoid this, OPTEE area shouldn't be used by EFI, so we need to mark
it as reserved.
Signed-off-by: Patrice Chotard
---
arch/arm/mach-stm32mp/dram_init.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-stm32mp/dram_init.c
b/arch/arm/mach-stm32mp/dram_init.c
index fb1208fc5d5..f67f54f2ae0 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -7,6 +7,7 @@
#include
#include
+#include
#include
#include
#include
@@ -75,3 +76,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t
total_size)
return reg + size;
}
+
+void efi_add_known_memory(void)
+{
+ if (IS_ENABLED(CONFIG_EFI_LOADER))
+ /*
+ * Memory over ram_top is reserved to OPTEE.
+ * Declare to EFI only memory area below ram_top
+ */
+ efi_add_memory_map(gd->ram_base, gd->ram_top - gd->ram_base,
+ EFI_CONVENTIONAL_MEMORY);
>>
>> With this change the EFI memory map passed to the operating system will
>> not contain any memory above gd->ram_top. Is this really your intent?
>> Don't you have any memory above 0xe000?
>
> Hi Heinrich
>
> On stm32mp157x-dk and stm32mp135x-dk boards, there is no memory above
> 0xe000.
> But, on stm32mp157x-ed1 or stm32mp157x-ev1, you are right, we got memory
> above 0xe000.
>
> I will rework this patch to take into account memory that could be present
> above OPTEE area.
After double checking, this patch is correct but i need to update the commit
message.
In fact for stm32mp157x-dk and stm32mp135x-dk boards, there is 512MB of memory
(0xc000 0x2000),
OPTEE is located at the end of memory : 0xde00 0x0200
But for stm32mp157c-ev1, there is 1GB of memory (0xC000 0x4000), and
identically,
OPTEE is located at the end of memory : 0xfe00 0x200
So in both cases, above OPTEE reserved-memory area, there is no more free
memory.
Thanks
Patrice
>
> Thanks for pointing this
> Patrice
>
>>
>> Best regards
>>
>> Heinrich
>>
+}
>>>
>>>
>>>
>>> Reviewed-by: Patrick Delaunay
>>>
>>> Thanks
>>> Patrick
>>>
>>
> ___
> Uboot-stm32 mailing list
> uboot-st...@st-md-mailman.stormreply.com
> https://st-md-mailman.stormreply.com/mailman/listinfo/uboot-stm32
[PATCH v2 3/3] net: eth-uclass: Add driver source possibility
Some net driver, like rtl8169, can set/get the MAC address from the
registers and store it in pdata->enetaddr.
When that happens, if there is a mismatch with the environment MAC
address, u-boot will show that the MAC address source is DT. This patch
ensures that the shown source is "driver" instead to avoid confusion.
Signed-off-by: Detlev Casanova
---
net/eth-uclass.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 682de3ec7bd..3caf03eaef6 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -559,9 +559,13 @@ static int eth_post_probe(struct udevice *dev)
priv->state = ETH_STATE_INIT;
priv->running = false;
+ /* Check if the driver has already set a valid MAC address */
+ if (is_valid_ethaddr(pdata->enetaddr)) {
+ source = "driver";
+ }
/* Check if the device has a valid MAC address in device tree */
- if (!eth_dev_get_mac_address(dev, pdata->enetaddr) ||
- !is_valid_ethaddr(pdata->enetaddr)) {
+ else if (!eth_dev_get_mac_address(dev, pdata->enetaddr) ||
+!is_valid_ethaddr(pdata->enetaddr)) {
/* Check if the device has a MAC address in ROM */
if (eth_get_ops(dev)->read_rom_hwaddr) {
int ret;
--
2.43.2
[PATCH v2 2/3] configs/rock5b: Set NET_PREFER_ROM_MAC_ADDR to y
--- configs/rock5b-rk3588_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 58c7c44fb4f..4cd4d369561 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -106,3 +106,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x350b CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_ERRNO_STR=y +CONFIG_NET_PREFER_ROM_MAC_ADDR=y -- 2.43.2
[PATCH v2 1/3] net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR
On some boards, a MAC address is set based on the CPU ID or other
information. This is usually done in the misc_init_r() function.
This becomes a problem for net devices that are probed after the call to
misc_init_r(), for example, when the ethernet is on a PCI port, which
needs to be enumerated.
In this case, misc_init_r() will set the ethaddr variable, then, when
the ethernet device is probed, if it has a ROM address, u-boot will warn
about a MAC address mismatch and use the misc_init_r() address instead
of the one in ROM.
The operating system later will most likely use the ROM MAC address,
which can be confusing.
To avoid that, this commit introduces NET_PREFER_ROM_MAC_ADDR that can
be set for boards that have such an interface.
Signed-off-by: Detlev Casanova
---
net/Kconfig | 7 +++
net/eth-uclass.c | 9 +++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/net/Kconfig b/net/Kconfig
index 5dff6336293..1797c2cea35 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -227,6 +227,13 @@ config SERVERIP
string "Value of the default 'serverip' value in the environment"
depends on USE_SERVERIP
+config NET_PREFER_ROM_MAC_ADDR
+ bool "Prefer using HW MAC address if environment address differs"
+ default n
+ help
+ In case of a MAC address mismatch between the environment and the HW,
+ prefer using the HW address.
+
config PROT_TCP
bool "TCP stack"
help
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 3d0ec91dfa4..682de3ec7bd 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -584,8 +584,13 @@ static int eth_post_probe(struct udevice *dev)
env_enetaddr);
}
- /* Override the ROM MAC address */
- memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN);
+ if (!IS_ENABLED(CONFIG_NET_PREFER_ROM_MAC_ADDR)) {
+ /* Override the ROM MAC address */
+ printf("Using address in environment\n");
+ memcpy(pdata->enetaddr, env_enetaddr, ARP_HLEN);
+ } else {
+ printf("Using address in %s\n", source);
+ }
} else if (is_valid_ethaddr(pdata->enetaddr)) {
eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
pdata->enetaddr);
--
2.43.2
[PATCH v2 0/3] Introduce NET_PREFER_ROM_MAC_ADDR config
When there is a MAC address mismatch between ROM and environment, u-boot chooses the one from the environment. This config allows to prefer the MAC address from the ROM instead of the environment. See the first commit message for details. Changes since v1: - Simplify implementation with a NET_PREFER_ROM_MAC_ADDR config Detlev Casanova (3): net: eth-uclass: Introduce NET_PREFER_ROM_MAC_ADDR configs/rock5b: Set NET_PREFER_ROM_MAC_ADDR to y net: eth-uclass: Add driver source possibility configs/rock5b-rk3588_defconfig | 1 + net/Kconfig | 7 +++ net/eth-uclass.c| 17 + 3 files changed, 21 insertions(+), 4 deletions(-) -- 2.43.2
[PATCH 1/1] cmd: CONFIG_CMD_BLOBLIST must depend on CONFIG_BLOBLIST
With CONFIG_CMD_BLOBLIST=y, CONFIG_BLOBLIST=n linker errors occur:
usr/bin/ld: cmd/bloblist.o: in function `do_bloblist_list':
cmd/bloblist.c:27:(.text.do_bloblist_list+0x6):
undefined reference to `bloblist_show_list'
/usr/bin/ld: cmd/bloblist.o: in function `do_bloblist_info':
cmd/bloblist.c:19:(.text.do_bloblist_info+0x6):
undefined reference to `bloblist_show_stats'
Fixes: 4aed22762303 ("bloblist: Add a command")
Signed-off-by: Heinrich Schuchardt
---
cmd/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 42757e0cdf1..2386391daf1 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -741,7 +741,8 @@ config CMD_BINOP
config CMD_BLOBLIST
bool "bloblist"
- default y if BLOBLIST
+ depends on BLOBLIST
+ default y
help
Show information about the bloblist, a collection of binary blobs
held in memory that persist between SPL and U-Boot. In the case of
--
2.43.0
[PATCH v1 0/3] riscv: Rename spl_soc_init() to spl_dram_init()
From: Lukas Funke This patch series renames spl_soc_init() to spl_dram_init() since the purpose of the function is to initialization the DRAM on sifive/starfive boards. spl_dram_init() is a commonly used function for this purpose. Lukas Funke (3): arch: riscv: Rename spl_soc_init() to spl_dram_init() board: sifive: Call spl_dram_init() for DRAM initialization board: starfive: Call spl_dram_init() for DRAM initialization arch/riscv/cpu/fu540/spl.c | 2 +- arch/riscv/cpu/fu740/spl.c | 2 +- arch/riscv/cpu/jh7110/spl.c | 2 +- arch/riscv/include/asm/arch-fu540/spl.h | 2 +- arch/riscv/include/asm/arch-fu740/spl.h | 2 +- arch/riscv/include/asm/arch-jh7110/spl.h | 2 +- board/sifive/unleashed/spl.c | 4 ++-- board/sifive/unmatched/spl.c | 4 ++-- board/starfive/visionfive2/spl.c | 4 ++-- 9 files changed, 12 insertions(+), 12 deletions(-) -- 2.30.2
[PATCH v1 2/3] board: sifive: Call spl_dram_init() for DRAM initialization
From: Lukas Funke
Call spl_dram_init() since this is commonly used for dram initialization
in u-boot.
Signed-off-by: Lukas Funke
---
board/sifive/unleashed/spl.c | 4 ++--
board/sifive/unmatched/spl.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/sifive/unleashed/spl.c b/board/sifive/unleashed/spl.c
index fe27316b2d..d6725a0e0e 100644
--- a/board/sifive/unleashed/spl.c
+++ b/board/sifive/unleashed/spl.c
@@ -27,9 +27,9 @@ int spl_board_init_f(void)
{
int ret;
- ret = spl_soc_init();
+ ret = spl_dram_init();
if (ret) {
- debug("FU540 SPL init failed: %d\n", ret);
+ debug("FU540 dram init failed: %d\n", ret);
return ret;
}
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
index e69bed9d99..500f484844 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -134,9 +134,9 @@ int spl_board_init_f(void)
{
int ret;
- ret = spl_soc_init();
+ ret = spl_dram_init();
if (ret) {
- debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
+ debug("HiFive Unmatched FU740 dram init failed: %d\n", ret);
goto end;
}
--
2.30.2
[PATCH v1 3/3] board: starfive: Call spl_dram_init() for DRAM initialization
From: Lukas Funke
Call spl_dram_init() since this is commonly used for dram initialization
in u-boot.
Signed-off-by: Lukas Funke
---
board/starfive/visionfive2/spl.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index 45848db6d8..d1db7ee87b 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -285,9 +285,9 @@ int spl_board_init_f(void)
jh7110_jtag_init();
- ret = spl_soc_init();
+ ret = spl_dram_init();
if (ret) {
- debug("JH7110 SPL init failed: %d\n", ret);
+ debug("JH7110 dram init failed: %d\n", ret);
return ret;
}
--
2.30.2
[PATCH v1 1/3] arch: riscv: Rename spl_soc_init() to spl_dram_init()
From: Lukas Funke
Rename spl_soc_init() to spl_dram_init() because the generic function
name does not reflect what the function is actually doing. In addition
spl_dram_init() is commonly used for dram initialization and should
be called from board_init_f().
Signed-off-by: Lukas Funke
---
arch/riscv/cpu/fu540/spl.c | 2 +-
arch/riscv/cpu/fu740/spl.c | 2 +-
arch/riscv/cpu/jh7110/spl.c | 2 +-
arch/riscv/include/asm/arch-fu540/spl.h | 2 +-
arch/riscv/include/asm/arch-fu740/spl.h | 2 +-
arch/riscv/include/asm/arch-jh7110/spl.h | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c
index 45657b7909..cedb70b66a 100644
--- a/arch/riscv/cpu/fu540/spl.c
+++ b/arch/riscv/cpu/fu540/spl.c
@@ -7,7 +7,7 @@
#include
#include
-int spl_soc_init(void)
+int spl_dram_init(void)
{
int ret;
struct udevice *dev;
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
index c6816e9ed4..16b307f036 100644
--- a/arch/riscv/cpu/fu740/spl.c
+++ b/arch/riscv/cpu/fu740/spl.c
@@ -10,7 +10,7 @@
#define CSR_U74_FEATURE_DISABLE0x7c1
-int spl_soc_init(void)
+int spl_dram_init(void)
{
int ret;
struct udevice *dev;
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 6bdf8b9c72..87aaf86524 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -28,7 +28,7 @@ static bool check_ddr_size(phys_size_t size)
}
}
-int spl_soc_init(void)
+int spl_dram_init(void)
{
int ret;
struct udevice *dev;
diff --git a/arch/riscv/include/asm/arch-fu540/spl.h
b/arch/riscv/include/asm/arch-fu540/spl.h
index 4697279f43..519e7eb210 100644
--- a/arch/riscv/include/asm/arch-fu540/spl.h
+++ b/arch/riscv/include/asm/arch-fu540/spl.h
@@ -9,6 +9,6 @@
#ifndef _SPL_SIFIVE_H
#define _SPL_SIFIVE_H
-int spl_soc_init(void);
+int spl_dram_init(void);
#endif /* _SPL_SIFIVE_H */
diff --git a/arch/riscv/include/asm/arch-fu740/spl.h
b/arch/riscv/include/asm/arch-fu740/spl.h
index 15ad9e7c8b..b327ac5036 100644
--- a/arch/riscv/include/asm/arch-fu740/spl.h
+++ b/arch/riscv/include/asm/arch-fu740/spl.h
@@ -9,6 +9,6 @@
#ifndef _SPL_SIFIVE_H
#define _SPL_SIFIVE_H
-int spl_soc_init(void);
+int spl_dram_init(void);
#endif /* _SPL_SIFIVE_H */
diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h
b/arch/riscv/include/asm/arch-jh7110/spl.h
index 23ce8871b3..d73355bf35 100644
--- a/arch/riscv/include/asm/arch-jh7110/spl.h
+++ b/arch/riscv/include/asm/arch-jh7110/spl.h
@@ -7,6 +7,6 @@
#ifndef _SPL_STARFIVE_H
#define _SPL_STARFIVE_H
-int spl_soc_init(void);
+int spl_dram_init(void);
#endif /* _SPL_STARFIVE_H */
--
2.30.2
BTRFS use-after-free bug at free_extent_buffer_internal
Hi,
I've hit a bug with u-boot on my BTRFS filesystem, and I'm fairly certain
it's a bug and not a corruption issue.
A bit of history on the filesystem. It is a fairly new filesystem as it was
being used to give me access to test a wayland application on a
Raspberry Pi. The filesystem was about 3 days old when I hit the bug, and
I'm fairly certain it never had an unclean shutdown. I have checked the
filesystem with "btrfs check" which has found no errors. The filesystem
mounts on Linux and is functional.
> # btrfs check --check-data-csum /dev/sda2
> Opening filesystem to check...
> Checking filesystem on /dev/sda2
> UUID: 18db6211-ac36-42c1-a22f-5e15e1486e0d
> [1/7] checking root items
> [2/7] checking extents
> [3/7] checking free space tree
> [4/7] checking fs roots
> [5/7] checking csums against data
> [6/7] checking root refs
> [7/7] checking quota groups skipped (not enabled on this FS)
> found 5070573568 bytes used, no error found
> total csum bytes: 4451620
> total tree bytes: 370458624
> total fs tree bytes: 353124352
> total extent tree bytes: 10010624
> btree space waste bytes: 62303284
> file data blocks allocated: 6786519040
> referenced 6328619008
I've made an image of the filesystem so I could reproduce the bug in an
environment that doesn't require the physical SBC, and have reproduced
the issue using the head of the master branch with "qemu-x86_64_defconfig".
My testing qemu was produced with the following:
> # make qemu-x86_64_defconfig
> # cat << EOF >> .config
> CONFIG_AUTOBOOT=y
> CONFIG_BOOTDELAY=1
> CONFIG_USE_BOOTCOMMAND=y
> CONFIG_BOOTSTD_DEFAULTS=y
> CONFIG_BOOTSTD_FULL=y
> CONFIG_CMD_BOOTFLOW_FULL=y
> CONFIG_BOOTCOMMAND="bootflow scan -lb"
> CONFIG_ENV_IS_NOWHERE=y
> CONFIG_LZ4=y
> CONFIG_BZIP2=y
> CONFIG_ZSTD=y
> CONFIG_FS_BTRFS=y
> CONFIG_CMD_BTRFS=y
> CONFIG_GZIP=y
> CONFIG_DEVICE_TREE_INCLUDES="bootstd.dtsi"
> EOF
> # make -j24
bootstd.dtsi is placed at "arch/x86/dts/bootstd.dtsi" and contains:
> / {
> bootstd {
> compatible = "u-boot,boot-std";
> filename-prefixes = "/@boot/", "/boot/", "/";
> bootdev-order = "scsi";
> extlinux {
> compatible = "u-boot,extlinux";
> };
> };
> };
The VM was run with
> qemu-system-x86_64 -bios u-boot.rom -nographic -M q35 -action reboot=shutdown
> -drive file=/mnt/dbg/u-boot-debug.img
The error message I recive on boot is
> BUG at fs/btrfs/extent-io.c:629/free_extent_buffer_internal()!
> BUG!
> resetting ...
I added a print statement to free_extent_buffer_internal that prints the
start address of the extent_buffer as I'm not sure what to be looking for
here. This print statement is before the decrement.
> printf("free_extent_buffer_internal: eb->start[%llx] eb->refs[%i]\n",
> eb->start, eb->refs);
The last message before the crash reported eb->start to be "0", with 0 refs.
> free_extent_buffer_internal: eb->start[0] eb->refs[0]
The extent at 0 struck me as odd, so I tried commenting out the freeing, by
removing the call to free_extent_buffer_final, and this resulted in bootflow
succeeding and showing me the boot menu, which suprised me.
I expected to see the bug reproduce itself, with refs being zero, but eb->start
pointing somewhere valid, but I instead got a valid address with refs at 2.
I'm assuming that the order free_extent_buffer_internal is called is
deterministic, so by counting the print outputs the line that prior held
the extent_buffer with a 0 start was replaced with:
> free_extent_buffer_internal: eb->start[249c000] eb->refs[2]
Interestingly, as can be seen in the full logs with my included print
messages, 249c000 is being used just before this, with a ref count of
2. 249c000 does appear to reach a point where it should have been freed
in the past, before it gets used again as seen in both logs.
The failing boot log:
> U-Boot SPL 2024.04-00949-g1dd659fd62-dirty (Apr 22 2024 - 11:32:37 +1000)
> Trying to boot from SPI
> Jumping to 64-bit U-Boot: Note many features are missing
>
>
> U-Boot 2024.04-00949-g1dd659fd62-dirty (Apr 22 2024 - 11:32:37 +1000)
>
> CPU: QEMU Virtual CPU version 2.5+
> DRAM: 128 MiB
> Core: 13 devices, 13 uclasses, devicetree: separate
> Loading Environment from nowhere... OK
> Model: QEMU x86 (I440FX)
> Net: e1000: 00:00:00:00:00:00
>
> Error: e1000#0 No valid MAC address found.
> eth_initialize() No ethernet found.
>
>
> Hit any key to stop autoboot: 0
> Scanning for bootflows in all bootdevs
> Seq Method State UclassPart Name Filename
> --- --- --
>
> scanning bus for devices...
> Target spinup took 0 ms.
> SATA link 1 timeout.
> Target spinup took 0 ms.
> SATA link 3 timeout.
> SATA link 4 timeout.
> SATA link 5 timeout.
> AHCI 0001. 32 slots 6 ports 1.5 Gbps 0x3f impl SATA mode
> flags: 64bit ncq only
>
Re: [PATCH] usb: dwc2: update reset method for host and device mode
Marek Vasut 于2024年4月22日周一 04:45写道：
>
> On 3/28/24 2:14 PM, Kongyang Liu wrote:
>
> [...]
>
> > @@ -464,12 +464,26 @@ static void reconfig_usbd(struct dwc2_udc *dev)
> > {
> > /* 2. Soft-reset OTG Core and then unreset again. */
> > int i;
> > - unsigned int uTemp = writel(CORE_SOFT_RESET, >grstctl);
> > + unsigned int uTemp;
> > uint32_t dflt_gusbcfg;
> > uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz;
> > u32 max_hw_ep;
> > int pdata_hw_ep;
> >
>
> Drop this newline
>
I will fix it
> > + u32 snpsid, greset;
> > +
> > + snpsid = readl(>gsnpsid);
> > + writel(CORE_SOFT_RESET, >grstctl);
> > + if ((snpsid & SNPSID_VER_MASK) < (SNPSID_VER_420a & SNPSID_VER_MASK))
> > {
>
> Can you use FIELD_GET()/FIELD_PREP() for this ?
>
I will fix it
> > + wait_for_bit_le32(>grstctl, CORE_SOFT_RESET, false,
> > 1000, false);
> > + } else {
> > + wait_for_bit_le32(>grstctl, CORE_SOFT_RESET_DONE, true,
> > 1000, false);
> > + greset = readl(>grstctl);
> > + greset &= ~CORE_SOFT_RESET;
> > + greset |= CORE_SOFT_RESET_DONE;
> > + writel(greset, >grstctl);
>
> clrsetbits_le32()
>
I will fix it
> [...]
>
> > diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> > index 637eb2dd06..1baeff96ee 100644
> > --- a/drivers/usb/host/dwc2.c
> > +++ b/drivers/usb/host/dwc2.c
> > @@ -159,6 +159,7 @@ static void dwc_otg_core_reset(struct udevice *dev,
> > struct dwc2_core_regs *regs)
> > {
> > int ret;
> > + u32 snpsid, greset;
> >
> > /* Wait for AHB master IDLE state. */
> > ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_AHBIDLE,
> > @@ -167,9 +168,20 @@ static void dwc_otg_core_reset(struct udevice *dev,
> > dev_info(dev, "%s: Timeout!\n", __func__);
> >
> > /* Core Soft Reset */
> > + snpsid = readl(>gsnpsid);
> > writel(DWC2_GRSTCTL_CSFTRST, >grstctl);
> > - ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
> > - false, 1000, false);
> > + if ((snpsid & DWC2_SNPSID_VER_MASK) < (DWC2_SNPSID_DEVID_VER_420a &
> > DWC2_SNPSID_VER_MASK)) {
> > + ret = wait_for_bit_le32(>grstctl, DWC2_GRSTCTL_CSFTRST,
> > + false, 1000, false);
> > + } else {
> > + ret = wait_for_bit_le32(>grstctl,
> > DWC2_GRSTCTL_GSFTRST_DONE,
> > + true, 1000, false);
> > + greset = readl(>grstctl);
> > + greset &= ~DWC2_GRSTCTL_CSFTRST;
> > + greset |= DWC2_GRSTCTL_GSFTRST_DONE;
> > + writel(greset, >grstctl);
>
> Same comments as above.
>
> Maybe this should be pulled into dedicated function to avoid duplication?
>
For U-Boot, the dwc2 USB driver is split into two modules: host and gadget.
Each has its own register definitions and definitions for register bits,
which makes it difficult to extract a single function. Moreover, deciding
where to place this function is also an issue.
> > + }
> > +
> > if (ret)
> > dev_info(dev, "%s: Timeout!\n", __func__);
> >
> > @@ -1180,7 +1192,8 @@ static int dwc2_init_common(struct udevice *dev,
> > struct dwc2_priv *priv)
> >snpsid >> 12 & 0xf, snpsid & 0xfff);
> >
> > if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
> > - (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
> > + (snpsid & DWC2_SNPSID_DEVID_MASK) !=
> > DWC2_SNPSID_DEVID_VER_3xx &&
> > + (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_4xx) {
>
> Try FIELD_GET/FIELD_PREP
I will fix it
Best regards
Kongyang Liu
Please pull u-boot-tegra staging
Dear Tom, The following changes since commit 1dd659fd626204bb6a6b4f330c27b11a7823bbb0: Merge tag 'video-20240421' of https://source.denx.de/u-boot/custodians/u-boot-video (2024-04-21 08:54:20 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-tegra.git staging for you to fetch changes up to 6898cc823413ff01661e7db74ad764da58b682d9: board: tegra30: switch to button cmd (2024-04-22 12:17:21 +0300) Jonas Schwöbel (2): board: asus: lg_x3: endeavoru: remove CONFIG_SYS_L2CACHE_OFF ARM: tegra: Enable UART-E for T20 and T30 Svyatoslav Ryhel (12): ARM: dts: paz00: remove display-timings node ARM: tegra: move to standard boot board: tegra30: switch to standard boot board: asus: tf600t: configure SPI pinmux board: asus: tf600t: adjust LV pinmux board: asus: transformer-t30: set the correct pinmux lock and io-reset board: asus: tf600t: enable TEGRA20_SLINK only for TF600T board: asus: transformer-t30: enable I2C_MUX only for TF700T board: asus: tf700t: bind tc358768 bridge and panel ARM: tegra: grouper: bind Hall sensor ARM: tegra: transformer-t30: bind Hall sensor board: tegra30: switch to button cmd arch/arm/Kconfig | 2 +- arch/arm/dts/tegra20-paz00.dts| 16 arch/arm/dts/tegra30-asus-grouper-common.dtsi | 6 ++ arch/arm/dts/tegra30-asus-p1801-t.dts | 28 +++--- arch/arm/dts/tegra30-asus-tf600t.dts | 101 +++-- arch/arm/dts/tegra30-asus-tf700t.dts | 102 +- arch/arm/dts/tegra30-asus-transformer.dtsi| 36 +--- arch/arm/mach-tegra/Kconfig | 4 + board/asus/transformer-t30/configs/p1801-t.config | 1 + board/asus/transformer-t30/configs/tf201.config | 1 + board/asus/transformer-t30/configs/tf300t.config | 1 + board/asus/transformer-t30/configs/tf300tg.config | 1 + board/asus/transformer-t30/configs/tf300tl.config | 1 + board/asus/transformer-t30/configs/tf600t.config | 2 + board/asus/transformer-t30/configs/tf700t.config | 2 + configs/endeavoru_defconfig | 4 +- configs/grouper_common_defconfig | 4 +- configs/paz00_defconfig | 1 + configs/transformer_t30_defconfig | 5 +- configs/x3_t30_defconfig | 4 +- include/configs/endeavoru.h | 3 +- include/configs/grouper.h | 5 +- include/configs/tegra-common-post.h | 30 +-- include/configs/transformer-common.h | 12 +-- include/configs/x3-t30.h | 3 +- 25 files changed, 255 insertions(+), 120 deletions(-) Branch contains minor internal improvemets for endeavoru, lg_x3, grouper, transformers and paz00 as well as migration to standard boot. All commits passed U-Boot checks and buildman for tegra. Thanks, Svyatoslav Ryhel.
[PATCH v2 5/5] pinctrl: qcom: ipq4019: support all pin functions
Currently, IPQ4019 pinctrl driver supports only a very limited number of
pin functions and is not fully DT compatible with Linux pinctrl nodes.
IPQ40xx SoC-s sometimes use different pin function numbers for the same
function depending on the pin number, so for example I2C0 on GPIO58 uses
function number 3 while on GPIO59 it uses function number 2.
So, in order to make the driver compatible with upstream DTS to avoid the
need to patch the pinctrl nodes in U-Boot and support all of the missing
pin functions lets rework the driver based on upstream Linux IPQ4019
pinctrl driver and the pending SM8150 U-Boot pinctrl driver which also uses
different function numbers pased on the exact pin number.
Signed-off-by: Robert Marko
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 306 +++--
1 file changed, 293 insertions(+), 13 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 48644a51ae..26ab487857 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -14,19 +14,291 @@
#define MAX_PIN_NAME_LEN 32
static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+enum ipq4019_functions {
+ qca_mux_gpio,
+ qca_mux_aud_pin,
+ qca_mux_audio_pwm,
+ qca_mux_blsp_i2c0,
+ qca_mux_blsp_i2c1,
+ qca_mux_blsp_spi0,
+ qca_mux_blsp_spi1,
+ qca_mux_blsp_uart0,
+ qca_mux_blsp_uart1,
+ qca_mux_chip_rst,
+ qca_mux_i2s_rx,
+ qca_mux_i2s_spdif_in,
+ qca_mux_i2s_spdif_out,
+ qca_mux_i2s_td,
+ qca_mux_i2s_tx,
+ qca_mux_jtag,
+ qca_mux_led0,
+ qca_mux_led1,
+ qca_mux_led2,
+ qca_mux_led3,
+ qca_mux_led4,
+ qca_mux_led5,
+ qca_mux_led6,
+ qca_mux_led7,
+ qca_mux_led8,
+ qca_mux_led9,
+ qca_mux_led10,
+ qca_mux_led11,
+ qca_mux_mdc,
+ qca_mux_mdio,
+ qca_mux_pcie,
+ qca_mux_pmu,
+ qca_mux_prng_rosc,
+ qca_mux_qpic,
+ qca_mux_rgmii,
+ qca_mux_rmii,
+ qca_mux_sdio,
+ qca_mux_smart0,
+ qca_mux_smart1,
+ qca_mux_smart2,
+ qca_mux_smart3,
+ qca_mux_tm,
+ qca_mux_wifi0,
+ qca_mux_wifi1,
+ qca_mux_NA,
+};
+
+#define QCA_PIN_FUNCTION(fname)\
+ [qca_mux_##fname] = {#fname, qca_mux_##fname}
+
static const struct pinctrl_function msm_pinctrl_functions[] = {
- {"gpio", 0},
- {"blsp_uart0_0", 1}, /* Only for GPIO:16,17 */
- {"blsp_uart0_1", 2}, /* Only for GPIO:60,61 */
- {"blsp_uart1", 1},
- {"blsp_spi0_0", 1}, /* Only for GPIO:12,13,14,15 */
- {"blsp_spi0_1", 2}, /* Only for GPIO:54,55,56,57 */
- {"blsp_spi1", 2},
- {"mdio_0", 1}, /* Only for GPIO6 */
- {"mdio_1", 2}, /* Only for GPIO53 */
- {"mdc_0", 1}, /* Only for GPIO7 */
- {"mdc_1", 2}, /* Only for GPIO52 */
+ QCA_PIN_FUNCTION(aud_pin),
+ QCA_PIN_FUNCTION(audio_pwm),
+ QCA_PIN_FUNCTION(blsp_i2c0),
+ QCA_PIN_FUNCTION(blsp_i2c1),
+ QCA_PIN_FUNCTION(blsp_spi0),
+ QCA_PIN_FUNCTION(blsp_spi1),
+ QCA_PIN_FUNCTION(blsp_uart0),
+ QCA_PIN_FUNCTION(blsp_uart1),
+ QCA_PIN_FUNCTION(chip_rst),
+ QCA_PIN_FUNCTION(gpio),
+ QCA_PIN_FUNCTION(i2s_rx),
+ QCA_PIN_FUNCTION(i2s_spdif_in),
+ QCA_PIN_FUNCTION(i2s_spdif_out),
+ QCA_PIN_FUNCTION(i2s_td),
+ QCA_PIN_FUNCTION(i2s_tx),
+ QCA_PIN_FUNCTION(jtag),
+ QCA_PIN_FUNCTION(led0),
+ QCA_PIN_FUNCTION(led1),
+ QCA_PIN_FUNCTION(led2),
+ QCA_PIN_FUNCTION(led3),
+ QCA_PIN_FUNCTION(led4),
+ QCA_PIN_FUNCTION(led5),
+ QCA_PIN_FUNCTION(led6),
+ QCA_PIN_FUNCTION(led7),
+ QCA_PIN_FUNCTION(led8),
+ QCA_PIN_FUNCTION(led9),
+ QCA_PIN_FUNCTION(led10),
+ QCA_PIN_FUNCTION(led11),
+ QCA_PIN_FUNCTION(mdc),
+ QCA_PIN_FUNCTION(mdio),
+ QCA_PIN_FUNCTION(pcie),
+ QCA_PIN_FUNCTION(pmu),
+ QCA_PIN_FUNCTION(prng_rosc),
+ QCA_PIN_FUNCTION(qpic),
+ QCA_PIN_FUNCTION(rgmii),
+ QCA_PIN_FUNCTION(rmii),
+ QCA_PIN_FUNCTION(sdio),
+ QCA_PIN_FUNCTION(smart0),
+ QCA_PIN_FUNCTION(smart1),
+ QCA_PIN_FUNCTION(smart2),
+ QCA_PIN_FUNCTION(smart3),
+ QCA_PIN_FUNCTION(tm),
+ QCA_PIN_FUNCTION(wifi0),
+ QCA_PIN_FUNCTION(wifi1),
};
+
+typedef unsigned int msm_pin_function[15];
+
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13,
f14) \
+ [id] = {qca_mux_gpio, /* gpio mode */ \
+ qca_mux_##f1, \
+ qca_mux_##f2, \
+ qca_mux_##f3, \
+ qca_mux_##f4, \
+ qca_mux_##f5, \
+ qca_mux_##f6, \
+
[PATCH v2 4/5] pinctrl: qcom: ipq4019: enable DM_FLAG_PRE_RELOC
If compiled with logging and debug UART support, the following is printed:
serial_msm serial@78af000: pinctrl_select_state_full:
uclass_get_device_by_phandle_id: err=-19
This is due to the fact that IPQ4019 pinctrl driver is not available prior
to relocation and thus MSM serial will fail probing as pinctrl provider is
not available.
So, lets enable DM_FLAG_PRE_RELOC for IPQ4019 pinctrl to fix this.
Signed-off-by: Robert Marko
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 4fcc4b1810..48644a51ae 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -68,4 +68,5 @@ U_BOOT_DRIVER(pinctrl_ipq4019) = {
.of_match = msm_pinctrl_ids,
.ops= _pinctrl_ops,
.bind = msm_pinctrl_bind,
+ .flags = DM_FLAG_PRE_RELOC,
};
--
2.44.0
[PATCH v2 3/5] pinctrl: qcom: ipq4019: adapt pin name lookup to upstream DTS
We want to use OF_UPSTREAM on IPQ40XX as its well supported upstream, so
as a preparation update pinctrl driver to look for the upstream pin format.
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
drivers/pinctrl/qcom/pinctrl-ipq4019.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
index 4479230313..4fcc4b1810 100644
--- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
+++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
@@ -36,7 +36,7 @@ static const char *ipq4019_get_function_name(struct udevice
*dev,
static const char *ipq4019_get_pin_name(struct udevice *dev,
unsigned int selector)
{
- snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+ snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
return pin_name;
}
--
2.44.0
[PATCH v2 2/5] mach-ipq40xx: import GPIO header from mach-snapgradon
Pinctrl driver was refactored and moved, but the required header that
it depends on was not included.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko
---
arch/arm/mach-ipq40xx/include/mach/gpio.h | 37 +++
1 file changed, 31 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-ipq40xx/include/mach/gpio.h
b/arch/arm/mach-ipq40xx/include/mach/gpio.h
index a45747c0fe..53c6ae0649 100644
--- a/arch/arm/mach-ipq40xx/include/mach/gpio.h
+++ b/arch/arm/mach-ipq40xx/include/mach/gpio.h
@@ -1,10 +1,35 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Empty gpio.h
+ * Qualcomm common pin control data.
*
- * This file must stay as arch/arm/include/asm/gpio.h requires it.
- *
- * Copyright (c) 2019 Sartura Ltd.
- *
- * Author: Robert Marko
+ * Copyright (C) 2023 Linaro Ltd.
*/
+#ifndef _QCOM_GPIO_H_
+#define _QCOM_GPIO_H_
+
+#include
+#include
+
+struct msm_pin_data {
+ int pin_count;
+ const unsigned int *pin_offsets;
+ /* Index of first special pin, these are ignored for now */
+ unsigned int special_pins_start;
+};
+
+static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int
selector)
+{
+ u32 out = (selector * 0x1000);
+
+ if (offs)
+ return out + offs[selector];
+
+ return out;
+}
+
+static inline bool qcom_is_special_pin(const struct msm_pin_data *pindata,
unsigned int pin)
+{
+ return pindata->special_pins_start && pin >=
pindata->special_pins_start;
+}
+
+#endif /* _QCOM_GPIO_H_ */
--
2.44.0
[PATCH v2 1/5] pinctrl: qcom: allow selecting with ARCH_IPQ40XX
IPQ4019 pinctrl driver was moved to the dedicated Qualcomm pinctrl
directory, but the KConfig depends on ARCH_SNAPDRAGON only and thus
PINCTRL_QCOM_IPQ4019 cannot be selected when ARCH_IPQ40XX is used.
Fixes: 24d2908e987a ("pinctrl: qcom: move ipq4019 driver from mach-ipq40xx")
Signed-off-by: Robert Marko
Reviewed-by: Caleb Connolly
---
drivers/pinctrl/qcom/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 2fe6398147..bd2019c866 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -1,4 +1,4 @@
-if ARCH_SNAPDRAGON
+if ARCH_SNAPDRAGON || ARCH_IPQ40XX
config PINCTRL_QCOM
depends on PINCTRL_GENERIC
--
2.44.0
Re: [PATCH] clk: imx8mn: add video clocks support
Hi Michael, On Mon, Apr 22, 2024 at 7:36 AM Michael Nazzareno Trimarchi wrote: > Are you considering if I wrap properly with VIDEO IS_ENABLED? I prefer you resend this patch as part of a complete series that adds panel support to an imx8mn board target. Otherwise, if this gets in as-is, it will become a dead code, which we want to avoid.
Re: [PATCH 01/10] board: ti: am62x: Init DRAM size in R5/A53 SPL
On 17/04/24 21:34, Tom Rini wrote: On Wed, Apr 17, 2024 at 05:48:31PM +0530, Sughosh Ganu wrote: hi Chintan, On Wed, 17 Apr 2024 at 13:21, Chintan Vankar wrote: On 16/04/24 22:30, Tom Rini wrote: On Tue, Apr 16, 2024 at 05:52:58PM +0530, Chintan Vankar wrote: On 12/04/24 03:37, Tom Rini wrote: On Wed, Apr 03, 2024 at 06:18:01PM +0530, Chintan Vankar wrote: On 22/01/24 10:11, Siddharth Vadapalli wrote: On 20/01/24 22:11, Tom Rini wrote: On Mon, Jan 15, 2024 at 01:42:51PM +0530, Siddharth Vadapalli wrote: Hello Tom, On 12/01/24 18:56, Tom Rini wrote: ... The list of conditionals in common/spl/spl.c::board_init_r() should be updated and probably use SPL_NET as the option to check for. Thank you for reviewing the patch and pointing this out. I wasn't aware of it. I assume that you are referring to the following change: if (IS_ENABLED(CONFIG_SPL_OS_BOOT) || CONFIG_IS_ENABLED(HANDOFF) || - IS_ENABLED(CONFIG_SPL_ATF)) + IS_ENABLED(CONFIG_SPL_ATF) || IS_ENABLED(CONFIG_SPL_NET)) dram_init_banksize(); I shall replace the current patch with the above change in the v2 series. Since this is in the common section, is there a generic reason I could provide in the commit message rather than the existing commit message which seems to be board specific? Also, I hope that the above change will not cause regressions for other non-TI devices. Please let me know. Yes, that's the area, and just note that networking also requires the DDR to be initialized. Thank you for confirming and providing your suggestion for the contents of the commit message. Following Tom's Suggestion of adding CONFIG_SPL_NET in common/spl/spl.c "dram_init_banksize()", the issue of fetching a file at SPL stage seemed to be fixed. However the commit "ba20b2443c29", which sets gd->ram_top for the very first time in "spl_enable_cache()" results in "arch_lmb_reserve()" function reserving memory region from Stack pointer at "0x81FFB820" to gd->ram_top pointing to "0x1". Previously when gd->ram_top was zero "arch_lmb_reserve()" was noop. Now using TFTP to fetch U-Boot image at SPL stage results in "tftp_init_load_addr()" function call that invokes "arch_lmb_reserve()" function, which reserves entire memory starting from Stack Pointer to gd->ram_top leaving no space to load U-Boot image via TFTP since TFTP loads files at pre configured memory address at "0x8200". As a workaround for this issue, one solution we can propose is to disable the checks "lmb_get_free_size()" at SPL and U-Boot stage. For that we can define a new config option for LMB reserve checks as "SPL_LMB". This config will be enable by default for the backword compatibility and disable for our use case at SPL and U-Boot stage. The problem here is that we need LMB for booting an OS, which is something we'll want in SPL in non-cortex-R cases too, which means this platform, so that's a no-go. I think you need to dig harder and see if you can correct the logic somewhere so that we don't over reserve? Since this issue is due to function call "lmb_init_and_reserve()" function invoked from "tftp_init_load_addr()" function. This function is defined by Simon in commit "a156c47e39ad", which fixes "CVE-2018-18439" to prevent overwriting reserved memory. Simon, can you explain why do we need to call "lmb_init_and_reserve()" function here ? This is indeed a tricky area which is why Sughosh is looking in to trying to re-work the LMB mechanic and we've had a few long threads about it as well. I've honestly forgotten the use case you have here, can you please remind us? We are trying to boot AM62x using Ethernet for which we need to load binary files at SPL and U-Boot stage using TFTP. To store the file we need a free memory in RAM, specifically we are storing these files at 0x8200. But we are facing an issue while loading the file since the memory area having an address 0x8200 is reserved due to "lmb_init_and_reserve()" function call. This function is called in "tftp_init_load_addr()" function which is getting called exactly before we are trying to get the free memory area by calling "lmb_get_free_size()". I have no idea about your platform but I was wondering if there is any particular importance of the load address of 0x8200? It looks as though the current location of the SP when arch_lmb_reserve() gets called means that the load address is getting reserved for the U-Boot image. Do you not have the option of loading the image at a lower address instead? Or using a higher address for SPL stack? You might be able to solve this just by re-examining which addresses (and RAM size limitations) need to be considered here. Tom, We changed SPL_STACK_R_ADDR to higher address as you suggested here and observe that the memory area which was getting reserved by "lmb_init_and_reserve()" function, when SPL_STACK_R_ADDR was 0x8200, is from 0x81FFB820 to gd->ram_top, but when
Re: [PATCH] usb: dwc3: support USB 3.1 controllers
On 21/04/2024 22:38, Marek Vasut wrote:
On 4/11/24 6:05 PM, Caleb Connolly wrote:
The revision is different for these, add the additional check as in
xhci-dwc3 core_init code.
Signed-off-by: Caleb Connolly
Is there a matching Linux kernel patch , or does Linux do some other
check ?
I just took this change from the xhci-dwc3 driver tbh... But I did some
archeology and it seems the associated Linux patch would be 690fb3718a70
("usb: dwc3: Support Synopsys USB 3.1 IP").
--
// Caleb (they/them)
Re: [PATCH] clk: imx8mn: add video clocks support
Hi Fabio On Sun, Apr 21, 2024 at 10:54 PM Michael Nazzareno Trimarchi wrote: > > Hi Fabio > > On Sun, Apr 21, 2024 at 10:24 PM Fabio Estevam wrote: > > > > Hi Michael, > > > > On Sun, Apr 21, 2024 at 11:07 AM Michael Trimarchi > > wrote: > > > > > > Add clocks support for the video subsystem. > > > > > > Signed-off-by: Michael Trimarchi > > > > Which target will make use of these clocks? > > > > As-is this patch adds only dead code. > > > > Adding a defconfig that uses these newly introduced clocks would be nice. > > > > You are right, I will wrap it and enable only on CONFIG_VIDEO > > > Also, to avoid size increase, please protect this code against > > CONFIG_VIDEO or something, like done here: > > https://source.denx.de/u-boot/custodians/u-boot-imx/-/commit/2b3310ef13998dfd03196a0806e03035212b102c > > Working on display panel integration on imx8m, trying to progress > merging things up. > Are you considering if I wrap properly with VIDEO IS_ENABLED? Michael > Michael > > > > -- > Michael Nazzareno Trimarchi > Co-Founder & Chief Executive Officer > M. +39 347 913 2170 > mich...@amarulasolutions.com > __ > > Amarula Solutions BV > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL > T. +31 (0)85 111 9172 > i...@amarulasolutions.com > www.amarulasolutions.com -- Michael Nazzareno Trimarchi Co-Founder & Chief Executive Officer M. +39 347 913 2170 mich...@amarulasolutions.com __ Amarula Solutions BV Joop Geesinkweg 125, 1114 AB, Amsterdam, NL T. +31 (0)85 111 9172 i...@amarulasolutions.com www.amarulasolutions.com
Re: [PATCH] efi_loader: do not install dtb if bootmgr fails
On Mon, 22 Apr 2024 at 12:16, Heinrich Schuchardt
wrote:
>
> If the UEFI boot manager fails, there is no point in installing the
> device-tree as a configuration table.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> lib/efi_loader/efi_bootmgr.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
> index c64cbe82402..2b0d3137338 100644
> --- a/lib/efi_loader/efi_bootmgr.c
> +++ b/lib/efi_loader/efi_bootmgr.c
> @@ -1209,15 +1209,15 @@ efi_status_t efi_bootmgr_run(void *fdt)
> return CMD_RET_FAILURE;
> }
>
> - ret = efi_install_fdt(fdt);
> - if (ret != EFI_SUCCESS)
> - return ret;
> -
> ret = efi_bootmgr_load(, _options);
> if (ret != EFI_SUCCESS) {
> log_notice("EFI boot manager: Cannot load any image\n");
> return ret;
> }
>
> + ret = efi_install_fdt(fdt);
> + if (ret != EFI_SUCCESS)
> + return ret;
> +
> return do_bootefi_exec(handle, load_options);
> }
> --
> 2.43.0
>
Reviewed-by: Ilias Apalodimas
Re: [PATCH 0/3] qcom: switch to OF_UPSTREAM
On Thu, 18 Apr 2024 at 10:24, Caleb Connolly wrote: > > This series does the initial switch to OF_UPSTREAM for Qualcomm > platforms. The DT files we have in U-Boot are outdated by now, so drop > them and move to upstream. > > Patch 2 drops all the Qualcomm dts files that are now provided in > dts/upstream. As some of the files exceed the 100k size limit by > themselves I thought it would be easier to just lump them together > rather than trying to split them up. > > The associated qcom headers will be cleaned up in future patches. > > --- > Caleb Connolly (3): > mach-snapdragon: use OF_UPSTREAM > arm: dts: drop qcom dts files > qcom_defconfig: set SYS_INIT_SP_BSS_OFFSET > Reviewed-by: Sumit Garg -Sumit > MAINTAINERS |4 - > arch/arm/Kconfig|1 + > arch/arm/dts/apq8016-sbc.dts| 729 > arch/arm/dts/apq8096-db820c.dts | 1137 -- > arch/arm/dts/msm8916-pm8916.dtsi| 157 - > arch/arm/dts/msm8916.dtsi | 2702 - > arch/arm/dts/msm8996.dtsi | 3884 -- > arch/arm/dts/pm8916.dtsi| 178 - > arch/arm/dts/pm8994.dtsi| 152 - > arch/arm/dts/pm8998.dtsi| 130 - > arch/arm/dts/pmi8994.dtsi | 65 - > arch/arm/dts/pmi8998.dtsi | 98 - > arch/arm/dts/pms405.dtsi| 149 - > arch/arm/dts/qcs404-evb-4000.dts| 96 - > arch/arm/dts/qcs404-evb.dtsi| 389 -- > arch/arm/dts/qcs404.dtsi| 1829 - > arch/arm/dts/sdm845-db845c.dts | 1190 -- > arch/arm/dts/sdm845-samsung-starqltechn.dts | 460 --- > arch/arm/dts/sdm845-wcd9340.dtsi| 86 - > arch/arm/dts/sdm845.dtsi| 5752 > --- > configs/dragonboard410c_defconfig |2 +- > configs/dragonboard820c_defconfig |2 +- > configs/qcom_defconfig |3 +- > 23 files changed, 5 insertions(+), 19190 deletions(-) > --- > base-commit: d5460b082cd6afd0e07c0ec0e5a82d1af8dc09f7 > > // Caleb (they/them) >
[PATCH v4 5/5] power: regulator: tps65941: Add TPS65224 PMIC regulator support
Reuse TPS65941 regulator driver to adds support for
TPS65224 PMIC's regulators. 4 BUCKs and 3 LDOs, where
BUCK1 and BUCK2 can be configured in dual phase mode.
Signed-off-by: Bhargav Raviprakash
---
drivers/power/regulator/tps65941_regulator.c | 280 ++-
1 file changed, 267 insertions(+), 13 deletions(-)
diff --git a/drivers/power/regulator/tps65941_regulator.c
b/drivers/power/regulator/tps65941_regulator.c
index d879c2301b..5809a53fa2 100644
--- a/drivers/power/regulator/tps65941_regulator.c
+++ b/drivers/power/regulator/tps65941_regulator.c
@@ -37,6 +37,8 @@
#define TPS65941_BUCK_CONV_OPS_IDX 0
#define TPS65941_LDO_CONV_OPS_IDX 0
+#define TPS65224_LDO_CONV_OPS_IDX 1
+#define TPS65224_BUCK_CONV_OPS_IDX 1
struct tps65941_reg_conv_ops {
int volt_mask;
@@ -55,6 +57,11 @@ static const char tps65941_ldo_ctrl[TPS65941_BUCK_NUM] =
{0x1D, 0x1E, 0x1F,
static const char tps65941_ldo_vout[TPS65941_BUCK_NUM] = {0x23, 0x24, 0x25,
0x26};
+static inline int tps65941_get_chip_id(struct udevice *dev)
+{
+ return dev->parent->driver_data;
+}
+
static int tps65941_buck_enable(struct udevice *dev, int op, bool *enable)
{
int ret;
@@ -146,6 +153,112 @@ int tps65941_lookup_slew(int id)
}
}
+static int tps65224_buck_volt2val(int idx, int uV)
+{
+ /* This functions maps a value which is in micro Volts to the VSET
value.
+* The mapping is as per the datasheet of TPS65224.
+*/
+
+ if (uV > TPS65224_BUCK_VOLT_MAX)
+ return -EINVAL;
+
+ if (idx > 0) {
+ /* Buck2, Buck3 and Buck4 of TPS65224 has a different schema in
+* converting b/w micro_volt and VSET hex values
+*
+* VSET value starts from 0x00 for 0.5V, and for every increment
+* in VSET value the output voltage increases by 25mV. This is
upto
+* 1.15V where VSET is 0x1A.
+*
+* For 0x1B the output voltage is 1.2V, and for every increment
of
+* VSET the output voltage increases by 50mV upto the max
voltage of
+* 3.3V
+*
+* | Voltage Ranges | VSET Ranges | Voltage Step |
+* +-+--+--+
+* | 0.5V to 1.50V | 0x00 to 0x1A | 25mV|
+* | 1.2V to 3.3V| 0x1B to 0x45 | 50mV|
+*/
+ if (uV >= 120)
+ return (uV - 120) / 5 + 0x1B;
+ else if (uV >= 50)
+ return (uV - 50) / 25000;
+ else
+ return -EINVAL;
+ }
+
+ /* Buck1 and Buck12(dual phase) has a different mapping b/w output
+* voltage and VSET value.
+*
+* | Voltage Ranges | VSET Ranges | Voltage Step |
+* +-+--+--+
+* | 0.5V to 0.58V | 0xA to 0xE | 20mV|
+* | 0.6V to 1.095V | 0xF to 0x72 | 5mV |
+* | 1.1V to 1.65V | 0x73 to 0xAA | 10mV|
+* | 1.6V to 3.3V| 0xAB to 0xFD | 20mV|
+*
+*/
+ if (uV >= 166)
+ return (uV - 166) / 2 + 0xAB;
+ else if (uV >= 110)
+ return (uV - 110) / 1 + 0x73;
+ else if (uV >= 60)
+ return (uV - 60) / 5000 + 0x0F;
+ else if (uV >= 50)
+ return (uV - 50) / 2 + 0x0A;
+ else
+ return -EINVAL;
+}
+
+static int tps65224_buck_val2volt(int idx, int val)
+{
+ /* This function does the opposite to the tps65224_buck_volt2val
function
+* described above.
+* This maps the VSET value to micro volts. Please refer to the ranges
+* mentioned the comments of tps65224_buck_volt2val.
+*/
+
+ if (idx > 0) {
+ if (val > TPS65224_BUCK234_VOLT_MAX_HEX)
+ return -EINVAL;
+ else if (val >= 0x1B)
+ return 120 + (val - 0x1B) * 5;
+ else if (val >= 0x00)
+ return 50 + (val - 0x00) * 25000;
+ else
+ return -EINVAL;
+ }
+
+ if (val > TPS65224_BUCK1_VOLT_MAX_HEX)
+ return -EINVAL;
+ else if (val >= 0xAB)
+ return 166 + (val - 0xAB) * 2;
+ else if (val >= 0x73)
+ return 110 + (val - 0x73) * 1;
+ else if (val >= 0xF)
+ return 60 + (val - 0xF) * 5000;
+ else if (val >= 0xA)
+ return 50 + (val - 0xA) * 2;
+ else
+ return -EINVAL;
+}
+
+int tps65224_lookup_slew(int id)
+{
+ switch (id) {
+ case 0:
+ return 1;
+ case 1:
+
[PATCH v4 4/5] power: regulator: tps65941: use function callbacks for conversion ops
Use function callbacks for volt2val, val2volt and slewrate lookups.
This makes it easier to add support for TPS65224 PMIC regulators.
Signed-off-by: Bhargav Raviprakash
Reviewed-by: Jaehoon Chung
---
drivers/power/regulator/tps65941_regulator.c | 61 +++-
1 file changed, 48 insertions(+), 13 deletions(-)
diff --git a/drivers/power/regulator/tps65941_regulator.c
b/drivers/power/regulator/tps65941_regulator.c
index cf54e30df5..d879c2301b 100644
--- a/drivers/power/regulator/tps65941_regulator.c
+++ b/drivers/power/regulator/tps65941_regulator.c
@@ -35,6 +35,17 @@
#define TPS65941_LDO_ID_3 3
#define TPS65941_LDO_ID_4 4
+#define TPS65941_BUCK_CONV_OPS_IDX 0
+#define TPS65941_LDO_CONV_OPS_IDX 0
+
+struct tps65941_reg_conv_ops {
+ int volt_mask;
+ int (*volt2val)(int idx, int uV);
+ int (*val2volt)(int idx, int volt);
+ int slew_mask;
+ int (*lookup_slew)(int id);
+};
+
static const char tps65941_buck_ctrl[TPS65941_BUCK_NUM] = {0x4, 0x6, 0x8, 0xA,
0xC};
static const char tps65941_buck_vout[TPS65941_BUCK_NUM] = {0xE, 0x10, 0x12,
@@ -79,7 +90,7 @@ static int tps65941_buck_enable(struct udevice *dev, int op,
bool *enable)
return 0;
}
-static int tps65941_buck_volt2val(int uV)
+static int tps65941_buck_volt2val(__maybe_unused int idx, int uV)
{
if (uV > TPS65941_BUCK_VOLT_MAX)
return -EINVAL;
@@ -95,7 +106,7 @@ static int tps65941_buck_volt2val(int uV)
return -EINVAL;
}
-static int tps65941_buck_val2volt(int val)
+static int tps65941_buck_val2volt(__maybe_unused int idx, int val)
{
if (val > TPS65941_BUCK_VOLT_MAX_HEX)
return -EINVAL;
@@ -135,12 +146,25 @@ int tps65941_lookup_slew(int id)
}
}
+static const struct tps65941_reg_conv_ops buck_conv_ops[] = {
+ [TPS65941_BUCK_CONV_OPS_IDX] = {
+ .volt_mask = TPS65941_BUCK_VOLT_MASK,
+ .volt2val = tps65941_buck_volt2val,
+ .val2volt = tps65941_buck_val2volt,
+ .slew_mask = TP65941_BUCK_CONF_SLEW_MASK,
+ .lookup_slew = tps65941_lookup_slew,
+ },
+};
+
static int tps65941_buck_val(struct udevice *dev, int op, int *uV)
{
unsigned int hex, adr;
- int ret, delta, uwait, slew;
+ int ret, delta, uwait, slew, idx;
struct dm_regulator_uclass_plat *uc_pdata;
+ const struct tps65941_reg_conv_ops *conv_ops;
+ idx = dev->driver_data;
+ conv_ops = _conv_ops[TPS65941_BUCK_CONV_OPS_IDX];
uc_pdata = dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET)
@@ -152,8 +176,8 @@ static int tps65941_buck_val(struct udevice *dev, int op,
int *uV)
if (ret < 0)
return ret;
- ret &= TPS65941_BUCK_VOLT_MASK;
- ret = tps65941_buck_val2volt(ret);
+ ret &= conv_ops->volt_mask;
+ ret = conv_ops->val2volt(idx, ret);
if (ret < 0)
return ret;
@@ -175,14 +199,14 @@ static int tps65941_buck_val(struct udevice *dev, int op,
int *uV)
if (slew < 0)
return ret;
- slew &= TP65941_BUCK_CONF_SLEW_MASK;
- slew = tps65941_lookup_slew(slew);
+ slew &= conv_ops->slew_mask;
+ slew = conv_ops->lookup_slew(slew);
if (slew <= 0)
return ret;
uwait = delta / slew;
- hex = tps65941_buck_volt2val(*uV);
+ hex = conv_ops->volt2val(idx, *uV);
if (hex < 0)
return hex;
@@ -231,7 +255,7 @@ static int tps65941_ldo_enable(struct udevice *dev, int op,
bool *enable)
return 0;
}
-static int tps65941_ldo_val2volt(int val)
+static int tps65941_ldo_val2volt(__maybe_unused int idx, int val)
{
if (val > TPS65941_LDO_VOLT_MAX_HEX || val < TPS65941_LDO_VOLT_MIN_HEX)
return -EINVAL;
@@ -241,12 +265,23 @@ static int tps65941_ldo_val2volt(int val)
return -EINVAL;
}
+static const struct tps65941_reg_conv_ops ldo_conv_ops[] = {
+ [TPS65941_LDO_CONV_OPS_IDX] = {
+ .volt_mask = TPS65941_LDO_VOLT_MASK,
+ .volt2val = tps65941_buck_volt2val,
+ .val2volt = tps65941_ldo_val2volt,
+ },
+};
+
static int tps65941_ldo_val(struct udevice *dev, int op, int *uV)
{
unsigned int hex, adr;
- int ret;
+ int ret, idx;
struct dm_regulator_uclass_plat *uc_pdata;
+ const struct tps65941_reg_conv_ops *conv_ops;
+ idx = dev->driver_data;
+ conv_ops = _conv_ops[TPS65941_LDO_CONV_OPS_IDX];
uc_pdata = dev_get_uclass_plat(dev);
if (op == PMIC_OP_GET)
@@ -258,8 +293,8 @@ static int tps65941_ldo_val(struct udevice *dev, int op,
int *uV)
if (ret < 0)
return ret;
- ret &= TPS65941_LDO_VOLT_MASK;
- ret = tps65941_ldo_val2volt(ret);
+ ret &= conv_ops->volt_mask;
+ ret =
[PATCH v4 3/5] power: regulator: tps65941: Added macros for BUCK ID
Adds macros for buck and ldo ids and switched to using switch
case instead of if else in probe functions. Helps in adding
support for TPS65224 PMIC.
Signed-off-by: Bhargav Raviprakash
Reviewed-by: Dhruva Gole
Reviewed-by: Jaehoon Chung
---
drivers/power/regulator/tps65941_regulator.c | 54 +++-
1 file changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/power/regulator/tps65941_regulator.c
b/drivers/power/regulator/tps65941_regulator.c
index b041126775..cf54e30df5 100644
--- a/drivers/power/regulator/tps65941_regulator.c
+++ b/drivers/power/regulator/tps65941_regulator.c
@@ -16,6 +16,25 @@
#include
#include
+/* Single Phase Buck IDs */
+#define TPS65941_BUCK_ID_11
+#define TPS65941_BUCK_ID_22
+#define TPS65941_BUCK_ID_33
+#define TPS65941_BUCK_ID_44
+#define TPS65941_BUCK_ID_55
+
+/* Multi Phase Buck IDs */
+#define TPS65941_BUCK_ID_12 12
+#define TPS65941_BUCK_ID_34 34
+#define TPS65941_BUCK_ID_123123
+#define TPS65941_BUCK_ID_1234 1234
+
+/* LDO IDs */
+#define TPS65941_LDO_ID_1 1
+#define TPS65941_LDO_ID_2 2
+#define TPS65941_LDO_ID_3 3
+#define TPS65941_LDO_ID_4 4
+
static const char tps65941_buck_ctrl[TPS65941_BUCK_NUM] = {0x4, 0x6, 0x8, 0xA,
0xC};
static const char tps65941_buck_vout[TPS65941_BUCK_NUM] = {0xE, 0x10, 0x12,
@@ -270,10 +289,15 @@ static int tps65941_ldo_probe(struct udevice *dev)
uc_pdata->type = REGULATOR_TYPE_LDO;
idx = dev->driver_data;
- if (idx == 1 || idx == 2 || idx == 3 || idx == 4) {
+ switch (idx) {
+ case TPS65941_LDO_ID_1:
+ case TPS65941_LDO_ID_2:
+ case TPS65941_LDO_ID_3:
+ case TPS65941_LDO_ID_4:
debug("Single phase regulator\n");
- } else {
- printf("Wrong ID for regulator\n");
+ break;
+ default:
+ pr_err("Wrong ID for regulator\n");
return -EINVAL;
}
@@ -292,18 +316,24 @@ static int tps65941_buck_probe(struct udevice *dev)
uc_pdata->type = REGULATOR_TYPE_BUCK;
idx = dev->driver_data;
- if (idx == 1 || idx == 2 || idx == 3 || idx == 4 || idx == 5) {
+ switch (idx) {
+ case TPS65941_BUCK_ID_1:
+ case TPS65941_BUCK_ID_2:
+ case TPS65941_BUCK_ID_3:
+ case TPS65941_BUCK_ID_4:
+ case TPS65941_BUCK_ID_5:
debug("Single phase regulator\n");
- } else if (idx == 12) {
+ break;
+ case TPS65941_BUCK_ID_12:
+ case TPS65941_BUCK_ID_123:
+ case TPS65941_BUCK_ID_1234:
idx = 1;
- } else if (idx == 34) {
+ break;
+ case TPS65941_BUCK_ID_34:
idx = 3;
- } else if (idx == 123) {
- idx = 1;
- } else if (idx == 1234) {
- idx = 1;
- } else {
- printf("Wrong ID for regulator\n");
+ break;
+ default:
+ pr_err("Wrong ID for regulator\n");
return -EINVAL;
}
--
2.25.1
[PATCH v4 2/5] power: pmic: tps65941: Add TI TPS65224 PMIC
Adds compatible and data field values of TPS65224 driver in
TPS65941 PMIC driver.
Signed-off-by: Bhargav Raviprakash
Reviewed-by: Dhruva Gole
Reviewed-by: Jaehoon Chung
---
drivers/power/pmic/tps65941.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/power/pmic/tps65941.c b/drivers/power/pmic/tps65941.c
index 727b42747a..ef63eb733a 100644
--- a/drivers/power/pmic/tps65941.c
+++ b/drivers/power/pmic/tps65941.c
@@ -75,6 +75,7 @@ static const struct udevice_id tps65941_ids[] = {
{ .compatible = "ti,tps659412", .data = TPS659411 },
{ .compatible = "ti,tps659413", .data = TPS659413 },
{ .compatible = "ti,lp876441", .data = LP876441 },
+ { .compatible = "ti,tps65224", .data = TPS65224 },
{ }
};
--
2.25.1
[PATCH v4 1/5] power: tps65941: Add macros of TPS65224 PMIC
Re-use the TPS65941 PMIC driver for TPS65224 PMIC. Add additional macros of TPS65224 to aid in the driver re-use. Signed-off-by: Bhargav Raviprakash Reviewed-by: Dhruva Gole Reviewed-by: Jaehoon Chung --- include/power/tps65941.h | 30 ++ 1 file changed, 30 insertions(+) diff --git a/include/power/tps65941.h b/include/power/tps65941.h index a2bc6814ba..cec85333f0 100644 --- a/include/power/tps65941.h +++ b/include/power/tps65941.h @@ -3,11 +3,14 @@ #define TPS659413 0x2 #define TPS659414 0x3 #define LP876441 0x4 +#define TPS65224 0x5 /* I2C device address for pmic tps65941 */ #define TPS65941_I2C_ADDR (0x12 >> 1) #define TPS65941_LDO_NUM 4 #define TPS65941_BUCK_NUM 5 +#define TPS65224_LDO_NUM 3 +#define TPS65224_BUCK_NUM 4 /* Drivers name */ #define TPS65941_LDO_DRIVER"tps65941_ldo" @@ -25,3 +28,30 @@ #define TPS65941_LDO_MODE_MASK 0x1 #define TPS65941_LDO_BYPASS_EN 0x80 #define TP65941_BUCK_CONF_SLEW_MASK0x7 + +#define TPS65224_BUCK_VOLT_MAX 330 +#define TPS65224_BUCK1_VOLT_MAX_HEX 0xFD +#define TPS65224_BUCK234_VOLT_MAX_HEX0x45 + +#define TPS65224_BUCK_CONF_SLEW_MASK 0x3 +#define TPS65224_LDO_VOLT_MASK(0x3F << 1) + +#define TPS65224_LDO1_VOLT_MIN_HEX 0x0C +#define TPS65224_LDO23_VOLT_MIN_HEX 0x00 +#define TPS65224_LDO1_VOLT_MAX_HEX 0x36 +#define TPS65224_LDO23_VOLT_MAX_HEX 0x38 + +#define TPS65224_LDO1_VOLT_MAX330 +#define TPS65224_LDO23_VOLT_MAX 340 +#define TPS65224_LDO1_VOLT_MIN120 +#define TPS65224_LDO23_VOLT_MIN60 + +#define TPS65224_LDO_STEP 5 + +#define TPS65224_LDO_BYP_CONFIG 7 + +#define TPS65224_LDO1_VOLT_BYP_MIN220 +#define TPS65224_LDO1_VOLT_BYP_MAX360 + +#define TPS65224_LDO23_VOLT_BYP_MIN 150 +#define TPS65224_LDO23_VOLT_BYP_MAX 550 -- 2.25.1
[PATCH v4 0/5] Add support for TI TPS65224 PMIC
TPS65224 is a Power Management IC which provides regulators and others features like GPIOs, RTC, watchdog, ADC, ESMs (Error Signal Monitor), and PFSM (Pre-configurable Finite State Machine). The SoC and the PMIC can communicate through the I2C. Data Sheet for TPS65224: https://www.ti.com/product/TPS65224-Q1 Reusing the TPS65941 PMIC driver to add support for TPS65224 PMIC in U-boot. This includes driver for PMIC and regulator. The driver was tested on Ti's custom AM62P EVM using U-boot's pmic list, regulator list, regulator status and regulator value commands. Since, support for Ti's AM62P is absent in u-boot next, the patches were applied on ti-u-boot ti-u-boot-2023.04-next and tested. Changelog v3 -> v4: - refactoring ldo probe function: removed a redundant branch Bhargav Raviprakash (5): power: tps65941: Add macros of TPS65224 PMIC power: pmic: tps65941: Add TI TPS65224 PMIC power: regulator: tps65941: Added macros for BUCK ID power: regulator: tps65941: use function callbacks for conversion ops power: regulator: tps65941: Add TPS65224 PMIC regulator support drivers/power/pmic/tps65941.c| 1 + drivers/power/regulator/tps65941_regulator.c | 381 +-- include/power/tps65941.h | 30 ++ 3 files changed, 381 insertions(+), 31 deletions(-) -- 2.25.1
Re: [PATCH 1/1] Makefile: don't add -Wno-maybe-uninitialized twice
Hi Heinrich,
On 4/16/24 09:35, Heinrich Schuchardt wrote:
Avoid adding the same flag to KBUILD_CFLAGS twice.
Fixes: 8602d97ca2cf ("Makefile: avoid false positive -Wmaybe-uninitialized")
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Quentin Schulz
Thanks,
Quentin
[PATCH v2 1/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
found on newer Qualcomm SoCs.
The Generic Interface (GENI) is a firmware based Qualcomm Universal
Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
bus protocols depending on the firmware type loaded at early boot time
based on system configuration.
It also supports the "I2C Master Hub" which is a single function Wrapper
that only FIFO mode I2C.
It replaces the fixed-function QUP Wrapper found on older SoCs.
The geni-se.h containing the generic GENI Serial Engine registers defines
is imported from Linux.
Only FIFO mode is implemented, neither SE DMA nor GPI DMA are implemented.
Signed-off-by: Neil Armstrong
---
drivers/i2c/Kconfig| 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/geni_i2c.c | 575 +
include/soc/qcom/geni-se.h | 265 +
4 files changed, 851 insertions(+)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 59c635af80b..34b02114dc6 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -638,6 +638,16 @@ config SYS_I2C_QUP
Technical Reference Manual, chapter "6.1 Qualcomm Universal
Peripherals Engine (QUP)".
+config SYS_I2C_GENI
+ bool "Qualcomm Generic Interface (GENI) I2C controller"
+ depends on ARCH_SNAPDRAGON
+ help
+ Support for the Qualcomm Generic Interface (GENI) I2C interface.
+ The Generic Interface (GENI) is a firmware based Qualcomm Universal
+ Peripherals (QUP) Serial Engine (SE) Wrapper which can support
multiple
+ bus protocols depending on the firmware type loaded at early boot time
+ based on system configuration.
+
config SYS_I2C_S3C24X0
bool "Samsung I2C driver"
depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 692f63bafd0..00b90523c62 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
obj-$(CONFIG_SYS_I2C_DW_PCI) += designware_i2c_pci.o
obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
+obj-$(CONFIG_SYS_I2C_GENI) += geni_i2c.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o
obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o
diff --git a/drivers/i2c/geni_i2c.c b/drivers/i2c/geni_i2c.c
new file mode 100644
index 000..eabf5c76c21
--- /dev/null
+++ b/drivers/i2c/geni_i2c.c
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited
+ * Author: Neil Armstrong
+ *
+ * Based on Linux driver: drivers/i2c/busses/i2c-qcom-geni.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SE_I2C_TX_TRANS_LEN0x26c
+#define SE_I2C_RX_TRANS_LEN0x270
+#define SE_I2C_SCL_COUNTERS0x278
+
+#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
+ M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
+#define SE_I2C_ABORT BIT(1)
+
+/* M_CMD OP codes for I2C */
+#define I2C_WRITE 0x1
+#define I2C_READ 0x2
+#define I2C_WRITE_READ 0x3
+#define I2C_ADDR_ONLY 0x4
+#define I2C_BUS_CLEAR 0x6
+#define I2C_STOP_ON_BUS0x7
+/* M_CMD params for I2C */
+#define PRE_CMD_DELAY BIT(0)
+#define TIMESTAMP_BEFORE BIT(1)
+#define STOP_STRETCH BIT(2)
+#define TIMESTAMP_AFTERBIT(3)
+#define POST_COMMAND_DELAY BIT(4)
+#define IGNORE_ADD_NACKBIT(6)
+#define READ_FINISHED_WITH_ACK BIT(7)
+#define BYPASS_ADDR_PHASE BIT(8)
+#define SLV_ADDR_MSK GENMASK(15, 9)
+#define SLV_ADDR_SHFT 9
+/* I2C SCL COUNTER fields */
+#define HIGH_COUNTER_MSK GENMASK(29, 20)
+#define HIGH_COUNTER_SHFT 20
+#define LOW_COUNTER_MSKGENMASK(19, 10)
+#define LOW_COUNTER_SHFT 10
+#define CYCLE_COUNTER_MSK GENMASK(9, 0)
+
+#define I2C_PACK_TXBIT(0)
+#define I2C_PACK_RXBIT(1)
+
+#define PACKING_BYTES_PW 4
+
+#define GENI_I2C_IS_MASTER_HUB BIT(0)
+
+#define I2C_TIMEOUT_MS 100
+
+struct geni_i2c_clk_fld {
+ u32 clk_freq_out;
+ u8 clk_div;
+ u8 t_high_cnt;
+ u8 t_low_cnt;
+ u8 t_cycle_cnt;
+};
+
+struct geni_i2c_priv {
+ fdt_addr_t wrapper;
+ phys_addr_t base;
+ struct clk core;
+ struct clk se;
+ u32 tx_wm;
+ bool is_master_hub;
+ const struct geni_i2c_clk_fld *clk_fld;
+};
+
+/*
+ * Hardware uses the underlying formula to calculate time periods of
+ * SCL clock cycle. Firmware uses some additional cycles excluded
[PATCH v2 2/2] configs: qcom_defconfig: enable GENI I2C Driver
Enable the GENI I2C driver in the default Qualcomm defconfig. Reviewed-by: Caleb Connolly Signed-off-by: Neil Armstrong --- configs/qcom_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index 1abb57345ff..8d440b23625 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -41,6 +41,7 @@ CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_QUP=y +CONFIG_SYS_I2C_GENI=y CONFIG_I2C_MUX=y CONFIG_DM_KEYBOARD=y CONFIG_BUTTON_KEYBOARD=y -- 2.34.1
[PATCH v2 0/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
Add Support for the Qualcomm Generic Interface (GENI) I2C interface found on newer Qualcomm SoCs. The Generic Interface (GENI) is a firmware based Qualcomm Universal Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple bus protocols depending on the firmware type loaded at early boot time based on system configuration. It also supports the "I2C Master Hub" which is a single function Wrapper that only FIFO mode I2C. It replaces the fixed-function QUP Wrapper found on older SoCs. The geni-se.h containing the generic GENI Serial Engine registers defines is imported from Linux. Only FIFO mode is implemented, neither SE DMA nor GPI DMA are implemented. Finally enable the driver in the default Qualcomm defconfig. Signed-off-by: Neil Armstrong --- Changes in v2: - Fixed commit msg, removed useless debug, switched to dev_err() in probe - Fixed some possible issues & typos and W=1 build warning - Link to v1: https://lore.kernel.org/r/20240419-topic-sm8x50-i2c-v1-0-67651e27f...@linaro.org --- Neil Armstrong (2): i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller configs: qcom_defconfig: enable GENI I2C Driver configs/qcom_defconfig | 1 + drivers/i2c/Kconfig| 10 + drivers/i2c/Makefile | 1 + drivers/i2c/geni_i2c.c | 575 + include/soc/qcom/geni-se.h | 265 + 5 files changed, 852 insertions(+) --- base-commit: b2511143fba4c0631446c968fb4c0d962b01d850 change-id: 20240419-topic-sm8x50-i2c-b51e576d5f57 Best regards, -- Neil Armstrong
Re: [PATCH 1/2] i2c: Add support for Qualcomm Generic Interface (GENI) I2C controller
On 19/04/2024 13:47, Caleb Connolly wrote:
Hi Neil,
On 18/04/2024 23:47, Neil Armstrong wrote:
Add Support for the Qualcomm Generic Interface (GENI) I2C interface
found on newer Qualcomm SoCs.
\o/
The Generic Interface (GENI) is a firmware based Qualcomm Universal
Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple
bus protocols depending on the firmware type loaded at early boot time
based on system configuration.
It also supports the "I2C Master Hub" which is a single function Wrapper
that only FIFO mode I2C.
It replaces the fixed-function QUP Wrapper found on older SoCs.
The geni-se.h containing the generic GENI Serial Engine registers defines
is imported from Linux.
Only FIFO mode is implemented, nor SE DMA nor GPI DMA is implemented.
nit: "neither SE DMA nor GPI DMA are implemented"
Thx!
A few minor things below, but otherwise LGTM!
Signed-off-by: Neil Armstrong
---
drivers/i2c/Kconfig| 10 +
drivers/i2c/Makefile | 1 +
drivers/i2c/geni_i2c.c | 576 +
include/soc/qcom/geni-se.h | 265 +
4 files changed, 852 insertions(+)
[...]
diff --git a/drivers/i2c/geni_i2c.c b/drivers/i2c/geni_i2c.c
new file mode 100644
index 000..8c3ed3bef89
--- /dev/null
+++ b/drivers/i2c/geni_i2c.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2024, Linaro Limited
+ * Author: Neil Armstrong
+ *
+ * Based on Linux driver: drivers/i2c/busses/i2c-qcom-geni.c
+ */
+
[...]
+static int geni_i2c_fifo_tx_fill(struct geni_i2c_priv *geni, struct i2c_msg
*msg)
+{
+ ulong start = get_timer(0);
+ ulong cur_xfer = 0;
+ int i;
+
+ while (get_timer(start) < I2C_TIMEOUT_MS) {
+ u32 status = readl(geni->base + SE_GENI_M_IRQ_STATUS);
+
+ if (status & (M_CMD_ABORT_EN |
+ M_CMD_OVERRUN_EN |
+ M_ILLEGAL_CMD_EN |
+ M_CMD_FAILURE_EN |
+ M_GP_IRQ_1_EN |
+ M_GP_IRQ_3_EN |
+ M_GP_IRQ_4_EN)) {
+ debug("%s:%d cmd err\n", __func__, __LINE__);
How likely are we to hit this? Would it make sense to promote it to a
pr_warn()?
Please drop the __LINE__ and (if it makes sense to?) print the value of
status.
It's used when the tranactions is nacked, so it would spam, so I rather remove
the print entirely. It's verly unlikely we see any of the other errors.
+ writel(status, geni->base + SE_GENI_M_IRQ_CLEAR);
+ writel(0, geni->base + SE_GENI_TX_WATERMARK_REG);
+ return -EREMOTEIO;
+ }
+
+ if ((status & M_TX_FIFO_WATERMARK_EN) == 0) {
+ udelay(1);
+ goto skip_fill;
+ }
+
+ for (i = 0; i < geni->tx_wm; i++) {
+ u32 temp, tx = 0;
+ unsigned int p = 0;
+
+ while (cur_xfer < msg->len && p < sizeof(tx)) {
+ temp = msg->buf[cur_xfer++];
+ tx |= temp << (p * 8);
+ p++;
+ }
+
+ writel(tx, geni->base + SE_GENI_TX_FIFOn);
+
+ if (cur_xfer == msg->len) {
+ writel(0, geni->base +
SE_GENI_TX_WATERMARK_REG);
+ break;
+ }
+ }
+
+skip_fill:
+ writel(status, geni->base + SE_GENI_M_IRQ_CLEAR);
+
+ if (status & M_CMD_DONE_EN)
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int geni_i2c_fifo_rx_drain(struct geni_i2c_priv *geni, struct i2c_msg
*msg)
+{
+ ulong start = get_timer(0);
+ ulong cur_xfer = 0;
+ int i;
+
+ while (get_timer(start) < I2C_TIMEOUT_MS) {
+ u32 status = readl(geni->base + SE_GENI_M_IRQ_STATUS);
+ u32 rxstatus = readl(geni->base + SE_GENI_RX_FIFO_STATUS);
+ u32 rxcnt = rxstatus & RX_FIFO_WC_MSK;
+
+ if (status & (M_CMD_ABORT_EN |
+ M_CMD_FAILURE_EN |
+ M_CMD_OVERRUN_EN |
+ M_ILLEGAL_CMD_EN |
+ M_GP_IRQ_1_EN |
+ M_GP_IRQ_3_EN |
+ M_GP_IRQ_4_EN)) {
+ debug("%s:%d cmd err\n", __func__, __LINE__);
Ditto
+ writel(status, geni->base + SE_GENI_M_IRQ_CLEAR);
+ return -EIO;
+ }
+
+ if ((status & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) ==
0) {
+ udelay(1);
+
Re: [PATCH] board: rk3288: simplify the DT file list in MAINTAINERS
On 2024-04-22 10:24, Kever Yang wrote: On 2024/4/18 15:06, Dragan Simic wrote: Use a wildcard to simplify the list of board DT files in the MAINTAINERS file for the Radxa Rock 2 Square board. Signed-off-by: Dragan Simic Reviewed-by: Kever Yang Thanks! --- board/radxa/rock2/MAINTAINERS | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/board/radxa/rock2/MAINTAINERS b/board/radxa/rock2/MAINTAINERS index 5328fd76014a..af974c983047 100644 --- a/board/radxa/rock2/MAINTAINERS +++ b/board/radxa/rock2/MAINTAINERS @@ -1,9 +1,7 @@ FIREFLY M:Simon Glass S:Maintained -F: arch/arm/dts/rk3288-rock2-som.dtsi -F: arch/arm/dts/rk3288-rock2-square.dts -F: arch/arm/dts/rk3288-rock2-square-u-boot.dtsi +F: arch/arm/dts/rk3288-rock2* F:board/radxa/rock2 F:include/configs/rock2.h F:configs/rock2_defconfig
Re: [PATCH v2 11/14] rockchip: rk3308-evb: Update defconfig
Hi Kever, On 2024-04-22 10:50, Kever Yang wrote: > Hi Jonas, > > On 2024/4/9 02:14, Jonas Karlman wrote: >> Update defconfig for rk3308-evb with new defaults. >> >> Add OF_LIBFDT_OVERLAY=y to support device tree overlays. >> >> Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. >> >> Use DEBUG_UART_BASE=0xFF0E and disable DEBUG_UART_BOARD_INIT to >> make debug uart use uart4, same as stdout-path prop. > > Why this change happen? I think rk3308-evb is using UART2 on 0xFF0C. > The device tree both used in U-Boot [1] and Linux [2] both use: stdout-path = "serial4:150n8" and only enable the uart4 node. Yet the defconfig in U-Boot use a DEBUG_UART_BASE for uart2 instead of uart4. Having U-Boot defconfig matching the upstream device tree seem like a good thing, but maybe the device tree is wrong? [1] https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/rk3308-evb.dts [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3308-evb.dts Regards, Jonas > > Thanks, > > - Kever > >> >> Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to >> allow use of U-Boot cmdline. >> >> Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. >> >> Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to >> allow full use of USB 2.0 host and otg ports. >> >> Enable EFI_LOADER to allow EFI boot. >> >> Signed-off-by: Jonas Karlman >> --- >> v2: Fix DEBUG_UART_BASE and disable DEBUG_UART_BOARD_INIT >> --- >> configs/evb-rk3308_defconfig | 37 +++- >> 1 file changed, 15 insertions(+), 22 deletions(-) >> >> diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig >> index 9dc7d9c0caea..04a94e13a68a 100644 >> --- a/configs/evb-rk3308_defconfig >> +++ b/configs/evb-rk3308_defconfig >> @@ -3,41 +3,32 @@ CONFIG_SKIP_LOWLEVEL_INIT=y >> CONFIG_COUNTER_FREQUENCY=2400 >> CONFIG_ARCH_ROCKCHIP=y >> CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb" >> +CONFIG_OF_LIBFDT_OVERLAY=y >> CONFIG_DM_RESET=y >> CONFIG_ROCKCHIP_RK3308=y >> -CONFIG_SPL_DRIVERS_MISC=y >> CONFIG_TARGET_EVB_RK3308=y >> -CONFIG_DEBUG_UART_BASE=0xFF0C >> +CONFIG_DEBUG_UART_BASE=0xFF0E >> CONFIG_DEBUG_UART_CLOCK=2400 >> +# CONFIG_DEBUG_UART_BOARD_INIT is not set >> CONFIG_SYS_LOAD_ADDR=0xc00800 >> CONFIG_DEBUG_UART=y >> CONFIG_ANDROID_BOOT_IMAGE=y >> CONFIG_FIT=y >> CONFIG_FIT_VERBOSE=y >> -CONFIG_BOOTDELAY=0 >> CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb" >> -CONFIG_SYS_CONSOLE_INFO_QUIET=y >> # CONFIG_DISPLAY_CPUINFO is not set >> -CONFIG_SPL_MAX_SIZE=0x2 >> +CONFIG_SPL_MAX_SIZE=0x4 >> CONFIG_SPL_PAD_TO=0x7f8000 >> # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set >> -# CONFIG_CMD_BDI is not set >> -# CONFIG_CMD_CONSOLE is not set >> -# CONFIG_CMD_ELF is not set >> -# CONFIG_CMD_IMI is not set >> -# CONFIG_CMD_XIMG is not set >> +CONFIG_CMD_GPIO=y >> CONFIG_CMD_GPT=y >> -# CONFIG_CMD_LOADB is not set >> -# CONFIG_CMD_LOADS is not set >> CONFIG_CMD_MMC=y >> CONFIG_CMD_USB=y >> +CONFIG_CMD_ROCKUSB=y >> CONFIG_CMD_USB_MASS_STORAGE=y >> -# CONFIG_CMD_ITEST is not set >> -# CONFIG_CMD_SETEXPR is not set >> -# CONFIG_CMD_SLEEP is not set >> -# CONFIG_SPL_DOS_PARTITION is not set >> -# CONFIG_ISO_PARTITION is not set >> -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 >> +CONFIG_CMD_RNG=y >> +CONFIG_CMD_KASLRSEED=y >> +CONFIG_CMD_REGULATOR=y >> CONFIG_SPL_OF_CONTROL=y >> CONFIG_OF_LIVE=y >> CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks >> assigned-clock-rates assigned-clock-parents" >> @@ -51,9 +42,11 @@ CONFIG_SYS_I2C_ROCKCHIP=y >> CONFIG_SUPPORT_EMMC_RPMB=y >> CONFIG_MMC_DW=y >> CONFIG_MMC_DW_ROCKCHIP=y >> +CONFIG_PHY_REALTEK=y >> +CONFIG_DM_ETH_PHY=y >> CONFIG_ETH_DESIGNWARE=y >> CONFIG_GMAC_ROCKCHIP=y >> -CONFIG_PHY=y >> +CONFIG_PHY_ROCKCHIP_INNO_USB2=y >> CONFIG_PINCTRL=y >> CONFIG_REGULATOR_PWM=y >> CONFIG_DM_REGULATOR_FIXED=y >> @@ -62,15 +55,15 @@ CONFIG_RAM=y >> CONFIG_BAUDRATE=150 >> CONFIG_DEBUG_UART_SHIFT=2 >> CONFIG_SYS_NS16550_MEM32=y >> +CONFIG_SYSINFO=y >> CONFIG_SYSRESET=y >> CONFIG_USB=y >> +CONFIG_DM_USB_GADGET=y >> CONFIG_USB_EHCI_HCD=y >> CONFIG_USB_EHCI_GENERIC=y >> -CONFIG_USB_DWC2=y >> CONFIG_USB_GADGET=y >> CONFIG_USB_GADGET_DWC2_OTG=y >> CONFIG_USB_GADGET_DOWNLOAD=y >> -CONFIG_SPL_TINY_MEMSET=y >> +CONFIG_USB_FUNCTION_ROCKUSB=y >> CONFIG_LZO=y >> CONFIG_ERRNO_STR=y >> -# CONFIG_EFI_LOADER is not set
[PATCH] efi_loader: do not install dtb if bootmgr fails
If the UEFI boot manager fails, there is no point in installing the
device-tree as a configuration table.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_bootmgr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index c64cbe82402..2b0d3137338 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -1209,15 +1209,15 @@ efi_status_t efi_bootmgr_run(void *fdt)
return CMD_RET_FAILURE;
}
- ret = efi_install_fdt(fdt);
- if (ret != EFI_SUCCESS)
- return ret;
-
ret = efi_bootmgr_load(, _options);
if (ret != EFI_SUCCESS) {
log_notice("EFI boot manager: Cannot load any image\n");
return ret;
}
+ ret = efi_install_fdt(fdt);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
return do_bootefi_exec(handle, load_options);
}
--
2.43.0
Re: BTRFS use-after-free bug at free_extent_buffer_internal
在 2024/4/22 16:45, Qu Wenruo 写道:
[...]
I added a print statement to free_extent_buffer_internal that prints the
start address of the extent_buffer as I'm not sure what to be looking for
here. This print statement is before the decrement.
printf("free_extent_buffer_internal: eb->start[%llx] eb->refs[%i]\n",
eb->start, eb->refs);
Just a small advice, in fact you can go with sandbox mode, running
U-boot in userspace, and bind a host file as a device to test the
filesystem code.
At least that's what I did for most U-boot bugs.
Thanks,
Qu
Re: [PATCH v2 14/14] rockchip: rk3308: Move cru and grf include files to arch-rockchip
On 2024/4/9 02:14, Jonas Karlman wrote:
Move cru_rk3308.h and grf_rk3308.h to arch-rockchip to match path used
for all other Rockchip SoCs.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: New patch
---
.../arm/include/asm/{arch-rk3308 => arch-rockchip}/cru_rk3308.h | 0
.../arm/include/asm/{arch-rk3308 => arch-rockchip}/grf_rk3308.h | 0
arch/arm/mach-rockchip/rk3308/clk_rk3308.c | 2 +-
arch/arm/mach-rockchip/rk3308/rk3308.c | 2 +-
board/firefly/firefly-rk3308/roc_cc_rk3308.c| 2 +-
drivers/clk/rockchip/clk_rk3308.c | 2 +-
drivers/net/gmac_rockchip.c | 2 +-
drivers/ram/rockchip/sdram_rk3308.c | 2 +-
8 files changed, 6 insertions(+), 6 deletions(-)
rename arch/arm/include/asm/{arch-rk3308 => arch-rockchip}/cru_rk3308.h (100%)
rename arch/arm/include/asm/{arch-rk3308 => arch-rockchip}/grf_rk3308.h (100%)
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3308.h
similarity index 100%
rename from arch/arm/include/asm/arch-rk3308/cru_rk3308.h
rename to arch/arm/include/asm/arch-rockchip/cru_rk3308.h
diff --git a/arch/arm/include/asm/arch-rk3308/grf_rk3308.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3308.h
similarity index 100%
rename from arch/arm/include/asm/arch-rk3308/grf_rk3308.h
rename to arch/arm/include/asm/arch-rockchip/grf_rk3308.h
diff --git a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
index ccda53380c6f..201bf661f9bb 100644
--- a/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/clk_rk3308.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#include
+#include
#include
int rockchip_get_clk(struct udevice **devp)
diff --git a/arch/arm/mach-rockchip/rk3308/rk3308.c
b/arch/arm/mach-rockchip/rk3308/rk3308.c
index b3ffabc5449a..a0915c72bfa0 100644
--- a/arch/arm/mach-rockchip/rk3308/rk3308.c
+++ b/arch/arm/mach-rockchip/rk3308/rk3308.c
@@ -5,8 +5,8 @@
#include
#include
#include
-#include
#include
+#include
#include
#include
#include
diff --git a/board/firefly/firefly-rk3308/roc_cc_rk3308.c
b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
index 99a52a77116a..af00250e118d 100644
--- a/board/firefly/firefly-rk3308/roc_cc_rk3308.c
+++ b/board/firefly/firefly-rk3308/roc_cc_rk3308.c
@@ -5,7 +5,7 @@
#include
#include
-#include
+#include
#include
#include
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index c46b58e31626..861648321d40 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -12,8 +12,8 @@
#include
#include
#include
-#include
#include
+#include
#include
#include
#include
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 33fc36da5077..51f835adabc3 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -19,7 +19,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/ram/rockchip/sdram_rk3308.c
b/drivers/ram/rockchip/sdram_rk3308.c
index 10828e80822a..264366291cf8 100644
--- a/drivers/ram/rockchip/sdram_rk3308.c
+++ b/drivers/ram/rockchip/sdram_rk3308.c
@@ -7,8 +7,8 @@
#include
#include
#include
-#include
#include
+#include
#include
struct dram_info {
Re: [PATCH v2 12/14] rockchip: rk3308-roc-cc: Update defconfig
On 2024/4/9 02:14, Jonas Karlman wrote: Update defconfig for rk3308-roc-cc with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: No change --- configs/roc-cc-rk3308_defconfig | 35 + 1 file changed, 14 insertions(+), 21 deletions(-) diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 041fa75b9659..ef58bd657532 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -4,9 +4,9 @@ CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="rk3308-roc-cc" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_ROC_RK3308_CC=y CONFIG_DEBUG_UART_BASE=0xFF0C CONFIG_DEBUG_UART_CLOCK=2400 @@ -15,30 +15,20 @@ CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-roc-cc.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x2 +CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -52,27 +42,30 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set
Re: [PATCH v2 13/14] rockchip: rk3308-rock-pi-s: Update defconfig
On 2024/4/9 02:14, Jonas Karlman wrote:
Update defconfig for rk3308-rock-pi-s with new defaults.
Add OF_LIBFDT_OVERLAY=y to support device tree overlays.
Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL.
Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to
allow use of U-Boot cmdline.
Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY.
Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to
allow full use of USB 2.0 host and otg ports.
Enable EFI_LOADER to allow EFI boot.
Also fix use of USB 2.0 otg port by removing improper use of phy-supply
and regulator-always-on props.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: Keep DEBUG_UART_BOARD_INIT disabled
---
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 8 ++
configs/rock-pi-s-rk3308_defconfig| 32 +--
2 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index 8d34ed1b3a36..a6fb8b12da38 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -15,6 +15,10 @@
bootph-some-ram;
};
+_otg {
+ /delete-property/ phy-supply;
+};
+
{
bootph-all;
clock-frequency = <2400>;
@@ -32,6 +36,10 @@
bootph-all;
};
+_otg {
+ /delete-property/ regulator-always-on;
+};
+
_core {
regulator-init-microvolt = <1015000>;
};
diff --git a/configs/rock-pi-s-rk3308_defconfig
b/configs/rock-pi-s-rk3308_defconfig
index 27ee24a62290..37a124eae181 100644
--- a/configs/rock-pi-s-rk3308_defconfig
+++ b/configs/rock-pi-s-rk3308_defconfig
@@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="rk3308-rock-pi-s"
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_DM_RESET=y
CONFIG_ROCKCHIP_RK3308=y
-CONFIG_SPL_DRIVERS_MISC=y
CONFIG_TARGET_EVB_RK3308=y
CONFIG_DEBUG_UART_BASE=0xFF0A
CONFIG_DEBUG_UART_CLOCK=2400
@@ -17,28 +16,19 @@ CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-rock-pi-s.dtb"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_SPL_MAX_SIZE=0x2
+CONFIG_SPL_MAX_SIZE=0x4
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
+CONFIG_CMD_ROCKUSB=y
CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_SLEEP is not set
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_ISO_PARTITION is not set
-CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_CMD_RNG=y
+CONFIG_CMD_KASLRSEED=y
+CONFIG_CMD_REGULATOR=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks
assigned-clock-rates assigned-clock-parents"
@@ -52,9 +42,11 @@ CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_PHY_REALTEK=y
+CONFIG_DM_ETH_PHY=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PHY=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_REGULATOR_PWM=y
CONFIG_DM_REGULATOR_FIXED=y
@@ -63,15 +55,15 @@ CONFIG_RAM=y
CONFIG_BAUDRATE=150
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSINFO=y
CONFIG_SYSRESET=y
CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_SPL_TINY_MEMSET=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
-# CONFIG_EFI_LOADER is not set
Re: [PATCH v3 07/11] rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS
On 2024/4/15 22:17, Quentin Schulz wrote:
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the evb_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
All defconfigs using the CONFIG_TARGET_EVB_RK3588 are updated at once
since they are impacted by this change.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/rockchip/evb_rk3588/Makefile | 6 -
board/rockchip/evb_rk3588/evb-rk3588.c | 39
configs/coolpi-4b-rk3588s_defconfig | 2 --
configs/coolpi-cm5-evb-rk3588_defconfig | 2 --
configs/evb-rk3588_defconfig | 2 --
configs/generic-rk3588_defconfig | 2 --
configs/orangepi-5-plus-rk3588_defconfig | 2 --
configs/orangepi-5-rk3588s_defconfig | 2 --
8 files changed, 57 deletions(-)
diff --git a/board/rockchip/evb_rk3588/Makefile
b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec597e..000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c
b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8d29c..000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/coolpi-4b-rk3588s_defconfig
b/configs/coolpi-4b-rk3588s_defconfig
index a0fe3708344..2608bb67679 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig
b/configs/coolpi-cm5-evb-rk3588_defconfig
index fc17660da2a..c5bb7a42957 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index c8db04c076e..187cf26a5c9 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
Re: [PATCH v2 11/14] rockchip: rk3308-evb: Update defconfig
Hi Jonas, On 2024/4/9 02:14, Jonas Karlman wrote: Update defconfig for rk3308-evb with new defaults. Add OF_LIBFDT_OVERLAY=y to support device tree overlays. Remove the SPL_DRIVERS_MISC=y option, no misc driver is used in SPL. Use DEBUG_UART_BASE=0xFF0E and disable DEBUG_UART_BOARD_INIT to make debug uart use uart4, same as stdout-path prop. Why this change happen? I think rk3308-evb is using UART2 on 0xFF0C. Thanks, - Kever Remove BOOTDELAY=0, SYS_CONSOLE_INFO_QUIET=y and enable more CMD to allow use of U-Boot cmdline. Add DM_ETH_PHY=y and PHY_REALTEK=y to support onboard ethernet PHY. Add PHY_ROCKCHIP_INNO_USB2=y, DM_USB_GADGET=y and remove USB_DWC2=y to allow full use of USB 2.0 host and otg ports. Enable EFI_LOADER to allow EFI boot. Signed-off-by: Jonas Karlman --- v2: Fix DEBUG_UART_BASE and disable DEBUG_UART_BOARD_INIT --- configs/evb-rk3308_defconfig | 37 +++- 1 file changed, 15 insertions(+), 22 deletions(-) diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index 9dc7d9c0caea..04a94e13a68a 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -3,41 +3,32 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_DEFAULT_DEVICE_TREE="rk3308-evb" +CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_DM_RESET=y CONFIG_ROCKCHIP_RK3308=y -CONFIG_SPL_DRIVERS_MISC=y CONFIG_TARGET_EVB_RK3308=y -CONFIG_DEBUG_UART_BASE=0xFF0C +CONFIG_DEBUG_UART_BASE=0xFF0E CONFIG_DEBUG_UART_CLOCK=2400 +# CONFIG_DEBUG_UART_BOARD_INIT is not set CONFIG_SYS_LOAD_ADDR=0xc00800 CONFIG_DEBUG_UART=y CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3308-evb.dtb" -CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set -CONFIG_SPL_MAX_SIZE=0x2 +CONFIG_SPL_MAX_SIZE=0x4 CONFIG_SPL_PAD_TO=0x7f8000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -# CONFIG_CMD_SLEEP is not set -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_CMD_RNG=y +CONFIG_CMD_KASLRSEED=y +CONFIG_CMD_REGULATOR=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" @@ -51,9 +42,11 @@ CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH_PHY=y CONFIG_ETH_DESIGNWARE=y CONFIG_GMAC_ROCKCHIP=y -CONFIG_PHY=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y CONFIG_PINCTRL=y CONFIG_REGULATOR_PWM=y CONFIG_DM_REGULATOR_FIXED=y @@ -62,15 +55,15 @@ CONFIG_RAM=y CONFIG_BAUDRATE=150 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSINFO=y CONFIG_SYSRESET=y CONFIG_USB=y +CONFIG_DM_USB_GADGET=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_DWC2=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_SPL_TINY_MEMSET=y +CONFIG_USB_FUNCTION_ROCKUSB=y CONFIG_LZO=y CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set
Re: [PATCH v2 10/14] rockchip: rk3308: Sync device tree from linux v6.8
On 2024/4/9 02:14, Jonas Karlman wrote:
Sync device tree from linux v6.8 and rename the rockchip,rk3308-mac
compatible in gmac_rockchip driver to match upstream linux.
Also move rk3308-roc-cc gmac node to u-boot.dtsi to not break features
not enabled in upstream device tree.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: Sort bootph-all prop after compatible and reg props
---
arch/arm/dts/rk3308-evb.dts | 104 +-
arch/arm/dts/rk3308-roc-cc-u-boot.dtsi| 19 +
arch/arm/dts/rk3308-roc-cc.dts| 83 +-
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi |4 +
arch/arm/dts/rk3308-rock-pi-s.dts | 100 +-
arch/arm/dts/rk3308-u-boot.dtsi | 14 +-
arch/arm/dts/rk3308.dtsi | 1205 +++--
drivers/net/gmac_rockchip.c |2 +-
8 files changed, 837 insertions(+), 694 deletions(-)
diff --git a/arch/arm/dts/rk3308-evb.dts b/arch/arm/dts/rk3308-evb.dts
index 124a24086684..184b84fdde07 100644
--- a/arch/arm/dts/rk3308-evb.dts
+++ b/arch/arm/dts/rk3308-evb.dts
@@ -23,7 +23,7 @@
poll-interval = <100>;
keyup-threshold-microvolt = <180>;
- func-key {
+ button-func {
linux,code = ;
label = "function";
press-threshold-microvolt = <18000>;
@@ -37,31 +37,31 @@
poll-interval = <100>;
keyup-threshold-microvolt = <180>;
- esc-key {
+ button-esc {
linux,code = ;
label = "micmute";
press-threshold-microvolt = <113>;
};
- home-key {
+ button-home {
linux,code = ;
label = "mode";
press-threshold-microvolt = <901000>;
};
- menu-key {
+ button-menu {
linux,code = ;
label = "play";
press-threshold-microvolt = <624000>;
};
- vol-down-key {
+ button-down {
linux,code = ;
label = "volume down";
press-threshold-microvolt = <30>;
};
- vol-up-key {
+ button-up {
linux,code = ;
label = "volume up";
press-threshold-microvolt = <18000>;
@@ -75,115 +75,115 @@
pinctrl-names = "default";
pinctrl-0 = <_key>;
- power {
+ key-power {
gpios = < RK_PA6 GPIO_ACTIVE_LOW>;
linux,code = ;
label = "GPIO Key Power";
- wakeup-source;
debounce-interval = <100>;
+ wakeup-source;
};
};
vcc12v_dcin: vcc12v-dcin {
compatible = "regulator-fixed";
regulator-name = "vcc12v_dcin";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <1200>;
regulator-max-microvolt = <1200>;
+ regulator-always-on;
+ regulator-boot-on;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
- regulator-always-on;
- regulator-boot-on;
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
- vin-supply = <_dcin>;
- };
-
- vdd_core: vdd-core {
- compatible = "pwm-regulator";
- pwms = < 0 5000 1>;
- regulator-name = "vdd_core";
- regulator-min-microvolt = <827000>;
- regulator-max-microvolt = <134>;
regulator-always-on;
regulator-boot-on;
- regulator-settling-time-up-us = <250>;
- pwm-supply = <_sys>;
- };
-
- vdd_log: vdd-log {
- compatible = "regulator-fixed";
- regulator-name = "vdd_log";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <105>;
- regulator-max-microvolt = <105>;
- vin-supply = <_sys>;
- };
-
- vdd_1v0: vdd-1v0 {
- compatible = "regulator-fixed";
- regulator-name = "vdd_1v0";
- regulator-always-on;
- regulator-boot-on;
- regulator-min-microvolt = <100>;
- regulator-max-microvolt = <100>;
- vin-supply = <_sys>;
+ vin-supply = <_dcin>;
};
vccio_sdio: vcc_1v8: vcc-1v8 {
compatible =
Re: [PATCH v2 09/14] phy: rockchip-inno-usb2: Add support for RK3308
On 2024/4/9 02:14, Jonas Karlman wrote:
Add clkout_ctl and phy_sus regs to support USB2PHY for RK3308.
Based on linux commit 31f840e7ff3e ("phy: phy-rockchip-inno-usb2: add
support for RK3308 USB phy").
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: No change
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 20 +++
1 file changed, 20 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index d392aed2d4de..43f6e020a6a0 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -329,6 +329,22 @@ bind_fail:
return ret;
}
+static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
+ {
+ .reg = 0x100,
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus= { 0x0100, 1, 0, 2, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus= { 0x0104, 1, 0, 2, 1 },
+ }
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rk3328_usb2phy_cfgs[] = {
{
.reg = 0x100,
@@ -442,6 +458,10 @@ static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[]
= {
};
static const struct udevice_id rockchip_usb2phy_ids[] = {
+ {
+ .compatible = "rockchip,rk3308-usb2phy",
+ .data = (ulong)_phy_cfgs,
+ },
{
.compatible = "rockchip,rk3328-usb2phy",
.data = (ulong)_usb2phy_cfgs,
Re: [PATCH v2 08/14] clk: rockchip: rk3308: Add dummy support for USB480M clock
On 2024/4/9 02:14, Jonas Karlman wrote:
Add dummy support for setting parent of USB480M clock.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: No change
---
drivers/clk/rockchip/clk_rk3308.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3308.c
b/drivers/clk/rockchip/clk_rk3308.c
index 7515fc8bb244..c46b58e31626 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -1085,6 +1085,8 @@ static ulong rk3308_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_RTC32K:
ret = rk3308_rtc32k_set_clk(priv, clk->id, rate);
break;
+ case USB480M:
+ return 0;
default:
return -ENOENT;
}
@@ -1117,6 +1119,8 @@ static int __maybe_unused rk3308_clk_set_parent(struct
clk *clk, struct clk *par
switch (clk->id) {
case SCLK_MAC:
return rk3308_mac_set_parent(clk, parent);
+ case USB480M:
+ return 0;
default:
break;
}
Re: [PATCH v2 07/14] clk: rockchip: rk3308: Add support for SCLK_RTC32K clock
On 2024/4/9 02:14, Jonas Karlman wrote:
From: Finley Xiao
Add support to get and set the SCLK_RTC32K clock rate.
Signed-off-by: Finley Xiao
[jo...@kwiboo.se: Update commit message]
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: No change
---
arch/arm/include/asm/arch-rk3308/cru_rk3308.h | 14 +++
drivers/clk/rockchip/clk_rk3308.c | 95 +++
2 files changed, 109 insertions(+)
diff --git a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
index 84b63e4d5682..091ae82d7cc1 100644
--- a/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
+++ b/arch/arm/include/asm/arch-rk3308/cru_rk3308.h
@@ -147,6 +147,20 @@ enum {
CORE_DIV_CON_SHIFT = 0,
CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
+ /* CRU_CLK_SEL2_CON */
+ CLK_RTC32K_SEL_SHIFT= 8,
+ CLK_RTC32K_SEL_MASK = 3 << CLK_RTC32K_SEL_SHIFT,
+ CLK_RTC32K_IO = 0,
+ CLK_RTC32K_PVTM,
+ CLK_RTC32K_FRAC_DIV,
+ CLK_RTC32K_DIV,
+
+ /* CRU_CLK_SEL3_CON */
+ CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_RTC32K_FRAC_NUMERATOR_MASK = 0x << 16,
+ CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_RTC32K_FRAC_DENOMINATOR_MASK= 0x,
+
/* CRU_CLK_SEL5_CON */
BUS_PLL_SEL_SHIFT = 6,
BUS_PLL_SEL_MASK= 0x3 << BUS_PLL_SEL_SHIFT,
diff --git a/drivers/clk/rockchip/clk_rk3308.c
b/drivers/clk/rockchip/clk_rk3308.c
index 7755b0161118..7515fc8bb244 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -65,6 +65,57 @@ static struct rockchip_pll_clock rk3308_pll_clks[] = {
RK3308_MODE_CON, 6, 10, 0, NULL),
};
+/*
+ *
+ * rational_best_approximation(31415, 1,
+ * (1 << 8) - 1, (1 << 5) - 1, , );
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+
static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
{
struct rk3308_cru *cru = priv->cru;
@@ -832,6 +883,44 @@ static ulong rk3308_crypto_set_clk(struct rk3308_clk_priv
*priv, ulong clk_id,
return rk3308_crypto_get_clk(priv, clk_id);
}
+static ulong rk3308_rtc32k_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
+{
+ struct rk3308_cru *cru = priv->cru;
+ unsigned long m, n;
+ u32 con, fracdiv;
+
+ con = readl(>clksel_con[2]);
+ if ((con & CLK_RTC32K_SEL_MASK) >> CLK_RTC32K_SEL_SHIFT !=
+ CLK_RTC32K_FRAC_DIV)
+ return -EINVAL;
+
+ fracdiv = readl(>clksel_con[3]);
+ m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK;
+ m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT;
+ n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK;
+ n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT;
+
+ return OSC_HZ * m / n;
+}
+
+static ulong rk3308_rtc32k_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
+ ulong hz)
+{
+ struct rk3308_cru *cru = priv->cru;
+ unsigned long m, n, val;
+
+ rational_best_approximation(hz, OSC_HZ,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ , );
+ val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n;
+ writel(val, >clksel_con[3]);
+ rk_clrsetreg(>clksel_con[2], CLK_RTC32K_SEL_MASK,
+CLK_RTC32K_FRAC_DIV << CLK_RTC32K_SEL_SHIFT);
+
+ return rk3308_rtc32k_get_clk(priv, clk_id);
+}
+
Re: [PATCH v2 06/14] rockchip: rk3308: Fix loading FIT from SD-card when booting from eMMC
On 2024/4/9 02:14, Jonas Karlman wrote:
When RK3308 boards run SPL from eMMC and fail to load FIT from eMMC due
to it being missing or checksum validation fails there can be a fallback
to read FIT from SD-card. However, without proper pinctrl configuration
reading FIT from SD-card may fail:
U-Boot SPL 2024.04-rc4 (Mar 16 2024 - 12:36:12 +)
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
Card did not respond to voltage select! : -110
mmc_init: -95, time 12
spl: mmc init failed with error: -95
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices (err=-6)
### ERROR ### Please RESET the board ###
Fix this by tagging related emmc and sdmmc pinctrl nodes with bootph
props. Also sort and move common nodes shared by all boards to the SoC
u-boot.dtsi.
Imply SPL_PINCTRL and SPL_DM_SEQ_ALIAS to apply correct pinconf before
trying to load FIT from a device.
Move u-boot,spl-boot-order to soc u-boot.dtsi and define both sdmmc and
emmc nodes as fallback.
Also fix boot from eMMC (SD NAND) on ROCK Pi S by using correct pinctrl.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: Add bootph-some-ram to pinctrl nodes
---
arch/arm/dts/rk3308-evb-u-boot.dtsi | 11 ++-
arch/arm/dts/rk3308-roc-cc-u-boot.dtsi| 15 ++--
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi | 35 --
arch/arm/dts/rk3308-u-boot.dtsi | 85 +--
arch/arm/mach-rockchip/Kconfig| 2 +
configs/evb-rk3308_defconfig | 2 +-
configs/roc-cc-rk3308_defconfig | 4 +-
configs/rock-pi-s-rk3308_defconfig| 2 +-
8 files changed, 114 insertions(+), 42 deletions(-)
diff --git a/arch/arm/dts/rk3308-evb-u-boot.dtsi
b/arch/arm/dts/rk3308-evb-u-boot.dtsi
index d15ba94d37b6..007a69f9a60e 100644
--- a/arch/arm/dts/rk3308-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-evb-u-boot.dtsi
@@ -4,14 +4,11 @@
*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl",
- };
-};
-
{
bootph-all;
clock-frequency = <2400>;
- status = "okay";
+};
+
+_xfer {
+ bootph-all;
};
diff --git a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
index 97d922c435d4..d823ac00c771 100644
--- a/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-roc-cc-u-boot.dtsi
@@ -4,14 +4,19 @@
*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl",
- };
+ {
+ bootph-pre-ram;
};
{
bootph-all;
clock-frequency = <2400>;
- status = "okay";
+};
+
+_xfer {
+ bootph-all;
+};
+
+_sd {
+ bootph-pre-ram;
};
diff --git a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
index d88dee80573e..e458fb3142ee 100644
--- a/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
@@ -4,39 +4,30 @@
*/
#include "rk3308-u-boot.dtsi"
-/ {
- chosen {
- u-boot,spl-boot-order = "same-as-spl", ,
- };
+ {
+ cap-sd-highspeed;
+ pinctrl-names = "default";
+ pinctrl-0 = <_clk _cmd _bus4>;
};
- {
- bootph-all;
-};
-
- {
+_bus4 {
+ bootph-pre-ram;
bootph-some-ram;
-
- uart0 {
- bootph-some-ram;
- };
- rtc {
- bootph-some-ram;
- };
};
-_xfer {
- bootph-some-ram;
+ {
+ bootph-all;
+ clock-frequency = <2400>;
};
_cts {
- bootph-some-ram;
+ bootph-all;
};
_rts {
- bootph-some-ram;
+ bootph-all;
};
-_32k {
- bootph-some-ram;
+_xfer {
+ bootph-all;
};
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index fa31c838d34d..26e1a94f2e1a 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -11,6 +11,10 @@
mmc1 =
};
+ chosen {
+ u-boot,spl-boot-order = "same-as-spl", ,
+ };
+
otp: nvmem@ff21 {
compatible = "rockchip,rk3308-otp";
reg = <0x0 0xff21 0x0 0x4000>;
@@ -42,21 +46,92 @@
};
{
+ bootph-pre-ram;
+ bootph-some-ram;
+
/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
u-boot,spl-fifo-mode;
+};
+
+_bus8 {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+_clk {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+_cmd {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+ {
bootph-all;
};
- {
+_pull_none {
bootph-all;
- u-boot,spl-fifo-mode;
};
- {
+_pull_none_4ma {
+ bootph-pre-ram;
+ bootph-some-ram;
+};
+
+_pull_none_8ma {
+ bootph-pre-ram;
+
Re: [PATCH v2 05/14] rockchip: rk3308: Enable random generator
On 2024/4/9 02:14, Jonas Karlman wrote:
The RK3308 SoC contain a crypto engine block that can generate random
numbers.
Add rng node to soc u-boot.dtsi and enable Kconfig options to take
advantage of the random generator.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: No change
---
arch/arm/dts/rk3308-u-boot.dtsi | 5 +
arch/arm/mach-rockchip/Kconfig | 2 ++
2 files changed, 7 insertions(+)
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index 436f66d1b87d..fa31c838d34d 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -26,6 +26,11 @@
reg = <0x07 0x10>;
};
};
+
+ rng: rng@ff2f {
+ compatible = "rockchip,cryptov2-rng";
+ reg = <0x0 0xff2f 0x0 0x4000>;
+ };
};
{
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 6e07a70bf4ae..fa5917236a43 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -162,9 +162,11 @@ config ROCKCHIP_RK3308
select SPL_LOAD_FIT
imply ARMV8_CRYPTO
imply ARMV8_SET_SMPEN
+ imply DM_RNG
imply LEGACY_IMAGE_FORMAT
imply MISC
imply MISC_INIT_R
+ imply RNG_ROCKCHIP
imply ROCKCHIP_COMMON_BOARD
imply ROCKCHIP_OTP
imply SPL_CLK
Re: [PATCH v2 04/14] rockchip: rk3308: Generate ethaddr based on cpu id
On 2024/4/9 02:14, Jonas Karlman wrote:
Like other Rockchip SoCs the RK3308 has cpu id programmed into OTP
memory. The rockchip_otp driver already support the RK3308 variant.
However, the device tree is missing a node to enable use of OTP.
Add the missing otp node to soc u-boot.dtsi, enable the rockchip_otp
driver and enable use of misc_init_r() to set ethaddr based on cpu id.
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: Add clocks and resets props
---
arch/arm/dts/rk3308-u-boot.dtsi | 16
arch/arm/mach-rockchip/Kconfig | 3 +++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/dts/rk3308-u-boot.dtsi b/arch/arm/dts/rk3308-u-boot.dtsi
index db2c20a7055e..436f66d1b87d 100644
--- a/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/arch/arm/dts/rk3308-u-boot.dtsi
@@ -10,6 +10,22 @@
mmc0 =
mmc1 =
};
+
+ otp: nvmem@ff21 {
+ compatible = "rockchip,rk3308-otp";
+ reg = <0x0 0xff21 0x0 0x4000>;
+ clocks = < SCLK_OTP_USR>, < PCLK_OTP_NS>,
+< PCLK_OTP_PHY>;
+ clock-names = "otp", "apb_pclk", "phy";
+ resets = < SRST_OTP_PHY>;
+ reset-names = "phy";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_id: id@7 {
+ reg = <0x07 0x10>;
+ };
+ };
};
{
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index 71c5945b5742..6e07a70bf4ae 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -163,7 +163,10 @@ config ROCKCHIP_RK3308
imply ARMV8_CRYPTO
imply ARMV8_SET_SMPEN
imply LEGACY_IMAGE_FORMAT
+ imply MISC
+ imply MISC_INIT_R
imply ROCKCHIP_COMMON_BOARD
+ imply ROCKCHIP_OTP
imply SPL_CLK
imply SPL_FIT_SIGNATURE
imply SPL_RAM
Re: [PATCH v2 03/14] rockchip: rk3308: Enable ARMv8 crypto and FIT checksum validation
On 2024/4/9 02:14, Jonas Karlman wrote: The RK3308 SoC support ARMv8 Cryptography Extensions and use of the ARMv8 crypto extensions help speed up FIT checksum validation in SPL. Imply ARMV8_SET_SMPEN and ARMV8_CRYPTO to take advantage of the crypto extensions for SHA256 when validating checksum of FIT images. Imply SPL_FIT_SIGNATURE and LEGACY_IMAGE_FORMAT to enable FIT checksum validation on all RK3308 boards. Also disable CONFIG_SPL_RAW_IMAGE_SUPPORT in board defconfigs to ensure SPL does not try to jump to code that failed checksum validation. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: No change --- arch/arm/mach-rockchip/Kconfig | 4 configs/evb-rk3308_defconfig | 1 + configs/roc-cc-rk3308_defconfig| 1 + configs/rock-pi-s-rk3308_defconfig | 1 + 4 files changed, 7 insertions(+) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 2fde8655d18a..71c5945b5742 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -160,8 +160,12 @@ config ROCKCHIP_RK3308 select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM select SPL_LOAD_FIT + imply ARMV8_CRYPTO + imply ARMV8_SET_SMPEN + imply LEGACY_IMAGE_FORMAT imply ROCKCHIP_COMMON_BOARD imply SPL_CLK + imply SPL_FIT_SIGNATURE imply SPL_RAM imply SPL_REGMAP imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/configs/evb-rk3308_defconfig b/configs/evb-rk3308_defconfig index d57b2f6b8e55..6a6d2540317d 100644 --- a/configs/evb-rk3308_defconfig +++ b/configs/evb-rk3308_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/roc-cc-rk3308_defconfig b/configs/roc-cc-rk3308_defconfig index 5e8f51ec01e3..2f4a160acc24 100644 --- a/configs/roc-cc-rk3308_defconfig +++ b/configs/roc-cc-rk3308_defconfig @@ -20,6 +20,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set diff --git a/configs/rock-pi-s-rk3308_defconfig b/configs/rock-pi-s-rk3308_defconfig index 1e9cd2c0fc7e..b0ad4d6ce354 100644 --- a/configs/rock-pi-s-rk3308_defconfig +++ b/configs/rock-pi-s-rk3308_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_MAX_SIZE=0x2 CONFIG_SPL_PAD_TO=0x7f8000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_CMD_BDI is not set # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_ELF is not set
Re: [PATCH v2 02/14] rockchip: rk3308: Sort imply statements alphabetically
On 2024/4/9 02:13, Jonas Karlman wrote: Sort imply statements under ROCKCHIP_RK3308 alphabetically and remove the config SPL_SERIAL statement from soc Kconfig file, it is already implyed in arch Kconfig. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: No change --- arch/arm/mach-rockchip/Kconfig| 8 arch/arm/mach-rockchip/rk3308/Kconfig | 3 --- 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index f68a0a48949a..2fde8655d18a 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -161,13 +161,13 @@ config ROCKCHIP_RK3308 select SPL_ATF_NO_PLATFORM_PARAM select SPL_LOAD_FIT imply ROCKCHIP_COMMON_BOARD - imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_CLK - imply SPL_REGMAP - imply SPL_SYSCON imply SPL_RAM - imply SPL_SERIAL + imply SPL_REGMAP + imply SPL_ROCKCHIP_COMMON_BOARD imply SPL_SEPARATE_BSS + imply SPL_SERIAL + imply SPL_SYSCON help The Rockchip RK3308 is a ARM-based Soc which embedded with quad Cortex-A35 and highly integrated audio interfaces. diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 749e9995d91f..fac966207a92 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -23,9 +23,6 @@ config ROCKCHIP_COMMON_STACK_ADDR config TEXT_BASE default 0x0060 -config SPL_SERIAL - default y - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig"
Re: [PATCH v2 01/14] board: rockchip: rk3308: Add device tree files and myself to MAINTAINERS
On 2024/4/9 02:13, Jonas Karlman wrote: Update MAINTAINERS files for RK3308 boards to include related device tree files. Also add myself as a reviewer for the ROCK Pi S board. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang Thanks, - Kever --- v2: No change --- board/firefly/firefly-rk3308/MAINTAINERS | 1 + board/rockchip/evb_rk3308/MAINTAINERS| 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/board/firefly/firefly-rk3308/MAINTAINERS b/board/firefly/firefly-rk3308/MAINTAINERS index e584038a2033..b70ff52ea741 100644 --- a/board/firefly/firefly-rk3308/MAINTAINERS +++ b/board/firefly/firefly-rk3308/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/firefly/firefly-rk3308/ F: configs/roc-cc-rk3308_defconfig F: include/configs/firefly_rk3308.h +F: arch/arm/dts/rk3308-roc-cc* diff --git a/board/rockchip/evb_rk3308/MAINTAINERS b/board/rockchip/evb_rk3308/MAINTAINERS index fe2c5f004c34..abffbb1eb0ab 100644 --- a/board/rockchip/evb_rk3308/MAINTAINERS +++ b/board/rockchip/evb_rk3308/MAINTAINERS @@ -4,10 +4,11 @@ S: Maintained F: board/rockchip/evb_rk3308 F: include/configs/evb_rk3308.h F: configs/evb-rk3308_defconfig +F: arch/arm/dts/rk3308-evb* ROCK-PI-S M: Akash Gajjar +R: Jonas Karlman S: Maintained F: configs/rock-pi-s-rk3308_defconfig -F: arch/arm/dts/rk3308-rock-pi-s.dts -F: arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi +F: arch/arm/dts/rk3308-rock-pi-s*
[PATCH v2 1/1] efi_loader: improve error handling in try_load_entry()
The image is not unloaded if a security violation occurs.
If efi_set_load_options() fails, we do not free the memory allocated for
the optional data. We do not unload the image.
* Unload the image if a security violation occurs.
* Free load_options if efi_set_load_options() fails.
* Unload the image if efi_set_load_options() fails.
Fixes: 53f6a5aa8626 ("efi_loader: Replace config option for initrd loading")
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Ilias Apalodimas
---
v2:
remove incorrect statement about uninitialized 'size' from commit
message
---
lib/efi_loader/efi_bootmgr.c | 97 +--
test/py/tests/test_efi_secboot/test_signed.py | 28 +++---
.../test_efi_secboot/test_signed_intca.py | 10 +-
.../tests/test_efi_secboot/test_unsigned.py | 6 +-
4 files changed, 70 insertions(+), 71 deletions(-)
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index 4ac519228a6..ca2ebdaa32f 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -613,9 +613,12 @@ static efi_status_t try_load_entry(u16 n, efi_handle_t
*handle,
void *load_option;
efi_uintn_t size;
efi_status_t ret;
+ u32 attributes;
- efi_create_indexed_name(varname, sizeof(varname), "Boot", n);
+ *handle = NULL;
+ *load_options = NULL;
+ efi_create_indexed_name(varname, sizeof(varname), "Boot", n);
load_option = efi_get_var(varname, _global_variable_guid, );
if (!load_option)
return EFI_LOAD_ERROR;
@@ -626,55 +629,54 @@ static efi_status_t try_load_entry(u16 n, efi_handle_t
*handle,
goto error;
}
- if (lo.attributes & LOAD_OPTION_ACTIVE) {
- u32 attributes;
-
- log_debug("trying to load \"%ls\" from %pD\n", lo.label,
- lo.file_path);
-
- if (EFI_DP_TYPE(lo.file_path, MEDIA_DEVICE, FILE_PATH)) {
- /* file_path doesn't contain a device path */
- ret = try_load_from_short_path(lo.file_path, handle);
- } else if (EFI_DP_TYPE(lo.file_path, MESSAGING_DEVICE,
MSG_URI)) {
- if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT))
- ret = try_load_from_uri_path(
- (struct efi_device_path_uri
*)lo.file_path,
- lo.label, handle);
- else
- ret = EFI_LOAD_ERROR;
- } else {
- ret = try_load_from_media(lo.file_path, handle);
- }
- if (ret != EFI_SUCCESS) {
- log_warning("Loading %ls '%ls' failed\n",
- varname, lo.label);
- goto error;
- }
+ if (!(lo.attributes & LOAD_OPTION_ACTIVE)) {
+ ret = EFI_LOAD_ERROR;
+ goto error;
+ }
- attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
-EFI_VARIABLE_RUNTIME_ACCESS;
- ret = efi_set_variable_int(u"BootCurrent",
- _global_variable_guid,
- attributes, sizeof(n), , false);
- if (ret != EFI_SUCCESS)
- goto unload;
- /* try to register load file2 for initrd's */
- if (IS_ENABLED(CONFIG_EFI_LOAD_FILE2_INITRD)) {
- ret = efi_initrd_register();
- if (ret != EFI_SUCCESS)
- goto unload;
- }
+ log_debug("trying to load \"%ls\" from %pD\n", lo.label, lo.file_path);
- log_info("Booting: %ls\n", lo.label);
+ if (EFI_DP_TYPE(lo.file_path, MEDIA_DEVICE, FILE_PATH)) {
+ /* file_path doesn't contain a device path */
+ ret = try_load_from_short_path(lo.file_path, handle);
+ } else if (EFI_DP_TYPE(lo.file_path, MESSAGING_DEVICE, MSG_URI)) {
+ if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT))
+ ret = try_load_from_uri_path(
+ (struct efi_device_path_uri *)lo.file_path,
+ lo.label, handle);
+ else
+ ret = EFI_LOAD_ERROR;
} else {
- ret = EFI_LOAD_ERROR;
+ ret = try_load_from_media(lo.file_path, handle);
+ }
+ if (ret != EFI_SUCCESS) {
+ log_warning("Loading %ls '%ls' failed\n",
+ varname, lo.label);
+ goto error;
+ }
+
+ attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS |
+EFI_VARIABLE_RUNTIME_ACCESS;
+ ret = efi_set_variable_int(u"BootCurrent", _global_variable_guid,
+ attributes, sizeof(n), , false);
+ if
Re: [PATCH v2] mmc: rockchip_sdhci: Fix 4 blocks PIO mode read limit for RK35xx
On 2024/4/10 22:30, Jonas Karlman wrote:
The commit 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks
read in a single command") introduced a limit of number of blocks to
read to fix a Data End Bit Error on RK3568 and RK3588. This had a side
affect of significant slowing down reading FIT from eMMC.
After the commit 6de9d7b2f13c ("rockchip: rk35xx: Enable eMMC HS200 mode
by default") the limit of number of blocks to read workaround is no
longer necessary and at HS200+ a Data End Bit Error is no longer
happening using PIO mode.
Change this limitation to allow reading more than 4 blocks with a single
CMD18 command in PIO mode at HS200+ speed, keep using the 4 blocks
limitation when loadig FIT from eMMC at lower speed than HS200.
Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a single
command")
Signed-off-by: Jonas Karlman
Reviewed-by: Kever Yang
Thanks,
- Kever
---
v2: Move cfg->b_max configuration to set_ios_post() ops
This significantly speed up FIT loading from eMMC on RK3588 boards with
a mmc-hs200 prop in the sdhci node, and boards without a mmc-hs200 prop
continue to work.
---
drivers/mmc/rockchip_sdhci.c | 26 --
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index 706fb1235796..c889c7bc9855 100644
--- a/drivers/mmc/rockchip_sdhci.c
+++ b/drivers/mmc/rockchip_sdhci.c
@@ -391,6 +391,8 @@ static int rk3568_sdhci_config_dll(struct sdhci_host *host,
u32 clock, bool enab
static int rk3568_sdhci_set_ios_post(struct sdhci_host *host)
{
struct mmc *mmc = host->mmc;
+ struct rockchip_sdhc_plat *plat = dev_get_plat(mmc->dev);
+ struct mmc_config *cfg = >cfg;
u32 reg;
reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
@@ -437,6 +439,20 @@ static int rk3568_sdhci_set_ios_post(struct sdhci_host
*host)
sdhci_writew(host, reg, DWCMSHC_EMMC_EMMC_CTRL);
+ /*
+* Reading more than 4 blocks with a single CMD18 command in PIO mode
+* triggers Data End Bit Error using a slower mode than HS200. Limit to
+* reading max 4 blocks in one command when using PIO mode.
+*/
+ if (!(host->flags & USE_DMA)) {
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == MMC_HS_400_ES)
+ cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+ else
+ cfg->b_max = 4;
+ }
+
return 0;
}
@@ -598,16 +614,6 @@ static int rockchip_sdhci_probe(struct udevice *dev)
dev_read_bool(dev, "u-boot,spl-fifo-mode"))
host->flags &= ~USE_DMA;
- /*
-* Reading more than 4 blocks with a single CMD18 command in PIO mode
-* triggers Data End Bit Error on RK3568 and RK3588. Limit to reading
-* max 4 blocks in one command when using PIO mode.
-*/
- if (!(host->flags & USE_DMA) &&
- (device_is_compatible(dev, "rockchip,rk3568-dwcmshc") ||
-device_is_compatible(dev, "rockchip,rk3588-dwcmshc")))
- cfg->b_max = 4;
-
return sdhci_probe(dev);
}
Re: [PATCH v3 11/11] rockchip: rk356x: use DRAM banks from ATAGS
On 2024/4/15 22:17, Quentin Schulz wrote: From: Quentin Schulz RK356x-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/anbernic-rgxx3-rk3566_defconfig | 1 - configs/bpi-r2-pro-rk3568_defconfig | 1 - configs/evb-rk3568_defconfig | 1 - configs/generic-rk3568_defconfig | 1 - configs/lubancat-2-rk3568_defconfig | 1 - configs/nanopi-r5c-rk3568_defconfig | 1 - configs/nanopi-r5s-rk3568_defconfig | 1 - configs/odroid-m1-rk3568_defconfig| 1 - configs/pinetab2-rk3566_defconfig | 1 - configs/quartz64-a-rk3566_defconfig | 1 - configs/quartz64-b-rk3566_defconfig | 1 - configs/radxa-cm3-io-rk3566_defconfig | 1 - configs/radxa-e25-rk3568_defconfig| 1 - configs/rock-3a-rk3568_defconfig | 1 - configs/soquartz-blade-rk3566_defconfig | 1 - configs/soquartz-cm4-rk3566_defconfig | 1 - configs/soquartz-model-a-rk3566_defconfig | 1 - 17 files changed, 17 deletions(-) diff --git a/configs/anbernic-rgxx3-rk3566_defconfig b/configs/anbernic-rgxx3-rk3566_defconfig index c8c9238f96f..aa3809e00c1 100644 --- a/configs/anbernic-rgxx3-rk3566_defconfig +++ b/configs/anbernic-rgxx3-rk3566_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3566-anbernic-rgxx3" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y diff --git a/configs/bpi-r2-pro-rk3568_defconfig b/configs/bpi-r2-pro-rk3568_defconfig index 5cc95241ba4..0f85dc63c55 100644 --- a/configs/bpi-r2-pro-rk3568_defconfig +++ b/configs/bpi-r2-pro-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2-pro" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig index 6e8061f5f48..f2f429d33c4 100644 --- a/configs/evb-rk3568_defconfig +++ b/configs/evb-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/generic-rk3568_defconfig b/configs/generic-rk3568_defconfig index e7d5e55bbfd..8f4a6259a27 100644 --- a/configs/generic-rk3568_defconfig +++ b/configs/generic-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-generic" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/lubancat-2-rk3568_defconfig b/configs/lubancat-2-rk3568_defconfig index 1c50a0ccbe6..ea67b6a7286 100644 --- a/configs/lubancat-2-rk3568_defconfig +++ b/configs/lubancat-2-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat-2" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5c-rk3568_defconfig b/configs/nanopi-r5c-rk3568_defconfig index 0f1a9461a0c..00743b7f926 100644 --- a/configs/nanopi-r5c-rk3568_defconfig +++ b/configs/nanopi-r5c-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5c" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/nanopi-r5s-rk3568_defconfig b/configs/nanopi-r5s-rk3568_defconfig index 4ebf0cc9ee8..91e3a19dea6 100644 --- a/configs/nanopi-r5s-rk3568_defconfig +++ b/configs/nanopi-r5s-rk3568_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3568-nanopi-r5s" CONFIG_ROCKCHIP_RK3568=y CONFIG_SPL_SERIAL=y diff --git a/configs/odroid-m1-rk3568_defconfig b/configs/odroid-m1-rk3568_defconfig index b5ed9e4bc98..e749f9af9d2 100644 --- a/configs/odroid-m1-rk3568_defconfig +++ b/configs/odroid-m1-rk3568_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x1000
Re: [PATCH v3 10/11] rockchip: rk3588: use DRAM banks from ATAGS
On 2024/4/15 22:17, Quentin Schulz wrote: From: Quentin Schulz RK3588-based devices now support creating DRAM banks with proper holes by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism instead. The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for reading banks from ATAGS, so let's use the default value instead. Co-developed-by: Chris Morgan Signed-off-by: Chris Morgan Signed-off-by: Quentin Schulz Reviewed-by: Kever Yang Thanks, - Kever --- configs/jaguar-rk3588_defconfig | 1 - configs/neu6a-io-rk3588_defconfig | 1 - configs/neu6b-io-rk3588_defconfig | 1 - 3 files changed, 3 deletions(-) diff --git a/configs/jaguar-rk3588_defconfig b/configs/jaguar-rk3588_defconfig index 3233b75cee9..f29505ea150 100644 --- a/configs/jaguar-rk3588_defconfig +++ b/configs/jaguar-rk3588_defconfig @@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y CONFIG_SPL_GPIO=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SF_DEFAULT_SPEED=2400 CONFIG_SF_DEFAULT_MODE=0x2000 CONFIG_ENV_SIZE=0x1f000 diff --git a/configs/neu6a-io-rk3588_defconfig b/configs/neu6a-io-rk3588_defconfig index 307a540f424..2b939e6795f 100644 --- a/configs/neu6a-io-rk3588_defconfig +++ b/configs/neu6a-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6a-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y diff --git a/configs/neu6b-io-rk3588_defconfig b/configs/neu6b-io-rk3588_defconfig index 9ef2bb21fff..d0fa0dca7ac 100644 --- a/configs/neu6b-io-rk3588_defconfig +++ b/configs/neu6b-io-rk3588_defconfig @@ -2,7 +2,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=2400 CONFIG_ARCH_ROCKCHIP=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_DEFAULT_DEVICE_TREE="rk3588-edgeble-neu6b-io" CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_SERIAL=y
Re: [PATCH v3 09/11] rockchip: turing-rk1-rk3588: use DRAM banks from ATAGS
On 2024/4/15 22:17, Quentin Schulz wrote:
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the turing-rk1-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/turing/turing-rk1-rk3588/Makefile| 6
board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c | 39 --
configs/turing-rk1-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/turing/turing-rk1-rk3588/Makefile
b/board/turing/turing-rk1-rk3588/Makefile
deleted file mode 100644
index a979d8023aa..000
--- a/board/turing/turing-rk1-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += turing-rk1-rk3588.o
diff --git a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
b/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
deleted file mode 100644
index e2338a2a35a..000
--- a/board/turing/turing-rk1-rk3588/turing-rk1-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int turing_rk1_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return turing_rk1_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/turing-rk1-rk3588_defconfig
b/configs/turing-rk1-rk3588_defconfig
index 07f7b848529..2195b03d57a 100644
--- a/configs/turing-rk1-rk3588_defconfig
+++ b/configs/turing-rk1-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-turing-rk1"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-turing-rk1.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
Re: [PATCH v3 07/11] rockchip: evb_rk3588 et al.: use DRAM banks from ATAGS
On 2024/4/15 22:17, Quentin Schulz wrote:
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the evb_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
All defconfigs using the CONFIG_TARGET_EVB_RK3588 are updated at once
since they are impacted by this change.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/rockchip/evb_rk3588/Makefile | 6 -
board/rockchip/evb_rk3588/evb-rk3588.c | 39
configs/coolpi-4b-rk3588s_defconfig | 2 --
configs/coolpi-cm5-evb-rk3588_defconfig | 2 --
configs/evb-rk3588_defconfig | 2 --
configs/generic-rk3588_defconfig | 2 --
configs/orangepi-5-plus-rk3588_defconfig | 2 --
configs/orangepi-5-rk3588s_defconfig | 2 --
8 files changed, 57 deletions(-)
diff --git a/board/rockchip/evb_rk3588/Makefile
b/board/rockchip/evb_rk3588/Makefile
deleted file mode 100644
index 240d2ec597e..000
--- a/board/rockchip/evb_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += evb-rk3588.o
diff --git a/board/rockchip/evb_rk3588/evb-rk3588.c
b/board/rockchip/evb_rk3588/evb-rk3588.c
deleted file mode 100644
index caf94d8d29c..000
--- a/board/rockchip/evb_rk3588/evb-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/coolpi-4b-rk3588s_defconfig
b/configs/coolpi-4b-rk3588s_defconfig
index a0fe3708344..2608bb67679 100644
--- a/configs/coolpi-4b-rk3588s_defconfig
+++ b/configs/coolpi-4b-rk3588s_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588s-coolpi-4b"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-coolpi-4b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/coolpi-cm5-evb-rk3588_defconfig
b/configs/coolpi-cm5-evb-rk3588_defconfig
index fc17660da2a..c5bb7a42957 100644
--- a/configs/coolpi-cm5-evb-rk3588_defconfig
+++ b/configs/coolpi-cm5-evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-coolpi-cm5-evb"
@@ -23,7 +22,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-coolpi-cm5-evb.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
diff --git a/configs/evb-rk3588_defconfig b/configs/evb-rk3588_defconfig
index c8db04c076e..187cf26a5c9 100644
--- a/configs/evb-rk3588_defconfig
+++ b/configs/evb-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb1-v10"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
Re: [PATCH v3 08/11] rockchip: toybrick_rk3588: use DRAM banks from ATAGS
On 2024/4/15 22:17, Quentin Schulz wrote:
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the toybrick_rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/rockchip/toybrick_rk3588/Makefile | 6
board/rockchip/toybrick_rk3588/toybrick-rk3588.c | 39
configs/toybrick-rk3588_defconfig| 2 --
3 files changed, 47 deletions(-)
diff --git a/board/rockchip/toybrick_rk3588/Makefile
b/board/rockchip/toybrick_rk3588/Makefile
deleted file mode 100644
index 75d4d9438f7..000
--- a/board/rockchip/toybrick_rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
-#
-
-obj-y += toybrick-rk3588.o
diff --git a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
b/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
deleted file mode 100644
index e3217f70b50..000
--- a/board/rockchip/toybrick_rk3588/toybrick-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2024 Rockchip Electronics Co,. Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-static int rk3588_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rk3588_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/toybrick-rk3588_defconfig
b/configs/toybrick-rk3588_defconfig
index 6ee92e94313..675e7d89e12 100644
--- a/configs/toybrick-rk3588_defconfig
+++ b/configs/toybrick-rk3588_defconfig
@@ -2,7 +2,6 @@ CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_DEFAULT_DEVICE_TREE="rk3588-toybrick-x0"
CONFIG_ROCKCHIP_RK3588=y
CONFIG_SPL_SERIAL=y
@@ -16,7 +15,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-toybrick-x0.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
Re: [PATCH v3 06/11] rockchip: rock5b-rk3588: use DRAM banks from ATAGS
On 2024/4/15 22:16, Quentin Schulz wrote:
From: Quentin Schulz
RK3588-based devices now support creating DRAM banks with proper holes
by reading the ATAGS from Rockchip TPL blob, so let's use that mechanism
instead.
Since ft_board_setup isn't defined anymore, there's no need for
selecting CONFIG_OF_BOARD_SETUP.
Similarly, because the rock5b-rk3588.c would be empty, it is simply
removed, with the (would-be-empty) Makefile as well.
The CONFIG_NR_DRAM_BANK now defaults to 10 which is a safe bet for
reading banks from ATAGS, so let's use the default value instead.
Co-developed-by: Chris Morgan
Signed-off-by: Chris Morgan
Signed-off-by: Quentin Schulz
Reviewed-by: Kever Yang
Thanks,
- Kever
---
board/radxa/rock5b-rk3588/Makefile| 6 -
board/radxa/rock5b-rk3588/rock5b-rk3588.c | 39 ---
configs/rock5b-rk3588_defconfig | 2 --
3 files changed, 47 deletions(-)
diff --git a/board/radxa/rock5b-rk3588/Makefile
b/board/radxa/rock5b-rk3588/Makefile
deleted file mode 100644
index 95d813596da..000
--- a/board/radxa/rock5b-rk3588/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (c) 2022 Collabora Ltd.
-#
-
-obj-y += rock5b-rk3588.o
diff --git a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
b/board/radxa/rock5b-rk3588/rock5b-rk3588.c
deleted file mode 100644
index 5c3b52b9489..000
--- a/board/radxa/rock5b-rk3588/rock5b-rk3588.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2023 Collabora Ltd.
- */
-
-#include
-#include
-
-#ifdef CONFIG_OF_BOARD_SETUP
-int rock5b_add_reserved_memory_fdt_nodes(void *new_blob)
-{
- struct fdt_memory gap1 = {
- .start = 0x3fc00,
- .end = 0x3fc4f,
- };
- struct fdt_memory gap2 = {
- .start = 0x3fff0,
- .end = 0x3,
- };
- unsigned long flags = FDTDEC_RESERVED_MEMORY_NO_MAP;
- unsigned int ret;
-
- /*
-* Inject the reserved-memory nodes into the DTS
-*/
- ret = fdtdec_add_reserved_memory(new_blob, "gap1", , NULL, 0,
-NULL, flags);
- if (ret)
- return ret;
-
- return fdtdec_add_reserved_memory(new_blob, "gap2", , NULL, 0,
- NULL, flags);
-}
-
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
- return rock5b_add_reserved_memory_fdt_nodes(blob);
-}
-#endif
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig
index 58c7c44fb4f..3603e175a0b 100644
--- a/configs/rock5b-rk3588_defconfig
+++ b/configs/rock5b-rk3588_defconfig
@@ -3,7 +3,6 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=2400
CONFIG_ARCH_ROCKCHIP=y
-CONFIG_NR_DRAM_BANKS=2
CONFIG_SF_DEFAULT_SPEED=2400
CONFIG_SF_DEFAULT_MODE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="rk3588-rock-5b"
@@ -24,7 +23,6 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_OF_BOARD_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
