On Thu, 2022-11-10 at 15:34 +0800, Macpaul Lin wrote:
> From: Fabien Parent
>
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
> and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
> hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
> From: Fabien Parent
>
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
> and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
> hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
On Wed, 2022-11-09 at 17:33 +0800, Macpaul Lin wrote:
> On 11/9/22 15:32, Macpaul Lin wrote:
> >
> > On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote:
> > > On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
> > > > From: Fabien Parent
> > > >
On Wed, 2022-11-09 at 17:50 +0800, Macpaul Lin wrote:
> From: Fabien Parent
>
> The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
> and
> a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
> hosts,
> SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several
Hi Marek,
On Fri, 2023-02-17 at 14:35 +0100, Marek Vasut wrote:
> On 2/17/23 10:04, Chunfeng Yun wrote:
> > There are 4 USB controllers on MT8195, the controllers (IP1~IP3,
> > exclude IP0) have a wrong default SOF/ITP interval which is
> > calculated from the frame counter clock 24Mhz by
On Mon, 2023-02-13 at 22:00 +0100, Marek Vasut wrote:
> On 2/13/23 02:46, Chunfeng Yun (云春峰) wrote:
> > On Fri, 2023-02-10 at 11:32 +0100, Marek Vasut wrote:
> > > On 2/10/23 09:33, Chunfeng Yun wrote:
> > > [...]
> > > > @@ -50,6 +50,27 @@
> > > &g
On Fri, 2023-02-10 at 11:32 +0100, Marek Vasut wrote:
> On 2/10/23 09:33, Chunfeng Yun wrote:
> [...]
> > @@ -50,6 +50,27 @@
> > #define IPPC_U3_CTRL(p) (IPPC_U3_CTRL_0P + ((p) * 0x08))
> > #define IPPC_U2_CTRL(p) (IPPC_U2_CTRL_0P + ((p) * 0x08))
> >
> > +/* xHCI CSR */
> > +#define
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