board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Move CONFIG_MACH_TYPE to board configuration file
Alison Wang (6):
arm: mvf600: Add Vybrid MVF600 CPU support
arm: mvf600: Add
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
It aligns Vybrid MVF600 platform with i.MX platform. As there are
some differences between MVF600 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/mvf600 directory.
Signed-off-by: Alison Wang b18
. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v2:
- Use common iomux-v3 code
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6 ++
arch/arm/include/asm/imx-common/iomux-v3.h | 18
This patch adds FEC support for Vybrid MVF600 platform.
Add code to use RMII for MVF600.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v2:
- Use common FEC driver fec_mxc.c
drivers/net/fec_mxc.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers
This patch adds watchdog support for Vybrid MVF600 platform.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this driver on other
MVF600TWR is a board based on Vybrid MVF600 SoC.
This patch adds basic support for Vybrid MVF600TWR board.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
Changes in v2:
- Add an entry
This patch adds watchdog support for Vybrid MVF600 platform.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v3: None
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v3:
- Define PAD_CTL_PUE with PKE enabled
Changes in v2:
- Use common iomux-v3 code
arch/arm/imx-common/Makefile | 2 +-
arch/arm/imx-common/iomux-v3.c | 6
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C structures to set/read
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Move CONFIG_MACH_TYPE to board configuration file
Alison Wang (6):
arm: mvf600: Add Vybrid MVF600 CPU support
arm: mvf600: Add IOMUX support for Vybrid
the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v3:
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup()
Changes in v2:
- Use common FEC driver
MVF600TWR is a board based on Vybrid MVF600 SoC.
This patch adds basic support for Vybrid MVF600TWR board.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
Changes in v3:
- Replace BOOT_FROM
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU.
It aligns Vybrid MVF600 platform with i.MX platform. As there are
some differences between MVF600 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/mvf600 directory.
Signed-off-by: Alison Wang b18
This patch adds watchdog support for Vybrid VF610 platform.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v4:
- Rename mvf600 to vf610
Changes in v3: None
Changes in v2:
- Add watchdog support
- Use reset_cpu() in imx_watchdog.c
drivers/watchdog/Makefile | 2 +-
1 file
' to 'mvf600twr'
- Use standard method to set gd-ram_size
- Rewrite board_mmc_getcd() function
- Remove useless undef
- Remove hardcoded IP addresses and MAC addresses
- Move CONFIG_MACH_TYPE to board configuration file
Alison Wang (7
. A
CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v4:
- Rename MVF600 to VF610
- Define PAD_CTL_PUS_47K_UP and PAD_CTL_PUS_100K_UP with PAD_CTL_PUE enabled
- Reorganize the definitions
- Correct the spaces and tabs
Changes in v3:
- Define
This patch adds lpuart support for Vybrid VF610 platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v4: None
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C
This patch adds generic codes to support Freescale's Vybrid VF610 CPU.
It aligns Vybrid VF610 platform with i.MX platform. As there are
some differences between VF610 and i.MX platforms, the specific
codes are in the arch/arm/cpu/armv7/vf610 directory.
Signed-off-by: Alison Wang b18
This patch adds Vybrid VF610 to mxc_ocotp document.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v4: New
Changes in v3: None
Changes in v2: None
doc/README.mxc_ocotp | 1 +
1 file changed, 1 insertion(+)
diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp
index 9a53311
the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang b18...@freescale.com
Reviewed-by: Benoit Thebaudeau benoit.thebaud...@advansee.com
---
Changes in v4: None
Changes in v3:
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits
VF610TWR is a board based on Vybrid VF610 SoC.
This patch adds basic support for Vybrid VF610TWR board.
Signed-off-by: Alison Wang b18...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: TsiChung Liew tsicl...@gmail.com
---
Changes in v4:
- Rename directory name
-off-by: Alison Wang b18...@freescale.com
---
drivers/i2c/mxc_i2c.c | 62 +--
1 file changed, 55 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index a73b10b..85e3e8b 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/arm/cpu/armv7/vf610/generic.c| 7 +++
arch/arm/include/asm/arch-vf610/clock.h | 1 +
arch/arm/include/asm/arch-vf610
This series contain the I2C support for Freescale Vybrid VF610 platform and
VF610TWR board.
Alison Wang (2):
vf610: Add I2C support for Vybrid VF610 platform
I2C: mxc_i2c: Add support for Vybrid VF610 platform
arch/arm/cpu/armv7/vf610/generic.c| 7 +++
arch/arm
and general purpose applications.
Alison Wang (5):
vybrid: add vybrid CPU support
vybrid: add Freescale vybrid vf600 tower board support
vybrid: add uart driver support
vybrid: add eSDHC driver support
vybrid: add ethernet driver support
Makefile
This patch adds Freescale vybrid vf600 tower board support.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
board/freescale/vybrid/Makefile| 40 +++
board/freescale/vybrid/vybrid.c
This patch adds eSDHC driver support for vybrid platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
This patch adds uart driver support for vybrid platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
drivers/serial/Makefile| 1 +
drivers/serial/serial.c| 2 +
drivers
This patch adds ethernet driver support for vybrid platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/arm/include/asm/fec.h| 302 ++
arch
This patch uses the general ffs definition to replace the
platform ffs definition.
This patch also fixes the build error by adding hweightN
definition for m5329evb and m5373evb.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k
This patch fixes the build error for MCF537x. As the NANDFLASH_SIZE is
redefined in boards.cfg, it is needed to rename NANDFLASH_SIZE into
CONFIG_NANDFLASH_SIZE in include/configs/M5373EVB.h.
Signed-off-by: Alison Wang b18...@freescale.com
---
include/configs/M5373EVB.h | 10 +-
1
From: Alison Wang b18...@freescale.com
This patch cleans up checkpatch warnings about Use of volatile is usually
wrong
for ColdFire platform.
The first patch adds clear and set bits macros for ColdFire platform. These
macros can be used to clear and set multiple bits in a register using
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf5227x/cpu.c | 13 ++--
arch/m68k/cpu/mcf5227x/cpu_init.c | 140 +
arch/m68k/cpu/mcf5227x/interrupts.c | 15 ++--
arch/m68k/cpu/mcf5227x/speed.c| 40 +-
board
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf52x2/cpu.c | 115 +--
arch/m68k/cpu/mcf52x2/cpu_init.c | 252 +
arch/m68k/cpu/mcf52x2/interrupts.c| 40 +++---
arch/m68k/cpu/mcf52x2/speed.c | 19
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf5445x/cpu.c | 13 +-
arch/m68k/cpu/mcf5445x/cpu_init.c | 215 +
arch/m68k/cpu/mcf5445x/interrupts.c | 15 ++-
arch/m68k/cpu/mcf5445x/pci.c | 74 ++--
arch
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf547x_8x/cpu.c| 38 +++---
arch/m68k/cpu/mcf547x_8x/cpu_init.c | 84 +
arch/m68k/cpu/mcf547x_8x/interrupts.c | 15 +++---
arch/m68k/cpu/mcf547x_8x/pci.c| 59
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf532x/cpu.c | 33 ++--
arch/m68k/cpu/mcf532x/cpu_init.c | 304 +
arch/m68k/cpu/mcf532x/interrupts.c| 15 +-
arch/m68k/cpu/mcf532x/speed.c | 77 +
board
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/include/asm/io.h | 38 +-
1 files changed, 37 insertions(+), 1 deletions(-)
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index d86eaf9..50ed749 100644
--- a/arch/m68k
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf523x/cpu.c | 33 +
arch/m68k/cpu/mcf523x/cpu_init.c| 122 ++-
arch/m68k/cpu/mcf523x/interrupts.c | 15 ++--
arch/m68k/cpu/mcf523x/speed.c | 10 ++-
board
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 24 +++-
drivers/net/tsec.c | 7 +++
include/fsl_mdio.h | 3 +++
include/tsec.h | 7 ++-
4 files changed, 35
and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR
board.
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
From: York Sun york...@freescale.com
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: New file.
board/freescale/ls1021atwr/Makefile | 7 +
board/freescale/ls1021atwr/README | 109 +++
board/freescale/ls1021atwr/ls1021atwr.c | 499
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank.
From: York Sun york...@freescale.com
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v2: no change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
1 file changed,
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..792fc40 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Change log:
v2: Remove ethaddr/ipaddr
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.w...@freescale.com
/TWR board basic support patches.
Alison Wang (2):
arm: ls102xa: Add SD boot support for LS1021AQDS board
arm: ls102xa: Add SD boot support for LS1021ATWR board
Makefile | 15
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.w...@freescale.com
This series contain the support for Freescale LS102xA SoC and
LS1021AQDS/TWR board.
The QorIQ LS1 family is built on Layerscape architecture, the
industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs
been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add
From: York Sun york...@freescale.com
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v3: No change.
v2: No change.
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Add I2C 3 support.
v2: No change.
drivers/i2c/mxc_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c14797c..83a9ffa 100644
--- a/drivers/i2c
As extra FPGA settings is needed for MDIO read/write
on LS1021AQDS, private MDIO read/write functions are
created.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio read and write
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank.
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: No change.
v2: Add private mdio read and write support.
drivers/net/tsec.c | 7
From: Claudiu Manoil claudiu.man...@freescale.com
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot
From: York Sun york...@freescale.com
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
From: Wang Huan b18...@freescale.com
This patch is to add basic support for LS1021AQDS board.
For the detail board information, please refer to README.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: York Sun york
From: Wang Huan b18...@freescale.com
This patch is to add basic support for LS1021ATWR board.
For the detail board information, please refer to README.
Signed-off-by: Chen Lu chen...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
From: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
---
Change log:
v3: New file.
drivers/serial/serial_lpuart.c | 122 +
1 file changed, 122 insertions(+)
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/common/dcu_sii9022a.c | 153 ++
board/freescale/common/dcu_sii9022a.h | 13 +++
3 files changed, 168 insertions
From: Wang Huan b18...@freescale.com
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
From: Wang Huan b18...@freescale.com
This patch is to add LETECH support for LS1021AQDS/TWR board.
For LETECH, LPUART is used for serial port.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
From: Wang Huan b18...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: New file.
board/freescale/ls1021atwr/Makefile | 1 +
board/freescale/ls1021atwr/dcu.c| 47 +
board/freescale/ls1021atwr/ls1021atwr.c | 6
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Add commit messages.
v3: Add I2C 3 support.
v2: No change.
drivers/i2c/mxc_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch
Use mb() instead of sync assembly instruction to be
compatible for both ARM and PowerPC.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: Use mb() to be compatible for both ARM and PowerPC.
Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log
been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed
This series contain the support for Freescale LS102xA SoC
and LS1021AQDS/TWR board.
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs
From: York Sun york...@freescale.com
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v4: No change.
v3: No change.
v2: No change.
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: No change.
v2: Add private mdio read and write support.
drivers/net
From: York Sun york...@freescale.com
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank.
From: Jingchang Lu jingchang...@freescale.com
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
---
From: Claudiu Manoil claudiu.man...@freescale.com
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a
workaround for LS1. It has been observed that currently
the Tx stops functioning after a fair amount of Tx traffic
with these settings on. These bits are sticky and once set
they cannot
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Add commit messages.
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/common
From: Wang Huan b18...@freescale.com
LS102xA is an ARMv7 implementation. This patch is to add
basic support for LS1021AQDS board.
One DDR controller
DUART1 is used as the console
For the detail board information, please refer to README.
Signed-off-by: Alison Wang alison.w...@freescale.com
From: Wang Huan b18...@freescale.com
This patch is to add DCU driver support. DCU also named
2D-ACE(Two Dimensional Animation and Compositing Engine)
is a system master that fetches graphics stored in internal
or external memory and displays them on a TFT LCD panel.
Signed-off-by: Alison Wang
-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Add more commit messages.
v3: Fix checkpatch error.
Update to Kconfig.
v2: New file.
arch/arm/Kconfig| 4 +
board/freescale/ls1021atwr/Kconfig | 23
As extra FPGA settings is needed for MDIO read/write
on LS1021AQDS, private MDIO read/write functions are
created.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio
From: Wang Huan b18...@freescale.com
This patch is to add LETECH support for LS1021AQDS/TWR board.
For LETECH, lpuart is used as console.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
From: Wang Huan b18...@freescale.com
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Add commit messages.
v3: New file.
board/freescale/ls1021atwr/Makefile
Signed-off-by: Alison Wang alison.w...@freescale.com
---
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..792fc40 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7
Signed-off-by: Alison Wang alison.w...@freescale.com
---
drivers/net/fsl_mdio.c | 15 ---
drivers/net/tsec.c | 7 +++
include/tsec.h | 7 ++-
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank.
From: York Sun york...@freescale.com
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.
Signed-off-by: York Sun
From: York Sun york...@freescale.com
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/arm_ddr_gen3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
information about LS1021AQDS board, please refer to README in
the patch.
Alison Wang (5):
arm: ls102xa: Add Freescale LS102xA SoC support
arm: ls102xa: Add i2c support for LS102xA
arm: ls102xa: Add etsec support
and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
board/freescale/ls1021aqds/Makefile
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