[U-Boot] [PATCH v2 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support
This series contain the support for Freescale Vybrid MVF600 CPU and MVF600TWR board. Vybird devices are built on an asymmetrical-multiprocessing architecture using ARM cores. The families in the Vybrid portfolio span entry-level, single core Cortex-A class SoCs all the way to dual heterogeneous core SoCs with multiple communication and connectivity options. Part of the Vybrid platform, MVF600 is a dual-core eMPU combining the ARM Cortex A5 and Cortex M4 cores. The u-boot runs on Cortex A5 core. MVF600 shares some IPs with i.MX family, such as FEC,ESDHC,WATCHDOG,I2C,ASRC and ESAI. MVF600 also shares some IPs with ColdFire family, such as eDMA and DSPI. MVF600 still has its own IPs, such as PIT,SAI,UART,QSPI and DCU. More documents for this soc can be found at: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xxfsrch=1sr=5 http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID Changes in v2: - Remove vybrid-common directory - Rename directory name 'vybrid' to 'mvf600' - Add generic.c file - Rewrite get_reset_cause() to make it readable - Remove reset_cpu(), and use the function in imx_watchdog.c - Rewrite timer.c file - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk() - Remove lowlevel_init.S, and add clock_init() in board_early_init_f() - Remove useless CONFIG_SYS_ defines - Move CONFIG_MACH_TYPE to board configuration file - Define C structures and access C structures to set/read registers - Remove useless errata - Remove useless macros - Rename directory name 'arch-vybrid' to 'arch-mvf600' - Use common iomux-v3 code - Use common FEC driver fec_mxc.c - Add watchdog support - Add an entry to MAINTAINERS file - Rename directory name 'vybird' to 'mvf600twr' - Use standard method to set gd-ram_size - Rewrite board_mmc_getcd() function - Remove useless undef - Remove hardcoded IP addresses and MAC addresses - Move CONFIG_MACH_TYPE to board configuration file Alison Wang (6): arm: mvf600: Add Vybrid MVF600 CPU support arm: mvf600: Add IOMUX support for Vybrid MVF600 arm: mvf600: Add FEC support for Vybrid MVF600 arm: mvf600: Add watchdog support for Vybrid MVF600 arm: mvf600: Add uart support for Vybrid MVF600 arm: mvf600: Add basic support for Vybrid MVF600TWR board MAINTAINERS | 4 ++ Makefile| 2 +- arch/arm/cpu/armv7/mvf600/Makefile | 42 +++ arch/arm/cpu/armv7/mvf600/generic.c | 309 arch/arm/cpu/armv7/mvf600/timer.c | 144 ++ arch/arm/imx-common/Makefile| 2 +- arch/arm/imx-common/iomux-v3.c | 6 ++ arch/arm/include/asm/arch-mvf600/clock.h| 38 ++ arch/arm/include/asm/arch-mvf600/crm_regs.h | 170 arch/arm/include/asm/arch-mvf600/imx-regs.h | 201 arch/arm/include/asm/arch-mvf600/mvf_pins.h | 92 arch/arm/include/asm/imx-common/iomux-v3.h | 18 + board/freescale/mvf600twr/Makefile | 39 +++ board/freescale/mvf600twr/imximage.cfg | 35 ++ board/freescale/mvf600twr/mvf600twr.c | 403 + boards.cfg | 1 + drivers/net/fec_mxc.c | 6 +- drivers/serial/Makefile | 1 + drivers/serial/serial_lpuart.c | 161 ++ drivers/watchdog/Makefile | 2 +- include/configs/mvf600twr.h | 147 ++ 21 files changed, 1819 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/mvf600/Makefile create mode 100644 arch/arm/cpu/armv7/mvf600/generic.c create mode 100644 arch/arm/cpu/armv7/mvf600/timer.c create mode 100644 arch/arm/include/asm/arch-mvf600/clock.h create mode 100644 arch/arm/include/asm/arch-mvf600/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mvf600/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mvf600/mvf_pins.h create mode 100644 board/freescale/mvf600twr/Makefile create mode 100644 board/freescale/mvf600twr/imximage.cfg create mode 100644 board/freescale/mvf600twr/mvf600twr.c create mode 100644 drivers/serial/serial_lpuart.c create mode 100644 include/configs/mvf600twr.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU. It aligns Vybrid MVF600 platform with i.MX platform. As there are some differences between MVF600 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/mvf600 directory. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v2: - Remove vybrid-common directory - Rename directory name 'vybrid' to 'mvf600' - Add generic.c file - Rewrite get_reset_cause() to make it readable - Remove reset_cpu(), and use the function in imx_watchdog.c - Rewrite timer.c file - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk() - Remove lowlevel_init.S, and add clock_init() in board_early_init_f() - Remove useless CONFIG_SYS_ defines - Move CONFIG_MACH_TYPE to board configuration file - Define C structures and access C structures to set/read registers - Remove useless errata - Remove useless macros - Rename directory 'arch-vybrid' to 'arch-mvf600' Makefile| 2 +- arch/arm/cpu/armv7/mvf600/Makefile | 42 arch/arm/cpu/armv7/mvf600/generic.c | 309 arch/arm/cpu/armv7/mvf600/timer.c | 144 + arch/arm/include/asm/arch-mvf600/clock.h| 38 arch/arm/include/asm/arch-mvf600/crm_regs.h | 170 +++ arch/arm/include/asm/arch-mvf600/imx-regs.h | 201 ++ arch/arm/include/asm/arch-mvf600/mvf_pins.h | 92 + 8 files changed, 997 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/mvf600/Makefile create mode 100644 arch/arm/cpu/armv7/mvf600/generic.c create mode 100644 arch/arm/cpu/armv7/mvf600/timer.c create mode 100644 arch/arm/include/asm/arch-mvf600/clock.h create mode 100644 arch/arm/include/asm/arch-mvf600/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mvf600/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mvf600/mvf_pins.h diff --git a/Makefile b/Makefile index c52f0f1..9df2138 100644 --- a/Makefile +++ b/Makefile @@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs mvf600)) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif diff --git a/arch/arm/cpu/armv7/mvf600/Makefile b/arch/arm/cpu/armv7/mvf600/Makefile new file mode 100644 index 000..9232cd4 --- /dev/null +++ b/arch/arm/cpu/armv7/mvf600/Makefile @@ -0,0 +1,42 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/mvf600/generic.c b/arch/arm/cpu/armv7/mvf600/generic.c new file mode 100644 index 000..f21ce73 --- /dev/null +++ b/arch/arm/cpu/armv7/mvf600/generic.c @@ -0,0 +1,309 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include common.h +#include asm/io.h +#include asm/arch/imx-regs.h +#include asm/arch/clock.h +#include asm/arch/crm_regs.h +#include
[U-Boot] [PATCH v2 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600
This patch adds the IOMUX support for Vybrid MVF600 platform. There is a little difference for IOMUXC module between MVF600 and i.MX platform, the muxmode and pad configuration share one 32bit register on MVF600, but they are two independent registers on I.MX platform. A CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v2: - Use common iomux-v3 code arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/iomux-v3.c | 6 ++ arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 8bba8a5..3378931 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libimx-common.o -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mvf600)) COBJS-y= iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 7fe5ce7..35880c7 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) __raw_writel(sel_input, base + sel_input_ofs); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG + if (!(pad_ctrl NO_PAD_CTRL)) + __raw_writel((mux_mode PAD_MUX_MODE_SHIFT) | pad_ctrl, + base + pad_ctrl_ofs); +#else if (!(pad_ctrl NO_PAD_CTRL) pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); +#endif } void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 0b4e763..7005fde 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 3) #define PAD_CTL_DSE_34ohm (7 3) +#elif defined(CONFIG_MVF600) + +#define PAD_MUX_MODE_SHIFT 20 + +#definePAD_CTL_PUS_47K_UP (1 4) +#definePAD_CTL_PUS_100K_UP (2 4) +#define PAD_CTL_PUE(1 2) +#define PAD_CTL_PKE(1 3) + +#define PAD_CTL_SPEED_HIGH (3 12) +#define PAD_CTL_SPEED_MED (1 12) + +#define PAD_CTL_DSE_20ohm (7 6) +#define PAD_CTL_DSE_25ohm (6 6) +#define PAD_CTL_DSE_50ohm (3 6) + +#define PAD_CTL_OBE_IBE_ENABLE (3 0) + #else #define PAD_CTL_DVS(1 13) -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/6] arm: mvf600: Add FEC support for Vybrid MVF600
This patch adds FEC support for Vybrid MVF600 platform. Add code to use RMII for MVF600. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v2: - Use common FEC driver fec_mxc.c drivers/net/fec_mxc.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 4dbcdca..21e58f4 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -518,7 +518,11 @@ static int fec_open(struct eth_device *edev) u32 ecr = readl(fec-eth-ecntrl) ~FEC_ECNTRL_SPEED; u32 rcr = (readl(fec-eth-r_cntrl) ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) | - FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE; + FEC_RCNTRL_MII_MODE; + if (fec-xcv_type == RGMII) + rcr |= FEC_RCNTRL_RGMII; + else if (fec-xcv_type == RMII) + rcr |= FEC_RCNTRL_RMII; if (speed == _1000BASET) ecr |= FEC_ECNTRL_SPEED; else if (speed != _100BASET) -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/6] arm: mvf600: Add watchdog support for Vybrid MVF600
This patch adds watchdog support for Vybrid MVF600 platform. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v2: - Add watchdog support - Use reset_cpu() in imx_watchdog.c drivers/watchdog/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 13e7c37..40946df 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,7 +27,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mvf600)) COBJS-y += imx_watchdog.o endif COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/6] arm: mvf600: Add uart support for Vybrid MVF600
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this driver on other platforms
drivers/serial/Makefile| 1 +
drivers/serial/serial_lpuart.c | 161 +
2 files changed, 162 insertions(+)
create mode 100644 drivers/serial/serial_lpuart.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index fbc4e97..bb6559b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
new file mode 100644
index 000..6ae7f77
--- /dev/null
+++ b/drivers/serial/serial_lpuart.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+#include linux/compiler.h
+#include asm/arch/imx-regs.h
+#include asm/arch/clock.h
+
+#define UART_BASE UART1_BASE
+
+struct lpuart_fsl {
+ u8 ubdh;
+ u8 ubdl;
+ u8 uc1;
+ u8 uc2;
+ u8 us1;
+ u8 us2;
+ u8 uc3;
+ u8 ud;
+ u8 uma1;
+ u8 uma2;
+ u8 uc4;
+ u8 uc5;
+ u8 ued;
+ u8 umodem;
+ u8 uir;
+ u8 reserved;
+ u8 upfifo;
+ u8 ucfifo;
+ u8 usfifo;
+ u8 utwfifo;
+ u8 utcfifo;
+ u8 urwfifo;
+ u8 urcfifo;
+ u8 rsvd[28];
+};
+
+#define US1_TDRE(1 7)
+#define US1_RDRF(1 5)
+#define UC2_TE (1 3)
+#define UC2_RE (1 2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct lpuart_fsl *base = (struct lpuart_fsl *)UART_BASE;
+
+static void lpuart_serial_setbrg(void)
+{
+ u32 clk = mvf_get_clock(MVF_UART_CLK);
+ u16 sbr;
+
+ if (!gd-baudrate)
+ gd-baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd-baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ __raw_writeb(sbr 8, base-ubdh);
+ __raw_writeb(sbr 0xff, base-ubdl);
+}
+
+static int lpuart_serial_getc(void)
+{
+ u8 status;
+
+ while (!(__raw_readb(base-us1) US1_RDRF))
+ WATCHDOG_RESET();
+
+ status = __raw_readb(base-us1);
+ status |= US1_RDRF;
+ __raw_writeb(status, base-us1);
+
+ return __raw_readb(base-ud);
+}
+
+static void lpuart_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(__raw_readb(base-us1) US1_TDRE))
+ WATCHDOG_RESET();
+
+ __raw_writeb(c, base-ud);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart_serial_tstc(void)
+{
+ if (__raw_readb(base-urcfifo) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = __raw_readb(base-uc2);
+ ctrl = ~UC2_RE;
+ ctrl = ~UC2_TE;
+ __raw_writeb(ctrl, base-uc2);
+
+ __raw_writeb(0, base-umodem);
+ __raw_writeb(0, base-uc1);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ __raw_writeb(UC2_RE | UC2_TE, base-uc2);
+
+ return 0;
+}
+
+static struct serial_device lpuart_serial_drv = {
+ .name = lpuart_serial,
+ .start = lpuart_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart_serial_setbrg,
+ .putc = lpuart_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart_serial_getc,
+ .tstc = lpuart_serial_tstc,
+};
+
+void lpuart_serial_initialize(void)
+{
+ serial_register(lpuart_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void
[U-Boot] [PATCH v2 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
MVF600TWR is a board based on Vybrid MVF600 SoC. This patch adds basic support for Vybrid MVF600TWR board. Signed-off-by: Alison Wang b18...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: TsiChung Liew tsicl...@gmail.com --- Changes in v2: - Add an entry to MAINTAINERS file - Rename directory name 'vybird' to 'mvf600twr' - Use standard method to set gd-ram_size - Rewrite board_mmc_getcd() function - Remove useless undef - Remove hardcoded IP addresses and MAC addresses - Remove useless CONFIG_SYS_ defines - Define C structures and access C structures to set/read registers - Move CONFIG_MACH_TYPE to board configuration file - Use common iomux-v3 code MAINTAINERS| 4 + board/freescale/mvf600twr/Makefile | 39 board/freescale/mvf600twr/imximage.cfg | 35 +++ board/freescale/mvf600twr/mvf600twr.c | 403 + boards.cfg | 1 + include/configs/mvf600twr.h| 147 6 files changed, 629 insertions(+) create mode 100644 board/freescale/mvf600twr/Makefile create mode 100644 board/freescale/mvf600twr/imximage.cfg create mode 100644 board/freescale/mvf600twr/mvf600twr.c create mode 100644 include/configs/mvf600twr.h diff --git a/MAINTAINERS b/MAINTAINERS index c05433a..d32ac66 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1057,6 +1057,10 @@ Eric Nelson eric.nel...@boundarydevices.com nitrogen6s i.MX6S 512MB nitrogen6s1gi.MX6S 1GB +Alison Wang b18...@freescale.com + + mvf600twr MVF600 + - Unknown / orphaned boards: diff --git a/board/freescale/mvf600twr/Makefile b/board/freescale/mvf600twr/Makefile new file mode 100644 index 000..7416228 --- /dev/null +++ b/board/freescale/mvf600twr/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/mvf600twr/imximage.cfg b/board/freescale/mvf600twr/imximage.cfg new file mode 100644 index 000..33ead0f --- /dev/null +++ b/board/freescale/mvf600twr/imximage.cfg @@ -0,0 +1,35 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd diff --git a/board/freescale/mvf600twr/mvf600twr.c b/board/freescale/mvf600twr/mvf600twr.c new file mode 100644 index 000..500ceb8 --- /dev/null +++ b/board/freescale/mvf600twr/mvf600twr.c @@ -0,0 +1,403 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License
[U-Boot] [PATCH v3 4/6] arm: mvf600: Add watchdog support for Vybrid MVF600
This patch adds watchdog support for Vybrid MVF600 platform. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v3: None Changes in v2: - Add watchdog support - Use reset_cpu() in imx_watchdog.c drivers/watchdog/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 13e7c37..40946df 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,7 +27,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 mvf600)) COBJS-y += imx_watchdog.o endif COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/6] arm: mvf600: Add IOMUX support for Vybrid MVF600
This patch adds the IOMUX support for Vybrid MVF600 platform. There is a little difference for IOMUXC module between MVF600 and i.MX platform, the muxmode and pad configuration share one 32bit register on MVF600, but they are two independent registers on I.MX platform. A CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v3: - Define PAD_CTL_PUE with PKE enabled Changes in v2: - Use common iomux-v3 code arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/iomux-v3.c | 6 ++ arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 8bba8a5..3378931 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libimx-common.o -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mvf600)) COBJS-y= iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 7fe5ce7..35880c7 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) __raw_writel(sel_input, base + sel_input_ofs); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG + if (!(pad_ctrl NO_PAD_CTRL)) + __raw_writel((mux_mode PAD_MUX_MODE_SHIFT) | pad_ctrl, + base + pad_ctrl_ofs); +#else if (!(pad_ctrl NO_PAD_CTRL) pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); +#endif } void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 0b4e763..012d66a 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 3) #define PAD_CTL_DSE_34ohm (7 3) +#elif defined(CONFIG_MVF600) + +#define PAD_MUX_MODE_SHIFT 20 + +#definePAD_CTL_PUS_47K_UP (1 4) +#definePAD_CTL_PUS_100K_UP (2 4) +#define PAD_CTL_PUE(1 2 | PAD_CTL_PKE) +#definePAD_CTL_PKE (1 3) + +#define PAD_CTL_SPEED_HIGH (3 12) +#define PAD_CTL_SPEED_MED (1 12) + +#define PAD_CTL_DSE_20ohm (7 6) +#define PAD_CTL_DSE_25ohm (6 6) +#define PAD_CTL_DSE_50ohm (3 6) + +#define PAD_CTL_OBE_IBE_ENABLE (3 0) + #else #define PAD_CTL_DVS(1 13) -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 5/6] arm: mvf600: Add uart support for Vybrid MVF600
This patch adds lpuart support for Vybrid MVF600 platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this driver on other platforms
drivers/serial/Makefile| 1 +
drivers/serial/serial_lpuart.c | 132 +
2 files changed, 133 insertions(+)
create mode 100644 drivers/serial/serial_lpuart.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index fbc4e97..bb6559b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
new file mode 100644
index 000..51d5666
--- /dev/null
+++ b/drivers/serial/serial_lpuart.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+#include linux/compiler.h
+#include asm/arch/imx-regs.h
+#include asm/arch/clock.h
+
+#define US1_TDRE(1 7)
+#define US1_RDRF(1 5)
+#define UC2_TE (1 3)
+#define UC2_RE (1 2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
+
+static void lpuart_serial_setbrg(void)
+{
+ u32 clk = mxc_get_clock(MXC_UART_CLK);
+ u16 sbr;
+
+ if (!gd-baudrate)
+ gd-baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd-baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ __raw_writeb(sbr 8, base-ubdh);
+ __raw_writeb(sbr 0xff, base-ubdl);
+}
+
+static int lpuart_serial_getc(void)
+{
+ u8 status;
+
+ while (!(__raw_readb(base-us1) US1_RDRF))
+ WATCHDOG_RESET();
+
+ status = __raw_readb(base-us1);
+ status |= US1_RDRF;
+ __raw_writeb(status, base-us1);
+
+ return __raw_readb(base-ud);
+}
+
+static void lpuart_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(__raw_readb(base-us1) US1_TDRE))
+ WATCHDOG_RESET();
+
+ __raw_writeb(c, base-ud);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart_serial_tstc(void)
+{
+ if (__raw_readb(base-urcfifo) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = __raw_readb(base-uc2);
+ ctrl = ~UC2_RE;
+ ctrl = ~UC2_TE;
+ __raw_writeb(ctrl, base-uc2);
+
+ __raw_writeb(0, base-umodem);
+ __raw_writeb(0, base-uc1);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ __raw_writeb(UC2_RE | UC2_TE, base-uc2);
+
+ return 0;
+}
+
+static struct serial_device lpuart_serial_drv = {
+ .name = lpuart_serial,
+ .start = lpuart_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart_serial_setbrg,
+ .putc = lpuart_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart_serial_getc,
+ .tstc = lpuart_serial_tstc,
+};
+
+void lpuart_serial_initialize(void)
+{
+ serial_register(lpuart_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return lpuart_serial_drv;
+}
--
1.8.0
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[U-Boot] [PATCH v3 0/6] arm: mvf600: Add Freescale Vybrid MVF600 CPU and MVF600TWR board support
This series contain the support for Freescale Vybrid MVF600 CPU and MVF600TWR board. Vybird devices are built on an asymmetrical-multiprocessing architecture using ARM cores. The families in the Vybrid portfolio span entry-level, single core Cortex-A class SoCs all the way to dual heterogeneous core SoCs with multiple communication and connectivity options. Part of the Vybrid platform, MVF600 is a dual-core eMPU combining the ARM Cortex A5 and Cortex M4 cores. MVF600 shares some IPs with i.MX family, such as FEC,ESDHC,WATCHDOG,I2C,ASRC and ESAI. MVF600 also shares some IPs with ColdFire family, such as eDMA and DSPI. MVF600 still has its own IPs, such as PIT,SAI,UART,QSPI and DCU. More documents for this soc can be found at: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xxfsrch=1sr=5 http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID The u-boot runs on Cortex A5 core. Changes in v3: - Rename the common functions and enums - Move the structure definitions to imx-regs.h - Define PAD_CTL_PUE with PKE enabled - Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup() - Replace BOOT_FROM by BOOT_OFFSET - Enable CONFIG_OF_LIBFDT option - Add useful define instead of raw number - Use clrsetbits_le32 to set the single bits - Move setup_iomux_enet() to board_early_init_f and remove board_eth_init() - Remove redundant define - Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h Changes in v2: - Remove vybrid-common directory - Rename directory name 'vybrid' to 'mvf600' - Add generic.c file - Rewrite get_reset_cause() to make it readable - Remove reset_cpu(), and use the function in imx_watchdog.c - Rewrite timer.c file - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk() - Remove lowlevel_init.S, and add clock_init() in board_early_init_f() - Remove useless CONFIG_SYS_ defines - Move CONFIG_MACH_TYPE to board configuration file - Define C structures and access C structures to set/read registers - Remove useless errata - Remove useless macros - Rename directory 'arch-vybrid' to 'arch-mvf600' - Use common iomux-v3 code - Use common FEC driver fec_mxc.c - Add watchdog support - Add an entry to MAINTAINERS file - Rename directory name 'vybird' to 'mvf600twr' - Use standard method to set gd-ram_size - Rewrite board_mmc_getcd() function - Remove useless undef - Remove hardcoded IP addresses and MAC addresses - Move CONFIG_MACH_TYPE to board configuration file Alison Wang (6): arm: mvf600: Add Vybrid MVF600 CPU support arm: mvf600: Add IOMUX support for Vybrid MVF600 net: fec_mxc: Add support for Vybrid MVF600 arm: mvf600: Add watchdog support for Vybrid MVF600 arm: mvf600: Add uart support for Vybrid MVF600 arm: mvf600: Add basic support for Vybrid MVF600TWR board MAINTAINERS | 4 ++ Makefile| 2 +- arch/arm/cpu/armv7/mvf600/Makefile | 42 +++ arch/arm/cpu/armv7/mvf600/generic.c | 324 ++ arch/arm/cpu/armv7/mvf600/timer.c | 103 ++ arch/arm/imx-common/Makefile| 2 +- arch/arm/imx-common/iomux-v3.c | 6 ++ arch/arm/include/asm/arch-mvf600/clock.h| 39 ++ arch/arm/include/asm/arch-mvf600/crm_regs.h | 225 + arch/arm/include/asm/arch-mvf600/imx-regs.h | 411 arch/arm/include/asm/arch-mvf600/mvf_pins.h | 92 arch/arm/include/asm/imx-common/iomux-v3.h | 18 + board/freescale/mvf600twr/Makefile | 39 ++ board/freescale/mvf600twr/imximage.cfg | 33 + board/freescale/mvf600twr/mvf600twr.c | 413 + boards.cfg | 1 + drivers/net/fec_mxc.c | 4 +- drivers/serial/Makefile | 1 + drivers/serial/serial_lpuart.c | 132 ++ drivers/watchdog/Makefile | 2 +- include/configs/mvf600twr.h | 140 21 files changed, 2027 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/armv7/mvf600/Makefile create mode 100644 arch/arm/cpu/armv7/mvf600/generic.c create mode 100644 arch/arm/cpu/armv7/mvf600/timer.c create mode 100644 arch/arm/include/asm/arch-mvf600/clock.h create mode 100644 arch/arm/include/asm/arch-mvf600/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mvf600/imx-regs.h create mode 100644 arch/arm
[U-Boot] [PATCH v3 3/6] net: fec_mxc: Add support for Vybrid MVF600
This patch adds FEC support for Vybrid MVF600 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for MVF600 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v3:
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup()
Changes in v2:
- Use common FEC driver fec_mxc.c
drivers/net/fec_mxc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4dbcdca..da95e28 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -516,9 +516,7 @@ static int fec_open(struct eth_device *edev)
#ifdef FEC_QUIRK_ENET_MAC
{
u32 ecr = readl(fec-eth-ecntrl) ~FEC_ECNTRL_SPEED;
- u32 rcr = (readl(fec-eth-r_cntrl)
- ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ u32 rcr = readl(fec-eth-r_cntrl) ~FEC_RCNTRL_RMII_10T;
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
--
1.8.0
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[U-Boot] [PATCH v3 6/6] arm: mvf600: Add basic support for Vybrid MVF600TWR board
MVF600TWR is a board based on Vybrid MVF600 SoC. This patch adds basic support for Vybrid MVF600TWR board. Signed-off-by: Alison Wang b18...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: TsiChung Liew tsicl...@gmail.com --- Changes in v3: - Replace BOOT_FROM by BOOT_OFFSET - Enable CONFIG_OF_LIBFDT option - Add useful define instead of raw number - Use clrsetbits_le32 to set the single bits - Move setup_iomux_enet() to board_early_init_f and remove board_eth_init() - Remove redundant define - Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h Changes in v2: - Add an entry to MAINTAINERS file - Rename directory name 'vybird' to 'mvf600twr' - Use standard method to set gd-ram_size - Rewrite board_mmc_getcd() function - Remove useless undef - Remove hardcoded IP addresses and MAC addresses - Remove useless CONFIG_SYS_ defines - Define C structures and access C structures to set/read registers - Move CONFIG_MACH_TYPE to board configuration file - Use common iomux-v3 code MAINTAINERS| 4 + board/freescale/mvf600twr/Makefile | 39 board/freescale/mvf600twr/imximage.cfg | 33 +++ board/freescale/mvf600twr/mvf600twr.c | 413 + boards.cfg | 1 + include/configs/mvf600twr.h| 140 +++ 6 files changed, 630 insertions(+) create mode 100644 board/freescale/mvf600twr/Makefile create mode 100644 board/freescale/mvf600twr/imximage.cfg create mode 100644 board/freescale/mvf600twr/mvf600twr.c create mode 100644 include/configs/mvf600twr.h diff --git a/MAINTAINERS b/MAINTAINERS index c05433a..d32ac66 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1057,6 +1057,10 @@ Eric Nelson eric.nel...@boundarydevices.com nitrogen6s i.MX6S 512MB nitrogen6s1gi.MX6S 1GB +Alison Wang b18...@freescale.com + + mvf600twr MVF600 + - Unknown / orphaned boards: diff --git a/board/freescale/mvf600twr/Makefile b/board/freescale/mvf600twr/Makefile new file mode 100644 index 000..7416228 --- /dev/null +++ b/board/freescale/mvf600twr/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/mvf600twr/imximage.cfg b/board/freescale/mvf600twr/imximage.cfg new file mode 100644 index 000..b00d4c1 --- /dev/null +++ b/board/freescale/mvf600twr/imximage.cfg @@ -0,0 +1,33 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include asm/imx-common/imximage.cfg + +/* image version */ +IMAGE_VERSION 2 + +/* Boot Offset 0x400, valid for both SD and NAND boot */ +BOOT_OFFSETFLASH_OFFSET_STANDARD diff --git a/board/freescale/mvf600twr
[U-Boot] [PATCH v3 1/6] arm: mvf600: Add Vybrid MVF600 CPU support
This patch adds generic codes to support Freescale's Vybrid MVF600 CPU. It aligns Vybrid MVF600 platform with i.MX platform. As there are some differences between MVF600 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/mvf600 directory. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v3: - Rename the common functions and enums - Move the structure definitions to imx-regs.h Changes in v2: - Remove vybrid-common directory - Rename directory name 'vybrid' to 'mvf600' - Add generic.c file - Rewrite get_reset_cause() to make it readable - Remove reset_cpu(), and use the function in imx_watchdog.c - Rewrite timer.c file - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk() - Remove lowlevel_init.S, and add clock_init() in board_early_init_f() - Remove useless CONFIG_SYS_ defines - Move CONFIG_MACH_TYPE to board configuration file - Define C structures and access C structures to set/read registers - Remove useless errata - Remove useless macros - Rename directory 'arch-vybrid' to 'arch-mvf600' Makefile| 2 +- arch/arm/cpu/armv7/mvf600/Makefile | 42 +++ arch/arm/cpu/armv7/mvf600/generic.c | 324 ++ arch/arm/cpu/armv7/mvf600/timer.c | 103 +++ arch/arm/include/asm/arch-mvf600/clock.h| 39 +++ arch/arm/include/asm/arch-mvf600/crm_regs.h | 225 +++ arch/arm/include/asm/arch-mvf600/imx-regs.h | 411 arch/arm/include/asm/arch-mvf600/mvf_pins.h | 92 +++ 8 files changed, 1237 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/mvf600/Makefile create mode 100644 arch/arm/cpu/armv7/mvf600/generic.c create mode 100644 arch/arm/cpu/armv7/mvf600/timer.c create mode 100644 arch/arm/include/asm/arch-mvf600/clock.h create mode 100644 arch/arm/include/asm/arch-mvf600/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mvf600/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mvf600/mvf_pins.h diff --git a/Makefile b/Makefile index c52f0f1..9df2138 100644 --- a/Makefile +++ b/Makefile @@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs mvf600)) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif diff --git a/arch/arm/cpu/armv7/mvf600/Makefile b/arch/arm/cpu/armv7/mvf600/Makefile new file mode 100644 index 000..9232cd4 --- /dev/null +++ b/arch/arm/cpu/armv7/mvf600/Makefile @@ -0,0 +1,42 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/mvf600/generic.c b/arch/arm/cpu/armv7/mvf600/generic.c new file mode 100644 index 000..f47ab1e --- /dev/null +++ b/arch/arm/cpu/armv7/mvf600/generic.c @@ -0,0 +1,324 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include common.h +#include asm/io.h
[U-Boot] [PATCH v4 4/7] arm: vf610: Add watchdog support for Vybrid VF610
This patch adds watchdog support for Vybrid VF610 platform. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v4: - Rename mvf600 to vf610 Changes in v3: None Changes in v2: - Add watchdog support - Use reset_cpu() in imx_watchdog.c drivers/watchdog/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 13e7c37..e96acab 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -27,7 +27,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o -ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6)) +ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610)) COBJS-y += imx_watchdog.o endif COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 0/7] arm: vf610: Add Freescale Vybrid VF610 CPU and VF610TWR board support
This series contain the support for Freescale Vybrid VF610 CPU and VF610TWR board. Vybird devices are built on an asymmetrical-multiprocessing architecture using ARM cores. The families in the Vybrid portfolio span entry-level, single core Cortex-A class SoCs all the way to dual heterogeneous core SoCs with multiple communication and connectivity options. Part of the Vybrid platform, VF610 is a dual-core eMPU combining the ARM Cortex A5 and Cortex M4 cores. VF610 shares some IPs with i.MX family, such as FEC,ESDHC,WATCHDOG,I2C,ASRC and ESAI. VF610 also shares some IPs with ColdFire family, such as eDMA and DSPI. VF610 still has its own IPs, such as PIT,SAI,UART,QSPI and DCU. More documents for this soc can be found at: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=VF6xxfsrch=1sr=5 http://www.freescale.com/webapp/sps/site/homepage.jsp?code=VYBRID To align with the description in the above documents, VF610 is used as the SoC name instead of MVF600. The u-boot runs on Cortex A5 core. Changes in v4: - Rename MVF600 to VF610 - Define PAD_CTL_PUS_47K_UP and PAD_CTL_PUS_100K_UP with PAD_CTL_PUE enabled - Reorganize the definitions - Correct the spaces and tabs - Rename mvf_pins.h to iomux-vf610.h - Add README.vf610 about fuse assignments for MAC addresses - Rename directory name 'mvf600' to 'vf610' - Rename directory 'arch-mvf600' to 'arch-vf610' - Add Vybrid VF610 to mxc_ocotp document - Rename directory name 'mvf600twr' to 'vf610twr' - Rename mvf600twr.h to vf610twr.h - Use NEW_PAD_CTRL instead of MUX_PAD_CTRL - Remove CONFIG_ETHPRIME option - Add CONFIG_CMD_MEMSET option Changes in v3: - Rename the common functions and enums - Move the structure definitions to imx-regs.h - Define PAD_CTL_PUE with PKE enabled - Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII / FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup() - Replace BOOT_FROM by BOOT_OFFSET - Enable CONFIG_OF_LIBFDT option - Add useful define instead of raw number - Use clrsetbits_le32 to set the single bits - Move setup_iomux_enet() to board_early_init_f and remove board_eth_init() - Remove redundant define - Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h Changes in v2: - Remove vybrid-common directory - Rename directory name 'vybrid' to 'mvf600' - Add generic.c file - Rewrite get_reset_cause() to make it readable - Remove reset_cpu(), and use the function in imx_watchdog.c - Rewrite timer.c file - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk() - Remove lowlevel_init.S, and add clock_init() in board_early_init_f() - Remove useless CONFIG_SYS_ defines - Move CONFIG_MACH_TYPE to board configuration file - Define C structures and access C structures to set/read registers - Remove useless errata - Remove useless macros - Rename directory 'arch-vybrid' to 'arch-mvf600' - Use common iomux-v3 code - Use common FEC driver fec_mxc.c - Add watchdog support - Add an entry to MAINTAINERS file - Rename directory name 'vybird' to 'mvf600twr' - Use standard method to set gd-ram_size - Rewrite board_mmc_getcd() function - Remove useless undef - Remove hardcoded IP addresses and MAC addresses - Move CONFIG_MACH_TYPE to board configuration file Alison Wang (7): arm: vf610: Add IOMUX support for Vybrid VF610 arm: vf610: Add Vybrid VF610 CPU support net: fec_mxc: Add support for Vybrid VF610 arm: vf610: Add watchdog support for Vybrid VF610 arm: vf610: Add uart support for Vybrid VF610 arm: vf610: Add Vybrid VF610 to mxc_ocotp document arm: vf610: Add basic support for Vybrid VF610TWR board MAINTAINERS | 4 + Makefile | 2 +- arch/arm/cpu/armv7/vf610/Makefile | 42 +++ arch/arm/cpu/armv7/vf610/generic.c| 324 +++ arch/arm/cpu/armv7/vf610/timer.c | 103 ++ arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/iomux-v3.c| 6 ++ arch/arm/include/asm/arch-vf610/clock.h | 39 ++ arch/arm/include/asm/arch-vf610/crm_regs.h| 225 +++ arch/arm/include/asm/arch-vf610/imx-regs.h| 419 +++ arch/arm/include/asm/arch-vf610/iomux-vf610.h | 101 + arch/arm/include/asm/imx-common/iomux-v3.h| 18 + board/freescale/vf610twr/Makefile | 39 ++ board/freescale/vf610twr/imximage.cfg | 33 + board/freescale/vf610twr/vf610twr.c | 410 boards.cfg| 1 + doc
[U-Boot] [PATCH v4 1/7] arm: vf610: Add IOMUX support for Vybrid VF610
This patch adds the IOMUX support for Vybrid VF610 platform. There is a little difference for IOMUXC module between VF610 and i.MX platform, the muxmode and pad configuration share one 32bit register on VF610, but they are two independent registers on I.MX platform. A CONFIG_IOMUX_SHARE_CONFIG_REG was introduced to fit this difference. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v4: - Rename MVF600 to VF610 - Define PAD_CTL_PUS_47K_UP and PAD_CTL_PUS_100K_UP with PAD_CTL_PUE enabled - Reorganize the definitions - Correct the spaces and tabs Changes in v3: - Define PAD_CTL_PUE with PKE enabled Changes in v2: - Use common iomux-v3 code arch/arm/imx-common/Makefile | 2 +- arch/arm/imx-common/iomux-v3.c | 6 ++ arch/arm/include/asm/imx-common/iomux-v3.h | 18 ++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index 8bba8a5..9492326 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libimx-common.o -ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6)) +ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 vf610)) COBJS-y= iomux-v3.o endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6)) diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 7fe5ce7..35880c7 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -48,8 +48,14 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) if (sel_input_ofs) __raw_writel(sel_input, base + sel_input_ofs); +#ifdef CONFIG_IOMUX_SHARE_CONF_REG + if (!(pad_ctrl NO_PAD_CTRL)) + __raw_writel((mux_mode PAD_MUX_MODE_SHIFT) | pad_ctrl, + base + pad_ctrl_ofs); +#else if (!(pad_ctrl NO_PAD_CTRL) pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); +#endif } void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index 0b4e763..ebf54cf 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -121,6 +121,24 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_DSE_40ohm (6 3) #define PAD_CTL_DSE_34ohm (7 3) +#elif defined(CONFIG_VF610) + +#define PAD_MUX_MODE_SHIFT 20 + +#define PAD_CTL_SPEED_MED (1 12) +#define PAD_CTL_SPEED_HIGH (3 12) + +#define PAD_CTL_DSE_50ohm (3 6) +#define PAD_CTL_DSE_25ohm (6 6) +#define PAD_CTL_DSE_20ohm (7 6) + +#define PAD_CTL_PUS_47K_UP (1 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP(2 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE(1 3) +#define PAD_CTL_PUE(1 2 | PAD_CTL_PKE) + +#define PAD_CTL_OBE_IBE_ENABLE (3 0) + #else #define PAD_CTL_DVS(1 13) -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 5/7] arm: vf610: Add uart support for Vybrid VF610
This patch adds lpuart support for Vybrid VF610 platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Alison Wang b18...@freescale.com
---
Changes in v4: None
Changes in v3:
- Move the structure definition to imx-regs.h
Changes in v2:
- Define C structures and access C structures to set/read registers
- Change the names to reuse this driver on other platforms
drivers/serial/Makefile| 1 +
drivers/serial/serial_lpuart.c | 132 +
2 files changed, 133 insertions(+)
create mode 100644 drivers/serial/serial_lpuart.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index fbc4e97..bb6559b 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
new file mode 100644
index 000..51d5666
--- /dev/null
+++ b/drivers/serial/serial_lpuart.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+#include linux/compiler.h
+#include asm/arch/imx-regs.h
+#include asm/arch/clock.h
+
+#define US1_TDRE(1 7)
+#define US1_RDRF(1 5)
+#define UC2_TE (1 3)
+#define UC2_RE (1 2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
+
+static void lpuart_serial_setbrg(void)
+{
+ u32 clk = mxc_get_clock(MXC_UART_CLK);
+ u16 sbr;
+
+ if (!gd-baudrate)
+ gd-baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd-baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ __raw_writeb(sbr 8, base-ubdh);
+ __raw_writeb(sbr 0xff, base-ubdl);
+}
+
+static int lpuart_serial_getc(void)
+{
+ u8 status;
+
+ while (!(__raw_readb(base-us1) US1_RDRF))
+ WATCHDOG_RESET();
+
+ status = __raw_readb(base-us1);
+ status |= US1_RDRF;
+ __raw_writeb(status, base-us1);
+
+ return __raw_readb(base-ud);
+}
+
+static void lpuart_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(__raw_readb(base-us1) US1_TDRE))
+ WATCHDOG_RESET();
+
+ __raw_writeb(c, base-ud);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart_serial_tstc(void)
+{
+ if (__raw_readb(base-urcfifo) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = __raw_readb(base-uc2);
+ ctrl = ~UC2_RE;
+ ctrl = ~UC2_TE;
+ __raw_writeb(ctrl, base-uc2);
+
+ __raw_writeb(0, base-umodem);
+ __raw_writeb(0, base-uc1);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ __raw_writeb(UC2_RE | UC2_TE, base-uc2);
+
+ return 0;
+}
+
+static struct serial_device lpuart_serial_drv = {
+ .name = lpuart_serial,
+ .start = lpuart_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart_serial_setbrg,
+ .putc = lpuart_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart_serial_getc,
+ .tstc = lpuart_serial_tstc,
+};
+
+void lpuart_serial_initialize(void)
+{
+ serial_register(lpuart_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return lpuart_serial_drv;
+}
--
1.8.0
___
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[U-Boot] [PATCH v4 2/7] arm: vf610: Add Vybrid VF610 CPU support
This patch adds generic codes to support Freescale's Vybrid VF610 CPU. It aligns Vybrid VF610 platform with i.MX platform. As there are some differences between VF610 and i.MX platforms, the specific codes are in the arch/arm/cpu/armv7/vf610 directory. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v4: - Rename mvf_pins.h to iomux-vf610.h - Add README.vf610 about fuse assignments for MAC addresses - Rename directory name 'mvf600' to 'vf610' - Rename directory 'arch-mvf600' to 'arch-vf610' Changes in v3: - Rename the common functions and enums - Move the structure definitions to imx-regs.h Changes in v2: - Remove vybrid-common directory - Rename directory name 'vybrid' to 'mvf600' - Add generic.c file - Rewrite get_reset_cause() to make it readable - Remove reset_cpu(), and use the function in imx_watchdog.c - Rewrite timer.c file - Use vybrid_get_clock(VYBRID_UART_CLK) instead of vybrid_get_uartclk() - Remove lowlevel_init.S, and add clock_init() in board_early_init_f() - Remove useless CONFIG_SYS_ defines - Move CONFIG_MACH_TYPE to board configuration file - Define C structures and access C structures to set/read registers - Remove useless errata - Remove useless macros - Rename directory 'arch-vybrid' to 'arch-mvf600' Makefile | 2 +- arch/arm/cpu/armv7/vf610/Makefile | 42 +++ arch/arm/cpu/armv7/vf610/generic.c| 324 arch/arm/cpu/armv7/vf610/timer.c | 103 +++ arch/arm/include/asm/arch-vf610/clock.h | 39 +++ arch/arm/include/asm/arch-vf610/crm_regs.h| 225 ++ arch/arm/include/asm/arch-vf610/imx-regs.h| 419 ++ arch/arm/include/asm/arch-vf610/iomux-vf610.h | 101 +++ doc/README.vf610 | 10 + 9 files changed, 1264 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/vf610/Makefile create mode 100644 arch/arm/cpu/armv7/vf610/generic.c create mode 100644 arch/arm/cpu/armv7/vf610/timer.c create mode 100644 arch/arm/include/asm/arch-vf610/clock.h create mode 100644 arch/arm/include/asm/arch-vf610/crm_regs.h create mode 100644 arch/arm/include/asm/arch-vf610/imx-regs.h create mode 100644 arch/arm/include/asm/arch-vf610/iomux-vf610.h create mode 100644 doc/README.vf610 diff --git a/Makefile b/Makefile index c52f0f1..363180c 100644 --- a/Makefile +++ b/Makefile @@ -341,7 +341,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C LIBS-y += $(CPUDIR)/omap-common/libomap-common.o endif -ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs)) +ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs vf610)) LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o endif diff --git a/arch/arm/cpu/armv7/vf610/Makefile b/arch/arm/cpu/armv7/vf610/Makefile new file mode 100644 index 000..9232cd4 --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/Makefile @@ -0,0 +1,42 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(SOC).o + +COBJS += generic.o +COBJS += timer.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c new file mode 100644 index 000..87f2a86 --- /dev/null +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -0,0 +1,324 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General
[U-Boot] [PATCH v4 6/7] arm: vf610: Add Vybrid VF610 to mxc_ocotp document
This patch adds Vybrid VF610 to mxc_ocotp document. Signed-off-by: Alison Wang b18...@freescale.com --- Changes in v4: New Changes in v3: None Changes in v2: None doc/README.mxc_ocotp | 1 + 1 file changed, 1 insertion(+) diff --git a/doc/README.mxc_ocotp b/doc/README.mxc_ocotp index 9a53311..7a2863c 100644 --- a/doc/README.mxc_ocotp +++ b/doc/README.mxc_ocotp @@ -2,6 +2,7 @@ Driver implementing the fuse API for Freescale's On-Chip OTP Controller (OCOTP) on MXC This IP can be found on the following SoCs: + - Vybrid VF610, - i.MX6. Note that this IP is different from albeit similar to the IPs of the same name -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 3/7] net: fec_mxc: Add support for Vybrid VF610
This patch adds FEC support for Vybrid VF610 platform.
In function fec_open(), RCR register is only set as RGMII mode. But RCR
register should be set as RMII mode for VF610 platform.
This configuration is already done in fec_reg_setup(), so this piece of
code could just leave untouched the FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits.
Signed-off-by: Alison Wang b18...@freescale.com
Reviewed-by: Benoit Thebaudeau benoit.thebaud...@advansee.com
---
Changes in v4: None
Changes in v3:
- Remove the changes for FEC_RCNTRL_RGMII / FEC_RCNTRL_RMII /
FEC_RCNTRL_MII_MODE bits, as they are already set in fec_reg_setup()
Changes in v2:
- Use common FEC driver fec_mxc.c
drivers/net/fec_mxc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 4dbcdca..da95e28 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -516,9 +516,7 @@ static int fec_open(struct eth_device *edev)
#ifdef FEC_QUIRK_ENET_MAC
{
u32 ecr = readl(fec-eth-ecntrl) ~FEC_ECNTRL_SPEED;
- u32 rcr = (readl(fec-eth-r_cntrl)
- ~(FEC_RCNTRL_RMII | FEC_RCNTRL_RMII_10T)) |
- FEC_RCNTRL_RGMII | FEC_RCNTRL_MII_MODE;
+ u32 rcr = readl(fec-eth-r_cntrl) ~FEC_RCNTRL_RMII_10T;
if (speed == _1000BASET)
ecr |= FEC_ECNTRL_SPEED;
else if (speed != _100BASET)
--
1.8.0
___
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[U-Boot] [PATCH v4 7/7] arm: vf610: Add basic support for Vybrid VF610TWR board
VF610TWR is a board based on Vybrid VF610 SoC. This patch adds basic support for Vybrid VF610TWR board. Signed-off-by: Alison Wang b18...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: TsiChung Liew tsicl...@gmail.com --- Changes in v4: - Rename directory name 'mvf600twr' to 'vf610twr' - Rename mvf600twr.h to vf610twr.h - Use NEW_PAD_CTRL instead of MUX_PAD_CTRL - Remove CONFIG_ETHPRIME option - Add CONFIG_CMD_MEMSET option Changes in v3: - Replace BOOT_FROM by BOOT_OFFSET - Enable CONFIG_OF_LIBFDT option - Add useful define instead of raw number - Use clrsetbits_le32 to set the single bits - Move setup_iomux_enet() to board_early_init_f and remove board_eth_init() - Remove redundant define - Move CONFIG_IOMUX_SHARE_CONF_REG to imx-regs.h Changes in v2: - Add an entry to MAINTAINERS file - Rename directory name 'vybird' to 'mvf600twr' - Use standard method to set gd-ram_size - Rewrite board_mmc_getcd() function - Remove useless undef - Remove hardcoded IP addresses and MAC addresses - Remove useless CONFIG_SYS_ defines - Define C structures and access C structures to set/read registers - Move CONFIG_MACH_TYPE to board configuration file - Use common iomux-v3 code MAINTAINERS | 4 + board/freescale/vf610twr/Makefile | 39 board/freescale/vf610twr/imximage.cfg | 33 +++ board/freescale/vf610twr/vf610twr.c | 410 ++ boards.cfg| 1 + include/configs/vf610twr.h| 140 6 files changed, 627 insertions(+) create mode 100644 board/freescale/vf610twr/Makefile create mode 100644 board/freescale/vf610twr/imximage.cfg create mode 100644 board/freescale/vf610twr/vf610twr.c create mode 100644 include/configs/vf610twr.h diff --git a/MAINTAINERS b/MAINTAINERS index c05433a..e4113d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1057,6 +1057,10 @@ Eric Nelson eric.nel...@boundarydevices.com nitrogen6s i.MX6S 512MB nitrogen6s1gi.MX6S 1GB +Alison Wang b18...@freescale.com + + vf610twrVF610 + - Unknown / orphaned boards: diff --git a/board/freescale/vf610twr/Makefile b/board/freescale/vf610twr/Makefile new file mode 100644 index 000..7416228 --- /dev/null +++ b/board/freescale/vf610twr/Makefile @@ -0,0 +1,39 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB):$(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/vf610twr/imximage.cfg b/board/freescale/vf610twr/imximage.cfg new file mode 100644 index 000..b00d4c1 --- /dev/null +++ b/board/freescale/vf610twr/imximage.cfg @@ -0,0 +1,33 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not write to the Free Software + * Foundation Inc. 51 Franklin Street Fifth Floor Boston, + * MA 02110-1301 USA + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +#include asm/imx-common/imximage.cfg
[U-Boot] [PATCH 2/2] I2C: mxc_i2c: Add support for Vybrid VF610 platform
This patch adds support for Vybrid VF610 platform.
There are some differences between i.MX6 and Vybrid for I2C controller.
(1) The registers' offset are different.
(2) The I2C clock divider values are different.
(3) In I2C control register, the enable/disable/reset bit is inverted for
Vybrid comparing to i.MX6.
(4) In I2C status register, the interrupt flag bit is cleared by writing 1
for Vybrid.
For i.MX6, this bit is cleared by writing 0.
(5) In I2C status register, the arbitration lost flag bit is cleared by writing
1 for Vybrid.
For i.MX6, this bit is cleared by writing 0.
Signed-off-by: Alison Wang b18...@freescale.com
---
drivers/i2c/mxc_i2c.c | 62 +--
1 file changed, 55 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index a73b10b..85e3e8b 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -38,6 +38,15 @@
#include i2c.h
#include watchdog.h
+#ifdef I2C_QUIRK_REG
+struct mxc_i2c_regs {
+ uint8_t iadr;
+ uint8_t ifdr;
+ uint8_t i2cr;
+ uint8_t i2sr;
+ uint8_t i2dr;
+};
+#else
struct mxc_i2c_regs {
uint32_tiadr;
uint32_tifdr;
@@ -45,8 +54,8 @@ struct mxc_i2c_regs {
uint32_ti2sr;
uint32_ti2dr;
};
+#endif
-#define I2CR_IEN (1 7)
#define I2CR_IIEN (1 6)
#define I2CR_MSTA (1 5)
#define I2CR_MTX (1 4)
@@ -59,10 +68,39 @@ struct mxc_i2c_regs {
#define I2SR_IIF (1 1)
#define I2SR_RX_NO_AK (1 0)
+#ifdef I2C_QUIRK_REG
+#define I2CR_IEN (0 7)
+#define I2CR_IDIS (1 7)
+#define I2SR_IIF_CLEAR (1 1)
+#else
+#define I2CR_IEN (1 7)
+#define I2CR_IDIS (0 7)
+#define I2SR_IIF_CLEAR (0 1)
+#endif
+
#if defined(CONFIG_HARD_I2C) !defined(CONFIG_SYS_I2C_BASE)
#error define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver
#endif
+#ifdef I2C_QUIRK_REG
+static u16 i2c_clk_div[60][2] = {
+ { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
+ { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
+ { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
+ { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
+ { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
+ { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
+ { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
+ { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
+ { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
+ { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
+ { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
+ { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
+ { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
+ { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
+ { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
+};
+#else
static u16 i2c_clk_div[50][2] = {
{ 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
{ 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
@@ -78,6 +116,7 @@ static u16 i2c_clk_div[50][2] = {
{ 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
{ 3072, 0x1E }, { 3840, 0x1F }
};
+#endif
/*
* Calculate and set proper clock divider
@@ -125,7 +164,7 @@ static int bus_i2c_set_bus_speed(void *base, int speed)
writeb(idx, i2c_regs-ifdr);
/* Reset module */
- writeb(0, i2c_regs-i2cr);
+ writeb(I2CR_IDIS, i2c_regs-i2cr);
writeb(0, i2c_regs-i2sr);
return 0;
}
@@ -157,7 +196,11 @@ static int wait_for_sr_state(struct mxc_i2c_regs
*i2c_regs, unsigned state)
for (;;) {
sr = readb(i2c_regs-i2sr);
if (sr I2SR_IAL) {
+#ifdef I2C_QUIRK_REG
+ writeb(sr | I2SR_IAL, i2c_regs-i2sr);
+#else
writeb(sr ~I2SR_IAL, i2c_regs-i2sr);
+#endif
printf(%s: Arbitration lost sr=%x cr=%x state=%x\n,
__func__, sr, readb(i2c_regs-i2cr), state);
return -ERESTART;
@@ -178,7 +221,7 @@ static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte)
{
int ret;
- writeb(0, i2c_regs-i2sr);
+ writeb(I2SR_IIF_CLEAR, i2c_regs-i2sr);
writeb(byte, i2c_regs-i2dr);
ret = wait_for_sr_state(i2c_regs, ST_IIF);
if (ret 0)
@@ -214,14 +257,18 @@ static int i2c_init_transfer_(struct mxc_i2c_regs
*i2c_regs,
int ret;
/* Enable I2C controller */
+#ifdef I2C_QUIRK_REG
+ if (readb(i2c_regs-i2cr) I2CR_IDIS) {
+#else
if (!(readb(i2c_regs-i2cr) I2CR_IEN)) {
+#endif
writeb(I2CR_IEN, i2c_regs-i2cr);
/* Wait for controller
[U-Boot] [PATCH 1/2] vf610: Add I2C support for Vybrid VF610 platform
This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/arm/cpu/armv7/vf610/generic.c| 7 +++
arch/arm/include/asm/arch-vf610/clock.h | 1 +
arch/arm/include/asm/arch-vf610/crm_regs.h| 1 +
arch/arm/include/asm/arch-vf610/imx-regs.h| 1 +
arch/arm/include/asm/arch-vf610/iomux-vf610.h | 4
board/freescale/vf610twr/vf610twr.c | 14 +-
include/configs/vf610twr.h| 7 +++
7 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/vf610/generic.c
b/arch/arm/cpu/armv7/vf610/generic.c
index 87f2a86..f6ef495 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -204,6 +204,11 @@ u32 get_fec_clk(void)
return freq;
}
+static u32 get_i2c_clk(void)
+{
+ return get_ipg_clk();
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@@ -219,6 +224,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_sdhc_clk();
case MXC_FEC_CLK:
return get_fec_clk();
+ case MXC_I2C_CLK:
+ return get_i2c_clk();
default:
break;
}
diff --git a/arch/arm/include/asm/arch-vf610/clock.h
b/arch/arm/include/asm/arch-vf610/clock.h
index 04e418c..3cbae0b 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -29,6 +29,7 @@ enum mxc_clock {
MXC_UART_CLK,
MXC_ESDHC_CLK,
MXC_FEC_CLK,
+ MXC_I2C_CLK,
};
void enable_ocotp_clk(unsigned char enable);
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h
b/arch/arm/include/asm/arch-vf610/crm_regs.h
index e3f703d..6a67eb0 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -190,6 +190,7 @@ struct anadig_reg {
#define CCM_CCGR4_WKUP_CTRL_MASK (0x3 20)
#define CCM_CCGR4_CCM_CTRL_MASK(0x3 22)
#define CCM_CCGR4_GPC_CTRL_MASK(0x3 24)
+#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 12)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 10)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 4)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h
b/arch/arm/include/asm/arch-vf610/imx-regs.h
index c9df32a..742e20a 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -103,6 +103,7 @@
#define CONFIG_IOMUX_SHARE_CONF_REG
#define FEC_QUIRK_ENET_MAC
+#define I2C_QUIRK_REG
/* MSCM interrupt rounter */
#define MSCM_IRSPRC_CP0_EN 1
diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index 1c728fa..7aeadce 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -30,6 +30,8 @@
#define VF610_ENET_PAD_CTRL(PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
PAD_CTL_OBE_IBE_ENABLE)
#define VF610_DDR_PAD_CTRL PAD_CTL_DSE_25ohm
+#define VF610_I2C_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_50ohm | \
+ PAD_CTL_SPEED_HIGH | PAD_CTL_OBE_IBE_ENABLE)
enum {
VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x, 0x, 2,
__NA_, 0, VF610_ENET_PAD_CTRL),
@@ -50,6 +52,8 @@ enum {
VF610_PAD_PTA27__ESDHC1_DAT1= IOMUX_PAD(0x0044, 0x0044, 5,
__NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA28__ESDHC1_DAT2= IOMUX_PAD(0x0048, 0x0048, 5,
__NA_, 0, VF610_SDHC_PAD_CTRL),
VF610_PAD_PTA29__ESDHC1_DAT3= IOMUX_PAD(0x004c, 0x004c, 5,
__NA_, 0, VF610_SDHC_PAD_CTRL),
+ VF610_PAD_PTB14__I2C0_SCL = IOMUX_PAD(0x0090, 0x0090, 2,
0x033c, 1, VF610_I2C_PAD_CTRL),
+ VF610_PAD_PTB15__I2C0_SDA = IOMUX_PAD(0x0094, 0x0094, 2,
0x0340, 1, VF610_I2C_PAD_CTRL),
VF610_PAD_DDR_A15__DDR_A_15 = IOMUX_PAD(0x0220, 0x0220, 0,
__NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A14__DDR_A_14 = IOMUX_PAD(0x0224, 0x0224, 0,
__NA_, 0, VF610_DDR_PAD_CTRL),
VF610_PAD_DDR_A13__DDR_A_13 = IOMUX_PAD(0x0228, 0x0228, 0,
__NA_, 0, VF610_DDR_PAD_CTRL),
diff --git a/board/freescale/vf610twr/vf610twr.c
b/board/freescale/vf610twr/vf610twr.c
index f14df8b..391f97e 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -27,6 +27,7 @@
#include fsl_esdhc.h
#include miiphy.h
#include netdev.h
+#include i2c.h
DECLARE_GLOBAL_DATA_PTR;
@@ -280,6 +281,16 @@ static void setup_iomux_enet(void)
imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
}
+static void setup_iomux_i2c(void)
+{
+ static const iomux_v3_cfg_t i2c0_pads
[U-Boot] [PATCH 0/2] vf610: Add I2C support for Freescale Vybrid VF610 platform
This series contain the I2C support for Freescale Vybrid VF610 platform and VF610TWR board. Alison Wang (2): vf610: Add I2C support for Vybrid VF610 platform I2C: mxc_i2c: Add support for Vybrid VF610 platform arch/arm/cpu/armv7/vf610/generic.c| 7 +++ arch/arm/include/asm/arch-vf610/clock.h | 1 + arch/arm/include/asm/arch-vf610/crm_regs.h| 1 + arch/arm/include/asm/arch-vf610/imx-regs.h| 1 + arch/arm/include/asm/arch-vf610/iomux-vf610.h | 4 board/freescale/vf610twr/vf610twr.c | 14 +- drivers/i2c/mxc_i2c.c | 62 +++--- include/configs/vf610twr.h| 7 +++ 8 files changed, 89 insertions(+), 8 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/5] vybrid: Add vybrid CPU and vf600 tower board support
This series contains the support for vybrid CPU and vf600 tower board. The Vybrid devices are a family of Freescale's latest Dual Single Core offering with ARM Cortex A5 and CM4 based processors for Advanced Connected Radio, Entry Infotainment, and Cluster as well as high end industrial and general purpose applications. Alison Wang (5): vybrid: add vybrid CPU support vybrid: add Freescale vybrid vf600 tower board support vybrid: add uart driver support vybrid: add eSDHC driver support vybrid: add ethernet driver support Makefile | 8 ++ arch/arm/cpu/armv7/vybrid-common/Makefile| 46 +++ arch/arm/cpu/armv7/vybrid-common/cpu.c | 127 ++ arch/arm/cpu/armv7/vybrid-common/speed.c | 37 + arch/arm/cpu/armv7/vybrid-common/timer.c | 140 +++ arch/arm/cpu/armv7/vybrid/Makefile | 45 +++ arch/arm/cpu/armv7/vybrid/asm-offsets.c | 70 ++ arch/arm/cpu/armv7/vybrid/clock.c| 278 ++ arch/arm/cpu/armv7/vybrid/iomux.c| 42 ++ arch/arm/cpu/armv7/vybrid/lowlevel_init.S| 128 ++ arch/arm/cpu/armv7/vybrid/soc.c | 42 ++ arch/arm/include/asm/arch-vybrid/clock.h | 41 ++ arch/arm/include/asm/arch-vybrid/iomux.h | 323 arch/arm/include/asm/arch-vybrid/serial-vybrid.h | 213 + arch/arm/include/asm/arch-vybrid/sys_proto.h | 30 + arch/arm/include/asm/arch-vybrid/timer.h | 405 +++ arch/arm/include/asm/arch-vybrid/vybrid-pins.h | 88 arch/arm/include/asm/arch-vybrid/vybrid-regs.h | 735 arch/arm/include/asm/fec.h | 302 + arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/mach-types.h| 56 arch/arm/include/asm/u-boot.h| 3 + board/freescale/vybrid/Makefile | 40 ++ board/freescale/vybrid/vybrid.c | 488 ++ board/freescale/vybrid/vybridimage.cfg | 44 ++ boards.cfg | 2 + drivers/mmc/fsl_esdhc.c | 4 +- drivers/net/mcffec.c | 18 ++- drivers/net/mcfmii.c | 5 +- drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_vybrid.c | 129 ++ include/configs/vybrid.h | 284 +++ include/configs/vybrid_iram.h| 284 +++ 34 files changed, 4455 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/armv7/vybrid-common/Makefile create mode 100644 arch/arm/cpu/armv7/vybrid-common/cpu.c create mode 100644 arch/arm/cpu/armv7/vybrid-common/speed.c create mode 100644 arch/arm/cpu/armv7/vybrid-common/timer.c create mode 100644 arch/arm/cpu/armv7/vybrid/Makefile create mode 100644 arch/arm/cpu/armv7/vybrid/asm-offsets.c create mode 100644 arch/arm/cpu/armv7/vybrid/clock.c create mode 100644 arch/arm/cpu/armv7/vybrid/iomux.c create mode 100644 arch/arm/cpu/armv7/vybrid/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/vybrid/soc.c create mode 100644 arch/arm/include/asm/arch-vybrid/clock.h create mode 100644 arch/arm/include/asm/arch-vybrid/iomux.h create mode 100644 arch/arm/include/asm/arch-vybrid/serial-vybrid.h create mode 100644 arch/arm/include/asm/arch-vybrid/sys_proto.h create mode 100644 arch/arm/include/asm/arch-vybrid/timer.h create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-pins.h create mode 100644 arch/arm/include/asm/arch-vybrid/vybrid-regs.h create mode 100644 arch/arm/include/asm/fec.h create mode 100644 board/freescale/vybrid/Makefile create mode 100644 board/freescale/vybrid/vybrid.c create mode 100644 board/freescale/vybrid/vybridimage.cfg create mode 100644 drivers/serial/serial_vybrid.c create mode 100644 include/configs/vybrid.h create mode 100644 include/configs/vybrid_iram.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/5] vybrid: add Freescale vybrid vf600 tower board support
This patch adds Freescale vybrid vf600 tower board support.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
board/freescale/vybrid/Makefile| 40 +++
board/freescale/vybrid/vybrid.c| 488 +
board/freescale/vybrid/vybridimage.cfg | 44 +++
boards.cfg | 2 +
include/configs/vybrid.h | 284 +++
include/configs/vybrid_iram.h | 284 +++
6 files changed, 1142 insertions(+)
create mode 100644 board/freescale/vybrid/Makefile
create mode 100644 board/freescale/vybrid/vybrid.c
create mode 100644 board/freescale/vybrid/vybridimage.cfg
create mode 100644 include/configs/vybrid.h
create mode 100644 include/configs/vybrid_iram.h
diff --git a/board/freescale/vybrid/Makefile b/board/freescale/vybrid/Makefile
new file mode 100644
index 000..0749b21
--- /dev/null
+++ b/board/freescale/vybrid/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright 2012-2013 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/freescale/vybrid/vybrid.c b/board/freescale/vybrid/vybrid.c
new file mode 100644
index 000..c2da1ff
--- /dev/null
+++ b/board/freescale/vybrid/vybrid.c
@@ -0,0 +1,488 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/fec.h
+#include asm/arch/vybrid-regs.h
+#include asm/arch/vybrid-pins.h
+#include asm/arch/iomux.h
+#include asm/errno.h
+#include asm/arch/sys_proto.h
+#include i2c.h
+#include mmc.h
+#include fsl_esdhc.h
+#include usb/ehci-fsl.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DDR_IOMUX 0x0180
+#define DDR_IOMUX1 0x00010180
+
+#define PHY_DQ_TIMING 0x2613
+#define PHY_DQS_TIMING 0x2615
+#define PHY_CTRL 0x01210080
+#define PHY_MASTER_CTRL0x0001012a
+#define PHY_SLAVE_CTRL 0x00012020
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg esdhc_cfg[2] = {
+ {CONFIG_SYS_ESDHC1_BASE, 1},
+ {ESDHC2_BASE_ADDR, 1},
+};
+#endif
+
+void setup_iomux_ddr(void)
+{
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A15);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A14);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A13);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A12);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A11);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A10);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A9);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A8);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A7);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A6);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A5);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A4);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A3);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A2);
+ __raw_writel(DDR_IOMUX, IOMUXC_DDR_A1);
+ __raw_writel
[U-Boot] [PATCH 4/5] vybrid: add eSDHC driver support
This patch adds eSDHC driver support for vybrid platform. Signed-off-by: TsiChung Liew tsicl...@gmail.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: Alison Wang b18...@freescale.com --- drivers/mmc/fsl_esdhc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 35f879e..f258868 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,5 +1,5 @@ /* - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc + * Copyright 2007, 2010-2013 Freescale Semiconductor, Inc * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -479,7 +479,7 @@ static int esdhc_init(struct mmc *mmc) while ((esdhc_read32(regs-sysctl) SYSCTL_RSTA) --timeout) udelay(1000); -#ifndef ARCH_MXC +#if !defined(ARCH_MXC) !defined(CONFIG_VYBRID) /* Enable cache snooping */ esdhc_write32(regs-scr, 0x0040); #endif -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] vybrid: add uart driver support
This patch adds uart driver support for vybrid platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
drivers/serial/Makefile| 1 +
drivers/serial/serial.c| 2 +
drivers/serial/serial_vybrid.c | 129 +
3 files changed, 132 insertions(+)
create mode 100644 drivers/serial/serial_vybrid.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index de3f471..776e018 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -53,6 +53,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_VYBRID_UART) += serial_vybrid.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 7922bf0..903a520 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -178,6 +178,7 @@ serial_initfunc(pl01x_serial_initialize);
serial_initfunc(s3c44b0_serial_initialize);
serial_initfunc(sa1100_serial_initialize);
serial_initfunc(sh_serial_initialize);
+serial_initfunc(vybrid_serial_initialize);
/**
* serial_register() - Register serial driver with serial driver core
@@ -272,6 +273,7 @@ void serial_initialize(void)
s3c44b0_serial_initialize();
sa1100_serial_initialize();
sh_serial_initialize();
+ vybrid_serial_initialize();
serial_assign(default_serial_console()-name);
}
diff --git a/drivers/serial/serial_vybrid.c b/drivers/serial/serial_vybrid.c
new file mode 100644
index 000..4dd9b52
--- /dev/null
+++ b/drivers/serial/serial_vybrid.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2012-2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include watchdog.h
+#include asm/io.h
+#include serial.h
+#include linux/compiler.h
+#include asm/arch/vybrid-regs.h
+#include asm/arch/serial-vybrid.h
+#include asm/arch/clock.h
+
+#ifndef CONFIG_VYBRID_UART_BASE
+#error define CONFIG_VYBRID_UART_BASE to use the VYBRID UART driver
+#endif
+
+#define UART_CONSOLE \
+ (CONFIG_VYBRID_UART_BASE + (CONFIG_SYS_UART_PORT * 0x1000))
+
+#ifdef CONFIG_SERIAL_MULTI
+#warning Vybrid driver does not support MULTI serials.
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void vybrid_serial_setbrg(void)
+{
+ u32 clk = vybrid_get_uartclk();
+ u16 sbr;
+
+ if (!gd-baudrate)
+ gd-baudrate = CONFIG_BAUDRATE;
+
+ sbr = (u16)(clk / (16 * gd-baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ out_8((UART_CONSOLE + UBDH), (sbr 8));
+ out_8((UART_CONSOLE + UBDL), (sbr 0xFF));
+}
+
+static int vybrid_serial_getc(void)
+{
+ while (!(in_8(UART_CONSOLE + US1) US1_RDRF))
+ WATCHDOG_RESET();
+
+ setbits_8((UART_CONSOLE + US1), US1_RDRF);
+
+ return in_8(UART_CONSOLE + UD);
+}
+
+static void vybrid_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(in_8(UART_CONSOLE + US1) US1_TDRE))
+ WATCHDOG_RESET();
+
+ out_8((UART_CONSOLE + UD), c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int vybrid_serial_tstc(void)
+{
+ if (in_8(UART_CONSOLE + URCFIFO) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int vybrid_serial_init(void)
+{
+ clrbits_8((UART_CONSOLE + UC2), UC2_RE);
+ clrbits_8((UART_CONSOLE + UC2), UC2_TE);
+
+ out_8((UART_CONSOLE + UMODEM), 0);
+ out_8((UART_CONSOLE + UC1), 0);
+
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ out_8((UART_CONSOLE + UC2), (UC2_RE | UC2_TE));
+
+ return 0;
+}
+
+static struct serial_device vybrid_serial_drv = {
+ .name = vybrid_serial,
+ .start = vybrid_serial_init,
+ .stop = NULL,
+ .setbrg = vybrid_serial_setbrg,
+ .putc = vybrid_serial_putc,
+ .puts
[U-Boot] [PATCH 5/5] vybrid: add ethernet driver support
This patch adds ethernet driver support for vybrid platform.
Signed-off-by: TsiChung Liew tsicl...@gmail.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/arm/include/asm/fec.h| 302 ++
arch/arm/include/asm/u-boot.h | 3 +
drivers/net/mcffec.c | 18 ++-
drivers/net/mcfmii.c | 5 +-
4 files changed, 322 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/include/asm/fec.h
diff --git a/arch/arm/include/asm/fec.h b/arch/arm/include/asm/fec.h
new file mode 100644
index 000..5bb946e
--- /dev/null
+++ b/arch/arm/include/asm/fec.h
@@ -0,0 +1,302 @@
+/*
+ * fec.h -- Fast Ethernet Controller definitions
+ *
+ * Some definitions copied from commproc.h for MPC8xx:
+ * MPC8xx Communication Processor Module.
+ *
+ * Add FEC Structure and definitions
+ * Copyright 2004-2013 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndeffec_h
+#definefec_h
+
+/* Buffer descriptors used FEC */
+typedef struct cpm_buf_desc {
+ ushort cbd_datlen; /* Data length in buffer */
+ ushort cbd_sc; /* Status and Control */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+#define BD_SC_EMPTY((ushort)0x8000) /* Receive is empty */
+#define BD_SC_READY((ushort)0x8000) /* Transmit is ready */
+#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
+#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
+#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
+#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
+#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
+#define BD_SC_P((ushort)0x0100) /* xmt preamble */
+#define BD_SC_BR ((ushort)0x0020) /* Break received */
+#define BD_SC_FR ((ushort)0x0010) /* Framing error */
+#define BD_SC_PR ((ushort)0x0008) /* Parity error */
+#define BD_SC_OV ((ushort)0x0002) /* Overrun */
+#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
+
+/* Buffer descriptor control/status used by Ethernet receive */
+#define BD_ENET_RX_EMPTY ((ushort)0x8000)
+#define BD_ENET_RX_RO1 ((ushort)0x4000)
+#define BD_ENET_RX_WRAP((ushort)0x2000)
+#define BD_ENET_RX_INTR((ushort)0x1000)
+#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
+#define BD_ENET_RX_LAST((ushort)0x0800)
+#define BD_ENET_RX_FIRST ((ushort)0x0400)
+#define BD_ENET_RX_MISS((ushort)0x0100)
+#define BD_ENET_RX_BC ((ushort)0x0080)
+#define BD_ENET_RX_MC ((ushort)0x0040)
+#define BD_ENET_RX_LG ((ushort)0x0020)
+#define BD_ENET_RX_NO ((ushort)0x0010)
+#define BD_ENET_RX_SH ((ushort)0x0008)
+#define BD_ENET_RX_CR ((ushort)0x0004)
+#define BD_ENET_RX_OV ((ushort)0x0002)
+#define BD_ENET_RX_CL ((ushort)0x0001)
+#define BD_ENET_RX_TR BD_ENET_RX_CL
+#define BD_ENET_RX_STATS ((ushort)0x013f)/* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit */
+#define BD_ENET_TX_READY ((ushort)0x8000)
+#define BD_ENET_TX_PAD ((ushort)0x4000)
+#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
+#define BD_ENET_TX_WRAP((ushort)0x2000)
+#define BD_ENET_TX_INTR((ushort)0x1000)
+#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
+#define BD_ENET_TX_LAST((ushort)0x0800)
+#define BD_ENET_TX_TC ((ushort)0x0400)
+#define BD_ENET_TX_DEF ((ushort)0x0200)
+#define BD_ENET_TX_ABC BD_ENET_TX_DEF
+#define BD_ENET_TX_HB ((ushort)0x0100)
+#define BD_ENET_TX_LC ((ushort)0x0080)
+#define BD_ENET_TX_RL ((ushort)0x0040)
+#define BD_ENET_TX_RCMASK ((ushort)0x003c)
+#define BD_ENET_TX_UN ((ushort)0x0002)
+#define BD_ENET_TX_CSL ((ushort)0x0001)
+#define BD_ENET_TX_STATS ((ushort
[U-Boot] [PATCH 2/2] ColdFire: Update the bitops for ColdFire platform
This patch uses the general ffs definition to replace the
platform ffs definition.
This patch also fixes the build error by adding hweightN
definition for m5329evb and m5373evb.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/include/asm/bitops.h | 59 ++-
1 files changed, 27 insertions(+), 32 deletions(-)
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h
index ad971b4..525d90c 100644
--- a/arch/m68k/include/asm/bitops.h
+++ b/arch/m68k/include/asm/bitops.h
@@ -17,41 +17,36 @@ extern int test_and_change_bit(int nr, volatile void *addr);
#ifdef __KERNEL__
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-extern __inline__ int ffs(int x)
+
+extern inline int test_bit(int nr, __const__ volatile void *addr)
{
- int r = 1;
-
- if (!x)
- return 0;
- if (!(x 0x)) {
- x = 16;
- r += 16;
- }
- if (!(x 0xff)) {
- x = 8;
- r += 8;
- }
- if (!(x 0xf)) {
- x = 4;
- r += 4;
- }
- if (!(x 3)) {
- x = 2;
- r += 2;
- }
- if (!(x 1)) {
- x = 1;
- r += 1;
- }
- return r;
+ __const__ unsigned int *p = (__const__ unsigned int *) addr;
+
+ return (p[nr 5] (1UL (nr 31))) != 0;
}
+
+extern inline int test_and_set_bit(int nr, volatile void *vaddr)
+{
+ char retval;
+
+ volatile char *p = ((volatile char *)vaddr)[(nr^31) 3];
+ __asm__ __volatile__ (bset %2,(%4); sne %0
+: =d (retval), =m (*p)
+: di (nr 7), m (*p), a (p));
+
+ return retval;
+}
+
#define __ffs(x) (ffs(x) - 1)
-#define PLATFORM_FFS
+
+/*
+ * * hweightN: returns the hamming weight (i.e. the number
+ * * of bits set) of a N-bit word
+ **/
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
#endif /* __KERNEL__ */
--
1.6.4
___
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[U-Boot] [PATCH 1/2] ColdFire: Rename NANDFLASH_SIZE into CONFIG_NANDFLASH_SIZE for MCF537x
This patch fixes the build error for MCF537x. As the NANDFLASH_SIZE is redefined in boards.cfg, it is needed to rename NANDFLASH_SIZE into CONFIG_NANDFLASH_SIZE in include/configs/M5373EVB.h. Signed-off-by: Alison Wang b18...@freescale.com --- include/configs/M5373EVB.h | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index d0044b1..17a6773 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -1,7 +1,7 @@ /* * Configuation settings for the Freescale MCF5373 FireEngine board. * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. * TsiChung Liew (tsi-chung.l...@freescale.com) * * See file CREDITS for list of people who contributed to this @@ -60,7 +60,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE # define CONFIG_CMD_NAND #endif @@ -209,7 +209,7 @@ # define CONFIG_SYS_FLASH_PROTECTION /* Real (hardware) sectors protection */ #endif -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE # define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 @@ -265,9 +265,9 @@ #define CONFIG_SYS_CS1_MASK0x001f0001 #define CONFIG_SYS_CS1_CTRL0x002A3780 -#ifdef NANDFLASH_SIZE +#ifdef CONFIG_NANDFLASH_SIZE #define CONFIG_SYS_CS2_BASE0x2000 -#define CONFIG_SYS_CS2_MASK((NANDFLASH_SIZE 20) | 1) +#define CONFIG_SYS_CS2_MASK((CONFIG_NANDFLASH_SIZE 20) | 1) #define CONFIG_SYS_CS2_CTRL0x1f60 #endif -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/7] ColdFire: Clean up checkpatch warnings about volatile for ColdFire platform
From: Alison Wang b18...@freescale.com This patch cleans up checkpatch warnings about Use of volatile is usually wrong for ColdFire platform. The first patch adds clear and set bits macros for ColdFire platform. These macros can be used to clear and set multiple bits in a register using a single call. These macros can also be used to set a multiple-bit bit pattern using a mask, by specifying the mask in the 'clear' parameter and the new bit pattern in the 'set' parameter. The second patch cleans up checkpatch warnings about Use of volatile is usually wrong for MCF5227x. The third patch cleans up checkpatch warnings about Use of volatile is usually wrong for MCF52x2, including m5208evbe, m5253demo, m5253evbe, m5272c3 and m5275evb. The fourth patch cleans up checkpatch warnings about Use of volatile is usually wrong for MCF532x/MCF537x/MCF5301x. The fifth patch cleans up checkpatch warnings about Use of volatile is usually wrong for MCF523x. The sixth patch cleans up checkpatch warnings about Use of volatile is usually wrong for MCF547x and MCF548x. The seventh patch cleans up checkpatch warnings about Use of volatile is usually wrong for MCF54451 and MCF54455. Alison Wang (7): ColdFire: Add clear and set bits macros for ColdFire platform ColdFire: Clean up checkpatch warnings for MCF5227x ColdFire: Clean up checkpatch warnings for MCF52x2 ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x ColdFire: Clean up checkpatch warnings for MCF523x ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455 arch/m68k/cpu/mcf5227x/cpu.c | 13 +- arch/m68k/cpu/mcf5227x/cpu_init.c | 140 arch/m68k/cpu/mcf5227x/interrupts.c | 15 +- arch/m68k/cpu/mcf5227x/speed.c| 40 +++-- arch/m68k/cpu/mcf523x/cpu.c | 33 ++-- arch/m68k/cpu/mcf523x/cpu_init.c | 122 +++--- arch/m68k/cpu/mcf523x/interrupts.c| 15 +- arch/m68k/cpu/mcf523x/speed.c | 10 +- arch/m68k/cpu/mcf52x2/cpu.c | 115 - arch/m68k/cpu/mcf52x2/cpu_init.c | 252 ++- arch/m68k/cpu/mcf52x2/interrupts.c| 40 +++-- arch/m68k/cpu/mcf52x2/speed.c | 19 +- arch/m68k/cpu/mcf532x/cpu.c | 33 ++-- arch/m68k/cpu/mcf532x/cpu_init.c | 304 + arch/m68k/cpu/mcf532x/interrupts.c| 15 +- arch/m68k/cpu/mcf532x/speed.c | 77 + arch/m68k/cpu/mcf5445x/cpu.c | 13 +- arch/m68k/cpu/mcf5445x/cpu_init.c | 215 --- arch/m68k/cpu/mcf5445x/interrupts.c | 15 +- arch/m68k/cpu/mcf5445x/pci.c | 74 + arch/m68k/cpu/mcf5445x/speed.c| 71 arch/m68k/cpu/mcf547x_8x/cpu.c| 38 ++-- arch/m68k/cpu/mcf547x_8x/cpu_init.c | 84 +- arch/m68k/cpu/mcf547x_8x/interrupts.c | 15 +- arch/m68k/cpu/mcf547x_8x/pci.c| 59 --- arch/m68k/cpu/mcf547x_8x/slicetimer.c | 38 +++-- arch/m68k/include/asm/io.h| 38 - board/freescale/m5208evbe/m5208evbe.c | 28 ++-- board/freescale/m52277evb/m52277evb.c | 30 ++-- board/freescale/m5235evb/m5235evb.c | 43 +++-- board/freescale/m5253demo/m5253demo.c | 29 ++-- board/freescale/m5253evbe/m5253evbe.c | 30 ++-- board/freescale/m5272c3/m5272c3.c |9 +- board/freescale/m5275evb/m5275evb.c | 50 +++--- board/freescale/m53017evb/m53017evb.c | 28 ++-- board/freescale/m5329evb/m5329evb.c | 28 ++-- board/freescale/m5329evb/nand.c | 14 +- board/freescale/m5373evb/m5373evb.c | 28 ++-- board/freescale/m5373evb/nand.c | 18 +- board/freescale/m54451evb/m54451evb.c | 32 ++-- board/freescale/m54455evb/m54455evb.c | 90 ++- board/freescale/m547xevb/m547xevb.c | 34 ++-- board/freescale/m548xevb/m548xevb.c | 34 ++-- 43 files changed, 1302 insertions(+), 1126 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/7] ColdFire: Clean up checkpatch warnings for MCF5227x
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf5227x/cpu.c | 13 ++--
arch/m68k/cpu/mcf5227x/cpu_init.c | 140 +
arch/m68k/cpu/mcf5227x/interrupts.c | 15 ++--
arch/m68k/cpu/mcf5227x/speed.c| 40 +-
board/freescale/m52277evb/m52277evb.c | 30 ---
5 files changed, 123 insertions(+), 115 deletions(-)
diff --git a/arch/m68k/cpu/mcf5227x/cpu.c b/arch/m68k/cpu/mcf5227x/cpu.c
index 09ef1d2..3a0ab97 100644
--- a/arch/m68k/cpu/mcf5227x/cpu.c
+++ b/arch/m68k/cpu/mcf5227x/cpu.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -30,14 +30,15 @@
#include command.h
#include asm/immap.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+ rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
- rcm-rcr |= RCM_RCR_SOFTRST;
+ setbits_8(rcm-rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
@@ -45,14 +46,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts(CPU: );
- msk = (ccm-cir 6);
- ver = (ccm-cir 0x003f);
+ msk = (in_be16(ccm-cir) 6);
+ ver = (in_be16(ccm-cir) 0x003f);
switch (msk) {
case 0x6c:
id = 52277;
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c
b/arch/m68k/cpu/mcf5227x/cpu_init.c
index beb78f5..e23b20d 100644
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5227x/cpu_init.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -29,6 +29,7 @@
#include watchdog.h
#include asm/immap.h
+#include asm/io.h
#include asm/rtc.h
/*
@@ -40,70 +41,70 @@
*/
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ pll_t *pll = (pll_t *)MMAP_PLL;
#if !defined(CONFIG_CF_SBF)
/* Workaround, must place before fbcs */
- pll-psr = 0x12;
-
- scm1-mpr = 0x;
- scm1-pacra = 0;
- scm1-pacrb = 0;
- scm1-pacrc = 0;
- scm1-pacrd = 0;
- scm1-pacre = 0;
- scm1-pacrf = 0;
- scm1-pacrg = 0;
- scm1-pacri = 0;
+ out_be32(pll-psr, 0x12);
+
+ out_be32(scm1-mpr, 0x);
+ out_be32(scm1-pacra, 0);
+ out_be32(scm1-pacrb, 0);
+ out_be32(scm1-pacrc, 0);
+ out_be32(scm1-pacrd, 0);
+ out_be32(scm1-pacre, 0);
+ out_be32(scm1-pacrf, 0);
+ out_be32(scm1-pacrg, 0);
+ out_be32(scm1-pacri, 0);
#if (defined(CONFIG_SYS_CS0_BASE) defined(CONFIG_SYS_CS0_MASK) \
defined(CONFIG_SYS_CS0_CTRL))
- fbcs-csar0 = CONFIG_SYS_CS0_BASE;
- fbcs-cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs-csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(fbcs-csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(fbcs-cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(fbcs-csmr0, CONFIG_SYS_CS0_MASK);
#endif
#endif /* CONFIG_CF_SBF */
#if (defined(CONFIG_SYS_CS1_BASE) defined(CONFIG_SYS_CS1_MASK) \
defined(CONFIG_SYS_CS1_CTRL))
- fbcs-csar1 = CONFIG_SYS_CS1_BASE;
- fbcs-cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs-csmr1 = CONFIG_SYS_CS1_MASK;
+ out_be32(fbcs-csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(fbcs-cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(fbcs-csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) defined(CONFIG_SYS_CS2_MASK) \
defined(CONFIG_SYS_CS2_CTRL))
- fbcs-csar2 = CONFIG_SYS_CS2_BASE;
- fbcs-cscr2 = CONFIG_SYS_CS2_CTRL;
- fbcs-csmr2 = CONFIG_SYS_CS2_MASK;
+ out_be32(fbcs-csar2, CONFIG_SYS_CS2_BASE);
+ out_be32(fbcs-cscr2, CONFIG_SYS_CS2_CTRL);
+ out_be32(fbcs-csmr2, CONFIG_SYS_CS2_MASK);
#endif
#if (defined(CONFIG_SYS_CS3_BASE) defined(CONFIG_SYS_CS3_MASK) \
defined(CONFIG_SYS_CS3_CTRL))
- fbcs-csar3 = CONFIG_SYS_CS3_BASE
[U-Boot] [PATCH 3/7] ColdFire: Clean up checkpatch warnings for MCF52x2
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf52x2/cpu.c | 115 +--
arch/m68k/cpu/mcf52x2/cpu_init.c | 252 +
arch/m68k/cpu/mcf52x2/interrupts.c| 40 +++---
arch/m68k/cpu/mcf52x2/speed.c | 19 ++--
board/freescale/m5208evbe/m5208evbe.c | 28 ++--
board/freescale/m5253demo/m5253demo.c | 29 ++--
board/freescale/m5253evbe/m5253evbe.c | 30 +++--
board/freescale/m5272c3/m5272c3.c |9 +-
board/freescale/m5275evb/m5275evb.c | 50 ---
9 files changed, 310 insertions(+), 262 deletions(-)
diff --git a/arch/m68k/cpu/mcf52x2/cpu.c b/arch/m68k/cpu/mcf52x2/cpu.c
index 571d078..7c6100c 100644
--- a/arch/m68k/cpu/mcf52x2/cpu.c
+++ b/arch/m68k/cpu/mcf52x2/cpu.c
@@ -9,6 +9,8 @@
* MCF5275 additions
* Copyright (C) 2008 Arthur Shipkowski (a...@videon-central.com)
*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -32,6 +34,7 @@
#include watchdog.h
#include command.h
#include asm/immap.h
+#include asm/io.h
#include netdev.h
#include cpu.h
@@ -40,11 +43,11 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_M5208
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *)(MMAP_RCM);
+ rcm_t *rcm = (rcm_t *)(MMAP_RCM);
udelay(1000);
- rcm-rcr = RCM_RCR_SOFTRST;
+ out_8(rcm-rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
@@ -65,18 +68,21 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- wdt-sr = 0x;
- wdt-sr = 0x;
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+ out_be16(wdt-sr, 0x);
+ out_be16(wdt-sr, 0x);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt-sr = 0x; /* reset watchdog counter */
- wdt-sr = 0x;
- wdt-cr = 0;/* disable watchdog timer */
+ /* reset watchdog counter */
+ out_be16(wdt-sr, 0x);
+ out_be16(wdt-sr, 0x);
+ /* disable watchdog timer */
+ out_be16(wdt-cr, 0);
puts(WATCHDOG:disabled\n);
return (0);
@@ -84,15 +90,18 @@ int watchdog_disable(void)
int watchdog_init(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt-cr = 0;/* disable watchdog */
+ /* disable watchdog */
+ out_be16(wdt-cr, 0);
/* set timeout and enable watchdog */
- wdt-mr =
- ((CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000)) -
1;
- wdt-sr = 0x; /* reset watchdog counter */
- wdt-sr = 0x;
+ out_be16(wdt-mr,
+ (CONFIG_WATCHDOG_TIMEOUT * CONFIG_SYS_HZ) / (32768 * 1000) - 1);
+
+ /* reset watchdog counter */
+ out_be16(wdt-sr, 0x);
+ out_be16(wdt-sr, 0x);
puts(WATCHDOG:enabled\n);
return (0);
@@ -178,13 +187,13 @@ int watchdog_init(void)
#ifdef CONFIG_M5272
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
- wdp-wdog_wrrr = 0;
+ out_be16(wdp-wdog_wrrr, 0);
udelay(1000);
/* enable watchdog, set timeout to 0 and wait */
- wdp-wdog_wrrr = 1;
+ out_be16(wdp-wdog_wrrr, 1);
while (1) ;
/* we don't return! */
@@ -193,12 +202,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
int checkcpu(void)
{
- volatile sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
+ sysctrl_t *sysctrl = (sysctrl_t *) (MMAP_CFG);
uchar msk;
char *suf;
puts(CPU: );
- msk = (sysctrl-sc_dir 28) 0xf;
+ msk = (in_be32(sysctrl-sc_dir) 28) 0xf;
switch (msk) {
case 0x2:
suf = 1K75N;
@@ -221,17 +230,21 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
- wdt-wdog_wcr = 0;
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
+
+ out_be16(wdt-wdog_wcr, 0);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdt = (volatile wdog_t *)(MMAP_WDOG);
+ wdog_t *wdt = (wdog_t *)(MMAP_WDOG);
- wdt-wdog_wcr = 0; /* reset watchdog counter */
- wdt-wdog_wirr = 0; /* disable watchdog interrupt */
- wdt-wdog_wrrr = 0; /* disable watchdog timer */
+ /* reset watchdog counter */
+ out_be16(wdt-wdog_wcr, 0);
+ /* disable watchdog interrupt */
+ out_be16(wdt-wdog_wirr, 0);
+ /* disable watchdog timer */
+ out_be16(wdt-wdog_wrrr
[U-Boot] [PATCH 7/7] ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf5445x/cpu.c | 13 +-
arch/m68k/cpu/mcf5445x/cpu_init.c | 215 +
arch/m68k/cpu/mcf5445x/interrupts.c | 15 ++-
arch/m68k/cpu/mcf5445x/pci.c | 74 ++--
arch/m68k/cpu/mcf5445x/speed.c| 71 ++-
board/freescale/m54451evb/m54451evb.c | 32 +++---
board/freescale/m54455evb/m54455evb.c | 90 --
7 files changed, 267 insertions(+), 243 deletions(-)
diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index 323a54e..adfc708 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -31,14 +31,15 @@
#include netdev.h
#include asm/immap.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+ rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
- rcm-rcr |= RCM_RCR_SOFTRST;
+ setbits_8(rcm-rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
@@ -46,14 +47,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts(CPU: );
- msk = (ccm-cir 6);
- ver = (ccm-cir 0x003f);
+ msk = (in_be16(ccm-cir) 6);
+ ver = (in_be16(ccm-cir) 0x003f);
switch (msk) {
case 0x48:
id = 54455;
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c
b/arch/m68k/cpu/mcf5445x/cpu_init.c
index fdcd185..3f9209f 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -30,6 +30,7 @@
#include asm/immap.h
#include asm/processor.h
#include asm/rtc.h
+#include asm/io.h
#if defined(CONFIG_CMD_NET)
#include config.h
@@ -46,64 +47,64 @@
*/
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
- scm1-mpr = 0x;
- scm1-pacra = 0;
- scm1-pacrb = 0;
- scm1-pacrc = 0;
- scm1-pacrd = 0;
- scm1-pacre = 0;
- scm1-pacrf = 0;
- scm1-pacrg = 0;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ out_be32(scm1-mpr, 0x);
+ out_be32(scm1-pacra, 0);
+ out_be32(scm1-pacrb, 0);
+ out_be32(scm1-pacrc, 0);
+ out_be32(scm1-pacrd, 0);
+ out_be32(scm1-pacre, 0);
+ out_be32(scm1-pacrf, 0);
+ out_be32(scm1-pacrg, 0);
/* FlexBus */
- gpio-par_be =
- GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
- GPIO_PAR_BE_BE0_BE0;
- gpio-par_fbctl =
- GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
- GPIO_PAR_FBCTL_TS_TS;
+ out_8(gpio-par_be,
+ GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+ GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+ out_8(gpio-par_fbctl,
+ GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+ GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#if !defined(CONFIG_CF_SBF)
#if (defined(CONFIG_SYS_CS0_BASE) defined(CONFIG_SYS_CS0_MASK)
defined(CONFIG_SYS_CS0_CTRL))
- fbcs-csar0 = CONFIG_SYS_CS0_BASE;
- fbcs-cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs-csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(fbcs-csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(fbcs-cscr0, CONFIG_SYS_CS0_CTRL);
+ out_be32(fbcs-csmr0, CONFIG_SYS_CS0_MASK);
#endif
#endif
#if (defined(CONFIG_SYS_CS1_BASE) defined(CONFIG_SYS_CS1_MASK)
defined(CONFIG_SYS_CS1_CTRL))
/* Latch chipselect */
- fbcs-csar1 = CONFIG_SYS_CS1_BASE;
- fbcs-cscr1 = CONFIG_SYS_CS1_CTRL;
- fbcs-csmr1 = CONFIG_SYS_CS1_MASK;
+ out_be32(fbcs-csar1, CONFIG_SYS_CS1_BASE);
+ out_be32(fbcs-cscr1, CONFIG_SYS_CS1_CTRL);
+ out_be32(fbcs-csmr1, CONFIG_SYS_CS1_MASK);
#endif
#if (defined(CONFIG_SYS_CS2_BASE) defined(CONFIG_SYS_CS2_MASK)
defined
[U-Boot] [PATCH 6/7] ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf547x_8x/cpu.c| 38 +++---
arch/m68k/cpu/mcf547x_8x/cpu_init.c | 84 +
arch/m68k/cpu/mcf547x_8x/interrupts.c | 15 +++---
arch/m68k/cpu/mcf547x_8x/pci.c| 59 ---
arch/m68k/cpu/mcf547x_8x/slicetimer.c | 38 ---
board/freescale/m547xevb/m547xevb.c | 34 +++--
board/freescale/m548xevb/m548xevb.c | 34 +++--
7 files changed, 158 insertions(+), 144 deletions(-)
diff --git a/arch/m68k/cpu/mcf547x_8x/cpu.c b/arch/m68k/cpu/mcf547x_8x/cpu.c
index 7590f2c..157a8e4 100644
--- a/arch/m68k/cpu/mcf547x_8x/cpu.c
+++ b/arch/m68k/cpu/mcf547x_8x/cpu.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -31,19 +31,20 @@
#include netdev.h
#include asm/immap.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- gptmr-pre = 10;
- gptmr-cnt = 1;
+ out_be16(gptmr-pre, 10);
+ out_be16(gptmr-cnt, 1);
/* enable watchdog, set timeout to 0 and wait */
- gptmr-mode = GPT_TMS_SGPIO;
- gptmr-ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE;
+ out_8(gptmr-mode, GPT_TMS_SGPIO);
+ out_8(gptmr-ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
/* we don't return! */
return 1;
@@ -51,12 +52,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
int checkcpu(void)
{
- volatile siu_t *siu = (siu_t *) MMAP_SIU;
+ siu_t *siu = (siu_t *) MMAP_SIU;
u16 id = 0;
puts(CPU: );
- switch ((siu-jtagid 0x000FF000) 12) {
+ switch ((in_be32(siu-jtagid) 0x000FF000) 12) {
case 0x0C:
id = 5485;
break;
@@ -111,18 +112,18 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
void hw_watchdog_reset(void)
{
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- gptmr-ocpw = 0xa5;
+ out_8(gptmr-ocpw, 0xa5);
}
int watchdog_disable(void)
{
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
- gptmr-mode = 0;
- gptmr-ctrl = 0;
+ out_8(gptmr-mode, 0);
+ out_8(gptmr-ctrl, 0);
puts(WATCHDOG:disabled\n);
@@ -131,14 +132,13 @@ int watchdog_disable(void)
int watchdog_init(void)
{
+ gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
- volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
+ out_be16(gptmr-pre, CONFIG_WATCHDOG_TIMEOUT);
+ out_be16(gptmr-cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
- gptmr-pre = CONFIG_WATCHDOG_TIMEOUT;
- gptmr-cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
-
- gptmr-mode = GPT_TMS_SGPIO;
- gptmr-ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
+ out_8(gptmr-mode, GPT_TMS_SGPIO);
+ out_8(gptmr-ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
puts(WATCHDOG:enabled\n);
return (0);
diff --git a/arch/m68k/cpu/mcf547x_8x/cpu_init.c
b/arch/m68k/cpu/mcf547x_8x/cpu_init.c
index 60c9126..4eb8a7c 100644
--- a/arch/m68k/cpu/mcf547x_8x/cpu_init.c
+++ b/arch/m68k/cpu/mcf547x_8x/cpu_init.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include common.h
#include MCD_dma.h
#include asm/immap.h
+#include asm/io.h
#if defined(CONFIG_CMD_NET)
#include config.h
@@ -44,58 +45,59 @@
*/
void cpu_init_f(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
- xlbarb-adrto = 0x2000;
- xlbarb-datto = 0x2500;
- xlbarb-busto = 0x3000;
+ out_be32(xlbarb-adrto, 0x2000);
+ out_be32(xlbarb-datto, 0x2500);
+ out_be32(xlbarb-busto, 0x3000);
- xlbarb-cfg = XARB_CFG_AT | XARB_CFG_DT;
+ out_be32(xlbarb-cfg, XARB_CFG_AT | XARB_CFG_DT);
/* Master Priority Enable */
- xlbarb-prien = 0xff;
- xlbarb-pri
[U-Boot] [PATCH 4/7] ColdFire: Clean up checkpatch warnings for MCF532x/MCF537x/MCF5301x
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf532x/cpu.c | 33 ++--
arch/m68k/cpu/mcf532x/cpu_init.c | 304 +
arch/m68k/cpu/mcf532x/interrupts.c| 15 +-
arch/m68k/cpu/mcf532x/speed.c | 77 +
board/freescale/m53017evb/m53017evb.c | 28 ++--
board/freescale/m5329evb/m5329evb.c | 28 ++--
board/freescale/m5329evb/nand.c | 14 +-
board/freescale/m5373evb/m5373evb.c | 28 ++--
board/freescale/m5373evb/nand.c | 18 +-
9 files changed, 287 insertions(+), 258 deletions(-)
diff --git a/arch/m68k/cpu/mcf532x/cpu.c b/arch/m68k/cpu/mcf532x/cpu.c
index 3346784..4f160a6 100644
--- a/arch/m68k/cpu/mcf532x/cpu.c
+++ b/arch/m68k/cpu/mcf532x/cpu.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -31,15 +31,16 @@
#include netdev.h
#include asm/immap.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
+ rcm_t *rcm = (rcm_t *) (MMAP_RCM);
udelay(1000);
- rcm-rcr |= RCM_RCR_SOFTRST;
+ setbits_8(rcm-rcr, RCM_RCR_SOFTRST);
/* we don't return! */
return 0;
@@ -47,14 +48,14 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts(CPU: );
- msk = (ccm-cir 6);
- ver = (ccm-cir 0x003f);
+ msk = (in_be16(ccm-cir) 6);
+ ver = (in_be16(ccm-cir) 0x003f);
switch (msk) {
#ifdef CONFIG_MCF5301x
case 0x78:
@@ -115,18 +116,20 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
- wdp-sr = 0x; /* Count register */
- wdp-sr = 0x; /* Count register */
+ /* Count register */
+ out_be16(wdp-sr, 0x);
+ out_be16(wdp-sr, 0x);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
- wdp-cr |= WTM_WCR_HALTED; /* halted watchdog timer */
+ /* halted watchdog timer */
+ setbits_be16(wdp-cr, WTM_WCR_HALTED);
puts(WATCHDOG:disabled\n);
return (0);
@@ -134,18 +137,18 @@ int watchdog_disable(void)
int watchdog_init(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CONFIG_SYS_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT);
#ifdef CONFIG_M5329
- wdp-mr = (wdog_module / 8192);
+ out_be16(wdp-mr, wdog_module / 8192);
#else
- wdp-mr = (wdog_module / 4096);
+ out_be16(wdp-mr, wdog_module / 4096);
#endif
- wdp-cr = WTM_WCR_EN;
+ out_be16(wdp-cr, WTM_WCR_EN);
puts(WATCHDOG:enabled\n);
return (0);
diff --git a/arch/m68k/cpu/mcf532x/cpu_init.c b/arch/m68k/cpu/mcf532x/cpu_init.c
index 6f551b6..f571fad 100644
--- a/arch/m68k/cpu/mcf532x/cpu_init.c
+++ b/arch/m68k/cpu/mcf532x/cpu_init.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * (C) Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2008, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include common.h
#include watchdog.h
#include asm/immap.h
+#include asm/io.h
#if defined(CONFIG_CMD_NET)
#include config.h
@@ -38,72 +39,68 @@
#ifdef CONFIG_MCF5301x
void cpu_init_f(void)
{
- volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
- /* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
- /*wdog-cr = 0; */
-#endif
-
- scm1-mpr = 0x;
- scm1-pacra = 0;
- scm1-pacrb = 0;
- scm1-pacrc = 0;
- scm1-pacrd = 0;
- scm1-pacre = 0;
- scm1-pacrf = 0;
- scm1-pacrg = 0;
+ scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+
+ out_be32(scm1-mpr, 0x);
+ out_be32(scm1-pacra, 0
[U-Boot] [PATCH 1/7] ColdFire: Add clear and set bits macros for ColdFire platform
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/include/asm/io.h | 38 +-
1 files changed, 37 insertions(+), 1 deletions(-)
diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h
index d86eaf9..50ed749 100644
--- a/arch/m68k/include/asm/io.h
+++ b/arch/m68k/include/asm/io.h
@@ -1,7 +1,7 @@
/*
* IO header file
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -225,6 +225,42 @@ extern inline void out_be32(volatile unsigned *addr, int
val)
*addr = val;
}
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+ out_##type((addr), in_##type(addr) ~(clear))
+
+#define setbits(type, addr, set) \
+ out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
static inline void sync(void)
{
/* This sync function is for PowerPC or other architecture instruction
--
1.6.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/7] ColdFire: Clean up checkpatch warnings for MCF523x
Signed-off-by: Alison Wang b18...@freescale.com
---
arch/m68k/cpu/mcf523x/cpu.c | 33 +
arch/m68k/cpu/mcf523x/cpu_init.c| 122 ++-
arch/m68k/cpu/mcf523x/interrupts.c | 15 ++--
arch/m68k/cpu/mcf523x/speed.c | 10 ++-
board/freescale/m5235evb/m5235evb.c | 43 +++--
5 files changed, 120 insertions(+), 103 deletions(-)
diff --git a/arch/m68k/cpu/mcf523x/cpu.c b/arch/m68k/cpu/mcf523x/cpu.c
index 2376f97..a3f5684 100644
--- a/arch/m68k/cpu/mcf523x/cpu.c
+++ b/arch/m68k/cpu/mcf523x/cpu.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -31,28 +31,29 @@
#include netdev.h
#include asm/immap.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
- ccm-rcr = CCM_RCR_SOFTRST;
+ out_8(ccm-rcr, CCM_RCR_SOFTRST);
/* we don't return! */
return 0;
-};
+}
int checkcpu(void)
{
- volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
+ ccm_t *ccm = (ccm_t *) MMAP_CCM;
u16 msk;
u16 id = 0;
u8 ver;
puts(CPU: );
- msk = (ccm-cir 6);
- ver = (ccm-cir 0x003f);
+ msk = (in_be16(ccm-cir) 6);
+ ver = (in_be16(ccm-cir) 0x003f);
switch (msk) {
case 0x31:
id = 5235;
@@ -76,19 +77,21 @@ int checkcpu(void)
/* Called by macro WATCHDOG_RESET */
void watchdog_reset(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
- wdp-sr = 0x; /* Count register */
+ /* Count register */
+ out_be16(wdp-sr, 0x);
asm(nop);
- wdp-sr = 0x; /* Count register */
+ out_be16(wdp-sr, 0x);
}
int watchdog_disable(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
/* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
- wdp-cr |= WTM_WCR_HALTED; /* halted watchdog timer */
+ /* halted watchdog timer */
+ setbits_be16(wdp-cr, WTM_WCR_HALTED);
puts(WATCHDOG:disabled\n);
return (0);
@@ -96,15 +99,15 @@ int watchdog_disable(void)
int watchdog_init(void)
{
- volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
+ wdog_t *wdp = (wdog_t *) (MMAP_WDOG);
u32 wdog_module = 0;
/* set timeout and enable watchdog */
wdog_module = ((CONFIG_SYS_CLK / CONFIG_SYS_HZ) *
CONFIG_WATCHDOG_TIMEOUT);
wdog_module |= (wdog_module / 8192);
- wdp-mr = wdog_module;
+ out_be16(wdp-mr, wdog_module);
- wdp-cr = WTM_WCR_EN;
+ out_be16(wdp-cr, WTM_WCR_EN);
puts(WATCHDOG:enabled\n);
return (0);
diff --git a/arch/m68k/cpu/mcf523x/cpu_init.c b/arch/m68k/cpu/mcf523x/cpu_init.c
index 0f299f0..d1c0b40 100644
--- a/arch/m68k/cpu/mcf523x/cpu_init.c
+++ b/arch/m68k/cpu/mcf523x/cpu_init.c
@@ -3,7 +3,7 @@
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, w...@denx.de.
*
- * (C) Copyright 2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
* TsiChung Liew (tsi-chung.l...@freescale.com)
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,7 @@
#include common.h
#include watchdog.h
#include asm/immap.h
+#include asm/io.h
#if defined(CONFIG_CMD_NET)
#include config.h
@@ -44,74 +45,74 @@
*/
void cpu_init_f(void)
{
- volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
- volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
- volatile scm_t *scm = (scm_t *) MMAP_SCM;
+ gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+ fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ wdog_t *wdog = (wdog_t *) MMAP_WDOG;
+ scm_t *scm = (scm_t *) MMAP_SCM;
/* watchdog is enabled by default - disable the watchdog */
#ifndef CONFIG_WATCHDOG
- wdog-cr = 0;
+ out_be16(wdog-cr, 0);
#endif
- scm-rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
+ out_be32(scm-rambar, CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
/* Port configuration */
- gpio-par_cs = 0;
+ out_8(gpio-par_cs, 0);
#if (defined(CONFIG_SYS_CS0_BASE) defined(CONFIG_SYS_CS0_MASK)
defined(CONFIG_SYS_CS0_CTRL))
- fbcs-csar0 = CONFIG_SYS_CS0_BASE;
- fbcs-cscr0 = CONFIG_SYS_CS0_CTRL;
- fbcs-csmr0 = CONFIG_SYS_CS0_MASK;
+ out_be32(fbcs-csar0, CONFIG_SYS_CS0_BASE);
+ out_be32(fbcs-cscr0, CONFIG_SYS_CS0_CTRL
[U-Boot] [PATCH v2 04/10] arm: ls102xa: Add etsec support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 24 +++-
drivers/net/tsec.c | 7 +++
include/fsl_mdio.h | 3 +++
include/tsec.h | 7 ++-
4 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 8d09f5d..3081228 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -12,6 +12,15 @@
#include asm/io.h
#include asm/errno.h
+void tsec_mdio_sync(void)
+{
+#if defined(CONFIG_PPC)
+ asm(sync);
+#elif defined(CONFIG_ARM)
+ asm(dsb);
+#endif
+}
+
void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
{
@@ -19,7 +28,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem
*phyregs, int port_addr,
out_be32(phyregs-miimadd, (port_addr 8) | (regnum 0x1f));
out_be32(phyregs-miimcon, value);
- asm(sync);
+ tsec_mdio_sync();
while ((in_be32(phyregs-miimind) MIIMIND_BUSY) timeout--)
;
@@ -37,11 +46,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem
*phyregs, int port_addr,
/* Clear the command register, and wait */
out_be32(phyregs-miimcom, 0);
- asm(sync);
+ tsec_mdio_sync();
/* Initiate a read command, and wait */
out_be32(phyregs-miimcom, MIIMCOM_READ_CYCLE);
- asm(sync);
+ tsec_mdio_sync();
/* Wait for the the indication that the read is done */
while ((in_be32(phyregs-miimind) (MIIMIND_NOTVALID | MIIMIND_BUSY))
@@ -98,8 +107,13 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info
*info)
return -1;
}
- bus-read = tsec_phy_read;
- bus-write = tsec_phy_write;
+ if (info-priv_mdio_read) {
+ bus-read = info-priv_mdio_read;
+ bus-write = info-priv_mdio_write;
+ } else {
+ bus-read = tsec_phy_read;
+ bus-write = tsec_phy_write;
+ }
bus-reset = fsl_pq_mdio_reset;
sprintf(bus-name, info-name);
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..a220221 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
#include fsl_mdio.h
#include asm/errno.h
#include asm/processor.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
do {
uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
}
/* This returns the status bits of the device. The return value
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index a531edf..fb7df08 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -57,6 +57,9 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int
dev_addr,
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
+ int (*priv_mdio_read)(struct mii_dev *bus, int addr, int devad, int
reg);
+ int (*priv_mdio_write)(struct mii_dev *bus, int addr, int devad, int
reg,
+ u16 val);
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..5b74f67 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
#include net.h
#include config.h
#include phy.h
-#include fsl_mdio.h
+#ifdef CONFIG_LS102xA
+#define TSEC_SIZE 0x4
+#define TSEC_MDIO_OFFSET 0x4
+#else
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
@@ -128,6 +132,7 @@
#define DMACTRL_INIT_SETTINGS 0x00c3
#define DMACTRL_GRS0x0010
#define DMACTRL_GTS0x0008
+#define DMACTRL_LE 0x8000
#define TSTAT_CLEAR_THALT 0x8000
#define RSTAT_CLEAR_RHALT 0x0080
--
1.8.0
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[U-Boot] [PATCH v2 01/10] arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Change log:
v2: Add serdes support.
Update DDR frequency and data rate information.
Fix overflow condition error for the timer.
arch/arm/cpu/armv7/ls102xa/Makefile | 12 +
arch/arm/cpu/armv7/ls102xa/clock.c| 131 ++
arch/arm/cpu/armv7/ls102xa/cpu.c | 103 +
arch/arm/cpu/armv7/ls102xa/fdt.c | 73
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 119 ++
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | 12 +
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c | 41 ++
arch/arm/cpu/armv7/ls102xa/timer.c| 127 ++
arch/arm/include/asm/arch-ls102xa/clock.h | 23 ++
arch/arm/include/asm/arch-ls102xa/config.h| 69
arch/arm/include/asm/arch-ls102xa/fsl_serdes.h| 33 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 461 ++
arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 +++
arch/arm/include/asm/config.h | 4 +
arch/arm/include/asm/io.h | 8 +-
drivers/watchdog/Makefile | 2 +-
16 files changed, 1269 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile
create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c
create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
new file mode 100644
index 000..d82ce8d
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clock.o
+obj-y += timer.o
+
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c
b/arch/arm/cpu/armv7/ls102xa/clock.c
new file mode 100644
index 000..75bb0e9
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/immap_ls102xa.h
+#include asm/arch/clock.h
+#include fsl_ifc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[6] = {
+ [0] = 0,/* CC1 PPL / 1 */
+ [1] = 0,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 1,/* CC2 PPL / 2 */
+ };
+
+ const u8 core_cplx_pll_div[6] = {
+ [0] = 1,/* CC1 PPL / 1 */
+ [1] = 2,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 2,/* CC2 PPL / 2 */
+ };
+
+ uint i;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sys_info-freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info-freq_ddrbus = sysclk;
+#endif
+
+ sys_info-freq_systembus *= (in_be32(gur-rcwsr[0
[U-Boot] [PATCH v2 05/10] arm: ls102xa: Add esdhc support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613..aec459f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct
mmc_data *data)
else if (cmd-resp_type MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) ||
defined(CONFIG_LS102xA)
if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg
*cfg)
memset(cfg-cfg, 0, sizeof(cfg-cfg));
voltage_caps = 0;
- caps = regs-hostcapblt;
+ caps = esdhc_read32(regs-hostcapblt);
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps ~(ESDHC_HOSTCAPBLT_SRS |
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 9814964..c1b6648 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
};
/* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32clrbits_le32
+#define esdhc_setbits32setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
--
1.8.0
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[U-Boot] [PATCH v2 03/10] net: Merge asm/fsl_enet.h into fsl_mdio.h
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com
---
Change log:
v2: no change.
arch/powerpc/include/asm/fsl_enet.h | 24
board/freescale/mpc8360emds/mpc8360emds.c | 2 +-
board/freescale/mpc837xemds/mpc837xemds.c | 1 -
drivers/net/fm/dtsec.c| 1 -
drivers/net/fm/fm.h | 2 +-
drivers/net/fm/init.c | 1 +
drivers/net/fm/memac.c| 1 -
drivers/net/fm/tgec.c | 1 -
drivers/net/fsl_mdio.c| 1 -
drivers/qe/uec.h | 1 -
include/fm_eth.h | 2 +-
include/fsl_mdio.h| 13 -
include/tsec.h| 2 +-
13 files changed, 17 insertions(+), 35 deletions(-)
delete mode 100644 arch/powerpc/include/asm/fsl_enet.h
diff --git a/arch/powerpc/include/asm/fsl_enet.h
b/arch/powerpc/include/asm/fsl_enet.h
deleted file mode 100644
index 96146b6..000
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include phy.h
-
-struct tsec_mii_mng {
- u32 miimcfg;/* MII management configuration reg */
- u32 miimcom;/* MII management command reg */
- u32 miimadd;/* MII management address reg */
- u32 miimcon;/* MII management control reg */
- u32 miimstat; /* MII management status reg */
- u32 miimind;/* MII management indication reg */
- u32 ifstat; /* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index ac96163..5ff9dff 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -11,13 +11,13 @@
#include i2c.h
#include miiphy.h
#include phy.h
+#include fsl_mdio.h
#if defined(CONFIG_PCI)
#include pci.h
#endif
#include spd_sdram.h
#include asm/mmu.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/mmu.h
#if defined(CONFIG_OF_LIBFDT)
#include libfdt.h
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c
b/board/freescale/mpc837xemds/mpc837xemds.c
index 0a3c972..c749e55 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -10,7 +10,6 @@
#include i2c.h
#include asm/io.h
#include asm/fsl_mpc83xx_serdes.h
-#include asm/fsl_enet.h
#include spd_sdram.h
#include tsec.h
#include libfdt.h
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 78bbd43..8d3dc0e 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,6 @@
#include common.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_dtsec.h
#include fsl_mdio.h
#include phy.h
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 43de114..c8eba4f 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -8,8 +8,8 @@
#define __FM_H__
#include common.h
+#include phy.h
#include fm_eth.h
-#include asm/fsl_enet.h
#include asm/fsl_fman.h
/* Port ID */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index cd787f4..7371dbf 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
#include common.h
#include asm/io.h
#include asm/fsl_serdes.h
+#include fsl_mdio.h
#include fm.h
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f..9499290 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_memac.h
#include fm.h
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index f450f80..5017123 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_tgec.h
#include fm.h
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 1d88e65..8d09f5d 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,7 +11,6 @@
#include
[U-Boot] [PATCH v2 0/9] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 06/10] driver/ddr/freescale: Add support of accumulate ECC
From: York Sun york...@freescale.com If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun york...@freescale.com --- Change log: v2: no change. drivers/ddr/fsl/ctrl_regs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index dcf6287..fa9c257 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int x32_en = 0;/* x32 enable */ unsigned int pchb8 = 0; /* precharge bit 8 enable */ unsigned int hse; /* Global half strength override */ + unsigned int acc_ecc_en = 0;/* Accumulated ECC enable */ unsigned int mem_halt = 0; /* memory controller halt */ unsigned int bi = 0;/* Bypass initialization */ @@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ba_intlv_ctl = popts-ba_intlv_ctl; hse = popts-half_strength_driver_enable; + /* set when ddr bus width 64 */ + acc_ecc_en = (dbw != 0 ecc_en == 1) ? 1 : 0; + ddr-ddr_sdram_cfg = (0 | ((mem_en 0x1) 31) | ((sren 0x1) 30) @@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((x32_en 0x1) 5) | ((pchb8 0x1) 4) | ((hse 0x1) 3) + | ((acc_ecc_en 0x1) 2) | ((mem_halt 0x1) 1) | ((bi 0x1) 0) ); -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 10/10] arm: ls102xa: Add basic support for LS1021ATWR board
Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v2: New file. board/freescale/ls1021atwr/Makefile | 7 + board/freescale/ls1021atwr/README | 109 +++ board/freescale/ls1021atwr/ls1021atwr.c | 499 boards.cfg | 1 + include/configs/ls1021atwr.h| 285 ++ 5 files changed, 901 insertions(+) create mode 100644 board/freescale/ls1021atwr/Makefile create mode 100644 board/freescale/ls1021atwr/README create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c create mode 100644 include/configs/ls1021atwr.h diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile new file mode 100644 index 000..b5df668 --- /dev/null +++ b/board/freescale/ls1021atwr/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README new file mode 100644 index 000..d2821cb --- /dev/null +++ b/board/freescale/ls1021atwr/README @@ -0,0 +1,109 @@ +Overview + +The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021ATWR board
[U-Boot] [PATCH v2 08/10] driver/ddr/fsl: Add support of overriding chip select write leveling
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v2: no change.
drivers/ddr/fsl/ctrl_regs.c | 3 +++
drivers/ddr/fsl/interactive.c | 2 ++
include/fsl_ddr_sdram.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index fa9c257..462d471 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2273,6 +2273,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
if (ip_rev 0x40400)
unq_mrs_en = 1;
+ if (ip_rev 0x40700)
+ ddr-debug[18] = popts-cswl_override;
+
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 7fb4187..6aa16b2 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t
*popts)
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e8a2db9..987119b 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0 0x0401
/*
* Generalized parameters for memory controller configuration,
* might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+ unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
--
1.8.0
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[U-Boot] [PATCH v2 07/10] driver/ddr/freescale: Fix DDR3 driver for ARM
From: York Sun york...@freescale.com Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun york...@freescale.com --- Change log: v2: no change. drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index d4ed9ae..59f2fd6 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -194,7 +194,7 @@ step2: * For example, 2GB on 666MT/s 64-bit bus takes about 402ms * Let's wait for 800ms */ - bus_width = 3 - ((ddr-sdram_cfg SDRAM_CFG_DBW_MASK) + bus_width = 3 - ((ddr_in32(ddr-sdram_cfg) SDRAM_CFG_DBW_MASK) SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller (6 - bus_width)) * 100 / (get_ddr_freq(0) 20)) 1; -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 02/10] arm: ls102xa: Add i2c support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: no change.
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..792fc40 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
- defined(CONFIG_MX6)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR
--
1.8.0
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[U-Boot] [PATCH v2 09/10] arm: ls102xa: Add basic support for LS1021AQDS board
Signed-off-by: Alison Wang alison.w...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: York Sun york...@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Change log: v2: Remove ethaddr/ipaddr setting. Add board maintainer. Add serdes and multiple ethernet controllers support. board/freescale/ls1021aqds/Makefile | 9 + board/freescale/ls1021aqds/README | 112 +++ board/freescale/ls1021aqds/ddr.c | 169 +++ board/freescale/ls1021aqds/ddr.h | 64 board/freescale/ls1021aqds/eth.c | 129 board/freescale/ls1021aqds/ls1021aqds.c | 244 +++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ boards.cfg| 1 + include/common.h | 5 +- include/configs/ls1021aqds.h | 419 ++ lib/lmb.c | 2 +- 11 files changed, 1185 insertions(+), 4 deletions(-) create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/eth.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 include/configs/ls1021aqds.h diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile new file mode 100644 index 000..3b6903c --- /dev/null +++ b/board/freescale/ls1021aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README new file mode 100644 index 000..c561776 --- /dev/null +++ b/board/freescale/ls1021aqds/README @@ -0,0 +1,112 @@ +Overview + +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM
[U-Boot] [PATCH 1/2] arm: ls102xa: Add SD boot support for LS1021AQDS board
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
---
Makefile | 15 -
arch/arm/cpu/armv7/ls102xa/Makefile | 1 +
arch/arm/cpu/armv7/ls102xa/spl.c | 35 +++
arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds | 83 +++
arch/arm/include/asm/arch-ls102xa/spl.h | 20 +++
board/freescale/common/qixis.h| 7 +++
board/freescale/ls1021aqds/ddr.c | 5 +-
board/freescale/ls1021aqds/ls1021aqds.c | 31 ++
board/freescale/ls1021aqds/ls102xa_pbi.cfg| 8 +++
board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | 14 +
boards.cfg| 1 +
common/spl/spl_mmc.c | 2 +
include/configs/ls1021aqds.h | 64 +
tools/pblimage.c | 20 +--
14 files changed, 300 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/spl.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds
create mode 100644 arch/arm/include/asm/arch-ls102xa/spl.h
create mode 100644 board/freescale/ls1021aqds/ls102xa_pbi.cfg
create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
diff --git a/Makefile b/Makefile
index b8cce74..760e8b0 100644
--- a/Makefile
+++ b/Makefile
@@ -711,6 +711,7 @@ ALL-y += u-boot.srec u-boot.bin System.map binary_size_check
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
+ALL-$(CONFIG_SPL_PBL_PAD) += spl/u-boot-spl-pbl-pad.bin
else
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
endif
@@ -936,13 +937,25 @@ endif
u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE
$(call if_changed,cat)
+OBJCOPYFLAGS_u-boot-spl-pbl-pad.bin = -I binary -O binary
--pad-to=$(CONFIG_SPL_MAX_SIZE) \
+ --gap-fill=0xff
+
+spl/u-boot-spl-pbl-pad.bin: spl/u-boot-spl.bin FORCE
+ $(call if_changed,pad_cat)
+
+ifdef CONFIG_SPL_PBL_PAD
+SPLPBL_BINLOAD := spl/u-boot-spl-pbl-pad.bin
+else
+SPLPBL_BINLOAD := spl/u-boot-spl.bin
+endif
+
#Add a target to create boot binary having SPL binary in PBI format
#concatenated with u-boot binary. It is need by PowerPC SoC having
#internal SRAM = 512KB.
MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:%=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:%=%) -T pblimage
-spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
+spl/u-boot-spl.pbl: $(SPLPBL_BINLOAD) FORCE
$(call if_changed,mkimage)
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary
--pad-to=$(CONFIG_SPL_PAD_TO) \
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
index d82ce8d..56ef3a7 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -10,3 +10,4 @@ obj-y += timer.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
+obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c
new file mode 100644
index 000..77ea1ee
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/spl.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include spl.h
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_MMC1;
+#endif
+ return BOOT_DEVICE_NAND;
+}
+
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ case BOOT_DEVICE_NAND:
+ return 0;
+ break;
+ default:
+ puts(spl: error: unsupported device\n);
+ hang();
+ }
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds
b/arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds
new file mode 100644
index 000..86cbc6b
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, ga...@denx.de
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+OUTPUT_FORMAT(elf32-littlearm, elf32-littlearm, elf32-littlearm)
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x;
+
+ . = ALIGN(4);
+ .text :
+ {
+ __image_copy_start = .;
+ CPUDIR/start.o (.text*)
+ *(.text
[U-Boot] [PATCH v1 0/2] Add SD boot support for LS1021AQDS/TWR board
This series contain SD boot support for LS1021AQDS/TWR board.SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. The patches are based on the former LS1021AQDS/TWR board basic support patches. Alison Wang (2): arm: ls102xa: Add SD boot support for LS1021AQDS board arm: ls102xa: Add SD boot support for LS1021ATWR board Makefile | 15 - arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/spl.c | 35 + arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds | 83 + arch/arm/include/asm/arch-ls102xa/spl.h | 20 board/freescale/common/qixis.h| 7 + board/freescale/ls1021aqds/ddr.c | 5 ++- board/freescale/ls1021aqds/ls1021aqds.c | 31 ++ board/freescale/ls1021aqds/ls102xa_pbi.cfg| 8 + board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | 14 + board/freescale/ls1021atwr/ls1021atwr.c | 31 +- board/freescale/ls1021atwr/ls102xa_pbi.cfg| 8 + board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 + boards.cfg| 2 ++ common/spl/spl_mmc.c | 2 ++ include/configs/ls1021aqds.h | 64 ++ include/configs/ls1021atwr.h | 49 + tools/pblimage.c | 20 +--- 18 files changed, 402 insertions(+), 7 deletions(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/spl.c create mode 100644 arch/arm/cpu/armv7/ls102xa/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-ls102xa/spl.h create mode 100644 board/freescale/ls1021aqds/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] arm: ls102xa: Add SD boot support for LS1021ATWR board
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
---
board/freescale/ls1021atwr/ls1021atwr.c | 31 -
board/freescale/ls1021atwr/ls102xa_pbi.cfg| 8 +
board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14
boards.cfg| 1 +
include/configs/ls1021atwr.h | 49 +++
5 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg
create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 3de5b83..02d0d39 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -16,6 +16,7 @@
#include netdev.h
#include fsl_mdio.h
#include tsec.h
+#include spl.h
DECLARE_GLOBAL_DATA_PTR;
@@ -66,6 +67,7 @@ struct cpld_data {
u8 rev2;/* Reserved */
};
+#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_QSPI_BOOT)
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
@@ -103,11 +105,14 @@ void cpld_show(void)
in_8(cpld_data-serdes_mux));
#endif
}
+#endif
int checkboard(void)
{
puts(Board: LS1021ATWR\n);
+#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_QSPI_BOOT)
cpld_show();
+#endif
return 0;
}
@@ -218,6 +223,7 @@ int board_eth_init(bd_t *bis)
}
#endif
+#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_QSPI_BOOT)
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -249,6 +255,7 @@ int config_serdes_mux(void)
return 0;
}
+#endif
int board_early_init_f(void)
{
@@ -273,6 +280,25 @@ int board_early_init_f(void)
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+ preloader_console_init();
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -284,9 +310,10 @@ int board_init(void)
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
+#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_QSPI_BOOT)
config_serdes_mux();
#endif
-
+#endif
return 0;
}
@@ -312,6 +339,7 @@ u16 flash_read16(void *addr)
return (((val) 8) 0x00ff) | (((val) 8) 0xff00);
}
+#if !defined(CONFIG_SD_BOOT) !defined(CONFIG_QSPI_BOOT)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -497,3 +525,4 @@ U_BOOT_CMD(
-change lane C lane D to PCIeX2\n
\nWARNING: If you aren't familiar with the setting of serdes, don't
try to change anything!\n
);
+#endif
diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg
b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
new file mode 100644
index 000..edf9f94
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg
@@ -0,0 +1,8 @@
+#PBI commands
+
+#Configure Scratch register
+09ee0200 1000
+#Configure alternate space
+09570158 0008
+#Flush PBL data
+096100c0 000F
diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
new file mode 100644
index 000..05e2082
--- /dev/null
+++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+#0608000a
+#2000 00404000 60025a00 21042000
+#0020 01038000
+# 001b1200
+
+#disable IFC, enable QSPI and DSPI
+0608000a
+2000 00404000 60025a00 21042000
+ 01038000
+20024800 001b1200
diff --git a/boards.cfg b/boards.cfg
index 3e5e1d0..65c3066 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -304,6 +304,7 @@ Active arm armv7 keystoneti
k2hk_evm
Active arm armv7 ls102xa freescale ls1021aqds
ls1021aqds_norls1021aqds
Alison Wang alison.w...@freescale.com
Active arm armv7 ls102xa freescale ls1021aqds
ls1021aqds_sdcard
ls1021aqds:RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT
[U-Boot] [PATCH v3 0/18] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board. The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. For the detail information about LS1021AQDS/TWR board, please refer to README in the patch. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 01/18] arm: ls102xa: Add Freescale LS102xA SoC support
From: Wang Huan b18...@freescale.com
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Change log:
v3: Fix checkpatch errors.
v2: Add serdes support.
Update DDR frequency and data rate information.
Fix overflow condition error for the timer.
arch/arm/cpu/armv7/ls102xa/Makefile | 12 +
arch/arm/cpu/armv7/ls102xa/clock.c| 130 ++
arch/arm/cpu/armv7/ls102xa/cpu.c | 103 +
arch/arm/cpu/armv7/ls102xa/fdt.c | 128 ++
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 119 ++
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | 12 +
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c | 41 ++
arch/arm/cpu/armv7/ls102xa/timer.c| 127 ++
arch/arm/include/asm/arch-ls102xa/clock.h | 23 ++
arch/arm/include/asm/arch-ls102xa/config.h| 71
arch/arm/include/asm/arch-ls102xa/fsl_serdes.h| 33 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 461 ++
arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 +++
arch/arm/include/asm/config.h | 4 +
arch/arm/include/asm/io.h | 8 +-
drivers/watchdog/Makefile | 2 +-
16 files changed, 1325 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile
create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c
create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
new file mode 100644
index 000..d82ce8d
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clock.o
+obj-y += timer.o
+
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c
b/arch/arm/cpu/armv7/ls102xa/clock.c
new file mode 100644
index 000..8f80c61
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/immap_ls102xa.h
+#include asm/arch/clock.h
+#include fsl_ifc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[6] = {
+ [0] = 0,/* CC1 PPL / 1 */
+ [1] = 0,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 1,/* CC2 PPL / 2 */
+ };
+
+ const u8 core_cplx_pll_div[6] = {
+ [0] = 1,/* CC1 PPL / 1 */
+ [1] = 2,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 2,/* CC2 PPL / 2 */
+ };
+
+ uint i;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sys_info-freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info-freq_ddrbus = sysclk;
+#endif
+
+ sys_info
[U-Boot] [PATCH v3 03/18] net: Merge asm/fsl_enet.h into fsl_mdio.h
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com
---
Change log:
v3: No change.
v2: No change.
arch/powerpc/include/asm/fsl_enet.h | 24
board/freescale/mpc8360emds/mpc8360emds.c | 2 +-
board/freescale/mpc837xemds/mpc837xemds.c | 1 -
drivers/net/fm/dtsec.c| 1 -
drivers/net/fm/fm.h | 2 +-
drivers/net/fm/init.c | 1 +
drivers/net/fm/memac.c| 1 -
drivers/net/fm/tgec.c | 1 -
drivers/net/fsl_mdio.c| 1 -
drivers/qe/uec.h | 1 -
include/fm_eth.h | 2 +-
include/fsl_mdio.h| 13 -
include/tsec.h| 2 +-
13 files changed, 17 insertions(+), 35 deletions(-)
delete mode 100644 arch/powerpc/include/asm/fsl_enet.h
diff --git a/arch/powerpc/include/asm/fsl_enet.h
b/arch/powerpc/include/asm/fsl_enet.h
deleted file mode 100644
index 96146b6..000
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include phy.h
-
-struct tsec_mii_mng {
- u32 miimcfg;/* MII management configuration reg */
- u32 miimcom;/* MII management command reg */
- u32 miimadd;/* MII management address reg */
- u32 miimcon;/* MII management control reg */
- u32 miimstat; /* MII management status reg */
- u32 miimind;/* MII management indication reg */
- u32 ifstat; /* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index ac96163..5ff9dff 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -11,13 +11,13 @@
#include i2c.h
#include miiphy.h
#include phy.h
+#include fsl_mdio.h
#if defined(CONFIG_PCI)
#include pci.h
#endif
#include spd_sdram.h
#include asm/mmu.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/mmu.h
#if defined(CONFIG_OF_LIBFDT)
#include libfdt.h
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c
b/board/freescale/mpc837xemds/mpc837xemds.c
index 0a3c972..c749e55 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -10,7 +10,6 @@
#include i2c.h
#include asm/io.h
#include asm/fsl_mpc83xx_serdes.h
-#include asm/fsl_enet.h
#include spd_sdram.h
#include tsec.h
#include libfdt.h
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 78bbd43..8d3dc0e 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,6 @@
#include common.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_dtsec.h
#include fsl_mdio.h
#include phy.h
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 316e06e..a9691c6 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -8,8 +8,8 @@
#define __FM_H__
#include common.h
+#include phy.h
#include fm_eth.h
-#include asm/fsl_enet.h
#include asm/fsl_fman.h
/* Port ID */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index ff04695..6cf21c6 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
#include common.h
#include asm/io.h
#include asm/fsl_serdes.h
+#include fsl_mdio.h
#include fm.h
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f..9499290 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_memac.h
#include fm.h
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index f450f80..5017123 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_tgec.h
#include fm.h
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 1d88e65..8d09f5d 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -11,7 +11,6
[U-Boot] [PATCH v3 05/18] net: mdio: Use mb() to be compatible for both ARM and PowerPC
Use mb() instead of sync assembly instruction to be compatible for both ARM and PowerPC. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v3: Use mb() to be compatible for both ARM and PowerPC. Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch. v2: Add private mdio read and write support. drivers/net/fsl_mdio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index 6eae78f..2657c44 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -19,7 +19,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, out_be32(phyregs-miimadd, (port_addr 8) | (regnum 0x1f)); out_be32(phyregs-miimcon, value); - asm(sync); + mb(); while ((in_be32(phyregs-miimind) MIIMIND_BUSY) timeout--) ; @@ -37,11 +37,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, /* Clear the command register, and wait */ out_be32(phyregs-miimcom, 0); - asm(sync); + mb(); /* Initiate a read command, and wait */ out_be32(phyregs-miimcom, MIIMCOM_READ_CYCLE); - asm(sync); + mb(); /* Wait for the the indication that the read is done */ while ((in_be32(phyregs-miimind) (MIIMIND_NOTVALID | MIIMIND_BUSY)) -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 09/18] driver/ddr/freescale: Fix DDR3 driver for ARM
From: York Sun york...@freescale.com Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun york...@freescale.com --- Change log: v3: No change. v2: No change. drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index d4ed9ae..59f2fd6 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -194,7 +194,7 @@ step2: * For example, 2GB on 666MT/s 64-bit bus takes about 402ms * Let's wait for 800ms */ - bus_width = 3 - ((ddr-sdram_cfg SDRAM_CFG_DBW_MASK) + bus_width = 3 - ((ddr_in32(ddr-sdram_cfg) SDRAM_CFG_DBW_MASK) SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller (6 - bus_width)) * 100 / (get_ddr_freq(0) 20)) 1; -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 07/18] ls102xa: esdhc: Add esdhc support for LS102xA
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: No change.
v2: No change.
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613..aec459f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct
mmc_data *data)
else if (cmd-resp_type MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) ||
defined(CONFIG_LS102xA)
if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg
*cfg)
memset(cfg-cfg, 0, sizeof(cfg-cfg));
voltage_caps = 0;
- caps = regs-hostcapblt;
+ caps = esdhc_read32(regs-hostcapblt);
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps ~(ESDHC_HOSTCAPBLT_SRS |
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 9814964..c1b6648 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
};
/* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32clrbits_le32
+#define esdhc_setbits32setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
--
1.8.4
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[U-Boot] [PATCH v3 02/18] ls102xa: i2c: Add i2c support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Add I2C 3 support.
v2: No change.
drivers/i2c/mxc_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c14797c..83a9ffa 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
- defined(CONFIG_MX6)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR
@@ -545,7 +545,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
CONFIG_SYS_MXC_I2C2_SLAVE, 1)
#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
- defined(CONFIG_MX6)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
--
1.8.4
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[U-Boot] [PATCH v3 04/18] net: mdio: Add private MDIO read/write function
As extra FPGA settings is needed for MDIO read/write
on LS1021AQDS, private MDIO read/write functions are
created.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 9 +++--
include/fsl_mdio.h | 4
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 8d09f5d..6eae78f 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -98,8 +98,13 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info
*info)
return -1;
}
- bus-read = tsec_phy_read;
- bus-write = tsec_phy_write;
+ if (info-priv_mdio_read) {
+ bus-read = info-priv_mdio_read;
+ bus-write = info-priv_mdio_write;
+ } else {
+ bus-read = tsec_phy_read;
+ bus-write = tsec_phy_write;
+ }
bus-reset = fsl_pq_mdio_reset;
sprintf(bus-name, info-name);
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index a531edf..633123c 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -57,6 +57,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int
dev_addr,
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
+ int (*priv_mdio_read)(struct mii_dev *bus, int addr,
+ int devad, int reg);
+ int (*priv_mdio_write)(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 val);
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
--
1.8.4
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[U-Boot] [PATCH v3 10/18] driver/ddr/fsl: Add support of overriding chip select write leveling
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v3: No change.
v2: No change.
drivers/ddr/fsl/ctrl_regs.c | 3 +++
drivers/ddr/fsl/interactive.c | 2 ++
include/fsl_ddr_sdram.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 5e0ee77..d9cac22 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
if (ip_rev 0x40400)
unq_mrs_en = 1;
+ if (ip_rev 0x40700)
+ ddr-debug[18] = popts-cswl_override;
+
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 7fb4187..6aa16b2 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t
*popts)
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e8a2db9..987119b 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0 0x0401
/*
* Generalized parameters for memory controller configuration,
* might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+ unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
--
1.8.4
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[U-Boot] [PATCH v3 06/18] ls102xa: etsec: Add etsec support for LS102xA
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: No change.
v2: Add private mdio read and write support.
drivers/net/tsec.c | 7 +++
include/tsec.h | 7 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..a220221 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
#include fsl_mdio.h
#include asm/errno.h
#include asm/processor.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
do {
uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
}
/* This returns the status bits of the device. The return value
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..5b74f67 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
#include net.h
#include config.h
#include phy.h
-#include fsl_mdio.h
+#ifdef CONFIG_LS102xA
+#define TSEC_SIZE 0x4
+#define TSEC_MDIO_OFFSET 0x4
+#else
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
@@ -128,6 +132,7 @@
#define DMACTRL_INIT_SETTINGS 0x00c3
#define DMACTRL_GRS0x0010
#define DMACTRL_GTS0x0008
+#define DMACTRL_LE 0x8000
#define TSTAT_CLEAR_THALT 0x8000
#define RSTAT_CLEAR_RHALT 0x0080
--
1.8.4
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[U-Boot] [PATCH v3 13/18] net: tsec: Remove tx snooping support from LS1
From: Claudiu Manoil claudiu.man...@freescale.com Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a workaround for LS1. It has been observed that currently the Tx stops functioning after a fair amount of Tx traffic with these settings on. These bits are sticky and once set they cannot be reset from Linux, for instance. Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com --- Change log: v3: New file. include/tsec.h | 4 1 file changed, 4 insertions(+) diff --git a/include/tsec.h b/include/tsec.h index 5b74f67..1f0c233 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -129,7 +129,11 @@ #define MINFLR_INIT_SETTINGS 0x0040 +#ifdef CONFIG_LS102xA +#define DMACTRL_INIT_SETTINGS 0x0003 +#else #define DMACTRL_INIT_SETTINGS 0x00c3 +#endif #define DMACTRL_GRS0x0010 #define DMACTRL_GTS0x0008 #define DMACTRL_LE 0x8000 -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 08/18] driver/ddr/freescale: Add support of accumulate ECC
From: York Sun york...@freescale.com If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun york...@freescale.com --- Change log: v3: No change. v2: No change. drivers/ddr/fsl/ctrl_regs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 04e4178..5e0ee77 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int x32_en = 0;/* x32 enable */ unsigned int pchb8 = 0; /* precharge bit 8 enable */ unsigned int hse; /* Global half strength override */ + unsigned int acc_ecc_en = 0;/* Accumulated ECC enable */ unsigned int mem_halt = 0; /* memory controller halt */ unsigned int bi = 0;/* Bypass initialization */ @@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ba_intlv_ctl = popts-ba_intlv_ctl; hse = popts-half_strength_driver_enable; + /* set when ddr bus width 64 */ + acc_ecc_en = (dbw != 0 ecc_en == 1) ? 1 : 0; + ddr-ddr_sdram_cfg = (0 | ((mem_en 0x1) 31) | ((sren 0x1) 30) @@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((x32_en 0x1) 5) | ((pchb8 0x1) 4) | ((hse 0x1) 3) + | ((acc_ecc_en 0x1) 2) | ((mem_halt 0x1) 1) | ((bi 0x1) 0) ); -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 11/18] arm: ls102xa: Add basic support for LS1021AQDS board
From: Wang Huan b18...@freescale.com This patch is to add basic support for LS1021AQDS board. For the detail board information, please refer to README. Signed-off-by: Alison Wang alison.w...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: York Sun york...@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Change log: v3: Fix checkpatch error. Update to Kconfig. v2: Remove ethaddr/ipaddr setting. Add board maintainer. Add serdes and multiple ethernet controllers support. arch/arm/Kconfig | 4 + board/freescale/ls1021aqds/Kconfig| 23 ++ board/freescale/ls1021aqds/MAINTAINERS| 6 + board/freescale/ls1021aqds/Makefile | 9 + board/freescale/ls1021aqds/README | 112 +++ board/freescale/ls1021aqds/ddr.c | 166 ++ board/freescale/ls1021aqds/ddr.h | 64 board/freescale/ls1021aqds/eth.c | 129 board/freescale/ls1021aqds/ls1021aqds.c | 248 +++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ configs/ls1021aqds_nor_defconfig | 2 + include/configs/ls1021aqds.h | 424 ++ 12 files changed, 1222 insertions(+) create mode 100644 board/freescale/ls1021aqds/Kconfig create mode 100644 board/freescale/ls1021aqds/MAINTAINERS create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/eth.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 configs/ls1021aqds_nor_defconfig create mode 100644 include/configs/ls1021aqds.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e385eda..62b3cc8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -731,6 +731,9 @@ config TARGET_LS2085A_EMU config TARGET_LS2085A_SIMU bool Support ls2085a_simu +config TARGET_LS1021AQDS + bool Support ls1021aqds_nor + config TARGET_BALLOON3 bool Support balloon3 @@ -865,6 +868,7 @@ source board/eukrea/cpu9260/Kconfig source board/eukrea/cpuat91/Kconfig source board/faraday/a320evb/Kconfig source board/freescale/ls2085a/Kconfig +source board/freescale/ls1021aqds/Kconfig source board/freescale/mx23evk/Kconfig source board/freescale/mx25pdk/Kconfig source board/freescale/mx28evk/Kconfig diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig new file mode 100644 index 000..c28bd2b --- /dev/null +++ b/board/freescale/ls1021aqds/Kconfig @@ -0,0 +1,23 @@ +if TARGET_LS1021AQDS + +config SYS_CPU + string + default armv7 + +config SYS_BOARD + string + default ls1021aqds + +config SYS_VENDOR + string + default freescale + +config SYS_SOC + string + default ls102xa + +config SYS_CONFIG_NAME + string + default ls1021aqds + +endif diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS new file mode 100644 index 000..021d82b --- /dev/null +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -0,0 +1,6 @@ +LS1021AQDS BOARD +M: Alison Wang alison.w...@freescale.com +S: Maintained +F: board/freescale/ls1021aqds/ +F: include/configs/ls1021aqds.h +F: configs/ls1021aqds_nor_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile new file mode 100644 index 000..3b6903c --- /dev/null +++ b/board/freescale/ls1021aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README new file mode 100644 index 000..c561776 --- /dev/null +++ b/board/freescale/ls1021aqds/README @@ -0,0 +1,112 @@ +Overview + +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects
[U-Boot] [PATCH v3 12/18] arm: ls102xa: Add basic support for LS1021ATWR board
From: Wang Huan b18...@freescale.com This patch is to add basic support for LS1021ATWR board. For the detail board information, please refer to README. Signed-off-by: Chen Lu chen...@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v3: Fix checkpatch error. Update to Kconfig. v2: New file. arch/arm/Kconfig| 4 + board/freescale/ls1021atwr/Kconfig | 23 ++ board/freescale/ls1021atwr/MAINTAINERS | 6 + board/freescale/ls1021atwr/Makefile | 7 + board/freescale/ls1021atwr/README | 109 +++ board/freescale/ls1021atwr/ls1021atwr.c | 494 configs/ls1021atwr_nor_defconfig| 2 + include/configs/ls1021atwr.h| 284 ++ 8 files changed, 929 insertions(+) create mode 100644 board/freescale/ls1021atwr/Kconfig create mode 100644 board/freescale/ls1021atwr/MAINTAINERS create mode 100644 board/freescale/ls1021atwr/Makefile create mode 100644 board/freescale/ls1021atwr/README create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c create mode 100644 configs/ls1021atwr_nor_defconfig create mode 100644 include/configs/ls1021atwr.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 62b3cc8..d207db7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -734,6 +734,9 @@ config TARGET_LS2085A_SIMU config TARGET_LS1021AQDS bool Support ls1021aqds_nor +config TARGET_LS1021ATWR + bool Support ls1021atwr_nor + config TARGET_BALLOON3 bool Support balloon3 @@ -869,6 +872,7 @@ source board/eukrea/cpuat91/Kconfig source board/faraday/a320evb/Kconfig source board/freescale/ls2085a/Kconfig source board/freescale/ls1021aqds/Kconfig +source board/freescale/ls1021atwr/Kconfig source board/freescale/mx23evk/Kconfig source board/freescale/mx25pdk/Kconfig source board/freescale/mx28evk/Kconfig diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig new file mode 100644 index 000..057808d --- /dev/null +++ b/board/freescale/ls1021atwr/Kconfig @@ -0,0 +1,23 @@ +if TARGET_LS1021ATWR + +config SYS_CPU + string + default armv7 + +config SYS_BOARD + string + default ls1021atwr + +config SYS_VENDOR + string + default freescale + +config SYS_SOC + string + default ls102xa + +config SYS_CONFIG_NAME + string + default ls1021atwr + +endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS new file mode 100644 index 000..4e5bc15 --- /dev/null +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -0,0 +1,6 @@ +LS1021ATWR BOARD +M: Alison Wang alison.w...@freescale.com +S: Maintained +F: board/freescale/ls1021atwr/ +F: include/configs/ls1021atwr.h +F: configs/ls1021atwr_nor_defconfig diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile new file mode 100644 index 000..b5df668 --- /dev/null +++ b/board/freescale/ls1021atwr/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README new file mode 100644 index 000..d2821cb --- /dev/null +++ b/board/freescale/ls1021atwr/README @@ -0,0 +1,109 @@ +Overview + +The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache
[U-Boot] [PATCH v3 14/18] serial: lpuart: add 32-bit registers lpuart support
From: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
---
Change log:
v3: New file.
drivers/serial/serial_lpuart.c | 122 +
1 file changed, 122 insertions(+)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index da5f9a2..6e639b7 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -17,10 +17,34 @@
#define UC2_TE (1 3)
#define UC2_RE (1 2)
+#define STAT_LBKDIF(1 31)
+#define STAT_RXEDGIF (1 30)
+#define STAT_TDRE (1 23)
+#define STAT_RDRF (1 21)
+#define STAT_IDLE (1 20)
+#define STAT_OR(1 19)
+#define STAT_NF(1 18)
+#define STAT_FE(1 17)
+#define STAT_PF(1 16)
+#define STAT_MA1F (1 15)
+#define STAT_MA2F (1 14)
+#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
+ STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
+
+#define CTRL_TE(1 19)
+#define CTRL_RE(1 18)
+
+#define FIFO_TXFE 0x80
+#define FIFO_RXFE 0x40
+
+#define WATER_TXWATER_OFF 1
+#define WATER_RXWATER_OFF 16
+
DECLARE_GLOBAL_DATA_PTR;
struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
+#ifndef CONFIG_LPUART_32B_REG
static void lpuart_serial_setbrg(void)
{
u32 clk = mxc_get_clock(MXC_UART_CLK);
@@ -107,13 +131,111 @@ static struct serial_device lpuart_serial_drv = {
.getc = lpuart_serial_getc,
.tstc = lpuart_serial_tstc,
};
+#else
+static void lpuart32_serial_setbrg(void)
+{
+ u32 clk = CONFIG_SYS_CLK_FREQ;
+ u32 sbr;
+
+ if (!gd-baudrate)
+ gd-baudrate = CONFIG_BAUDRATE;
+
+ sbr = (clk / (16 * gd-baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ out_be32(base-baud, sbr);
+}
+
+static int lpuart32_serial_getc(void)
+{
+ u32 stat;
+
+ while (((stat = in_be32(base-stat)) STAT_RDRF) == 0) {
+ out_be32(base-stat, STAT_FLAGS);
+ WATCHDOG_RESET();
+ }
+
+ return in_be32(base-data) 0x3ff;
+}
+
+static void lpuart32_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(in_be32(base-stat) STAT_TDRE))
+ WATCHDOG_RESET();
+
+ out_be32(base-data, c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart32_serial_tstc(void)
+{
+ if ((in_be32(base-water) 24) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart32_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = in_be32(base-ctrl);
+ ctrl = ~CTRL_RE;
+ ctrl = ~CTRL_TE;
+ out_be32(base-ctrl, ctrl);
+
+ out_be32(base-modir, 0);
+ out_be32(base-fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+ out_be32(base-match, 0);
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ out_be32(base-ctrl, CTRL_RE | CTRL_TE);
+
+ return 0;
+}
+
+static struct serial_device lpuart32_serial_drv = {
+ .name = lpuart32_serial,
+ .start = lpuart32_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart32_serial_setbrg,
+ .putc = lpuart32_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart32_serial_getc,
+ .tstc = lpuart32_serial_tstc,
+};
+#endif
+void lpuart32_serial_initialize(void)
+{
+ serial_register(lpuart32_serial_drv);
+}
void lpuart_serial_initialize(void)
{
+#ifdef CONFIG_LPUART_32B_REG
+ serial_register(lpuart32_serial_drv);
+#else
serial_register(lpuart_serial_drv);
+#endif
}
__weak struct serial_device *default_serial_console(void)
{
+#ifdef CONFIG_LPUART_32B_REG
+ return lpuart32_serial_drv;
+#else
return lpuart_serial_drv;
+#endif
}
--
1.8.4
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[U-Boot] [PATCH v3 16/18] video: dcu: Add Sii9022A HDMI Transmitter support
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/common/dcu_sii9022a.c | 153 ++
board/freescale/common/dcu_sii9022a.h | 13 +++
3 files changed, 168 insertions(+)
create mode 100644 board/freescale/common/dcu_sii9022a.c
create mode 100644 board/freescale/common/dcu_sii9022a.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 22b57cc..808ddd0 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL
obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
endif
+obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
+
obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
diff --git a/board/freescale/common/dcu_sii9022a.c
b/board/freescale/common/dcu_sii9022a.c
new file mode 100644
index 000..2da627e
--- /dev/null
+++ b/board/freescale/common/dcu_sii9022a.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include common.h
+#include fsl_dcu_fb.h
+#include i2c.h
+#include linux/fb.h
+
+#define PIXEL_CLK_LSB_REG 0x00
+#define PIXEL_CLK_MSB_REG 0x01
+#define VERT_FREQ_LSB_REG 0x02
+#define VERT_FREQ_MSB_REG 0x03
+#define TOTAL_PIXELS_LSB_REG 0x04
+#define TOTAL_PIXELS_MSB_REG 0x05
+#define TOTAL_LINES_LSB_REG0x06
+#define TOTAL_LINES_MSB_REG0x07
+#define TPI_INBUS_FMT_REG 0x08
+#define TPI_INPUT_FMT_REG 0x09
+#define TPI_OUTPUT_FMT_REG 0x0A
+#define TPI_SYS_CTRL_REG 0x1A
+#define TPI_PWR_STAT_REG 0x1E
+#define TPI_AUDIO_HANDING_REG 0x25
+#define TPI_AUDIO_INTF_REG 0x26
+#define TPI_AUDIO_FREQ_REG 0x27
+#define TPI_SET_PAGE_REG 0xBC
+#define TPI_SET_OFFSET_REG 0xBD
+#define TPI_RW_ACCESS_REG 0xBE
+#define TPI_TRANS_MODE_REG 0xC7
+
+#define TPI_INBUS_CLOCK_RATIO_1(1 6)
+#define TPI_INBUS_FULL_PIXEL_WIDE (1 5)
+#define TPI_INBUS_RISING_EDGE (1 4)
+#define TPI_INPUT_CLR_DEPTH_8BIT (0 6)
+#define TPI_INPUT_VRANGE_EXPAN_AUTO(0 2)
+#define TPI_INPUT_CLR_RGB (0 0)
+#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 6)
+#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 2)
+#define TPI_OUTPUT_CLR_HDMI_RGB(0 0)
+#define TPI_SYS_TMDS_OUTPUT(0 4)
+#define TPI_SYS_AV_NORAML (0 3)
+#define TPI_SYS_AV_MUTE(1 3)
+#define TPI_SYS_DVI_MODE (0 0)
+#define TPI_SYS_HDMI_MODE (1 0)
+#define TPI_PWR_STAT_MASK (3 0)
+#define TPI_PWR_STAT_D0(0 0)
+#define TPI_AUDIO_PASS_BASIC (0 0)
+#define TPI_AUDIO_INTF_I2S (2 6)
+#define TPI_AUDIO_INTF_NORMAL (0 4)
+#define TPI_AUDIO_TYPE_PCM (1 0)
+#define TPI_AUDIO_SAMP_SIZE_16BIT (1 6)
+#define TPI_AUDIO_SAMP_FREQ_44K(2 3)
+#define TPI_SET_PAGE_SII9022A 0x01
+#define TPI_SET_OFFSET_SII9022A0x82
+#define TPI_RW_EN_SRC_TERMIN (1 0)
+#define TPI_TRANS_MODE_ENABLE (0 7)
+
+/* Programming of Silicon SIi9022a HDMI Transmitter */
+int dcu_set_dvi_encoder(struct fb_videomode *videomode)
+{
+ u8 temp;
+ u16 temp1, temp2;
+ u32 temp3;
+
+ i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+
+ /* Enable TPI transmitter mode */
+ temp = TPI_TRANS_MODE_ENABLE;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, temp, 1);
+
+ /* Enter into D0 state, full operation */
+ i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, temp, 1);
+ temp = ~TPI_PWR_STAT_MASK;
+ temp |= TPI_PWR_STAT_D0;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, temp, 1);
+
+ /* Enable source termination */
+ temp = TPI_SET_PAGE_SII9022A;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, temp, 1);
+ temp = TPI_SET_OFFSET_SII9022A;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, temp, 1);
+
+ i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, temp, 1);
+ temp |= TPI_RW_EN_SRC_TERMIN;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, temp, 1);
+
+ /* Set TPI system control */
+ temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, temp, 1);
+
+ /* Set pixel clock */
+ temp1 = PICOS2KHZ(videomode-pixclock) / 10;
+ temp = (u8)(temp1 0xFF);
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, temp, 1
[U-Boot] [PATCH v3 17/18] video: dcu: Add DCU driver support
From: Wang Huan b18...@freescale.com This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v3: New file. arch/arm/include/asm/arch-ls102xa/config.h | 4 + drivers/video/Makefile | 1 + drivers/video/fsl_dcu_fb.c | 365 + include/fsl_dcu_fb.h | 16 ++ 4 files changed, 386 insertions(+) create mode 100644 drivers/video/fsl_dcu_fb.c create mode 100644 include/fsl_dcu_fb.h diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ddc747f..dfc5668 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_FSL_LS1_CLK_ADDR(CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_DCU_ADDR(CONFIG_SYS_IMMR + 0x01ce) #define CONFIG_SYS_TSEC1_OFFSET0x01d1 #define CONFIG_SYS_TSEC2_OFFSET0x01d5 @@ -57,6 +58,9 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_DCU_BE + +#define DCU_LAYER_MAX_NUM 16 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 945f35d..3dafef3 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_L5F31188) += l5f31188.o obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c new file mode 100644 index 000..36c1566 --- /dev/null +++ b/drivers/video/fsl_dcu_fb.c @@ -0,0 +1,365 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include asm/io.h +#include common.h +#include fsl_dcu_fb.h +#include linux/fb.h +#include malloc.h +#include video_fb.h +#include videomodes.h + +/* Convert the X,Y resolution pair into a single number */ +#define RESOLUTION(x, y) (((u32)(x) 16) | (y)) + +#ifdef CONFIG_SYS_FSL_DCU_LE +#definedcu_read32 in_le32 +#definedcu_write32 out_le32 +#elif defined(CONFIG_SYS_FSL_DCU_BE) +#definedcu_read32 in_be32 +#definedcu_write32 out_be32 +#endif + +#define DCU_MODE_BLEND_ITER(x) ((x) 20) +#define DCU_MODE_RASTER_EN (1 14) +#define DCU_MODE_NORMAL1 +#define DCU_MODE_COLORBAR 3 +#define DCU_BGND_R(x) ((x) 16) +#define DCU_BGND_G(x) ((x) 8) +#define DCU_BGND_B(x) (x) +#define DCU_DISP_SIZE_DELTA_Y(x) ((x) 16) +#define DCU_DISP_SIZE_DELTA_X(x) (x) +#define DCU_HSYN_PARA_BP(x)((x) 22) +#define DCU_HSYN_PARA_PW(x)((x) 11) +#define DCU_HSYN_PARA_FP(x)(x) +#define DCU_VSYN_PARA_BP(x)((x) 22) +#define DCU_VSYN_PARA_PW(x)((x) 11) +#define DCU_VSYN_PARA_FP(x)(x) +#define DCU_SYN_POL_INV_PXCK_FALL (0 6) +#define DCU_SYN_POL_NEG_REMAIN (0 5) +#define DCU_SYN_POL_INV_VS_LOW (1 1) +#define DCU_SYN_POL_INV_HS_LOW (1) +#define DCU_THRESHOLD_LS_BF_VS(x) ((x) 16) +#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) 8) +#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) +#define DCU_UPDATE_MODE_MODE(1 31) +#define DCU_UPDATE_MODE_READREG (1 30) + +#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) 16) +#define DCU_CTRLDESCLN_1_WIDTH(x) (x) +#define DCU_CTRLDESCLN_2_POSY(x) ((x) 16) +#define DCU_CTRLDESCLN_2_POSX(x) (x) +#define DCU_CTRLDESCLN_4_EN(1 31) +#define DCU_CTRLDESCLN_4_TILE_EN (1 30) +#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 29) +#define DCU_CTRLDESCLN_4_SAFETY_EN (1 28) +#define DCU_CTRLDESCLN_4_TRANS(x) ((x) 20) +#define DCU_CTRLDESCLN_4_BPP(x)((x) 16) +#define DCU_CTRLDESCLN_4_RLE_EN(1 15) +#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) 4) +#define DCU_CTRLDESCLN_4_BB_ON (1 2) +#define DCU_CTRLDESCLN_4_AB(x) (x) +#define DCU_CTRLDESCLN_5_CKMAX_R(x)((x) 16) +#define DCU_CTRLDESCLN_5_CKMAX_G(x)((x) 8
[U-Boot] [PATCH v3 15/18] arm: ls102xa: Add LETECH support for LS1021AQDS/TWR board
From: Wang Huan b18...@freescale.com This patch is to add LETECH support for LS1021AQDS/TWR board. For LETECH, LPUART is used for serial port. Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v3: New file. board/freescale/ls1021aqds/MAINTAINERS | 1 + board/freescale/ls1021atwr/MAINTAINERS | 1 + configs/ls1021aqds_letech_defconfig| 3 +++ configs/ls1021atwr_letech_defconfig| 3 +++ include/configs/ls1021aqds.h | 13 + include/configs/ls1021atwr.h | 12 6 files changed, 33 insertions(+) create mode 100644 configs/ls1021aqds_letech_defconfig create mode 100644 configs/ls1021atwr_letech_defconfig diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 021d82b..590b89b 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/ls1021aqds/ F: include/configs/ls1021aqds.h F: configs/ls1021aqds_nor_defconfig +F: configs/ls1021aqds_letech_defconfig diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 4e5bc15..14a7441 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/ls1021atwr/ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig +F: configs/ls1021atwr_letech_defconfig diff --git a/configs/ls1021aqds_letech_defconfig b/configs/ls1021aqds_letech_defconfig new file mode 100644 index 000..b70971e --- /dev/null +++ b/configs/ls1021aqds_letech_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS=LETECH ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021atwr_letech_defconfig b/configs/ls1021atwr_letech_defconfig new file mode 100644 index 000..4b187b3 --- /dev/null +++ b/configs/ls1021atwr_letech_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS=LETECH ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 856fdfc..5a8bf21 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -279,11 +279,16 @@ unsigned long get_board_ddr_clk(void); /* * Serial Port */ +#ifdef CONFIG_LETECH +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE115200 @@ -367,11 +372,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 +#ifdef CONFIG_LETECH +#define CONFIG_EXTRA_ENV_SETTINGS \ + bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0 \ + fdt_high=0xcfff\0 \ + initrd_high=0xcfff\0 \ + hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0 +#else #define CONFIG_EXTRA_ENV_SETTINGS \ bootargs=root=/dev/ram0 rw console=ttyS0,115200\0 \ fdt_high=0xcfff\0 \ initrd_high=0xcfff\0 \ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0 +#endif /* * Miscellaneous configurable options diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f8cbe32..b268a70 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -147,11 +147,16 @@ unsigned long get_board_ddr_clk(void); /* * Serial Port */ +#ifdef CONFIG_LETECH +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE115200 @@ -228,10 +233,17 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 +#ifdef CONFIG_LETECH +#define CONFIG_EXTRA_ENV_SETTINGS \ + bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0 \ + initrd_high=0xcfff\0 \ + fdt_high=0xcfff\0 +#else #define CONFIG_EXTRA_ENV_SETTINGS \ bootargs=root=/dev/ram0 rw console=ttyS0,115200\0 \ initrd_high=0xcfff\0 \ fdt_high=0xcfff\0 +#endif /* * Miscellaneous configurable options -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 18/18] ls102xa: dcu: Add platform support for DCU on LS1021ATWR board
From: Wang Huan b18...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v3: New file.
board/freescale/ls1021atwr/Makefile | 1 +
board/freescale/ls1021atwr/dcu.c| 47 +
board/freescale/ls1021atwr/ls1021atwr.c | 6 +
include/configs/ls1021atwr.h| 18 +
4 files changed, 72 insertions(+)
create mode 100644 board/freescale/ls1021atwr/dcu.c
diff --git a/board/freescale/ls1021atwr/Makefile
b/board/freescale/ls1021atwr/Makefile
index b5df668..01296c0 100644
--- a/board/freescale/ls1021atwr/Makefile
+++ b/board/freescale/ls1021atwr/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1021atwr.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c
new file mode 100644
index 000..8fe4ccb
--- /dev/null
+++ b/board/freescale/ls1021atwr/dcu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include fsl_dcu_fb.h
+#include div64.h
+#include ../common/dcu_sii9022a.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long long div;
+
+ div = (unsigned long long)(gd-bus_clk / 1000);
+ div *= (unsigned long long)pixclock;
+ do_div(div, 10);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ const char *name;
+ unsigned int pixel_format;
+
+ if (strncmp(port, twr_lcd, 4) == 0) {
+ name = TWR_LCD_RGB card;
+ } else {
+ name = HDMI;
+ dcu_set_dvi_encoder(dcu_fb_videomode);
+ }
+
+ printf(DCU: Switching to %s monitor @ %ux%u\n, name, xres, yres);
+
+ pixel_format = 32;
+ fsl_dcu_init(xres, yres, pixel_format);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 7fdcbcd..e4364dd 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -264,6 +264,12 @@ int board_early_init_f(void)
init_early_memctl_regs();
#endif
+#ifdef CONFIG_FSL_DCU_FB
+ out_be32(scfg-scfgrevcr, 0x);
+ out_be32(scfg-pixclkcr, 0x8000);
+ out_be32(scfg-scfgrevcr, 0x);
+#endif
+
out_le32(cci-ctrl_ord, 0x0008);
return 0;
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index b268a70..fb2cf08 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -182,6 +182,24 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_GENERIC_MMC
/*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DCU_SII9022A
+#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
+#define CONFIG_SYS_I2C_DVI_ADDR0x39
+#endif
+
+/*
* eTSEC
*/
#define CONFIG_TSEC_ENET
--
1.8.4
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[U-Boot] [PATCH v4 02/18] ls102xa: i2c: Add i2c support for LS102xA
This patch is to add I2C 1,2,3 support for LS102xA.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Add commit messages.
v3: Add I2C 3 support.
v2: No change.
drivers/i2c/mxc_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index c14797c..83a9ffa 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
- defined(CONFIG_MX6)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR
@@ -545,7 +545,7 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
CONFIG_SYS_MXC_I2C2_SLAVE, 1)
#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
- defined(CONFIG_MX6)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
mxc_i2c_read, mxc_i2c_write,
mxc_i2c_set_bus_speed,
--
1.8.4
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[U-Boot] [PATCH v4 03/18] net: Merge asm/fsl_enet.h into fsl_mdio.h
From: Claudiu Manoil claudiu.man...@freescale.com
fsl_enet.h defines the mapping of the usual MII management
registers, which are included in the MDIO register block
common to Freescale ethernet controllers. So it shouldn't
depend on the CPU architecture but it should be actually
part of the arch independent fsl_mdio.h.
To remove the arch dependency, merge the content of
asm/fsl_enet.h into fsl_mdio.h.
Some files (like fm_eth.h) were simply including fsl_enet.h
only for phy.h. These were updated to include phy.h instead.
Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com
---
Change log:
v4: No change.
v3: No change.
v2: No change.
arch/powerpc/include/asm/fsl_enet.h | 24
board/freescale/mpc8360emds/mpc8360emds.c | 2 +-
board/freescale/mpc837xemds/mpc837xemds.c | 1 -
drivers/net/fm/dtsec.c| 1 -
drivers/net/fm/fm.h | 2 +-
drivers/net/fm/init.c | 1 +
drivers/net/fm/memac.c| 1 -
drivers/net/fm/tgec.c | 1 -
drivers/net/fsl_mdio.c| 1 -
drivers/qe/uec.h | 1 -
include/fm_eth.h | 2 +-
include/fsl_mdio.h| 13 -
include/tsec.h| 2 +-
13 files changed, 17 insertions(+), 35 deletions(-)
delete mode 100644 arch/powerpc/include/asm/fsl_enet.h
diff --git a/arch/powerpc/include/asm/fsl_enet.h
b/arch/powerpc/include/asm/fsl_enet.h
deleted file mode 100644
index 96146b6..000
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef __ASM_PPC_FSL_ENET_H
-#define __ASM_PPC_FSL_ENET_H
-
-#include phy.h
-
-struct tsec_mii_mng {
- u32 miimcfg;/* MII management configuration reg */
- u32 miimcom;/* MII management command reg */
- u32 miimadd;/* MII management address reg */
- u32 miimcon;/* MII management control reg */
- u32 miimstat; /* MII management status reg */
- u32 miimind;/* MII management indication reg */
- u32 ifstat; /* Interface Status Register */
-} __attribute__ ((packed));
-
-int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
-
-#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c
b/board/freescale/mpc8360emds/mpc8360emds.c
index ac96163..5ff9dff 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -11,13 +11,13 @@
#include i2c.h
#include miiphy.h
#include phy.h
+#include fsl_mdio.h
#if defined(CONFIG_PCI)
#include pci.h
#endif
#include spd_sdram.h
#include asm/mmu.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/mmu.h
#if defined(CONFIG_OF_LIBFDT)
#include libfdt.h
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c
b/board/freescale/mpc837xemds/mpc837xemds.c
index 0a3c972..c749e55 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -10,7 +10,6 @@
#include i2c.h
#include asm/io.h
#include asm/fsl_mpc83xx_serdes.h
-#include asm/fsl_enet.h
#include spd_sdram.h
#include tsec.h
#include libfdt.h
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
index 78bbd43..8d3dc0e 100644
--- a/drivers/net/fm/dtsec.c
+++ b/drivers/net/fm/dtsec.c
@@ -7,7 +7,6 @@
#include common.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_dtsec.h
#include fsl_mdio.h
#include phy.h
diff --git a/drivers/net/fm/fm.h b/drivers/net/fm/fm.h
index 316e06e..a9691c6 100644
--- a/drivers/net/fm/fm.h
+++ b/drivers/net/fm/fm.h
@@ -8,8 +8,8 @@
#define __FM_H__
#include common.h
+#include phy.h
#include fm_eth.h
-#include asm/fsl_enet.h
#include asm/fsl_fman.h
/* Port ID */
diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c
index ff04695..6cf21c6 100644
--- a/drivers/net/fm/init.c
+++ b/drivers/net/fm/init.c
@@ -6,6 +6,7 @@
#include common.h
#include asm/io.h
#include asm/fsl_serdes.h
+#include fsl_mdio.h
#include fm.h
diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c
index 592a67f..9499290 100644
--- a/drivers/net/fm/memac.c
+++ b/drivers/net/fm/memac.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_memac.h
#include fm.h
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
index f450f80..5017123 100644
--- a/drivers/net/fm/tgec.c
+++ b/drivers/net/fm/tgec.c
@@ -12,7 +12,6 @@
#include phy.h
#include asm/types.h
#include asm/io.h
-#include asm/fsl_enet.h
#include asm/fsl_tgec.h
#include fm.h
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 1d88e65..8d09f5d 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
[U-Boot] [PATCH v4 05/18] net: mdio: Use mb() to be compatible for both ARM and PowerPC
Use mb() instead of sync assembly instruction to be compatible for both ARM and PowerPC. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v4: No change. v3: Use mb() to be compatible for both ARM and PowerPC. Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch. v2: Add private mdio read and write support. drivers/net/fsl_mdio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index 6eae78f..2657c44 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -19,7 +19,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr, out_be32(phyregs-miimadd, (port_addr 8) | (regnum 0x1f)); out_be32(phyregs-miimcon, value); - asm(sync); + mb(); while ((in_be32(phyregs-miimind) MIIMIND_BUSY) timeout--) ; @@ -37,11 +37,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr, /* Clear the command register, and wait */ out_be32(phyregs-miimcom, 0); - asm(sync); + mb(); /* Initiate a read command, and wait */ out_be32(phyregs-miimcom, MIIMCOM_READ_CYCLE); - asm(sync); + mb(); /* Wait for the the indication that the read is done */ while ((in_be32(phyregs-miimind) (MIIMIND_NOTVALID | MIIMIND_BUSY)) -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 07/18] ls102xa: esdhc: Add esdhc support for LS102xA
For LS102xA, the platform is little endian, while esdhc IP is
big endian. So two macros are added, CONFIG_SYS_FSL_ESDHC_LE
and CONFIG_SYS_FSL_ESDHC_BE, to determine the registers'
reading/writing in big or little endian format.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: Add commit messages.
v2: No change.
drivers/mmc/fsl_esdhc.c | 4 ++--
include/fsl_esdhc.h | 14 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 5541613..aec459f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct
mmc_data *data)
else if (cmd-resp_type MMC_RSP_PRESENT)
xfertyp |= XFERTYP_RSPTYP_48;
-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240)
+#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) ||
defined(CONFIG_LS102xA)
if (cmd-cmdidx == MMC_CMD_STOP_TRANSMISSION)
xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
@@ -561,7 +561,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg
*cfg)
memset(cfg-cfg, 0, sizeof(cfg-cfg));
voltage_caps = 0;
- caps = regs-hostcapblt;
+ caps = esdhc_read32(regs-hostcapblt);
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
caps = caps ~(ESDHC_HOSTCAPBLT_SRS |
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 9814964..c1b6648 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -162,7 +162,19 @@ struct fsl_esdhc_cfg {
};
/* Select the correct accessors depending on endianess */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32 in_le32
+#define esdhc_write32 out_le32
+#define esdhc_clrsetbits32 clrsetbits_le32
+#define esdhc_clrbits32clrbits_le32
+#define esdhc_setbits32setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32in_be32
+#define esdhc_write32 out_be32
+#define esdhc_clrsetbits32 clrsetbits_be32
+#define esdhc_clrbits32 clrbits_be32
+#define esdhc_setbits32 setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
#define esdhc_read32 in_le32
#define esdhc_write32 out_le32
#define esdhc_clrsetbits32 clrsetbits_le32
--
1.8.4
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[U-Boot] [PATCH v4 01/18] arm: ls102xa: Add Freescale LS102xA SoC support
From: Wang Huan b18...@freescale.com
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
Change log:
v4: No change.
v3: Fix checkpatch errors.
v2: Add serdes support.
Update DDR frequency and data rate information.
Fix overflow condition error for the timer.
arch/arm/cpu/armv7/ls102xa/Makefile | 12 +
arch/arm/cpu/armv7/ls102xa/clock.c| 130 ++
arch/arm/cpu/armv7/ls102xa/cpu.c | 103 +
arch/arm/cpu/armv7/ls102xa/fdt.c | 128 ++
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 119 ++
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h | 12 +
arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c | 41 ++
arch/arm/cpu/armv7/ls102xa/timer.c| 127 ++
arch/arm/include/asm/arch-ls102xa/clock.h | 23 ++
arch/arm/include/asm/arch-ls102xa/config.h| 71
arch/arm/include/asm/arch-ls102xa/fsl_serdes.h| 33 ++
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 461 ++
arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 +++
arch/arm/include/asm/config.h | 4 +
arch/arm/include/asm/io.h | 8 +-
drivers/watchdog/Makefile | 2 +-
16 files changed, 1325 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile
create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.h
create mode 100644 arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c
create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/fsl_serdes.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
new file mode 100644
index 000..d82ce8d
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clock.o
+obj-y += timer.o
+
+obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c
b/arch/arm/cpu/armv7/ls102xa/clock.c
new file mode 100644
index 000..8f80c61
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/immap_ls102xa.h
+#include asm/arch/clock.h
+#include fsl_ifc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[6] = {
+ [0] = 0,/* CC1 PPL / 1 */
+ [1] = 0,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 1,/* CC2 PPL / 2 */
+ };
+
+ const u8 core_cplx_pll_div[6] = {
+ [0] = 1,/* CC1 PPL / 1 */
+ [1] = 2,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 2,/* CC2 PPL / 2 */
+ };
+
+ uint i;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sys_info-freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info-freq_ddrbus = sysclk;
+#endif
[U-Boot] [PATCH v4 0/18] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS/TWR board support
This series contain the support for Freescale LS102xA SoC and LS1021AQDS/TWR board. The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. For the detail information about LS1021AQDS/TWR board, please refer to README in the patch. Changes in v4: - Add commit messages. Changes in v3: - Fix checkpatch errors. - Add I2C 3 support. - Split arm: ls102xa: Add etsec support for LS102xA into 3 patches. The 3 patches: net: mdio: Add private MDIO read/write function, net: mdio: Use mb() to be compatible for both ARM and PowerPC, ls102xa: etsec: Add etsec support for LS102xA. - Use mb() to be compatible for both ARM and PowerPC. - Update to Kconfig. - Add new patches: net: tsec: Remove tx snooping support from LS1 serial: lpuart: add 32-bit registers lpuart support arm: ls102xa: Add LETECH support for LS1021AQDS/TWR board video: dcu: Add Sii9022A HDMI Transmitter support video: dcu: Add DCU driver support ls102xa: dcu: Add platform support for DCU on LS1021ATWR board Changes in v2: - Add serdes support. - Update DDR frequency and data rate information. - Fix overflow condition error for the timer. - Add private mdio read and write support. - Remove ethaddr/ipaddr setting. - Add board maintainer. - Add serdes and multiple ethernet controllers support. - Add new patch: arm: ls102xa: Add basic support for LS1021ATWR board ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 09/18] driver/ddr/freescale: Fix DDR3 driver for ARM
From: York Sun york...@freescale.com Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun york...@freescale.com --- Change log: v4: No change. v3: No change. v2: No change. drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index d4ed9ae..59f2fd6 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -194,7 +194,7 @@ step2: * For example, 2GB on 666MT/s 64-bit bus takes about 402ms * Let's wait for 800ms */ - bus_width = 3 - ((ddr-sdram_cfg SDRAM_CFG_DBW_MASK) + bus_width = 3 - ((ddr_in32(ddr-sdram_cfg) SDRAM_CFG_DBW_MASK) SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller (6 - bus_width)) * 100 / (get_ddr_freq(0) 20)) 1; -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 06/18] ls102xa: etsec: Add etsec support for LS102xA
For LS102xA, RxBDs and TxBDs are interpreted with little-endian
bytes ordering. The offset for each of eTSECs and MDIOs is
256K bytes.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: No change.
v2: Add private mdio read and write support.
drivers/net/tsec.c | 7 +++
include/tsec.h | 7 ++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..a220221 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
#include fsl_mdio.h
#include asm/errno.h
#include asm/processor.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
do {
uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
}
/* This returns the status bits of the device. The return value
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..5b74f67 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
#include net.h
#include config.h
#include phy.h
-#include fsl_mdio.h
+#ifdef CONFIG_LS102xA
+#define TSEC_SIZE 0x4
+#define TSEC_MDIO_OFFSET 0x4
+#else
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
@@ -128,6 +132,7 @@
#define DMACTRL_INIT_SETTINGS 0x00c3
#define DMACTRL_GRS0x0010
#define DMACTRL_GTS0x0008
+#define DMACTRL_LE 0x8000
#define TSTAT_CLEAR_THALT 0x8000
#define RSTAT_CLEAR_RHALT 0x0080
--
1.8.4
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[U-Boot] [PATCH v4 08/18] driver/ddr/freescale: Add support of accumulate ECC
From: York Sun york...@freescale.com If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun york...@freescale.com --- Change log: v4: No change. v3: No change. v2: No change. drivers/ddr/fsl/ctrl_regs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 04e4178..5e0ee77 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int x32_en = 0;/* x32 enable */ unsigned int pchb8 = 0; /* precharge bit 8 enable */ unsigned int hse; /* Global half strength override */ + unsigned int acc_ecc_en = 0;/* Accumulated ECC enable */ unsigned int mem_halt = 0; /* memory controller halt */ unsigned int bi = 0;/* Bypass initialization */ @@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ba_intlv_ctl = popts-ba_intlv_ctl; hse = popts-half_strength_driver_enable; + /* set when ddr bus width 64 */ + acc_ecc_en = (dbw != 0 ecc_en == 1) ? 1 : 0; + ddr-ddr_sdram_cfg = (0 | ((mem_en 0x1) 31) | ((sren 0x1) 30) @@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((x32_en 0x1) 5) | ((pchb8 0x1) 4) | ((hse 0x1) 3) + | ((acc_ecc_en 0x1) 2) | ((mem_halt 0x1) 1) | ((bi 0x1) 0) ); -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 10/18] driver/ddr/fsl: Add support of overriding chip select write leveling
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun york...@freescale.com
---
Change log:
v4: No change.
v3: No change.
v2: No change.
drivers/ddr/fsl/ctrl_regs.c | 3 +++
drivers/ddr/fsl/interactive.c | 2 ++
include/fsl_ddr_sdram.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 5e0ee77..d9cac22 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
if (ip_rev 0x40400)
unq_mrs_en = 1;
+ if (ip_rev 0x40700)
+ ddr-debug[18] = popts-cswl_override;
+
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index 7fb4187..6aa16b2 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
@@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t
*popts)
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e8a2db9..987119b 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0 0x0401
/*
* Generalized parameters for memory controller configuration,
* might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+ unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
--
1.8.4
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[U-Boot] [PATCH v4 14/18] serial: lpuart: add 32-bit registers lpuart support
From: Jingchang Lu jingchang...@freescale.com
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers
are 32-bit. This patch adds the support for 32-bit registers on
LS102xA.
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Yuan Yao yao.y...@freescale.com
---
Change log:
v4: Add commit messages.
v3: New file.
drivers/serial/serial_lpuart.c | 122 +
1 file changed, 122 insertions(+)
diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c
index da5f9a2..6e639b7 100644
--- a/drivers/serial/serial_lpuart.c
+++ b/drivers/serial/serial_lpuart.c
@@ -17,10 +17,34 @@
#define UC2_TE (1 3)
#define UC2_RE (1 2)
+#define STAT_LBKDIF(1 31)
+#define STAT_RXEDGIF (1 30)
+#define STAT_TDRE (1 23)
+#define STAT_RDRF (1 21)
+#define STAT_IDLE (1 20)
+#define STAT_OR(1 19)
+#define STAT_NF(1 18)
+#define STAT_FE(1 17)
+#define STAT_PF(1 16)
+#define STAT_MA1F (1 15)
+#define STAT_MA2F (1 14)
+#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
+ STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
+
+#define CTRL_TE(1 19)
+#define CTRL_RE(1 18)
+
+#define FIFO_TXFE 0x80
+#define FIFO_RXFE 0x40
+
+#define WATER_TXWATER_OFF 1
+#define WATER_RXWATER_OFF 16
+
DECLARE_GLOBAL_DATA_PTR;
struct lpuart_fsl *base = (struct lpuart_fsl *)LPUART_BASE;
+#ifndef CONFIG_LPUART_32B_REG
static void lpuart_serial_setbrg(void)
{
u32 clk = mxc_get_clock(MXC_UART_CLK);
@@ -107,13 +131,111 @@ static struct serial_device lpuart_serial_drv = {
.getc = lpuart_serial_getc,
.tstc = lpuart_serial_tstc,
};
+#else
+static void lpuart32_serial_setbrg(void)
+{
+ u32 clk = CONFIG_SYS_CLK_FREQ;
+ u32 sbr;
+
+ if (!gd-baudrate)
+ gd-baudrate = CONFIG_BAUDRATE;
+
+ sbr = (clk / (16 * gd-baudrate));
+ /* place adjustment later - n/32 BRFA */
+
+ out_be32(base-baud, sbr);
+}
+
+static int lpuart32_serial_getc(void)
+{
+ u32 stat;
+
+ while (((stat = in_be32(base-stat)) STAT_RDRF) == 0) {
+ out_be32(base-stat, STAT_FLAGS);
+ WATCHDOG_RESET();
+ }
+
+ return in_be32(base-data) 0x3ff;
+}
+
+static void lpuart32_serial_putc(const char c)
+{
+ if (c == '\n')
+ serial_putc('\r');
+
+ while (!(in_be32(base-stat) STAT_TDRE))
+ WATCHDOG_RESET();
+
+ out_be32(base-data, c);
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+static int lpuart32_serial_tstc(void)
+{
+ if ((in_be32(base-water) 24) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static int lpuart32_serial_init(void)
+{
+ u8 ctrl;
+
+ ctrl = in_be32(base-ctrl);
+ ctrl = ~CTRL_RE;
+ ctrl = ~CTRL_TE;
+ out_be32(base-ctrl, ctrl);
+
+ out_be32(base-modir, 0);
+ out_be32(base-fifo, ~(FIFO_TXFE | FIFO_RXFE));
+
+ out_be32(base-match, 0);
+ /* provide data bits, parity, stop bit, etc */
+
+ serial_setbrg();
+
+ out_be32(base-ctrl, CTRL_RE | CTRL_TE);
+
+ return 0;
+}
+
+static struct serial_device lpuart32_serial_drv = {
+ .name = lpuart32_serial,
+ .start = lpuart32_serial_init,
+ .stop = NULL,
+ .setbrg = lpuart32_serial_setbrg,
+ .putc = lpuart32_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpuart32_serial_getc,
+ .tstc = lpuart32_serial_tstc,
+};
+#endif
+void lpuart32_serial_initialize(void)
+{
+ serial_register(lpuart32_serial_drv);
+}
void lpuart_serial_initialize(void)
{
+#ifdef CONFIG_LPUART_32B_REG
+ serial_register(lpuart32_serial_drv);
+#else
serial_register(lpuart_serial_drv);
+#endif
}
__weak struct serial_device *default_serial_console(void)
{
+#ifdef CONFIG_LPUART_32B_REG
+ return lpuart32_serial_drv;
+#else
return lpuart_serial_drv;
+#endif
}
--
1.8.4
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[U-Boot] [PATCH v4 13/18] net: tsec: Remove tx snooping support from LS1
From: Claudiu Manoil claudiu.man...@freescale.com Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a workaround for LS1. It has been observed that currently the Tx stops functioning after a fair amount of Tx traffic with these settings on. These bits are sticky and once set they cannot be reset from Linux, for instance. Signed-off-by: Claudiu Manoil claudiu.man...@freescale.com --- Change log: v4: No change. v3: New file. include/tsec.h | 4 1 file changed, 4 insertions(+) diff --git a/include/tsec.h b/include/tsec.h index 5b74f67..1f0c233 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -129,7 +129,11 @@ #define MINFLR_INIT_SETTINGS 0x0040 +#ifdef CONFIG_LS102xA +#define DMACTRL_INIT_SETTINGS 0x0003 +#else #define DMACTRL_INIT_SETTINGS 0x00c3 +#endif #define DMACTRL_GRS0x0010 #define DMACTRL_GTS0x0008 #define DMACTRL_LE 0x8000 -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 16/18] video: dcu: Add Sii9022A HDMI Transmitter support
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter
is used. This patch adds the common setting for this
chip.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Add commit messages.
v3: New file.
board/freescale/common/Makefile | 2 +
board/freescale/common/dcu_sii9022a.c | 153 ++
board/freescale/common/dcu_sii9022a.h | 13 +++
3 files changed, 168 insertions(+)
create mode 100644 board/freescale/common/dcu_sii9022a.c
create mode 100644 board/freescale/common/dcu_sii9022a.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 22b57cc..808ddd0 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -34,6 +34,8 @@ ifndef CONFIG_RAMBOOT_PBL
obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
endif
+obj-$(CONFIG_FSL_DCU_SII9022A)+= dcu_sii9022a.o
+
obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o
obj-$(CONFIG_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_MPC8555CDS) += cds_pci_ft.o
diff --git a/board/freescale/common/dcu_sii9022a.c
b/board/freescale/common/dcu_sii9022a.c
new file mode 100644
index 000..2da627e
--- /dev/null
+++ b/board/freescale/common/dcu_sii9022a.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include asm/io.h
+#include common.h
+#include fsl_dcu_fb.h
+#include i2c.h
+#include linux/fb.h
+
+#define PIXEL_CLK_LSB_REG 0x00
+#define PIXEL_CLK_MSB_REG 0x01
+#define VERT_FREQ_LSB_REG 0x02
+#define VERT_FREQ_MSB_REG 0x03
+#define TOTAL_PIXELS_LSB_REG 0x04
+#define TOTAL_PIXELS_MSB_REG 0x05
+#define TOTAL_LINES_LSB_REG0x06
+#define TOTAL_LINES_MSB_REG0x07
+#define TPI_INBUS_FMT_REG 0x08
+#define TPI_INPUT_FMT_REG 0x09
+#define TPI_OUTPUT_FMT_REG 0x0A
+#define TPI_SYS_CTRL_REG 0x1A
+#define TPI_PWR_STAT_REG 0x1E
+#define TPI_AUDIO_HANDING_REG 0x25
+#define TPI_AUDIO_INTF_REG 0x26
+#define TPI_AUDIO_FREQ_REG 0x27
+#define TPI_SET_PAGE_REG 0xBC
+#define TPI_SET_OFFSET_REG 0xBD
+#define TPI_RW_ACCESS_REG 0xBE
+#define TPI_TRANS_MODE_REG 0xC7
+
+#define TPI_INBUS_CLOCK_RATIO_1(1 6)
+#define TPI_INBUS_FULL_PIXEL_WIDE (1 5)
+#define TPI_INBUS_RISING_EDGE (1 4)
+#define TPI_INPUT_CLR_DEPTH_8BIT (0 6)
+#define TPI_INPUT_VRANGE_EXPAN_AUTO(0 2)
+#define TPI_INPUT_CLR_RGB (0 0)
+#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 6)
+#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 2)
+#define TPI_OUTPUT_CLR_HDMI_RGB(0 0)
+#define TPI_SYS_TMDS_OUTPUT(0 4)
+#define TPI_SYS_AV_NORAML (0 3)
+#define TPI_SYS_AV_MUTE(1 3)
+#define TPI_SYS_DVI_MODE (0 0)
+#define TPI_SYS_HDMI_MODE (1 0)
+#define TPI_PWR_STAT_MASK (3 0)
+#define TPI_PWR_STAT_D0(0 0)
+#define TPI_AUDIO_PASS_BASIC (0 0)
+#define TPI_AUDIO_INTF_I2S (2 6)
+#define TPI_AUDIO_INTF_NORMAL (0 4)
+#define TPI_AUDIO_TYPE_PCM (1 0)
+#define TPI_AUDIO_SAMP_SIZE_16BIT (1 6)
+#define TPI_AUDIO_SAMP_FREQ_44K(2 3)
+#define TPI_SET_PAGE_SII9022A 0x01
+#define TPI_SET_OFFSET_SII9022A0x82
+#define TPI_RW_EN_SRC_TERMIN (1 0)
+#define TPI_TRANS_MODE_ENABLE (0 7)
+
+/* Programming of Silicon SIi9022a HDMI Transmitter */
+int dcu_set_dvi_encoder(struct fb_videomode *videomode)
+{
+ u8 temp;
+ u16 temp1, temp2;
+ u32 temp3;
+
+ i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
+
+ /* Enable TPI transmitter mode */
+ temp = TPI_TRANS_MODE_ENABLE;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, temp, 1);
+
+ /* Enter into D0 state, full operation */
+ i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, temp, 1);
+ temp = ~TPI_PWR_STAT_MASK;
+ temp |= TPI_PWR_STAT_D0;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, temp, 1);
+
+ /* Enable source termination */
+ temp = TPI_SET_PAGE_SII9022A;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, temp, 1);
+ temp = TPI_SET_OFFSET_SII9022A;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, temp, 1);
+
+ i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, temp, 1);
+ temp |= TPI_RW_EN_SRC_TERMIN;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, temp, 1);
+
+ /* Set TPI system control */
+ temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
+ i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, temp, 1);
+
+ /* Set pixel clock */
+ temp1 = PICOS2KHZ
[U-Boot] [PATCH v4 11/18] arm: ls102xa: Add basic support for LS1021AQDS board
From: Wang Huan b18...@freescale.com LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021AQDS board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Alison Wang alison.w...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: York Sun york...@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- Change log: v4: Add more commit messages. v3: Fix checkpatch error. Update to Kconfig. v2: Remove ethaddr/ipaddr setting. Add board maintainer. Add serdes and multiple ethernet controllers support. arch/arm/Kconfig | 4 + board/freescale/ls1021aqds/Kconfig| 23 ++ board/freescale/ls1021aqds/MAINTAINERS| 6 + board/freescale/ls1021aqds/Makefile | 9 + board/freescale/ls1021aqds/README | 112 +++ board/freescale/ls1021aqds/ddr.c | 166 ++ board/freescale/ls1021aqds/ddr.h | 64 board/freescale/ls1021aqds/eth.c | 129 board/freescale/ls1021aqds/ls1021aqds.c | 248 +++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ configs/ls1021aqds_nor_defconfig | 2 + include/configs/ls1021aqds.h | 424 ++ 12 files changed, 1222 insertions(+) create mode 100644 board/freescale/ls1021aqds/Kconfig create mode 100644 board/freescale/ls1021aqds/MAINTAINERS create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/eth.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 configs/ls1021aqds_nor_defconfig create mode 100644 include/configs/ls1021aqds.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e385eda..62b3cc8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -731,6 +731,9 @@ config TARGET_LS2085A_EMU config TARGET_LS2085A_SIMU bool Support ls2085a_simu +config TARGET_LS1021AQDS + bool Support ls1021aqds_nor + config TARGET_BALLOON3 bool Support balloon3 @@ -865,6 +868,7 @@ source board/eukrea/cpu9260/Kconfig source board/eukrea/cpuat91/Kconfig source board/faraday/a320evb/Kconfig source board/freescale/ls2085a/Kconfig +source board/freescale/ls1021aqds/Kconfig source board/freescale/mx23evk/Kconfig source board/freescale/mx25pdk/Kconfig source board/freescale/mx28evk/Kconfig diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig new file mode 100644 index 000..c28bd2b --- /dev/null +++ b/board/freescale/ls1021aqds/Kconfig @@ -0,0 +1,23 @@ +if TARGET_LS1021AQDS + +config SYS_CPU + string + default armv7 + +config SYS_BOARD + string + default ls1021aqds + +config SYS_VENDOR + string + default freescale + +config SYS_SOC + string + default ls102xa + +config SYS_CONFIG_NAME + string + default ls1021aqds + +endif diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS new file mode 100644 index 000..021d82b --- /dev/null +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -0,0 +1,6 @@ +LS1021AQDS BOARD +M: Alison Wang alison.w...@freescale.com +S: Maintained +F: board/freescale/ls1021aqds/ +F: include/configs/ls1021aqds.h +F: configs/ls1021aqds_nor_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile new file mode 100644 index 000..3b6903c --- /dev/null +++ b/board/freescale/ls1021aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README new file mode 100644 index 000..c561776 --- /dev/null +++ b/board/freescale/ls1021aqds/README @@ -0,0 +1,112 @@ +Overview + +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000
[U-Boot] [PATCH v4 17/18] video: dcu: Add DCU driver support
From: Wang Huan b18...@freescale.com This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v4: No change. v3: New file. arch/arm/include/asm/arch-ls102xa/config.h | 4 + drivers/video/Makefile | 1 + drivers/video/fsl_dcu_fb.c | 365 + include/fsl_dcu_fb.h | 16 ++ 4 files changed, 386 insertions(+) create mode 100644 drivers/video/fsl_dcu_fb.c create mode 100644 include/fsl_dcu_fb.h diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ddc747f..dfc5668 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_FSL_LS1_CLK_ADDR(CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1(CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2(CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_DCU_ADDR(CONFIG_SYS_IMMR + 0x01ce) #define CONFIG_SYS_TSEC1_OFFSET0x01d1 #define CONFIG_SYS_TSEC2_OFFSET0x01d5 @@ -57,6 +58,9 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_DCU_BE + +#define DCU_LAYER_MAX_NUM 16 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 945f35d..3dafef3 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_L5F31188) += l5f31188.o obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c new file mode 100644 index 000..36c1566 --- /dev/null +++ b/drivers/video/fsl_dcu_fb.c @@ -0,0 +1,365 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#include asm/io.h +#include common.h +#include fsl_dcu_fb.h +#include linux/fb.h +#include malloc.h +#include video_fb.h +#include videomodes.h + +/* Convert the X,Y resolution pair into a single number */ +#define RESOLUTION(x, y) (((u32)(x) 16) | (y)) + +#ifdef CONFIG_SYS_FSL_DCU_LE +#definedcu_read32 in_le32 +#definedcu_write32 out_le32 +#elif defined(CONFIG_SYS_FSL_DCU_BE) +#definedcu_read32 in_be32 +#definedcu_write32 out_be32 +#endif + +#define DCU_MODE_BLEND_ITER(x) ((x) 20) +#define DCU_MODE_RASTER_EN (1 14) +#define DCU_MODE_NORMAL1 +#define DCU_MODE_COLORBAR 3 +#define DCU_BGND_R(x) ((x) 16) +#define DCU_BGND_G(x) ((x) 8) +#define DCU_BGND_B(x) (x) +#define DCU_DISP_SIZE_DELTA_Y(x) ((x) 16) +#define DCU_DISP_SIZE_DELTA_X(x) (x) +#define DCU_HSYN_PARA_BP(x)((x) 22) +#define DCU_HSYN_PARA_PW(x)((x) 11) +#define DCU_HSYN_PARA_FP(x)(x) +#define DCU_VSYN_PARA_BP(x)((x) 22) +#define DCU_VSYN_PARA_PW(x)((x) 11) +#define DCU_VSYN_PARA_FP(x)(x) +#define DCU_SYN_POL_INV_PXCK_FALL (0 6) +#define DCU_SYN_POL_NEG_REMAIN (0 5) +#define DCU_SYN_POL_INV_VS_LOW (1 1) +#define DCU_SYN_POL_INV_HS_LOW (1) +#define DCU_THRESHOLD_LS_BF_VS(x) ((x) 16) +#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) 8) +#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) +#define DCU_UPDATE_MODE_MODE(1 31) +#define DCU_UPDATE_MODE_READREG (1 30) + +#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) 16) +#define DCU_CTRLDESCLN_1_WIDTH(x) (x) +#define DCU_CTRLDESCLN_2_POSY(x) ((x) 16) +#define DCU_CTRLDESCLN_2_POSX(x) (x) +#define DCU_CTRLDESCLN_4_EN(1 31) +#define DCU_CTRLDESCLN_4_TILE_EN (1 30) +#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 29) +#define DCU_CTRLDESCLN_4_SAFETY_EN (1 28) +#define DCU_CTRLDESCLN_4_TRANS(x) ((x) 20) +#define DCU_CTRLDESCLN_4_BPP(x)((x) 16) +#define DCU_CTRLDESCLN_4_RLE_EN(1 15) +#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) 4) +#define DCU_CTRLDESCLN_4_BB_ON (1 2) +#define DCU_CTRLDESCLN_4_AB(x) (x) +#define DCU_CTRLDESCLN_5_CKMAX_R(x)((x) 16) +#define DCU_CTRLDESCLN_5_CKMAX_G(x
[U-Boot] [PATCH v4 12/18] arm: ls102xa: Add basic support for LS1021ATWR board
From: Wang Huan b18...@freescale.com LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021ATWR board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Chen Lu chen...@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v4: Add more commit messages. v3: Fix checkpatch error. Update to Kconfig. v2: New file. arch/arm/Kconfig| 4 + board/freescale/ls1021atwr/Kconfig | 23 ++ board/freescale/ls1021atwr/MAINTAINERS | 6 + board/freescale/ls1021atwr/Makefile | 7 + board/freescale/ls1021atwr/README | 109 +++ board/freescale/ls1021atwr/ls1021atwr.c | 494 configs/ls1021atwr_nor_defconfig| 2 + include/configs/ls1021atwr.h| 284 ++ 8 files changed, 929 insertions(+) create mode 100644 board/freescale/ls1021atwr/Kconfig create mode 100644 board/freescale/ls1021atwr/MAINTAINERS create mode 100644 board/freescale/ls1021atwr/Makefile create mode 100644 board/freescale/ls1021atwr/README create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c create mode 100644 configs/ls1021atwr_nor_defconfig create mode 100644 include/configs/ls1021atwr.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 62b3cc8..d207db7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -734,6 +734,9 @@ config TARGET_LS2085A_SIMU config TARGET_LS1021AQDS bool Support ls1021aqds_nor +config TARGET_LS1021ATWR + bool Support ls1021atwr_nor + config TARGET_BALLOON3 bool Support balloon3 @@ -869,6 +872,7 @@ source board/eukrea/cpuat91/Kconfig source board/faraday/a320evb/Kconfig source board/freescale/ls2085a/Kconfig source board/freescale/ls1021aqds/Kconfig +source board/freescale/ls1021atwr/Kconfig source board/freescale/mx23evk/Kconfig source board/freescale/mx25pdk/Kconfig source board/freescale/mx28evk/Kconfig diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig new file mode 100644 index 000..057808d --- /dev/null +++ b/board/freescale/ls1021atwr/Kconfig @@ -0,0 +1,23 @@ +if TARGET_LS1021ATWR + +config SYS_CPU + string + default armv7 + +config SYS_BOARD + string + default ls1021atwr + +config SYS_VENDOR + string + default freescale + +config SYS_SOC + string + default ls102xa + +config SYS_CONFIG_NAME + string + default ls1021atwr + +endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS new file mode 100644 index 000..4e5bc15 --- /dev/null +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -0,0 +1,6 @@ +LS1021ATWR BOARD +M: Alison Wang alison.w...@freescale.com +S: Maintained +F: board/freescale/ls1021atwr/ +F: include/configs/ls1021atwr.h +F: configs/ls1021atwr_nor_defconfig diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile new file mode 100644 index 000..b5df668 --- /dev/null +++ b/board/freescale/ls1021atwr/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README new file mode 100644 index 000..d2821cb --- /dev/null +++ b/board/freescale/ls1021atwr/README @@ -0,0 +1,109 @@ +Overview + +The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32
[U-Boot] [PATCH v4 04/18] net: mdio: Add private MDIO read/write function
As extra FPGA settings is needed for MDIO read/write
on LS1021AQDS, private MDIO read/write functions are
created.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: Split from the 0004-arm-ls102xa-Add-etsec-support-for-LS102xA patch.
v2: Add private mdio read and write support.
drivers/net/fsl_mdio.c | 9 +++--
include/fsl_mdio.h | 4
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 8d09f5d..6eae78f 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -98,8 +98,13 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info
*info)
return -1;
}
- bus-read = tsec_phy_read;
- bus-write = tsec_phy_write;
+ if (info-priv_mdio_read) {
+ bus-read = info-priv_mdio_read;
+ bus-write = info-priv_mdio_write;
+ } else {
+ bus-read = tsec_phy_read;
+ bus-write = tsec_phy_write;
+ }
bus-reset = fsl_pq_mdio_reset;
sprintf(bus-name, info-name);
diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index a531edf..633123c 100644
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -57,6 +57,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int
dev_addr,
struct fsl_pq_mdio_info {
struct tsec_mii_mng __iomem *regs;
char *name;
+ int (*priv_mdio_read)(struct mii_dev *bus, int addr,
+ int devad, int reg);
+ int (*priv_mdio_write)(struct mii_dev *bus, int addr, int devad,
+ int reg, u16 val);
};
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
--
1.8.4
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[U-Boot] [PATCH v4 15/18] arm: ls102xa: Add LETECH support for LS1021AQDS/TWR board
From: Wang Huan b18...@freescale.com This patch is to add LETECH support for LS1021AQDS/TWR board. For LETECH, lpuart is used as console. Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Alison Wang alison.w...@freescale.com --- Change log: v4: No change. v3: New file. board/freescale/ls1021aqds/MAINTAINERS | 1 + board/freescale/ls1021atwr/MAINTAINERS | 1 + configs/ls1021aqds_letech_defconfig| 3 +++ configs/ls1021atwr_letech_defconfig| 3 +++ include/configs/ls1021aqds.h | 13 + include/configs/ls1021atwr.h | 12 6 files changed, 33 insertions(+) create mode 100644 configs/ls1021aqds_letech_defconfig create mode 100644 configs/ls1021atwr_letech_defconfig diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 021d82b..590b89b 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/ls1021aqds/ F: include/configs/ls1021aqds.h F: configs/ls1021aqds_nor_defconfig +F: configs/ls1021aqds_letech_defconfig diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 4e5bc15..14a7441 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/ls1021atwr/ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig +F: configs/ls1021atwr_letech_defconfig diff --git a/configs/ls1021aqds_letech_defconfig b/configs/ls1021aqds_letech_defconfig new file mode 100644 index 000..b70971e --- /dev/null +++ b/configs/ls1021aqds_letech_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS=LETECH ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021atwr_letech_defconfig b/configs/ls1021atwr_letech_defconfig new file mode 100644 index 000..4b187b3 --- /dev/null +++ b/configs/ls1021atwr_letech_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS=LETECH ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 856fdfc..5a8bf21 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -279,11 +279,16 @@ unsigned long get_board_ddr_clk(void); /* * Serial Port */ +#ifdef CONFIG_LETECH +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE115200 @@ -367,11 +372,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 +#ifdef CONFIG_LETECH +#define CONFIG_EXTRA_ENV_SETTINGS \ + bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0 \ + fdt_high=0xcfff\0 \ + initrd_high=0xcfff\0 \ + hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0 +#else #define CONFIG_EXTRA_ENV_SETTINGS \ bootargs=root=/dev/ram0 rw console=ttyS0,115200\0 \ fdt_high=0xcfff\0 \ initrd_high=0xcfff\0 \ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0 +#endif /* * Miscellaneous configurable options diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index f8cbe32..b268a70 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -147,11 +147,16 @@ unsigned long get_board_ddr_clk(void); /* * Serial Port */ +#ifdef CONFIG_LETECH +#define CONFIG_FSL_LPUART +#define CONFIG_LPUART_32B_REG +#else #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE115200 @@ -228,10 +233,17 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTDELAY 3 +#ifdef CONFIG_LETECH +#define CONFIG_EXTRA_ENV_SETTINGS \ + bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0 \ + initrd_high=0xcfff\0 \ + fdt_high=0xcfff\0 +#else #define CONFIG_EXTRA_ENV_SETTINGS \ bootargs=root=/dev/ram0 rw console=ttyS0,115200\0 \ initrd_high=0xcfff\0 \ fdt_high=0xcfff\0 +#endif /* * Miscellaneous configurable options -- 1.8.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 18/18] ls102xa: dcu: Add platform support for DCU on LS1021ATWR board
From: Wang Huan b18...@freescale.com
This patch adds the TWR_LCD_RGB card/HDMI options and the common
configuration for DCU on LS1021ATWR board.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Add commit messages.
v3: New file.
board/freescale/ls1021atwr/Makefile | 1 +
board/freescale/ls1021atwr/dcu.c| 47 +
board/freescale/ls1021atwr/ls1021atwr.c | 6 +
include/configs/ls1021atwr.h| 18 +
4 files changed, 72 insertions(+)
create mode 100644 board/freescale/ls1021atwr/dcu.c
diff --git a/board/freescale/ls1021atwr/Makefile
b/board/freescale/ls1021atwr/Makefile
index b5df668..01296c0 100644
--- a/board/freescale/ls1021atwr/Makefile
+++ b/board/freescale/ls1021atwr/Makefile
@@ -5,3 +5,4 @@
#
obj-y += ls1021atwr.o
+obj-$(CONFIG_FSL_DCU_FB) += dcu.o
diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c
new file mode 100644
index 000..8fe4ccb
--- /dev/null
+++ b/board/freescale/ls1021atwr/dcu.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * FSL DCU Framebuffer driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include fsl_dcu_fb.h
+#include div64.h
+#include ../common/dcu_sii9022a.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int dcu_set_pixel_clock(unsigned int pixclock)
+{
+ unsigned long long div;
+
+ div = (unsigned long long)(gd-bus_clk / 1000);
+ div *= (unsigned long long)pixclock;
+ do_div(div, 10);
+
+ return div;
+}
+
+int platform_dcu_init(unsigned int xres, unsigned int yres,
+ const char *port,
+ struct fb_videomode *dcu_fb_videomode)
+{
+ const char *name;
+ unsigned int pixel_format;
+
+ if (strncmp(port, twr_lcd, 4) == 0) {
+ name = TWR_LCD_RGB card;
+ } else {
+ name = HDMI;
+ dcu_set_dvi_encoder(dcu_fb_videomode);
+ }
+
+ printf(DCU: Switching to %s monitor @ %ux%u\n, name, xres, yres);
+
+ pixel_format = 32;
+ fsl_dcu_init(xres, yres, pixel_format);
+
+ return 0;
+}
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 7fdcbcd..e4364dd 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -264,6 +264,12 @@ int board_early_init_f(void)
init_early_memctl_regs();
#endif
+#ifdef CONFIG_FSL_DCU_FB
+ out_be32(scfg-scfgrevcr, 0x);
+ out_be32(scfg-pixclkcr, 0x8000);
+ out_be32(scfg-scfgrevcr, 0x);
+#endif
+
out_le32(cci-ctrl_ord, 0x0008);
return 0;
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index b268a70..fb2cf08 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -182,6 +182,24 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_GENERIC_MMC
/*
+ * Video
+ */
+#define CONFIG_FSL_DCU_FB
+
+#ifdef CONFIG_FSL_DCU_FB
+#define CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
+
+#define CONFIG_FSL_DCU_SII9022A
+#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
+#define CONFIG_SYS_I2C_DVI_ADDR0x39
+#endif
+
+/*
* eTSEC
*/
#define CONFIG_TSEC_ENET
--
1.8.4
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[U-Boot] [PATCH 2/9] arm: ls102xa: Add i2c support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
drivers/i2c/mxc_i2c.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 48468d7..792fc40 100644
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -423,7 +423,7 @@ static void * const i2c_bases[] = {
(void *)IMX_I2C2_BASE
#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
- defined(CONFIG_MX6)
+ defined(CONFIG_MX6) || defined(CONFIG_LS102xA)
(void *)I2C1_BASE_ADDR,
(void *)I2C2_BASE_ADDR,
(void *)I2C3_BASE_ADDR
--
1.8.0
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[U-Boot] [PATCH 4/9] arm: ls102xa: Add etsec support for LS102xA
Signed-off-by: Alison Wang alison.w...@freescale.com
---
drivers/net/fsl_mdio.c | 15 ---
drivers/net/tsec.c | 7 +++
include/tsec.h | 7 ++-
3 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c
index 8d09f5d..5cee709 100644
--- a/drivers/net/fsl_mdio.c
+++ b/drivers/net/fsl_mdio.c
@@ -12,6 +12,15 @@
#include asm/io.h
#include asm/errno.h
+void tsec_mdio_sync(void)
+{
+#if defined(CONFIG_PPC)
+ asm(sync);
+#elif defined(CONFIG_ARM)
+ asm(dsb);
+#endif
+}
+
void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
{
@@ -19,7 +28,7 @@ void tsec_local_mdio_write(struct tsec_mii_mng __iomem
*phyregs, int port_addr,
out_be32(phyregs-miimadd, (port_addr 8) | (regnum 0x1f));
out_be32(phyregs-miimcon, value);
- asm(sync);
+ tsec_mdio_sync();
while ((in_be32(phyregs-miimind) MIIMIND_BUSY) timeout--)
;
@@ -37,11 +46,11 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem
*phyregs, int port_addr,
/* Clear the command register, and wait */
out_be32(phyregs-miimcom, 0);
- asm(sync);
+ tsec_mdio_sync();
/* Initiate a read command, and wait */
out_be32(phyregs-miimcom, MIIMCOM_READ_CYCLE);
- asm(sync);
+ tsec_mdio_sync();
/* Wait for the the indication that the read is done */
while ((in_be32(phyregs-miimind) (MIIMIND_NOTVALID | MIIMIND_BUSY))
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..a220221 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
#include fsl_mdio.h
#include asm/errno.h
#include asm/processor.h
+#include asm/io.h
DECLARE_GLOBAL_DATA_PTR;
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
do {
uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
out_be32(regs-tstat, TSTAT_CLEAR_THALT);
out_be32(regs-rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(regs-dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102xA
+ setbits_be32(regs-dmactrl, DMACTRL_LE);
+#endif
}
/* This returns the status bits of the device. The return value
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..5b74f67 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
#include net.h
#include config.h
#include phy.h
-#include fsl_mdio.h
+#ifdef CONFIG_LS102xA
+#define TSEC_SIZE 0x4
+#define TSEC_MDIO_OFFSET 0x4
+#else
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
@@ -128,6 +132,7 @@
#define DMACTRL_INIT_SETTINGS 0x00c3
#define DMACTRL_GRS0x0010
#define DMACTRL_GTS0x0008
+#define DMACTRL_LE 0x8000
#define TSTAT_CLEAR_THALT 0x8000
#define RSTAT_CLEAR_RHALT 0x0080
--
1.8.0
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[U-Boot] [PATCH 8/9] driver/ddr/fsl: Add support of overriding chip select write leveling
From: York Sun york...@freescale.com
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/ctrl_regs.c | 3 +++
drivers/ddr/fsl/interactive.c | 2 ++
include/fsl_ddr_sdram.h | 2 ++
3 files changed, 7 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 4c7a1e8..0cf0400 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -2273,6 +2273,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t
*popts,
if (ip_rev 0x40400)
unq_mrs_en = 1;
+ if (ip_rev 0x40700)
+ ddr-debug[18] = popts-cswl_override;
+
set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en);
set_ddr_sdram_mode(ddr, popts, common_dimm,
cas_latency, additive_latency, unq_mrs_en);
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index cfe1e1f..cdb12de 100644
--- a/drivers/ddr/fsl/interactive.c
+++ b/drivers/ddr/fsl/interactive.c
@@ -510,6 +510,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
@@ -800,6 +801,7 @@ static void print_memctl_options(const memctl_options_t
*popts)
CTRL_OPTIONS(wrlvl_override),
CTRL_OPTIONS(wrlvl_sample),
CTRL_OPTIONS(wrlvl_start),
+ CTRL_OPTIONS_HEX(cswl_override),
CTRL_OPTIONS(rcw_override),
CTRL_OPTIONS(rcw_1),
CTRL_OPTIONS(rcw_2),
diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h
index e8a2db9..987119b 100644
--- a/include/fsl_ddr_sdram.h
+++ b/include/fsl_ddr_sdram.h
@@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s {
#define DDR_DATA_BUS_WIDTH_64 0
#define DDR_DATA_BUS_WIDTH_32 1
#define DDR_DATA_BUS_WIDTH_16 2
+#define DDR_CSWL_CS0 0x0401
/*
* Generalized parameters for memory controller configuration,
* might be a little specific to the FSL memory controller
@@ -340,6 +341,7 @@ typedef struct memctl_options_s {
unsigned int cpo_override;
unsigned int write_data_delay; /* DQS adjust */
+ unsigned int cswl_override;
unsigned int wrlvl_override;
unsigned int wrlvl_sample; /* Write leveling */
unsigned int wrlvl_start;
--
1.8.0
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[U-Boot] [PATCH 6/9] driver/ddr/freescale: Add support of accumulate ECC
From: York Sun york...@freescale.com If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun york...@freescale.com --- drivers/ddr/fsl/ctrl_regs.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 78e82bb..4c7a1e8 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -693,6 +693,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, unsigned int x32_en = 0;/* x32 enable */ unsigned int pchb8 = 0; /* precharge bit 8 enable */ unsigned int hse; /* Global half strength override */ + unsigned int acc_ecc_en = 0;/* Accumulated ECC enable */ unsigned int mem_halt = 0; /* memory controller halt */ unsigned int bi = 0;/* Bypass initialization */ @@ -736,6 +737,9 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, ba_intlv_ctl = popts-ba_intlv_ctl; hse = popts-half_strength_driver_enable; + /* set when ddr bus width 64 */ + acc_ecc_en = (dbw != 0 ecc_en == 1) ? 1 : 0; + ddr-ddr_sdram_cfg = (0 | ((mem_en 0x1) 31) | ((sren 0x1) 30) @@ -752,6 +756,7 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, | ((x32_en 0x1) 5) | ((pchb8 0x1) 4) | ((hse 0x1) 3) + | ((acc_ecc_en 0x1) 2) | ((mem_halt 0x1) 1) | ((bi 0x1) 0) ); -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 7/9] driver/ddr/freescale: Fix DDR3 driver for ARM
From: York Sun york...@freescale.com Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun york...@freescale.com --- drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index d4ed9ae..59f2fd6 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -194,7 +194,7 @@ step2: * For example, 2GB on 666MT/s 64-bit bus takes about 402ms * Let's wait for 800ms */ - bus_width = 3 - ((ddr-sdram_cfg SDRAM_CFG_DBW_MASK) + bus_width = 3 - ((ddr_in32(ddr-sdram_cfg) SDRAM_CFG_DBW_MASK) SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller (6 - bus_width)) * 100 / (get_ddr_freq(0) 20)) 1; -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 0/9] arm: ls102xa: Add Freescale LS102xA SoC and LS1021AQDS board support
This series contain the support for Freescale LS102xA SoC and LS1021AQDS board. The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. For the detail information about LS1021AQDS board, please refer to README in the patch. Alison Wang (5): arm: ls102xa: Add Freescale LS102xA SoC support arm: ls102xa: Add i2c support for LS102xA arm: ls102xa: Add etsec support for LS102xA arm: ls102xa: Add esdhc support for LS102xA arm: ls102xa: Add basic support for LS1021AQDS board Claudiu Manoil (1): net: Merge asm/fsl_enet.h into fsl_mdio.h York Sun (3): driver/ddr/freescale: Add support of accumulate ECC driver/ddr/freescale: Fix DDR3 driver for ARM driver/ddr/fsl: Add support of overriding chip select write leveling arch/powerpc/include/asm/fsl_enet.h | 24 -- board/freescale/ls1021aqds/Makefile | 8 + board/freescale/ls1021aqds/README | 112 + board/freescale/ls1021aqds/ddr.c | 169 + board/freescale/ls1021aqds/ddr.h | 64 + board/freescale/ls1021aqds/ls1021aqds.c | 208 board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ board/freescale/mpc8360emds/mpc8360emds.c | 2 +- board/freescale/mpc837xemds/mpc837xemds.c | 1 - boards.cfg| 1 + drivers/ddr/fsl/arm_ddr_gen3.c| 2 +- drivers/ddr/fsl/ctrl_regs.c | 8 + drivers/ddr/fsl/interactive.c | 2 + drivers/i2c/mxc_i2c.c | 2 +- drivers/mmc/fsl_esdhc.c | 4 +- drivers/net/fm/dtsec.c| 1 - drivers/net/fm/fm.h | 2 +- drivers/net/fm/init.c | 1 + drivers/net/fm/memac.c| 1 - drivers/net/fm/tgec.c | 1 - drivers/net/fsl_mdio.c| 16 +- drivers/net/tsec.c| 7 + drivers/qe/uec.h | 1 - include/common.h | 5 +- include/configs/ls1021aqds.h | 418 include/fm_eth.h | 2 +- include/fsl_ddr_sdram.h | 2 + include/fsl_esdhc.h | 14 +- include/fsl_mdio.h| 13 +- include/tsec.h| 7 +- 30 files changed, 1087 insertions(+), 46 deletions(-) delete mode 100644 arch/powerpc/include/asm/fsl_enet.h create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 include/configs/ls1021aqds.h ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/9] arm: ls102xa: Add Freescale LS102xA SoC support
The QorIQ LS1 family is built on Layerscape architecture,
the industry's first software-aware, core-agnostic networking
architecture to offer unprecedented efficiency and scale.
Freescale LS102xA is a set of SoCs combines two ARM
Cortex-A7 cores that have been optimized for high
reliability and pack the highest level of integration
available for sub-3 W embedded communications processors
with Layerscape architecture and with a comprehensive
enablement model focused on ease of programmability.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Jingchang Lu jingchang...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/Makefile | 11 +
arch/arm/cpu/armv7/ls102xa/clock.c| 131 +++
arch/arm/cpu/armv7/ls102xa/cpu.c | 102 ++
arch/arm/cpu/armv7/ls102xa/fdt.c | 82 +
arch/arm/cpu/armv7/ls102xa/timer.c| 129 +++
arch/arm/include/asm/arch-ls102xa/clock.h | 23 ++
arch/arm/include/asm/arch-ls102xa/config.h| 70
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 420 ++
arch/arm/include/asm/arch-ls102xa/imx-regs.h | 53 +++
arch/arm/include/asm/config.h | 4 +
arch/arm/include/asm/io.h | 8 +-
drivers/watchdog/Makefile | 2 +-
12 files changed, 1033 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/Makefile
create mode 100644 arch/arm/cpu/armv7/ls102xa/clock.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/cpu.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fdt.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/timer.c
create mode 100644 arch/arm/include/asm/arch-ls102xa/clock.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/config.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
create mode 100644 arch/arm/include/asm/arch-ls102xa/imx-regs.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
new file mode 100644
index 000..7ef793a
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -0,0 +1,11 @@
+#
+# Copyright 2014 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cpu.o
+obj-y += clock.o
+obj-y += timer.o
+
+obj-$(CONFIG_OF_LIBFDT)+= fdt.o
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c
b/arch/arm/cpu/armv7/ls102xa/clock.c
new file mode 100644
index 000..75bb0e9
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/immap_ls102xa.h
+#include asm/arch/clock.h
+#include fsl_ifc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
+#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
+#endif
+
+void get_sys_info(struct sys_info *sys_info)
+{
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+ struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+ u32 ccr;
+#endif
+ struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ unsigned int cpu;
+ const u8 core_cplx_pll[6] = {
+ [0] = 0,/* CC1 PPL / 1 */
+ [1] = 0,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 1,/* CC2 PPL / 2 */
+ };
+
+ const u8 core_cplx_pll_div[6] = {
+ [0] = 1,/* CC1 PPL / 1 */
+ [1] = 2,/* CC1 PPL / 2 */
+ [4] = 1,/* CC2 PPL / 1 */
+ [5] = 2,/* CC2 PPL / 2 */
+ };
+
+ uint i;
+ uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
+
+ sys_info-freq_systembus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+ sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+#else
+ sys_info-freq_ddrbus = sysclk;
+#endif
+
+ sys_info-freq_systembus *= (in_be32(gur-rcwsr[0])
+ RCWSR0_SYS_PLL_RAT_SHIFT) RCWSR0_SYS_PLL_RAT_MASK;
+ sys_info-freq_ddrbus *= (in_be32(gur-rcwsr[0])
+ RCWSR0_MEM_PLL_RAT_SHIFT) RCWSR0_MEM_PLL_RAT_MASK;
+
+ for (i = 0; i CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
+ ratio[i] = (in_be32(clk-pllcgsr[i].pllcngsr) 1) 0x3f;
+ if (ratio[i] 4)
+ freq_c_pll[i] = sysclk * ratio[i];
+ else
+ freq_c_pll[i] = sys_info-freq_systembus * ratio[i];
+ }
+
+ for (cpu = 0; cpu CONFIG_MAX_CPUS; cpu++) {
+ u32 c_pll_sel = (in_be32(clk-clkcsr[cpu].clkcncsr) 27)
+0xf;
+ u32 cplx_pll = core_cplx_pll
[U-Boot] [PATCH 9/9] arm: ls102xa: Add basic support for LS1021AQDS board
Signed-off-by: Alison Wang alison.w...@freescale.com Signed-off-by: Jason Jin jason@freescale.com Signed-off-by: York Sun york...@freescale.com Signed-off-by: Yuan Yao yao.y...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com --- board/freescale/ls1021aqds/Makefile | 8 + board/freescale/ls1021aqds/README | 112 +++ board/freescale/ls1021aqds/ddr.c | 169 +++ board/freescale/ls1021aqds/ddr.h | 64 board/freescale/ls1021aqds/ls1021aqds.c | 208 + board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ boards.cfg| 1 + include/common.h | 5 +- include/configs/ls1021aqds.h | 418 ++ 9 files changed, 1017 insertions(+), 3 deletions(-) create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 include/configs/ls1021aqds.h diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile new file mode 100644 index 000..96c8c4c --- /dev/null +++ b/board/freescale/ls1021aqds/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README new file mode 100644 index 000..c561776 --- /dev/null +++ b/board/freescale/ls1021aqds/README @@ -0,0 +1,112 @@ +Overview + +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +-- +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine
