From: Chenhui Zhao chenhui.z...@freescale.com
When resuming from deep sleep, the I2C channel may not be
in the default channel. So, switch to the default channel
before accessing DDR SPD.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
board/freescale/ls1021aqds/ls1021aqds.c | 32
CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
S0 will cause CAAM self test failure. This patch is to enable snooping
for S0 slave interface.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
board/freescale/ls1021aqds/ls1021aqds.c | 3 +--
board/freescale
This patch will fix the bug that the partitions on the SD card could
not be accessed and add the support for the FAT fs.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
include/configs/ls1021aqds.h | 3 +++
include/configs/ls1021atwr.h | 3 +++
2 files changed, 6 insertions(+)
diff
variable: bootmode
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/m68k/cpu/mcf5227x/speed.c | 2 +-
arch/m68k/cpu/mcf532x/speed.c | 3 ++-
arch/m68k/cpu/mcf5445x/speed.c | 2 +-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/m68k/cpu/mcf5227x/speed.c b/arch/m68k/cpu
the definition of CONFIG_SPL_MAX_SIZE.
Pad the variable u-boot size to 64 byte boundary in pblimage tool.
Use pblimage_check_params() insteady of basing on the file name.
Use generic u-boot-spl.lds.
Alison Wang (9
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log
and the calculation
of pbl_cmd_initaddr.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: Change the Copyright year.
v2: Remove the definition of CONFIG_SPL_MAX_SIZE.
Pad the variable u-boot size to 64 byte boundary in pblimage tool.
Use pblimage_check_params
make: *** [spl/u-boot-spl] Error 2
So this patch fixed this issue and the above .o files will be produced
no matter CONFIG_SPL_BUILD is enabled or disabled.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: Gave more explaination in the commit.
v2
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.w...@freescale.com
to fix the issue about
using I2C in SPL.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: No change.
v3: No change.
v2: New file.
arch/arm/cpu/u-boot-spl.lds | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log
-by: Alison Wang alison.w...@freescale.com
Signed-off-by: Jason Jin jason@freescale.com
---
Change log:
v4: Enable IFC in SD boot.
v3: Update MAINTAINERS file.
Update PBI and RCW for SD boot.
v2: Use generic u-boot-spl.lds.
board/freescale/ls1021atwr/MAINTAINERS| 1 +
board
...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Use some defines instead of the magic numbers.
v3: New file.
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 +
board/freescale/ls1021aqds/MAINTAINERS
Add SUPPORT_SPL feature for SD and NAND boot on
LS1021AQDS and LS1021ATWR.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: New file.
arch/arm/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0982117..1f00e93 100644
As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR
boards, the prompt message Support ls1021aqds_nor in
Kconfig is not clear. This patch changes it to
Support ls1021aqds.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/Kconfig | 4 ++--
1 file changed, 2 insertions(+), 2
...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v4: Use some defines instead of the magic numbers.
v3: New file.
arch/arm/include/asm/arch-ls102xa/config.h| 1 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 ++
board/freescale/ls1021aqds/MAINTAINERS
...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Rebase the patch.
Add CONFIG_SYS_DCSR_DCFG_ADDR instead of CONFIG_SYS_DCSRBAR.
arch/arm/include/asm/arch-ls102xa/config.h| 3 +
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 ++
board/freescale
This patch adds QSPI boot support for LS1021AQDS/TWR board.
The QSPI boot image need to be programmed into the QSPI flash
first. Then the booting will start from QSPI memory space.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Rebase the patch.
arch/arm/include/asm
This patch will fix the bug that the partitions on the SD card could
not be accessed and add the support for the FAT fs.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
v2: Rebase the patch.
include/configs/ls1021aqds.h | 3 +++
include/configs/ls1021atwr.h | 3 +++
2
The SD/NAND/QSPI boot definations are wrong for QE support, this
patch is to fix this error.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
include/configs/ls1021aqds.h | 3 ++-
include/configs/ls1021atwr.h | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/include
This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and
CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will
be used via hwconfig.
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm
As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are
only enabled in QSPI boot, and disabled in other boot modes.
IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot.
This patch will add fdt support for the above rules.
Signed-off-by: Alison Wang alison.w...@freescale.com
There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Changes in v2:
- Move changing CCSR macros to a separated patch.
arch/arm/include/asm
This patch is to define default values for some CCSR macros
to make header files cleaner.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 37 +++
1 file changed, 37 insertions(+)
diff --git a/arch/arm/include/asm
requests and DVM message requests are enabled.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
board/freescale/ls1021aqds/ls1021aqds.c | 21 ---
board/freescale/ls1021atwr/ls1021atwr.c | 25
This patch adds generic board support for MCF547X/8X and MCF5445X.
It is based on the patch about common generic board support for
M68K architecture sent by Angelo.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
common/board_f.c | 8
common/board_r.c
On silicon VER1.0, there is an interleaving issue on CCI400
slave interface S2. The workaround is to enable regulation
of outstanding read transactions for slave interface S2.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
board
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +
board/freescale/ls1021aqds/ls1021aqds.c | 69
There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
for using the same SMMU3 on LS1021A.
Signed-off-by: Xiubo Li li.xi...@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
arch/arm/include/asm/arch
This patch adds LPUART support for LS1021AQDS board.
For ls1021aqds_nor_lpuart_defconfig, LPUART is used as the console.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
board/freescale/ls1021aqds/MAINTAINERS | 1 +
configs/ls1021aqds_nor_lpuart_defconfig | 3 +++
include/configs
This patch adds LPUART support for LS1021ATWR board.
For ls1021atwr_nor_lpuart_defconfig, LPUART is used as the console.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
board/freescale/ls1021atwr/MAINTAINERS | 1 +
configs/ls1021atwr_nor_lpuart_defconfig | 3 +++
include/configs
On QDS board with DDR4 DIMM, LPUART is used as console
output to verify DCU driver. This patch adds
ls1021aqds_ddr4_nor_lpuart_defconfig for this support.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
board/freescale/ls1021aqds/MAINTAINERS | 1 +
configs
This patch will enable regulation of outstanding read
transactions for slave interface S2 for silicon VER1.0.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Changes in v2:
- Modify the subject and commit to describe accurately
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Changes in v2:
- Modify the subject to describe accurately
- Change SOC_VER_1_0 and SOC_VER_2_0 to SOC_MAJOR_VER_1_0
-Boot for NOR boot is
adjusted to 0x6010.
In RCW, the PBI command needs to change as follows:
.pbi
-write 0xee0200, 0x67f8
+write 0xee0200, 0x6010
.end
Signed-off-by: Alison Wang alison.w...@freescale.com
---
include/configs/ls1021aqds.h | 2 +-
include/configs/ls1021atwr.h | 2 +-
2
As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.
Signed-off-by: Alison
As SCFG_ENDIANCR register is added to choose little-endian or big-endian
for audio IPs on Rev2.0 silion, little-endian mode is selected.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 ++-
board/freescale/ls1021aqds/ls1021aqds.c
This patch rewrites MMU translation table entries. To start, all table
entries are written as invalid, then device-ngnrnr and normal are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang alison.w...@freescale.com
Signed-off-by: York Sun york
From: Zhichun Hua zhichun@freescale.com
For ARMv8, outer shareable is 0b10, inner shareable is 0b11 at bit
position [13:12] of TCR_ELx register.
Signed-off-by: Zhichun Hua zhichun@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/include/asm/armv8/mmu.h | 4 ++--
From: Zhichun Hua zhichun@freescale.com
When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.
Signed-off-by: Zhichun Hua zhichun@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html
Signed-off-by: Chris Kilgour tec...@whiterocker.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/cpu.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/cpu
This patch rewrites MMU translation table entries to achieve:
a) Start with all table entries as invalid.
b) Rewrite the table entries as device-ngnrne for cache-inhibit
access.
c) Rewrite the table entries as normal for cache-enabled access.
Signed-off-by: Alison Wang alison.w...@freescale.com
the issue.
[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html
Signed-off-by: Chris Kilgour tec...@whiterocker.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/timer.c| 3 ++-
arch/arm/include/asm/arch-ls102xa
Acked-by: Alison Wang alison.w...@freescale.com
--
View this message in context:
http://u-boot.10912.n7.nabble.com/PATCH-ls1021atwr-added-deep-sleep-support-in-uboot-tp214734p219806.html
Sent from the U-Boot mailing list archive at Nabble.com.
___
U
Acked-by: Alison Wang alison.w...@freescale.com
Zhao Chenhui-3 wrote
Program the external regulator to switch off voltage in deep sleep.
Signed-off-by: Chenhui Zhao lt;
chenhui.zhao@
gt;
---
board/freescale/ls1021atwr/ls1021atwr.c | 34
+
1 file
to the value of 0x. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.
For the same reason, initrd_high is set to the value of 0x too.
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
include/configs/ls1021
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ar
As the environment variables "serial#" and "ethaddr" need to be
overwriten by the users, CONFIG_ENV_OVERWRITE is defined to disable
the write protection. Anybody can change or delete these parameters.
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
include/co
-by: Alison Wang <alison.w...@freescale.com>
---
include/configs/ls1021aqds.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d19b1e3..562e78f 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/c
-by: Alison Wang <alison.w...@freescale.com>
---
include/configs/ls1021aqds.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 562e78f..489db9c 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/c
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.
Signed-off-by: York Sun <york...@freescale.com>
Signed-off-by: Alison Wang <alison.w...@freescale.com>
Reported-by: Zhichun
to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
Changes in v2:
- Fix checkpatch warnings about line over 80 characters.
Makefile | 4
This patch rewrites MMU translation table entries to achieve:
a) Start with all table entries as invalid.
b) Rewrite the table entries as device-ngnrne for cache-inhibit
access.
c) Rewrite the table entries as normal for cache-enabled access.
Signed-off-by: Alison Wang alison.w...@freescale.com
To improve eTSEC performance on LS1021A Rev2.0,
snooping of all transmit frames from memory and
all transmit BD memory accesses in enabled.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
include/tsec.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/tsec.h b/include
On LS1021A Rev2.0, OCRAM's security level needs to be changed to
non-secure access for SD boot. This patch will allow OCRAM
access permission as R/W in SPL.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
board/freescale/ls1021aqds/ls1021aqds.c | 178
Pointer 'reg' returned from call to function 'fdt_getprop' may be
NULL, will be passed to function and may be dereferenced there by
passing argument 1 to function 'of_read_number'. So check pointer
'reg' first.
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
arch/arm/cpu/arm
to the value read from SCTLR, it causes CR_M bit is not set.
Then MMU is not enabled, the access to VA for PCIE fails.
This patch will add the missing volatile for reading SCTLR register.
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
arch/arm/include/asm/system.h | 2 +-
1 file c
to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.w...@freescale.com>
---
Makefile | 4
board/freescale/ls1021atwr/MAINTAINERS | 3 ++-
board/fre
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison
C.
- Support to call armv8_switch_to_el2_m and armv8_switch_to_el1_m.
Alison Wang (2):
armv8: Support loading 32-bit OS in AArch32 execution state
armv8: fsl-layerscape: SMP support for loading 32-bit OS
arch/arm/Kconfig | 6
arch/arm/cpu/armv8/fsl-layersca
ed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Changes in v4:
- Correct config ARM64_SUPPORT_AARCH32.
- Omit arch and ftaddr arguments.
- Rename "xreg5" to "tmp".
- Use xxx_RES1 to combine all RES1 fields in xxx reg
ed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Changes in v3:
- Comments the functions and the arguments.
- Rename the real parameters.
- Use the macros instead of the magic values.
- Remove the redundant codes.
- Clean
to switch to AArch64 EL1 or AArch32 SVC.
- Support to call armv8_switch_to_el2_m and armv8_switch_to_el1_m.
Alison Wang (2):
armv8: Support loading 32-bit OS in AArch32 execution state
armv8: fsl-layerscape: SMP support
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison
Increase the kernel size supported for LS1021A platform. Define
CONFIG_SYS_BOOTM_LEN to 64M.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
include/configs/ls1021aqds.h | 2 ++
include/configs/ls1021atwr.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/include/configs/ls1021
The initialization for smmu and stream id is moved into the common soc
code.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
arch/arm/cpu/armv7/ls102xa/soc.c| 48 +
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h | 2 ++
board/freescale/ls10
to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig
is used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
board/freescale/ls1021aqds/MAINTAINERS | 3 ++-
board/freescale/ls1021aqds/ls1021aqds.c| 4 ++--
board/fre
In general, a carriage return needs to execute before a line feed.
The patch is to change serial DM driver based on this rule.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
drivers/serial/serial-uclass.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/d
As the compatible property values for QSPI and DSPI dts nodes
are changed in kernel, FSL_QSPI_COMPAT and FSL_DSPI_COMPAT
need to be updated too.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
arch/arm/include/asm/arch-ls102xa/config.h | 4 ++--
1 file changed, 2 insertions(+), 2 del
In general, a carriage return needs to execute before a line feed.
The patch is to change some serial drivers based on this rule, such
as serial_mxc.c, serial_pxa.c, serial_s3c24x0.c and usbtty.c.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
drivers/serial/serial_mxc.c
to be called in ar8035_config() to enable and restart
auto-negotiation.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
drivers/net/phy/atheros.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index ba57b1a..e57c412 100644
--- a/d
on the monitor.
The patch is to disabled CONFIG_DM_STDIO for LCD/HDMI display.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
include/configs/ls1021aqds.h | 4
include/configs/ls1021atwr.h | 4
2 files changed, 8 insertions(+)
diff --git a/include/configs/ls1021aqds.h b/include/c
As QSPI driver is supported in ls1021atwr_sdcard_qspi_defconfig,
CONFIG_MTD needs to be enabled for SPI-NOR with MTD uclass.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
configs/ls1021atwr_sdcard_qspi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/c
As QSPI driver is supported in ls1021aqds_sdcard_qspi_defconfig, SPI-NOR
with MTD uclass, CONFIG_MTD_DATAFLASH and new flash vendor config
CONFIG_SPI_NOR_SPANSION need be enabled.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
configs/ls1021aqds_sdcard_qspi_defconfig | 7 +--
CONFIG_SYS_CONSOLE_IS_IN_ENV needs to be enabled, so we could set stdout
environment variable to specify the vga for the console output when
LCD/HDMI is connected to the boards.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
include/configs/ls1021aqds.h | 1 +
include/configs/ls1021
In general, a carriage return needs to execute before a line feed. The
patch is to change serial DM driver serial-uclass.c based on this rule.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
drivers/serial/serial-uclass.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
As the handling for carriage return and line feed is done in the common
DM driver serial-uclass.c, such handling in some serial DM drivers is
duplicated and need to be removed.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
drivers/serial/serial_arc.c| 3 ---
drivers/
In general, a carriage return needs to execute before a line feed.
The patch is to change some serial drivers based on this rule, such
as serial_mxc.c, serial_pxa.c, serial_s3c24x0.c and usbtty.c.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
drivers/serial/serial_mxc.c
This serial is to fix the error handling for carriage return and line feed.
Alison Wang (3):
dm: serial-uclass: Move a carriage return before a line feed
serial: Move carriage return before line feed for some serial
For LS1021A Secure Boot, SPARE2 register is used and modified by the
IBR. To avoid the conflict, SPARE4 is used instead of SPARE2 to store
the entry point of kernel. This patch is to get the entry point of
kernel from SPARE4 instead of SPARE2.
Signed-off-by: Alison Wang <alison.w...@nxp.
As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit
70e21b06425ad6e1e90931333a704a600941cfff, the workaround to flush dcache
is unnecessary and will be removed.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
arch/a
. armv8_switch_to_el2_m is used
to switch to AArch64 EL2 or AArch32 Hyp.
- armv8_switch_to_el1_aarch32() is removed. armv8_switch_to_el1_m is used
to switch to AArch64 EL1 or AArch32 SVC.
Alison Wang (2):
armv8: Support loading 32
ed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Changes in v2:
- armv8_switch_to_el2_aarch32() is removed. armv8_switch_to_el2_m is used
to switch to AArch64 EL2 or AArch32 Hyp.
- armv8_switch_to_el1_aarch32() is removed. armv8_switc
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison
ed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
arch/arm/cpu/armv8/transition.S | 100
arch/arm/include/asm/system.h | 2 +
arch/arm/lib/bootm.c| 20 +++-
.
Alison Wang (2):
armv8: Support loading 32-bit OS in AArch32 execution state
armv8: fsl-layerscape: SMP support for loading 32-bit OS
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 21 +++
arch/arm/cpu/armv8/fsl-layerscape
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison
In defconfig, enable CONFIG_OF_LIBFDT to support booting DT linux kernel
and enable COFNIG_FIT to support FIT image.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
configs/ls1021aqds_ddr4_nor_defconfig| 3 +++
configs/ls1021aqds_ddr4_nor_lpuart_defconfig | 3 +++
c
rmv8_switch_to_el1_m.
----
Alison Wang (2):
armv8: Support loading 32-bit OS in AArch32 execution state
armv8: fsl-layerscape: SMP support for loading 32-bit OS
arch/arm/Kconfig | 6 ++
arch/arm/cpu/armv8/fsl-layersca
ed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Changes in v5:
- Modified armv8_switch_to_el2(). It will always jump to ep when switching to
AArch64 or AArch32 modes.
Changes in v4:
- Correct config ARM64_SUPPORT_AARCH32.
- Om
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison
As CONFIG_ARMV8_SWITCH_TO_EL1 is not used now, this patch is to remove
CONFIG_ARMV8_SWITCH_TO_EL1 and the corresponding functions.
Signed-off-by: Alison Wang <alison.w...@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 13
arch/arm/cpu/armv8/start.S
@nxp.com>; Shaohui
> Xie <shaohui@nxp.com>; Alison Wang <b18...@freescale.com>
> Subject: [PATCH V3 13/19] serial: lpuart: restructure lpuart driver
>
> Drop CONFIG_LPUART_32B_REG.
> Move the register structure to a common file include/fsl_lpuart.h
> D
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.w...@nxp.
> On 01/13/2017 10:36 AM, Alison Wang wrote:
> >> On 01/13/2017 09:23 AM, Alison Wang wrote:
> >>>>> Am 13.01.2017 um 08:50 schrieb Alison Wang <b18...@freescale.com>:
> >>>>>
> >>>>> For 64-bit kernel, there is a warning abo
> On 16 January 2017 at 08:34, Alexander Graf <ag...@suse.de> wrote:
> >
> >
> > On 16/01/2017 07:16, Alison Wang wrote:
> >>
> >> For 64-bit kernel, there is a warning about x1-x3 nonzero in
> >> violation of boot proto
> On 16/01/2017 07:16, Alison Wang wrote:
> > For 64-bit kernel, there is a warning about x1-x3 nonzero in
> violation
> > of boot protocol. To fix this issue, input argument 4 is added for
> > armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4
> will
&g
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.w...@nxp.
Spin-table method is used for secondary cores to load 32-bit OS. The
architecture information will be got through checking FIT image and
saved in the os_arch element of spin-table, then the secondary cores
will check os_arch and jump to 32-bit OS or 64-bit OS automatically.
Signed-off-by: Alison
ed-off-by: Alison Wang <alison.w...@nxp.com>
Signed-off-by: Chenhui Zhao <chenhui.z...@nxp.com>
---
Changes in v6:
- Modified armv8_switch_to_el1(). It will always jump to ep when switching to
AArch64 or AArch32 modes.
- Make other platforms compatible with the new a
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