[U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

help Provide Andes Technology AndeStar V5 families specific cache support. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 7/7] riscv: ae350: enable SMP

From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 44cb302..5e682b6 100644 ---

[U-Boot] [PATCH v3 6/7] riscv: dts: ae350 support SMP

From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- V3: - Fix some mis-alignments. - Recovery isa string of CPU1. arch/riscv/dts/ae350_32.dts | 81 + arch/riscv/dts/ae350_64.dts | 81 + 2

[U-Boot] [PATCH v3 4/7] riscv: ax25: Add platform-specific Kconfig options

if RISCV_MMODE + imply ANDES_PLMT if RISCV_MMODE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. -- 2.7.4 ___ U-Boot mailing list U-Boot

[U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

5 files changed, 67 insertions(+) create mode 100644 arch/riscv/lib/andes_plmt.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 511768b..ae8ff7b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -118,6 +118,15 @@ config ANDES_PLIC The Andes PLIC block holds memory

[U-Boot] [PATCH v3 3/7] riscv: ae350: disable ATCPIT100 timer

From: Rick Chen Disable ATCPIT100 SoC timer and replace by PLMT. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- configs/ae350_rv32_defconfig | 1 - configs/ae350_rv64_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/ae350_rv32_defconfig

[U-Boot] [PATCH v3 0/7] AE350 SMP support RISC-V

riscv: ax25: Add platform-specific Kconfig options riscv: ax25: Andes specific cache shall only support in M-mode riscv: dts: ae350 support SMP riscv: ae350: enable SMP arch/riscv/Kconfig | 18 ++ arch/riscv/cpu/ax25/Kconfig | 7 +++ arch/riscv/dts/ae350_32

[U-Boot] [PATCH v3 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

The SiFive CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. +config ANDES_PLIC + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The Andes PLIC block holds memory

[U-Boot] [PATCH v2 6/7] riscv: dts: ae350 support SMP

From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350_32.dts | 81 + arch/riscv/dts/ae350_64.dts | 47 +++--- 2 files changed, 101 insertions(+), 27 deletions(-) diff --git

[U-Boot] [PATCH v2 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

help Provide Andes Technology AndeStar V5 families specific cache support. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v2 4/7] riscv: ax25: Add platform-specific Kconfig options

if RISCV_MMODE + imply ANDES_PLMT if RISCV_MMODE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. -- 2.7.4 ___ U-Boot mailing list U-Boot

[U-Boot] [PATCH v2 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

arch/riscv/lib/andes_plmt.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 511768b..ae8ff7b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -118,6 +118,15 @@ config ANDES_PLIC The Andes PLIC block holds memory-mapped claim and pending registers associated

[U-Boot] [PATCH v2 1/7] riscv: Add a SYSCON driver for Andestech's PLIC

and timer interrupts. +config ANDES_PLIC + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The Andes PLIC block holds memory-mapped claim and pending registers + associated with software interrupt. + config RISCV_RDTIME

[U-Boot] [PATCH v2 7/7] riscv: ae350: enable SMP

From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 44cb302..5e682b6 100644 ---

[U-Boot] [PATCH v2 3/7] riscv: ae350: disable ATCPIT100 timer

From: Rick Chen Disable ATCPIT100 SoC timer and replace by PLMT. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- configs/ae350_rv32_defconfig | 1 - configs/ae350_rv64_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/ae350_rv32_defconfig

[U-Boot] [PATCH v2 0/7] AE350 SMP support RISC-V

PLIC riscv: Add a SYSCON driver for Andestech's PLMT riscv: ae350: disable ATCPIT100 timer riscv: ax25: Add platform-specific Kconfig options riscv: ax25: Andes specific cache shall only support in M-mode riscv: dts: ae350 support SMP riscv: ae350: enable SMP arch/riscv/Kconfig

[U-Boot] [PATCH 9/9] riscv: ae350: enable SMP

From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 44cb302..5e682b6 100644 --- a/board/AndesTech/ax25-ae350/Kconfig

[U-Boot] [PATCH 8/9] riscv: dts: ae350 support SMP.

From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350_32.dts | 81 + arch/riscv/dts/ae350_64.dts | 47 +++--- 2 files changed, 101 insertions(+), 27 deletions(-) diff --git

[U-Boot] [PATCH 6/9] riscv: ax25: Add platform-specific Kconfig options

NDS_PLMT if RISCV_MMODE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https

[U-Boot] [PATCH 5/9] riscv: ae350: disable ATCPIT100 timer

From: Rick Chen Disable ATCPIT100 SoC timer and replace by PLMT. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ae350_rv32_defconfig | 1 - configs/ae350_rv64_defconfig | 1 - 2 files changed, 2 deletions(-) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig

[U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.

/Kconfig index 0901709..e030df4 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -14,6 +14,7 @@ if RISCV_NDS config RISCV_NDS_CACHE bool "AndeStar V5 families specific cache support" + depends on RISCV_MMODE help Provide Andes

[U-Boot] [PATCH 3/9] riscv: Add a SYSCON driver for Andestech's PLMT

arch/riscv/lib/nds_plmt.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index fef11dd..697892e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -118,6 +118,15 @@ config NDS_PLIC The Andes PLIC block holds memory-mapped claim and pending registers associated

[U-Boot] [PATCH 4/9] riscv: ae350: initialize PLIC

From: Rick Chen Initialize PLIC when ae350 board startup. Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/ax25-ae350.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c

[U-Boot] [PATCH 2/9] riscv: Add a SYSCON driver for Andestech's PLIC

interrupts. +config NDS_PLIC + bool + depends on RISCV_MMODE + select REGMAP + select SYSCON + help + The Andes PLIC block holds memory-mapped claim and pending registers + associated with software interrupt. + config RISCV_RDTIME bool

[U-Boot] [PATCH 1/9] riscv: ax25: Create a simple-bus driver for the soc node

From: Rick Chen To enumerate devices on the /soc/ node, create a "simple-bus" driver to match "andestech,riscv-ae350-soc". Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/cpu/ax25/cpu.c | 16 1 file changed, 16 insertions(+) diff --git a/arch/riscv/cpu/ax25/cpu.c

[U-Boot] [PATCH 0/9] AE350 SMP support RISC-V

: Andes specific cache shall only support in M-mode. riscv: dts: ae350 support SMP. riscv: ae350: enable SMP arch/riscv/Kconfig | 18 +++ arch/riscv/cpu/ax25/Kconfig | 7 +++ arch/riscv/cpu/ax25/cpu.c | 16 +++ arch/riscv/dts/ae350_32.dts

[U-Boot] [PATCH] nds32: dts: Fix mmc node compatible string

From: Rick Chen In the two commits: cf3922dddc44a968685b535f2af195f1e51f4a7b mmc: ftsdc010_mci: Sync compatible with DT mmc node c14e90e8445e7b1c3531b4bdeb778c47bd6570eb riscv: dts: Sync DT with Linux Kernel ftsdc010_mci's compatible has been modified as "andestech,atfsdc010" for RISC-V

[U-Boot] [PATCH 4/4] nds32: Fix boot fail issue when build with elf-mculib.

From: Rick Chen Add -mcmodel=large can let elf-mculib have the same default behavior just like linux-glibc. And it help to pass U-Boot booting sequence. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/nds32/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[U-Boot] [PATCH 3/4] nds32: Generate SW fpu instruction.

From: Rick Chen Force it to generate SW fup instruction. It help to avoid bugs when running on no-HW-fpu board, but compile with v3f which support HW fpu instruction. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/nds32/config.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

[U-Boot] [PATCH 2/4] nds32: Remove gcc unused option

From: Rick Chen -G0 is an old option, not support now, So remove it. It can help to fix compile error when build with nds32 pre-build toolchain. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/nds32/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[U-Boot] [PATCH 1/4] .travis.yml: Support nds32 prebuilt toolchain

From: Rick Chen Download nds32 prebuild toolchain from github which is base on gcc 8.0.1 version for regression. Signed-off-by: Rick Chen Cc: Greentime Hu --- .travis.yml | 9 + 1 file changed, 9 insertions(+) diff --git a/.travis.yml b/.travis.yml index 321fd79..4b7c696 100644 ---

[U-Boot] [PATCH 0/4] Support nds32 pre-build toolchain

From: Rick Chen 1. Support nds32 pre-build toolcahin for buildman. 2. Fix some bugs about fpu and toolchain issues. Rick Chen (4): .travis.yml: Support nds32 prebuilt toolchain nds32: Remove gcc unused option nds32: Generate SW fpu instruction. nds32: Fix boot fail issue when build with

[U-Boot] [PATCH v4 2/2] doc: README.ae350: Sync for ax25-ae350 rename

From: Rick Chen Rename ax25-ae350 as ae350_rv[32|64] for 32 or 64 bit. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- doc/README.ae350 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/README.ae350 b/doc/README.ae350 index fe75b80..189a6b7 100644

[U-Boot] [PATCH v4 1/2] riscv: configs: Rename ax25-ae350 defconfig

From: Rick Chen Remove cpu name from the defconfig naming. Because other cpus maybe run on AE350 platform. So only use platfrom name in defconfig naming will be better. Also sync MAINTAINERS: Rename a25-ae350_32_defconfig as ae350_rv32_defconfig ax25-ae350_64_defconfig as ae350_rv64_defconfig

[U-Boot] [PATCH v4 0/2] Rename ax25-ae350 defconfig

From: Rick Chen Remove cpu name from the defconfig naming. Because other cpus maybe run on AE350 platform. So only use platfrom name in defconfig naming will be better. Changes since v3: - squashed [PATCH v3 2/3] MAINTAINERS: Sync for ax25-ae350 rename into [PATCH v3 1/3] riscv:

[U-Boot] [PATCH v3 3/3] doc: README.ae350: Sync for ax25-ae350 rename

From: Rick Chen Rename ax25-ae350 as ae350_rv[32|64] for 32 or 64 bit. Signed-off-by: Rick Chen Cc: Greentime Hu --- doc/README.ae350 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/README.ae350 b/doc/README.ae350 index fe75b80..189a6b7 100644 --- a/doc/README.ae350

[U-Boot] [PATCH v3 2/3] MAINTAINERS: Sync for ax25-ae350 rename

From: Rick Chen Rename a25-ae350_32_defconfig as ae350_rv32_defconfig ax25-ae350_64_defconfig as ae350_rv64_defconfig Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/MAINTAINERS | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git

[U-Boot] [PATCH v3 1/3] riscv: configs: Rename ax25-ae350 defconfig

From: Rick Chen Remove cpu name from the defconfig naming. Because other cpus maybe run on AE350 platform. So only use platfrom name in defconfig naming will be better. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- configs/a25-ae350_32_defconfig | 36

[U-Boot] [PATCH v3 0/3] Rename ax25-ae350 defconfig

From: Rick Chen Remove cpu name from the defconfig naming. Because other cpus maybe run on AE350 platform. So only use platfrom name in defconfig naming will be better. Changes since v2: - Fix travis failure case 6.51 Checkfor configs without MAINTAINERS entry.

[U-Boot] [PATCH v2] riscv: configs: Rename ax25-ae350 defconfig

From: Rick Chen Remove cpu name from the defconfig naming. Because other cpus maybe run on AE350 platform. So only use platfrom name in defconfig naming will be better. Signed-off-by: Rick Chen Cc: Greentime Hu --- Changes since v1: Use git format-patch �VM to show delta when rename. ---

[U-Boot] [PATCH] riscv: configs: Rename ax25-ae350 defconfig

From: Rick Chen Remove cpu name from the defconfig naming. Because other cpus maybe run on AE350 platform. So only use platfrom name in defconfig naming will be better. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/a25-ae350_32_defconfig | 36

[U-Boot] [PATCH v3] riscv: cache: Implement i/dcache [status, enable, disable]

7 @@ +config RISCV_NDS + bool "AndeStar V5 ISA support" + default n + help + Say Y here if you plan to run U-Boot on AndeStar v5 + platforms and use some specific features which are + provided by Andes Technology AndeStar V5 Fam

[U-Boot] [PATCH v2] riscv: cache: Implement i/dcache [status, enable, disable]

default n + help + Say Y here if you plan to run U-Boot on AndeStar v5 + platforms and use some specific features which are + provided by Andes Technology AndeStar V5 Families. + endmenu diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/ax25/Make

[U-Boot] [PATCH] riscv: ax25-ae350: Pass dtb address to u-boot with a1 register

From: Rick Chen ax25-ae350 use CONFIG_OF_BOARD which allow the board to override the fdt address. And prior_stage_fdt_address offer a temporary memory address to keep the dtb address which was passed from loader(gdb) to u-boot with a1. Signed-off-by: Rick Chen Cc: Greentime Hu ---

[U-Boot] [PATCH] riscv: cache: Implement i/dcache [status, enable, disable]

pport" + def_bool n + help + Say Y here if you plan to run U-Boot on AndeStar v5 + platforms and use some specific features which are + provided by Andes Technology AndeStar V5 Families. + endmenu diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/

[U-Boot] [PATCH] board: ax25-ae350: Print board information.

From: Rick Chen Add to print board and bit information message. Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/ax25-ae350.c | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c b/board/AndesTech/ax25-ae350/ax25-ae350.c index

[U-Boot] [PATCH 2/2] riscv: dts: Add ae350_32.dts for 32 bit

From: Rick Chen Add ae350_32.dts for 32 bit. And also rename ae350.dts to ae350_64.dts for 64 bit. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts| 229 arch/riscv/dts/ae350_32.dts | 229

[U-Boot] [PATCH 1/2] riscv: configs: Separate ax25-ae350 for 32/64 bit.

From: Rick Chen Separate ax25-ae350 from one to two for 32 and 64 bit individually. And also select different dts for 32 and 64 bit. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ax25-ae350-32_defconfig | 33 + configs/ax25-ae350-64_defconfig | 34

[U-Boot] [PATCH] riscv: dts: Sync to Linux Kernel ae350 dts.

From: Rick Chen Use same dts to boot U-Boot and Kernel. Following are the change notes : 1 Remove early printk bootargs. 2 Timer frequency are changed to 60MHz. 3 Add dma, snd, lcd, virtio nodes which are used in kernel drivers. They does not been used by U-Boot. 4 Change spi irq from 3 to 4.

[U-Boot] [PATCH] travis.yml: Support RISC-V 64-bit

From: Rick Chen Fix riscv: ax25-ae350 build fail problem https://travis-ci.org/trini/u-boot/jobs/385147373 ... Building current source for 1 boards (1 thread, 2 jobs per thread) riscv: + ax25-ae350 +arch/riscv/cpu/ax25/start.S: Assembler messages: +arch/riscv/cpu/ax25/start.S:48: Error:

[U-Boot] [PATCH 2/4] riscv: dts: Support cfi flash

From: Rick Chen Add nor node for cfi-flash driver and smc node for smc(aftsmc020) controller. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts | 12

[U-Boot] [PATCH 4/4] mtd: ftsmc020: Drop unsed code

From: Rick Chen ftsmc020_init is not used anymore. So it can be removed. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- drivers/mtd/Makefile | 1 - drivers/mtd/ftsmc020.c | 38

[U-Boot] [PATCH 3/4] board: ax25-ae350: Support cfi flash

From: Rick Chen Add smc_init() to get register base from dts and deal with atfsmc020 controler initialzation job. Write protect is enabled by default. So WP shall be disabled when startup, then cfi flash can be detected and erasing and writing can be executed. Adp-ae3xx and

[U-Boot] [PATCH 1/4] configs: ax25-ae350: Support cfi flash

From: Rick Chen Enable cfi flash driver and setup flash parameters to support parallel nor flash which type is JS28F00A-M29EWH. Verification: Size detection, data read, erase and write are all ok. Signed-off-by: Rick Chen Signed-off-by: Rick Chen

[U-Boot] [PATCH 2/2] mmc: ftsdc010_mci: Sync compatible with DT mmc node

From: Rick Chen The compatible string of ftsdc010_mci.c is different from the mmc driver in Linux Kernel. Modify it for consistency. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu ---

[U-Boot] [PATCH 1/2] riscv: dts: Sync DT with Linux Kernel

From: Rick Chen Use same dts to boot U-Boot and RISC-V Linux Kernel v4.16-rc2 in ax25-ae350 platform. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/ae350.dts | 204

[U-Boot] [PATCH 3/3] net: ftmac100: Fix compiler warning

From: Rick Chen Fix warnings as below when compile in 64-bit. warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu

[U-Boot] [PATCH 2/3] spi: atcspi200: Fix compiler warning

From: Rick Chen Fix warning as below when compile in 64-bit. warning: format '%u' expects argument of type 'unsigned int', but argument 6 has type 'size_t {aka long unsigned int} Signed-off-by: Rick Chen Signed-off-by: Rick Chen

[U-Boot] [PATCH 1/3] configs: ax25-ae350: Set 64-bit as default configuration

From: Rick Chen Set 64-bit as default configuration for ax25-ae350. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ax25-ae350_defconfig | 1 + 1 file changed, 1 insertion(+)

[U-Boot] [PATCH 4/4] doc: ae250: Rename as ae350

s(-) create mode 100644 doc/README.AX25 delete mode 100644 doc/README.NX25 delete mode 100644 doc/README.ae250 create mode 100644 doc/README.ae350 diff --git a/doc/README.AX25 b/doc/README.AX25 new file mode 100644 index 000..7a607dd --- /dev/null +++ b/doc/README.AX25 @@ -0,0 +1,46 @@ +AX25

[U-Boot] [PATCH 3/4] configs: nx25-ae250:Rename as ax25-ae350

TS=y diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h new file mode 100644 index 000..a90c75a --- /dev/null +++ b/include/configs/ax25-ae350.h @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <r...@andes

[U-Boot] [PATCH 2/4] board: nx25-ae250: Rename as ax25-ae350

/ax25-ae350/Makefile b/board/AndesTech/ax25-ae350/Makefile new file mode 100644 index 000..b8bd8ec --- /dev/null +++ b/board/AndesTech/ax25-ae350/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology Corporation <r...@andestech.com&g

[U-Boot] [PATCH 1/4] riscv: cpu: nx25: Rename as ax25

From: Rick Chen <r...@andestech.com> Andes has rearranged the product combinations. nx25 and ax25 both are RISC-V architecture cpu core. But ax25 has MMU unit inside, and nx25 is not. Cpu nx25 and platform ae250 are arranged in pairs. Cpu ax25 and platform ae350 are arranged in

[U-Boot] [PATCH] riscv: ae250: Support DT provided by the board at runtime

From: Rick Chen Enable CONFIG_OF_BOAD to support delivery dtb to u-boot at run time instead of embedded. There are two methods to delivery dtb. 1 Pass from loader: When u-boot boot from RAM, gdb or loader can pass dtb via a2 to u-boot dynamically. Of course gdb or

[U-Boot] [PATCH 7/7] configs: Drop CONFIG_MMC_NDS32

From: Rick Chen Remove CONFIG_MMC_NDS32 from the three config (adp-ae3xx_defconfig, adp-ag101p_defconfig, nx25-ae250_defconfig). Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu ---

[U-Boot] [PATCH 5/7] mmc: ftsdc010: Migrate CONFIG_FTSDC010_SDIO to Kconfig

From: Rick Chen Convert CONFIG_FTSDC010_SDIO to Kconfig. So CONFIG_FTSDC010_SDIO can also be removed from config_whitelist.txt. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu ---

[U-Boot] [PATCH 6/7] mmc: ftsdc010: Merge nds32_mmc to ftsdc010

rivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index 5506ef4..9de3a15 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -4,23 +4,63 @@ * (C) Copyright 2010 Faraday Technology * Dante Su <dant...@faraday-tech.com> * + * Copyright 2018 Andes Technology, Inc.

[U-Boot] [PATCH 4/7] Drop CONFIG_FTSDC010_NUMBER

From: Rick Chen CONFIG_FTSDC010_NUMBER was not used anymore, can be removed now. So CONFIG_FTSDC010_NUMBER can also be removed from config_whitelist.txt. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu

[U-Boot] [PATCH 3/7] Drop CONFIG_FTSDC010_BASE

From: Rick Chen After drop non-dm code of ftsdc010, the sd register base definition can be droppped now. So CONFIG_FTSDC010_BASE and CONFIG_FTSDC010_BASE_LIST both can be removed from config_whitelist.txt Signed-off-by: Rick Chen Signed-off-by: Rick

[U-Boot] [PATCH 2/7] board: Drop ftsdc010 non-dm code

From: Rick Chen Remove board_mmc_init() in adp-ag101p, adp-ae3xx and nx25-ae250 boards. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/adp-ae3xx/adp-ae3xx.c | 11

[U-Boot] [PATCH 1/7] mmc: ftsdc010: Drop non-dm code

From: Rick Chen Only three defconfig(adp-ag101p_defconfig, adp-ae3xx_defconfig, nx25-ae250_defconfig) set CONFIG_FTSDC010=y. And they all also enable CONFIG_DM_MMC. So the non-dm code of ftsdc010 can be dropped now. Signed-off-by: Rick Chen

[U-Boot] [PATCH 1/3] mmc: ftsdc010: Support High-Speed mode

From: Rick Chen <r...@andestech.com> ftsdc010 dm driver has been disable High-Speed mode as default to work around Andes AE3XX platform's problem, because of it does not support High-Speed mode in commit id 73cd56b2df213c629191139e5c6705e069b6214f. But other platforms or SoCs maybe s

[U-Boot] [PATCH 3/3] nds32: dts: AG101P support sd High-Speed mode

From: Rick Chen Enable High-Speed mode with cap-sd-highspeed in dts Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- arch/nds32/dts/ag101p.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/nds32/dts/ag101p.dts

[U-Boot] [PATCH 2/3] riscv: dts: AE250 support sd High-Speed mode

From: Rick Chen Enable High-Speed mode with cap-sd-highspeed in dts. Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- arch/riscv/dts/ae250.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts/ae250.dts

[U-Boot] [PATCH 4/4] doc: ae250: Describe riscv-linux booting via u-boot

From: Rick Chen Simply record riscv-linux booting steps and messages from bbl via u-boot on QEMU in README.ae250. Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- doc/README.ae250 | 148

[U-Boot] [PATCH 3/4] tools: mkimage: Support RISC-V arch

From: Rick Chen Add riscv uimage arch to support riscv-linux booting. It can Convert riscv-linux to image which can be booted by bootm command. Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- common/image.c | 1 + 1 file

[U-Boot] [PATCH 2/4] riscv: bootm: Remove ATAGS

From: Rick Chen ATAGS is not supported and will be replaced by DT in riscv-linux. So can be removed now. Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- arch/riscv/include/asm/bootm.h | 49 ---

[U-Boot] [PATCH 1/4] riscv: bootm: Support to boot riscv-linux

From: Rick Chen riscv-linux should use BBL (Berkeley bootloader) for loading the Linux kernel. U-Boot can play as FSBL(first stage bootloader) to boot BBL and riscv-linux. In BBL's init_first_hart(), it will pass dtb with a1. So implement bootm to pass arguments to BBL

[U-Boot] [PATCH 5/5] riscv: checkpatch: Fix static const char * array declarations

From: Rick Chen It is reported by checkpatch.pl WARNING: static const char * array should probably be static const char * const Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- arch/riscv/lib/interrupts.c | 2 +- 1 file

[U-Boot] [PATCH 4/5] riscv: checkpatch: Fix missing a blank line after declarations

From: Rick Chen It is reported by checkpatch.pl WARNING: Missing a blank line after declarations. Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- arch/riscv/lib/bootm.c | 4 ++-- 1 file changed, 2 insertions(+), 2

[U-Boot] [PATCH 3/5] riscv: checkpatch: Fix alignment should match open parenthesis

From: Rick Chen It is reported by checkpatch.pl. CHECK: Alignment should match open parenthesis Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- arch/riscv/include/asm/io.h | 23 ++-

[U-Boot] [PATCH 2/5] riscv: checkpatch: Fix use of volatile

From: Rick Chen It is reported by checkpatch.pl WARNING: Use of volatile is usually wrong: see Documentation/process/volatile-considered-harmful.rst Signed-off-by: Rick Chen Signed-off-by: Rick Chen ---

[U-Boot] [PATCH 1/5] riscv: checkpatch: Fix Macro argument reuse

From: Rick Chen It is CHECK reported by checkpatch.pl CHECK: Macro argument reuse 'PTE' - possible side-effects? Signed-off-by: Rick Chen Signed-off-by: Rick Chen --- arch/riscv/include/asm/encoding.h| 16 +++-

[U-Boot] [PATCH] spi: atcspi200: Full dm conversion

From: Rick Chen atcspi200_spi now support dt along with platform data. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- drivers/spi/atcspi200_spi.c | 134

[U-Boot] [PATCH] travis.yml: Support RISC-V

From: Rick Chen Enable travis-ci support with a link having built. Signed-off-by: Chih-Mao Chen Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu ---

[U-Boot] [PATCH v2 08/12] riscv: defconfig: Add nx25-ae250 defconfig to support RISC-V

From: Rick Chen Add nx25-ae250 default configuration for RISC-V Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- configs/nx25-ae250_defconfig | 36

[U-Boot] [PATCH v2 12/12] riscv: doc: Add relative doc to describe RISC-V

pointer to the global data + Memory Management: -- diff --git a/doc/README.NX25 b/doc/README.NX25 new file mode 100644 index 000..9f054e5 --- /dev/null +++ b/doc/README.NX25 @@ -0,0 +1,46 @@ +NX25 is Andes CPU IP to adopt RISC-V architecture. + +Features + + +C

[U-Boot] [PATCH v2 11/12] riscv: Modify generic codes to support RISC-V

From: Rick Chen Support common commands bdinfo and image format, also modify common generic flow for RISC-V. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu Reviewed-by: Tom Rini

[U-Boot] [PATCH v2 10/12] riscv: Support standalone

+ 2 files changed, 53 insertions(+) create mode 100644 examples/standalone/riscv.lds diff --git a/examples/standalone/riscv.lds b/examples/standalone/riscv.lds new file mode 100644 index 000..7d8c482 --- /dev/null +++ b/examples/standalone/riscv.lds @@ -0,0 +1,41 @@ +/* + * Copyright (C) 201

[U-Boot] [PATCH v2 07/12] riscv: configs: Add nx25-ae250.h to support RISC-V

5-ae250.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <r...@andestech.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * CPU and Board Configuration Options + */ +#define CONFIG

[U-Boot] [PATCH v2 09/12] riscv: tools: Prelink u-boot

T_OBJS) fdtgrep.o diff --git a/tools/prelink-riscv.c b/tools/prelink-riscv.c new file mode 100644 index 000..632d2da --- /dev/null +++ b/tools/prelink-riscv.c @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2017 Andes Technology + * Chih-Mao Chen <cmc...@andestech.com> + * + * SPDX-License-I

[U-Boot] [PATCH v2 04/12] riscv: nx25: include: Add header files to support RISC-V

scv/include/asm/bitops.h @@ -0,0 +1,172 @@ +/* + * Copyright 1995, Russell King. + * Various bits and pieces copyrights include: + * Linus Torvalds (test_bit). + * + * Copyright (C) 2017 Andes Technology Corporation + * Rick Chen, Andes Technology Corporation <r...@andestech.com> + * + * bi

[U-Boot] [PATCH v2 05/12] riscv: Add Kconfig to support RISC-V

32BIT + bool + +config 64BIT + bool + +endmenu diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile new file mode 100644 index 000..09d24db --- /dev/null +++ b/arch/riscv/Makefile @@ -0,0 +1,11 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen, Andes Technology

[U-Boot] [PATCH v2 03/12] riscv: nx25: dts: Add AE250 dts to support RISC-V

From: Rick Chen AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250. Signed-off-by: Rick Chen Signed-off-by: Rick Chen Signed-off-by: Greentime Hu ---

[U-Boot] [PATCH v2 06/12] riscv: board: Add nx25-ae250 to support RISC-V

configs/nx25-ae250_defconfig diff --git a/board/AndesTech/nx25-ae250/Makefile b/board/AndesTech/nx25-ae250/Makefile new file mode 100644 index 000..66b6814 --- /dev/null +++ b/board/AndesTech/nx25-ae250/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2017 Andes Technology Corporation. +# Rick Chen,

[U-Boot] [PATCH v2 02/12] riscv: nx25: lib: Add relative lib funcs to support RISC-V

ch/riscv/lib/Makefile new file mode 100644 index 000..323cf3e --- /dev/null +++ b/arch/riscv/lib/Makefile @@ -0,0 +1,14 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# Copyright (C) 2017 Andes Technology Corporation +# Rick Chen, Andes Technology C

[U-Boot] [PATCH v2 01/12] riscv: cpu: Add nx25 to support RISC-V

From: Rick Chen <r...@andestech.com> Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok.

[U-Boot] [PATCH v2 00/12] Add NX25 to support RISC-V

From: Rick Chen Changelog v2: - Patch 5/12 : Changes - Patch 9/12 : Changes - Others : No changed [Patch 5/12] riscv: Add Kconfig to support RISC-V - Modify the top-level MAINTAINERS for RISC-V [Patch 9/12] riscv: tools: Prelink u-boot - Add license

[U-Boot] [PATCH 12/12] riscv: doc: Add relative doc to describe RISC-V

to hold a pointer to the global data + Memory Management: -- diff --git a/doc/README.NX25 b/doc/README.NX25 new file mode 100644 index 000..9f054e5 --- /dev/null +++ b/doc/README.NX25 @@ -0,0 +1,46 @@ +NX25 is Andes CPU IP to adopt RISC-V architecture. + +Features + + +C

[U-Boot] [PATCH 10/12] riscv: Support standalone

++ 2 files changed, 53 insertions(+), 0 deletions(-) create mode 100644 examples/standalone/riscv.lds diff --git a/examples/standalone/riscv.lds b/examples/standalone/riscv.lds new file mode 100644 index 000..7d8c482 --- /dev/null +++ b/examples/standalone/riscv.lds @@ -0,0 +1,41 @@

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