[PATCH] board: ti: j721e: Return if there is an error while configuring SerDes
While configuring SerDes, errors could be encountered, in these cases,
return instead of going ahead. This is will help in booting even if
configuration of SerDes fails.
Signed-off-by: Aswath Govindraju
---
board/ti/j721e/evm.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index e6ff54c065de..c62716788e2e 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -380,19 +380,25 @@ void configure_serdes_torrent(void)
ret = uclass_get_device_by_driver(UCLASS_PHY,
DM_DRIVER_GET(torrent_phy_provider),
);
- if (ret)
+ if (ret) {
printf("Torrent init failed:%d\n", ret);
+ return;
+ }
serdes.dev = dev;
serdes.id = 0;
ret = generic_phy_init();
- if (ret)
- printf("phy_init failed!!\n");
+ if (ret) {
+ printf("phy_init failed!!: %d\n", ret);
+ return;
+ }
ret = generic_phy_power_on();
- if (ret)
- printf("phy_power_on failed !!\n");
+ if (ret) {
+ printf("phy_power_on failed!!: %d\n", ret);
+ return;
+ }
}
void configure_serdes_sierra(void)
@@ -408,21 +414,27 @@ void configure_serdes_sierra(void)
ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(sierra_phy_provider),
);
- if (ret)
+ if (ret) {
printf("Sierra init failed:%d\n", ret);
+ return;
+ }
count = device_get_child_count(dev);
for (i = 0; i < count; i++) {
ret = device_get_child(dev, i, _dev);
- if (ret)
- printf("probe of sierra child node %d failed\n", i);
+ if (ret) {
+ printf("probe of sierra child node %d failed: %d\n", i,
ret);
+ return;
+ }
if (link_dev->driver->id == UCLASS_PHY) {
link.dev = link_dev;
link.id = link_count++;
ret = generic_phy_power_on();
- if (ret)
- printf("phy_power_on failed !!\n");
+ if (ret) {
+ printf("phy_power_on failed!!: %d\n", ret);
+ return;
+ }
}
}
}
--
2.17.1
Re: [PATCH] fdtdec: drop needlessly convoluted CONFIG_PHANDLE_CHECK_SEQ
Hi Rasmus,
On 19/05/22 16:58, Rasmus Villemoes wrote:
> On 19/05/2022 12.41, Aswath Govindraju wrote:
>> Hi Rasmus,
>>
>> On 19/05/22 14:40, Rasmus Villemoes wrote:
>>> Asking if the alias we found actually points at the device tree node
>>> we passed in (in the guise of its offset from blob) can be done simply
>>> by asking if the fdt_path_offset() of the alias' path is identical to
>>> offset.
>>>
>>> In fact, the current method suffers from the possibility of false
>>> negatives: dtc does not necessarily emit a phandle property for a node
>>> just because it is referenced in /aliases; it only emits a phandle
>>> property for a node if it is referenced in
>>> somewhere. So if both the node we passed in and the alias node we're
>>> considering don't have phandles, fdt_get_phandle() returns 0 for both.
>>>
>>> Since the proper check is so simple, there's no reason to hide that
>>> behind a config option (and if one really wanted that, it should be
>>> called something else because there's no need to involve phandle in
>>> the check).
>>>
>>> Signed-off-by: Rasmus Villemoes
>>> ---
>>> configs/am65x_evm_a53_defconfig | 1 -
>>> configs/evb-ast2600_defconfig| 1 -
>>> configs/sama7g5ek_mmc1_defconfig | 1 -
>>> configs/sama7g5ek_mmc_defconfig | 1 -
>>> lib/Kconfig | 7 ---
>>> lib/fdtdec.c | 7 ++-
>>> 6 files changed, 2 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/configs/am65x_evm_a53_defconfig
>>> b/configs/am65x_evm_a53_defconfig
>>> index 9f41b397c3..a635d6d137 100644
>>> --- a/configs/am65x_evm_a53_defconfig
>>> +++ b/configs/am65x_evm_a53_defconfig
>>> @@ -170,4 +170,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
>>> CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
>>> CONFIG_USB_GADGET_DOWNLOAD=y
>>> CONFIG_OF_LIBFDT_OVERLAY=y
>>> -CONFIG_PHANDLE_CHECK_SEQ=y
>>> diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
>>> index ea75762926..015df20f09 100644
>>> --- a/configs/evb-ast2600_defconfig
>>> +++ b/configs/evb-ast2600_defconfig
>>> @@ -84,4 +84,3 @@ CONFIG_WDT=y
>>> CONFIG_SHA384=y
>>> CONFIG_HEXDUMP=y
>>> # CONFIG_EFI_LOADER is not set
>>> -CONFIG_PHANDLE_CHECK_SEQ=y
>>> diff --git a/configs/sama7g5ek_mmc1_defconfig
>>> b/configs/sama7g5ek_mmc1_defconfig
>>> index 42d96f7c02..3f33eb1142 100644
>>> --- a/configs/sama7g5ek_mmc1_defconfig
>>> +++ b/configs/sama7g5ek_mmc1_defconfig
>>> @@ -76,4 +76,3 @@ CONFIG_TIMER=y
>>> CONFIG_MCHP_PIT64B_TIMER=y
>>> CONFIG_OF_LIBFDT_OVERLAY=y
>>> # CONFIG_EFI_LOADER_HII is not set
>>> -CONFIG_PHANDLE_CHECK_SEQ=y
>>> diff --git a/configs/sama7g5ek_mmc_defconfig
>>> b/configs/sama7g5ek_mmc_defconfig
>>> index e03a6ba9af..6266eb0b59 100644
>>> --- a/configs/sama7g5ek_mmc_defconfig
>>> +++ b/configs/sama7g5ek_mmc_defconfig
>>> @@ -76,4 +76,3 @@ CONFIG_TIMER=y
>>> CONFIG_MCHP_PIT64B_TIMER=y
>>> CONFIG_OF_LIBFDT_OVERLAY=y
>>> # CONFIG_EFI_LOADER_HII is not set
>>> -CONFIG_PHANDLE_CHECK_SEQ=y
>>> diff --git a/lib/Kconfig b/lib/Kconfig
>>> index acc0ac081a..884569f9b1 100644
>>> --- a/lib/Kconfig
>>> +++ b/lib/Kconfig
>>> @@ -958,11 +958,4 @@ config LMB_RESERVED_REGIONS
>>> Define the number of supported reserved regions in the library logical
>>> memory blocks.
>>>
>>> -config PHANDLE_CHECK_SEQ
>>> - bool "Enable phandle check while getting sequence number"
>>> - help
>>> - When there are multiple device tree nodes with same name,
>>> - enable this config option to distinguish them using
>>> - phandles in fdtdec_get_alias_seq() function.
>>> -
>>> endmenu
>>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>>> index e20f6aad9c..ffa78f97ca 100644
>>> --- a/lib/fdtdec.c
>>> +++ b/lib/fdtdec.c
>>> @@ -516,11 +516,8 @@ int fdtdec_get_alias_seq(const void *blob, const char
>>> *base, int offset,
>>> * Adding an extra check to distinguish DT nodes with
>>> * same name
>>> */
>>> - if (IS_ENABLED(CONFIG_PHANDLE_CHECK_SEQ)) {
>>> - if (fdt_get_phandle(blob, offset) !=
>>> - fdt_get_phandle(blo
Re: [PATCH] fdtdec: drop needlessly convoluted CONFIG_PHANDLE_CHECK_SEQ
Hi Rasmus,
On 19/05/22 14:40, Rasmus Villemoes wrote:
> Asking if the alias we found actually points at the device tree node
> we passed in (in the guise of its offset from blob) can be done simply
> by asking if the fdt_path_offset() of the alias' path is identical to
> offset.
>
> In fact, the current method suffers from the possibility of false
> negatives: dtc does not necessarily emit a phandle property for a node
> just because it is referenced in /aliases; it only emits a phandle
> property for a node if it is referenced in
> somewhere. So if both the node we passed in and the alias node we're
> considering don't have phandles, fdt_get_phandle() returns 0 for both.
>
> Since the proper check is so simple, there's no reason to hide that
> behind a config option (and if one really wanted that, it should be
> called something else because there's no need to involve phandle in
> the check).
>
> Signed-off-by: Rasmus Villemoes
> ---
> configs/am65x_evm_a53_defconfig | 1 -
> configs/evb-ast2600_defconfig| 1 -
> configs/sama7g5ek_mmc1_defconfig | 1 -
> configs/sama7g5ek_mmc_defconfig | 1 -
> lib/Kconfig | 7 ---
> lib/fdtdec.c | 7 ++-
> 6 files changed, 2 insertions(+), 16 deletions(-)
>
> diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
> index 9f41b397c3..a635d6d137 100644
> --- a/configs/am65x_evm_a53_defconfig
> +++ b/configs/am65x_evm_a53_defconfig
> @@ -170,4 +170,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0451
> CONFIG_USB_GADGET_PRODUCT_NUM=0x6162
> CONFIG_USB_GADGET_DOWNLOAD=y
> CONFIG_OF_LIBFDT_OVERLAY=y
> -CONFIG_PHANDLE_CHECK_SEQ=y
> diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
> index ea75762926..015df20f09 100644
> --- a/configs/evb-ast2600_defconfig
> +++ b/configs/evb-ast2600_defconfig
> @@ -84,4 +84,3 @@ CONFIG_WDT=y
> CONFIG_SHA384=y
> CONFIG_HEXDUMP=y
> # CONFIG_EFI_LOADER is not set
> -CONFIG_PHANDLE_CHECK_SEQ=y
> diff --git a/configs/sama7g5ek_mmc1_defconfig
> b/configs/sama7g5ek_mmc1_defconfig
> index 42d96f7c02..3f33eb1142 100644
> --- a/configs/sama7g5ek_mmc1_defconfig
> +++ b/configs/sama7g5ek_mmc1_defconfig
> @@ -76,4 +76,3 @@ CONFIG_TIMER=y
> CONFIG_MCHP_PIT64B_TIMER=y
> CONFIG_OF_LIBFDT_OVERLAY=y
> # CONFIG_EFI_LOADER_HII is not set
> -CONFIG_PHANDLE_CHECK_SEQ=y
> diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig
> index e03a6ba9af..6266eb0b59 100644
> --- a/configs/sama7g5ek_mmc_defconfig
> +++ b/configs/sama7g5ek_mmc_defconfig
> @@ -76,4 +76,3 @@ CONFIG_TIMER=y
> CONFIG_MCHP_PIT64B_TIMER=y
> CONFIG_OF_LIBFDT_OVERLAY=y
> # CONFIG_EFI_LOADER_HII is not set
> -CONFIG_PHANDLE_CHECK_SEQ=y
> diff --git a/lib/Kconfig b/lib/Kconfig
> index acc0ac081a..884569f9b1 100644
> --- a/lib/Kconfig
> +++ b/lib/Kconfig
> @@ -958,11 +958,4 @@ config LMB_RESERVED_REGIONS
> Define the number of supported reserved regions in the library logical
> memory blocks.
>
> -config PHANDLE_CHECK_SEQ
> - bool "Enable phandle check while getting sequence number"
> - help
> - When there are multiple device tree nodes with same name,
> - enable this config option to distinguish them using
> - phandles in fdtdec_get_alias_seq() function.
> -
> endmenu
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index e20f6aad9c..ffa78f97ca 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -516,11 +516,8 @@ int fdtdec_get_alias_seq(const void *blob, const char
> *base, int offset,
>* Adding an extra check to distinguish DT nodes with
>* same name
>*/
> - if (IS_ENABLED(CONFIG_PHANDLE_CHECK_SEQ)) {
> - if (fdt_get_phandle(blob, offset) !=
> - fdt_get_phandle(blob, fdt_path_offset(blob, prop)))
> - continue;
> - }
> + if (offset != fdt_path_offset(blob, prop))
> + continue;
The offset over here is the offset of the dt node and the offset that we
get from fdt_path_offset(blob, prop) is the offset of the aliases
property. I don't think these both offsets will match for any case. That
is the reason behind comparing phandles and not offsets.
Also, as fdt_path_offset() slow and this would effect the U-Boot
startup. To avert the time penalty on all boards, this extra check
put under a config option.
Thanks,
Aswath
>
> val = trailing_strtol(name);
> if (val != -1)
[PATCH 2/3] arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.
Signed-off-by: Aswath Govindraju
---
arch/arm/mach-k3/am6_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index 86c1a349f1fc..7992918adcdc 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -127,8 +127,8 @@ static int fixup_usb_boot(void)
* before the dwc3 bind takes place
*/
ret = fdt_find_and_setprop((void *)gd->fdt_blob,
- "/interconnect@10/dwc3@400/usb@1",
- "dr_mode", "host", 11, 0);
+ "/bus@10/dwc3@400/usb@1",
+ "dr_mode", "host", 5, 0);
if (ret)
printf("%s: fdt_find_and_setprop() failed:%d\n",
__func__,
ret);
--
2.17.1
[PATCH 3/3] configs: am65_evm_r5_usb*_defconfig: Sync the checks for size of image and stack from generic r5 defconfig
Sync the configs required for enabling checks for size of image and stack from generic r5 defconfig file. Signed-off-by: Aswath Govindraju --- configs/am65x_evm_r5_usbdfu_defconfig | 5 + configs/am65x_evm_r5_usbmsc_defconfig | 5 + 2 files changed, 10 insertions(+) diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 57cd0f35a56f..20e32373bbfe 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -16,6 +16,8 @@ CONFIG_SPL_TEXT_BASE=0x41c0 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_SIZE_LIMIT=0x7ec00 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set @@ -23,6 +25,9 @@ CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008 CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index e6147d1be36d..c4b0ff0b6775 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -16,12 +16,17 @@ CONFIG_SPL_TEXT_BASE=0x41c0 CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_SIZE_LIMIT=0x7ec00 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x2000 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set CONFIG_SPL_LOAD_FIT=y CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_EARLY_BSS=y -- 2.17.1
[PATCH 0/3] AM65: Fix USB boot modes
The following series of patches along with [1], fix usb boot modes on AM654 IDK board. [1] - https://patchwork.ozlabs.org/project/uboot/list/?series=300845 Aswath Govindraju (3): arm: dts: k3-am654-r5-base-board: Fix the dt properties in usb0 instance arm: mach-k3: am6_init: Fix the path and value's length in the fixup performed for usb boot configs: am65_evm_r5_usb*_defconfig: Sync the checks for size of image and stack from generic r5 defconfig arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi | 2 +- arch/arm/dts/k3-am654-r5-base-board.dts | 1 + arch/arm/mach-k3/am6_init.c | 4 ++-- configs/am65x_evm_r5_usbdfu_defconfig | 5 + configs/am65x_evm_r5_usbmsc_defconfig | 5 + 5 files changed, 14 insertions(+), 3 deletions(-) -- 2.17.1
[PATCH 1/3] arm: dts: k3-am654-r5-base-board: Fix the dt properties in usb0 instance
For dfu boot mode, the clocks property needs to be deleted and dr_mode
needs to be set to peripheral. Therefore, add the required fixes for the
same.
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi | 2 +-
arch/arm/dts/k3-am654-r5-base-board.dts | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
index 26567f4167ff..1d0659ea8fff 100644
--- a/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi
@@ -198,7 +198,7 @@
{
pinctrl-names = "default";
pinctrl-0 = <_pins_default>;
- dr_mode = "host";
+ dr_mode = "peripheral";
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts
b/arch/arm/dts/k3-am654-r5-base-board.dts
index 24881c86f2a8..455698a93630 100644
--- a/arch/arm/dts/k3-am654-r5-base-board.dts
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -309,6 +309,7 @@
_0 {
status = "okay";
u-boot,dm-spl;
+ /delete-property/ clocks;
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
--
2.17.1
[PATCH] usb: dwc3: Fix the error paths in usb3-phy PHY configuration
generic_phy_power_off(), needs to be called in dwc3_glue_remove() while
exiting as we powering on the phy in the dwc3_glue_probe(). Therefore,
instantiate struct phy in dwc3_glue_data to use in dwc3_glue_probe() as
well as dwc3_glue_remove().
In cases where "usb3-phy" is not present in the phy-names property,
generic_phy_get_by_name() returns -ENODATA. Therefore, add condition to not
return when the error code is -ENODATA too.
Also, generic_phy_init() and generic_phy_power_on() functions, have checks
to verify if the struct phy argument passed is valid. Therefore, remove
additional checks added for these in the dwc3_glue_probe().
Fixes: 142d50fbce7c ("usb: dwc3: Add support for usb3-phy PHY configuration")
Signed-off-by: Aswath Govindraju
---
drivers/usb/dwc3/dwc3-generic.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 6e1a1d066b40..f74d710a2447 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -30,6 +30,7 @@
struct dwc3_glue_data {
struct clk_bulk clks;
struct reset_ctl_bulk resets;
+ struct phy phy;
fdt_addr_t regs;
};
@@ -458,21 +459,21 @@ static int dwc3_glue_probe(struct udevice *dev)
{
struct dwc3_glue_ops *ops = (struct dwc3_glue_ops
*)dev_get_driver_data(dev);
struct dwc3_glue_data *glue = dev_get_plat(dev);
+ struct phy *phy = >phy;
struct udevice *child = NULL;
int index = 0;
int ret;
- struct phy phy;
- ret = generic_phy_get_by_name(dev, "usb3-phy", );
- if (!ret) {
- ret = generic_phy_init();
- if (ret)
- return ret;
- } else if (ret != -ENOENT) {
+ ret = generic_phy_get_by_name(dev, "usb3-phy", phy);
+ if (ret && ret != -ENOENT && ret != -ENODATA) {
debug("could not get phy (err %d)\n", ret);
return ret;
}
+ ret = generic_phy_init(phy);
+ if (ret)
+ return ret;
+
glue->regs = dev_read_addr(dev);
ret = dwc3_glue_clk_init(dev, glue);
@@ -483,11 +484,9 @@ static int dwc3_glue_probe(struct udevice *dev)
if (ret)
return ret;
- if (phy.dev) {
- ret = generic_phy_power_on();
- if (ret)
- return ret;
- }
+ ret = generic_phy_power_on(phy);
+ if (ret)
+ return ret;
ret = device_find_first_child(dev, );
if (ret)
@@ -516,6 +515,8 @@ static int dwc3_glue_remove(struct udevice *dev)
{
struct dwc3_glue_data *glue = dev_get_plat(dev);
+ generic_phy_power_off(>phy);
+
reset_release_bulk(>resets);
clk_release_bulk(>clks);
--
2.17.1
[PATCH] include: configs: am**x/j721e/j721s2_evm.h: Move the stack pointer init address in arm64
Currently, in case of arm64 bootloader and U-Boot the stack pointer is initialized at an offset of NON_SECURE_MSRAM_SIZE from arm64 SPL's text base address. After jumping to arm64, execution is done out of DDR. Therefore, having an offset corresponding to the size of MSRAM does not have any significance. Instead, initialize the stack pointer after an offset of 4MB from the SPL text base address. This helps in allocating larger memory for stack. ┌┐0x8008 ││ │ arm64 SPL│ ├┤ │▲ │ ││ │ │ STACK │ ├┤0x8048 │ Memory for Load│ │ Buffer Allocation │ ├┤0x8080 ││ │U-Boot Image│ ││ └┘ Signed-off-by: Aswath Govindraju --- Notes: - Verified SD and DFU boot modes on platforms where this change will have an effect and are supported - AM64 - SD boot mode, https://pastebin.ubuntu.com/p/YDBjhTqwSK/ - DFU boot mode, https://pastebin.ubuntu.com/p/Xsjn4h7h2W/ - "Error setting up memory banksize. -22" This error was present even without the changes done by this patch - J721e - SD boot mode, https://pastebin.ubuntu.com/p/NpVvKjMMxc/ - DFU boot mode, https://pastebin.ubuntu.com/p/MZPS4Wmkj5/ - J7200 - SD boot mode, https://pastebin.ubuntu.com/p/QyyC8WFsS2/ - DFU boot mode, https://pastebin.ubuntu.com/p/Nmjf3mVRyH/ - J721s2 - SD boot mode, https://pastebin.ubuntu.com/p/xh96CP8ndB/ - AM654 - SD boot mode, https://pastebin.ubuntu.com/p/DbFjFSvj2C/ include/configs/am64x_evm.h | 3 +-- include/configs/am65x_evm.h | 3 +-- include/configs/j721e_evm.h | 3 +-- include/configs/j721s2_evm.h | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h index 135cb3c2ee20..d84a8db97ede 100644 --- a/include/configs/am64x_evm.h +++ b/include/configs/am64x_evm.h @@ -24,8 +24,7 @@ #define CONFIG_SPL_MAX_SIZECONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE #if defined(CONFIG_TARGET_AM642_A53_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE +\ - CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h index 55fa6419e33d..b1f9050f3f5b 100644 --- a/include/configs/am65x_evm.h +++ b/include/configs/am65x_evm.h @@ -19,8 +19,7 @@ /* SPL Loader Configuration */ #ifdef CONFIG_TARGET_AM654_A53_EVM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE +\ -CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #else /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index df3c16540ba3..2590ee6b0140 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -20,8 +20,7 @@ /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE +\ -CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #define CONFIG_SYS_UBOOT_BASE 0x5028 /* Image load address in RAM for DFU boot*/ #else diff --git a/include/configs/j721s2_evm.h b/include/configs/j721s2_evm.h index f0d56b8778ee..a5505f079b43 100644 --- a/include/configs/j721s2_evm.h +++ b/include/configs/j721s2_evm.h @@ -21,8 +21,7 @@ /* SPL Loader Configuration */ #if defined(CONFIG_TARGET_J721S2_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE +\ -CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + SZ_4M) #define CONFIG_SYS_UBOOT_BASE 0x5028 /* Image load address in RAM for DFU boot*/ #else -- 2.17.1
[PATCH] drivers: usb: dwc3: Add support for AM62 USB wrapper driver
Add support for AM62 USB wrapper for DWC3 Controller in AM62 SoC.
Signed-off-by: Aswath Govindraju
---
Link to corresponding kernel dt-bindings and driver patches,
- https://patchwork.kernel.org/project/linux-usb/list/?series=629613
drivers/usb/dwc3/Kconfig | 7 +
drivers/usb/dwc3/Makefile| 1 +
drivers/usb/dwc3/dwc3-am62.c | 284 +++
3 files changed, 292 insertions(+)
create mode 100644 drivers/usb/dwc3/dwc3-am62.c
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 62aa65bf0cd2..87e19720ab84 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -63,6 +63,13 @@ config USB_DWC3_LAYERSCAPE
Host and Peripheral operation modes are supported. OTG is not
supported.
+config USB_DWC3_AM62
+ tristate "Texas Instruments AM62 Platforms"
+ depends on ARCH_K3 || COMPILE_TEST
+ default USB_DWC3
+ help
+ Support of USB2 functionality in TI's AM62 platforms
+
menu "PHY Subsystem"
config USB_DWC3_PHY_OMAP
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 0dd1ba87cd94..26bc3a7379b7 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -7,6 +7,7 @@ dwc3-y := core.o
obj-$(CONFIG_USB_DWC3_GADGET) += gadget.o ep0.o
obj-$(CONFIG_USB_DWC3_OMAP)+= dwc3-omap.o
+obj-$(CONFIG_USB_DWC3_AM62)+= dwc3-am62.o
obj-$(CONFIG_USB_DWC3_MESON_G12A) += dwc3-meson-g12a.o
obj-$(CONFIG_USB_DWC3_MESON_GXL) += dwc3-meson-gxl.o
obj-$(CONFIG_USB_DWC3_GENERIC) += dwc3-generic.o
diff --git a/drivers/usb/dwc3/dwc3-am62.c b/drivers/usb/dwc3/dwc3-am62.c
new file mode 100644
index ..a3ad609036e2
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-am62.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dwc3-am62.c - TI specific Glue layer for AM62 DWC3 USB Controller
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* USB WRAPPER register offsets */
+#define USBSS_PID 0x0
+#define USBSS_OVERCURRENT_CTRL 0x4
+#define USBSS_PHY_CONFIG 0x8
+#define USBSS_PHY_TEST 0xc
+#define USBSS_CORE_STAT0x14
+#define USBSS_HOST_VBUS_CTRL 0x18
+#define USBSS_MODE_CONTROL 0x1c
+#define USBSS_WAKEUP_CONFIG0x30
+#define USBSS_WAKEUP_STAT 0x34
+#define USBSS_OVERRIDE_CONFIG 0x38
+#define USBSS_IRQ_MISC_STATUS_RAW 0x430
+#define USBSS_IRQ_MISC_STATUS 0x434
+#define USBSS_IRQ_MISC_ENABLE_SET 0x438
+#define USBSS_IRQ_MISC_ENABLE_CLR 0x43c
+#define USBSS_IRQ_MISC_EOI 0x440
+#define USBSS_INTR_TEST0x490
+#define USBSS_VBUS_FILTER 0x614
+#define USBSS_VBUS_STAT0x618
+#define USBSS_DEBUG_CFG0x708
+#define USBSS_DEBUG_DATA 0x70c
+#define USBSS_HOST_HUB_CTRL0x714
+
+/* PHY CONFIG register bits */
+#define USBSS_PHY_VBUS_SEL_MASKGENMASK(2, 1)
+#define USBSS_PHY_VBUS_SEL_SHIFT 1
+#define USBSS_PHY_LANE_REVERSE BIT(0)
+
+/* MODE CONTROL register bits */
+#define USBSS_MODE_VALID BIT(0)
+
+/* IRQ_MISC_STATUS_RAW register bits */
+#define USBSS_IRQ_MISC_RAW_VBUSVALID BIT(22)
+#define USBSS_IRQ_MISC_RAW_SESSVALID BIT(20)
+
+/* IRQ_MISC_STATUS register bits */
+#define USBSS_IRQ_MISC_VBUSVALID BIT(22)
+#define USBSS_IRQ_MISC_SESSVALID BIT(20)
+
+/* IRQ_MISC_ENABLE_SET register bits */
+#define USBSS_IRQ_MISC_ENABLE_SET_VBUSVALIDBIT(22)
+#define USBSS_IRQ_MISC_ENABLE_SET_SESSVALIDBIT(20)
+
+/* IRQ_MISC_ENABLE_CLR register bits */
+#define USBSS_IRQ_MISC_ENABLE_CLR_VBUSVALIDBIT(22)
+#define USBSS_IRQ_MISC_ENABLE_CLR_SESSVALIDBIT(20)
+
+/* VBUS_STAT register bits */
+#define USBSS_VBUS_STAT_SESSVALID BIT(2)
+#define USBSS_VBUS_STAT_VBUSVALID BIT(0)
+
+/* Mask for PHY PLL REFCLK */
+#define PHY_PLL_REFCLK_MASKGENMASK(3, 0)
+
+struct dwc3_data {
+ struct udevice *dev;
+ void __iomem *usbss;
+ struct regmap *syscon;
+ unsigned int offset;
+ unsigned int vbus_divider;
+};
+
+static inline u32 dwc3_ti_readl(struct dwc3_data *data, u32 offset)
+{
+ return readl(data->usbss + offset);
+}
+
+static inline void dwc3_ti_writel(struct dwc3_data *data, u32 offset, u32
value)
+{
+ writel(value, data->usbss + offset);
+}
+
+static const int dwc3_ti_rate_table[] = { /* in KHZ */
+ 9600,
+ 1,
+ 12000,
+ 19200,
+ 2,
+ 24000,
+ 25000,
+ 26000,
+ 38400,
+ 4,
+ 58000,
+ 5,
+
Re: [PATCH] doc: mmc dev
Hi Patrick,
On 29/03/22 19:31, Patrick Delaunay wrote:
> Provide human readable descriptions of the speed nodes instead of the name
> of constants from the code as it is already done for 'mmc rescan'
> command in commit 212f078496e4 ("doc: mmc rescan speed mode").
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Aswath Govindraju
Thanks,
Aswath
> ---
>
> doc/usage/mmc.rst | 36
> 1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/doc/usage/mmc.rst b/doc/usage/mmc.rst
> index 02b5d7b1c7..55e3f9cf98 100644
> --- a/doc/usage/mmc.rst
> +++ b/doc/usage/mmc.rst
> @@ -85,22 +85,26 @@ The 'mmc dev' command shows or set current mmc device.
>
> mode
> speed mode to set.
> - CONFIG_MMC_SPEED_MODE_SET should be enabled. The required speed mode
> is
> - passed as the index from the following list.
> -
> - 0 - MMC_LEGACY
> - 1 - MMC_HS
> - 2 - SD_HS
> - 3 - MMC_HS_52
> - 4 - MMC_DDR_52
> - 5 - UHS_SDR12
> - 6 - UHS_SDR25
> - 7 - UHS_SDR50
> - 8 - UHS_DDR50
> - 9 - UHS_SDR104
> - 10 - MMC_HS_200
> - 11 - MMC_HS_400
> - 12 - MMC_HS_400_ES
> + CONFIG_MMC_SPEED_MODE_SET should be enabled. The requested speed mode
> is
> + passed as a decimal number according to the following table:
> +
> + == ==
> + Speed mode Description
> + == ==
> + 0 MMC legacy
> + 1 MMC High Speed (26MHz)
> + 2 SD High Speed (50MHz)
> + 3 MMC High Speed (52MHz)
> + 4 MMC DDR52 (52MHz)
> + 5 UHS SDR12 (25MHz)
> + 6 UHS SDR25 (50MHz)
> + 7 UHS SDR50 (100MHz)
> + 8 UHS DDR50 (50MHz)
> + 9 UHS SDR104 (208MHz)
> + 10 HS200 (200MHz)
> + 11 HS400 (200MHz)
> + 12 HS400ES (200MHz)
> + == ==
>
> A speed mode can be set only if it has already been enabled in the
> device tree
>
[PATCH 2/2] board: ti: j721e: evm.c: Fix the probing of in Sierra SerDes0
Initialization and power on operations of links have been moved under the
link device in the Sierra SerDes driver. Also, the UCLASS of
sierra_phy_provider has been changed to UCLASS_MISC.
Therefore, fix the probing of SerDes0 instance accordingly.
Signed-off-by: Aswath Govindraju
Reviewed-by: Georgi Vlaev
---
board/ti/j721e/evm.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index f479197e722b..e6ff54c065de 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -397,36 +397,34 @@ void configure_serdes_torrent(void)
void configure_serdes_sierra(void)
{
- struct udevice *dev, *lnk_dev;
- struct phy serdes;
+ struct udevice *dev, *link_dev;
+ struct phy link;
int ret, count, i;
+ int link_count = 0;
if (!IS_ENABLED(CONFIG_PHY_CADENCE_SIERRA))
return;
- ret = uclass_get_device_by_driver(UCLASS_PHY,
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
DM_DRIVER_GET(sierra_phy_provider),
);
if (ret)
printf("Sierra init failed:%d\n", ret);
- serdes.dev = dev;
- serdes.id = 0;
-
count = device_get_child_count(dev);
for (i = 0; i < count; i++) {
- ret = device_get_child(dev, i, _dev);
+ ret = device_get_child(dev, i, _dev);
if (ret)
printf("probe of sierra child node %d failed\n", i);
- }
+ if (link_dev->driver->id == UCLASS_PHY) {
+ link.dev = link_dev;
+ link.id = link_count++;
- ret = generic_phy_init();
- if (ret)
- printf("phy_init failed!!\n");
-
- ret = generic_phy_power_on();
- if (ret)
- printf("phy_power_on failed !!\n");
+ ret = generic_phy_power_on();
+ if (ret)
+ printf("phy_power_on failed !!\n");
+ }
+ }
}
#ifdef CONFIG_BOARD_LATE_INIT
--
2.17.1
[PATCH 1/2] phy: cadence: Sierra: Move the link operations from serdes phy to link device
In commit 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for
links"), a separate udevice of type UCLASS_PHY was created for each link.
Therefore, move the corresponding link operations under the link device.
Also, change the uclass of sierra phy to UCLASS_MISC as it is no longer the
phy device.
Fixes: 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links")
Signed-off-by: Aswath Govindraju
Reviewed-by: Georgi Vlaev
---
drivers/phy/cadence/phy-cadence-sierra.c | 59
1 file changed, 20 insertions(+), 39 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index d95d4b432a98..fc5044fd5d35 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -358,26 +358,10 @@ static inline int cdns_reset_deassert(struct
reset_control *rst)
return 0;
}
-static inline struct cdns_sierra_inst *phy_get_drvdata(struct phy *phy)
+static int cdns_sierra_link_init(struct phy *gphy)
{
- struct cdns_sierra_phy *sp = dev_get_priv(phy->dev);
- int index;
-
- if (phy->id >= SIERRA_MAX_LANES)
- return NULL;
-
- for (index = 0; index < sp->nsubnodes; index++) {
- if (phy->id == sp->phys[index]->mlane)
- return sp->phys[index];
- }
-
- return NULL;
-}
-
-static int cdns_sierra_phy_init(struct phy *gphy)
-{
- struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
- struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
+ struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev);
+ struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev->parent);
struct cdns_sierra_data *init_data = phy->init_data;
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
@@ -443,10 +427,11 @@ static int cdns_sierra_phy_init(struct phy *gphy)
return 0;
}
-static int cdns_sierra_phy_on(struct phy *gphy)
+static int cdns_sierra_link_on(struct phy *gphy)
{
- struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
- struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
+ struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent);
+
struct udevice *dev = gphy->dev;
u32 val;
int ret;
@@ -503,16 +488,16 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
-static int cdns_sierra_phy_off(struct phy *gphy)
+static int cdns_sierra_link_off(struct phy *gphy)
{
- struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
+ struct cdns_sierra_inst *ins = dev_get_priv(gphy->dev);
return reset_assert_bulk(ins->lnk_rst);
}
-static int cdns_sierra_phy_reset(struct phy *gphy)
+static int cdns_sierra_link_reset(struct phy *gphy)
{
- struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(gphy->dev->parent);
reset_control_assert(sp->phy_rst);
reset_control_deassert(sp->phy_rst);
@@ -520,10 +505,10 @@ static int cdns_sierra_phy_reset(struct phy *gphy)
};
static const struct phy_ops ops = {
- .init = cdns_sierra_phy_init,
- .power_on = cdns_sierra_phy_on,
- .power_off = cdns_sierra_phy_off,
- .reset = cdns_sierra_phy_reset,
+ .init = cdns_sierra_link_init,
+ .power_on = cdns_sierra_link_on,
+ .power_off = cdns_sierra_link_off,
+ .reset = cdns_sierra_link_reset,
};
struct cdns_sierra_pll_mux_sel {
@@ -580,7 +565,7 @@ static const struct clk_ops cdns_sierra_pll_mux_ops = {
.set_parent = cdns_sierra_pll_mux_set_parent,
};
-int cdns_sierra_pll_mux_probe(struct udevice *dev)
+static int cdns_sierra_pll_mux_probe(struct udevice *dev)
{
struct cdns_sierra_pll_mux *priv = dev_get_priv(dev);
struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
@@ -1012,9 +997,8 @@ static int cdns_sierra_phy_get_resets(struct
cdns_sierra_phy *sp,
return 0;
}
-static int cdns_sierra_bind_link_nodes(struct cdns_sierra_phy *sp)
+static int cdns_sierra_phy_bind(struct udevice *dev)
{
- struct udevice *dev = sp->dev;
struct driver *link_drv;
ofnode child;
int rc;
@@ -1079,6 +1063,7 @@ U_BOOT_DRIVER(sierra_phy_link) = {
.name = "sierra_phy_link",
.id = UCLASS_PHY,
.probe = cdns_sierra_link_probe,
+ .ops= ,
.priv_auto = sizeof(struct cdns_sierra_inst),
};
@@ -1141,10 +1126,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
}
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
- /* Binding li
[PATCH 0/2] J721E: Fix DFU in U-Boot
The following series of patches fix USB DFU in U-Boot for J721e. Aswath Govindraju (2): phy: cadence: Sierra: Move the link operations from serdes phy to link device board: ti: j721e: evm.c: Fix the probing of in Sierra SerDes0 board/ti/j721e/evm.c | 28 ++- drivers/phy/cadence/phy-cadence-sierra.c | 59 2 files changed, 33 insertions(+), 54 deletions(-) -- 2.17.1
[PATCH v2 3/3] configs: j721e_hs_evm_a72_defconfig: Add command for initializing QSGMII PHY
QSGMII PHY present on the j721e common processor board requires
to be initialized before the core boots up. Therefore, run the
corresponding command during boot to do the same.
Signed-off-by: Aswath Govindraju
---
configs/j721e_hs_evm_a72_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/j721e_hs_evm_a72_defconfig
b/configs/j721e_hs_evm_a72_defconfig
index ae184b035878..c37c20a91b08 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -30,7 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run
get_overlaystring; run run_fit"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
--
2.17.1
[PATCH v2 2/3] configs: j721e_evm_a72_defconfig: Fix the bootcmd
Add the command "boot_rprocs" that is required for booting remote
processors in U-Boot.
Fixes: 5980925e2a5a ("include: configs: j721e_evm: Add support to boot ethfw
core in j721e")
Reported-by: Jesse Villarreal
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index b843a84415b1..7929e2226909 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,7 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
--
2.17.1
[PATCH v2 1/3] include: configs: j721e_evm.h: Fix the env variable corresponding to QSGMII PHY init
QSGMII PHY initialization should only be done for J721E EVMs and not for
J721E-SK boards. Therefore, fix the environment variables accordingly.
Also, by default remote processors should not be booted in U-Boot but
rather be left to the users to enable this by setting dorprocboot.
Therefore, remove dorprocboot that is being set by default.
Fixes: 5980925e2a5a ("include: configs: j721e_evm: Add support to boot ethfw
core in j721e")
Reported-by: Suman Anna
Signed-off-by: Aswath Govindraju
---
include/configs/j721e_evm.h | 19 +--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index e4b167dd219d..5aaa31eaa152 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -122,9 +122,8 @@
"partitions=" PARTS_DEFAULT
/* Set the default list of remote processors to boot */
-#if defined(CONFIG_TARGET_J721E_A72_EVM) ||
defined(CONFIG_TARGET_J7200_A72_EVM)
+#if defined(CONFIG_TARGET_J7200_A72_EVM)
#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
- "dorprocboot=1\0" \
"do_main_cpsw0_qsgmii_phyinit=1\0" \
"init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
"gpio clear gpio@22_16\0" \
@@ -136,6 +135,22 @@
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
#endif
+#elif defined(CONFIG_TARGET_J721E_A72_EVM)
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+"gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit="\
+ "if test $board_name = J721EX-PM1-SOM || test $board_name =
J721EX-PM2-SOM " \
+ "|| test $board_name = j721e; then " \
+ "do_main_cpsw0_qsgmii_phyinit=1; else " \
+ "do_main_cpsw0_qsgmii_phyinit=0; fi;" \
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
+#ifdef DEFAULT_RPROCS
+#undef DEFAULT_RPROCS
+#endif
#endif
#ifdef CONFIG_TARGET_J721E_A72_EVM
--
2.17.1
[PATCH v2 0/3] J721E: Fix initialization of QSGMII PHY
The following series of patches, - Fix the initialization of QSGMII PHY such that it is only applicable to J721E EVM - Remove the default setting of dorprocboot - Add boot_rprocs command in the GP bootcmd - Add phy initialization command in hs bootcmd Changes since v1: - Add checks such that the QSGMII PHY initialization is only applicable for J721E EVM - Rearranged the order of PHY initialization and boot_rpocs in the bootcmd - Added reported-bys - Split the fix into two patches. Aswath Govindraju (3): include: configs: j721e_evm.h: Fix the env variable corresponding to QSGMII PHY init configs: j721e_evm_a72_defconfig: Fix the bootcmd configs: j721e_hs_evm_a72_defconfig: Add command for initializing QSGMII PHY configs/j721e_evm_a72_defconfig| 2 +- configs/j721e_hs_evm_a72_defconfig | 2 +- include/configs/j721e_evm.h| 19 +-- 3 files changed, 19 insertions(+), 4 deletions(-) -- 2.17.1
Re: [PATCH 0/2] J721E: Fix bootcmd
Hi, On 18/02/22 6:59 pm, Aswath Govindraju wrote: > The following series of patches fix the bootcmd for J721e, > - adds the command 'run boot_rpocs' for booting remote processors > from U-Boot (As it was earlier) > - removes setting of dorprocboot to 1. Since this should be > set by the user and not set by default > - Syncs the bootcmd of hs configs with GP. > Please do not apply this patch as I have found out that there are few fixes that need to done. I will be posting a v2 of this series soon. > Aswath Govindraju (2): > configs: j721e_evm_a72_defconfig: Fix the bootcmd > configs: j721e_hs_evm_a72_defconfig: Sync up the bootcmd with GP > configs > > configs/j721e_evm_a72_defconfig| 2 +- > configs/j721e_hs_evm_a72_defconfig | 2 +- > include/configs/j721e_evm.h| 1 - > 3 files changed, 2 insertions(+), 3 deletions(-) > -- Thanks, Aswath
[PATCH 2/2] configs: j721e_hs_evm_a72_defconfig: Sync up the bootcmd with GP configs
Sync up the bootcmd with GP configs, to initialize the QSGMII phy required
for ethfw.
Signed-off-by: Aswath Govindraju
---
configs/j721e_hs_evm_a72_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/j721e_hs_evm_a72_defconfig
b/configs/j721e_hs_evm_a72_defconfig
index ae184b035878..545746ef7aee 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -30,7 +30,7 @@ CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
boot_rprocs; run main_cpsw0_qsgmii_phyinit; run get_fit_${boot}; run
get_overlaystring; run run_fit"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
--
2.17.1
[PATCH 1/2] configs: j721e_evm_a72_defconfig: Fix the bootcmd
In J721e remote processors are booted from U-Boot by using the command
'boot_rprocs' and the env variable 'dorprocboot'. Remote processors are
booted only when 'dorprocboot' it set to 1. By default this variable is set
to 0, so that it can be enabled through user specific environment files.
Therefore, fix the bootcmd to reflect the same.
Fixes: 5980925e2a5a ("include: configs: j721e_evm: Add support to boot ethfw
core in j721e")
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index b843a84415b1..4d62585b247c 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,7 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
boot_rprocs; run main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index e4b167dd219d..2d86b7fbb089 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -124,7 +124,6 @@
/* Set the default list of remote processors to boot */
#if defined(CONFIG_TARGET_J721E_A72_EVM) ||
defined(CONFIG_TARGET_J7200_A72_EVM)
#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
- "dorprocboot=1\0" \
"do_main_cpsw0_qsgmii_phyinit=1\0" \
"init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
"gpio clear gpio@22_16\0" \
--
2.17.1
[PATCH 0/2] J721E: Fix bootcmd
The following series of patches fix the bootcmd for J721e, - adds the command 'run boot_rpocs' for booting remote processors from U-Boot (As it was earlier) - removes setting of dorprocboot to 1. Since this should be set by the user and not set by default - Syncs the bootcmd of hs configs with GP. Aswath Govindraju (2): configs: j721e_evm_a72_defconfig: Fix the bootcmd configs: j721e_hs_evm_a72_defconfig: Sync up the bootcmd with GP configs configs/j721e_evm_a72_defconfig| 2 +- configs/j721e_hs_evm_a72_defconfig | 2 +- include/configs/j721e_evm.h| 1 - 3 files changed, 2 insertions(+), 3 deletions(-) -- 2.17.1
[PATCH] configs: j721e_*_evm_a72_defconfig: Enable config for setting mmc speed mode
Enable config for setting mmc speed mode from U-Boot command line. Signed-off-by: Aswath Govindraju --- configs/j721e_evm_a72_defconfig| 1 + configs/j721e_hs_evm_a72_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 8f412d65a8ac..c7a3f52762ec 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -190,3 +190,4 @@ CONFIG_UFS=y CONFIG_CADENCE_UFS=y CONFIG_TI_J721E_UFS=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_MMC_SPEED_MODE_SET=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index ae184b035878..6479f9baff0c 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -162,3 +162,4 @@ CONFIG_UFS=y CONFIG_CADENCE_UFS=y CONFIG_TI_J721E_UFS=y CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_MMC_SPEED_MODE_SET=y -- 2.17.1
Re: [PATCH 00/25] SIERRA: Add support for MultiLink
Hi All, On 27/01/22 2:42 pm, Aswath Govindraju wrote: > The following series of patches, > - add support for MultiLink on Sierra SerDes > - Also adds the required to configs, dt node changes > to enable this on J721e common processor board. > > Notes: > - Patches 1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15, 16, 17, > 18, 19, 20, 21 and 22 are ported from upstream kernel > v5.17-rc1 > - Patch 24, syncs with linux kernel dt, with the following patch > https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=608996 > > Posted v2 for this series, https://patchwork.ozlabs.org/project/uboot/list/?series=283316 Thanks, Aswath > Aswath Govindraju (8): > phy: cadence: Sierra: Add a UCLASS_PHY device for links > phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock > phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE > board: ti: j721e: evm.c: Add support for probing SerDes0 > arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 > phy: cadence: Sierra: Add support for skipping configuration > arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII > include: configs: j721e_evm: Add support to boot ethfw core in j721e > > Kishon Vijay Abraham I (6): > phy: cadence: Sierra: Fix PHY power_on sequence > phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes > phy: cadence: Sierra: Move all clk_get_*() to a separate function > phy: cadence: Sierra: Move all reset_control_get*() to a separate > function > phy: cadence: Sierra: Add array of input clocks in "struct > cdns_sierra_phy" > phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove > callback > > Sanket Parmar (1): > phy: cadence: sierra: Fix for USB3 U1/U2 state > > Swapnil Jakhade (10): > phy: cadence: Sierra: Prepare driver to add support for multilink > configurations > dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode > phy: cadence: Sierra: Add support to get SSC type from device tree. > phy: cadence: Sierra: Rename some regmap variables to be in sync with > Sierra documentation > phy: cadence: Sierra: Add PHY PCS common register configurations > phy: cadence: Sierra: Check cmn_ready assertion during PHY power on > phy: cadence: Sierra: Check PIPE mode PHY status to be ready for > operation > phy: cadence: Sierra: Update single link PCIe register configuration > phy: cadence: Sierra: Add support for PHY multilink configurations > phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration > > .../k3-j721e-common-proc-board-u-boot.dtsi| 15 + > arch/arm/dts/k3-j721e-common-proc-board.dts | 14 +- > .../arm/dts/k3-j721e-r5-common-proc-board.dts | 32 + > board/ti/j721e/evm.c | 37 + > configs/j721e_evm_a72_defconfig |2 +- > drivers/phy/cadence/phy-cadence-sierra.c | 1536 +++-- > drivers/phy/ti/phy-j721e-wiz.c|2 +- > include/configs/j721e_evm.h | 19 +- > include/dt-bindings/phy/phy-cadence.h |4 + > 9 files changed, 1493 insertions(+), 168 deletions(-) >
[PATCH v2 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e
Add configs to enable booting ethfw core in j721e
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 19 ++-
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 2e452739034e..8f412d65a8ac 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,7 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index abea7517e8b5..627c363ce66e 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -119,6 +119,16 @@
/* Set the default list of remote processors to boot */
#if defined(CONFIG_TARGET_J721E_A72_EVM) ||
defined(CONFIG_TARGET_J7200_A72_EVM)
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "dorprocboot=1\0" \
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+"gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit="\
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
#endif
@@ -136,15 +146,6 @@
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
- "do_main_cpsw0_qsgmii_phyinit=1\0" \
- "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
-"gpio clear gpio@22_16\0" \
- "main_cpsw0_qsgmii_phyinit="\
- "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
- "test ${boot} = mmc; then " \
- "run init_main_cpsw0_qsgmii_phy;" \
- "fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "
--
2.17.1
[PATCH v2 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
Add support for QSGMII multilink configuration.
Signed-off-by: Aswath Govindraju
---
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 5 +
arch/arm/dts/k3-j721e-common-proc-board.dts| 14 +++---
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 12 ++--
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 938e978a6b66..677a72d2a241 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -242,3 +242,8 @@
assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <_pll1_refclk>;
};
+
+_qsgmii_link {
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <_pll1_refclk>;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 8bd02d9e28ad..f3b6302a4317 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -345,7 +345,7 @@
};
_ln_ctrl {
- idle-states = ,
,
+ idle-states = ,
,
,
,
,
,
,
,
@@ -671,8 +671,8 @@
};
{
- assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <_pll1_refclk>;
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>, <
CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <_pll1_refclk>, <_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
@@ -681,6 +681,14 @@
cdns,phy-type = ;
resets = <_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <_wiz0 2>;
+ };
};
{
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 8299463c3e01..5362c528703d 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -374,8 +374,8 @@
};
{
- assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <_pll1_refclk>;
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>, <
CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <_pll1_refclk>, <_pll1_refclk>;
serdes0_pcie_link: link@0 {
reg = <0>;
@@ -384,4 +384,12 @@
cdns,phy-type = ;
resets = <_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <_wiz0 2>;
+ };
};
--
2.17.1
[PATCH v2 23/25] phy: cadence: Sierra: Add support for skipping configuration
In some cases, a single SerDes instance can be shared between two different
processors, each using a separate link. In these cases, the SerDes
configuration is done in an earlier boot stage. Therefore, add support to
skip reconfiguring, if it is was already configured beforehand.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 58 +---
1 file changed, 42 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 95cdd39cb367..d95d4b432a98 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -13,6 +13,7 @@
*/
#include
#include
+#include
#include
#include
#include
@@ -28,6 +29,8 @@
#include
#include
+#define usleep_range(a, b) udelay((b))
+
#define NUM_SSC_MODE 3
#define NUM_PHY_TYPE 4
@@ -336,6 +339,7 @@ struct cdns_sierra_phy {
int nsubnodes;
u32 num_lanes;
bool autoconf;
+ unsigned int already_configured;
};
static inline int cdns_reset_assert(struct reset_control *rst)
@@ -386,7 +390,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
int i, j;
/* Initialise the PHY registers, unless auto configured */
- if (phy->autoconf || phy->nsubnodes > 1)
+ if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1)
return 0;
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
@@ -447,6 +451,11 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
+ if (sp->already_configured) {
+ usleep_range(5000, 1);
+ return 0;
+ }
+
if (sp->nsubnodes == 1) {
/* Take the PHY out of reset */
ret = reset_control_deassert(sp->phy_rst);
@@ -934,13 +943,6 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
struct clk *clk;
int ret;
- clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(clk);
- }
- sp->input_clks[PHY_CLK] = clk;
-
clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
if (IS_ERR(clk)) {
dev_err(dev, "cmn_refclk_dig_div clock not found\n");
@@ -976,6 +978,25 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->input_clks[PHY_CLK] = clk;
+
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
+ if (ret)
+ return ret;
+
+ return 0;
+}
static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
struct udevice *dev)
{
@@ -1045,7 +1066,7 @@ static int cdns_sierra_link_probe(struct udevice *dev)
sp->num_lanes += inst->num_lanes;
/* If more than one subnode, configure the PHY as multilink */
- if (!sp->autoconf && sp->nsubnodes > 1) {
+ if (!sp->autoconf && !sp->already_configured && sp->nsubnodes > 1) {
ret = cdns_sierra_phy_configure_multilink(sp);
if (ret)
return ret;
@@ -1098,13 +1119,17 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- ret = cdns_sierra_phy_get_resets(sp, dev);
- if (ret)
- return ret;
+ regmap_field_read(sp->pma_cmn_ready, >already_configured);
- ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
- if (ret)
- return ret;
+ if (!sp->already_configured) {
+ ret = cdns_sierra_phy_clk(sp);
+ if (ret)
+ return ret;
+
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
+ }
/* Check that PHY is present */
regmap_field_read(sp->macro_id_type, _value);
@@ -1125,7 +1150,8 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return 0;
clk_disable:
- clk_disable_unprepare(sp->input_clks[PHY_CLK]);
+ if (!sp->already_configured)
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
return ret;
}
--
2.17.1
[PATCH v2 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
From: Swapnil Jakhade
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 378 ++-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 5641c5672806..95cdd39cb367 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -50,6 +50,9 @@
#define SIERRA_CMN_REFRCV1_PREG0xB8
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
+#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
+#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
+#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)
@@ -63,6 +66,9 @@
#define SIERRA_PSM_A0IN_TMR_PREG 0x009
#define SIERRA_PSM_A3IN_TMR_PREG 0x00C
#define SIERRA_PSM_DIAG_PREG 0x015
+#define SIERRA_PSC_LN_A3_PREG 0x023
+#define SIERRA_PSC_LN_A4_PREG 0x024
+#define SIERRA_PSC_LN_IDLE_PREG0x026
#define SIERRA_PSC_TX_A0_PREG 0x028
#define SIERRA_PSC_TX_A1_PREG 0x029
#define SIERRA_PSC_TX_A2_PREG 0x02A
@@ -72,6 +78,7 @@
#define SIERRA_PSC_RX_A2_PREG 0x032
#define SIERRA_PSC_RX_A3_PREG 0x033
#define SIERRA_PLLCTRL_SUBRATE_PREG0x03A
+#define SIERRA_PLLCTRL_GEN_A_PREG 0x03B
#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG0x03F
#define SIERRA_PLLCTRL_STATUS_PREG 0x044
@@ -154,6 +161,7 @@
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
+#define SIERRA_CPI_RESBIAS_BIN_PREG0x17E
#define SIERRA_CPI_TRIM_PREG 0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG0x183
#define SIERRA_EPI_CTRL_PREG 0x187
@@ -260,7 +268,8 @@ struct cdns_sierra_pll_mux {
enum cdns_sierra_phy_type {
TYPE_NONE,
TYPE_PCIE,
- TYPE_USB
+ TYPE_USB,
+ TYPE_QSGMII
};
enum cdns_sierra_ssc_mode {
@@ -639,6 +648,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst
*inst,
case PHY_TYPE_USB3:
inst->phy_type = TYPE_USB;
break;
+ case PHY_TYPE_QSGMII:
+ inst->phy_type = TYPE_QSGMII;
+ break;
default:
return -EINVAL;
}
@@ -903,6 +915,9 @@ static int cdns_sierra_phy_configure_multilink(struct
cdns_sierra_phy *sp)
regmap_write(regmap, reg_pairs[j].off,
reg_pairs[j].val);
}
}
+
+ if (phy_t1 == TYPE_QSGMII)
+ reset_deassert_bulk(sp->phys[node]->lnk_rst);
}
/* Take the PHY out of reset */
@@ -1133,6 +1148,72 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
return 0;
}
+/* QSGMII PHY PMA lane configuration */
+static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
+ {0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
+};
+
+static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {
+ .reg_pairs = qsgmii_phy_pma_ln_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),
+};
+
+/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {
+ {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
+ {0x, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
+ {0x, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
+};
+
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x0252, SIERRA_DET_STANDEC_E_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x0FFE, SIERRA_PSC_RX_A0_PREG},
+ {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
+ {0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
+ {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
+ {0x, SIERRA_DRVCTRL_ATTEN_PREG},
+ {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
+ {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
+ {0x, SIERRA_CREQ_EQ_CTRL_PREG},
+ {0x8422, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG
[PATCH v2 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations
From: Swapnil Jakhade
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 153 +--
1 file changed, 145 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 54d316d4ec41..5641c5672806 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -29,7 +29,7 @@
#include
#define NUM_SSC_MODE 3
-#define NUM_PHY_TYPE 3
+#define NUM_PHY_TYPE 4
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
@@ -183,6 +183,11 @@
(0xD000 + ((ln) * (0x800 >> (3 -
(offset)
#define SIERRA_PHY_ISO_LINK_CTRL 0xB
+/* PHY PMA lane registers */
+#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, offset) \
+ (0xF000 + ((ln) * (0x800 >> (3 -
(offset)
+#define SIERRA_PHY_PMA_XCVR_CTRL 0x000
+
#define SIERRA_MACRO_ID0x7364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -288,6 +293,8 @@ struct cdns_sierra_data {
u8 reg_offset_shift;
struct cdns_sierra_vals
*pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
+ struct cdns_sierra_vals
*phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
struct cdns_sierra_vals
*pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
@@ -306,6 +313,7 @@ struct cdns_sierra_phy {
struct regmap *regmap_phy_pcs_common_cdb;
struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pma_common_cdb;
+ struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
@@ -361,6 +369,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
+ struct cdns_sierra_vals *phy_pma_ln_vals;
const struct cdns_reg_pairs *reg_pairs;
struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap;
@@ -368,7 +377,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
int i, j;
/* Initialise the PHY registers, unless auto configured */
- if (phy->autoconf)
+ if (phy->autoconf || phy->nsubnodes > 1)
return 0;
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
@@ -384,6 +393,18 @@ static int cdns_sierra_phy_init(struct phy *gphy)
regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
}
+ /* PHY PMA lane registers configurations */
+ phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (phy_pma_ln_vals) {
+ reg_pairs = phy_pma_ln_vals->reg_pairs;
+ num_regs = phy_pma_ln_vals->num_regs;
+ for (i = 0; i < ins->num_lanes; i++) {
+ regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off,
reg_pairs[j].val);
+ }
+ }
+
/* PMA common registers configurations */
pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pma_cmn_vals) {
@@ -417,10 +438,13 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
- ret = reset_control_deassert(sp->phy_rst);
- if (ret) {
- dev_err(dev, "Failed to take the PHY out of reset\n");
- return ret;
+ if (sp->nsubnodes == 1) {
+ /* Take the PHY out of reset */
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
}
/* Take the PHY lane group out of reset */
@@ -776,6 +800,116 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_phy_pma_common_cdb = regmap;
+ for (i = 0; i < SIERRA_MA
[PATCH v2 20/25] phy: cadence: Sierra: Update single link PCIe register configuration
From: Swapnil Jakhade
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 218 ++-
1 file changed, 215 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 8518594b266b..54d316d4ec41 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -41,10 +41,15 @@
#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG0x4B
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
+#define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51
+#define SIERRA_CMN_PLLLC_SS_PREG 0x52
+#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53
+#define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG0x62
#define SIERRA_CMN_REFRCV_PREG 0x98
#define SIERRA_CMN_REFRCV1_PREG0xB8
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
+#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)
@@ -56,6 +61,7 @@
#define SIERRA_DET_STANDEC_E_PREG 0x004
#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008
#define SIERRA_PSM_A0IN_TMR_PREG 0x009
+#define SIERRA_PSM_A3IN_TMR_PREG 0x00C
#define SIERRA_PSM_DIAG_PREG 0x015
#define SIERRA_PSC_TX_A0_PREG 0x028
#define SIERRA_PSC_TX_A1_PREG 0x029
@@ -72,12 +78,15 @@
#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B
#define SIERRA_DFE_BIASTRIM_PREG 0x04C
#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
+#define SIERRA_DRVCTRL_BOOST_PREG 0x06F
#define SIERRA_CLKPATHCTRL_TMR_PREG0x081
#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086
#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
+#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C
#define SIERRA_CREQ_CCLKDET_MODE01_PREG0x08E
+#define SIERRA_RX_CTLE_CAL_PREG0x08F
#define SIERRA_RX_CTLE_MAINTENANCE_PREG0x091
#define SIERRA_CREQ_FSMCLK_SEL_PREG0x092
#define SIERRA_CREQ_EQ_CTRL_PREG 0x093
@@ -127,15 +136,27 @@
#define SIERRA_DEQ_ALUT12 0x114
#define SIERRA_DEQ_ALUT13 0x115
#define SIERRA_DEQ_DFETAP_CTRL_PREG0x128
+#define SIERRA_DEQ_DFETAP0 0x129
+#define SIERRA_DEQ_DFETAP1 0x12B
+#define SIERRA_DEQ_DFETAP2 0x12D
+#define SIERRA_DEQ_DFETAP3 0x12F
+#define SIERRA_DEQ_DFETAP4 0x131
#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134
+#define SIERRA_DEQ_PRECUR_PREG 0x138
+#define SIERRA_DEQ_POSTCUR_PREG0x140
+#define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
+#define SIERRA_DEQ_TAU_CTRL3_PREG 0x152
+#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158
#define SIERRA_DEQ_PICTRL_PREG 0x161
#define SIERRA_CPICAL_TMRVAL_MODE1_PREG0x170
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
+#define SIERRA_CPI_TRIM_PREG 0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG0x183
+#define SIERRA_EPI_CTRL_PREG 0x187
#define SIERRA_LFPSDET_SUPPORT_PREG0x188
#define SIERRA_LFPSFILT_NS_PREG0x18A
#define SIERRA_LFPSFILT_RD_PREG0x18B
@@ -985,6 +1006,146 @@ static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
};
+/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
+static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {
[PATCH v2 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
From: Swapnil Jakhade
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 35
1 file changed, 35 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 9267293703c3..df31fb3f19a3 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -153,6 +153,10 @@
#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
+/* PHY PMA common registers */
+#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000
+#define SIERRA_PHY_PMA_CMN_CTRL0x0
+
#define SIERRA_MACRO_ID0x7364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -173,6 +177,8 @@ static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
+static const struct reg_field pma_cmn_ready =
+ REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
@@ -270,9 +276,11 @@ struct cdns_sierra_phy {
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pcs_common_cdb;
+ struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
+ struct regmap_field *pma_cmn_ready;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
struct regmap_field
*cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
@@ -392,6 +400,17 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
+ /*
+* Wait for cmn_ready assertion
+* PHY_PMA_CMN_CTRL[0] == 1
+*/
+ ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,
+1000, PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for CMN ready\n");
+ return ret;
+ }
+
ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
val, val, 1000, PLL_LOCK_TIME);
if (ret < 0)
@@ -632,6 +651,14 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
}
sp->phy_pll_cfg_1 = field;
+ regmap = sp->regmap_phy_pma_common_cdb;
+ field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ sp->pma_cmn_ready = field;
+
for (i = 0; i < SIERRA_MAX_LANES; i++) {
regmap = sp->regmap_lane_cdb[i];
field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
@@ -681,6 +708,14 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_phy_pcs_common_cdb = regmap;
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pma_common_cdb = regmap;
+
return 0;
}
--
2.17.1
[PATCH v2 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
From: Swapnil Jakhade
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 41 +++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index df31fb3f19a3..8518594b266b 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -157,6 +157,11 @@
#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000
#define SIERRA_PHY_PMA_CMN_CTRL0x0
+/* PHY PCS lane registers */
+#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, offset) \
+ (0xD000 + ((ln) * (0x800 >> (3 -
(offset)
+#define SIERRA_PHY_ISO_LINK_CTRL 0xB
+
#define SIERRA_MACRO_ID0x7364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -181,6 +186,8 @@ static const struct reg_field pma_cmn_ready =
REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const struct reg_field phy_iso_link_ctrl_1 =
+ REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
static const char * const clk_names[] = {
[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
@@ -276,6 +283,7 @@ struct cdns_sierra_phy {
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pcs_common_cdb;
+ struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
@@ -286,6 +294,7 @@ struct cdns_sierra_phy {
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
+ struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -400,6 +409,15 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
+ if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
+ ret =
regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
+val, !val, 1000,
PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for PHY status ready\n");
+ return ret;
+ }
+ }
+
/*
* Wait for cmn_ready assertion
* PHY_PMA_CMN_CTRL[0] == 1
@@ -666,7 +684,17 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
return PTR_ERR(field);
}
- sp->pllctrl_lock[i] = field;
+ sp->pllctrl_lock[i] = field;
+ }
+
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ regmap = sp->regmap_phy_pcs_lane_cdb[i];
+ field = devm_regmap_field_alloc(dev, regmap,
phy_iso_link_ctrl_1);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane
%d failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->phy_iso_link_ctrl_1[i] = field;
}
return 0;
@@ -708,6 +736,17 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_phy_pcs_common_cdb = regmap;
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i,
reg_offset_shift);
+ regmap = cdns_regmap_init(dev, base, block_offset,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PCS lane CDB
regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pcs_lane_cdb[i] = regmap;
+ }
+
regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET,
block_offset_shift, reg_offset_shift);
if (IS_ERR(regmap)) {
--
2.17.1
[PATCH v2 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations
From: Swapnil Jakhade
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 951344f5ace5..9267293703c3 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -150,6 +150,7 @@
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
+#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID0x7364
@@ -251,6 +252,8 @@ struct cdns_sierra_data {
u32 id_value;
u8 block_offset_shift;
u8 reg_offset_shift;
+ struct cdns_sierra_vals
*pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+[NUM_SSC_MODE];
struct cdns_sierra_vals
*pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
@@ -321,6 +324,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs;
+ struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap;
u32 num_regs;
int i, j;
@@ -332,6 +336,16 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 2500);
+ /* PHY PCS common registers configurations */
+ pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pcs_cmn_vals) {
+ reg_pairs = pcs_cmn_vals->reg_pairs;
+ num_regs = pcs_cmn_vals->num_regs;
+ regmap = phy->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
+ }
+
/* PMA common registers configurations */
pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pma_cmn_vals) {
@@ -887,6 +901,16 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
return 0;
}
+/* PCIE PHY PCS common configuration */
+static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
+ {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
+};
+
+static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
+ .reg_pairs = pcie_phy_pcs_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
+};
+
/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@@ -1038,6 +1062,13 @@ static const struct cdns_sierra_data cdns_map_sierra = {
.id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x2,
.reg_offset_shift = 0x2,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = _phy_pcs_cmn_vals,
+ },
+ },
+ },
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
@@ -1068,6 +1099,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra
= {
.id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x0,
.reg_offset_shift = 0x1,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = _phy_pcs_cmn_vals,
+ },
+ },
+ },
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
--
2.17.1
[PATCH v2 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation
From: Swapnil Jakhade
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index e2f631e330da..951344f5ace5 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -149,7 +149,7 @@
#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
-#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000
+#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
#define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID0x7364
@@ -266,7 +266,7 @@ struct cdns_sierra_phy {
struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
- struct regmap *regmap_phy_config_ctrl;
+ struct regmap *regmap_phy_pcs_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
@@ -610,7 +610,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
sp->cmn_refrcv_refclk_termen_preg[i] = field;
}
- regmap = sp->regmap_phy_config_ctrl;
+ regmap = sp->regmap_phy_pcs_common_cdb;
field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
if (IS_ERR(field)) {
dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
@@ -659,13 +659,13 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_common_cdb = regmap;
- regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET,
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PCS_COMMON_OFFSET,
block_offset_shift, reg_offset_shift);
if (IS_ERR(regmap)) {
- dev_err(dev, "Failed to init PHY config and control regmap\n");
+ dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
return PTR_ERR(regmap);
}
- sp->regmap_phy_config_ctrl = regmap;
+ sp->regmap_phy_pcs_common_cdb = regmap;
return 0;
}
--
2.17.1
[PATCH v2 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree.
From: Swapnil Jakhade
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 745c34088a5b..e2f631e330da 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -234,6 +234,7 @@ struct cdns_sierra_inst {
u32 num_lanes;
u32 mlane;
struct reset_ctl_bulk *lnk_rst;
+ enum cdns_sierra_ssc_mode ssc_mode;
};
struct cdns_reg_pairs {
@@ -318,7 +319,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
struct cdns_sierra_data *init_data = phy->init_data;
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
- enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
+ enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap = phy->regmap;
u32 num_regs;
@@ -546,6 +547,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst
*inst,
return -EINVAL;
}
+ inst->ssc_mode = EXTERNAL_SSC;
+ ofnode_read_u32(child, "cdns,ssc-mode", >ssc_mode);
+
return 0;
}
--
2.17.1
[PATCH v2 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations
From: Swapnil Jakhade
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 188 ---
1 file changed, 135 insertions(+), 53 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 7e52a19f0dae..745c34088a5b 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -28,6 +28,9 @@
#include
#include
+#define NUM_SSC_MODE 3
+#define NUM_PHY_TYPE 3
+
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG0x0
@@ -214,8 +217,20 @@ struct cdns_sierra_pll_mux {
#define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl
+enum cdns_sierra_phy_type {
+ TYPE_NONE,
+ TYPE_PCIE,
+ TYPE_USB
+};
+
+enum cdns_sierra_ssc_mode {
+ NO_SSC,
+ EXTERNAL_SSC,
+ INTERNAL_SSC
+};
+
struct cdns_sierra_inst {
- u32 phy_type;
+ enum cdns_sierra_phy_type phy_type;
u32 num_lanes;
u32 mlane;
struct reset_ctl_bulk *lnk_rst;
@@ -226,18 +241,19 @@ struct cdns_reg_pairs {
u32 off;
};
+struct cdns_sierra_vals {
+ const struct cdns_reg_pairs *reg_pairs;
+ u32 num_regs;
+};
+
struct cdns_sierra_data {
u32 id_value;
u8 block_offset_shift;
u8 reg_offset_shift;
- u32 pcie_cmn_regs;
- u32 pcie_ln_regs;
- u32 usb_cmn_regs;
- u32 usb_ln_regs;
- struct cdns_reg_pairs *pcie_cmn_vals;
- struct cdns_reg_pairs *pcie_ln_vals;
- struct cdns_reg_pairs *usb_cmn_vals;
- struct cdns_reg_pairs *usb_ln_vals;
+ struct cdns_sierra_vals
*pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+[NUM_SSC_MODE];
+ struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
};
struct cdns_sierra_phy {
@@ -299,10 +315,14 @@ static int cdns_sierra_phy_init(struct phy *gphy)
{
struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
+ struct cdns_sierra_data *init_data = phy->init_data;
+ struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
+ enum cdns_sierra_phy_type phy_type = ins->phy_type;
+ enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
+ const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap = phy->regmap;
+ u32 num_regs;
int i, j;
- struct cdns_reg_pairs *cmn_vals, *ln_vals;
- u32 num_cmn_regs, num_ln_regs;
/* Initialise the PHY registers, unless auto configured */
if (phy->autoconf)
@@ -311,28 +331,25 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 2500);
- if (ins->phy_type == PHY_TYPE_PCIE) {
- num_cmn_regs = phy->init_data->pcie_cmn_regs;
- num_ln_regs = phy->init_data->pcie_ln_regs;
- cmn_vals = phy->init_data->pcie_cmn_vals;
- ln_vals = phy->init_data->pcie_ln_vals;
- } else if (ins->phy_type == PHY_TYPE_USB3) {
- num_cmn_regs = phy->init_data->usb_cmn_regs;
- num_ln_regs = phy->init_data->usb_ln_regs;
- cmn_vals = phy->init_data->usb_cmn_vals;
- ln_vals = phy->init_data->usb_ln_vals;
- } else {
- return -EINVAL;
+ /* PMA common registers configurations */
+ pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_cmn_vals) {
+ reg_pairs = pma_cmn_vals->reg_pairs;
+ num_regs = pma_cmn_vals->num_regs;
+ regmap = phy->regmap_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
}
- regmap = phy->regmap_common_cdb;
- for (j = 0; j < num_cmn_regs ; j++)
- regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
-
- for (i = 0; i < ins->num_lanes; i++) {
- for (j = 0; j < num_ln_regs ; j++) {
+ /* PMA TX lane registers configurations */
+ pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_ln_vals) {
+ reg_pairs = pma_ln_vals->reg_pairs;
+ num_regs
[PATCH v2 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
From: Swapnil Jakhade Add binding to specify Spread Spectrum Clocking mode used Signed-off-by: Swapnil Jakhade Signed-off-by: Aswath Govindraju --- include/dt-bindings/phy/phy-cadence.h | 4 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h index 4652bcb86265..0122c6067b17 100644 --- a/include/dt-bindings/phy/phy-cadence.h +++ b/include/dt-bindings/phy/phy-cadence.h @@ -17,4 +17,8 @@ #define CDNS_SIERRA_PLL_CMNLC 0 #define CDNS_SIERRA_PLL_CMNLC1 1 +#define SIERRA_SERDES_NO_SSC 0 +#define SIERRA_SERDES_EXTERNAL_SSC 1 +#define SIERRA_SERDES_INTERNAL_SSC 2 + #endif /* _DT_BINDINGS_CADENCE_SERDES_H */ -- 2.17.1
[PATCH v2 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.
Signed-off-by: Aswath Govindraju
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 10
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 24 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 3ca9b5c801f0..938e978a6b66 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -232,3 +232,13 @@
_serdes_mux {
u-boot,mux-autoprobe;
};
+
+ {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+_pcie_link {
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <_pll1_refclk>;
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 4b2362a5dd05..8299463c3e01 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -8,6 +8,7 @@
#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
+#include
/ {
aliases {
@@ -361,3 +362,26 @@
_udmap {
ti,sci = <_tifs>;
};
+
+_pll1_refclk {
+ assigned-clocks = <_pll1_refclk>;
+ assigned-clock-parents = <_refclk1>;
+};
+
+_refclk_dig {
+ assigned-clocks = <_refclk_dig>;
+ assigned-clock-parents = <_refclk1>;
+};
+
+ {
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <_pll1_refclk>;
+
+ serdes0_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <_wiz0 1>;
+ };
+};
--
2.17.1
[PATCH v2 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0
Add support for probing, initializing and powering, SerDes0 instance.
Signed-off-by: Aswath Govindraju
---
board/ti/j721e/evm.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 077d83420c9c..ad85b9d50115 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -413,6 +413,40 @@ void configure_serdes_torrent(void)
printf("phy_power_on failed !!\n");
}
+void configure_serdes_sierra(void)
+{
+ struct udevice *dev, *lnk_dev;
+ struct phy serdes;
+ int ret, count, i;
+
+ if (!IS_ENABLED(CONFIG_PHY_CADENCE_SIERRA))
+ return;
+
+ ret = uclass_get_device_by_driver(UCLASS_PHY,
+ DM_DRIVER_GET(sierra_phy_provider),
+ );
+ if (ret)
+ printf("Sierra init failed:%d\n", ret);
+
+ serdes.dev = dev;
+ serdes.id = 0;
+
+ count = device_get_child_count(dev);
+ for (i = 0; i < count; i++) {
+ ret = device_get_child(dev, i, _dev);
+ if (ret)
+ printf("probe of sierra child node %d failed\n", i);
+ }
+
+ ret = generic_phy_init();
+ if (ret)
+ printf("phy_init failed!!\n");
+
+ ret = generic_phy_power_on();
+ if (ret)
+ printf("phy_power_on failed !!\n");
+}
+
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@@ -426,6 +460,9 @@ int board_late_init(void)
if (board_is_j7200_som())
configure_serdes_torrent();
+ if (board_is_j721e_som())
+ configure_serdes_sierra();
+
return 0;
}
--
2.17.1
[PATCH v2 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju --- drivers/phy/ti/phy-j721e-wiz.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index d74efcd21208..686cdc6f7c23 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -523,7 +523,7 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl) return ret; } - if (wiz->lane_phy_type[id - 1] == PHY_TYPE_PCIE) + if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); else ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); -- 2.17.1
[PATCH v2 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 223 +--
1 file changed, 210 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index af67df6d06cb..7e52a19f0dae 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -13,6 +13,7 @@
*/
#include
#include
+#include
#include
#include
#include
@@ -24,11 +25,13 @@
#include
#include
#include
+#include
#include
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG0x0
+#define SIERRA_CMN_PLLLC_GEN_PREG 0x42
#define SIERRA_CMN_PLLLC_MODE_PREG 0x48
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
@@ -36,6 +39,9 @@
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG0x62
+#define SIERRA_CMN_REFRCV_PREG 0x98
+#define SIERRA_CMN_REFRCV1_PREG0xB8
+#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)
@@ -147,13 +153,18 @@
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
-#define CDNS_SIERRA_INPUT_CLOCKS 3
+#define CDNS_SIERRA_INPUT_CLOCKS 5
enum cdns_sierra_clock_input {
PHY_CLK,
CMN_REFCLK_DIG_DIV,
CMN_REFCLK1_DIG_DIV,
+ PLL0_REFCLK,
+ PLL1_REFCLK,
};
+#define SIERRA_NUM_CMN_PLLC2
+#define SIERRA_NUM_CMN_PLLC_PARENTS2
+
static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
@@ -161,6 +172,44 @@ static const struct reg_field phy_pll_cfg_1 =
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const char * const clk_names[] = {
+ [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
+ [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
+};
+
+enum cdns_sierra_cmn_plllc {
+ CMN_PLLLC,
+ CMN_PLLLC1,
+};
+
+struct cdns_sierra_pll_mux_reg_fields {
+ struct reg_fieldpfdclk_sel_preg;
+ struct reg_fieldplllc1en_field;
+ struct reg_fieldtermen_field;
+};
+
+static const struct cdns_sierra_pll_mux_reg_fields
cmn_plllc_pfdclk1_sel_preg[] = {
+ [CMN_PLLLC] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
+ },
+ [CMN_PLLLC1] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
+ },
+};
+
+struct cdns_sierra_pll_mux {
+ struct cdns_sierra_phy *sp;
+ struct clk *clk;
+ struct clk *parent_clks[2];
+ struct regmap_field *pfdclk_sel_preg;
+ struct regmap_field *plllc1en_field;
+ struct regmap_field *termen_field;
+};
+
#define reset_control_assert(rst) cdns_reset_assert(rst)
#define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl
@@ -191,12 +240,6 @@ struct cdns_sierra_data {
struct cdns_reg_pairs *usb_ln_vals;
};
-struct cdns_regmap_cdb_context {
- struct udevice *dev;
- void __iomem *base;
- u8 reg_offset_shift;
-};
-
struct cdns_sierra_phy {
struct udevice *dev;
void *base;
@@ -211,6 +254,9 @@ struct cdns_sierra_phy {
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
+ struct regmap_field
*cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
int nsubnodes;
u32 num
[PATCH v2 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 116 +++
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 90699f2fa653..af67df6d06cb 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -203,7 +203,7 @@ struct cdns_sierra_phy {
size_t size;
struct regmap *regmap;
struct cdns_sierra_data *init_data;
- struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
+ struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_config_ctrl;
@@ -242,8 +242,8 @@ static inline struct cdns_sierra_inst
*phy_get_drvdata(struct phy *phy)
return NULL;
for (index = 0; index < sp->nsubnodes; index++) {
- if (phy->id == sp->phys[index].mlane)
- return >phys[index];
+ if (phy->id == sp->phys[index]->mlane)
+ return sp->phys[index];
}
return NULL;
@@ -500,13 +500,79 @@ static int cdns_sierra_phy_get_resets(struct
cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_bind_link_nodes(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct driver *link_drv;
+ ofnode child;
+ int rc;
+
+ link_drv = lists_driver_lookup_name("sierra_phy_link");
+ if (!link_drv) {
+ dev_err(dev, "Cannot find driver 'sierra_phy_link'\n");
+ return -ENOENT;
+ }
+
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (!(ofnode_name_eq(child, "phy") ||
+ ofnode_name_eq(child, "link")))
+ continue;
+
+ rc = device_bind(dev, link_drv, "link", NULL, child, NULL);
+ if (rc) {
+ dev_err(dev, "cannot bind driver for link\n");
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int cdns_sierra_link_probe(struct udevice *dev)
+{
+ struct cdns_sierra_inst *inst = dev_get_priv(dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
+ struct reset_ctl_bulk *rst;
+ int ret, node;
+
+ rst = devm_reset_bulk_get_by_node(dev, dev_ofnode(dev));
+ if (IS_ERR(rst)) {
+ ret = PTR_ERR(rst);
+ dev_err(dev, "failed to get reset\n");
+ return ret;
+ }
+ inst->lnk_rst = rst;
+
+ ret = cdns_sierra_get_optional(inst, dev_ofnode(dev));
+ if (ret) {
+ dev_err(dev, "missing property in node\n");
+ return ret;
+ }
+ node = sp->nsubnodes;
+ sp->phys[node] = inst;
+ sp->nsubnodes += 1;
+ sp->num_lanes += inst->num_lanes;
+
+ /* If more than one subnode, configure the PHY as multilink */
+ if (!sp->autoconf && sp->nsubnodes > 1)
+ regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sierra_phy_link) = {
+ .name = "sierra_phy_link",
+ .id = UCLASS_PHY,
+ .probe = cdns_sierra_link_probe,
+ .priv_auto = sizeof(struct cdns_sierra_inst),
+};
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
int ret, node = 0;
- ofnode child;
sp->dev = dev;
@@ -558,46 +624,14 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
}
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
-
- ofnode_for_each_subnode(child, dev_ofnode(dev)) {
- if (!(ofnode_name_eq(child, "phy") ||
- ofnode_name_eq(child, "link")))
- continue;
-
- sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
-child);
- if (IS_ERR(sp->phys[node].lnk_rst)) {
- ret = PTR_ERR(sp->phys[node].lnk_rst);
- dev_err(dev, "failed to get reset %s\n",
- ofnode_get_name(child));
- goto put_child2;
- }
-
- if (!sp->autoconf) {
- ret = cdns_sierra_get_optional(>phys[node], child);
- if (ret) {
- dev_err(dev, "missing
[PATCH v2 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback
From: Kishon Vijay Abraham I Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Aswath Govindraju --- drivers/phy/cadence/phy-cadence-sierra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 0bc60bb73e88..90699f2fa653 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -617,6 +617,8 @@ static int cdns_sierra_phy_remove(struct udevice *dev) for (i = 0; i < phy->nsubnodes; i++) reset_assert_bulk(phy->phys[i].lnk_rst); + clk_disable_unprepare(phy->input_clks[PHY_CLK]); + return 0; } -- 2.17.1
[PATCH v2 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
From: Kishon Vijay Abraham I
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 25 ++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index eaa32939c1c2..0bc60bb73e88 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -147,6 +147,13 @@
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
+#define CDNS_SIERRA_INPUT_CLOCKS 3
+enum cdns_sierra_clock_input {
+ PHY_CLK,
+ CMN_REFCLK_DIG_DIV,
+ CMN_REFCLK1_DIG_DIV,
+};
+
static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
@@ -204,9 +211,7 @@ struct cdns_sierra_phy {
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
- struct clk *clk;
- struct clk *cmn_refclk;
- struct clk *cmn_refclk1;
+ struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -257,8 +262,8 @@ static int cdns_sierra_phy_init(struct phy *gphy)
if (phy->autoconf)
return 0;
- clk_set_rate(phy->cmn_refclk, 2500);
- clk_set_rate(phy->cmn_refclk1, 2500);
+ clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
+ clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 2500);
if (ins->phy_type == PHY_TYPE_PCIE) {
num_cmn_regs = phy->init_data->pcie_cmn_regs;
@@ -459,7 +464,7 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
dev_err(dev, "failed to get clock phy_clk\n");
return PTR_ERR(clk);
}
- sp->clk = clk;
+ sp->input_clks[PHY_CLK] = clk;
clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
if (IS_ERR(clk)) {
@@ -467,7 +472,7 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
ret = PTR_ERR(clk);
return ret;
}
- sp->cmn_refclk = clk;
+ sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
if (IS_ERR(clk)) {
@@ -475,7 +480,7 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
ret = PTR_ERR(clk);
return ret;
}
- sp->cmn_refclk1 = clk;
+ sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
return 0;
}
@@ -539,7 +544,7 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- ret = clk_prepare_enable(sp->clk);
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
if (ret)
return ret;
@@ -594,7 +599,7 @@ put_child:
put_child2:
clk_disable:
- clk_disable_unprepare(sp->clk);
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
return ret;
}
--
2.17.1
[PATCH v2 05/25] phy: cadence: Sierra: Move all reset_control_get*() to a separate function
From: Kishon Vijay Abraham I
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index d07cf1d97df2..eaa32939c1c2 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -480,6 +480,21 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct reset_control *rst;
+
+ rst = devm_reset_control_get(dev, "sierra_reset");
+ if (IS_ERR(rst)) {
+ dev_err(dev, "failed to get reset\n");
+ return PTR_ERR(rst);
+ }
+ sp->phy_rst = rst;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
@@ -520,6 +535,10 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return PTR_ERR(sp->phy_rst);
}
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
+
ret = clk_prepare_enable(sp->clk);
if (ret)
return ret;
--
2.17.1
[PATCH v2 02/25] phy: cadence: Sierra: Fix PHY power_on sequence
From: Kishon Vijay Abraham I
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 6b26b30dcf9d..bd42145fcacc 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -296,6 +296,12 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
+
/* Take the PHY lane group out of reset */
ret = reset_deassert_bulk(ins->lnk_rst);
if (ret) {
@@ -544,7 +550,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (!sp->autoconf && sp->nsubnodes > 1)
regmap_field_write(sp->phy_pll_cfg_1, 0x1);
- reset_control_deassert(sp->phy_rst);
dev_info(dev, "sierra probed\n");
return 0;
--
2.17.1
[PATCH v2 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function
From: Kishon Vijay Abraham I
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 45d6d6a796a5..d07cf1d97df2 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -448,13 +448,44 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
return 0;
}
+static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->clk = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk1 = clk;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
int ret, node = 0;
- struct clk *clk;
ofnode child;
sp->dev = dev;
@@ -479,11 +510,9 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- sp->clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(sp->clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(sp->clk);
- }
+ ret = cdns_sierra_phy_get_clocks(sp, dev);
+ if (ret)
+ return ret;
sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
if (IS_ERR(sp->phy_rst)) {
@@ -491,22 +520,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return PTR_ERR(sp->phy_rst);
}
- clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk = clk;
-
- clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk1 clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk1 = clk;
-
ret = clk_prepare_enable(sp->clk);
if (ret)
return ret;
--
2.17.1
[PATCH v2 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
From: Kishon Vijay Abraham I
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index bd42145fcacc..45d6d6a796a5 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -523,6 +523,10 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (!(ofnode_name_eq(child, "phy") ||
+ ofnode_name_eq(child, "link")))
+ continue;
+
sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
child);
if (IS_ERR(sp->phys[node].lnk_rst)) {
--
2.17.1
[PATCH v2 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state
From: Sanket Parmar
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 27
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 715def6f173b..6b26b30dcf9d 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -606,10 +606,10 @@ static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[]
= {
static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
{0x000F, SIERRA_DET_STANDEC_B_PREG},
- {0x00A5, SIERRA_DET_STANDEC_C_PREG},
+ {0x55A5, SIERRA_DET_STANDEC_C_PREG},
{0x69ad, SIERRA_DET_STANDEC_D_PREG},
{0x0241, SIERRA_DET_STANDEC_E_PREG},
- {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
+ {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
{0xCF00, SIERRA_PSM_DIAG_PREG},
{0x001F, SIERRA_PSC_TX_A0_PREG},
@@ -617,7 +617,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x0003, SIERRA_PSC_TX_A2_PREG},
{0x0003, SIERRA_PSC_TX_A3_PREG},
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
- {0x0619, SIERRA_PSC_RX_A1_PREG},
+ {0x0003, SIERRA_PSC_RX_A1_PREG},
{0x0003, SIERRA_PSC_RX_A2_PREG},
{0x0001, SIERRA_PSC_RX_A3_PREG},
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
@@ -626,19 +626,19 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] =
{
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
{0x, SIERRA_DRVCTRL_ATTEN_PREG},
- {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG},
- {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
- {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
- {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
{0x, SIERRA_CREQ_EQ_CTRL_PREG},
- {0x8000, SIERRA_CREQ_SPARE_PREG},
+ {0x, SIERRA_CREQ_SPARE_PREG},
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
- {0x8453, SIERRA_CTLELUT_CTRL_PREG},
- {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG},
- {0x4110, SIERRA_DFE_SMP_RATESEL_PREG},
- {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
+ {0x8452, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
+ {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
+ {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
@@ -646,7 +646,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
- {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG},
+ {0x, SIERRA_DEQ_VGATUNE_CTRL_PREG},
{0x0014, SIERRA_DEQ_GLUT0},
{0x0014, SIERRA_DEQ_GLUT1},
{0x0014, SIERRA_DEQ_GLUT2},
@@ -693,6 +693,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x000F, SIERRA_LFPSFILT_NS_PREG},
{0x0009, SIERRA_LFPSFILT_RD_PREG},
{0x0001, SIERRA_LFPSFILT_MP_PREG},
+ {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
{0x8009, SIERRA_SDFILT_L2H_PREG},
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
--
2.17.1
[PATCH v2 00/25] SIERRA: Add support for Mulitlink Configuration
The following series of patches add support for PCIe + QSGMII multilink configuration on J721e EVM. The PHY lanes are configured in U-Boot and, PCIe driver in Kernel and QSGMII driver in the ethernet firmware use them. Notes: - Patches 1 -8 and 13 - 22 are ported from upstream kernel v5.17-rc1 - Patch 24, syncs with linux kernel dt, with the following patch https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=608996 Changes since v1: - Fixed the logic for skipping multilink configuration in patch 23 - Fixed the offset calcualation for SIERRA_PHY_PCS_LANE_CDB_OFFSET and SIERRA_PHY_PMA_LANE_CDB_OFFSET in patches 18 and 21. Aswath Govindraju (8): phy: cadence: Sierra: Add a UCLASS_PHY device for links phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE board: ti: j721e: evm.c: Add support for probing SerDes0 arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 phy: cadence: Sierra: Add support for skipping configuration arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII include: configs: j721e_evm: Add support to boot ethfw core in j721e Kishon Vijay Abraham I (6): phy: cadence: Sierra: Fix PHY power_on sequence phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes phy: cadence: Sierra: Move all clk_get_*() to a separate function phy: cadence: Sierra: Move all reset_control_get*() to a separate function phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Sanket Parmar (1): phy: cadence: sierra: Fix for USB3 U1/U2 state Swapnil Jakhade (10): phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree. phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration .../k3-j721e-common-proc-board-u-boot.dtsi| 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 14 +- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 32 + board/ti/j721e/evm.c | 37 + configs/j721e_evm_a72_defconfig |2 +- drivers/phy/cadence/phy-cadence-sierra.c | 1537 +++-- drivers/phy/ti/phy-j721e-wiz.c|2 +- include/configs/j721e_evm.h | 19 +- include/dt-bindings/phy/phy-cadence.h |4 + 9 files changed, 1494 insertions(+), 168 deletions(-) -- 2.17.1
[PATCH 02/25] phy: cadence: Sierra: Fix PHY power_on sequence
From: Kishon Vijay Abraham I
Commit 39b823381d9d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 6b26b30dcf9d..bd42145fcacc 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -296,6 +296,12 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
+
/* Take the PHY lane group out of reset */
ret = reset_deassert_bulk(ins->lnk_rst);
if (ret) {
@@ -544,7 +550,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (!sp->autoconf && sp->nsubnodes > 1)
regmap_field_write(sp->phy_pll_cfg_1, 0x1);
- reset_control_deassert(sp->phy_rst);
dev_info(dev, "sierra probed\n");
return 0;
--
2.17.1
[PATCH 06/25] phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy"
From: Kishon Vijay Abraham I
Instead of having separate structure members for each input clock, add
an array for the input clocks within "struct cdns_sierra_phy". This is
in preparation for adding more input clocks required for supporting
additional clock combination.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 25 ++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index eaa32939c1c2..0bc60bb73e88 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -147,6 +147,13 @@
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
+#define CDNS_SIERRA_INPUT_CLOCKS 3
+enum cdns_sierra_clock_input {
+ PHY_CLK,
+ CMN_REFCLK_DIG_DIV,
+ CMN_REFCLK1_DIG_DIV,
+};
+
static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
@@ -204,9 +211,7 @@ struct cdns_sierra_phy {
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
- struct clk *clk;
- struct clk *cmn_refclk;
- struct clk *cmn_refclk1;
+ struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -257,8 +262,8 @@ static int cdns_sierra_phy_init(struct phy *gphy)
if (phy->autoconf)
return 0;
- clk_set_rate(phy->cmn_refclk, 2500);
- clk_set_rate(phy->cmn_refclk1, 2500);
+ clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
+ clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 2500);
if (ins->phy_type == PHY_TYPE_PCIE) {
num_cmn_regs = phy->init_data->pcie_cmn_regs;
@@ -459,7 +464,7 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
dev_err(dev, "failed to get clock phy_clk\n");
return PTR_ERR(clk);
}
- sp->clk = clk;
+ sp->input_clks[PHY_CLK] = clk;
clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
if (IS_ERR(clk)) {
@@ -467,7 +472,7 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
ret = PTR_ERR(clk);
return ret;
}
- sp->cmn_refclk = clk;
+ sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;
clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
if (IS_ERR(clk)) {
@@ -475,7 +480,7 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
ret = PTR_ERR(clk);
return ret;
}
- sp->cmn_refclk1 = clk;
+ sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;
return 0;
}
@@ -539,7 +544,7 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- ret = clk_prepare_enable(sp->clk);
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
if (ret)
return ret;
@@ -594,7 +599,7 @@ put_child:
put_child2:
clk_disable:
- clk_disable_unprepare(sp->clk);
+ clk_disable_unprepare(sp->input_clks[PHY_CLK]);
return ret;
}
--
2.17.1
[PATCH 03/25] phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes
From: Kishon Vijay Abraham I
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index bd42145fcacc..45d6d6a796a5 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -523,6 +523,10 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (!(ofnode_name_eq(child, "phy") ||
+ ofnode_name_eq(child, "link")))
+ continue;
+
sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
child);
if (IS_ERR(sp->phys[node].lnk_rst)) {
--
2.17.1
[PATCH 23/25] phy: cadence: Sierra: Add support for skipping configuration
Skip the phy configuration if the required configurations were done in an
earlier boot stage.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 55 +---
1 file changed, 40 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 28921d90261e..3853bddb617d 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -13,6 +13,7 @@
*/
#include
#include
+#include
#include
#include
#include
@@ -28,6 +29,8 @@
#include
#include
+#define usleep_range(a, b) udelay((b))
+
#define NUM_SSC_MODE 3
#define NUM_PHY_TYPE 4
@@ -336,6 +339,7 @@ struct cdns_sierra_phy {
int nsubnodes;
u32 num_lanes;
bool autoconf;
+ unsigned int already_configured;
};
static inline int cdns_reset_assert(struct reset_control *rst)
@@ -386,7 +390,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
int i, j;
/* Initialise the PHY registers, unless auto configured */
- if (phy->autoconf || phy->nsubnodes > 1)
+ if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1)
return 0;
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
@@ -447,6 +451,11 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
+ if (sp->already_configured) {
+ usleep_range(5000, 1);
+ return 0;
+ }
+
if (sp->nsubnodes == 1) {
/* Take the PHY out of reset */
ret = reset_control_deassert(sp->phy_rst);
@@ -934,13 +943,6 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
struct clk *clk;
int ret;
- clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(clk);
- }
- sp->input_clks[PHY_CLK] = clk;
-
clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
if (IS_ERR(clk)) {
dev_err(dev, "cmn_refclk_dig_div clock not found\n");
@@ -976,6 +978,25 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->input_clks[PHY_CLK] = clk;
+
+ ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
+ if (ret)
+ return ret;
+
+ return 0;
+}
static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
struct udevice *dev)
{
@@ -1045,7 +1066,7 @@ static int cdns_sierra_link_probe(struct udevice *dev)
sp->num_lanes += inst->num_lanes;
/* If more than one subnode, configure the PHY as multilink */
- if (!sp->autoconf && sp->nsubnodes > 1) {
+ if (!(sp->autoconf || sp->already_configured) && sp->nsubnodes > 1) {
ret = cdns_sierra_phy_configure_multilink(sp);
if (ret)
return ret;
@@ -1098,13 +1119,17 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- ret = cdns_sierra_phy_get_resets(sp, dev);
- if (ret)
- return ret;
+ regmap_field_read(sp->pma_cmn_ready, >already_configured);
- ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);
- if (ret)
- return ret;
+ if (!(sp->already_configured)) {
+ ret = cdns_sierra_phy_clk(sp);
+ if (ret)
+ return ret;
+
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
+ }
/* Check that PHY is present */
regmap_field_read(sp->macro_id_type, _value);
--
2.17.1
[PATCH 25/25] include: configs: j721e_evm: Add support to boot ethfw core in j721e
Add configs to enable booting ethfw core in j721e
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 19 ++-
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 2e452739034e..8f412d65a8ac 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -29,7 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run get_kern_${boot}; run get_fdt_${boot}; run
get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index abea7517e8b5..627c363ce66e 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -119,6 +119,16 @@
/* Set the default list of remote processors to boot */
#if defined(CONFIG_TARGET_J721E_A72_EVM) ||
defined(CONFIG_TARGET_J7200_A72_EVM)
+#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
+ "dorprocboot=1\0" \
+ "do_main_cpsw0_qsgmii_phyinit=1\0" \
+ "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
+"gpio clear gpio@22_16\0" \
+ "main_cpsw0_qsgmii_phyinit="\
+ "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
+ "test ${boot} = mmc; then " \
+ "run init_main_cpsw0_qsgmii_phy;" \
+ "fi;\0"
#ifdef DEFAULT_RPROCS
#undef DEFAULT_RPROCS
#endif
@@ -136,15 +146,6 @@
#endif /* CONFIG_TARGET_J721E_A72_EVM */
#ifdef CONFIG_TARGET_J7200_A72_EVM
-#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \
- "do_main_cpsw0_qsgmii_phyinit=1\0" \
- "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \
-"gpio clear gpio@22_16\0" \
- "main_cpsw0_qsgmii_phyinit="\
- "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot}
-eq 1 && " \
- "test ${boot} = mmc; then " \
- "run init_main_cpsw0_qsgmii_phy;" \
- "fi;\0"
#define DEFAULT_RPROCS "" \
"2 /lib/firmware/j7200-main-r5f0_0-fw " \
"3 /lib/firmware/j7200-main-r5f0_1-fw "
--
2.17.1
[PATCH 24/25] arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII
Add support for QSGMII multilink configuration.
Signed-off-by: Aswath Govindraju
---
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 5 +
arch/arm/dts/k3-j721e-common-proc-board.dts| 14 +++---
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 12 ++--
3 files changed, 26 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 938e978a6b66..677a72d2a241 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -242,3 +242,8 @@
assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
assigned-clock-parents = <_pll1_refclk>;
};
+
+_qsgmii_link {
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <_pll1_refclk>;
+};
diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 8bd02d9e28ad..f3b6302a4317 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -345,7 +345,7 @@
};
_ln_ctrl {
- idle-states = ,
,
+ idle-states = ,
,
,
,
,
,
,
,
@@ -671,8 +671,8 @@
};
{
- assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <_pll1_refclk>;
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>, <
CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <_pll1_refclk>, <_pll1_refclk>;
serdes0_pcie_link: phy@0 {
reg = <0>;
@@ -681,6 +681,14 @@
cdns,phy-type = ;
resets = <_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <_wiz0 2>;
+ };
};
{
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 8299463c3e01..5362c528703d 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -374,8 +374,8 @@
};
{
- assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
- assigned-clock-parents = <_pll1_refclk>;
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>, <
CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <_pll1_refclk>, <_pll1_refclk>;
serdes0_pcie_link: link@0 {
reg = <0>;
@@ -384,4 +384,12 @@
cdns,phy-type = ;
resets = <_wiz0 1>;
};
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <_wiz0 2>;
+ };
};
--
2.17.1
[PATCH 22/25] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration
From: Swapnil Jakhade
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 378 ++-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 43a0f6537ab6..28921d90261e 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -50,6 +50,9 @@
#define SIERRA_CMN_REFRCV1_PREG0xB8
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
+#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG 0xCA
+#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG 0xD0
+#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG 0xE2
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)
@@ -63,6 +66,9 @@
#define SIERRA_PSM_A0IN_TMR_PREG 0x009
#define SIERRA_PSM_A3IN_TMR_PREG 0x00C
#define SIERRA_PSM_DIAG_PREG 0x015
+#define SIERRA_PSC_LN_A3_PREG 0x023
+#define SIERRA_PSC_LN_A4_PREG 0x024
+#define SIERRA_PSC_LN_IDLE_PREG0x026
#define SIERRA_PSC_TX_A0_PREG 0x028
#define SIERRA_PSC_TX_A1_PREG 0x029
#define SIERRA_PSC_TX_A2_PREG 0x02A
@@ -72,6 +78,7 @@
#define SIERRA_PSC_RX_A2_PREG 0x032
#define SIERRA_PSC_RX_A3_PREG 0x033
#define SIERRA_PLLCTRL_SUBRATE_PREG0x03A
+#define SIERRA_PLLCTRL_GEN_A_PREG 0x03B
#define SIERRA_PLLCTRL_GEN_D_PREG 0x03E
#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG0x03F
#define SIERRA_PLLCTRL_STATUS_PREG 0x044
@@ -154,6 +161,7 @@
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
+#define SIERRA_CPI_RESBIAS_BIN_PREG0x17E
#define SIERRA_CPI_TRIM_PREG 0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG0x183
#define SIERRA_EPI_CTRL_PREG 0x187
@@ -260,7 +268,8 @@ struct cdns_sierra_pll_mux {
enum cdns_sierra_phy_type {
TYPE_NONE,
TYPE_PCIE,
- TYPE_USB
+ TYPE_USB,
+ TYPE_QSGMII
};
enum cdns_sierra_ssc_mode {
@@ -639,6 +648,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst
*inst,
case PHY_TYPE_USB3:
inst->phy_type = TYPE_USB;
break;
+ case PHY_TYPE_QSGMII:
+ inst->phy_type = TYPE_QSGMII;
+ break;
default:
return -EINVAL;
}
@@ -903,6 +915,9 @@ static int cdns_sierra_phy_configure_multilink(struct
cdns_sierra_phy *sp)
regmap_write(regmap, reg_pairs[j].off,
reg_pairs[j].val);
}
}
+
+ if (phy_t1 == TYPE_QSGMII)
+ reset_deassert_bulk(sp->phys[node]->lnk_rst);
}
/* Take the PHY out of reset */
@@ -1133,6 +1148,72 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
return 0;
}
+/* QSGMII PHY PMA lane configuration */
+static struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {
+ {0x9010, SIERRA_PHY_PMA_XCVR_CTRL}
+};
+
+static struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {
+ .reg_pairs = qsgmii_phy_pma_ln_regs,
+ .num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),
+};
+
+/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {
+ {0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},
+ {0x, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},
+ {0x, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}
+};
+
+static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {
+ {0xFC08, SIERRA_DET_STANDEC_A_PREG},
+ {0x0252, SIERRA_DET_STANDEC_E_PREG},
+ {0x0004, SIERRA_PSC_LN_IDLE_PREG},
+ {0x0FFE, SIERRA_PSC_RX_A0_PREG},
+ {0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},
+ {0x0001, SIERRA_PLLCTRL_GEN_A_PREG},
+ {0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},
+ {0x, SIERRA_DRVCTRL_ATTEN_PREG},
+ {0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
+ {0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},
+ {0x, SIERRA_CREQ_EQ_CTRL_PREG},
+ {0x8422, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4111, SIERRA_DFE_ECMP_RATESEL_PREG
[PATCH 21/25] phy: cadence: Sierra: Add support for PHY multilink configurations
From: Swapnil Jakhade
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 153 +--
1 file changed, 145 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 323cfe470bd5..43a0f6537ab6 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -29,7 +29,7 @@
#include
#define NUM_SSC_MODE 3
-#define NUM_PHY_TYPE 3
+#define NUM_PHY_TYPE 4
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
@@ -183,6 +183,11 @@
(0xD000 + ((ln) * (0x800 >> (2 -
(offset)
#define SIERRA_PHY_ISO_LINK_CTRL 0xB
+/* PHY PMA lane registers */
+#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, offset) \
+ (0xF000 + ((ln) * (0x800 >> (2 -
(offset)
+#define SIERRA_PHY_PMA_XCVR_CTRL 0x000
+
#define SIERRA_MACRO_ID0x7364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -288,6 +293,8 @@ struct cdns_sierra_data {
u8 reg_offset_shift;
struct cdns_sierra_vals
*pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
+ struct cdns_sierra_vals
*phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
struct cdns_sierra_vals
*pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
@@ -306,6 +313,7 @@ struct cdns_sierra_phy {
struct regmap *regmap_phy_pcs_common_cdb;
struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pma_common_cdb;
+ struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
@@ -361,6 +369,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
+ struct cdns_sierra_vals *phy_pma_ln_vals;
const struct cdns_reg_pairs *reg_pairs;
struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap;
@@ -368,7 +377,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
int i, j;
/* Initialise the PHY registers, unless auto configured */
- if (phy->autoconf)
+ if (phy->autoconf || phy->nsubnodes > 1)
return 0;
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
@@ -384,6 +393,18 @@ static int cdns_sierra_phy_init(struct phy *gphy)
regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
}
+ /* PHY PMA lane registers configurations */
+ phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (phy_pma_ln_vals) {
+ reg_pairs = phy_pma_ln_vals->reg_pairs;
+ num_regs = phy_pma_ln_vals->num_regs;
+ for (i = 0; i < ins->num_lanes; i++) {
+ regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];
+ for (j = 0; j < num_regs; j++)
+ regmap_write(regmap, reg_pairs[j].off,
reg_pairs[j].val);
+ }
+ }
+
/* PMA common registers configurations */
pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pma_cmn_vals) {
@@ -417,10 +438,13 @@ static int cdns_sierra_phy_on(struct phy *gphy)
u32 val;
int ret;
- ret = reset_control_deassert(sp->phy_rst);
- if (ret) {
- dev_err(dev, "Failed to take the PHY out of reset\n");
- return ret;
+ if (sp->nsubnodes == 1) {
+ /* Take the PHY out of reset */
+ ret = reset_control_deassert(sp->phy_rst);
+ if (ret) {
+ dev_err(dev, "Failed to take the PHY out of reset\n");
+ return ret;
+ }
}
/* Take the PHY lane group out of reset */
@@ -776,6 +800,116 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_phy_pma_common_cdb = regmap;
+ for (i = 0; i < SIERRA_MA
[PATCH 20/25] phy: cadence: Sierra: Update single link PCIe register configuration
From: Swapnil Jakhade
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 218 ++-
1 file changed, 215 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index ded0da19546e..323cfe470bd5 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -41,10 +41,15 @@
#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG0x4B
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
+#define SIERRA_CMN_PLLLC_DSMCORR_PREG 0x51
+#define SIERRA_CMN_PLLLC_SS_PREG 0x52
+#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG 0x53
+#define SIERRA_CMN_PLLLC_SSTWOPT_PREG 0x54
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG0x62
#define SIERRA_CMN_REFRCV_PREG 0x98
#define SIERRA_CMN_REFRCV1_PREG0xB8
#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
+#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG 0x63
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)
@@ -56,6 +61,7 @@
#define SIERRA_DET_STANDEC_E_PREG 0x004
#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG 0x008
#define SIERRA_PSM_A0IN_TMR_PREG 0x009
+#define SIERRA_PSM_A3IN_TMR_PREG 0x00C
#define SIERRA_PSM_DIAG_PREG 0x015
#define SIERRA_PSC_TX_A0_PREG 0x028
#define SIERRA_PSC_TX_A1_PREG 0x029
@@ -72,12 +78,15 @@
#define SIERRA_CLKPATH_BIASTRIM_PREG 0x04B
#define SIERRA_DFE_BIASTRIM_PREG 0x04C
#define SIERRA_DRVCTRL_ATTEN_PREG 0x06A
+#define SIERRA_DRVCTRL_BOOST_PREG 0x06F
#define SIERRA_CLKPATHCTRL_TMR_PREG0x081
#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG 0x085
#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG 0x086
#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG 0x087
#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG 0x088
+#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG 0x08C
#define SIERRA_CREQ_CCLKDET_MODE01_PREG0x08E
+#define SIERRA_RX_CTLE_CAL_PREG0x08F
#define SIERRA_RX_CTLE_MAINTENANCE_PREG0x091
#define SIERRA_CREQ_FSMCLK_SEL_PREG0x092
#define SIERRA_CREQ_EQ_CTRL_PREG 0x093
@@ -127,15 +136,27 @@
#define SIERRA_DEQ_ALUT12 0x114
#define SIERRA_DEQ_ALUT13 0x115
#define SIERRA_DEQ_DFETAP_CTRL_PREG0x128
+#define SIERRA_DEQ_DFETAP0 0x129
+#define SIERRA_DEQ_DFETAP1 0x12B
+#define SIERRA_DEQ_DFETAP2 0x12D
+#define SIERRA_DEQ_DFETAP3 0x12F
+#define SIERRA_DEQ_DFETAP4 0x131
#define SIERRA_DFE_EN_1010_IGNORE_PREG 0x134
+#define SIERRA_DEQ_PRECUR_PREG 0x138
+#define SIERRA_DEQ_POSTCUR_PREG0x140
+#define SIERRA_DEQ_POSTCUR_DECR_PREG 0x142
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_DEQ_TAU_CTRL2_PREG 0x151
+#define SIERRA_DEQ_TAU_CTRL3_PREG 0x152
+#define SIERRA_DEQ_OPENEYE_CTRL_PREG 0x158
#define SIERRA_DEQ_PICTRL_PREG 0x161
#define SIERRA_CPICAL_TMRVAL_MODE1_PREG0x170
#define SIERRA_CPICAL_TMRVAL_MODE0_PREG0x171
#define SIERRA_CPICAL_PICNT_MODE1_PREG 0x174
#define SIERRA_CPI_OUTBUF_RATESEL_PREG 0x17C
+#define SIERRA_CPI_TRIM_PREG 0x17F
#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG0x183
+#define SIERRA_EPI_CTRL_PREG 0x187
#define SIERRA_LFPSDET_SUPPORT_PREG0x188
#define SIERRA_LFPSFILT_NS_PREG0x18A
#define SIERRA_LFPSFILT_RD_PREG0x18B
@@ -985,6 +1006,146 @@ static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
};
+/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */
+static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {
+ {0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
+ {
[PATCH 19/25] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation
From: Swapnil Jakhade
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 41 +++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index df31fb3f19a3..ded0da19546e 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -157,6 +157,11 @@
#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000
#define SIERRA_PHY_PMA_CMN_CTRL0x0
+/* PHY PCS lane registers */
+#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, offset) \
+ (0xD000 + ((ln) * (0x800 >> (2 -
(offset)
+#define SIERRA_PHY_ISO_LINK_CTRL 0xB
+
#define SIERRA_MACRO_ID0x7364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -181,6 +186,8 @@ static const struct reg_field pma_cmn_ready =
REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const struct reg_field phy_iso_link_ctrl_1 =
+ REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);
static const char * const clk_names[] = {
[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
@@ -276,6 +283,7 @@ struct cdns_sierra_phy {
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pcs_common_cdb;
+ struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
@@ -286,6 +294,7 @@ struct cdns_sierra_phy {
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
+ struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -400,6 +409,15 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
+ if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {
+ ret =
regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],
+val, !val, 1000,
PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for PHY status ready\n");
+ return ret;
+ }
+ }
+
/*
* Wait for cmn_ready assertion
* PHY_PMA_CMN_CTRL[0] == 1
@@ -666,7 +684,17 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
return PTR_ERR(field);
}
- sp->pllctrl_lock[i] = field;
+ sp->pllctrl_lock[i] = field;
+ }
+
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ regmap = sp->regmap_phy_pcs_lane_cdb[i];
+ field = devm_regmap_field_alloc(dev, regmap,
phy_iso_link_ctrl_1);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane
%d failed\n", i);
+ return PTR_ERR(field);
+ }
+ sp->phy_iso_link_ctrl_1[i] = field;
}
return 0;
@@ -708,6 +736,17 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_phy_pcs_common_cdb = regmap;
+ for (i = 0; i < SIERRA_MAX_LANES; i++) {
+ block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i,
reg_offset_shift);
+ regmap = cdns_regmap_init(dev, base, block_offset,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PCS lane CDB
regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pcs_lane_cdb[i] = regmap;
+ }
+
regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET,
block_offset_shift, reg_offset_shift);
if (IS_ERR(regmap)) {
--
2.17.1
[PATCH 18/25] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on
From: Swapnil Jakhade
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 35
1 file changed, 35 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 9267293703c3..df31fb3f19a3 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -153,6 +153,10 @@
#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
+/* PHY PMA common registers */
+#define SIERRA_PHY_PMA_COMMON_OFFSET 0xe000
+#define SIERRA_PHY_PMA_CMN_CTRL0x0
+
#define SIERRA_MACRO_ID0x7364
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
@@ -173,6 +177,8 @@ static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);
+static const struct reg_field pma_cmn_ready =
+ REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
@@ -270,9 +276,11 @@ struct cdns_sierra_phy {
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_pcs_common_cdb;
+ struct regmap *regmap_phy_pma_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
+ struct regmap_field *pma_cmn_ready;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
struct regmap_field
*cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
@@ -392,6 +400,17 @@ static int cdns_sierra_phy_on(struct phy *gphy)
return ret;
}
+ /*
+* Wait for cmn_ready assertion
+* PHY_PMA_CMN_CTRL[0] == 1
+*/
+ ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,
+1000, PLL_LOCK_TIME);
+ if (ret) {
+ dev_err(dev, "Timeout waiting for CMN ready\n");
+ return ret;
+ }
+
ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],
val, val, 1000, PLL_LOCK_TIME);
if (ret < 0)
@@ -632,6 +651,14 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
}
sp->phy_pll_cfg_1 = field;
+ regmap = sp->regmap_phy_pma_common_cdb;
+ field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);
+ if (IS_ERR(field)) {
+ dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");
+ return PTR_ERR(field);
+ }
+ sp->pma_cmn_ready = field;
+
for (i = 0; i < SIERRA_MAX_LANES; i++) {
regmap = sp->regmap_lane_cdb[i];
field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);
@@ -681,6 +708,14 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_phy_pcs_common_cdb = regmap;
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PMA_COMMON_OFFSET,
+ block_offset_shift, reg_offset_shift);
+ if (IS_ERR(regmap)) {
+ dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");
+ return PTR_ERR(regmap);
+ }
+ sp->regmap_phy_pma_common_cdb = regmap;
+
return 0;
}
--
2.17.1
[PATCH 17/25] phy: cadence: Sierra: Add PHY PCS common register configurations
From: Swapnil Jakhade
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 38
1 file changed, 38 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 951344f5ace5..9267293703c3 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -150,6 +150,7 @@
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
+#define SIERRA_PHY_PIPE_CMN_CTRL1 0x0
#define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID0x7364
@@ -251,6 +252,8 @@ struct cdns_sierra_data {
u32 id_value;
u8 block_offset_shift;
u8 reg_offset_shift;
+ struct cdns_sierra_vals
*pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+[NUM_SSC_MODE];
struct cdns_sierra_vals
*pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
[NUM_SSC_MODE];
struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
@@ -321,6 +324,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
enum cdns_sierra_phy_type phy_type = ins->phy_type;
enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs;
+ struct cdns_sierra_vals *pcs_cmn_vals;
struct regmap *regmap = phy->regmap;
u32 num_regs;
int i, j;
@@ -332,6 +336,16 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 2500);
+ /* PHY PCS common registers configurations */
+ pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pcs_cmn_vals) {
+ reg_pairs = pcs_cmn_vals->reg_pairs;
+ num_regs = pcs_cmn_vals->num_regs;
+ regmap = phy->regmap_phy_pcs_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
+ }
+
/* PMA common registers configurations */
pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
if (pma_cmn_vals) {
@@ -887,6 +901,16 @@ static int cdns_sierra_phy_remove(struct udevice *dev)
return 0;
}
+/* PCIE PHY PCS common configuration */
+static struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {
+ {0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}
+};
+
+static struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {
+ .reg_pairs = pcie_phy_pcs_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),
+};
+
/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */
static struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {
{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},
@@ -1038,6 +1062,13 @@ static const struct cdns_sierra_data cdns_map_sierra = {
.id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x2,
.reg_offset_shift = 0x2,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = _phy_pcs_cmn_vals,
+ },
+ },
+ },
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
@@ -1068,6 +1099,13 @@ static const struct cdns_sierra_data cdns_ti_map_sierra
= {
.id_value = SIERRA_MACRO_ID,
.block_offset_shift = 0x0,
.reg_offset_shift = 0x1,
+ .pcs_cmn_vals = {
+ [TYPE_PCIE] = {
+ [TYPE_NONE] = {
+ [EXTERNAL_SSC] = _phy_pcs_cmn_vals,
+ },
+ },
+ },
.pma_cmn_vals = {
[TYPE_PCIE] = {
[TYPE_NONE] = {
--
2.17.1
[PATCH 16/25] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation
From: Swapnil Jakhade
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index e2f631e330da..951344f5ace5 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -149,7 +149,7 @@
#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG 0x14F
#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG 0x150
-#define SIERRA_PHY_CONFIG_CTRL_OFFSET 0xc000
+#define SIERRA_PHY_PCS_COMMON_OFFSET 0xc000
#define SIERRA_PHY_PLL_CFG 0xe
#define SIERRA_MACRO_ID0x7364
@@ -266,7 +266,7 @@ struct cdns_sierra_phy {
struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
- struct regmap *regmap_phy_config_ctrl;
+ struct regmap *regmap_phy_pcs_common_cdb;
struct regmap *regmap_common_cdb;
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
@@ -610,7 +610,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy *sp)
sp->cmn_refrcv_refclk_termen_preg[i] = field;
}
- regmap = sp->regmap_phy_config_ctrl;
+ regmap = sp->regmap_phy_pcs_common_cdb;
field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);
if (IS_ERR(field)) {
dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");
@@ -659,13 +659,13 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
}
sp->regmap_common_cdb = regmap;
- regmap = cdns_regmap_init(dev, base, SIERRA_PHY_CONFIG_CTRL_OFFSET,
+ regmap = cdns_regmap_init(dev, base, SIERRA_PHY_PCS_COMMON_OFFSET,
block_offset_shift, reg_offset_shift);
if (IS_ERR(regmap)) {
- dev_err(dev, "Failed to init PHY config and control regmap\n");
+ dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");
return PTR_ERR(regmap);
}
- sp->regmap_phy_config_ctrl = regmap;
+ sp->regmap_phy_pcs_common_cdb = regmap;
return 0;
}
--
2.17.1
[PATCH 13/25] phy: cadence: Sierra: Prepare driver to add support for multilink configurations
From: Swapnil Jakhade
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 188 ---
1 file changed, 135 insertions(+), 53 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 7e52a19f0dae..745c34088a5b 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -28,6 +28,9 @@
#include
#include
+#define NUM_SSC_MODE 3
+#define NUM_PHY_TYPE 3
+
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG0x0
@@ -214,8 +217,20 @@ struct cdns_sierra_pll_mux {
#define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl
+enum cdns_sierra_phy_type {
+ TYPE_NONE,
+ TYPE_PCIE,
+ TYPE_USB
+};
+
+enum cdns_sierra_ssc_mode {
+ NO_SSC,
+ EXTERNAL_SSC,
+ INTERNAL_SSC
+};
+
struct cdns_sierra_inst {
- u32 phy_type;
+ enum cdns_sierra_phy_type phy_type;
u32 num_lanes;
u32 mlane;
struct reset_ctl_bulk *lnk_rst;
@@ -226,18 +241,19 @@ struct cdns_reg_pairs {
u32 off;
};
+struct cdns_sierra_vals {
+ const struct cdns_reg_pairs *reg_pairs;
+ u32 num_regs;
+};
+
struct cdns_sierra_data {
u32 id_value;
u8 block_offset_shift;
u8 reg_offset_shift;
- u32 pcie_cmn_regs;
- u32 pcie_ln_regs;
- u32 usb_cmn_regs;
- u32 usb_ln_regs;
- struct cdns_reg_pairs *pcie_cmn_vals;
- struct cdns_reg_pairs *pcie_ln_vals;
- struct cdns_reg_pairs *usb_cmn_vals;
- struct cdns_reg_pairs *usb_ln_vals;
+ struct cdns_sierra_vals
*pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+[NUM_SSC_MODE];
+ struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]
+ [NUM_SSC_MODE];
};
struct cdns_sierra_phy {
@@ -299,10 +315,14 @@ static int cdns_sierra_phy_init(struct phy *gphy)
{
struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);
struct cdns_sierra_phy *phy = dev_get_priv(gphy->dev);
+ struct cdns_sierra_data *init_data = phy->init_data;
+ struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
+ enum cdns_sierra_phy_type phy_type = ins->phy_type;
+ enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
+ const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap = phy->regmap;
+ u32 num_regs;
int i, j;
- struct cdns_reg_pairs *cmn_vals, *ln_vals;
- u32 num_cmn_regs, num_ln_regs;
/* Initialise the PHY registers, unless auto configured */
if (phy->autoconf)
@@ -311,28 +331,25 @@ static int cdns_sierra_phy_init(struct phy *gphy)
clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 2500);
clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 2500);
- if (ins->phy_type == PHY_TYPE_PCIE) {
- num_cmn_regs = phy->init_data->pcie_cmn_regs;
- num_ln_regs = phy->init_data->pcie_ln_regs;
- cmn_vals = phy->init_data->pcie_cmn_vals;
- ln_vals = phy->init_data->pcie_ln_vals;
- } else if (ins->phy_type == PHY_TYPE_USB3) {
- num_cmn_regs = phy->init_data->usb_cmn_regs;
- num_ln_regs = phy->init_data->usb_ln_regs;
- cmn_vals = phy->init_data->usb_cmn_vals;
- ln_vals = phy->init_data->usb_ln_vals;
- } else {
- return -EINVAL;
+ /* PMA common registers configurations */
+ pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_cmn_vals) {
+ reg_pairs = pma_cmn_vals->reg_pairs;
+ num_regs = pma_cmn_vals->num_regs;
+ regmap = phy->regmap_common_cdb;
+ for (i = 0; i < num_regs; i++)
+ regmap_write(regmap, reg_pairs[i].off,
reg_pairs[i].val);
}
- regmap = phy->regmap_common_cdb;
- for (j = 0; j < num_cmn_regs ; j++)
- regmap_write(regmap, cmn_vals[j].off, cmn_vals[j].val);
-
- for (i = 0; i < ins->num_lanes; i++) {
- for (j = 0; j < num_ln_regs ; j++) {
+ /* PMA TX lane registers configurations */
+ pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];
+ if (pma_ln_vals) {
+ reg_pairs = pma_ln_vals->reg_pairs;
+ num_regs
[PATCH 15/25] phy: cadence: Sierra: Add support to get SSC type from device tree.
From: Swapnil Jakhade
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 745c34088a5b..e2f631e330da 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -234,6 +234,7 @@ struct cdns_sierra_inst {
u32 num_lanes;
u32 mlane;
struct reset_ctl_bulk *lnk_rst;
+ enum cdns_sierra_ssc_mode ssc_mode;
};
struct cdns_reg_pairs {
@@ -318,7 +319,7 @@ static int cdns_sierra_phy_init(struct phy *gphy)
struct cdns_sierra_data *init_data = phy->init_data;
struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;
enum cdns_sierra_phy_type phy_type = ins->phy_type;
- enum cdns_sierra_ssc_mode ssc = EXTERNAL_SSC;
+ enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;
const struct cdns_reg_pairs *reg_pairs;
struct regmap *regmap = phy->regmap;
u32 num_regs;
@@ -546,6 +547,9 @@ static int cdns_sierra_get_optional(struct cdns_sierra_inst
*inst,
return -EINVAL;
}
+ inst->ssc_mode = EXTERNAL_SSC;
+ ofnode_read_u32(child, "cdns,ssc-mode", >ssc_mode);
+
return 0;
}
--
2.17.1
[PATCH 14/25] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
From: Swapnil Jakhade Add binding to specify Spread Spectrum Clocking mode used Signed-off-by: Swapnil Jakhade Signed-off-by: Aswath Govindraju --- include/dt-bindings/phy/phy-cadence.h | 4 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h index 4652bcb86265..0122c6067b17 100644 --- a/include/dt-bindings/phy/phy-cadence.h +++ b/include/dt-bindings/phy/phy-cadence.h @@ -17,4 +17,8 @@ #define CDNS_SIERRA_PLL_CMNLC 0 #define CDNS_SIERRA_PLL_CMNLC1 1 +#define SIERRA_SERDES_NO_SSC 0 +#define SIERRA_SERDES_EXTERNAL_SSC 1 +#define SIERRA_SERDES_INTERNAL_SSC 2 + #endif /* _DT_BINDINGS_CADENCE_SERDES_H */ -- 2.17.1
[PATCH 12/25] arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the
function device_probe, the corresponding clocks are probed before calling
the device's probe. The PLL_CMNLC mux clock can only be created after the
device's probe. Therefore, move assigned-clocks and assigned-clock-parents
to the link nodes in U-Boot device tree file.
Signed-off-by: Aswath Govindraju
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 10
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 24 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 3ca9b5c801f0..938e978a6b66 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -232,3 +232,13 @@
_serdes_mux {
u-boot,mux-autoprobe;
};
+
+ {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+};
+
+_pcie_link {
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <_pll1_refclk>;
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 4b2362a5dd05..8299463c3e01 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -8,6 +8,7 @@
#include "k3-j721e-som-p0.dtsi"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
+#include
/ {
aliases {
@@ -361,3 +362,26 @@
_udmap {
ti,sci = <_tifs>;
};
+
+_pll1_refclk {
+ assigned-clocks = <_pll1_refclk>;
+ assigned-clock-parents = <_refclk1>;
+};
+
+_refclk_dig {
+ assigned-clocks = <_refclk_dig>;
+ assigned-clock-parents = <_refclk1>;
+};
+
+ {
+ assigned-clocks = < CDNS_SIERRA_PLL_CMNLC>;
+ assigned-clock-parents = <_pll1_refclk>;
+
+ serdes0_pcie_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = ;
+ resets = <_wiz0 1>;
+ };
+};
--
2.17.1
[PATCH 11/25] board: ti: j721e: evm.c: Add support for probing SerDes0
Add support for probing, initializing and powering, SerDes0 instance.
Signed-off-by: Aswath Govindraju
---
board/ti/j721e/evm.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 077d83420c9c..ad85b9d50115 100644
--- a/board/ti/j721e/evm.c
+++ b/board/ti/j721e/evm.c
@@ -413,6 +413,40 @@ void configure_serdes_torrent(void)
printf("phy_power_on failed !!\n");
}
+void configure_serdes_sierra(void)
+{
+ struct udevice *dev, *lnk_dev;
+ struct phy serdes;
+ int ret, count, i;
+
+ if (!IS_ENABLED(CONFIG_PHY_CADENCE_SIERRA))
+ return;
+
+ ret = uclass_get_device_by_driver(UCLASS_PHY,
+ DM_DRIVER_GET(sierra_phy_provider),
+ );
+ if (ret)
+ printf("Sierra init failed:%d\n", ret);
+
+ serdes.dev = dev;
+ serdes.id = 0;
+
+ count = device_get_child_count(dev);
+ for (i = 0; i < count; i++) {
+ ret = device_get_child(dev, i, _dev);
+ if (ret)
+ printf("probe of sierra child node %d failed\n", i);
+ }
+
+ ret = generic_phy_init();
+ if (ret)
+ printf("phy_init failed!!\n");
+
+ ret = generic_phy_power_on();
+ if (ret)
+ printf("phy_power_on failed !!\n");
+}
+
int board_late_init(void)
{
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
@@ -426,6 +460,9 @@ int board_late_init(void)
if (board_is_j7200_som())
configure_serdes_torrent();
+ if (board_is_j721e_som())
+ configure_serdes_sierra();
+
return 0;
}
--
2.17.1
[PATCH 09/25] phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 223 +--
1 file changed, 210 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index af67df6d06cb..7e52a19f0dae 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -13,6 +13,7 @@
*/
#include
#include
+#include
#include
#include
#include
@@ -24,11 +25,13 @@
#include
#include
#include
+#include
#include
/* PHY register offsets */
#define SIERRA_COMMON_CDB_OFFSET 0x0
#define SIERRA_MACRO_ID_REG0x0
+#define SIERRA_CMN_PLLLC_GEN_PREG 0x42
#define SIERRA_CMN_PLLLC_MODE_PREG 0x48
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
@@ -36,6 +39,9 @@
#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F
#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50
#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG0x62
+#define SIERRA_CMN_REFRCV_PREG 0x98
+#define SIERRA_CMN_REFRCV1_PREG0xB8
+#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2
#define SIERRA_LANE_CDB_OFFSET(ln, offset) \
(0x4000 + ((ln) * (0x800 >> (2 - (offset)
@@ -147,13 +153,18 @@
#define SIERRA_MAX_LANES 16
#define PLL_LOCK_TIME 100
-#define CDNS_SIERRA_INPUT_CLOCKS 3
+#define CDNS_SIERRA_INPUT_CLOCKS 5
enum cdns_sierra_clock_input {
PHY_CLK,
CMN_REFCLK_DIG_DIV,
CMN_REFCLK1_DIG_DIV,
+ PLL0_REFCLK,
+ PLL1_REFCLK,
};
+#define SIERRA_NUM_CMN_PLLC2
+#define SIERRA_NUM_CMN_PLLC_PARENTS2
+
static const struct reg_field macro_id_type =
REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);
static const struct reg_field phy_pll_cfg_1 =
@@ -161,6 +172,44 @@ static const struct reg_field phy_pll_cfg_1 =
static const struct reg_field pllctrl_lock =
REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);
+static const char * const clk_names[] = {
+ [CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",
+ [CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",
+};
+
+enum cdns_sierra_cmn_plllc {
+ CMN_PLLLC,
+ CMN_PLLLC1,
+};
+
+struct cdns_sierra_pll_mux_reg_fields {
+ struct reg_fieldpfdclk_sel_preg;
+ struct reg_fieldplllc1en_field;
+ struct reg_fieldtermen_field;
+};
+
+static const struct cdns_sierra_pll_mux_reg_fields
cmn_plllc_pfdclk1_sel_preg[] = {
+ [CMN_PLLLC] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),
+ },
+ [CMN_PLLLC1] = {
+ .pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),
+ .plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),
+ .termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),
+ },
+};
+
+struct cdns_sierra_pll_mux {
+ struct cdns_sierra_phy *sp;
+ struct clk *clk;
+ struct clk *parent_clks[2];
+ struct regmap_field *pfdclk_sel_preg;
+ struct regmap_field *plllc1en_field;
+ struct regmap_field *termen_field;
+};
+
#define reset_control_assert(rst) cdns_reset_assert(rst)
#define reset_control_deassert(rst) cdns_reset_deassert(rst)
#define reset_control reset_ctl
@@ -191,12 +240,6 @@ struct cdns_sierra_data {
struct cdns_reg_pairs *usb_ln_vals;
};
-struct cdns_regmap_cdb_context {
- struct udevice *dev;
- void __iomem *base;
- u8 reg_offset_shift;
-};
-
struct cdns_sierra_phy {
struct udevice *dev;
void *base;
@@ -211,6 +254,9 @@ struct cdns_sierra_phy {
struct regmap_field *macro_id_type;
struct regmap_field *phy_pll_cfg_1;
struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];
+ struct regmap_field
*cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];
+ struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];
struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];
int nsubnodes;
u32 num
[PATCH 08/25] phy: cadence: Sierra: Add a UCLASS_PHY device for links
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 116 +++
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 90699f2fa653..af67df6d06cb 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -203,7 +203,7 @@ struct cdns_sierra_phy {
size_t size;
struct regmap *regmap;
struct cdns_sierra_data *init_data;
- struct cdns_sierra_inst phys[SIERRA_MAX_LANES];
+ struct cdns_sierra_inst *phys[SIERRA_MAX_LANES];
struct reset_control *phy_rst;
struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];
struct regmap *regmap_phy_config_ctrl;
@@ -242,8 +242,8 @@ static inline struct cdns_sierra_inst
*phy_get_drvdata(struct phy *phy)
return NULL;
for (index = 0; index < sp->nsubnodes; index++) {
- if (phy->id == sp->phys[index].mlane)
- return >phys[index];
+ if (phy->id == sp->phys[index]->mlane)
+ return sp->phys[index];
}
return NULL;
@@ -500,13 +500,79 @@ static int cdns_sierra_phy_get_resets(struct
cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_bind_link_nodes(struct cdns_sierra_phy *sp)
+{
+ struct udevice *dev = sp->dev;
+ struct driver *link_drv;
+ ofnode child;
+ int rc;
+
+ link_drv = lists_driver_lookup_name("sierra_phy_link");
+ if (!link_drv) {
+ dev_err(dev, "Cannot find driver 'sierra_phy_link'\n");
+ return -ENOENT;
+ }
+
+ ofnode_for_each_subnode(child, dev_ofnode(dev)) {
+ if (!(ofnode_name_eq(child, "phy") ||
+ ofnode_name_eq(child, "link")))
+ continue;
+
+ rc = device_bind(dev, link_drv, "link", NULL, child, NULL);
+ if (rc) {
+ dev_err(dev, "cannot bind driver for link\n");
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static int cdns_sierra_link_probe(struct udevice *dev)
+{
+ struct cdns_sierra_inst *inst = dev_get_priv(dev);
+ struct cdns_sierra_phy *sp = dev_get_priv(dev->parent);
+ struct reset_ctl_bulk *rst;
+ int ret, node;
+
+ rst = devm_reset_bulk_get_by_node(dev, dev_ofnode(dev));
+ if (IS_ERR(rst)) {
+ ret = PTR_ERR(rst);
+ dev_err(dev, "failed to get reset\n");
+ return ret;
+ }
+ inst->lnk_rst = rst;
+
+ ret = cdns_sierra_get_optional(inst, dev_ofnode(dev));
+ if (ret) {
+ dev_err(dev, "missing property in node\n");
+ return ret;
+ }
+ node = sp->nsubnodes;
+ sp->phys[node] = inst;
+ sp->nsubnodes += 1;
+ sp->num_lanes += inst->num_lanes;
+
+ /* If more than one subnode, configure the PHY as multilink */
+ if (!sp->autoconf && sp->nsubnodes > 1)
+ regmap_field_write(sp->phy_pll_cfg_1, 0x1);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(sierra_phy_link) = {
+ .name = "sierra_phy_link",
+ .id = UCLASS_PHY,
+ .probe = cdns_sierra_link_probe,
+ .priv_auto = sizeof(struct cdns_sierra_inst),
+};
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
int ret, node = 0;
- ofnode child;
sp->dev = dev;
@@ -558,46 +624,14 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
}
sp->autoconf = dev_read_bool(dev, "cdns,autoconf");
-
- ofnode_for_each_subnode(child, dev_ofnode(dev)) {
- if (!(ofnode_name_eq(child, "phy") ||
- ofnode_name_eq(child, "link")))
- continue;
-
- sp->phys[node].lnk_rst = devm_reset_bulk_get_by_node(dev,
-child);
- if (IS_ERR(sp->phys[node].lnk_rst)) {
- ret = PTR_ERR(sp->phys[node].lnk_rst);
- dev_err(dev, "failed to get reset %s\n",
- ofnode_get_name(child));
- goto put_child2;
- }
-
- if (!sp->autoconf) {
- ret = cdns_sierra_get_optional(>phys[node], child);
- if (ret) {
- dev_err(dev, "missing
[PATCH 10/25] phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: Aswath Govindraju --- drivers/phy/ti/phy-j721e-wiz.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index d74efcd21208..686cdc6f7c23 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -523,7 +523,7 @@ static int wiz_reset_deassert(struct reset_ctl *reset_ctl) return ret; } - if (wiz->lane_phy_type[id - 1] == PHY_TYPE_PCIE) + if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP) ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE); else ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE); -- 2.17.1
[PATCH 07/25] phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback
From: Kishon Vijay Abraham I Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Aswath Govindraju --- drivers/phy/cadence/phy-cadence-sierra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c index 0bc60bb73e88..90699f2fa653 100644 --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c @@ -617,6 +617,8 @@ static int cdns_sierra_phy_remove(struct udevice *dev) for (i = 0; i < phy->nsubnodes; i++) reset_assert_bulk(phy->phys[i].lnk_rst); + clk_disable_unprepare(phy->input_clks[PHY_CLK]); + return 0; } -- 2.17.1
[PATCH 05/25] phy: cadence: Sierra: Move all reset_control_get*() to a separate function
From: Kishon Vijay Abraham I
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index d07cf1d97df2..eaa32939c1c2 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -480,6 +480,21 @@ static int cdns_sierra_phy_get_clocks(struct
cdns_sierra_phy *sp,
return 0;
}
+static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct reset_control *rst;
+
+ rst = devm_reset_control_get(dev, "sierra_reset");
+ if (IS_ERR(rst)) {
+ dev_err(dev, "failed to get reset\n");
+ return PTR_ERR(rst);
+ }
+ sp->phy_rst = rst;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
@@ -520,6 +535,10 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return PTR_ERR(sp->phy_rst);
}
+ ret = cdns_sierra_phy_get_resets(sp, dev);
+ if (ret)
+ return ret;
+
ret = clk_prepare_enable(sp->clk);
if (ret)
return ret;
--
2.17.1
[PATCH 04/25] phy: cadence: Sierra: Move all clk_get_*() to a separate function
From: Kishon Vijay Abraham I
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 45d6d6a796a5..d07cf1d97df2 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -448,13 +448,44 @@ static int cdns_regmap_init_blocks(struct cdns_sierra_phy
*sp,
return 0;
}
+static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
+ struct udevice *dev)
+{
+ struct clk *clk;
+ int ret;
+
+ clk = devm_clk_get_optional(dev, "phy_clk");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "failed to get clock phy_clk\n");
+ return PTR_ERR(clk);
+ }
+ sp->clk = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk = clk;
+
+ clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "cmn_refclk1_dig_div clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->cmn_refclk1 = clk;
+
+ return 0;
+}
+
static int cdns_sierra_phy_probe(struct udevice *dev)
{
struct cdns_sierra_phy *sp = dev_get_priv(dev);
struct cdns_sierra_data *data;
unsigned int id_value;
int ret, node = 0;
- struct clk *clk;
ofnode child;
sp->dev = dev;
@@ -479,11 +510,9 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
if (ret)
return ret;
- sp->clk = devm_clk_get_optional(dev, "phy_clk");
- if (IS_ERR(sp->clk)) {
- dev_err(dev, "failed to get clock phy_clk\n");
- return PTR_ERR(sp->clk);
- }
+ ret = cdns_sierra_phy_get_clocks(sp, dev);
+ if (ret)
+ return ret;
sp->phy_rst = devm_reset_control_get(dev, "sierra_reset");
if (IS_ERR(sp->phy_rst)) {
@@ -491,22 +520,6 @@ static int cdns_sierra_phy_probe(struct udevice *dev)
return PTR_ERR(sp->phy_rst);
}
- clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk = clk;
-
- clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");
- if (IS_ERR(clk)) {
- dev_err(dev, "cmn_refclk1 clock not found\n");
- ret = PTR_ERR(clk);
- return ret;
- }
- sp->cmn_refclk1 = clk;
-
ret = clk_prepare_enable(sp->clk);
if (ret)
return ret;
--
2.17.1
[PATCH 00/25] SIERRA: Add support for MultiLink
The following series of patches, - add support for MultiLink on Sierra SerDes - Also adds the required to configs, dt node changes to enable this on J721e common processor board. Notes: - Patches 1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15, 16, 17, 18, 19, 20, 21 and 22 are ported from upstream kernel v5.17-rc1 - Patch 24, syncs with linux kernel dt, with the following patch https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=608996 Aswath Govindraju (8): phy: cadence: Sierra: Add a UCLASS_PHY device for links phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE board: ti: j721e: evm.c: Add support for probing SerDes0 arm: dts: k3-j721e: Add support for PLL_CMNLC clocks in SerDes0 phy: cadence: Sierra: Add support for skipping configuration arm: dts: k3-j721e: Add support for multilink PCIe + QSGMII include: configs: j721e_evm: Add support to boot ethfw core in j721e Kishon Vijay Abraham I (6): phy: cadence: Sierra: Fix PHY power_on sequence phy: cadence: Sierra: Create PHY only for "phy" or "link" sub-nodes phy: cadence: Sierra: Move all clk_get_*() to a separate function phy: cadence: Sierra: Move all reset_control_get*() to a separate function phy: cadence: Sierra: Add array of input clocks in "struct cdns_sierra_phy" phy: cadence: Sierra: Add missing clk_disable_unprepare() in .remove callback Sanket Parmar (1): phy: cadence: sierra: Fix for USB3 U1/U2 state Swapnil Jakhade (10): phy: cadence: Sierra: Prepare driver to add support for multilink configurations dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode phy: cadence: Sierra: Add support to get SSC type from device tree. phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration .../k3-j721e-common-proc-board-u-boot.dtsi| 15 + arch/arm/dts/k3-j721e-common-proc-board.dts | 14 +- .../arm/dts/k3-j721e-r5-common-proc-board.dts | 32 + board/ti/j721e/evm.c | 37 + configs/j721e_evm_a72_defconfig |2 +- drivers/phy/cadence/phy-cadence-sierra.c | 1536 +++-- drivers/phy/ti/phy-j721e-wiz.c|2 +- include/configs/j721e_evm.h | 19 +- include/dt-bindings/phy/phy-cadence.h |4 + 9 files changed, 1493 insertions(+), 168 deletions(-) -- 2.17.1
[PATCH 01/25] phy: cadence: sierra: Fix for USB3 U1/U2 state
From: Sanket Parmar
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 27
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 715def6f173b..6b26b30dcf9d 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -606,10 +606,10 @@ static struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[]
= {
static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0xFE0A, SIERRA_DET_STANDEC_A_PREG},
{0x000F, SIERRA_DET_STANDEC_B_PREG},
- {0x00A5, SIERRA_DET_STANDEC_C_PREG},
+ {0x55A5, SIERRA_DET_STANDEC_C_PREG},
{0x69ad, SIERRA_DET_STANDEC_D_PREG},
{0x0241, SIERRA_DET_STANDEC_E_PREG},
- {0x0010, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
+ {0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},
{0x0014, SIERRA_PSM_A0IN_TMR_PREG},
{0xCF00, SIERRA_PSM_DIAG_PREG},
{0x001F, SIERRA_PSC_TX_A0_PREG},
@@ -617,7 +617,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x0003, SIERRA_PSC_TX_A2_PREG},
{0x0003, SIERRA_PSC_TX_A3_PREG},
{0x0FFF, SIERRA_PSC_RX_A0_PREG},
- {0x0619, SIERRA_PSC_RX_A1_PREG},
+ {0x0003, SIERRA_PSC_RX_A1_PREG},
{0x0003, SIERRA_PSC_RX_A2_PREG},
{0x0001, SIERRA_PSC_RX_A3_PREG},
{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},
@@ -626,19 +626,19 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] =
{
{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},
{0x2512, SIERRA_DFE_BIASTRIM_PREG},
{0x, SIERRA_DRVCTRL_ATTEN_PREG},
- {0x873E, SIERRA_CLKPATHCTRL_TMR_PREG},
- {0x03CF, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
- {0x01CE, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
+ {0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},
+ {0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},
{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},
- {0x033F, SIERRA_RX_CTLE_MAINTENANCE_PREG},
+ {0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},
{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},
{0x, SIERRA_CREQ_EQ_CTRL_PREG},
- {0x8000, SIERRA_CREQ_SPARE_PREG},
+ {0x, SIERRA_CREQ_SPARE_PREG},
{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},
- {0x8453, SIERRA_CTLELUT_CTRL_PREG},
- {0x4110, SIERRA_DFE_ECMP_RATESEL_PREG},
- {0x4110, SIERRA_DFE_SMP_RATESEL_PREG},
- {0x0002, SIERRA_DEQ_PHALIGN_CTRL},
+ {0x8452, SIERRA_CTLELUT_CTRL_PREG},
+ {0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},
+ {0x4121, SIERRA_DFE_SMP_RATESEL_PREG},
+ {0x0003, SIERRA_DEQ_PHALIGN_CTRL},
{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},
{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},
{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},
@@ -646,7 +646,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},
{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},
{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},
- {0x9A8A, SIERRA_DEQ_VGATUNE_CTRL_PREG},
+ {0x, SIERRA_DEQ_VGATUNE_CTRL_PREG},
{0x0014, SIERRA_DEQ_GLUT0},
{0x0014, SIERRA_DEQ_GLUT1},
{0x0014, SIERRA_DEQ_GLUT2},
@@ -693,6 +693,7 @@ static struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {
{0x000F, SIERRA_LFPSFILT_NS_PREG},
{0x0009, SIERRA_LFPSFILT_RD_PREG},
{0x0001, SIERRA_LFPSFILT_MP_PREG},
+ {0x6013, SIERRA_SIGDET_SUPPORT_PREG},
{0x8013, SIERRA_SDFILT_H2L_A_PREG},
{0x8009, SIERRA_SDFILT_L2H_PREG},
{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},
--
2.17.1
Re: [PATCH v3 00/20] J721S2: Add initial support
Hi All, On 18/01/22 12:57 pm, Aswath Govindraju wrote: > The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration in automotive ADAS applications and > industrial applications requiring AI at the network edge. This SoC extends > the Jacinto 7 family of SoCs with focus on lowering system costs and power > while providing interfaces, memory architecture and compute performance for > single and multi-sensor applications. > > Some highlights of this SoC are: > > * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable > dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x > floating point Vector DSP. > * 3D GPU: Automotive grade IMG BXS-4-64 > * Vision Processing Accelerator (VPAC) with image signal processor and > Depth and Motion Processing Accelerator (DMPAC) > * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. > * Two Ethernet ports with RGMII support. > * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, > * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, > QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL > management. > * Chips and Media Wave521CL H.264/H.265 encode/decode engine > > See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) > for further details: http://www.ti.com/lit/pdf/spruj28 > > bootlog: > - https://pastebin.ubuntu.com/p/8FfVJjVVSC/ > > Notes: > - Patches 12, 13, 14, 15 and 16 are synced from upstream kernel v5.17-rc1 > tag > I have posted v4 for this series after addressing the comments in this series. Thanks, Aswath > Changes since v2: > - Removed the redundant config K3_J721S2_DDRSS and instead used > K3_J721E_DDRSS > - Formatted the Kconfig files to remove extra lines > - Added dts files in the MAINTAINERS baord folder > > Changes since v1: > - Removed unused serial aliases > - Assigned serial2 alias for main uart8 instance > - Moved aliases to respective board files > > Aswath Govindraju (10): > ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance > ram: k3-ddrss: Add support for multiple instances of DDR subsystems > ram: k3-ddrss: Add support for configuring MSMC subsystem in case of > Multiple DDR subsystems > dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC > dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 > arm: dts: Add initial support for J721S2 SoC > arm: dts: Add initial support for J721S2 System on Module > arm: dts: Add support for A72 specific J721S2 Common Processor Board > arm: dts: k3-j721s2: Add r5 specific dt support > arm: dts: k3-j721s2-ddr: Add DDR support > > David Huang (9): > arm: K3: Add basic support for J721S2 SoC definition > drivers: dma: Add support for J721S2 > clk: clk-k3: Add support for J721S2 SoC > power: domain: ti: Add support for J721S2 SoC > ram: k3-ddrss: Add support for J721S2 SoC > soc: ti: k3-socinfo: Add entry for J721S2 SoC > board: ti: j721s2: Add board support for J721S2 > configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig > configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig > > Nishanth Menon (1): > remoteproc: k3_system_controller: Support optional boot_notification > channel > > arch/arm/dts/Makefile |2 + > .../k3-j721s2-common-proc-board-u-boot.dtsi | 149 + > arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++ > arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 4387 > arch/arm/dts/k3-j721s2-ddr.dtsi | 4440 + > arch/arm/dts/k3-j721s2-main.dtsi | 937 > arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi| 302 ++ > .../dts/k3-j721s2-r5-common-proc-board.dts| 198 + > arch/arm/dts/k3-j721s2-som-p0.dtsi| 173 + > arch/arm/dts/k3-j721s2.dtsi | 167 + > arch/arm/mach-k3/Kconfig | 15 +- > arch/arm/mach-k3/Makefile |1 + > arch/arm/mach-k3/arm64-mmu.c | 53 + > arch/arm/mach-k3/include/mach/hardware.h |4 + > .../mach-k3/include/mach/j721s2_hardware.h| 60 + > arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 + > arch/arm/mach-k3/include/mach/spl.h |4 + > arch/arm/mach-k3/j721s2/Makefile |5 + > arch/arm/mach-k3/j721s2/clk-data.c| 403 ++ > arch/arm/mach-k3/j721s2/dev-data.c| 85 + > arch/arm/mach-k3/j721s2_init.c| 312 ++ > board/ti/j721s2/Kconfig | 63 + &g
[PATCH v4 20/20] configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig
From: David Huang
Enable A72 specific configs for J721S2
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Hari Nagalla
---
configs/j721s2_evm_a72_defconfig | 207 +++
1 file changed, 207 insertions(+)
create mode 100644 configs/j721s2_evm_a72_defconfig
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
new file mode 100644
index ..92f668f8f931
--- /dev/null
+++ b/configs/j721s2_evm_a72_defconfig
@@ -0,0 +1,207 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+CONFIG_ENV_SIZE=0x2
+CONFIG_ENV_OFFSET=0x68
+CONFIG_SYS_MALLOC_LEN=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_ENV_OFFSET_REDUND=0x6A
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_CLK_CCF=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x8200
+CONFIG_FASTBOOT_BUF_SIZE=0x2F00
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HS512T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+# CONFIG_SPI_FLASH_USE_4K_SE
[PATCH v4 19/20] configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig
From: David Huang Enable R5 SPL specific configs for J721S2. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Hari Nagalla --- configs/j721s2_evm_r5_defconfig | 171 1 file changed, 171 insertions(+) create mode 100644 configs/j721s2_evm_r5_defconfig diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig new file mode 100644 index ..4ecab605357c --- /dev/null +++ b/configs/j721s2_evm_r5_defconfig @@ -0,0 +1,171 @@ +CONFIG_PANIC_HANG=y +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x1 +CONFIG_SOC_K3_J721S2=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_J721S2_R5_EVM=y +CONFIG_ENV_SIZE=0x2 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x41c0 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +# CONFIG_CLK_TI_SCI is not set +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_FS_LOADER=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HS512T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_QSPI_PHY=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_K3_DM_FW=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_LIBFDT=y +CONFIG_SPL_DM_GPIO=y +CONFIG_SYS_MALLOC_LEN=0x200 +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SP
[PATCH v4 17/20] arm: dts: k3-j721s2: Add r5 specific dt support
Add initial support for device tree that runs on R5.
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/Makefile | 3 +-
.../dts/k3-j721s2-r5-common-proc-board.dts| 196 ++
2 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 84cf3d76ffe7..825a5be588e0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1132,7 +1132,8 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
-dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb\
+ k3-j721s2-r5-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
new file mode 100644
index ..12590d391fce
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-r5-common-proc-board.dts
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2-som-p0.dtsi"
+
+/ {
+ chosen {
+ firmware-loader = _loader0;
+ stdout-path = _uart8;
+ tick-timer =
+ };
+
+ aliases {
+ remoteproc0 =
+ remoteproc1 = _0;
+ };
+
+ fs_loader0: fs_loader@0 {
+ compatible = "u-boot,fs-loader";
+ u-boot,dm-pre-reloc;
+ };
+
+ a72_0: a72@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a9 0x0 0x10>;
+ power-domains = <_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <_pds 202 TI_SCI_PD_EXCLUSIVE>;
+ resets = <_reset 202 0>;
+ clocks = <_clks 61 1>;
+ assigned-clocks = <_clks 61 1>, <_clks 202 0>;
+ assigned-clock-parents = <_clks 61 2>;
+ assigned-clock-rates = <2>, <20>;
+ ti,sci = <>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ clk_200mhz: dummy_clock_200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ u-boot,dm-spl;
+ };
+
+ clk_19_2mhz: dummy_clock_19_2mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <1920>;
+ u-boot,dm-spl;
+ };
+};
+
+_mcu_wakeup {
+ sa3_secproxy: secproxy@4488 {
+ u-boot,dm-spl;
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x4488 0x0 0x2>,
+ <0x0 0x4486 0x0 0x2>,
+ <0x0 0x4360 0x0 0x1>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ };
+
+ mcu_secproxy: secproxy@2a38 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a38 0x0 0x8>,
+ <0x0 0x2a40 0x0 0x8>,
+ <0x0 0x2a48 0x0 0x8>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <_secproxy 4>, <_secproxy 5>, <_secproxy 5>;
+ mbox-names = "tx", "rx", "boot_notify";
+ u-boot,dm-spl;
+ };
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <_secproxy 21>,
+ <_secproxy 23>;
+ u-boot,dm-spl;
+ };
+};
+
+_pmx0 {
+ main_uart8_pins_default: main-uart8-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x040, PIN_INPUT, 14) /* (AC28)
MCASP0_AXR0.UART8_CTSn */
+
[PATCH v4 16/20] arm: dts: Add support for A72 specific J721S2 Common Processor Board
The EVM architecture for J721S2 is similar to that of J721E and J7200. It
is as follows,
+--+
| +---+ |
| | | |
| |Add-on Card 1 Options | |
| | | |
| +---+ |
| |
| |
| +---+|
| | ||
| | SOM ||
| +--+ | ||
| | | | ||
| | Add-on | +---+|
| | Card 2 ||Power Supply
| | Options |||
| | |||
| +--+| <---
+--+
Common Processor Board
Common Processor board is the baseboard that contains most of the actual
connectors, power supply etc. The System on Module (SoM) is plugged on to
the common processor baord. Therefore, add support for peripherals brought
out in the common processor board.
Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/Makefile | 1 +
.../k3-j721s2-common-proc-board-u-boot.dtsi | 149 ++
arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++
3 files changed, 580 insertions(+)
create mode 100644 arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
create mode 100644 arch/arm/dts/k3-j721s2-common-proc-board.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce332021d895..84cf3d76ffe7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1132,6 +1132,7 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_J721S2) += k3-j721s2-common-proc-board.dtb
dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
k3-am642-r5-evm.dtb \
k3-am642-sk.dtb \
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
new file mode 100644
index ..749bc717f390
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer =
+ };
+
+ aliases {
+ serial0 = _uart0;
+ serial1 = _uart0;
+ serial2 = _uart8;
+ i2c0 = _i2c0;
+ i2c1 = _i2c0;
+ i2c2 = _i2c1;
+ i2c3 = _i2c0;
+ ethernet0 = _port1;
+ };
+};
+
+_i2c0 {
+ u-boot,dm-spl;
+};
+
+_main {
+ u-boot,dm-spl;
+};
+
+_navss {
+ u-boot,dm-spl;
+};
+
+_mcu_wakeup {
+ u-boot,dm-spl;
+
+ timer1: timer@4040 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x4040 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <2500>;
+ u-boot,dm-spl;
+ };
+
+ chipid@4314 {
+ u-boot,dm-spl;
+ };
+};
+
+_navss {
+ u-boot,dm-spl;
+};
+
+_ringacc {
+ reg = <0x0 0x2b80 0x0 0x40>,
+ <0x0 0x2b00 0x0 0x40>,
+ <0x0 0x2859 0x0 0x100>,
+ <0x0 0x2a50 0x0 0x4>,
+ <0x0 0x2844 0x0 0x4>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+};
+
+_udmap {
+ reg = <0x0 0x285c 0x0 0x100>,
+ <0x0 0x284c 0x0 0x4000>,
+ <0x0 0x2a80 0x0 0x4>,
+ <0x0 0x284a 0x0 0x4000>,
+ <0x0 0x2aa0 0x0 0x4>,
+ <0x0 0x2840 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+};
+
+_proxy_main {
+ u-boot,dm-spl;
+};
+
+ {
+ u-boot,dm-spl;
+ k3
[PATCH v4 14/20] arm: dts: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.
See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
Introduce basic support for the J721S2 SoC.
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Nishanth Menon
---
arch/arm/dts/k3-j721s2-main.dtsi | 937 +
arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi | 302
arch/arm/dts/k3-j721s2.dtsi| 167 +
3 files changed, 1406 insertions(+)
create mode 100644 arch/arm/dts/k3-j721s2-main.dtsi
create mode 100644 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
create mode 100644 arch/arm/dts/k3-j721s2.dtsi
diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi
new file mode 100644
index ..976ba1e95aba
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-main.dtsi
@@ -0,0 +1,937 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for J721S2 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+_main {
+ msmc_ram: sram@7000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x7000 0x0 0x40>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x7000 0x40>;
+
+ atf-sram@0 {
+ reg = <0x0 0x2>;
+ };
+
+ tifs-sram@1f {
+ reg = <0x1f 0x1>;
+ };
+
+ l3cache-sram@20 {
+ reg = <0x20 0x20>;
+ };
+ };
+
+ gic500: interrupt-controller@180 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x0180 0x00 0x20>, /* GICD */
+ <0x00 0x0190 0x00 0x10>; /* GICR */
+
+ /* vcpumntirq: virtual CPU interface maintenance interrupt */
+ interrupts = ;
+
+ gic_its: msi-controller@182 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x0182 0x00 0x1>;
+ socionext,synquacer-pre-its = <0x100 0x40>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ main_gpio_intr: interrupt-controller@a0 {
+ compatible = "ti,sci-intr";
+ reg = <0x00 0x00a0 0x00 0x800>;
+ ti,intr-trigger-type = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ #interrupt-cells = <1>;
+ ti,sci = <>;
+ ti,sci-dev-id = <148>;
+ ti,interrupt-ranges = <8 360 56>;
+ };
+
+ main_pmx0: pinctrl@11c000 {
+ compatible = "pinctrl-single";
+ /* Proxy 0 addressing */
+ reg = <0x0 0x11c000 0x0 0x120>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x>;
+ };
+
+ main_uart0: serial@280 {
+ compatible = "ti,j721e-uart", "ti,am654-uart";
+ reg = <0x00 0x0280 0x00 0x200>;
+ interrupts = ;
+ current-speed = <115200>;
+ clocks = <_clks 146 3>;
+
[PATCH v4 15/20] arm: dts: Add initial support for J721S2 System on Module
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/k3-j721s2-som-p0.dtsi | 173 +
1 file changed, 173 insertions(+)
create mode 100644 arch/arm/dts/k3-j721s2-som-p0.dtsi
diff --git a/arch/arm/dts/k3-j721s2-som-p0.dtsi
b/arch/arm/dts/k3-j721s2-som-p0.dtsi
new file mode 100644
index ..c0687fece017
--- /dev/null
+++ b/arch/arm/dts/k3-j721s2-som-p0.dtsi
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-j721s2.dtsi"
+#include
+
+/ {
+ memory@8000 {
+ device_type = "memory";
+ /* 16 GB RAM */
+ reg = <0x00 0x8000 0x00 0x8000>,
+ <0x08 0x8000 0x03 0x8000>;
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e80 {
+ reg = <0x00 0x9e80 0x00 0x0180>;
+ alignment = <0x1000>;
+ no-map;
+ };
+
+ };
+
+ transceiver0: can-phy0 {
+ /* standby pin has been grounded by default */
+ compatible = "ti,tcan1042";
+ #phy-cells = <0>;
+ max-bitrate = <500>;
+ };
+};
+
+_pmx0 {
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AH25)
I2C0_SCL */
+ J721S2_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AE24)
I2C0_SDA */
+ >;
+ };
+
+ main_mcan16_pins_default: main-mcan16-pins-default {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */
+ J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */
+ >;
+ };
+};
+
+_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c0_pins_default>;
+ clock-frequency = <40>;
+
+ exp_som: gpio@21 {
+ compatible = "ti,tca6408";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "USB2.0_MUX_SEL", "CANUART_MUX1_SEL0",
+ "CANUART_MUX2_SEL0", "CANUART_MUX_SEL1",
+ "GPIO_RGMII1_RST", "GPIO_eDP_ENABLE",
+ "GPIO_LIN_EN", "CAN_STB";
+ };
+};
+
+_mcan16 {
+ pinctrl-0 = <_mcan16_pins_default>;
+ pinctrl-names = "default";
+ phys = <>;
+};
+
+_cluster0 {
+ status = "disabled";
+};
+
+_cluster1 {
+ status = "disabled";
+};
+
+_cluster2 {
+ status = "disabled";
+};
+
+_cluster3 {
+ status = "disabled";
+};
+
+_cluster4 {
+ status = "disabled";
+};
+
+_cluster5 {
+ status = "disabled";
+};
+
+_cluster6 {
+ status = "disabled";
+};
+
+_cluster7 {
+ status = "disabled";
+};
+
+_cluster8 {
+ status = "disabled";
+};
+
+_cluster9 {
+ status = "disabled";
+};
+
+_cluster10 {
+ status = "disabled";
+};
+
+_cluster11 {
+ status = "disabled";
+};
+
+_cluster0 {
+ status = "disabled";
+};
+
+_cluster1 {
+ status = "disabled";
+};
+
+_cluster2 {
+ status = "disabled";
+};
+
+_cluster3 {
+ status = "disabled";
+};
+
+_cluster4 {
+ status = "disabled";
+};
+
+_cluster5 {
+ status = "disabled";
+};
+
+_cluster6 {
+ status = "disabled";
+};
+
+_cluster7 {
+ status = "disabled";
+};
+
+_cluster8 {
+ status = "disabled";
+};
+
+_cluster9 {
+ status = "disabled";
+};
+
+_cluster10 {
+ status = "disabled";
+};
+
+_cluster11 {
+ status = "disabled";
+};
--
2.17.1
[PATCH v4 13/20] dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2
Add pinctrl macros for J721S2 SoC. These macro definitions are similar to that of J721E, but adding new definitions to avoid any naming confusions in the soc dts files. checkpatch insists the following error exists: ERROR: Macros with complex values should be enclosed in parentheses However, we do not need parentheses enclosing the values for this macro as we do intend it to generate two separate values as has been done for other similar platforms. Signed-off-by: Aswath Govindraju --- include/dt-bindings/pinctrl/k3.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h index e085f102b283..63e038e36ca3 100644 --- a/include/dt-bindings/pinctrl/k3.h +++ b/include/dt-bindings/pinctrl/k3.h @@ -38,4 +38,7 @@ #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) +#define J721S2_WKUP_IOPAD(pa, val, muxmode)(((pa) & 0x1fff)) ((val) | (muxmode)) + #endif -- 2.17.1
[PATCH v4 12/20] dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC
There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES lane mux can select upto 4 different IPs. Define all the possible functions. Signed-off-by: Aswath Govindraju --- include/dt-bindings/mux/ti-serdes.h | 22 ++ 1 file changed, 22 insertions(+) diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h index d417b9268b16..d3116c52ab72 100644 --- a/include/dt-bindings/mux/ti-serdes.h +++ b/include/dt-bindings/mux/ti-serdes.h @@ -95,4 +95,26 @@ #define AM64_SERDES0_LANE0_PCIE0 0x0 #define AM64_SERDES0_LANE0_USB 0x1 +/* J721S2 */ + +#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 +#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 +#define J721S2_SERDES0_LANE0_IP3_UNUSED0x2 +#define J721S2_SERDES0_LANE0_IP4_UNUSED0x3 + +#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 +#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 +#define J721S2_SERDES0_LANE1_USB 0x2 +#define J721S2_SERDES0_LANE1_IP4_UNUSED0x3 + +#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 +#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 +#define J721S2_SERDES0_LANE2_IP3_UNUSED0x2 +#define J721S2_SERDES0_LANE2_IP4_UNUSED0x3 + +#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 +#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 +#define J721S2_SERDES0_LANE3_USB 0x2 +#define J721S2_SERDES0_LANE3_IP4_UNUSED0x3 + #endif /* _DT_BINDINGS_MUX_TI_SERDES */ -- 2.17.1
[PATCH v4 11/20] board: ti: j721s2: Add board support for J721S2
From: David Huang
Add board support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
board/ti/j721s2/Kconfig | 63 +
board/ti/j721s2/MAINTAINERS | 16
board/ti/j721s2/Makefile| 8 ++
board/ti/j721s2/evm.c | 180
4 files changed, 267 insertions(+)
create mode 100644 board/ti/j721s2/Kconfig
create mode 100644 board/ti/j721s2/MAINTAINERS
create mode 100644 board/ti/j721s2/Makefile
create mode 100644 board/ti/j721s2/evm.c
diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig
new file mode 100644
index ..2e115f14171d
--- /dev/null
+++ b/board/ti/j721s2/Kconfig
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+# David Huang
+
+choice
+ prompt "K3 J721S2 board"
+ optional
+
+config TARGET_J721S2_A72_EVM
+ bool "TI K3 based J721S2 EVM running on A72"
+ select ARM64
+ select SOC_K3_J721S2
+ select BOARD_LATE_INIT
+ imply TI_I2C_BOARD_DETECT
+ select SYS_DISABLE_DCACHE_OPS
+
+config TARGET_J721S2_R5_EVM
+ bool "TI K3 based J721S2 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select SOC_K3_J721S2
+ select K3_LOAD_SYSFW
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_J721S2_A72_EVM
+
+config SYS_BOARD
+ default "j721s2"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721s2_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_J721S2_R5_EVM
+
+config SYS_BOARD
+ default "j721s2"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "j721s2_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/j721s2/MAINTAINERS b/board/ti/j721s2/MAINTAINERS
new file mode 100644
index 0000..323bd2353a7e
--- /dev/null
+++ b/board/ti/j721s2/MAINTAINERS
@@ -0,0 +1,16 @@
+J721S2 BOARD
+M: Aswath Govindraju
+S: Maintained
+F: board/ti/j721s2
+F: include/configs/j721s2_evm.h
+F: configs/j721s2_evm_r5_defconfig
+F: configs/j721s2_evm_a72_defconfig
+F: arch/arm/dts/k3-j721s2.dtsi
+F: arch/arm/dts/k3-j721s2-main.dtsi
+F: arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi
+F: arch/arm/dts/k3-j721s2-som-p0.dtsi
+F: arch/arm/dts/k3-j721s2-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+F: arch/arm/dts//k3-j721s2-r5-common-proc-board.dts
+F: arch/arm/dts/k3-j721s2-ddr.dtsi
+F: arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi
diff --git a/board/ti/j721s2/Makefile b/board/ti/j721s2/Makefile
new file mode 100644
index ..9dced1269942
--- /dev/null
+++ b/board/ti/j721s2/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+# David Huang
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
new file mode 100644
index ..3c75ecfc0fe4
--- /dev/null
+++ b/board/ti/j721s2/evm.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for J721S2 EVM
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * David Huang
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../common/board_detect.h"
+
+#define board_is_j721s2_som() board_ti_k3_is("J721S2X-PM1-SOM")
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+#ifdef CONFIG_PHYS_64BIT
+ gd->ram_size = 0x1;
+#else
+ gd->ram_size = 0x8000;
+#endif
+
+ return 0;
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_PHYS_64BIT
+ /* Limit RAM used by U-Boot to the DDR low region */
+ if (gd->ram_top > 0x1)
+ return 0x1;
+#endif
+
+ return gd->ram_top;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x7fff;
+ gd->ram_size = 0x8000;
+
+#ifdef CONFIG_PHYS_64BIT
+ /* Bank 1 declares the memory available in the DDR high region */
+ gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE1;
+ gd->bd->bi_dram[1].size = 0x37fff;
+ gd->ram_size = 0x4;
+#endif
+
[PATCH v4 10/20] soc: ti: k3-socinfo: Add entry for J721S2 SoC
From: David Huang Add support for J721S2 SoC identification. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju --- drivers/soc/soc_ti_k3.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 9abed7d490a2..c8f7a5768775 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -14,6 +14,7 @@ #define J721E 0xbb64 #define J7200 0xbb6d #define AM64X 0xbb38 +#define J721S2 0xbb75 #define REV_SR1_0 0 #define REV_SR2_0 1 @@ -48,6 +49,9 @@ static const char *get_family_string(u32 idreg) case AM64X: family = "AM64X"; break; + case J721S2: + family = "J721S2"; + break; default: family = "Unknown Silicon"; }; -- 2.17.1
[PATCH v4 09/20] ram: k3-ddrss: Add support for J721S2 SoC
From: David Huang Add support for DDR subsystem in J721S2 SoC. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju --- drivers/ram/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index a79594d35198..709c916a2a11 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -62,7 +62,7 @@ choice depends on K3_DDRSS prompt "K3 DDRSS Arch Support" - default K3_J721E_DDRSS if SOC_K3_J721E + default K3_J721E_DDRSS if SOC_K3_J721E || SOC_K3_J721S2 default K3_AM64_DDRSS if SOC_K3_AM642 config K3_J721E_DDRSS -- 2.17.1
[PATCH v4 08/20] power: domain: ti: Add support for J721S2 SoC
From: David Huang
Add support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/power/domain/ti-power-domain.c | 5 +
include/k3-dev.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/power/domain/ti-power-domain.c
b/drivers/power/domain/ti-power-domain.c
index 4fe31686bd35..6af5dbb24191 100644
--- a/drivers/power/domain/ti-power-domain.c
+++ b/drivers/power/domain/ti-power-domain.c
@@ -81,6 +81,11 @@ static const struct soc_attr ti_k3_soc_pd_data[] = {
.family = "J7200",
.data = _pd_platdata,
},
+#elif CONFIG_SOC_K3_J721S2
+ {
+ .family = "J721S2",
+ .data = _pd_platdata,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/include/k3-dev.h b/include/k3-dev.h
index 55c5057db35a..b46b8c3aabc7 100644
--- a/include/k3-dev.h
+++ b/include/k3-dev.h
@@ -77,6 +77,7 @@ struct ti_k3_pd_platdata {
extern const struct ti_k3_pd_platdata j721e_pd_platdata;
extern const struct ti_k3_pd_platdata j7200_pd_platdata;
+extern const struct ti_k3_pd_platdata j721s2_pd_platdata;
u8 ti_pd_state(struct ti_pd *pd);
u8 lpsc_get_state(struct ti_lpsc *lpsc);
--
2.17.1
[PATCH v4 07/20] clk: clk-k3: Add support for J721S2 SoC
From: David Huang
Add support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/clk/ti/clk-k3.c | 5 +
include/k3-clk.h| 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index e04c57eff252..74beb4d8ebda 100644
--- a/drivers/clk/ti/clk-k3.c
+++ b/drivers/clk/ti/clk-k3.c
@@ -68,6 +68,11 @@ static const struct soc_attr ti_k3_soc_clk_data[] = {
.family = "J7200",
.data = _clk_platdata,
},
+#elif CONFIG_SOC_K3_J721S2
+ {
+ .family = "J721S2",
+ .data = _clk_platdata,
+ },
#endif
{ /* sentinel */ }
};
diff --git a/include/k3-clk.h b/include/k3-clk.h
index 59c76db86ead..31292b59f20c 100644
--- a/include/k3-clk.h
+++ b/include/k3-clk.h
@@ -173,6 +173,7 @@ struct ti_k3_clk_platdata {
extern const struct ti_k3_clk_platdata j721e_clk_platdata;
extern const struct ti_k3_clk_platdata j7200_clk_platdata;
+extern const struct ti_k3_clk_platdata j721s2_clk_platdata;
struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
void __iomem *reg);
--
2.17.1
[PATCH v4 06/20] drivers: dma: Add support for J721S2
From: David Huang
Add support for DMA in J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j721s2.c | 167 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers/dma/ti/k3-psil.c | 2 +
drivers/firmware/ti_sci_static_data.h | 40 +-
5 files changed, 208 insertions(+), 3 deletions(-)
create mode 100644 drivers/dma/ti/k3-psil-j721s2.c
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 0391cd3d80c9..6a4f4f1365bd 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
diff --git a/drivers/dma/ti/k3-psil-j721s2.c b/drivers/dma/ti/k3-psil-j721s2.c
new file mode 100644
index ..4c4172a4d271
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-j721s2.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#include
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x)\
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_PDMA_MCASP(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .pdma_acc32 = 1,\
+ .pdma_burst = 1,\
+ }, \
+ }
+
+#define PSIL_ETHERNET(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 16, \
+ }, \
+ }
+
+#define PSIL_SA2UL(x, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1,\
+ .psd_size = 64, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep j721s2_src_ep_map[] = {
+ /* PDMA_MCASP - McASP0-4 */
+ PSIL_PDMA_MCASP(0x4400),
+ PSIL_PDMA_MCASP(0x4401),
+ PSIL_PDMA_MCASP(0x4402),
+ PSIL_PDMA_MCASP(0x4403),
+ PSIL_PDMA_MCASP(0x4404),
+ /* PDMA_SPI_G0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4600),
+ PSIL_PDMA_XY_PKT(0x4601),
+ PSIL_PDMA_XY_PKT(0x4602),
+ PSIL_PDMA_XY_PKT(0x4603),
+ PSIL_PDMA_XY_PKT(0x4604),
+ PSIL_PDMA_XY_PKT(0x4605),
+ PSIL_PDMA_XY_PKT(0x4606),
+ PSIL_PDMA_XY_PKT(0x4607),
+ PSIL_PDMA_XY_PKT(0x4608),
+ PSIL_PDMA_XY_PKT(0x4609),
+ PSIL_PDMA_XY_PKT(0x460a),
+ PSIL_PDMA_XY_PKT(0x460b),
+ PSIL_PDMA_XY_PKT(0x460c),
+ PSIL_PDMA_XY_PKT(0x460d),
+ PSIL_PDMA_XY_PKT(0x460e),
+ PSIL_PDMA_XY_PKT(0x460f),
+ /* PDMA_SPI_G1 - SPI4-7 */
+ PSIL_PDMA_XY_PKT(0x4610),
+ PSIL_PDMA_XY_PKT(0x4611),
+ PSIL_PDMA_XY_PKT(0x4612),
+ PSIL_PDMA_XY_PKT(0x4613),
+ PSIL_PDMA_XY_PKT(0x4614),
+ PSIL_PDMA_XY_PKT(0x4615),
+ PSIL_PDMA_XY_PKT(0x4616),
+ PSIL_PDMA_XY_PKT(0x4617),
+ PSIL_PDMA_XY_PKT(0x4618),
+ PSIL_PDMA_XY_
[PATCH v4 05/20] arm: K3: Add basic support for J721S2 SoC definition
From: David Huang Add basic support for J721S2 SoC definition Signed-off-by: David Huang Signed-off-by: Aswath Govindraju Signed-off-by: Dave Gerlach Signed-off-by: Nishanth Menon Signed-off-by: Hari Nagalla --- arch/arm/mach-k3/Kconfig | 15 +- arch/arm/mach-k3/Makefile | 1 + arch/arm/mach-k3/arm64-mmu.c | 41 ++ arch/arm/mach-k3/include/mach/hardware.h | 4 + .../mach-k3/include/mach/j721s2_hardware.h| 60 +++ arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 ++ arch/arm/mach-k3/include/mach/spl.h | 4 + arch/arm/mach-k3/j721s2/Makefile | 5 + arch/arm/mach-k3/j721s2/clk-data.c| 403 ++ arch/arm/mach-k3/j721s2/dev-data.c| 85 arch/arm/mach-k3/j721s2_init.c| 312 ++ include/configs/j721s2_evm.h | 191 + 12 files changed, 1162 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-k3/include/mach/j721s2_hardware.h create mode 100644 arch/arm/mach-k3/include/mach/j721s2_spl.h create mode 100644 arch/arm/mach-k3/j721s2/Makefile create mode 100644 arch/arm/mach-k3/j721s2/clk-data.c create mode 100644 arch/arm/mach-k3/j721s2/dev-data.c create mode 100644 arch/arm/mach-k3/j721s2_init.c create mode 100644 include/configs/j721s2_evm.h diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig index 526f5f8b76c2..a01bf2351499 100644 --- a/arch/arm/mach-k3/Kconfig +++ b/arch/arm/mach-k3/Kconfig @@ -10,6 +10,9 @@ config SOC_K3_AM6 config SOC_K3_J721E bool "TI's K3 based J721E SoC Family Support" +config SOC_K3_J721S2 + bool "TI's K3 based J721S2 SoC Family Support" + config SOC_K3_AM642 bool "TI's K3 based AM642 SoC Family Support" @@ -21,7 +24,7 @@ config SYS_SOC config SYS_K3_NON_SECURE_MSRAM_SIZE hex default 0x8 if SOC_K3_AM6 - default 0x10 if SOC_K3_J721E + default 0x10 if SOC_K3_J721E || SOC_K3_J721S2 default 0x1c if SOC_K3_AM642 help Describes the total size of the MCU or OCMC MSRAM present on @@ -32,7 +35,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE hex default 0x58000 if SOC_K3_AM6 - default 0xc if SOC_K3_J721E + default 0xc if SOC_K3_J721E || SOC_K3_J721S2 default 0x18 if SOC_K3_AM642 help Describes the maximum size of the image that ROM can download @@ -41,14 +44,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE config SYS_K3_MCU_SCRATCHPAD_BASE hex default 0x4028 if SOC_K3_AM6 - default 0x4028 if SOC_K3_J721E + default 0x4028 if SOC_K3_J721E || SOC_K3_J721S2 help Describes the base address of MCU Scratchpad RAM. config SYS_K3_MCU_SCRATCHPAD_SIZE hex default 0x200 if SOC_K3_AM6 - default 0x200 if SOC_K3_J721E + default 0x200 if SOC_K3_J721E || SOC_K3_J721S2 help Describes the size of MCU Scratchpad RAM. @@ -56,6 +59,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX hex default 0x41c7fbfc if SOC_K3_AM6 default 0x41cffbfc if SOC_K3_J721E + default 0x41cfdbfc if SOC_K3_J721S2 default 0x701bebfc if SOC_K3_AM642 help Address at which ROM stores the value which determines if SPL @@ -156,7 +160,7 @@ config K3_ATF_LOAD_ADDR config K3_DM_FW bool "Separate DM firmware image" - depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN + depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN default y help Enabling this will indicate that the system has separate DM @@ -169,4 +173,5 @@ source "board/ti/am65x/Kconfig" source "board/ti/am64x/Kconfig" source "board/ti/j721e/Kconfig" source "board/siemens/iot2050/Kconfig" +source "board/ti/j721s2/Kconfig" endif diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile index 47cf7b6d17a8..c0a6a9c87d8f 100644 --- a/arch/arm/mach-k3/Makefile +++ b/arch/arm/mach-k3/Makefile @@ -5,6 +5,7 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/ +obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/ obj-$(CONFIG_SOC_K3_AM642) += am642_init.o obj-$(CONFIG_ARM64) += arm64-mmu.o obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 94242e1e5cc3..527e66431888 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -181,6 +181,47 @@ struct mm_region *mem_map = j7200_mem_map; #endif /* CONFIG_SOC_K3_J721E */ +#ifdef CONFIG_SOC_K3_J721S2 +#define NR_MMU_R
[PATCH v4 04/20] ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems
In Multi DDR subystems with interleaving support, the following needs to
configured,
- interleaving granular size and region
- EMIFs to be enabled
- EMIFs with ecc to be enabled
- EMIF separated or interleaved
- number of cycles of unsuccessful EMIF arbitration to wait before
arbitrating for a different EMIF port, by default set to 3
Add support for configuring all the above by using a MSMC device
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 158
1 file changed, 158 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 96084d0b83d9..25e3976e6569 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -33,6 +33,75 @@
#define SINGLE_DDR_SUBSYSTEM 0x1
#define MULTI_DDR_SUBSYSTEM0x2
+#define MULTI_DDR_CFG0 0x00114100
+#define MULTI_DDR_CFG1 0x00114104
+#define DDR_CFG_LOAD0x00114110
+
+enum intrlv_gran {
+ GRAN_128B,
+ GRAN_512B,
+ GRAN_2KB,
+ GRAN_4KB,
+ GRAN_16KB,
+ GRAN_32KB,
+ GRAN_512KB,
+ GRAN_1GB,
+ GRAN_1_5GB,
+ GRAN_2GB,
+ GRAN_3GB,
+ GRAN_4GB,
+ GRAN_6GB,
+ GRAN_8GB,
+ GRAN_16GB
+};
+
+enum intrlv_size {
+ SIZE_0,
+ SIZE_128MB,
+ SIZE_256MB,
+ SIZE_512MB,
+ SIZE_1GB,
+ SIZE_2GB,
+ SIZE_3GB,
+ SIZE_4GB,
+ SIZE_6GB,
+ SIZE_8GB,
+ SIZE_12GB,
+ SIZE_16GB,
+ SIZE_32GB
+};
+
+struct k3_ddrss_data {
+ u32 flags;
+};
+
+enum ecc_enable {
+ DISABLE_ALL = 0,
+ ENABLE_0,
+ ENABLE_1,
+ ENABLE_ALL
+};
+
+enum emif_config {
+ INTERLEAVE_ALL = 0,
+ SEPR0,
+ SEPR1
+};
+
+enum emif_active {
+ EMIF_0 = 1,
+ EMIF_1,
+ EMIF_ALL
+};
+
+struct k3_msmc {
+ enum intrlv_gran gran;
+ enum intrlv_size size;
+ enum ecc_enable enable;
+ enum emif_config config;
+ enum emif_active active;
+};
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
@@ -512,3 +581,92 @@ U_BOOT_DRIVER(k3_ddrss) = {
.probe = k3_ddrss_probe,
.priv_auto = sizeof(struct k3_ddrss_desc),
};
+
+static int k3_msmc_set_config(struct k3_msmc *msmc)
+{
+ u32 ddr_cfg0 = 0;
+ u32 ddr_cfg1 = 0;
+
+ ddr_cfg0 |= msmc->gran << 24;
+ ddr_cfg0 |= msmc->size << 16;
+ /* heartbeat_per, bit[4:0] setting to 3 is advisable */
+ ddr_cfg0 |= 3;
+
+ /* Program MULTI_DDR_CFG0 */
+ writel(ddr_cfg0, MULTI_DDR_CFG0);
+
+ ddr_cfg1 |= msmc->enable << 16;
+ ddr_cfg1 |= msmc->config << 8;
+ ddr_cfg1 |= msmc->active;
+
+ /* Program MULTI_DDR_CFG1 */
+ writel(ddr_cfg1, MULTI_DDR_CFG1);
+
+ /* Program DDR_CFG_LOAD */
+ writel(0x6000, DDR_CFG_LOAD);
+
+ return 0;
+}
+
+static int k3_msmc_probe(struct udevice *dev)
+{
+ struct k3_msmc *msmc = dev_get_priv(dev);
+ int ret = 0;
+
+ /* Read the granular size from DT */
+ ret = dev_read_u32(dev, "intrlv-gran", >gran);
+ if (ret) {
+ dev_err(dev, "missing intrlv-gran property");
+ return -EINVAL;
+ }
+
+ /* Read the interleave region from DT */
+ ret = dev_read_u32(dev, "intrlv-size", >size);
+ if (ret) {
+ dev_err(dev, "missing intrlv-size property");
+ return -EINVAL;
+ }
+
+ /* Read ECC enable config */
+ ret = dev_read_u32(dev, "ecc-enable", >enable);
+ if (ret) {
+ dev_err(dev, "missing ecc-enable property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF configuration */
+ ret = dev_read_u32(dev, "emif-config", >config);
+ if (ret) {
+ dev_err(dev, "missing emif-config property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF active */
+ ret = dev_read_u32(dev, "emif-active", >active);
+ if (ret) {
+ dev_err(dev, "missing emif-active property");
+ return -EINVAL;
+ }
+
+ ret = k3_msmc_set_config(msmc);
+ if (ret) {
+ dev_err(dev, "error setting msmc config");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id k3_msmc_ids[] = {
+ { .compatible = "ti,j721s2-msmc"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_msmc) = {
+ .name = "k3_msmc",
+ .of_match = k3_msmc_ids,
+ .id = UCLASS_MISC,
+ .probe = k3_msmc_probe,
+ .priv_auto = sizeof(struct k3_msmc),
+ .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
--
2.17.1
[PATCH v4 03/20] ram: k3-ddrss: Add support for multiple instances of DDR subsystems
The current driver only supports single instance of DRR subsystem. Add
support for probing multiple instances of DDR subsystem.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 138
1 file changed, 87 insertions(+), 51 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 95b5cf9128b0..96084d0b83d9 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -30,6 +30,9 @@
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
+#define SINGLE_DDR_SUBSYSTEM 0x1
+#define MULTI_DDR_SUBSYSTEM0x2
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
@@ -42,14 +45,12 @@ struct k3_ddrss_desc {
u32 ddr_freq2;
u32 ddr_fhs_cnt;
struct udevice *vtt_supply;
+ u32 instance;
+ lpddr4_obj *driverdt;
+ lpddr4_config config;
+ lpddr4_privatedata pd;
};
-static lpddr4_obj *driverdt;
-static lpddr4_config config;
-static lpddr4_privatedata pd;
-
-static struct k3_ddrss_desc *ddrss;
-
struct reginitdata {
u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
@@ -83,15 +84,16 @@ struct reginitdata {
offset = offset * 10 + (*i - '0'); } \
} while (0)
-static u32 k3_lpddr4_read_ddr_type(void)
+static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
{
u32 status = 0U;
u32 offset = 0U;
u32 regval = 0U;
u32 dram_class = 0U;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
- status = driverdt->readreg(, LPDDR4_CTL_REGS, offset, );
+ status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, );
if (status > 0U) {
printf("%s: Failed to read DRAM_CLASS\n", __func__);
hang();
@@ -102,23 +104,23 @@ static u32 k3_lpddr4_read_ddr_type(void)
return dram_class;
}
-static void k3_lpddr4_freq_update(void)
+static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
{
unsigned int req_type, counter;
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10, 0x80,
true, 1, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
req_type = readl(ddrss->ddrss_ctrl_mmr +
-CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
+CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10) & 0x03;
- debug("%s: received freq change req: req type = %d, req no. =
%d\n",
- __func__, req_type, counter);
+ debug("%s: received freq change req: req type = %d, req no. =
%d, instance = %d\n",
+ __func__, req_type, counter, ddrss->instance);
if (req_type == 1)
clk_set_rate(>ddr_clk, ddrss->ddr_freq1);
@@ -132,31 +134,32 @@ static void k3_lpddr4_freq_update(void)
printf("%s: Invalid freq request type\n", __func__);
writel(0x1, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance *
0x10);
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10, 0x80,
false, 10, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
writel(0x0, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance *
0x10);
}
}
-static void k3_lpddr4_ack_freq_upd_req(void)
+static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{
u32 dram_class;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
- dram_class = k3_lpddr4_read_ddr_type();
+ dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dra
[PATCH v4 00/20] J721S2: Add initial support
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 bootlog: - https://pastebin.ubuntu.com/p/NkwRvJH5Gg/ Notes: - Patches 12, 13, 14, 15 and 16 are synced from upstream kernel v5.17-rc1 tag Changes since v3: - Fixed the MMU mapping to standard in patch 5 based on the comments received from Suman. Changes since v2: - Removed the redundant config K3_J721S2_DDRSS and instead used K3_J721E_DDRSS - Formatted the Kconfig files to remove extra lines - Added dts files in the MAINTAINERS baord folder Changes since v1: - Removed unused serial aliases - Assigned serial2 alias for main uart8 instance - Moved aliases to respective board files Aswath Govindraju (10): ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance ram: k3-ddrss: Add support for multiple instances of DDR subsystems ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 arm: dts: Add initial support for J721S2 SoC arm: dts: Add initial support for J721S2 System on Module arm: dts: Add support for A72 specific J721S2 Common Processor Board arm: dts: k3-j721s2: Add r5 specific dt support arm: dts: k3-j721s2-ddr: Add DDR support David Huang (9): arm: K3: Add basic support for J721S2 SoC definition drivers: dma: Add support for J721S2 clk: clk-k3: Add support for J721S2 SoC power: domain: ti: Add support for J721S2 SoC ram: k3-ddrss: Add support for J721S2 SoC soc: ti: k3-socinfo: Add entry for J721S2 SoC board: ti: j721s2: Add board support for J721S2 configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig Nishanth Menon (1): remoteproc: k3_system_controller: Support optional boot_notification channel arch/arm/dts/Makefile |2 + .../k3-j721s2-common-proc-board-u-boot.dtsi | 149 + arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++ arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 4387 arch/arm/dts/k3-j721s2-ddr.dtsi | 4440 + arch/arm/dts/k3-j721s2-main.dtsi | 937 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi| 302 ++ .../dts/k3-j721s2-r5-common-proc-board.dts| 198 + arch/arm/dts/k3-j721s2-som-p0.dtsi| 173 + arch/arm/dts/k3-j721s2.dtsi | 167 + arch/arm/mach-k3/Kconfig | 15 +- arch/arm/mach-k3/Makefile |1 + arch/arm/mach-k3/arm64-mmu.c | 41 + arch/arm/mach-k3/include/mach/hardware.h |4 + .../mach-k3/include/mach/j721s2_hardware.h| 60 + arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 + arch/arm/mach-k3/include/mach/spl.h |4 + arch/arm/mach-k3/j721s2/Makefile |5 + arch/arm/mach-k3/j721s2/clk-data.c| 403 ++ arch/arm/mach-k3/j721s2/dev-data.c| 85 + arch/arm/mach-k3/j721s2_init.c| 312 ++ board/ti/j721s2/Kconfig | 63 + board/ti/j721s2/MAINTAINERS | 16 + board/ti/j721s2/Makefile |8 + board/ti/j721s2/evm.c | 180 + configs/j721s2_evm_a72_defconfig | 207 + configs/j721s2_evm_r5_defconfig | 171 + .../remoteproc/k3-system-controller.txt |3 + drivers/clk/ti/clk-k3.c |5 + drivers/dma/ti/Makefile |1 + drivers/dma/ti/k3-psil-j721s2.c | 167 + drivers/dma/ti/k3
[PATCH v4 02/20] ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance
Add a pointer to ddr instance int the lpddr4_privatedata_s structure for
supporting mutliple instances of DDR in the drivers.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/lpddr4_structs_if.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
index e41cbb7ff488..f2f1210c3c4e 100644
--- a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
@@ -24,6 +24,7 @@ struct lpddr4_privatedata_s {
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
+ void *ddr_instance;
};
struct lpddr4_debuginfo_s {
--
2.17.1
[PATCH v4 01/20] remoteproc: k3_system_controller: Support optional boot_notification channel
From: Nishanth Menon
If there is an optional boot notification channel that an SoC uses
separate from the rx path, use the same.
Signed-off-by: Nishanth Menon
---
.../remoteproc/k3-system-controller.txt | 3 +++
drivers/remoteproc/k3_system_controller.c | 20 ++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
index 32f4720b0d17..33dc46812ed4 100644
--- a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
+++ b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
@@ -13,6 +13,9 @@ Required properties:
"rx" for Receive channel
- mboxes: Corresponding phandles to mailbox channels.
+Optional properties:
+
+- mbox-names: "boot_notify" for Optional alternate boot notification
channel.
Example:
diff --git a/drivers/remoteproc/k3_system_controller.c
b/drivers/remoteproc/k3_system_controller.c
index 89cb90207dcb..e2affe69c678 100644
--- a/drivers/remoteproc/k3_system_controller.c
+++ b/drivers/remoteproc/k3_system_controller.c
@@ -77,14 +77,18 @@ struct k3_sysctrler_desc {
* struct k3_sysctrler_privdata - Structure representing System Controller
data.
* @chan_tx: Transmit mailbox channel
* @chan_rx: Receive mailbox channel
+ * @chan_boot_notify: Boot notification channel
* @desc: SoC description for this instance
* @seq_nr:Counter for number of messages sent.
+ * @has_boot_notify: Has separate boot notification channel
*/
struct k3_sysctrler_privdata {
struct mbox_chan chan_tx;
struct mbox_chan chan_rx;
+ struct mbox_chan chan_boot_notify;
struct k3_sysctrler_desc *desc;
u32 seq_nr;
+ bool has_boot_notify;
};
static inline
@@ -223,7 +227,8 @@ static int k3_sysctrler_start(struct udevice *dev)
debug("%s(dev=%p)\n", __func__, dev);
/* Receive the boot notification. Note that it is sent only once. */
- ret = mbox_recv(>chan_rx, , priv->desc->max_rx_timeout_us);
+ ret = mbox_recv(priv->has_boot_notify ? >chan_boot_notify :
+ >chan_rx, , priv->desc->max_rx_timeout_us);
if (ret) {
dev_err(dev, "%s: Boot Notification response failed. ret =
%d\n",
__func__, ret);
@@ -272,6 +277,19 @@ static int k3_of_to_priv(struct udevice *dev,
return ret;
}
+ /* Some SoCs may have a optional channel for boot notification. */
+ priv->has_boot_notify = 1;
+ ret = mbox_get_by_name(dev, "boot_notify", >chan_boot_notify);
+ if (ret == -ENODATA) {
+ dev_dbg(dev, "%s: Acquiring optional Boot_notify failed. ret =
%d. Using Rx\n",
+ __func__, ret);
+ priv->has_boot_notify = 0;
+ } else if (ret) {
+ dev_err(dev, "%s: Acquiring boot_notify channel failed. ret =
%d\n",
+ __func__, ret);
+ return ret;
+ }
+
return 0;
}
--
2.17.1
Re: [PATCH v2 00/20] J721S2: Add initial support
Hi all, On 11/01/22 1:25 pm, Aswath Govindraju wrote: > The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, > providing advanced system integration in automotive ADAS applications and > industrial applications requiring AI at the network edge. This SoC extends > the Jacinto 7 family of SoCs with focus on lowering system costs and power > while providing interfaces, memory architecture and compute performance for > single and multi-sensor applications. > > Some highlights of this SoC are: > > * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable > dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x > floating point Vector DSP. > * 3D GPU: Automotive grade IMG BXS-4-64 > * Vision Processing Accelerator (VPAC) with image signal processor and > Depth and Motion Processing Accelerator (DMPAC) > * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. > * Two Ethernet ports with RGMII support. > * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, > * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, > QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. > * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL > management. > * Chips and Media Wave521CL H.264/H.265 encode/decode engine > > See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) > for further details: http://www.ti.com/lit/pdf/spruj28 > > bootlog: > - https://pastebin.ubuntu.com/p/WDpTxGHcGD/ > > Changes since v1: > - Removed unused serial aliases > - Assigned serial2 alias for main uart8 instance > - Moved aliases to respective board files > I have posted v3 for this series after fixing the patches based on the comments received. Thanks, Aswath > Aswath Govindraju (10): > ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance > ram: k3-ddrss: Add support for multiple instances of DDR subsystems > ram: k3-ddrss: Add support for configuring MSMC subsystem in case of > Multiple DDR subsystems > dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC > dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 > arm: dts: Add initial support for J721S2 SoC > arm: dts: Add initial support for J721S2 System on Module > arm: dts: Add support for A72 specific J721S2 Common Processor Board > arm: dts: k3-j721s2: Add r5 specific dt support > arm: dts: k3-j721s2-ddr: Add DDR support > > David Huang (9): > arm: K3: Add basic support for J721S2 SoC definition > drivers: dma: Add support for J721S2 > clk: clk-k3: Add support for J721S2 SoC > power: domain: ti: Add support for J721S2 SoC > ram: k3-ddrss: Add support for J721S2 SoC > soc: ti: k3-socinfo: Add entry for J721S2 SoC > board: ti: j721s2: Add board support for J721S2 > configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig > configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig > > Nishanth Menon (1): > remoteproc: k3_system_controller: Support optional boot_notification > channel > > arch/arm/dts/Makefile |2 + > .../k3-j721s2-common-proc-board-u-boot.dtsi | 149 + > arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++ > arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 4387 > arch/arm/dts/k3-j721s2-ddr.dtsi | 4440 + > arch/arm/dts/k3-j721s2-main.dtsi | 937 > arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi| 302 ++ > .../dts/k3-j721s2-r5-common-proc-board.dts| 198 + > arch/arm/dts/k3-j721s2-som-p0.dtsi| 173 + > arch/arm/dts/k3-j721s2.dtsi | 167 + > arch/arm/mach-k3/Kconfig | 11 +- > arch/arm/mach-k3/Makefile |1 + > arch/arm/mach-k3/arm64-mmu.c | 53 + > arch/arm/mach-k3/include/mach/hardware.h |4 + > .../mach-k3/include/mach/j721s2_hardware.h| 60 + > arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 + > arch/arm/mach-k3/include/mach/spl.h |4 + > arch/arm/mach-k3/j721s2/Makefile |5 + > arch/arm/mach-k3/j721s2/clk-data.c| 403 ++ > arch/arm/mach-k3/j721s2/dev-data.c| 85 + > arch/arm/mach-k3/j721s2_init.c| 312 ++ > board/ti/j721s2/Kconfig | 63 + > board/ti/j721s2/MAINTAINERS |7 + > board/ti/j721s2/Makefile |8 + > board/ti/j721s2/evm.c | 180 + > configs/j721s2_evm_a72_defconfig | 207 + > configs/j721s2_evm_r5_defconfig | 171 + > .../remoteproc/k3-system
[PATCH v3 20/20] configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig
From: David Huang
Enable A72 specific configs for J721S2
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Hari Nagalla
---
configs/j721s2_evm_a72_defconfig | 207 +++
1 file changed, 207 insertions(+)
create mode 100644 configs/j721s2_evm_a72_defconfig
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
new file mode 100644
index ..92f668f8f931
--- /dev/null
+++ b/configs/j721s2_evm_a72_defconfig
@@ -0,0 +1,207 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_J721S2=y
+CONFIG_TARGET_J721S2_A72_EVM=y
+CONFIG_ENV_SIZE=0x2
+CONFIG_ENV_OFFSET=0x68
+CONFIG_SYS_MALLOC_LEN=0x200
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x28
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x8008
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_SPL_STACK_R_ADDR=0x8200
+CONFIG_ENV_OFFSET_REDUND=0x6A
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-common-proc-board"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x8100
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run
main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run
get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_LOGLEVEL=7
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+# CONFIG_SPL_SPI_FLASH_TINY is not set
+CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_THERMAL=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_UFS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MTDIDS_DEFAULT="nor0=4704.spi.0,nor0=47034000.hyperbus"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=4704.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),256k(ospi.env.backup),57088k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),-@8m(hbmc.rootfs)"
+CONFIG_CMD_UBI=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x80
+CONFIG_CLK_CCF=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x8200
+CONFIG_FASTBOOT_BUF_SIZE=0x2F00
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_SPL_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_S28HS512T=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+# CONFIG_SPI_FLASH_USE_4K_SE
[PATCH v3 19/20] configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig
From: David Huang Enable R5 SPL specific configs for J721S2. Signed-off-by: David Huang Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Signed-off-by: Hari Nagalla --- configs/j721s2_evm_r5_defconfig | 171 1 file changed, 171 insertions(+) create mode 100644 configs/j721s2_evm_r5_defconfig diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig new file mode 100644 index ..4ecab605357c --- /dev/null +++ b/configs/j721s2_evm_r5_defconfig @@ -0,0 +1,171 @@ +CONFIG_PANIC_HANG=y +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x1 +CONFIG_SOC_K3_J721S2=y +CONFIG_K3_EARLY_CONS=y +CONFIG_TARGET_J721S2_R5_EVM=y +CONFIG_ENV_SIZE=0x2 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x8 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_TEXT_BASE=0x41c0 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="k3-j721s2-r5-common-proc-board" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x8008 +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_USE_BOOTCOMMAND=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_EARLY_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_SUPPORT=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +# CONFIG_SPL_SPI_FLASH_TINY is not set +CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x4 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_DFU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_REMOTEPROC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +# CONFIG_CLK_TI_SCI is not set +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_FS_LOADER=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SPL_MMC_HS400_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CFI_FLASH=y +CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_S28HS512T=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +# CONFIG_TI_SCI_POWER_DOMAIN is not set +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_DM_RESET=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_CADENCE_QSPI_PHY=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_SPL_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" +CONFIG_USB_GADGET_VENDOR_NUM=0x0451 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_TI_POWER_DOMAIN=y +CONFIG_SPL_CLK_CCF=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_K3_DM_FW=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_OF_LIBFDT=y +CONFIG_SPL_DM_GPIO=y +CONFIG_SYS_MALLOC_LEN=0x200 +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SP
