On Mon, 2019-02-11 at 04:32 +, Anup Patel wrote:
> > -Original Message-
> > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Monday, February 11, 2019 12:10 AM
> > To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com;
>
On Sat, 2019-02-09 at 06:33 +, Anup Patel wrote:
> This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V
> because bootm will update initrd location in DTB only if
> CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable
> this option then bootm assumes DTB already has initrd details
On Sat, 2019-02-09 at 06:33 +, Anup Patel wrote:
> From: Atish Patra
>
> The readme guide describes the procedure to build, flash and boot
> Linux
> using U-boot on HiFive Unleashed. It also explains the current state
> of
> U-boot support and future action items.
nit: U-Boot
>
> Signed-of
On Sat, 2019-02-09 at 06:32 +, Anup Patel wrote:
> Add driver code for the SiFive FU540 PRCI IP block. This IP block
> handles reset and clock control for the SiFive FU540 device and
> implements SoC-level clock tree controls and dividers.
>
> Based on code written by Wesley Terpstra
> found
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> Some of the drivers expect asm/arch/clk.h to be provided by
> arch support code so we add place-holder asm/arch/clk.h for
> RISC-V support.
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/include/asm/arch/clk.h | 14 ++
> 1 file
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> Currently, the mrproper make target tries to force remove all
> "arch/*/include/asm/arch" paths assuming they are symlinks but
> this prevents us from adding place-holder headers under the
> arch/riscv/include/asm/arch directory.
>
> To solve
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> We will be adding place-holder headers under include/asm/arch
> for RISC-V so this patch updates .gitignore to not consider
> files under arch/riscv/include/asm/arch
>
> Signed-off-by: Anup Patel
> ---
> arch/.gitignore | 1 +
> 1 file chang
On Mon, 2019-01-21 at 12:39 +, Auer, Lukas wrote:
> On Sun, 2019-01-20 at 17:07 -0800, Atish Patra wrote:
> > On 1/20/19 12:22 PM, Auer, Lukas wrote:
> > > Hi Anup,
> > >
> > > On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> > > > From: A
On Sat, 2019-02-02 at 09:06 -0800, Paul Walmsley wrote:
> On Tue, 22 Jan 2019, Auer, Lukas wrote:
>
> > For the same reason, I agree with you that it does not make sense
> > to
> > implement the SBI in U-Boot. OpenSBI is better suited to handle
> > this.
>
&g
On Tue, 2019-01-22 at 12:31 +, Anup Patel wrote:
> > -Original Message-
> > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, January 22, 2019 5:21 PM
> > To: s...@chromium.org; bmeng...@gmail.com; r...@andestech.com; Anup
> >
On Mon, 2019-01-21 at 04:04 +, Anup Patel wrote:
> > -Original Message-
> > From: Atish Patra [mailto:atish.pa...@wdc.com]
> > Sent: Monday, January 21, 2019 7:07 AM
> > To: Auer, Lukas ; s...@chromium.org;
> > bmeng...@gmail.com; r...@andestech.com;
On Sun, 2019-01-20 at 17:22 -0800, Atish Patra wrote:
> On 1/20/19 12:26 PM, Auer, Lukas wrote:
> > Hi Anup,
> >
> > On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> > > This patch adds SiFive FU540 board support. For now, only
> > > SiFive serial, Si
On Sun, 2019-01-20 at 17:07 -0800, Atish Patra wrote:
> On 1/20/19 12:22 PM, Auer, Lukas wrote:
> > Hi Anup,
> >
> > On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> > > From: Atish Patra
> > >
> > > It is possible that input clock i
On Mon, 2019-01-21 at 05:55 +, Anup Patel wrote:
> > -Original Message-
> > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Monday, January 21, 2019 1:43 AM
> > To: s...@chromium.org; bmeng...@gmail.com; r...@andestech.com; Anup
> >
Hi Anup,
On Fri, 2019-01-18 at 11:18 +, Anup Patel wrote:
> This patchset adds SiFive Freedom Unleashed (FU540) support
> to RISC-V U-Boot.
>
> The patches are based upon latest RISC-V U-Boot tree
> (git://git.denx.de/u-boot-riscv.git) at commit id
> 91882c472d8c0aef4db699d3f2de55bf43d4ae4b
>
Hi Anup,
On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> This patch adds SiFive FU540 board support. For now, only
> SiFive serial, SiFive PRCI, and Cadance MACB drivers are
> only enabled. The SiFive FU540 defconfig by default builds
> U-Boot for S-Mode because U-Boot on SiFive FU540 will
On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> From: Atish Patra
>
> Currently, timer driver is bound only for hart0.
>
> There is no mandatory requirement that hart0 should always
> come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
> in S-mode because it only has M-mode.
>
> Th
Hi Anup,
On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> From: Atish Patra
>
> It is possible that input clock is not available because clk
> device was not available and 'clock-frequency' DT property is
> also not available.
Why would the clock device not be available?
I suspect the pro
On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> From: Atish Patra
>
> Compute the baud rate multipler with more precision.
>
> Signed-off-by: Atish Patra
> Reviewed-by: Alexander Graf
> ---
> drivers/serial/serial_sifive.c | 28 ++--
> 1 file changed, 26 inserti
Hi Anup,
On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> Add driver code for the SiFive FU540 PRCI IP block. This IP block
> handles reset and clock control for the SiFive FU540 device and
> implements SoC-level clock tree controls and dividers.
>
> Based on code written by Wesley Terpstr
On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> From: Atish Patra
>
> Fix MID bit field check to correctly identify all GEM hardwares.
>
> The check is updated as per macb driver in Linux location:
> /drivers/net/ethernet/cadence/macb_main.c:259
>
> Signed-off-by: Atish Patra
> Reviewed
On Fri, 2019-01-18 at 11:18 +, Anup Patel wrote:
> On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
> DMA mapping APIs will generate DMA addresses beyond 4GB. This
> breaks DMA programming in 32bit DMA capable devices (such as
> Cadence MACB ethernet). For example, If DRAM is
On Fri, 2019-01-18 at 11:18 +, Anup Patel wrote:
> This patch adds asm/dma-mapping.h for Linux-like DMA mappings
> APIs required by some of the drivers (such as, Cadance MACB
> Ethernet driver).
>
> Signed-off-by: Anup Patel
> Reviewed-by: Bin Meng
> Reviewed-by: Alexander Graf
> ---
> arc
On Fri, 2019-01-18 at 11:18 +, Anup Patel wrote:
> The QEMU CPU support under arch/riscv is pretty much generic
> and works fine for SiFive Unleashed as well. In fact, there
> will be quite a few RISC-V SOCs for which QEMU CPU support
> will work fine.
>
> This patch renames cpu/qemu to cpu/ge
Hi Bryan,
On Thu, 2019-01-03 at 01:44 +, Bryan O'Donoghue wrote:
> This patch imports the Linux kernel warp7 dts as at upstream kernel
> commit
> cf76c364a1e1.
>
> The following was dropped from the incoming kernel DTS file
>
> -&wdog1 {
> - pinctrl-names = "default";
> - pinctrl
Hi Rick,
On Thu, 2019-01-03 at 08:48 +0800, Rick Chen wrote:
> Hi Lukas
>
> Auer, Lukas 於 2019年1月2日 週三 下午8:22寫道：
> > Hi Rick,
> >
> > On Wed, 2019-01-02 at 10:54 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > > From: Lukas
Hi Rick,
On Wed, 2019-01-02 at 10:54 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Monday, December 31, 2018 2:28 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng;
> > > Greentim
Hi Bin,
On Wed, 2018-12-12 at 22:11 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Dec 12, 2018 at 7:53 PM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-12-11 at 23:11 -0800, Bin Meng wrote:
> > > This updates supports_extension() imp
On Wed, 2018-12-12 at 06:12 -0800, Bin Meng wrote:
> There is no need to expose RISCV_NDS to the Kconfig menu as it is
> an ax25-specific option. Introduce a dedicated Kconfig option for
> the cache ops of ax25 platform and use that to guard the cache ops.
>
> Signed-off-by: Bin Meng
>
> ---
>
Hi Bin,
On Tue, 2018-12-11 at 23:11 -0800, Bin Meng wrote:
> This updates supports_extension() implementation to use the desc
> string from the cpu driver whenever possible, which avoids the
> reading of misa CSR for S-mode U-Boot.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v4:
> - pri
Hi Bin,
On Wed, 2018-12-12 at 15:02 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Dec 12, 2018 at 7:40 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> > > This updates supports_extension() imp
Hi Bin,
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> This updates supports_extension() implementation to use the desc
> string from the cpu driver whenever possible, which avoids the
> reading of misa CSR for S-mode U-Boot.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - new
On Tue, 2018-12-11 at 01:35 -0800, Bin Meng wrote:
> This is not used by any board. Remove it.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - new patch to remove ae350.dts
>
> Changes in v2: None
>
> arch/riscv/dts/ae350.dts | 229 ---
> ---
On Tue, 2018-12-11 at 01:35 -0800, Bin Meng wrote:
> Avoid reading mhartid CSR directly, instead use the one we saved
> in the global data structure before.
>
> With this patch, BBL no longer needs to be hacked to provide the
> mhartid CSR emulation for S-mode U-Boot.
>
> Signed-off-by: Bin Meng
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> At present the hart id passed via a0 in the U-Boot entry is saved
> to s0 at the beginning but does not preserve later. Save it to the
> global data structure so that it can be used later.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> In arch_cpu_init_dm() do some basic architecture level cpu
> initialization, like FPU enable, etc.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - only initialize mcounteren CSR for S-mode
> - only touch satp in M-mode U-Boot
> - m
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> With DM CPU driver, the non-DM version of print_cpuinfo() is no
> longer needed.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - new patch to remove non-DM version of print_cpuinfo()
>
> Changes in v2: None
>
> arch/riscv/cpu/cp
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> This adds U-Boot syscon driver for SiFive's Core Local Interruptor
> (CLINT). The CLINT block holds memory-mapped control and status
> registers associated with software and timer interrupts.
>
> This driver implements the riscv_get_time() API a
Hi Bin,
On Fri, 2018-12-07 at 21:59 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Nov 15, 2018 at 5:57 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> > > This adds a driver for RISC-V CPU. N
Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> Implement arch_cpu_init() to do some basic architecture level cpu
> initialization, like FPU enable, etc.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - use csr_set() to set MSTATUS_FS
> - only enabling the cycle, time, a
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> With current csr_xxx ops, we cannot pass a macro to parameter
> 'csr', hence we need add another level to allow the parameter
> to be a macro itself, aka indirect stringification.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - new
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds all exception codes in encoding.h.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> arch/riscv/include/asm/encoding.h | 15 +++
> 1 file changed, 15 insertions(+)
>
Reviewed-by: Lukas Auer
__
Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> The standard RISC-V ISA sets aside a 12-bit encoding space for up
> to 4096 CSRs. This adds all known CSR numbers as defined in the
> RISC-V Privileged Architecture Version 1.10.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: No
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> From: Anup Patel
>
> This adds an implementation of riscv_get_time() API that is using
> rdtime instruction.
>
> This is the case for S-mode U-Boot, and is useful for processors
> that support rdtime in M-mode too.
>
> Signed-off-by: Anup Pat
Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds U-Boot syscon driver for SiFive's Core Local Interruptor
> (CLINT). The CLINT block holds memory-mapped control and status
> registers associated with software and timer interrupts.
>
> This driver implements the riscv_get_tim
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> From: Anup Patel
>
> So far we have a Kconfig option for supervisor mode. This adds an
> option for the machine mode.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - incorporated and reworked Anup's S
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> There is no need to expose RISCV_NDS to the Kconfig menu as it is
> an ax25-specific option.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> arch/riscv/cpu/ax25/Kconfig | 8 +++-
> 1 file changed, 3 insertions(+), 5 deletio
Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> RISC-V privileged architecture v1.10 defines a real-time counter,
> exposed as a memory-mapped machine-mode register - mtime. mtime must
> run at constant frequency, and the platform must provide a mechanism
> for determining the timebas
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds a driver for RISC-V CPU. Note the driver will bind
> a RISC-V timer driver if "timebase-frequency" property is
> present in the device tree.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - pass NULL as the timer device to
Hi Bin,
On Thu, 2018-12-06 at 18:07 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Dec 6, 2018 at 7:11 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Wed, 2018-12-05 at 17:59 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
Hi Bin,
On Wed, 2018-12-05 at 17:59 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Nov 14, 2018 at 6:33 PM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Wed, 2018-11-14 at 09:48 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
Hi Bin,
On Mon, 2018-12-03 at 16:45 +0800, Bin Meng wrote:
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 4:12 PM Anup Patel
> wrote:
> >
> > On Mon, Dec 3, 2018 at 1:27 PM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Dec 3, 2018 at 3:44 PM Anup Patel
> > > wrote:
> > > >
> > > > On Mon
Hi Bin,
On Fri, 2018-11-30 at 17:56 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Nov 15, 2018 at 6:59 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> > > The most significant bit in mcaus
Hi Bin,
On Fri, 2018-11-30 at 17:48 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Fri, Nov 16, 2018 at 7:10 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> > > Implement arch_cpu_i
On Mon, 2018-11-26 at 23:10 +0800, Bin Meng wrote:
> On Mon, Nov 26, 2018 at 6:43 PM Anup Patel
> wrote:
> >
> > Currently, the RISC-V U-Boot is saving a2 register at
> > CONFIG_SYS_DRAM_BASE in start.S which does not make sense
> > because there is no information passed by previous booting
> > s
Hi Rick,
On Thu, 2018-11-22 at 17:42 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年11月22日 週四
> 下午5:18寫道：
> >
> > Hi Rick,
> >
> > On Thu, 2018-11-22 at 16:38 +0800, Rick Chen wrote:
> > > Auer, Lukas 於 2018年11月21日 週三
> > > 下午9:09寫道：
> > >
Hi Rick,
On Thu, 2018-11-22 at 16:38 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年11月21日 週三
> 下午9:09寫道：
> >
> > Hi Rick,
> >
> > On Wed, 2018-11-21 at 17:37 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > >
> > >
Hi Rick,
On Wed, 2018-11-07 at 09:54 +0800, Andes wrote:
> From: Rick Chen
>
> AndeStar RISC-V(V5) provide mcache_ctl register which
> can configure I/D cache as enabled or disabled.
>
> This CSR will be encapsulated by CONFIG_RISCV_NDS.
> If you want to configure cache on AndeStar V5
> AE350 p
Hi Anup,
On Wed, 2018-11-21 at 13:47 +, Auer, Lukas wrote:
> Hi Anup,
>
> On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> > This patch adds kconfig option RISCV_SMODE to run u-boot in
>
> nit: U-Boot (also in the first line of the commit message)
>
> >
Hi Palmer,
On Wed, 2018-11-21 at 08:28 -0800, Palmer Dabbelt wrote:
> On Tue, 20 Nov 2018 19:41:10 PST (-0800), a...@brainfault.org wrote:
> > This patch adds kconfig option RISCV_SMODE to run u-boot in
> > S-mode. When this opition is enabled we use s CSRs instead
> > of m CSRs.
> >
> > It is im
On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> This patch adds S-mode defconfigs for QEMU virt machine so
> that we can run u-boot in S-mode on QEMU using M-mode runtime
> firmware (BBL or equivalent).
>
> Signed-off-by: Anup Patel
> Reviewed-by: Bin Meng
> Tested-by: Bin Meng
> ---
>
On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> When u-boot runs in S-mode, the M-mode runtime firmware
> (BBL or equivalent) uses memory range in 0x8000 to
> 0x8020. Due to this, we cannot use 0x8000 as
> SYS_TEXT_BASE when running in S-mode. Instead for S-mode,
> we use 0x80200
Hi Anup,
On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> This patch adds kconfig option RISCV_SMODE to run u-boot in
nit: U-Boot (also in the first line of the commit message)
> S-mode. When this opition is enabled we use s CSRs instead
> of m CSRs.
>
> It is important to note that there
Hi Rick,
On Wed, 2018-11-21 at 17:37 +0800, Rick Chen wrote:
> Hi Lukas
>
> > >
> > > Hi Rick,
> > >
> > > Thanks for pulling my changes! I have some notes and questions on
> > > it.
> > >
> > > I can't find all of your patches on the mailing list, for example
> > > the patch "configs:
> > > a
On Tue, 2018-11-20 at 18:18 +0800, ub...@andestech.com wrote:
> Hi Tom,
>
> Please pull the following patch from u-boot-riscv into your tree.
> Thanks!
>
> The following changes since commit
> d73d81fd85e4a030ade42c4b2d13466d45090aa3:
>
> Merge tag 'mips-pull-2018-11-18' of git://git.denx.d
Hi Rick,
On Tue, 2018-11-13 at 14:52 +0800, Rick Chen wrote:
> Bin Meng 於 2018年11月13日 週二 下午2:49寫道：
> >
> > Hi Rick,
> >
> > On Tue, Nov 13, 2018 at 2:41 PM Rick Chen
> > wrote:
> > >
> > > > > This patch series includes general fixes and cleanup for
> > > > > RISC-V. It also adds
> > > > > su
On Wed, 2018-11-14 at 09:23 +0100, Alexander Graf wrote:
> On 11/12/2018 08:57 PM, Heinrich Schuchardt wrote:
> > qemu-riscv32_defconfig and qemu-riscv64_defconfig do not supply a
> > timer.
> > This causes the EFI selftest to hang on tests which require a
> > timer.
> >
> > So let's disable CONFI
Hi Bin,
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> Implement arch_cpu_init() to do some basic architecture level cpu
> initialization, like FPU enable, etc.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/cpu.c | 21 +
> 1 file changed, 21 insertions(+)
>
>
Hi Bin,
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> Allow U-Boot to run on hart 0 only, and suspend other harts.
>
> With this change, '-smp n' works on QEMU RISC-V board.
>
> Signed-off-by: Bin Meng
>
> ---
>
> arch/riscv/cpu/start.S | 4
> 1 file changed, 4 insertions(+)
>
Hi Bin,
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> Use a variable 'code' to store the exception code to simplify the
> codes in handle_trap().
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/lib/interrupts.c | 16 ++--
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
Hi Bin,
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> The most significant bit in mcause register should be masked to
> form the exception code for _exit_trap().
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/lib/interrupts.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> With this change, we can avoid a forward declaration.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/lib/interrupts.c | 62 ++-
> --
> 1 file changed, 30 insertions(+), 32 deletions(-)
>
Reviewed-by
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> At present the trap handler returns to M-mode only. Change to
> returning to previous privilege level instead.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/mtrap.S | 3 ---
> 1 file changed, 3 deletions(-)
>
Reviewed-by: Lukas Auer
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> sp cannot be loaded before restoring other registers.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/mtrap.S | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Lukas Auer
Good catch!
> diff --git a/arch/riscv/cp
On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> Currently the M-mode trap handler codes are in start.S. For future
> extension, move them to a separate file mtrap.S.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/Makefile | 2 +-
> arch/riscv/cpu/mtrap.S | 106
> ++
Hi Bin,
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> The standard RISC-V ISA sets aside a 12-bit encoding space for up
> to 4096 CSRs. This adds all known CSR numbers as defined in the
> RISC-V Privileged Architecture Version 1.10.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/inclu
Hi Bin,
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> This calls cpu_probe_all() to probe all available cpus.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/qemu/Kconfig | 1 +
> arch/riscv/cpu/qemu/cpu.c | 14 ++
> 2 files changed, 15 insertions(+)
>
Reviewed-by:
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> Increase the heap size for the pre-relocation stage, so that CPU
> driver can be loaded.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/Kconfig | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Lukas Auer
Hi Bin,
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> At present there are just two levels of Kconfig option hierarchy in
> RISC-V. This adds a new level for platform to specify additional
> options. It is organized in a way that platform-specific options
> followed by board-specific ones,
Hi Bin,
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> This adds a driver for RISC-V CPU. Note the driver will bind
> a RISC-V timer driver if "timebase-frequency" property is
> present in the device tree.
>
> Signed-off-by: Bin Meng
> ---
>
Since we have the CPU driver, we could also en
Hi Bin,
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> To enumerate devices on the /soc/ node, create a "simple-bus"
> driver to match "riscv-virtio-soc".
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/cpu/qemu/cpu.c | 13 +
> 1 file changed, 13 insertions(+)
>
Reviewed-b
Hi Bin,
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> This adds a timebase_freq member to the 'struct cpu_platdata', to
> hold the "timebase-frequency" value in the cpu or /cpus node.
>
> Signed-off-by: Bin Meng
> ---
>
> include/cpu.h | 3 +++
> 1 file changed, 3 insertions(+)
>
Revi
Hi Bin,
On Wed, 2018-11-14 at 09:48 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Nov 13, 2018 at 10:45 PM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> > > This adds U-Boot syscon driver for RIS
On Tue, 2018-11-13 at 10:01 +0100, Alexander Graf wrote:
>
> On 09.11.18 13:59, Lukas Auer wrote:
> > QEMU embeds the location of the kernel image in the device tree.
> > Store
> > this address in the environment as variable kernel_start. It is
> > used in
> > the board-local distro boot command Q
Hi Bin,
On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> This adds U-Boot syscon driver for RISC-V Core Local Interruptor
> (CLINT). The CLINT block holds memory-mapped control and status
> registers associated with software and timer interrupts.
>
> 3 APIs are provided for U-Boot to implemen
Hi Bin,
On Tue, 2018-11-13 at 15:34 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Oct 31, 2018 at 11:01 PM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Wed, 2018-10-31 at 10:13 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> &g
Hi Bin,
On Wed, 2018-10-10 at 22:06 -0700, Bin Meng wrote:
> Currently the comments of several APIs (eg: dm_init_and_scan()) say:
>
> @pre_reloc_only: If true, bind only drivers with the
> DM_FLAG_PRE_RELOC
> flag. If false bind all drivers.
>
> The 'Pre-Relocation Support' chapter in doc/driver
Hi Rick,
On Tue, 2018-11-06 at 10:28 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年11月4日 週日
> 下午10:21寫道：
> >
> > Hi Rick,
> >
> > On Thu, 2018-11-01 at 12:08 +0800, Andes wrote:
> > > From: Rick Chen
> > >
> > > AndeStar RISC-V(V5)
EFI applications on the
> RISC-V
> QEMU port.
>
> Reported-by: Auer, Lukas
> Signed-off-by: Alexander Graf
> ---
> lib/efi_loader/efi_runtime.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>
Tested-by: Lukas Auer
Thanks for the patch! That explains why it was working on t
Hi Bin,
On Sun, 2018-11-04 at 22:39 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
> wrote:
> >
> > QEMU embeds the location of the kernel image in the device tree.
> > Store
> > this address in the environment as variable kernel_start and use it
> > in
> > CO
Hi Rick,
On Thu, 2018-11-01 at 12:08 +0800, Andes wrote:
> From: Rick Chen
>
> AndeStar RISC-V(V5) provide mcache_ctl register which
> can configure I/D cache as enabled or disabled.
>
> This CSR will be encapsulated by CONFIG_RISCV_NDS.
> If you want to configure cache on AndeStar V5
> AE350 p
On Sat, 2018-11-03 at 20:33 +0100, Alexander Graf wrote:
>
> On 03.11.18 18:07, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
> > >
> > > On 30.10.18 16:02, Auer, Lukas wrote:
> > > > On Tue, 2018-10-30 at 13:55 +0100, L
Hi Rick,
On Wed, 2018-10-31 at 12:22 +0800, Rick Chen wrote:
> Greentime Hu 於 2018年10月31日 週三 上午11:48寫道：
> >
> > Rick Chen 於 2018年10月29日 週一 上午10:25寫道：
> > >
> > > Auer, Lukas 於 2018年10月27日 週六
> > > 上午12:27寫道：
> > > >
> > > >
On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
>
> On 30.10.18 16:02, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
> > > QEMU embeds the location of the kernel image in the device tree.
> > > Store
> > > this
Hi Bin,
On Wed, 2018-10-31 at 10:13 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
> wrote:
> >
> > RISC-V has two code models, medium low (medlow) and medium any
> > (medany).
> > Medlow limits addressable memory to a single 2 GiB range between
> > the
> > ab
On Tue, 2018-10-30 at 16:27 +0100, Alexander Graf wrote:
>
> On 30.10.18 16:02, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
> > > QEMU embeds the location of the kernel image in the device tree.
> > > Store
> > > this
On Tue, 2018-10-30 at 13:55 +0100, Lukas Auer wrote:
> QEMU embeds the location of the kernel image in the device tree.
> Store
> this address in the environment as variable kernel_start and use it
> in
> CONFIG_BOOTCOMMAND to boot the kernel. Use the device tree passed by
> the
> prior boot stage
On Tue, 2018-10-30 at 14:53 +0100, Alexander Graf wrote:
>
> On 30.10.18 14:44, Auer, Lukas wrote:
> > On Tue, 2018-10-30 at 14:19 +0100, Alexander Graf wrote:
> > >
> > > On 30.10.18 13:55, Lukas Auer wrote:
> > > > The device tree passed by the pr
On Tue, 2018-10-30 at 14:19 +0100, Alexander Graf wrote:
>
> On 30.10.18 13:55, Lukas Auer wrote:
> > The device tree passed by the prior boot stage can be used to boot
> > Linux. Store it as environment variable "prior_stage_dtb", so that
> > it
> > can be used as part of the boot command.
> >
>
Hi Rick,
On Tue, 2018-10-30 at 10:48 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年10月29日 週一
> 下午8:13寫道：
> >
> > Hi Rick,
> >
> > On Mon, 2018-10-29 at 11:16 +0800, Rick Chen wrote:
> > > Auer, Lukas 於 2018年10月27日 週六
> > > 上午12:32寫道：
> >
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