Hi Rick,
On Tue, 2018-10-30 at 09:49 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年10月30日 週二
> 上午12:43寫道：
> >
> > Hi Rick,
> >
> > On Thu, 2018-10-25 at 15:56 +, Auer, Lukas wrote:
> > > Hi Rick,
> > >
> > > On Thu, 2018-10-25 at 09:
Hi Rick,
On Thu, 2018-10-25 at 15:56 +, Auer, Lukas wrote:
> Hi Rick,
>
> On Thu, 2018-10-25 at 09:16 +0800, Rick Chen wrote:
> > Auer, Lukas 於 2018年10月24日 週三
> > 下午10:14寫道：
> > >
> > > Hi Rick,
> > >
> > > On Wed, 2018-10-24 at 13
Hi Rick,
On Mon, 2018-10-29 at 11:16 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年10月27日 週六
> 上午12:32寫道：
> >
> > Hi Rick,
> >
> > On Mon, 2018-10-22 at 16:16 +0800, Andes wrote:
> > > From: Rick Chen
> > >
> > > AndeStar V5 provide m
Hi Rick,
On Mon, 2018-10-22 at 16:16 +0800, Andes wrote:
> From: Rick Chen
>
> AndeStar V5 provide mcache_ctl register which can configure
> I/D cache as enabled or disabled.
>
> This CSR will be encapsulated by CONFIG_NDS_V5.
> If you want to configure cache on AndeStar V5
> AE350 platform. YO
Hi Rick,
On Mon, 2018-10-22 at 09:39 +0800, Rick Chen wrote:
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Saturday, October 20, 2018 6:08 AM
> > To: u-boot@lists.denx.de
> > Cc: Bin Meng; Lukas Auer; Greentime Hu; Alexander Graf; Rick Jian-
> > Zhi Chen(陳建志)
> > Subject:
Hi Bin,
On Fri, 2018-10-26 at 21:20 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Oct 22, 2018 at 5:37 PM Bin Meng wrote:
> >
> > Hi Lukas,
> >
> > On Sat, Oct 20, 2018 at 6:08 AM Lukas Auer
> > wrote:
> > >
> > >
> > > This patch series includes general fixes and cleanup for RISC-V.
> > >
Hi Rick and Bin,
On Wed, 2018-10-24 at 14:54 +0800, Rick Chen wrote:
> > > > Print the address of the u-boot device tree.
> > > >
> > >
> > > This is unnecessary as it is already done by 'fdt' command.
> > >
>
> Hi Bin & Lukas
>
> At the beginning, I really don't understand the fdt Usage:
> M
Hi Bin,
On Mon, 2018-10-22 at 17:35 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:11 AM Lukas Auer
> wrote:
> >
> > Signed-off-by: Lukas Auer
> > ---
> >
> > include/dm/ofnode.h | 10 ++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/include/dm/ofnode.h
Hi Rick,
On Thu, 2018-10-25 at 09:16 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年10月24日 週三
> 下午10:14寫道：
> >
> > Hi Rick,
> >
> > On Wed, 2018-10-24 at 13:47 +0800, Rick Chen wrote:
> > > Rick Chen 於 2018年10月24日 週三 下午1:20寫道：
> > >
Hi Bin,
On Thu, 2018-10-25 at 10:57 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Oct 22, 2018 at 5:19 PM Bin Meng wrote:
> >
> > Hi Lukas,
> >
> > On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
> > wrote:
> > >
> > > CONFIG_INIT_CRITICAL is deprecated and not used for RISC-V.
> > > Remove it.
Hi Bin,
On Mon, 2018-10-22 at 15:36 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
> wrote:
> >
> > RISC-V u-boot reimplements the generic io functions from
>
> nits: U-Boot
>
Fixed in v2.
Thanks,
Lukas
> > asm-generic/io.h. Remove the redundant implement
Hi Bin,
On Mon, 2018-10-22 at 15:36 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
> wrote:
> >
> > Replace the barrier functions in arch/riscv/include/asm/io.h with
> > those
> > defined in barrier.h, which is imported from Linux. This version is
> > modified
Hi Rick and Bin,
On Tue, 2018-10-23 at 13:52 +0800, Rick Chen wrote:
> > > -static void _exit_trap(int code, uint epc, struct pt_regs *regs)
> > > +static void _exit_trap(ulong code, ulong epc, struct pt_regs
> > > *regs)
> > > {
> > > static const char * const exception_code[] = {
> > >
Hi Bin,
On Mon, 2018-10-22 at 15:22 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
> wrote:
> >
> > Move the target selection into a separate file (Kconfig.board) to
> > avoid
> > clutter once we support more boards.
> >
> > Signed-off-by: Lukas Auer
> > ---
Hi Bin,
On Thu, 2018-10-25 at 10:50 +0800, Bin Meng wrote:
> On Tue, Oct 23, 2018 at 10:48 AM Rick Chen
> wrote:
> >
> > > > Subject: Re: [PATCH 09/30] riscv: move target selection into
> > > > separate file
> > > >
> > > > Hi Lukas,
> > > >
> > > > On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer <
Hi Rick,
On Thu, 2018-10-25 at 11:28 +0800, Rick Chen wrote:
> Bin Meng 於 2018年10月25日 週四 上午11:16寫道：
> >
> > Hi Rick,
> >
> > On Thu, Oct 25, 2018 at 11:11 AM Rick Chen
> > wrote:
> > >
> > > Bin Meng 於 2018年10月25日 週四 上午10:33寫道：
> > > >
> > > > Hi Rick,
> > > >
> > > > On Thu, Oct 25, 2018
Hi Bin,
On Mon, 2018-10-22 at 15:21 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer
> wrote:
> >
> > Use the new Kconfig entries to construct the ISA string for the
> > -march
> > compiler flag. The -mabi compiler flag is selected based on the
> > base
> > inte
Hi Bin,
On Wed, 2018-10-24 at 23:32 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Oct 24, 2018 at 11:21 PM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-10-22 at 15:21 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> &g
Hi Bin,
On Mon, 2018-10-22 at 15:21 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer
> wrote:
> >
> > Add Kconfig entries for the C (compressed instructions) and A
> > (atomic
> > instructions) ISA extensions. Only the C ISA extension is
> > selectable.
> > This
Hi Bin,
On Mon, 2018-10-22 at 14:23 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Sat, Oct 20, 2018 at 6:09 AM Lukas Auer
> wrote:
> >
> > RISC-V defines the base integer instruction sets as RV32I and
> > RV64I.
> > Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_64I to
> > match
>
> A
Hi Rick and Bin,
On Tue, 2018-10-23 at 09:30 +0800, Rick Chen wrote:
> > From: Bin Meng [mailto:bmeng...@gmail.com]
> > Sent: Monday, October 22, 2018 2:16 PM
> > To: Lukas Auer
> > Cc: U-Boot Mailing List; Rick Jian-Zhi Chen(陳建志)
> > Subject: Re: [PATCH 02/30] riscv: ignore device tree binaries
>
Hi Rick,
On Wed, 2018-10-24 at 13:47 +0800, Rick Chen wrote:
> Rick Chen 於 2018年10月24日 週三 下午1:20寫道：
> >
> > Bin Meng 於 2018年10月24日 週三 上午11:34寫道：
> > >
> > > Hi Rich,
> > >
> > > On Wed, Oct 24, 2018 at 10:37 AM Rick Chen
> > > wrote:
> > > >
> > > > > > > The labels nmi_vector, trap_vector
Hi Bin,
On Thu, 2018-10-04 at 15:01 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Oct 4, 2018 at 12:45 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Wed, 2018-09-26 at 06:55 -0700, Bin Meng wrote:
> > > This series adds QEMU RISC-V 'vir
Hi Bin,
On Wed, 2018-09-26 at 06:55 -0700, Bin Meng wrote:
> This series adds QEMU RISC-V 'virt' board target support, with the
> hope of helping people easily test U-Boot on RISC-V.
>
> Some existing RISC-V codes have been changed to make it easily to
> support new targets. Some spotted coding s
On Wed, 2018-09-26 at 06:55 -0700, Bin Meng wrote:
> Add printing of U-Boot relocation address.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - net patch to print the relocation address in cmd 'bdinfo'
>
> Changes in v2: None
>
> cmd/bdinfo.c | 2 ++
> 1 file changed, 2 insertions
On Wed, 2018-09-26 at 06:55 -0700, Bin Meng wrote:
> This implies DM support for some common drivers that are used on
> RISC-V.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - new patch to imply DM support for some common drivers
>
> Changes in v2: None
>
> arch/Kconfig
Hi Bin,
On Wed, 2018-09-26 at 06:55 -0700, Bin Meng wrote:
> We don't have a reset method on any RISC-V board yet. Instead of
> adding the same 'unsupported' message for each CPU variant it might
> make more sense to add a generic do_reset function for all CPU
> variants to lib/, similar to the on
Hi Bin,
On Tue, 2018-09-18 at 16:50 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Sep 18, 2018 at 6:01 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-17 at 13:02 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
Hi Bin,
On Tue, 2018-09-18 at 16:53 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Sep 18, 2018 at 5:59 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-17 at 12:55 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
Hi Bin,
On Mon, 2018-09-17 at 13:02 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Sep 17, 2018 at 5:09 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > We don't have a reset method on
Hi Bin,
On Mon, 2018-09-17 at 12:55 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Sep 17, 2018 at 4:54 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > This adds a helper routine to print C
Hi Bin,
On Mon, 2018-09-17 at 13:18 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Sep 17, 2018 at 5:02 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > This adds QEMU RISC-V '
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> We don't have a reset method on any RISC-V board yet. Instead of
> adding the same 'unsupported' message for each CPU variant it might
> make more sense to add a generic do_reset function for all CPU
> variants to lib/, similar to the on
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds QEMU RISC-V 'virt' board target support, with the hope of
> helping people easily test U-Boot on RISC-V.
>
> The QEMU virt machine models a generic RISC-V virtual machine with
> support for the VirtIO standard networking and b
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> RISC-V is a pretty new architecture and should support DM and
> OF_CONTROL by default.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are quite a lot of mixed tabs and spaces in the ae350.dts.
> Clean them up.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
> common for all RISC-V targets.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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h
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> So far this is hardcoded to zero, and we should read the value from
> mhartid CSR and pass it to Linux kernel.
>
> Suggested-by: Lukas Auer
> Signed-off-by: Bin Meng
>
>
Reviewed-by: Lukas Auer
_
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There is no reason to keep two versions of CSR read/write defines
> in encoding.h. We already have one set of defines in csr.h, which
> is from Linux kernel, and let's drop the one in encoding.h.
>
> Signed-off-by: Bin Meng
>
>
Reviewed-by:
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds a helper routine to print CPU information. Currently
> it prints all the instruction set extensions that the processor
> core supports.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> arch/riscv/Makefile
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> At present the compiler flag against which architecture and abi
> variant the riscv image is built for is not explicitly indicated
> which means the default compiler configuration is used. But this
> does not work if we want to build a different
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are several coding style issues in the linker script. Fix them.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The linker script can be shared by all RISC-V targets. Move it to
> a common place.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Since the mach_id is not used by RISC-V, remove it.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The first argument of Linux kernel is the risc-v core hart id,
> from which the kernel is booted from. It is not the mach_id,
> which seems to be copied from arm.
>
> While we are here, this also changes the Linux kernel entry
> parameters' type
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This was copied from ARM, and does not apply to RISC-V. While we
> are here, bootm.h is eventually removed as its content is only
> the inclusion of setup.h.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
_
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> It's RISC-V that is the official name, not RISCV.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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Hi Bin,
On Thu, 2018-09-06 at 11:15 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Sep 5, 2018 at 5:37 PM Auer, Lukas
> wrote:
> >
> > On Wed, 2018-09-05 at 10:34 +0800, Bin Meng wrote:
> > > Hi Rick,
> > >
> > > On
Hi Bin,
On Thu, 2018-09-06 at 11:14 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Sep 5, 2018 at 5:35 PM Auer, Lukas
> wrote:
> >
> > On Wed, 2018-09-05 at 09:28 +0800, Rick Chen wrote:
> > > > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de
Hi Bin,
On Thu, 2018-09-06 at 10:57 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Sep 4, 2018 at 5:41 AM Auer, Lukas
> wrote:
> >
> > On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:
> > > The first argument of Linux kernel is the risc-v core hart id,
>
Hi Bin,
On Thu, 2018-09-06 at 11:03 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Sep 4, 2018 at 5:42 AM Auer, Lukas
> wrote:
> >
> > On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:
> > > This adds a helper routine to print CPU information. Currently
> &
On Wed, 2018-09-05 at 10:34 +0800, Bin Meng wrote:
> Hi Rick,
>
> On Wed, Sep 5, 2018 at 9:27 AM Rick Chen
> wrote:
> >
> > > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > > > Sent: Wednesday, September 05, 2018 5:53 AM
> > &
On Wed, 2018-09-05 at 09:28 +0800, Rick Chen wrote:
> > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Wednesday, September 05, 2018 5:53 AM
> > > To: bmeng...@gmail.com
> > > Cc: Rick Jian-Zhi Chen(陳建志); u-boot@lists.denx.de
>
On Tue, 2018-09-04 at 17:31 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Sep 4, 2018 at 5:39 AM Auer, Lukas
> wrote:
> >
> > On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:
> > > This adds QEMU RISC-V 'virt' board target support, with the hope
On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:
> This adds a helper routine to print CPU information. Currently
> it prints all the instruction set extensions that the processor
> core supports.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/Makefile | 1 +
> arch/riscv/cpu/Mak
On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:
> The first argument of Linux kernel is the risc-v core hart id,
> from which the kernel is booted from. It is not the mach_id,
> which seems to be copied from arm.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/lib/bootm.c | 18 +
On Thu, 2018-08-30 at 00:54 -0700, Bin Meng wrote:
> This adds QEMU RISC-V 'virt' board target support, with the hope of
> helping people easily test U-Boot on RISC-V.
>
> The QEMU virt machine models a generic RISC-V virtual machine with
> support for the VirtIO standard networking and block stor
On Fri, 2018-01-26 at 16:27 +, Bryan O'Donoghue wrote:
> This patch adds a sec_init call into arch_misc_init(). Doing so in
> conjunction with the patch "drivers/crypto/fsl: assign job-rings to
> non-TrustZone" enables use of the CAAM in Linux when OPTEE/TrustZone
> is
> active.
>
> u-boot wil
On Fri, 2018-01-26 at 12:24 +, Bryan O'Donoghue wrote:
> This patch adds a sec_init call into arch_misc_init(). Doing so in
> conjunction with the patch "drivers/crypto/fsl: assign job-rings to
> non-TrustZone" enables use of the CAAM in Linux when OPTEE/TrustZone
> is
> active.
>
> u-boot wil
On Fri, 2018-01-26 at 11:32 +, Bryan O'Donoghue wrote:
>
> On 26/01/18 09:09, Auer, Lukas wrote:
> > Hi Bryan,
> >
> > this fails to apply for me on current HEAD. It seems like you have
> > additional modifications to wrap7.c in your tree (there is
On Fri, 2018-01-26 at 02:09 +, Bryan O'Donoghue wrote:
> This patch adds a sec_init call into board_init. Doing so in
> conjunction
> with the patch "drivers/crypto/fsl: assign job-rings to non-
> TrustZone"
> enables use of the CAAM in Linux when OPTEE/TrustZone is active.
>
> u-boot will ini
On Fri, 2018-01-26 at 02:09 +, Bryan O'Donoghue wrote:
> After enabling TrustZone various parts of the CAAM silicon become
> inaccessible to non TrustZone contexts. The job-ring registers are
> designed
> to allow non TrustZone contexts like Linux to still submit jobs to
> CAAM
> even after Tru
On Thu, 2018-01-25 at 15:53 +, Bryan O'Donoghue wrote:
>
> On 25/01/18 13:11, Lukas Auer wrote:
> > Extend the instantiate_rng() function and the corresponding CAAM
> > job
> > descriptor to instantiate all RNG state handles. This moves the RNG
> > instantiation code in line with the CAAM kern
On Wed, 2018-01-24 at 19:41 +, Bryan O'Donoghue wrote:
>
> On 24/01/18 17:41, Auer, Lukas wrote:
> > Thanks for adding me to the CC list.
> > I have experienced the same thing regarding the dec0 registers.
> > However, I don't understand why you wan
On Wed, 2018-01-24 at 14:35 +, Bryan O'Donoghue wrote:
>
> On 24/01/18 12:52, Auer, Lukas wrote:
> > On Tue, 2018-01-23 at 21:10 +, Bryan O'Donoghue wrote:
> > > This series is the u-boot fix to a problem we encountered when
> > > enabling
> &g
On Tue, 2018-01-23 at 21:10 +, Bryan O'Donoghue wrote:
> This series is the u-boot fix to a problem we encountered when
> enabling
> OPTEE/TrustZone on the WaRP7. The symptom is once TrustZone is
> activated
> the first page of CAAM registers becomes read-only, read-zero from
> the
> perspectiv
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