Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> RISC-V privileged architecture v1.10 defines a real-time counter,
> exposed as a memory-mapped machine-mode register - mtime. mtime must
> run at constant frequency, and the platform must provide a mechanism
> for determining the
Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds U-Boot syscon driver for SiFive's Core Local Interruptor
> (CLINT). The CLINT block holds memory-mapped control and status
> registers associated with software and timer interrupts.
>
> This driver implements the
Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> The standard RISC-V ISA sets aside a 12-bit encoding space for up
> to 4096 CSRs. This adds all known CSR numbers as defined in the
> RISC-V Privileged Architecture Version 1.10.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2:
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> With current csr_xxx ops, we cannot pass a macro to parameter
> 'csr', hence we need add another level to allow the parameter
> to be a macro itself, aka indirect stringification.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> -
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds all exception codes in encoding.h.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> arch/riscv/include/asm/encoding.h | 15 +++
> 1 file changed, 15 insertions(+)
>
Reviewed-by: Lukas Auer
Hi Bin,
On Fri, 2018-12-07 at 21:59 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Nov 15, 2018 at 5:57 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-11-13 at 00:21 -0800, Bin Meng wrote:
> > > This adds a driver for RISC-V CPU. N
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds a driver for RISC-V CPU. Note the driver will bind
> a RISC-V timer driver if "timebase-frequency" property is
> present in the device tree.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - pass NULL as the timer device
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> From: Anup Patel
>
> This adds an implementation of riscv_get_time() API that is using
> rdtime instruction.
>
> This is the case for S-mode U-Boot, and is useful for processors
> that support rdtime in M-mode too.
>
> Signed-off-by: Anup
Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> Implement arch_cpu_init() to do some basic architecture level cpu
> initialization, like FPU enable, etc.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - use csr_set() to set MSTATUS_FS
> - only enabling the cycle, time,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> From: Anup Patel
>
> So far we have a Kconfig option for supervisor mode. This adds an
> option for the machine mode.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - incorporated and reworked Anup's
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> This adds U-Boot syscon driver for SiFive's Core Local Interruptor
> (CLINT). The CLINT block holds memory-mapped control and status
> registers associated with software and timer interrupts.
>
> This driver implements the riscv_get_time() API
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> In arch_cpu_init_dm() do some basic architecture level cpu
> initialization, like FPU enable, etc.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - only initialize mcounteren CSR for S-mode
> - only touch satp in M-mode U-Boot
> -
On Tue, 2018-12-11 at 01:35 -0800, Bin Meng wrote:
> This is not used by any board. Remove it.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - new patch to remove ae350.dts
>
> Changes in v2: None
>
> arch/riscv/dts/ae350.dts | 229 ---
>
Hi Bin,
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> This updates supports_extension() implementation to use the desc
> string from the cpu driver whenever possible, which avoids the
> reading of misa CSR for S-mode U-Boot.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> -
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> With DM CPU driver, the non-DM version of print_cpuinfo() is no
> longer needed.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - new patch to remove non-DM version of print_cpuinfo()
>
> Changes in v2: None
>
>
On Tue, 2018-12-11 at 01:35 -0800, Bin Meng wrote:
> Avoid reading mhartid CSR directly, instead use the one we saved
> in the global data structure before.
>
> With this patch, BBL no longer needs to be hacked to provide the
> mhartid CSR emulation for S-mode U-Boot.
>
> Signed-off-by: Bin Meng
On Tue, 2018-12-11 at 01:34 -0800, Bin Meng wrote:
> At present the hart id passed via a0 in the U-Boot entry is saved
> to s0 at the beginning but does not preserve later. Save it to the
> global data structure so that it can be used later.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in
Hi Bin,
On Tue, 2018-12-11 at 23:11 -0800, Bin Meng wrote:
> This updates supports_extension() implementation to use the desc
> string from the cpu driver whenever possible, which avoids the
> reading of misa CSR for S-mode U-Boot.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v4:
> -
Hi Bin,
On Wed, 2018-12-05 at 17:59 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Wed, Nov 14, 2018 at 6:33 PM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Wed, 2018-11-14 at 09:48 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
Hi Bin,
On Thu, 2018-12-06 at 18:07 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Dec 6, 2018 at 7:11 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Wed, 2018-12-05 at 17:59 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
Hi Bin,
On Mon, 2018-12-03 at 16:45 +0800, Bin Meng wrote:
> Hi Anup,
>
> On Mon, Dec 3, 2018 at 4:12 PM Anup Patel
> wrote:
> >
> > On Mon, Dec 3, 2018 at 1:27 PM Bin Meng wrote:
> > >
> > > Hi Anup,
> > >
> > > On Mon, Dec 3, 2018 at 3:44 PM Anup Patel
> > > wrote:
> > > >
> > > > On
Hi Bin,
On Fri, 2018-11-30 at 17:48 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Fri, Nov 16, 2018 at 7:10 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> > > Implement arch_cpu_i
Hi Bin,
On Fri, 2018-11-30 at 17:56 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Nov 15, 2018 at 6:59 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Tue, 2018-11-13 at 00:22 -0800, Bin Meng wrote:
> > > The most significant bit in m
Hi Rick,
On Wed, 2018-11-07 at 09:54 +0800, Andes wrote:
> From: Rick Chen
>
> AndeStar RISC-V(V5) provide mcache_ctl register which
> can configure I/D cache as enabled or disabled.
>
> This CSR will be encapsulated by CONFIG_RISCV_NDS.
> If you want to configure cache on AndeStar V5
> AE350
Hi Palmer,
On Wed, 2018-11-21 at 08:28 -0800, Palmer Dabbelt wrote:
> On Tue, 20 Nov 2018 19:41:10 PST (-0800), a...@brainfault.org wrote:
> > This patch adds kconfig option RISCV_SMODE to run u-boot in
> > S-mode. When this opition is enabled we use s CSRs instead
> > of m CSRs.
> >
> > It is
Hi Anup,
On Wed, 2018-11-21 at 13:47 +, Auer, Lukas wrote:
> Hi Anup,
>
> On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> > This patch adds kconfig option RISCV_SMODE to run u-boot in
>
> nit: U-Boot (also in the first line of the commit message)
>
>
On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> When u-boot runs in S-mode, the M-mode runtime firmware
> (BBL or equivalent) uses memory range in 0x8000 to
> 0x8020. Due to this, we cannot use 0x8000 as
> SYS_TEXT_BASE when running in S-mode. Instead for S-mode,
> we use
Hi Anup,
On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> This patch adds kconfig option RISCV_SMODE to run u-boot in
nit: U-Boot (also in the first line of the commit message)
> S-mode. When this opition is enabled we use s CSRs instead
> of m CSRs.
>
> It is important to note that
Hi Rick,
On Wed, 2018-11-21 at 17:37 +0800, Rick Chen wrote:
> Hi Lukas
>
> > >
> > > Hi Rick,
> > >
> > > Thanks for pulling my changes! I have some notes and questions on
> > > it.
> > >
> > > I can't find all of your patches on the mailing list, for example
> > > the patch "configs:
> > >
On Wed, 2018-11-21 at 09:11 +0530, Anup Patel wrote:
> This patch adds S-mode defconfigs for QEMU virt machine so
> that we can run u-boot in S-mode on QEMU using M-mode runtime
> firmware (BBL or equivalent).
>
> Signed-off-by: Anup Patel
> Reviewed-by: Bin Meng
> Tested-by: Bin Meng
> ---
>
Hi Rick,
On Thu, 2018-11-22 at 16:38 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年11月21日 週三
> 下午9:09寫道：
> >
> > Hi Rick,
> >
> > On Wed, 2018-11-21 at 17:37 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > >
> > >
Hi Rick,
On Thu, 2018-11-22 at 17:42 +0800, Rick Chen wrote:
> Auer, Lukas 於 2018年11月22日 週四
> 下午5:18寫道：
> >
> > Hi Rick,
> >
> > On Thu, 2018-11-22 at 16:38 +0800, Rick Chen wrote:
> > > Auer, Lukas 於 2018年11月21日 週三
> > > 下午9:09寫道：
> > >
On Tue, 2018-11-20 at 18:18 +0800, ub...@andestech.com wrote:
> Hi Tom,
>
> Please pull the following patch from u-boot-riscv into your tree.
> Thanks!
>
> The following changes since commit
> d73d81fd85e4a030ade42c4b2d13466d45090aa3:
>
> Merge tag 'mips-pull-2018-11-18' of
On Mon, 2018-11-26 at 23:10 +0800, Bin Meng wrote:
> On Mon, Nov 26, 2018 at 6:43 PM Anup Patel
> wrote:
> >
> > Currently, the RISC-V U-Boot is saving a2 register at
> > CONFIG_SYS_DRAM_BASE in start.S which does not make sense
> > because there is no information passed by previous booting
> >
Hi Rick,
On Wed, 2019-01-02 at 10:54 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Monday, December 31, 2018 2:28 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Anup Patel; Lukas Auer; Rick Jian-Zhi Chen(陳建志); Bin Meng;
> > >
Hi Rick,
On Thu, 2019-01-03 at 08:48 +0800, Rick Chen wrote:
> Hi Lukas
>
> Auer, Lukas 於 2019年1月2日 週三 下午8:22寫道：
> > Hi Rick,
> >
> > On Wed, 2019-01-02 at 10:54 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > > From: Lukas
Hi Bryan,
On Thu, 2019-01-03 at 01:44 +, Bryan O'Donoghue wrote:
> This patch imports the Linux kernel warp7 dts as at upstream kernel
> commit
> cf76c364a1e1.
>
> The following was dropped from the incoming kernel DTS file
>
> - {
> - pinctrl-names = "default";
> - pinctrl-0 =
Hi Bin,
On Mon, 2018-09-17 at 13:18 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Sep 17, 2018 at 5:02 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > This adds QEMU RISC
Hi Bin,
On Mon, 2018-09-17 at 12:55 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Sep 17, 2018 at 4:54 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > This adds a helper routine to print C
Hi Bin,
On Mon, 2018-09-17 at 13:02 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Mon, Sep 17, 2018 at 5:09 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> > > We don't have a reset method on
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
> common for all RISC-V targets.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are quite a lot of mixed tabs and spaces in the ae350.dts.
> Clean them up.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The first argument of Linux kernel is the risc-v core hart id,
> from which the kernel is booted from. It is not the mach_id,
> which seems to be copied from arm.
>
> While we are here, this also changes the Linux kernel entry
> parameters'
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> Since the mach_id is not used by RISC-V, remove it.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> RISC-V is a pretty new architecture and should support DM and
> OF_CONTROL by default.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> At present the compiler flag against which architecture and abi
> variant the riscv image is built for is not explicitly indicated
> which means the default compiler configuration is used. But this
> does not work if we want to build a different
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> We don't have a reset method on any RISC-V board yet. Instead of
> adding the same 'unsupported' message for each CPU variant it might
> make more sense to add a generic do_reset function for all CPU
> variants to lib/, similar to the
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds a helper routine to print CPU information. Currently
> it prints all the instruction set extensions that the processor
> core supports.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in v2: None
>
> arch/riscv/Makefile
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There is no reason to keep two versions of CSR read/write defines
> in encoding.h. We already have one set of defines in csr.h, which
> is from Linux kernel, and let's drop the one in encoding.h.
>
> Signed-off-by: Bin Meng
>
>
Reviewed-by:
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> So far this is hardcoded to zero, and we should read the value from
> mhartid CSR and pass it to Linux kernel.
>
> Suggested-by: Lukas Auer
> Signed-off-by: Bin Meng
>
>
Reviewed-by: Lukas Auer
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> It's RISC-V that is the official name, not RISCV.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This was copied from ARM, and does not apply to RISC-V. While we
> are here, bootm.h is eventually removed as its content is only
> the inclusion of setup.h.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
Hi Bin,
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> This adds QEMU RISC-V 'virt' board target support, with the hope of
> helping people easily test U-Boot on RISC-V.
>
> The QEMU virt machine models a generic RISC-V virtual machine with
> support for the VirtIO standard networking and
On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> The linker script can be shared by all RISC-V targets. Move it to
> a common place.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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On Mon, 2018-09-10 at 21:54 -0700, Bin Meng wrote:
> There are several coding style issues in the linker script. Fix them.
>
> Signed-off-by: Bin Meng
>
Reviewed-by: Lukas Auer
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Hi Bin,
On Tue, 2018-09-18 at 16:53 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Sep 18, 2018 at 5:59 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-17 at 12:55 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
Hi Bin,
On Tue, 2018-09-18 at 16:50 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Sep 18, 2018 at 6:01 AM Auer, Lukas
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, 2018-09-17 at 13:02 +0800, Bin Meng wrote:
> > > Hi Lukas,
> > >
> >
On Tue, 2019-04-02 at 15:56 +0800, Andes wrote:
> From: Rick Chen
>
> The Platform-Level Interrupt Controller (PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt. It is required
> for handling IPI.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
On Tue, 2019-04-02 at 15:56 +0800, Andes wrote:
> From: Rick Chen
>
> The platform-Level Machine Timer (PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
>
> This driver implements the riscv_get_time() which
> is required by the generic RISC-V timer driver.
>
>
Hi Rick,
On Tue, 2019-04-02 at 10:12 +0800, Rick Chen wrote:
> Hi Lukas
>
> > Auer, Lukas 於 2019年4月1日 週一 下午5:08寫道：
> >
> > Hi Rick,
> >
> > On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> > > From: Rick Chen
> > >
> > > T
On Wed, 2019-04-03 at 10:43 +0800, Andes wrote:
> From: Rick Chen
>
> It occurs since commit 27cb7300ffda
> ("Ensure device tree DTS is compiled").
>
> More details can refer to
> 89c2b5c02049aea746b1edee0b4e1d8519dec2f4
> ARM: fix arch/arm/dts/Makefile
>
> Signed-off-by: Rick Chen
> Cc:
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> ---
> V3:
> - Fix some mis-alignments.
> - Recovery isa string of CPU1.
>
> arch/riscv/dts/ae350_32.dts | 81
> +
>
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> board/AndesTech/ax25-ae350/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Lukas Auer
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Limit the cache configuration only can be supported in M mode.
> It can not be manipulated in S mode.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> arch/riscv/cpu/ax25/Kconfig | 1 +
> 1
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Add ax25 RISC-V platform-specific Kconfig options, to include
> CPU and timer drivers.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> arch/riscv/cpu/ax25/Kconfig | 6 ++
> 1 file
Hi Rick,
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> The platform-Level Machine Timer (PLMT) block
> holds memory-mapped mtime register associated
> with timer tick.
>
> This driver implements the riscv_get_time() which
> is required by the generic RISC-V timer
Hi Rick,
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> Disable ATCPIT100 SoC timer and replace by PLMT.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> Reviewed-by: Bin Meng
> ---
> configs/ae350_rv32_defconfig | 1 -
> configs/ae350_rv64_defconfig | 1 -
> 2
Hi Rick,
On Mon, 2019-04-01 at 16:24 +0800, Andes wrote:
> From: Rick Chen
>
> The Platform-Level Interrupt Controller (PLIC)
> block holds memory-mapped claim and pending registers
> associated with software interrupt. It is required
> for handling IPI.
>
> Signed-off-by: Rick Chen
> Cc:
> > > > > From: Andreas Schwab
> > > > > Sent: Wednesday, March 6, 2019 4:27 PM
> > > > > To: Anup Patel
> > > > > Cc: Auer, Lukas ;
> > > > > u-boot@lists.denx.de;
> > > > > paul.walms...@sifive.c
On Wed, 2019-03-06 at 10:07 +, Anup Patel wrote:
> > -Original Message-
> > From: Auer, Lukas
> > Sent: Wednesday, March 6, 2019 2:52 PM
> > To: u-boot@lists.denx.de; Anup Patel
> > Cc: paul.walms...@sifive.com; ag...@suse.de; a...@brainfa
On Wed, 2019-03-06 at 04:00 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer
> > Sent: Wednesday, March 6, 2019 4:23 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer Dabbelt ;
> > Alexander Graf ; Lukas Auer
On Tue, 2019-02-19 at 13:46 +0530, Anup Patel wrote:
> On Mon, Feb 18, 2019 at 5:11 PM Auer, Lukas
> wrote:
> > On Mon, 2019-02-18 at 10:01 +, Auer, Lukas wrote:
> > > On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> > > > On Tue, Feb 12, 2019 at
Hi Rick,
On Tue, 2019-03-12 at 09:15 +0800, Rick Chen wrote:
> Hi Lukas
>
> Auer, Lukas 於 2019年3月11日 週一
> 上午2:12寫道：
> > On Sun, 2019-03-10 at 20:24 +0530, Anup Patel wrote:
> > > On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas
> > > wrote:
> > > > Hi
On Sun, 2019-03-10 at 21:01 +0800, Bin Meng wrote:
> On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer
> wrote:
> > On RISC-V, all harts boot independently. To be able to run on a
> > multi-hart system, U-Boot must be extended with the functionality
> > to
> > manage all harts in the system. All harts
Hi Rick,
On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Tuesday, February 12, 2019 6:14 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer
> > >
On Sun, 2019-03-10 at 20:24 +0530, Anup Patel wrote:
> On Sun, Mar 10, 2019 at 7:28 PM Auer, Lukas
> wrote:
> > Hi Rick,
> >
> > On Thu, 2019-03-07 at 17:30 +0800, Rick Chen wrote:
> > > Hi Lukas
> > >
> > > > > From: Lukas Auer [mailt
On Wed, 2019-03-06 at 19:20 -0800, Atish Patra wrote:
> On 3/5/19 2:54 PM, Lukas Auer wrote:
> > Harts on RISC-V boot independently, U-Boot is responsible for
> > managing
> > them. Functions are called on other harts with smp_call_function(),
> > which sends inter-processor interrupts (IPIs) to
On Wed, 2019-03-20 at 05:37 -0700, Palmer Dabbelt wrote:
> On Sun, 17 Mar 2019 11:28:31 PDT (-0700),
> lukas.a...@aisec.fraunhofer.de wrote:
> > This patch series adds SMP support for RISC-V to U-Boot. It allows
> > U-Boot to run on multi-hart systems (hart is the RISC-V terminology
> > for
> >
Hi Bin,
On Tue, 2019-02-12 at 11:03 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Tue, Feb 12, 2019 at 6:14 AM Lukas Auer
> wrote:
> > Harts on RISC-V boot independently and U-Boot is responsible for
> > managing them. Functions are called on other harts with
> > smp_call_function(), which sends
On Tue, 2019-02-12 at 01:48 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 3:44 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer
On Tue, 2019-02-12 at 05:05 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 4:12 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer
On Tue, 2019-02-12 at 01:44 +, Anup Patel wrote:
> > -Original Message-
> > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Tuesday, February 12, 2019 3:44 AM
> > To: u-boot@lists.denx.de
> > Cc: Atish Patra ; Anup Patel
> > ; Bin Meng ; Andreas
> > Schwab ; Palmer
Hi Rick,
On Fri, 2019-02-15 at 14:51 +0800, Rick Chen wrote:
> Hi Lukas
>
> > > From: Lukas Auer [mailto:lukas.a...@aisec.fraunhofer.de]
> > > Sent: Tuesday, February 12, 2019 6:14 AM
> > > To: u-boot@lists.denx.de
> > > Cc: Atish Patra; Anup Patel; Bin Meng; Andreas Schwab; Palmer
> > >
On Mon, 2019-02-18 at 09:10 +0530, Anup Patel wrote:
> On Mon, Feb 18, 2019 at 8:53 AM Rick Chen
> wrote:
> > 於 2019年2月18日 週一 上午11:00寫道：
> > >
> > >
> > > > -----Original Message-
> > > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraun
On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> On Tue, Feb 12, 2019 at 3:44 AM Lukas Auer
> wrote:
> > Harts on RISC-V boot independently and U-Boot is responsible for
> > managing them. Functions are called on other harts with
> > smp_call_function(), which sends inter-processor
On Mon, 2019-02-18 at 10:01 +, Auer, Lukas wrote:
> On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> > On Tue, Feb 12, 2019 at 3:44 AM Lukas Auer
> > wrote:
> > > Harts on RISC-V boot independently and U-Boot is responsible for
> > > managing them. Fu
On Mon, 2019-02-18 at 18:46 +0530, Anup Patel wrote:
> On Mon, Feb 18, 2019 at 5:11 PM Auer, Lukas
> wrote:
> > On Mon, 2019-02-18 at 10:01 +, Auer, Lukas wrote:
> > > On Mon, 2019-02-18 at 10:28 +0530, Anup Patel wrote:
> > > > On Tue, Feb 12, 2019 at
On Wed, 2019-02-13 at 01:31 +, Atish Patra wrote:
> > On Feb 12, 2019, at 4:18 PM, Kevin Hilman
> > wrote:
> >
> > Anup Patel writes:
> >
> > > From: Atish Patra
> > >
> > > The readme guide describes the procedure to build, flash and boot
> > > Linux
> > > using U-Boot on HiFive
On Wed, 2019-02-13 at 10:35 +0100, Andreas Schwab wrote:
> On Feb 13 2019, Anup Patel wrote:
>
> > General practice (atlease what I have seen on few boards), is that
> > board
> > will have unique MAC address printed/labelled for each Ethernet
> > port. We
> > can just set-and-save "ethaddr"
On Mon, 2019-02-11 at 23:16 +0100, Philipp Tomsich wrote:
> On 11.02.2019, at 23:13, Lukas Auer
> wrote:
> > This patch series adds SMP support for RISC-V to U-Boot. It allows
> > U-Boot to run on multi-hart systems and will boot images passed to
> > bootm
> > on all harts. The bootm command is
On Mon, 2019-01-21 at 12:39 +, Auer, Lukas wrote:
> On Sun, 2019-01-20 at 17:07 -0800, Atish Patra wrote:
> > On 1/20/19 12:22 PM, Auer, Lukas wrote:
> > > Hi Anup,
> > >
> > > On Fri, 2019-01-18 at 11:19 +, Anup Patel wrote:
> > > > Fr
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> We will be adding place-holder headers under include/asm/arch
> for RISC-V so this patch updates .gitignore to not consider
> files under arch/riscv/include/asm/arch
>
> Signed-off-by: Anup Patel
> ---
> arch/.gitignore | 1 +
> 1 file
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> Currently, the mrproper make target tries to force remove all
> "arch/*/include/asm/arch" paths assuming they are symlinks but
> this prevents us from adding place-holder headers under the
> arch/riscv/include/asm/arch directory.
>
> To solve
On Sat, 2019-02-09 at 06:31 +, Anup Patel wrote:
> Some of the drivers expect asm/arch/clk.h to be provided by
> arch support code so we add place-holder asm/arch/clk.h for
> RISC-V support.
>
> Signed-off-by: Anup Patel
> ---
> arch/riscv/include/asm/arch/clk.h | 14 ++
> 1
On Sat, 2019-02-02 at 09:06 -0800, Paul Walmsley wrote:
> On Tue, 22 Jan 2019, Auer, Lukas wrote:
>
> > For the same reason, I agree with you that it does not make sense
> > to
> > implement the SBI in U-Boot. OpenSBI is better suited to handle
> > this.
>
On Sat, 2019-02-09 at 06:33 +, Anup Patel wrote:
> From: Atish Patra
>
> The readme guide describes the procedure to build, flash and boot
> Linux
> using U-boot on HiFive Unleashed. It also explains the current state
> of
> U-boot support and future action items.
nit: U-Boot
>
>
On Sat, 2019-02-09 at 06:32 +, Anup Patel wrote:
> Add driver code for the SiFive FU540 PRCI IP block. This IP block
> handles reset and clock control for the SiFive FU540 device and
> implements SoC-level clock tree controls and dividers.
>
> Based on code written by Wesley Terpstra
>
On Sat, 2019-02-09 at 06:33 +, Anup Patel wrote:
> This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V
> because bootm will update initrd location in DTB only if
> CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable
> this option then bootm assumes DTB already has initrd details
On Mon, 2019-02-11 at 04:32 +, Anup Patel wrote:
> > -Original Message-
> > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de]
> > Sent: Monday, February 11, 2019 12:10 AM
> > To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com;
>
Hi Rick,
On Wed, 2019-04-10 at 17:05 +0800, Rick Chen wrote:
> Hi Bin and Lukas
>
> Bin Meng 於 2019年3月21日 週四 下午5:17寫道：
> > Hi Rick,
> >
> > On Thu, Mar 21, 2019 at 5:00 PM Rick Chen wrote:
> > > Bin Meng 於 2019年3月21日 週四 下午4:49寫道：
> > > > Hi Rick,
> > > >
> > > > On Thu, Mar 21, 2019 at 4:27
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