This series adds support for fastboot related to USB.
[PATCH 1/2] fixed max packet size check error for ep_in in high speed condition
[PATCH 2/2] add usb phy control to support fastboot for rk3036
Tested on RK3036 SDK board, it works Okay.
board/evb_rk3036/evb_rk3036/evb_rk3036.c | 27
In current fastboot frame, both full and high speed use 'fs_ep_in',
but fs_ep_in.wMaxPacketSize is configurated 64 bytes as default,
I do not understand why high speed TX max packet size is also set as
64 bytes, so I changed the condition from '!=' to '>' as a workaround.
Signed-off-by: Fr
Used s3c usb otg device driver frame and added USB PHY handle function.
Signed-off-by: Frank Wang <frank.w...@rock-chips.com>
---
board/evb_rk3036/evb_rk3036/evb_rk3036.c | 27 ++
drivers/usb/gadget/Makefile |1 +
drivers/usb/gadget/rk_udc_otg
ewski [mailto:l.majew...@samsung.com]
发送时间: 2015年12月7日 20:58
收件人: Frank Wang
抄送: ma...@denx.de; tr...@konsulko.com; u-boot@lists.denx.de;
benc...@chromium.org; kmix...@chromium.org; s...@chromium.org; cf@rock-chips.
com
主题: Re: [PATCH 1/2] usb: gadget: s3c_udc_otg: fixed max packet size check
for ep_in in
Hi Lukasz,
Friendly Ping!
Could you help to review this series of patches in your free time?
BR.
Frank
On 12/23/2015 08:10 AM, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 09:25:49 AM, Frank Wang wrote:
[PATCH 1/3] Modified the check condition for max packet size of ep_in in
high
'!=' to '>' to fix this issue.
Signed-off-by: Frank Wang <frank.w...@rock-chips.com>
---
drivers/usb/gadget/dwc2_udc_otg.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/dwc2_udc_otg.c
b/drivers/usb/gadget/dwc2_udc_otg.c
index ffe2952..cb20b
When the actual length is less than request length in the last request,
the data transmission should be terminated, because the packet
transmission have alreay finished.
Signed-off-by: Frank Wang <frank.w...@rock-chips.com>
---
drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c |2 +-
1 file c
Used dwc2 usb otg device driver frame and added USB PHY handle function.
Signed-off-by: Frank Wang <frank.w...@rock-chips.com>
---
board/evb_rk3036/evb_rk3036/evb_rk3036.c | 30 +++
drivers/usb/gadget/Makefile |1 +
drivers/usb/gadget/dwc2_udc_otg_
[PATCH 1/3] Modified the check condition for max packet size of ep_in in high
speed
[PATCH 2/3] Fixed the error that the last packet transmission could not be
terminated
[PATCH 3/3] Add usb phy control to support fastboot for rk3036
Tested on RK3036 SDK board, it works Okay.
Hi Jagan,
All ack related will be fixed in the next patches.
BR,
Frank
On 2020/4/28 17:27, Jagan Teki wrote:
On Tue, Apr 28, 2020 at 12:01 PM Frank Wang wrote:
This implements the Type-C PHY driver for Rockchip platform
with Cadence IP block.
Signed-off-by: Frank Wang
Signed-off
This implements the Type-C PHY driver for Rockchip platform
with Cadence IP block.
Signed-off-by: Frank Wang
Signed-off-by: William Wu
---
drivers/phy/Kconfig| 6 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-typec.c | 534
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang
---
drivers/usb/common/common.c | 25 ++
drivers/usb/dwc3/core.c | 65 +++--
drivers
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
---
drivers/usb/host/Kconfig | 9 --
drivers/usb/host/Makefile| 1 -
drivers/usb/host/xhci-rockchip.c | 196
This series add quirks for DWC3 and add Rockchip RK3399 USB3.0 host support.
Frank Wang (8):
usb: dwc3: add dis_enblslpm_quirk
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: amend UTMI/UTMIW phy interface setup
usb: dwc3: add make compatible for rockchip platform
phy: rockchip
We have changed to use dwc3 generic driver for Rockchip SoCs
so let amend dts to fix it and keep in line with Linux Kernel.
Signed-off-by: Frank Wang
---
arch/arm/dts/rk3399-evb.dts | 28 ---
arch/arm/dts/rk3399-puma.dtsi | 35 +++---
arch/arm/dts/rk3399-u
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang
---
drivers/usb/dwc3/core.c | 6 ++
d
hip Kernel.
Signed-off-by: Frank Wang
---
drivers/usb/dwc3/core.c | 6 ++
drivers/usb/dwc3/core.h | 2 ++
include/dwc3-uboot.h| 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index a80e7d54aa..3c81a07dad 100644
--- a/drivers/usb/dwc3/co
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
---
drivers/usb/dwc3/dwc3-generic.c | 33
Update evb-rk3399 default config to support USB3.0 host.
Signed-off-by: Frank Wang
---
configs/evb-rk3399_defconfig | 5 +
1 file changed, 5 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 3f74be3b3c..d68fede479 100644
--- a/configs/evb
Hi Jagan,
On 2020/4/28 17:17, Jagan Teki wrote:
On Tue, Apr 28, 2020 at 12:04 PM Frank Wang wrote:
We have changed to use dwc3 generic driver for Rockchip SoCs
so let amend dts to fix it and keep in line with Linux Kernel.
Signed-off-by: Frank Wang
---
arch/arm/dts/rk3399-evb.dts | 28
Hi Marek,
On 2020/4/28 17:21, Marek Vasut wrote:
On 4/28/20 11:05 AM, Frank Wang wrote:
Hi Marek,
On 2020/4/28 16:27, Marek Vasut wrote:
On 4/28/20 8:27 AM, Frank Wang wrote:
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2
Hi Marek,
On 2020/4/28 16:27, Marek Vasut wrote:
On 4/28/20 8:27 AM, Frank Wang wrote:
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip
This implements the Type-C PHY driver for Rockchip platform
with Cadence IP block.
Signed-off-by: Frank Wang
Signed-off-by: William Wu
---
drivers/phy/Kconfig| 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-typec.c | 523
We have changed to use dwc3 generic driver for Rockchip SoCs,
so let amend dts to fix it and keep in line with Linux Kernel.
Signed-off-by: Frank Wang
---
arch/arm/dts/rk3399-evb.dts | 16 +++
arch/arm/dts/rk3399.dtsi| 54 ++---
2 files changed, 49
Update evb-rk3399 default config to enable USB3.0 Host.
Signed-off-by: Frank Wang
---
configs/evb-rk3399_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index a342bfd16d..0234995175 100644
--- a/configs/evb
Update evb-rk3399 default config to enable Type-C PHY.
Signed-off-by: Frank Wang
---
configs/evb-rk3399_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 7f14e18b1b..a342bfd16d 100644
--- a/configs/evb
hip Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
drivers/usb/dwc3/core.c | 6 ++
drivers/usb/dwc3/core.h | 2 ++
include/dwc3-uboot.h| 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index a80e7d54aa..3c81a07dad 100644
---
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
---
drivers/usb/host/Kconfig | 9 --
drivers/usb/host/Makefile| 1 -
drivers/usb/host/xhci-rockchip.c | 196
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
drivers/usb/common/common.c | 25 ++
drivers/usb/dwc3/core.c | 65
] and [PATCH 3/8].
Frank Wang (9):
usb: dwc3: add dis_enblslpm_quirk
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: amend UTMI/UTMIW phy interface setup
usb: dwc3: add make compatible for rockchip platform
phy: rockchip: add a new driver for type-c phy
driver: usb: drop legacy
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
---
drivers/usb/dwc3/dwc3-generic.c | 33
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
drivers/usb/d
Hi Marek,
On 2020/5/12 15:26, Marek Vasut wrote:
On 5/12/20 3:08 AM, Frank Wang wrote:
Hi Marek,
On 2020/5/11 17:48, Marek Vasut wrote:
On 5/11/20 9:57 AM, Frank Wang wrote:
[...]
@@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev)
if (ret)
return ret
Hi Marek,
On 2020/5/11 17:48, Marek Vasut wrote:
On 5/11/20 9:57 AM, Frank Wang wrote:
[...]
@@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev)
if (ret)
return ret;
+ if (glue->resets.count < 1) {
This condition is only true if count == 0 ?
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
configs/evb-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 7f14e18b1b..6cfb4e5dac 100644
From: Jagan Teki
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
From: Jagan Teki
Enable USB3.0 Host support for ROC-RK3399-PC boards.
Tested USB3.0 SSD on Type C1 port on board.
=> usb start
starting USB...
Bus usb@fe38: USB EHCI 1.00
Bus usb@fe3c: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the
From: Jagan Teki
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki
---
drivers/Makefile
From: Jagan Teki
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index
] and [PATCH 3/8].
[1]
https://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-ja...@amarulasolutions.com
BR,
Frank
Frank Wang (7):
usb: dwc3: add dis_enblslpm_quirk
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: amend UTMI/UTMIW phy interface setup
usb: dwc3: add make
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
Reviewed-by:
From: Jagan Teki
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted,
- Once we support the PHY subsystem to get the PHY
even though
From: Jagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = < SCLK_UPHY0_TCPDCORE>;
assigned-clocks = <
From: Jagan Teki
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
---
drivers/phy/rockchip/Kconfig | 7
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/usb/common/common.c | 25 ++
drivers/usb/dwc3/core.c
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb-u
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
---
drivers/usb/dwc3
From: Jagan Teki
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
drivers/usb/host/Kconfig | 9 --
drivers/usb/host/Makefile| 1 -
drivers/usb/host/xhci
From: Jagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use this quirk, the controller implements a
hip Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
drivers/usb/dwc3/core.c | 6 ++
drivers/usb/dwc3/core.h | 2 ++
include/dwc3-uboot.h| 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/d
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
---
Changes for v3:
- none
drivers/usb/host/Kconfig | 9 --
drivers/usb/host/Makefile| 1 -
drivers/usb/host/xhci
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang
---
Changes for v3:
- select more config to support USB3.0 host.
configs/evb-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
Changes for v3:
- none
drivers/usb/common/common.c | 25 ++
drivers/usb/dwc3/core.c
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
---
Changes for v3:
- drop dtsi changes to keep the same with Linux Kernel.
- amend rk3399-evb.dts to support usb3.0 host.
arch/arm/dts/rk3399-evb.dts | 13
hip Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
Changes for v3:
- none
drivers/usb/dwc3/core.c | 6 ++
drivers/usb/dwc3/core.h | 2 ++
include/dwc3-uboot.h| 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
---
Changes for v3:
- none
drivers/usb/dwc3/dwc3
].
[1]
https://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-ja...@amarulasolutions.com
BR,
Frank
Frank Wang (7):
usb: dwc3: add dis_enblslpm_quirk
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: amend UTMI/UTMIW phy interface setup
usb: dwc3: add make compatible
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
Changes for
Hi Jagan,
On 2020/5/1 14:53, Jagan Teki wrote:
On Thu, Apr 30, 2020 at 7:47 AM Frank Wang wrote:
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_
Hi Jagan,
On 2020/5/1 15:17, Jagan Teki wrote:
On Thu, Apr 30, 2020 at 7:47 AM Frank Wang wrote:
This implements the Type-C PHY driver for Rockchip platform
with Cadence IP block.
Signed-off-by: Frank Wang
Signed-off-by: William Wu
---
drivers/phy/Kconfig| 7
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
configs/evb-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index 7f14e18b1b..6cfb4e5dac 100644
From: Jagan Teki
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
---
drivers/usb/dwc3
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/dts/rk3399-evb-u
From: Jagan Teki
Enable USB3.0 Host support for ROC-RK3399-PC boards.
Tested USB3.0 SSD on Type C1 port on board.
=> usb start
starting USB...
Bus usb@fe38: USB EHCI 1.00
Bus usb@fe3c: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
---
drivers/usb/host/Kconfig | 9 --
drivers/usb/host/Makefile| 1 -
drivers/usb/host/xhci
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/usb/common/common.c | 25 ++
drivers/usb/dwc3/core.c
From: Jagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use this quirk, the controller implements a
From: Jagan Teki
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
is not part of the root structure.
This will be reverted,
- Once we support the PHY subsystem to get the PHY
even though
hip Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
drivers/usb/dwc3/core.c | 6 ++
drivers/usb/dwc3/core.h | 2 ++
include/dwc3-uboot.h| 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 20be617fd4..3cb66515a2 100644
---
From: Jagan Teki
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
---
drivers/phy/rockchip/Kconfig | 7
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
---
drivers/usb/d
From: Jagan Teki
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki
---
drivers/Makefile
From: Jagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = < SCLK_UPHY0_TCPDCORE>;
assigned-clocks = <
From: Jagan Teki
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
From: Jagan Teki
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/clk_rk3399.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index
commit for [PATCH 7/8].
- Split RK3399 default config for [PATCH 8/8].
- Add 'Reviewed-by' tag for [PATCH 1/8], [PATCH 2/8] and [PATCH 3/8].
[1]
https://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-ja...@amarulasolutions.com
BR,
Frank
Frank Wang (7):
usb: dwc3: add
Hi Peter,
On 2020/5/7 16:17, Peter Robinson wrote:
On Thu, May 7, 2020 at 9:13 AM Frank Wang wrote:
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
---
Changes for v3:
- drop dtsi changes to keep the same
Hi Marek & Jagan,
On 2020/5/9 2:52, Jagan Teki wrote:
On Sat, May 9, 2020 at 12:03 AM Marek Vasut wrote:
On 5/8/20 7:46 PM, Jagan Teki wrote:
On Fri, May 8, 2020 at 11:13 PM Marek Vasut wrote:
On 5/8/20 7:24 PM, Jagan Teki wrote:
On Thu, May 7, 2020 at 1:43 PM Frank Wang wrote:
Up
From: Jagan Teki
Enable/Disable the USB2PHY clk for rk3399.
CLK is clear in enable and set in disable functionality.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk_rk3399.c | 12
1 file changed, 12 insertions(+)
diff --git
From: Jagan Teki
Enable USB3.0 Host support for ROC-RK3399-PC boards.
Tested USB3.0 SSD on Type C1 port on board.
=> usb start
starting USB...
Bus usb@fe38: USB EHCI 1.00
Bus usb@fe3c: USB EHCI 1.00
Bus dwc3: usb maximum-speed not found
Register 2000140 NbrPorts 2
Starting the
RK3399 Type-C PHY is required that must hold whole USB3.0 OTG controller
in resetting to hold pipe power state in P2 before initializing the PHY.
This commit fixed it and added device compatible for rockchip platform.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
We have changed to use dwc3 generic driver for usb3.0 host, so the
legacy Rockchip's xHCI driver is not needed, and drop it.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/usb/host/Kconfig | 9 --
drivers/usb/host/Makefile| 1
Update evb-rk3399 default config to support USB3.0 Host.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
---
configs/evb-rk3399_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig
index
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.
Signed-off-by: Frank Wang
Reviewed-by: Jagan Teki
Reviewed-by: Kever Yang
---
arch/arm/dts/rk3399-evb-u-boot.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch
Hi Jagan, Kever,
On 2020/5/15 10:40, Kever Yang wrote:
Hi Jagan, Frank,
On 2020/5/13 下午3:15, Frank Wang wrote:
From: Jagan Teki
Yes, This is changing the actual device tree u2phy
structure but the problem with the current Generic
PHY subsystem is unable to find PHY if the PHY node
From: Jagan Teki
Add USB TYPEC PHY driver for rockchip platform.
Referenced from Linux TypeC PHY driver, currently
supporting usb3-port and dp-port need to add it
in the future.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/phy/rockchip/Kconfig
hip Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki
---
drivers/usb/dwc3/core.c | 6 ++
drivers/usb/dwc3/core.h | 2 ++
include/dwc3-uboot.h| 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/d
From: Jagan Teki
Add Rockchip USB2PHY driver with initial support.
This will help to use it for EHCI controller in host
mode, and USB 3.0 controller in otg mode.
More functionality like charge, vbus detection will
add it in future changes.
Signed-off-by: Jagan Teki
Signed-off-by: Frank Wang
://patchwork.ozlabs.org/project/uboot/cover/20200506075025.1677-1-ja...@amarulasolutions.com
BR,
Frank
Frank Wang (8):
arm: mach-rockchip: bind sub-nodes for rk3399_syscon
usb: dwc3: add dis_enblslpm_quirk
usb: dwc3: add dis_u2_freeclk_exists_quirk
usb: dwc3: amend UTMI/UTMIW phy interface setup
usb
From: Jagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi
have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks
which are usually required for Linux and don't require to
handle them in U-Boot.
assigned-clocks = < SCLK_UPHY0_TCPDCORE>;
assigned-clocks = <
From: Jagan Teki
Enable/Disable TCPHY clock for rk3399 platform.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/clk/rockchip/clk_rk3399.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk")
in Linux Kernel.
Signed-off-by: Frank Wang
Reviewed-by: Kever Yang
Reviewed-by:
From: Jagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check
during HS transmit. Refer the dwc3 databook, we can use it for
some special platforms if the linestate not reflect the expected
line state(J) during transmission.
When use this quirk, the controller implements a
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init
that is convenient for both DM_USB and u-boot traditional process.
Signed-off-by: Frank Wang
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
drivers/usb/common/common.c | 25 ++
drivers/usb/dwc3/core.c
From: Jagan Teki
By default when core sees any transaction error (CRC or overflow) it
replies with terminating retry ACK (Retry=1 and Nump == 0).
Enabling this Auto Retry feature in controller will make the core send
a non-terminanting ACK upon such transaction errors. That is, ACK TP
with
There are some sub-nodes under the grf DT, so add bind callback
function in rk3399 syscon driver to scan them recursively.
Signed-off-by: Frank Wang
---
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3399
Hi Icenowy Zheng,
In my view, it is better to implement this mechanism in phy-uclass which
resemble Linux Kernel have implemented that can avoid do duplication of
work in each SoC's PHY driver.
BR.
Frank
On 2021/4/6 23:10, Icenowy Zheng wrote:
The OHCI and EHCI controllers are both bound
Hi,
On 2021/4/7 14:43, Icenowy Zheng wrote:
于 2021年4月7日 GMT+08:00 下午2:42:34, Frank Wang 写到:
Hi Icenowy Zheng,
In my view, it is better to implement this mechanism in phy-uclass
which
resemble Linux Kernel have implemented that can avoid do duplication of
work in each SoC's PHY driver
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