Marek, Wolfgang,
On Fri, Aug 10, 2012 at 9:56 PM, Ilya Yanok
ilya.ya...@cogentembedded.comwrote:
Dear Marek, Wolfgang,
On Thu, Aug 9, 2012 at 11:23 PM, Wolfgang Denk w...@denx.de wrote:
I hate to say it ... but given that this will cause duplication of
code, I'm
somehow inclined
Argh, sorry. could = could not.
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are not supported. The only ported driver
is for TI AM33xx, but others should be easy to port too.
Tested it on AM335x EVM and BeagleBone with CDC Ethernet gadget.
Ilya Yanok (5):
linux/usb/ch9.h: update with the version from Linux tree
musb-new: port of Linux musb gadget driver
musb-new: dsps
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
drivers/usb/gadget/config.c |1 -
drivers/usb/gadget/epautoconf.c |1 -
drivers/usb/gadget/ether.c |1 -
drivers/usb/gadget/s3c_udc_otg.c |1 -
drivers/usb/gadget/usbstring.c |1 -
include/linux/usb/ch9
Enable musb gadget in Ethernet mode on port 0.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
include/configs/am335x_evm.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index c827ebf..e0f0656
AM33xx has support for dual port MUSB OTG controller. This patch
adds initialization for the controller using new MUSB gadget
driver and ether gadget.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
arch/arm/cpu/armv7/am33xx/board.c | 81 ++-
arch
Backend driver for MUSB OTG controllers found on TI AM33xx and
TI81xx SoCs (tested with AM33xx only).
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
arch/arm/include/asm/omap_musb.h | 25 ++
drivers/usb/musb-new/Makefile|1 +
drivers/usb/musb-new/musb_dsps.c | 769
on other code so SPL size
is increased significantly. No effort was done to decouple network
code and environment so far.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v3:
- use BOOTP in SPL regardless of CONFIG_CMD_DHCP
- add support for setting different VCI in SPL
Hi Tom,
On Tue, Aug 7, 2012 at 1:11 AM, Ilya Yanok ilya.ya...@cogentembedded.comwrote:
Yes. What I meant was that not all of the stuff that is guarded today
is garbage collected so the resulting image is larger than it must be.
Yep. And that's actually goes beyond the subject
Hi guys,
Is it a good place to post patman patches? Or should I go to some chromium
list?
Regards, Ilya.
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Hi Stefano,
On Tue, Aug 7, 2012 at 12:57 PM, Stefano Babic sba...@denx.de wrote:
On 07/08/2012 10:54, Ilya Yanok wrote:
Hi guys,
Hi Ilya,
Is it a good place to post patman patches? Or should I go to some
chromium
list?
IMHO here is the best place, patman is integrated in u-boot
Changes may end in '---' line or Signoff line (generated by
git format-patch) in case of Series-changes: lines being
the last ones in commit message. So detect it properly.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
tools/patman/patchstream.py |6 ++
1 file changed, 6
and disables additional
signoff and changelog processing.
Ilya Yanok (4):
patman: fix end of changes detection
patman: don't pick changes while processing patches
patman: don't mess with changelog
patman: don't mess with signoffs
tools/patman/patchstream.py | 22
We already got all changes from git log output and the comment
to the ProcessLine function clearly states that 'patch' mode
is not for scanning tags.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
tools/patman/patchstream.py |3 ++-
1 file changed, 2 insertions(+), 1 deletion
Don't try to sort and uniq changelog entries as this breaks
multiline entries. It will be better to add some real multi-line
support but for now just preserve the entries as is.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
tools/patman/series.py |5 ++---
1 file changed, 2
line between signoffs.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
tools/patman/patchstream.py | 13 ++---
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/tools/patman/patchstream.py b/tools/patman/patchstream.py
index 3de32d5..0503bac 100644
--- a/tools
Beaglebone uses SMSC PHY which works incorrectly with generic PHY
driver so enable SMSC PHY driver to fix networking problems on
Beaglebone.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
include/configs/am335x_evm.h |1 +
1 file changed, 1 insertion(+)
diff --git a/include
Hi Tom,
On Mon, Aug 6, 2012 at 2:35 AM, Tom Rini tr...@ti.com wrote:
On Sun, Aug 5, 2012 at 2:21 PM, Ilya Yanok
ilya.ya...@cogentembedded.com wrote:
We need to initialize timer properly, otherwise all delays
inside SPL will be wrong.
Signed-off-by: Ilya Yanok ilya.ya
Hi Tom,
On Mon, Aug 6, 2012 at 2:36 AM, Tom Rini tr...@ti.com wrote:
On Sun, Aug 5, 2012 at 2:21 PM, Ilya Yanok
ilya.ya...@cogentembedded.com wrote:
__u_boot_cmd* symbols are not used in SPL so there is no need
to tell the linker that they are undefined. With these symbols
marked
On Mon, Aug 6, 2012 at 7:30 PM, Tom Rini tr...@ti.com wrote:
On 08/06/2012 08:10 AM, Ilya Yanok wrote:
Hi Tom,
On Mon, Aug 6, 2012 at 2:36 AM, Tom Rini tr...@ti.com
mailto:tr...@ti.com wrote:
On Sun, Aug 5, 2012 at 2:21 PM, Ilya Yanok
ilya.ya...@cogentembedded.com
Hi Tom,
On Mon, Aug 6, 2012 at 9:10 PM, Tom Rini tr...@ti.com wrote:
OK, installed and it's still larger with this change than without and
it's not garbage collecting and dropping commands if I un-guard the
nandecc command for example. Tested with omap3_beagle.
Did some testing as well.
Hi Tom,
On Tue, Aug 7, 2012 at 12:52 AM, Tom Rini tr...@ti.com wrote:
By comparing of two images I've found that the difference comes from
ro-strings (two help strings in U_BOOT_CMD, string in printf, sw
hw).
It looks like the linker doesn't collect ro-strings referenced from
collected
var inside macro
- rename spl_eth.c to spl_net.c
- set ethact variable if device name is passed
- used strlen instead of sizeof
Ilya Yanok (5):
net/bootp: add VCI support for BOOTP also
spl: don't mark __u_boot_cmd* as undefined
OMAP: spl: call timer_inti() from SPL
OMAP: networking
Vendor Class Identifier option is common to BOOTP and DHCP and
can be useful without PXE. So send VCI in both BOOTP and DHCP
requests if CONFIG_BOOTP_VCI_STRING is defined.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v4:
- moved vci_strlen var inside macro
- used
We need to initialize timer properly, otherwise all delays
inside SPL will be wrong.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
arch/arm/cpu/armv7/omap-common/spl.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv7/omap-common/spl.c
b/arch/arm/cpu
__u_boot_cmd* symbols are not used in SPL so there is no need
to tell the linker that they are undefined. With these symbols
marked as undefined linker fails to garbage collect some unused
functions and even fails to build the resulting image.
Signed-off-by: Ilya Yanok ilya.ya
on other code so SPL size
is increased significantly. No effort was done to decouple network
code and environment so far.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v3:
- add support for setting different VCI in SPL
- use BOOTP in SPL regardless of CONFIG_CMD_DHCP
This patch adds support for networking in SPL on TI AM335x based
boards. Vendor Class Identifier used by SPL during BOOTP is
AM335x U-Boot SPL.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v3:
- set Vendor Class Identifier for SPL
Changes in v4:
- SPL_BOARD_INIT
Hi Joe,
On Wed, Jul 25, 2012 at 3:29 AM, Joe Hershberger
joe.hershber...@gmail.comwrote:
+#define put_vci(e, str)\
+ do {\
+ *e++ = 60; \
Please keep the comment on the magic
From: Chandan Nath chandan.n...@ti.com
This patch adds pin mux settings for CPSW switch found on
TI AM335X based boards (MII and RGMII modes).
Signed-off-by: Chandan Nath chandan.n...@ti.com
[Ilya: split pinmux into separate patch]
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
Read the on-board EEPROM during startup to detect the version
of the board we are running on (as for now only BeagleBone vs
EVM detection is supported).
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
board/ti/am335x/evm.c | 72 +++--
1
: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v2:
- fix timeout handling
- use internal RAM for descriptors
Changes in v3:
- change calls to miiphy_{speed,duplex
by Mugunthan V N)
- use BOOTP in SPL regardless of CONFIG_CMD_DHCP
Chandan Nath (3):
am33xx: CPSW init and definitions
am33xx: pin mux defintions for CPSW switch
am335x_evm: CPSW support
Cyril Chemparathy (1):
cpsw: add driver for cpsw ethernet device
Ilya Yanok (4):
am335x_evm: read
on other code so SPL size
is increased significantly. No effort was done to decouple network
code and environment so far.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v3:
- add support for setting different VCI in SPL
- use BOOTP in SPL regardless of CONFIG_CMD_DHCP
arch
From: Chandan Nath chandan.n...@ti.com
This patch adds board-specific initialization for CPSW on
TI AM335X based boards. Tested on BeagleBone.
Signed-off-by: Chandan Nath chandan.n...@ti.com
[Ilya: split board-specific part into separate patch]
Signed-off-by: Ilya Yanok ilya.ya
Vendor Class Identifier option is common to BOOTP and DHCP and
can be useful without PXE. So send VCI in both BOOTP and DHCP
requests if CONFIG_BOOTP_VCI_STRING is defined.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
net/bootp.c | 20 +++-
1 file changed, 15
This patch adds support for networking in SPL on TI AM335x based
boards. Vendor Class Identifier used by SPL during BOOTP is
AM335x U-Boot SPL.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v3:
- set Vendor Class Identifier for SPL
board/ti/am335x/evm.c| 12
From: Chandan Nath chandan.n...@ti.com
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.
Signed-off-by: Chandan Nath chandan.n...@ti.com
[Ilya: split init out of original patch]
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes in v3:
- fix
Hi,
On Fri, Jul 20, 2012 at 10:59 PM, McClintock Matthew-B29882
b29...@freescale.com wrote:
On Fri, Jul 20, 2012 at 1:56 PM, Marek Vasut ma...@denx.de wrote:
Dear McClintock Matthew-B29882,
[...]
I think this merge is causing issues. Resetting to the previous merge
(ad8439d Merge
Dear Marek,
On Mon, Jul 16, 2012 at 2:47 PM, Marek Vasut ma...@denx.de wrote:
ok, I finally managed to fix it. Will post the patches in a few seconds.
So the link I sent you was true afterall ? :)
Not exactly ;) Actually I've already switched to another task but when I
went to bed one
Dear Marek,
ok, I finally managed to fix it. Will post the patches in a few seconds.
Regards, Ilya.
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Move or_asynclistaddr programming to ehci_submit_async()
function to make sure queue head is properly programmed
before every transfer. This solves the problem with changing
qh address.
Also remove unneeded qh_list-qh_link reprogramming at the
end of transfer.
Signed-off-by: Ilya Yanok ilya.ya
buffer fixes to separate patch,
we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN
for qh_list, qh and qtd structures to make sure they are proper aligned
for both controller and cache operations.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from V2:
- qh
Dear Marek,
On Sun, Jul 15, 2012 at 12:14 PM, Marek Vasut ma...@denx.de wrote:
The patch is good in the sense it does fix the real problem. But I wonder
if it's a good idea to expose lower layer details (like size/number of
buffers per EHCI TD) to upper layer driver? I know EHCI is most
Dear Marek,
On Sun, Jul 15, 2012 at 12:07 PM, Marek Vasut ma...@denx.de wrote:
@@ -207,8 +210,8 @@ static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void
*buffer,
int length, struct devrequest *req)
{
- static
was introduced by these patches.
Ilya Yanok (5):
ehci-hcd: fix external buffer cache handling
usb: pass cache-aligned buffer to usb_get_descriptor()
usb: check return value of submit_{control,bulk}_msg
ehci-hcd: change debug() to printf() in case of errors
smsc95xx: align buffers to cache
From: Tom Rini tr...@ti.com
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut ma...@denx.de
Signed-off-by: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
buffer fixes to separate patch,
we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN
for qh_list, qh and qtd structures to make sure they are proper aligned
for both controller and cache operations.
For some unclear reason qh structure should remain static.
Signed-off-by: Ilya
specification.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from Marek's version:
- added #include linux/compiler.h (needed for __aligned())
- added macros with additional argument to allow explicit alignment
specification
include/common.h | 21 ++---
1
about that.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
drivers/usb/host/ehci-hcd.c | 23 ++-
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 59039f4..a6cd5e3 100644
--- a/drivers/usb
usb_get_descriptor passes it's buffer argument directly to
usb_control_msg() so it has to be properly aligned/padded.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
common/usb.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/usb.c b/common/usb.c
Return values of submit_{control,bulk}_msg() functions
should be checked to detect possible error.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
common/usb.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/common/usb.c b/common/usb.c
index 46f4741
Printing message could be useful if something goes really wrong.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
drivers/usb/host/ehci-hcd.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index
Align buffers passed to the USB code to cache line size so
they can be DMAed safely.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
drivers/usb/eth/smsc95xx.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb
Dear Marek,
On Sun, Jul 15, 2012 at 1:51 PM, Marek Vasut ma...@denx.de wrote:
Thanks! I'm marking this important in my mailbox to avoid missing that we
need
to fix this. Ilya, can you check the driver model papers and see if we can
somehow integrate this into that?
I will try to.
Dear Marek,
On Sun, Jul 15, 2012 at 6:59 PM, Marek Vasut ma...@denx.de wrote:
index 04300be..59039f4 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -34,7 +34,10 @@ struct ehci_hccr *hccr;/* R/O registers, not need
for
volatile */ volatile struct
Hi,
On Sun, Jul 8, 2012 at 7:08 AM, Marek Vasut ma...@denx.de wrote:
@@ -207,8 +210,8 @@ static int
ehci_submit_async(struct usb_device *dev, unsigned long pipe, void
*buffer,
int length, struct devrequest *req)
{
- static struct QH qh
Dear Marek,
On Tue, Jul 10, 2012 at 5:55 AM, Marek Vasut ma...@denx.de wrote:
+ invalidate_dcache_range((uint32_t)buffer,
+ ALIGN_END_ADDR(u8, buffer, length));
We shouldn't use ALIGN_END_ADDR here. This can lead to strange results on
systems with
Hi,
The patch is good in the sense it does fix the real problem. But I wonder
if it's a good idea to expose lower layer details (like size/number of
buffers per EHCI TD) to upper layer driver? I know EHCI is most common USB
HCD but we have drivers for a bunch of others... How about them?
Hi guys,
On Tue, Jul 10, 2012 at 12:37 PM, Tom Rini tr...@ti.com wrote:
What do we want to do about the USB issue (on ARM platforms, with
EHCI,
with 32byte alignment requirements, if dcache isn't build-time
disabled, USB is unusable, a change from previous releases), for this
Hi Marek,
On Tue, Jul 10, 2012 at 6:17 AM, Marek Vasut marek.va...@gmail.com wrote:
Well, of course we need proper alignment for cache stuff (well, actually
we
can skip this alignment thing for the buffer we will flush as long as all
buffers we are going to invalidate are properly
On Tue, Jul 10, 2012 at 1:34 PM, Marek Vasut marek.va...@gmail.com wrote:
aligned to
16 bytes for arch with 16 byte cachelines.
Yes, and this is exactly what we need.
ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1); this stuff maybe? It'll be
It isn't, EHCI needs it aligned on 32 byte
Dear Marek,
On Mon, Jul 9, 2012 at 4:45 AM, Marek Vasut marek.va...@gmail.com wrote:
But in practice it works without any alignment... ok, you made me read
the
spec ;)
page 55: For the page 0 current offset interpretation, this field is the
byte offset into the current page
See the
Hi Marek,
On Sun, Jul 8, 2012 at 7:08 AM, Marek Vasut ma...@denx.de wrote:
- /* Invalidate the memory area occupied by buffer */
- invalidate_dcache_range(((uint32_t)buffer ~31),
- ((uint32_t)buffer ~31) + roundup(length, 32));
+ /*
+* Invalidate
Hi Marek,
On Sun, Jul 8, 2012 at 7:08 AM, Marek Vasut ma...@denx.de wrote:
[...]
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 04300be..5199560 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -34,7 +34,10 @@ struct ehci_hccr
Hi Marek,
On Sun, Jul 8, 2012 at 7:08 AM, Marek Vasut ma...@denx.de wrote:
This is the out-of-function-scope counterpart of
ALLOC_CACHE_ALIGN_BUFFER.
+#define DEFINE_CACHE_ALIGN_BUFFER(type, name, size)\
+ static char __##name[roundup(size * sizeof(type),
Align buffers passed to the USB code to cache line size so
they can be DMAed safely.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Depens on Marek's patch [1] for DEFINE_CACHE_ALIGN_BUFFER.
[1] http://patchwork.ozlabs.org/patch/169619/
drivers/usb/eth/smsc95xx.c | 13
Dear Marek,
On Sun, Jul 8, 2012 at 10:59 PM, Marek Vasut marek.va...@gmail.com wrote:
btw. this will fail with cache line 32 .
Hm.. I have to admit I'm not very much into USB specs and I don't have any
non-ARMv7 system now to do some testing...
But it used to work without any alignment,
Dear Marek,
On Mon, Jul 9, 2012 at 1:31 AM, Marek Vasut marek.va...@gmail.com wrote:
non-ARMv7 system now to do some testing...
But it used to work without any alignment, right? (with disabled dcache,
of
course)
That makes me think that data buffers don't need any alignment (from USB
Hi Tom,
On Thu, Jul 5, 2012 at 9:15 PM, Tom Rini tr...@ti.com wrote:
On Wed, Jul 04, 2012 at 05:03:59PM +0400, Ilya Yanok wrote:
`
From: Tom Rini tr...@ti.com
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum
Hi Marek,
On Thu, Jul 5, 2012 at 12:24 AM, Marek Vasut ma...@denx.de wrote:
-static struct QH qh_list __attribute__((aligned(32)));
+static char __qh_list[ALIGN(sizeof(struct QH), USB_DMA_MINALIGN)]
+ __attribute__((aligned(USB_DMA_MINALIGN)));
+static struct QH
Hi Marek,
On Thu, Jul 5, 2012 at 11:58 PM, Marek Vasut ma...@denx.de wrote:
Yep. I even thought about this but decided not to do... can't recall why.
Now I think it's really a good idea.
Maybe we should create DEFINE_ALIGNED_VARIABLE as a common.h macro?
Like what's in common.h --
. If we got unaligned buffer from the
upper layer -- that's definetely a bug so it's good to buzz
about it. But we have to align the buffer length -- upper layers
should take care to reserve enough space.
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from Tom's V4:
- Internal
Hi All,
04.07.2012 04:14, Marek Vasut wrote:
Ilya, thank you for saving my back ;-)
And thank you for investing your time into this.
You are welcome ;)
Just posted the patch. No dealing with unaligned buffers from upper
layers for now but at least fatload with aligned address works fine.
Hi Tom,
02.07.2012 23:06, Tom Rini wrote:
On Mon, Jul 02, 2012 at 08:41:56PM +0200, Wolfgang Denk wrote:
Hello all,
I would like to get out -rc1 ASAP. If you have any patches queued
that should make it into the upcoming release, then plase send your
pull requezts as soon as possible.
Hi,
On Sun, Jul 1, 2012 at 9:33 PM, Harman Sohanpal harmansohan...@gmail.comwrote:
Thanks for your review.
But I believe you are talking of version 3 of the patches.
Kindly have a look at the version 4 I have sent.
Yes, my bad. I've seen your fourth version just after sending my comment.
Dear Marek,
04.07.2012 21:57, Marek Vasut wrote:
OK, thanks. I'll do some testing and wait for Marek to ack :) Then I
think it should go via the USB tree since it's all under drivers/usb/
now.
Was I CCed on those? I can't find them in my mailbox :-(
There is actually only one updated
Dear Marek,
30.06.2012 23:27, Marek Vasut wrote:
do {
/* Invalidate dcache */
invalidate_dcache_range((uint32_t)qh_list,
(uint32_t)qh_list + sizeof(struct QH));
invalidate_dcache_range((uint32_t)qh,
Dear Marek,
30.06.2012 23:28, Marek Vasut wrote:
Not exactly. It never worked (at least on my systems) with D-Cache
enabled. But at least we had a choice of run-time disabled dcache. With
the recent changes we have to disable cache support at compile time.
I see what you're after. But do you
Hi Tom,
04.07.2012 00:43, Tom Rini wrote:
On 07/03/2012 01:13 PM, Ilya Yanok wrote:
Dear Marek,
30.06.2012 23:28, Marek Vasut wrote:
Not exactly. It never worked (at least on my systems) with D-Cache
enabled. But at least we had a choice of run-time disabled dcache. With
the recent changes
Dear Marek,
28.06.2012 19:41, Marek Vasut wrote:
Surely. (but that probably was an AM3517 with 64 byte cache line)
m28 is imx28 with 32byte cacheline
You are lucky then. But some systems have bigger cacheline, right?
patch) and loading from ext2 and vfat (worked).
This is just a
Dear Marek,
29.06.2012 04:54, Marek Vasut wrote:
To clarify for everyone, the first part of this series fixes some
alignment issues for things that were not starting address aligned.
There still exist end-address alignment issues within ehci-hcd. The
time I have for this problem right now
Dear Marek,
28.06.2012 02:48, Marek Vasut wrote:
Sorry for missing this discussion. I think compile-time disabling of the
cache is too brutal.
ehci-hcd cache handling is broken anyway: doing unaligned
flushes/invalidates is a bug, and we know for sure that upper layers
don't care about
Dear Marek,
28.06.2012 18:37, Marek Vasut wrote:
Really? Don't forget my old patch [1] then ;)
Still I think we should rip off all the cache stuff from ehci-hcd until
all patches for upper layers are included. Again, this stuff doesn't do
proper things now anyway and USB won't work with dcache
Hi,
21.06.2012 02:14, Tom Rini wrote:
USB EHCI and DCACHE are not compatible, so disable DCACHE support at
build-time as run-time disable is insufficient for USB use.
Sorry for missing this discussion. I think compile-time disabling of the
cache is too brutal.
ehci-hcd cache handling is
):
am33xx: CPSW init and definitions
am33xx: pin mux defintions for CPSW switch
am335x_evm: CPSW support
Cyril Chemparathy (1):
cpsw: add driver for cpsw ethernet device
Ilya Yanok (3):
am335x_evm: read the on-board EEPROM
OMAP: networking support for SPL
am335x_evm: enable networking in SPL
From: Chandan Nath chandan.n...@ti.com
This patch adds platform-specific initialization for CPSW
switch on TI AM33XX SoCs.
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from V1:
- rebased to u-boot-ti/next
arch/arm/cpu/armv7/am33xx/clock.c
From: Chandan Nath chandan.n...@ti.com
This patch adds pin mux settings for CPSW switch found on
TI AM335X based boards (MII and RGMII modes).
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from V1:
- rebased to u-boot-ti/next
arch/arm/include
Read the on-board EEPROM during startup to detect the version
of the board we are running on (as for now only BeagleBone vs
EVM detection is supported).
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from V1:
- rebased to u-boot-ti/next
board/ti
on other code so SPL size
is increased significantly. No effort was done to decouple network
code and environment so far.
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
arch/arm/cpu/armv7/omap-common/Makefile |3 ++
arch/arm/cpu/armv7/omap-common/spl.c
From: Chandan Nath chandan.n...@ti.com
This patch adds board-specific initialization for CPSW on
TI AM335X based boards. Tested on BeagleBone.
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from V1:
- rebased to u-boot-ti/next
board/ti/am335x
sandhya.satyanaray...@ti.com
[ilya.yanok: Cleaned cache handling, some style cleanup, some small
fixes, use of internal RAM for descriptors]
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
Changes from V1:
- rebased to u-boot-ti/next
- use internal RAM for descriptors (dma_alloc_coherent
This patch adds support for networking in SPL on TI AM335x based
boards.
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
board/ti/am335x/evm.c| 12
include/configs/am335x_evm.h |5 -
2 files changed, 16 insertions(+), 1
Hi Marek,
On Tue, Jun 19, 2012 at 3:37 AM, Marek Vasut marek.va...@gmail.com wrote:
Kind of ... I mean rather insert an entry into MMU table at runtime that
says
this region is uncached. But that'd need some hack in the mallocator now
that
I think about it. It might not be as simple as I
Hi Marek,
[sorry for copying, forget to CC the list]
On Sat, Jun 16, 2012 at 2:29 AM, Marek Vasut marek.va...@gmail.com wrote:
Hm, can't we just punch a hole in the MMU table at runtime instead of
preallocating it like this?
It's allocated at runtime now, do you mean allocate it on demand?
Hi All,
On Thu, May 31, 2012 at 1:41 AM, Ilya Yanok
ilya.ya...@cogentembedded.comwrote:
This is a draft implementation of cache coherent memory allocator.
This simple implementation just reserves memory area below malloc
space and leave it uncached even if data cache is enabled.
Allocations
Tom, guys,
I've just found that I forgot to mention that this version requires my
patch [1] to work with enabled D-Cache correctly.
Hope to get some comments on it soon.
[1] http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/132464
Regards, Ilya.
On Fri, Jun 8, 2012 at 5:12 PM, Ilya Yanok
These patches add CPSW switch driver and enable support for it
on TI AM335x based boards. We need to detect the board type
to configure pins correctly so these patches also include small
fix to OMAP I2C driver.
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
compatible hardware
with 16bit data register so I can't test if those #ifdef
clauses really work.
CC: Tom Rini tr...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
drivers/i2c/omap24xx_i2c.c | 58
1 file changed, 26 insertions(+), 32
chandan.n...@ti.com
Signed-off-by: Satyanarayana, Sandhya sandhya.satyanaray...@ti.com
Signed-off-by: Ilya Yanok ilya.ya...@cogentembedded.com
---
drivers/net/Makefile |1 +
drivers/net/cpsw.c | 994 ++
include/cpsw.h | 51 +++
3 files
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