To support fastboot, we need to enable the controller first.
rk3399 is using dwc3 as usb device controller, this patch enable
the configs for dwc3 gadget.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
include/configs/rk3399_common.h | 21 +
1 file chang
This patch add board_usb_init() and interrupt callback
for dwc3 gadget.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
board/rockchip/evb_rk3399/evb-rk3399.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c
b
This patch set enable rk3399 dwc3 controller and gadget driver
for fastboot.
Kever Yang (4):
rk3399: add a empty "sys_proto.h" header file
board: evb-rk3399: add api to support dwc3 gadget
usb: dwc3: add support for 16 bit UTMI+ interface
config: rk3399: add support for d
The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one MACRO CONFIG_USB_DWC3_USB2PHY_16BIT to support 16 bit
UTMI+ interface on some SoCs like Rockchip rk3399.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/usb/dwc3/core.c | 10 ++
drivers/us
driver/usb/dwc3/gadget.c need a "sys_proto.h" header file, add a
empty one to make compile success.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/sys_proto.h | 10 ++
1 file changed, 10 insertions(+)
create mode 100644 arch
This patch add pinctrl driver for rk3399.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- move and reg value MACRO in C source, and use MASK/SHIFT
arch/arm/include/asm/arch-rockchip/grf_rk3399.h | 321 +
drivers/pinctrl/K
pmugrf is a module like grf which contain some of the iomux registers
and other registers.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/arm/include/asm/arch-rockchip/clock.h| 1 +
arch/arm/mach-roc
when driver probe.
Module like pwm which without interrupt number need to call the pinctrl
API manually.
Changes in v2:
- move and reg value MACRO in C source, and use MASK/SHIFT
Kever Yang (5):
rk3399: syscon: add support for pmugrf
pinctrl: add driver for rk3399
config: evb-rk3399: enable
This patch add pinctrl for sdcard which may not be initialized before
uboot.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/arm/dts/rk3399.dtsi | 37 +
1 file
This patch enable rk3399 pinctrl driver and gpio driver which is sub-node
of pinctrl.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
configs/evb-rk3399_defconfig | 2 ++
1 file changed, 2 insertions(+)
There is no interrupt line for each PWM which used by pinctrl to get the
periph_id, so it's not able to enable the default pinctrl setting by pinctrl
framework, let's enable it at board_init().
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chr
Hi Marek,
On 08/16/2016 09:18 PM, Marek Vasut wrote:
On 08/16/2016 12:03 PM, Kever Yang wrote:
The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one MACRO CONFIG_USB_DWC3_USB2PHY_16BIT to support 16 bit
UTMI+ interface on some SoCs like Rockchip rk3399.
Signed-off
Hi Marek,
On 08/17/2016 09:39 AM, Marek Vasut wrote:
On 08/17/2016 03:31 AM, Kever Yang wrote:
Hi Marek,
Hi,
On 08/16/2016 09:18 PM, Marek Vasut wrote:
On 08/16/2016 12:03 PM, Kever Yang wrote:
The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one MACRO
2017 at 23:37, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Simon,
For my rk3399(64bit) dts, the address is described as below:
#address-cells = <2>;
reg = <0x0 0xfe32 0x0 0x4000>;
not like 32-bit soc which reg address describe like:
reg = <0xfe32 0x4000>;
Hi Simon,
On 01/24/2017 09:51 PM, Simon Glass wrote:
Hi Kever,
On 18 January 2017 at 05:16, Kever Yang <kever.y...@rock-chips.com
<mailto:kever.y...@rock-chips.com>> wrote:
> This series patch enable basic driver for rk3399 SPL, the ATF support
> has been split a
Hi Simon,
On 01/26/2017 10:23 PM, Simon Glass wrote:
Hi Kever,
On 18 January 2017 at 05:16, Kever Yang <kever.y...@rock-chips.com> wrote:
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.
Signed-off-by: Kever Yang &l
Hi Simon,
Found 1 typo on the subject, 'suport' should be 'support',
do I need to send a new patch or you can correct it when you apply?
Thanks,
- Kever
On 01/26/2017 10:23 PM, Simon Glass wrote:
On 18 January 2017 at 05:25, Kever Yang <kever.y...@rock-chips.com> wrote:
Just do n
Hi Simon,
On 01/26/2017 10:23 PM, Simon Glass wrote:
Hi Kever,
On 18 January 2017 at 05:16, Kever Yang <kever.y...@rock-chips.com> wrote:
Add spl support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch
Hi Andre,
On 01/22/2017 06:58 PM, André Przywara wrote:
On 22/01/17 07:08, Kever Yang wrote:
Hi Andre,
Thanks for your patches, this is great help for enable ATF on U-Boot
SPL.
For ATF use case, we would like to identify which one is bl31 for we
need to
get entry point for it while we
Hi Andre,
On 01/22/2017 06:42 PM, André Przywara wrote:
On 22/01/17 07:16, Kever Yang wrote:
Hi Andre,
On 01/20/2017 09:53 AM, Andre Przywara wrote:
At the moment we load two images from a FIT image: the actual U-Boot
image and the DTB. Both times we have very similar code to deal
Hi Andre,
On 01/20/2017 09:53 AM, Andre Przywara wrote:
At the moment we load two images from a FIT image: the actual U-Boot
image and the DTB. Both times we have very similar code to deal with
alignment requirement the media we load from imposes upon us.
Factor out this code into a new
Hi Andre,
Thanks for your patches, this is great help for enable ATF on
U-Boot SPL.
For ATF use case, we would like to identify which one is bl31 for we need to
get entry point for it while we only need load address for other image.
Any idea on get this information from different
Hi Rick,
On 01/20/2017 02:29 AM, Rick Bronson wrote:
Hi Kever and Simon,
Thanks very much for the help. Really appreciate it.
I didn't see your detail steps for getting u-boot-dtb.bin, does it
include SPL here?
I'm using this method:
2. with "CONFIG_ROCKCHIP_SPL_BACK_TO_BROM",
Hi Simon,
On 02/14/2017 01:31 PM, Simon Glass wrote:
Hi Kever,
On 13 February 2017 at 01:13, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Simon,
On 02/08/2017 01:10 PM, Simon Glass wrote:
Hi Kever,
On 4 February 2017 at 16:30, Kever Yang <kever.y...@rock-chips.com> wrot
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v3:
- enable driver without of-platdata
- add binding file for sdram driver
- some fix base on Simon's c
Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2:
- split SPL patch into 4 patches
Changes in v1: None
arch
Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2: None
Changes in v1: None
arch/arm/dts/rk3399-evb.dts | 2 ++
Enable all the CONFIGs which need by SPL.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2: None
Changes in v1: None
configs/evb-rk3399_defconfig| 18 ++
include/configs/rk3
into dram_info instead of separate global
variables.
- add return value for error case
Kever Yang (4):
arm64: rk3399: add ddr controller driver
dts: rk3399: update for spl require driver
arm64: rk3399: add SPL support
config: rk3399: enable SPL config for evb-rk3399
arch/arm/Kconfig
ed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/arm/mach-rockchip/Kconfig| 11 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3328/Kconfig | 23 +++
Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Si
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- split rockchip_get_cru into arch/arm/mach-rockchip
- fix include header file order
- drop MACRO
Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2:
- fix include header file order
Hi Simon,
On 02/22/2017 02:06 AM, Simon Glass wrote:
Hi Kever,
On 17 February 2017 at 01:07, Kever Yang <kever.y...@rock-chips.com> wrote:
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Y
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/arm/dts/Makefile
Add rk3328 sysreset driver.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2:
- fix include header file order
drivers/sysreset/Makefile | 1 +
file order
- add space around operators in header file
- fix include header file order
- README file fix
Kever Yang (7):
rockchip: rk3328: add device tree file
rockchip: rk3328: add soc basic support
rockchip: rk3288: add clock driver
rockchip: rk3328: add pinctrl driver
rockchip: rk3328
RK_SPL_HDR_SIZE);
+ if (rkcommon_need_rc4_spl(params))
+ rkcommon_rc4_encode_spl(buf, RK_SPL_START - 4,
+ params->file_size - RK_SPL_START + 4);
+
/*
* Spread the image out so we only use the first 2KB of each 4KB
* regio
e },
{ "rk3288", "RK32", 0x8000, false },
{ "rk3399", "RK33", 0x2, false },
};
Reviewed-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Hi Heiko,
For this patch series, I have test and works on my NAND based rodxa board.
For the sd-card, you will need one patch to fix the problem which I have
send
to you offline.
Tested-by: Kever Yang <kever.y...@rock-chips.com>
Thanks,
- Kever
On 02/04/2017 12:09 AM, Heiko Stuebner
Hi Simon,
There is a typo on the subject of this patch, it should be rk3328
instead
of rk3288 :(
Sorry for that, are you able to fix it in your tree?
Thanks,
- Kever
On 02/24/2017 12:20 AM, Simon Glass wrote:
On 23 February 2017 at 00:37, Kever Yang <kever.y...@rock-chips.com>
Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2:
- fix include heade
ed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
- Removed contents of rk3328/Kconfig to avoid build error
Changes in v2: None
arch/arm/mach-rockchip/Kconfig| 11 +
arch/arm/mach-rockchip/Makefile
Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Si
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v3:
- remove I2C reg value MACRO definition
Changes in v2:
- split rockchip_get_cru into arch/arm/m
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v3:
- Moved new binding #defines into this pa
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.
Hi Simon,
On 02/23/2017 12:16 PM, Simon Glass wrote:
Hi Kever,
On 13 February 2017 at 02:39, Kever Yang <kever.y...@rock-chips.com> wrote:
Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- spl
Add rk3328 sysreset driver.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2:
- fix include header file order
drivers/sysreset/Make
Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v4:
- move SPL_SEPARATE_BSS to RK3399
Changes in v2:
- split SPL patch into 4 patches
arch/arm/mach-rock
file
- fix include header file order
- README file fix
Kever Yang (7):
rockchip: rk3328: add device tree file
rockchip: rk3328: add soc basic support
rockchip: rk3328: add clock driver
rockchip: rk3328: add pinctrl driver
rockchip: rk3328: add sysreset driver
rockchip: rk3328: add evb
Hi Simon, Jaehoon,
On 02/13/2017 05:51 PM, Jaehoon Chung wrote:
On 02/13/2017 06:23 PM, Kever Yang wrote:
Hi Simon,
On 01/16/2017 12:15 PM, Simon Glass wrote:
Hi Kever,
On 15 January 2017 at 18:28, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Simon,
I met two issue when
Hi Jacob,
On 02/15/2017 11:06 AM, Jacob Chen wrote:
We should remove config_spl_of_platdata to build u-boot-spl-dtb.bin rather than
u-boot-spl-nodtb.bin
since we use spl_back_to_brom.
Have you try with CONFIG_SPL_OF_PLATDATA on and without SPL_BACK_TO_BROM?
If this works on firefly, then we
Hi Simon,
On 02/08/2017 01:10 PM, Simon Glass wrote:
+Tom in case you have some thoughts
Hi Kever,
On 4 February 2017 at 18:45, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Simon,
On 01/26/2017 10:23 PM, Simon Glass wrote:
Hi Kever,
On 18 January 2017 at 05:16, Kever Yang &l
Hi Simon,
On 01/16/2017 12:15 PM, Simon Glass wrote:
Hi Kever,
On 15 January 2017 at 18:28, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Simon,
I met two issue when using of-platdata
1. compitable name with '.'
I get compile error as below:
In file included from incl
Hi Simon,
On 02/08/2017 01:10 PM, Simon Glass wrote:
Hi Kever,
On 4 February 2017 at 16:30, Kever Yang <kever.y...@rock-chips.com> wrote:
Hi Simon,
For rk3399, the data for sdram driver in dts is big, I don't want to do
the copy for it,
Are you referring to th
ARM64 is using 64bit address which address cell is 2 instead of 1,
update to support it when of-platdata enabled.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/core/regmap.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/d
Enable all the CONFIGs which need by SPL.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
Changes in v1: None
configs/evb-rk3399_defconfig| 18 ++
include/configs/rk3399_common.h | 5 +
2 files changed, 23 insertions(+)
diff
rk3399 has different syscon registers which may used in spl,
add to support rk3399 spl.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
Changes in v1: None
arch/arm/include/asm/arch-rockchip/clock.h| 2 ++
arch/arm/mach-rockchip/rk3399/syscon_rk3399.
Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
Changes in v1: None
arch/arm/include/asm/arch-rockchip/clock.h | 7
rk3399 grf register bit defenitions should locate in header
file, so that not only pinctrl can use it.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
Changes in v1: None
arch/arm/include/asm/arch-rockchip/
- get all controller base address from dts instead of hard code
- gather all controller into dram_info instead of separate global
variables.
- add return value for error case
Kever Yang (9):
arm64: rk3399: add ddr controller driver
arm64: rk3399: move grf register definitions to grf_rk3399.h
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- use lower-case hex for input dts data
- using rk3288 like style to encode/decode sys_reg
- gathe
Add SPL support for rk3399, default with of-platdata enabled.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- split SPL patch into 4 patches
Changes in v1: None
arch/arm/Kconfig | 1 +
arch/arm/mach-rockchip/Kconfig
Add syscon and dmc node, and 'u-boot,dm-pre-reloc' option for
required driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2: None
Changes in v1: None
arch/arm/dts/rk3399-evb.dts | 2 ++
arch/arm/dts/rk3399.dtsi| 44 +
Do not use the API which of-platdata not support.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
Changes in v1: None
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 5 -
1 file changed, 4 insertions(+)
Change some API in order to enable of-platdata.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
Changes in v1: None
drivers/mmc/rockchip_sdhci.c | 17 -
1 file changed, 16 insertions(+)
Add dts binding header for rk3328, files origin from kernel.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/rk3328-evb.dts| 45 +
Add rk3328 sysreset driver.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_rk3328.c | 45 ++
2 files
evb-rk3328 is an evb from Rockchip based on rk3328 SoC:
- 2 USB2.0 Host port;
- 1 USB3.0 Host port;
- 1 HDMI port;
- 2 10/100M eth port;
- 2GB ddr;
- 16GB eMMC;
- UART to USB debug port;
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.
Enable board config for evb-rk3328.
SDcard and eMMC boot is OK in this initial version,
USB and EMAC function is not available now, will comes later.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Add rk3328 pinctrl driver and grf/iomux structure definition.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 134
drivers/pin
Add rk3328 clock driver and cru structure definition.
Signed-off-by: William Zhang <william.zh...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/cru_rk3328.h | 65 +++
drivers/clk/rockchip/Makefile |
ed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/mach-rockchip/Kconfig| 11 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3328/Kconfig | 23 ++
arch/arm/mach-rockchip/rk3328/Makefile| 8
arch/arm/m
SPL in this
version, for the ATF patches is still under discussion, we'd
better have a version which able to work.
Kever Yang (7):
arm64: dts: add support for Rockchip rk3328 soc
ARM64: rockchip: add support for rk3328 SoC
clk: rockchip: add support for rk3328
pinctrl: rockchip: add support
Hi Simon,
Thanks for your review, I would like to take all the comments but
one below,
because I think the change only get a lot of work to do but have no any help
on understand the source code, because each of shift/mask operation has
comment
for it.
I have spend a lot of time on
Hi
Who is suppose to maintain source in "common/spl"?
I hope to get more comments before my first version patch without 'RFC'
and with suggestion from Michal.
Thanks,
- Kever
On 12/29/2016 06:25 PM, Kever Yang wrote:
ATF(ARM Trust Firmware) is used by ARM arch64 SoCs, find more
Change some API in order to enable of-platdata.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/mmc/rockchip_sdhci.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
index e
Just do nothing in post_bind if of-platdata enabled,
for there is no dm_scan_fdt_dev().
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/core/simple-bus.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c
index 5
Add ddr clock setting, add rockchip_get_pmucru API,
and enable of-platdata support.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/include/asm/arch-rockchip/clock.h | 7 ++
arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 5 ++
arch/arm/mach-rockchip/
RK3399 support DDR3, LPDDR3, DDR4 sdram, this patch is porting from
coreboot, support 4GB lpddr3 in this version.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
arch/arm/dts/rk3399-sdram-lpddr3-4GB-1600.dtsi| 1536 +
arch/arm/include/asm/arch-ro
Do not use the API which of-platdata not support.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
drivers/pinctrl/rockchip/pinctrl_rk3399.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3399.c
b/drivers/pinctrl/ro
;daniel.m...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- update for comments from Marek
drivers/usb/host/Makefile| 1 +
drivers/usb/host/xhci-rockchip.c | 227 +++
include/linux/usb/dwc3.h
devices on rk3399 evb.
Note: type-C port only support usb 2.0 currently because the PD driver
and USB 3.0 phy driver not enabled.
Changes in v2:
- update for comments from Marek
- use regulator_get_by_platname instead of uclass_get_device_by_name
- add Acked-by Tag from Simon
Kever Yang (3):
dts
From: MengDongyang <daniel.m...@rock-chips.com>
rk3399 has two dwc3 controller for type-C port, add the dts node
and enable them.
Signed-off-by: MengDongyang <daniel.m...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chrom
From: MengDongyang <daniel.m...@rock-chips.com>
This patch to enable configs for usb module
- xhci
- ehci
- usb storage
- usb net
Signed-off-by: MengDongyang <daniel.m...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chrom
rk3399 evb using one gpio to enable 5V output for both USB 2.0
host port, let's use fixed regulator for them.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2: None
arch/arm/dts/rk3399-evb.dts | 6 ++
1 fil
This patch enable fixed regulator driver for rk3399 evb.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v2:
- add Acked-by Tag from Simon
configs/evb-rk3399_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --g
From: MengDongyang <daniel.m...@rock-chips.com>
Select DM_USB to compatible with USB DM driver model.
Signed-off-by: MengDongyang <daniel.m...@rock-chips.com>
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Change
rk3399 using one gpio control signal for two usb 2.0 host port,
it's better to enable the power in board file instead of in usb driver.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v2:
- use regulator_get_by_platname instead of uclass_get_device_by_name
board/ro
From: Kever Yang <kever.y...@gmail.com>
This patch set add the pinctrl driver for rk3399 and enable pinctrl for
pwm module.
Module with pinctrl driver support and with interrupt number and default
pinctrl in dts node will get pinctrl initialized when driver probe.
Module like pwm which w
Hi Andy,
On 02/28/2017 12:22 AM, Andy Shevchenko wrote:
Add a specific serial driver for Intel MID platforms.
It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.
The UART clock is calculated as
UART clock = XTAL * UART_MUL /
+ Marek
On 08/24/2016 11:46 AM, Kever Yang wrote:
This patch add board_usb_init() and interrupt callback
for dwc3 gadget.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Reviewed-by: Simon Glass <s...@chromium.org>
---
Changes in v2:
- parse dt for utmi width
bo
Hi Marek,
On 08/24/2016 07:38 PM, Marek Vasut wrote:
On 08/24/2016 05:46 AM, Kever Yang wrote:
The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one variable in dwc3/dwc3_device struct to support 16 bit
UTMI+ interface on some SoCs like Rockchip rk3399.
Signed-off
On 08/31/2016 08:32 PM, Marek Vasut wrote:
On 08/31/2016 10:40 AM, Kever Yang wrote:
The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one variable in dwc3/dwc3_device struct to support 16 bit
UTMI+ interface on some SoCs like Rockchip rk3399.
Signed-off-by: Kever Yang
This patch add board_usb_init() and interrupt callback
for dwc3 gadget.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v4:
- parse DT for quirk, base address and maximum speed
Changes in v3:
- remove utmi width DT parse from borad init
Changes in v2:
- parse dt fo
driver/usb/dwc3/gadget.c need a "sys_proto.h" header file, add a
empty one to make compile success.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Acked-by: Simon Glass <s...@chromium.org>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/inc
The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
add one variable in dwc3/dwc3_device struct to support 16 bit
UTMI+ interface on some SoCs like Rockchip rk3399.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v4:
- use 1 bit for usb2_phyif_utmi
width in dwc3 driver
- move the config into Kconfig file.
Changes in v2:
- parse dt for utmi width
- use a variable to identify utmi+ bus width instead of CONFIG MACRO
- remove config for USB2PHY UTMI BITS
Kever Yang (4):
rk3399: add a empty "sys_proto.h" header file
board: evb-rk339
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