[PATCH v3 1/1] andes: Unify naming policy for Andes related source
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig| 4 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile| 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +++---
arch/riscv/cpu/{andesv5 => andes}/cpu.c | 0
arch/riscv/cpu/{andesv5 => andes}/spl.c | 0
board/{AndesTech => andestech}/ae350/Kconfig | 6 +--
.../ae350/MAINTAINERS | 2 +-
board/{AndesTech => andestech}/ae350/Makefile | 0
board/{AndesTech => andestech}/ae350/ae350.c | 2 +-
doc/board/index.rst | 2 +-
drivers/cache/Kconfig | 6 +--
drivers/cache/Makefile| 2 +-
.../cache/{cache-v5l2.c => cache-andes-l2.c} | 40 +--
14 files changed, 40 insertions(+), 40 deletions(-)
rename arch/riscv/cpu/{andesv5 => andes}/Kconfig (91%)
rename arch/riscv/cpu/{andesv5 => andes}/Makefile (100%)
rename arch/riscv/cpu/{andesv5 => andes}/cache.c (90%)
rename arch/riscv/cpu/{andesv5 => andes}/cpu.c (100%)
rename arch/riscv/cpu/{andesv5 => andes}/spl.c (100%)
rename board/{AndesTech => andestech}/ae350/Kconfig (91%)
rename board/{AndesTech => andestech}/ae350/MAINTAINERS (95%)
rename board/{AndesTech => andestech}/ae350/Makefile (100%)
rename board/{AndesTech => andestech}/ae350/ae350.c (99%)
rename drivers/cache/{cache-v5l2.c => cache-andes-l2.c} (84%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e20ef63bb..fa3b016c52 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -80,7 +80,7 @@ config SPL_ZERO_MEM_BEFORE_USE
Sifive core devices that uses L2 cache to store SPL.
# board-specific options below
-source "board/AndesTech/ae350/Kconfig"
+source "board/andestech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/openpiton/riscv64/Kconfig"
@@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig"
source "board/xilinx/mbv/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/andes/Kconfig"
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andes/Kconfig
similarity index 91%
rename from arch/riscv/cpu/andesv5/Kconfig
rename to arch/riscv/cpu/andes/Kconfig
index e3efb0de8f..120fec5e54 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andes/Kconfig
@@ -1,4 +1,4 @@
-config RISCV_NDS
+config RISCV_ANDES
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
@@ -8,7 +8,7 @@ config RISCV_NDS
imply ANDES_PLMT_TIMER
imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply V5L2_CACHE
+ imply ANDES_L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andes/Makefile
similarity index 100%
rename from arch/riscv/cpu/andesv5/Makefile
rename to arch/riscv/cpu/andes/Makefile
diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andes/cache.c
similarity index 90%
rename from arch/riscv/cpu/andesv5/cache.c
rename to arch/riscv/cpu/andes/cache.c
index 269bb27f75..7d3df8722d 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -12,21 +12,21 @@
#include
#include
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
void enable_caches(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_CACHE,
- DM_DRIVER_GET(v5l2_cache),
+ DM_DRIVER_GET(andes_l2_cache),
);
if (ret) {
- log_debug("Cannot enable v5l2 cache\n");
+ log_debug("Cannot enable Andes L2 cache\n");
} else {
ret = cache_enable(dev);
if (ret)
- log_debug("v5l2 cache enable failed\n");
+ log_debug("Failed to enable Andes L2 cache\n");
}
}
@@ -78,7 +78,7 @@ void dcache_enable(void)
asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_enable);
#endif
}
@@ -89,7 +89,7 @@ void dcache_disable(void)
asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_disable);
#endif
}
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arc
[PATCH v2 1/1] andes: Unify naming policy for Andes related source
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig| 2 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile| 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +++---
arch/riscv/cpu/{andesv5 => andes}/cpu.c | 0
arch/riscv/cpu/{andesv5 => andes}/spl.c | 0
board/{AndesTech => andestech}/ae350/Kconfig | 4 +-
.../ae350/MAINTAINERS | 0
board/{AndesTech => andestech}/ae350/Makefile | 0
board/{AndesTech => andestech}/ae350/ae350.c | 2 +-
drivers/cache/Kconfig | 6 +--
drivers/cache/Makefile| 2 +-
.../cache/{cache-v5l2.c => cache-andes-l2.c} | 40 +--
13 files changed, 36 insertions(+), 36 deletions(-)
rename arch/riscv/cpu/{andesv5 => andes}/Kconfig (91%)
rename arch/riscv/cpu/{andesv5 => andes}/Makefile (100%)
rename arch/riscv/cpu/{andesv5 => andes}/cache.c (90%)
rename arch/riscv/cpu/{andesv5 => andes}/cpu.c (100%)
rename arch/riscv/cpu/{andesv5 => andes}/spl.c (100%)
rename board/{AndesTech => andestech}/ae350/Kconfig (94%)
rename board/{AndesTech => andestech}/ae350/MAINTAINERS (100%)
rename board/{AndesTech => andestech}/ae350/Makefile (100%)
rename board/{AndesTech => andestech}/ae350/ae350.c (99%)
rename drivers/cache/{cache-v5l2.c => cache-andes-l2.c} (84%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e20ef63bb..120ee1a01c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig"
source "board/xilinx/mbv/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/andes/Kconfig"
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andes/Kconfig
similarity index 91%
rename from arch/riscv/cpu/andesv5/Kconfig
rename to arch/riscv/cpu/andes/Kconfig
index e3efb0de8f..120fec5e54 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andes/Kconfig
@@ -1,4 +1,4 @@
-config RISCV_NDS
+config RISCV_ANDES
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
@@ -8,7 +8,7 @@ config RISCV_NDS
imply ANDES_PLMT_TIMER
imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply V5L2_CACHE
+ imply ANDES_L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andes/Makefile
similarity index 100%
rename from arch/riscv/cpu/andesv5/Makefile
rename to arch/riscv/cpu/andes/Makefile
diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andes/cache.c
similarity index 90%
rename from arch/riscv/cpu/andesv5/cache.c
rename to arch/riscv/cpu/andes/cache.c
index 269bb27f75..7d3df8722d 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -12,21 +12,21 @@
#include
#include
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
void enable_caches(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_CACHE,
- DM_DRIVER_GET(v5l2_cache),
+ DM_DRIVER_GET(andes_l2_cache),
);
if (ret) {
- log_debug("Cannot enable v5l2 cache\n");
+ log_debug("Cannot enable Andes L2 cache\n");
} else {
ret = cache_enable(dev);
if (ret)
- log_debug("v5l2 cache enable failed\n");
+ log_debug("Failed to enable Andes L2 cache\n");
}
}
@@ -78,7 +78,7 @@ void dcache_enable(void)
asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_enable);
#endif
}
@@ -89,7 +89,7 @@ void dcache_disable(void)
asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_disable);
#endif
}
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andes/cpu.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/cpu.c
rename to arch/riscv/cpu/andes/cpu.c
diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andes/spl.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/spl.c
rename to arch/riscv/cpu/andes/spl.c
diff --git a/board/AndesTech/ae350/Kconfig b/board/andestech/ae350/Kconfig
similarity index 94%
rename from board/AndesTech/ae350/Kconfig
rename to board/andestech/ae350/Kconfig
[PATCH 1/1] andes: Unify naming policy for Andes related source
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig| 2 +-
arch/riscv/cpu/{andesv5 => andes}/Kconfig | 4 +-
arch/riscv/cpu/{andesv5 => andes}/Makefile| 0
arch/riscv/cpu/{andesv5 => andes}/cache.c | 12 +++---
arch/riscv/cpu/{andesv5 => andes}/cpu.c | 0
arch/riscv/cpu/{andesv5 => andes}/spl.c | 0
board/{AndesTech => andestech}/ae350/Kconfig | 4 +-
.../ae350/MAINTAINERS | 0
board/{AndesTech => andestech}/ae350/Makefile | 0
board/{AndesTech => andestech}/ae350/ae350.c | 2 +-
drivers/cache/Kconfig | 6 +--
drivers/cache/Makefile| 2 +-
.../cache/{cache-v5l2.c => cache-andes-l2.c} | 40 +--
13 files changed, 36 insertions(+), 36 deletions(-)
rename arch/riscv/cpu/{andesv5 => andes}/Kconfig (91%)
rename arch/riscv/cpu/{andesv5 => andes}/Makefile (100%)
rename arch/riscv/cpu/{andesv5 => andes}/cache.c (90%)
rename arch/riscv/cpu/{andesv5 => andes}/cpu.c (100%)
rename arch/riscv/cpu/{andesv5 => andes}/spl.c (100%)
rename board/{AndesTech => andestech}/ae350/Kconfig (94%)
rename board/{AndesTech => andestech}/ae350/MAINTAINERS (100%)
rename board/{AndesTech => andestech}/ae350/Makefile (100%)
rename board/{AndesTech => andestech}/ae350/ae350.c (99%)
rename drivers/cache/{cache-v5l2.c => cache-andes-l2.c} (84%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7e20ef63bb..120ee1a01c 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -93,7 +93,7 @@ source "board/thead/th1520_lpi4a/Kconfig"
source "board/xilinx/mbv/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/andesv5/Kconfig"
+source "arch/riscv/cpu/andes/Kconfig"
source "arch/riscv/cpu/cv1800b/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andes/Kconfig
similarity index 91%
rename from arch/riscv/cpu/andesv5/Kconfig
rename to arch/riscv/cpu/andes/Kconfig
index e3efb0de8f..120fec5e54 100644
--- a/arch/riscv/cpu/andesv5/Kconfig
+++ b/arch/riscv/cpu/andes/Kconfig
@@ -1,4 +1,4 @@
-config RISCV_NDS
+config RISCV_ANDES
bool
select ARCH_EARLY_INIT_R
select SYS_CACHE_SHIFT_6
@@ -8,7 +8,7 @@ config RISCV_NDS
imply ANDES_PLMT_TIMER
imply SPL_ANDES_PLMT_TIMER
imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
- imply V5L2_CACHE
+ imply ANDES_L2_CACHE
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
diff --git a/arch/riscv/cpu/andesv5/Makefile b/arch/riscv/cpu/andes/Makefile
similarity index 100%
rename from arch/riscv/cpu/andesv5/Makefile
rename to arch/riscv/cpu/andes/Makefile
diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andes/cache.c
similarity index 90%
rename from arch/riscv/cpu/andesv5/cache.c
rename to arch/riscv/cpu/andes/cache.c
index 269bb27f75..801857ab8f 100644
--- a/arch/riscv/cpu/andesv5/cache.c
+++ b/arch/riscv/cpu/andes/cache.c
@@ -12,21 +12,21 @@
#include
#include
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
void enable_caches(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_CACHE,
- DM_DRIVER_GET(v5l2_cache),
+ DM_DRIVER_GET(andes_l2_cache),
);
if (ret) {
- log_debug("Cannot enable v5l2 cache\n");
+ log_debug("Cannot enable andes-l2 cache\n");
} else {
ret = cache_enable(dev);
if (ret)
- log_debug("v5l2 cache enable failed\n");
+ log_debug("andes-l2 cache enable failed\n");
}
}
@@ -78,7 +78,7 @@ void dcache_enable(void)
asm volatile("csrsi %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_enable);
#endif
}
@@ -89,7 +89,7 @@ void dcache_disable(void)
asm volatile("csrci %0, 0x2" :: "i"(CSR_MCACHE_CTL));
#endif
-#ifdef CONFIG_V5L2_CACHE
+#ifdef CONFIG_ANDES_L2_CACHE
cache_ops(cache_disable);
#endif
}
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andes/cpu.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/cpu.c
rename to arch/riscv/cpu/andes/cpu.c
diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andes/spl.c
similarity index 100%
rename from arch/riscv/cpu/andesv5/spl.c
rename to arch/riscv/cpu/andes/spl.c
diff --git a/board/AndesTech/ae350/Kconfig b/board/andestech/ae350/Kconfig
similarity index 94%
rename from board/AndesTech/ae350/Kconfig
rename to board/andestech/ae350/Kconfig
[PATCH 1/1] spl: Improve error message for SPL memory allocation
There could be two memory allocation scheme in SPL phase.
Explicitly print the corresponding error message.
Signed-off-by: Leo Yu-Chi Liang
---
common/spl/spl_fit.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 872df0c0fe..e5195d460c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -550,7 +550,12 @@ static void *spl_get_fit_load_buffer(size_t size)
buf = malloc_cache_aligned(size);
if (!buf) {
pr_err("Could not get FIT buffer of %lu bytes\n", (ulong)size);
- pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_SIZE\n");
+
+ if (IS_ENABLED(CONFIG_SPL_SYS_MALLOC))
+ pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_SIZE\n");
+ else
+ pr_err("\tcheck CONFIG_SPL_SYS_MALLOC_F_LEN\n");
+
buf = spl_get_load_buffer(0, size);
}
return buf;
--
2.34.1
[PATCH v2 6/6] andes: ae350: Enable MISC_INIT_R for ae350 platform
Enable MISC_INIT_R for ae350 to support CPU name detection and re-sync the configs via make savedefconfig. Signed-off-by: Leo Yu-Chi Liang --- configs/ae350_rv32_defconfig | 5 +++-- configs/ae350_rv32_spl_defconfig | 5 +++-- configs/ae350_rv32_spl_xip_defconfig | 5 +++-- configs/ae350_rv32_xip_defconfig | 5 +++-- configs/ae350_rv64_defconfig | 5 +++-- configs/ae350_rv64_spl_defconfig | 5 +++-- configs/ae350_rv64_spl_xip_defconfig | 5 +++-- configs/ae350_rv64_xip_defconfig | 5 +++-- 8 files changed, 24 insertions(+), 16 deletions(-) diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 06cd972a0d..3bfa3e9f8e 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -11,14 +11,15 @@ CONFIG_SYS_LOAD_ADDR=0x10 CONFIG_TARGET_ANDES_AE350=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index f469d5bb2b..aeb50206d2 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 +CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10 CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 9672a19c23..f15ec301ce 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -17,19 +17,20 @@ CONFIG_SPL_XIP=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 +CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10 CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index b90200a97e..c40eb043c5 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -12,14 +12,15 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_XIP=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig index a4b9ad6162..7ae938aeb2 100644 --- a/configs/ae350_rv64_defconfig +++ b/configs/ae350_rv64_defconfig @@ -11,14 +11,15 @@ CONFIG_TARGET_ANDES_AE350=y CONFIG_ARCH_RV64I=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SYS_PROMPT="RISC-V # " -CONFIG_SYS_PBSIZE=1050 -CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_CMD_IMLS=y CONFIG_CMD_MMC=y CONFIG_CMD_SF_TEST=y diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 834a0fbbdd..68ac4325ab 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -16,19 +16,20 @@ CONFIG_RISCV_SMODE=y CONFIG_SYS_MONITOR_BASE=0x8800 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x1000 +CONFIG_SYS_BOOTM_LEN=0x400 CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_SYS_PBSIZE=1050 CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y CONFIG_SPL_MAX_SIZE=0x10 CONFIG_SPL_BSS_START_ADDR=0x40 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_CACHE=y CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x0 CONFIG_SYS_PROMPT="RISC-V # &q
[PATCH v2 5/6] andes: ae350: Save cpu name to env
Detect CPU name through marchid and then save it to env.
Signed-off-by: Leo Yu-Chi Liang
---
board/AndesTech/ae350/ae350.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index bef9e3149e..4e53fee5d2 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -13,7 +13,9 @@
#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
#include
#endif
+#include
#include
+#include
#include
#include
#include
@@ -27,6 +29,27 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* Miscellaneous platform dependent initializations
*/
+#if IS_ENABLED(CONFIG_MISC_INIT_R)
+int misc_init_r(void)
+{
+long csr_marchid = 0;
+const long mask_64 = 0x8000;
+const long mask_cpu = 0xff;
+char cpu_name[10] = {};
+
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+sbi_get_marchid(_marchid);
+#elif CONFIG_IS_ENABLED(RISCV_MMODE)
+csr_marchid = csr_read(CSR_MARCHID);
+#endif
+if (mask_64 & csr_marchid)
+snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu &
csr_marchid));
+else
+snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid));
+
+return env_set("cpu", cpu_name);
+}
+#endif
#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x10)
--
2.34.1
[PATCH v2 4/6] andes: cpu: Enable cache and TLB ECC support
Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/cpu/andesv5/cpu.c| 3 ++- arch/riscv/include/asm/arch-andes/csr.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index a23b7948d9..d25ecba0e8 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -35,7 +35,8 @@ void harts_early_init(void) mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ - MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN); + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) mcache_ctl_val |= MCACHE_CTL_IC_EN; diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 3f3f05b348..028fd01c2f 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -18,11 +18,14 @@ #define MCACHE_CTL_IC_EN BIT(0) #define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_IC_ECCENBIT(3) +#define MCACHE_CTL_DC_ECCENBIT(5) #define MCACHE_CTL_CCTL_SUEN BIT(8) #define MCACHE_CTL_IC_PREFETCH_EN BIT(9) #define MCACHE_CTL_DC_PREFETCH_EN BIT(10) #define MCACHE_CTL_DC_WAROUND_EN BIT(13) #define MCACHE_CTL_L2C_WAROUND_EN BIT(15) +#define MCACHE_CTL_TLB_ECCEN BIT(18) #define MCACHE_CTL_DC_COHENBIT(19) #define MCACHE_CTL_DC_COHSTA BIT(20) -- 2.34.1
[PATCH v2 3/6] andes: cpu: Enable memboost feature
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c| 9 -
arch/riscv/include/asm/arch-andes/csr.h | 6 ++
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index e764f6c5c0..a23b7948d9 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -31,8 +31,11 @@ void harts_early_init(void)
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
- mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
+ mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \
+ MCACHE_CTL_IC_PREFETCH_EN |
MCACHE_CTL_DC_PREFETCH_EN | \
+ MCACHE_CTL_DC_WAROUND_EN |
MCACHE_CTL_L2C_WAROUND_EN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl_val |= MCACHE_CTL_IC_EN;
@@ -52,5 +55,9 @@ void harts_early_init(void)
while (!(csr_read(CSR_MCACHE_CTL) &
MCACHE_CTL_DC_COHSTA));
}
}
+
+ mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+ csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
}
}
diff --git a/arch/riscv/include/asm/arch-andes/csr.h
b/arch/riscv/include/asm/arch-andes/csr.h
index 12d5eb6f6c..3f3f05b348 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -19,9 +19,15 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
#define MCACHE_CTL_DC_COHENBIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
#define CCTL_L1D_WBINVAL_ALL 6
--
2.34.1
[PATCH v2 2/6] andes: ae350: Implement cache switch via Kconfig
Kconfig provides SYS_[I|D]CACHE_OFF config options to switch off caches.
Provide the corresponding implementation to the options.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c | 25 -
board/AndesTech/ae350/ae350.c | 3 ++-
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 63bc24cdfc..e764f6c5c0 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -32,18 +32,25 @@ void harts_early_init(void)
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
- mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
- MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
+ mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN;
+
+ if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
+ mcache_ctl_val |= MCACHE_CTL_IC_EN;
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ mcache_ctl_val |= (MCACHE_CTL_DC_EN |
MCACHE_CTL_DC_COHEN);
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
- /*
-* Check mcache_ctl.DC_COHEN, we assume this platform does
-* not support CM if the bit is hard-wired to 0.
-*/
- if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
- /* Wait for DC_COHSTA bit to be set */
- while (!(csr_read(CSR_MCACHE_CTL) &
MCACHE_CTL_DC_COHSTA));
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+ /*
+* Check mcache_ctl.DC_COHEN, we assume this platform
does
+* not support CM if the bit is hard-wired to 0.
+*/
+ if (csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHEN) {
+ /* Wait for DC_COHSTA bit to be set */
+ while (!(csr_read(CSR_MCACHE_CTL) &
MCACHE_CTL_DC_COHSTA));
+ }
}
}
}
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..bef9e3149e 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err)
void spl_board_init()
{
/* enable v5l2 cache */
- enable_caches();
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ enable_caches();
}
#endif
--
2.34.1
[PATCH v2 1/6] andes: csr.h: Clean up CSR definition
Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/arch-andes/csr.h | 20 arch/riscv/include/asm/csr.h| 1 + 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 393d51c6dd..12d5eb6f6c 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -12,20 +12,16 @@ #define CSR_MCACHE_CTL 0x7ca #define CSR_MMISC_CTL 0x7d0 -#define CSR_MARCHID 0xf12 #define CSR_MCCTLCOMMAND 0x7cc -#define MCACHE_CTL_IC_EN_OFFSET 0 -#define MCACHE_CTL_DC_EN_OFFSET 1 -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define MCACHE_CTL_DC_COHEN_OFFSET 19 -#define MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) +/* mcache_ctl register */ + +#define MCACHE_CTL_IC_EN BIT(0) +#define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_DC_COHENBIT(19) +#define MCACHE_CTL_DC_COHSTA BIT(20) + #define CCTL_L1D_WBINVAL_ALL 6 diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 1a15089cae..986f951c31 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -142,6 +142,7 @@ #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 +#define CSR_MARCHID0xf12 #define CSR_MHARTID0xf14 #ifndef __ASSEMBLY__ -- 2.34.1
[PATCH 5/5] andes: ae350: Save cpu name to env
Detect CPU name through marchid and then save it to env.
Signed-off-by: Leo Yu-Chi Liang
---
board/AndesTech/ae350/ae350.c | 20
1 file changed, 20 insertions(+)
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index bef9e3149e..9faf46d96e 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -28,6 +28,26 @@ DECLARE_GLOBAL_DATA_PTR;
* Miscellaneous platform dependent initializations
*/
+int misc_init_r(void)
+{
+long csr_marchid = 0;
+const long mask_64 = 0x8000;
+const long mask_cpu = 0xff;
+char cpu_name[10] = {};
+
+#if CONFIG_IS_ENABLED(RISCV_SMODE)
+sbi_get_marchid(_marchid);
+#elif CONFIG_IS_ENABLED(RISCV_MMODE)
+csr_marchid = csr_read(CSR_MARCHID);
+#endif
+if (mask_64 & csr_marchid)
+snprintf(cpu_name, sizeof(cpu_name), "ax%lx", (mask_cpu &
csr_marchid));
+else
+snprintf(cpu_name, sizeof(cpu_name), "a%lx", (mask_cpu & csr_marchid));
+
+return env_set("cpu", cpu_name);
+}
+
#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x10)
void spl_perform_fixups(struct spl_image_info *spl_image)
--
2.34.1
[PATCH 4/5] andes: cpu: Enable cache and TLB ECC support
Andes CPU supports cache and TLB ECC. Enable them by default. Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/cpu/andesv5/cpu.c| 1 + arch/riscv/include/asm/arch-andes/csr.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index c9288dcb51..c011c00a94 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -36,6 +36,7 @@ void harts_early_init(void) mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN | \ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN); if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) mcache_ctl |= MCACHE_CTL_IC_EN; diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 755504c3c4..1a34618066 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -19,11 +19,14 @@ #define MCACHE_CTL_IC_EN BIT(0) #define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_IC_ECCENBIT(3) +#define MCACHE_CTL_DC_ECCENBIT(5) #define MCACHE_CTL_CCTL_SUEN BIT(8) #define MCACHE_CTL_IC_PREFETCH_EN BIT(9) #define MCACHE_CTL_DC_PREFETCH_EN BIT(10) #define MCACHE_CTL_DC_WAROUND_EN BIT(13) #define MCACHE_CTL_L2C_WAROUND_EN BIT(15) +#define MCACHE_CTL_TLB_ECCEN BIT(18) #define MCACHE_CTL_DC_COHENBIT(19) #define MCACHE_CTL_DC_COHSTA BIT(20) -- 2.34.1
[PATCH 3/5] andes: cpu: Enable memboost feature
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c| 7 +++
arch/riscv/include/asm/arch-andes/csr.h | 6 ++
2 files changed, 13 insertions(+)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 50cd31905d..c9288dcb51 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -31,8 +31,11 @@ void harts_early_init(void)
/* Enable I/D-cache in SPL */
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL);
mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN |
\
+ MCACHE_CTL_IC_PREFETCH_EN |
MCACHE_CTL_DC_PREFETCH_EN | \
+ MCACHE_CTL_DC_WAROUND_EN |
MCACHE_CTL_L2C_WAROUND_EN | \
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
mcache_ctl |= MCACHE_CTL_IC_EN;
@@ -51,4 +54,8 @@ void harts_early_init(void)
while (!(csr_read(CSR_MCACHE_CTL) &
MCACHE_CTL_DC_COHSTA));
}
}
+ mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+
+ csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
+ }
}
diff --git a/arch/riscv/include/asm/arch-andes/csr.h
b/arch/riscv/include/asm/arch-andes/csr.h
index 93aa8b2343..755504c3c4 100644
--- a/arch/riscv/include/asm/arch-andes/csr.h
+++ b/arch/riscv/include/asm/arch-andes/csr.h
@@ -20,9 +20,15 @@
#define MCACHE_CTL_IC_EN BIT(0)
#define MCACHE_CTL_DC_EN BIT(1)
#define MCACHE_CTL_CCTL_SUEN BIT(8)
+#define MCACHE_CTL_IC_PREFETCH_EN BIT(9)
+#define MCACHE_CTL_DC_PREFETCH_EN BIT(10)
+#define MCACHE_CTL_DC_WAROUND_EN BIT(13)
+#define MCACHE_CTL_L2C_WAROUND_EN BIT(15)
#define MCACHE_CTL_DC_COHENBIT(19)
#define MCACHE_CTL_DC_COHSTA BIT(20)
+/* mmisc_ctl register */
+#define MMISC_CTL_NON_BLOCKING_EN BIT(8)
#define CCTL_L1D_WBINVAL_ALL 6
--
2.34.1
[PATCH 2/5] andes: ae350: Implement cache switch via Kconfig
Kconfig provides SYS_[I|D]CACHE_OFF config options
to switch off caches. Implement the corresponding options.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/andesv5/cpu.c | 9 +++--
board/AndesTech/ae350/ae350.c | 3 ++-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
index 63bc24cdfc..50cd31905d 100644
--- a/arch/riscv/cpu/andesv5/cpu.c
+++ b/arch/riscv/cpu/andesv5/cpu.c
@@ -32,8 +32,13 @@ void harts_early_init(void)
if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
- mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_IC_EN |
- MCACHE_CTL_DC_EN | MCACHE_CTL_CCTL_SUEN);
+ mcache_ctl_val |= (MCACHE_CTL_DC_COHEN | MCACHE_CTL_CCTL_SUEN |
\
+
+ if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF))
+ mcache_ctl |= MCACHE_CTL_IC_EN;
+
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) {
+ mcache_ctl |= MCACHE_CTL_DC_EN;
csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c
index 772c6bf1ee..bef9e3149e 100644
--- a/board/AndesTech/ae350/ae350.c
+++ b/board/AndesTech/ae350/ae350.c
@@ -102,7 +102,8 @@ void *board_fdt_blob_setup(int *err)
void spl_board_init()
{
/* enable v5l2 cache */
- enable_caches();
+ if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
+ enable_caches();
}
#endif
--
2.34.1
[PATCH 1/5] andes: csr.h: Clean up CSR definition
Signed-off-by: Leo Yu-Chi Liang --- arch/riscv/include/asm/arch-andes/csr.h | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 393d51c6dd..93aa8b2343 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -15,17 +15,14 @@ #define CSR_MARCHID 0xf12 #define CSR_MCCTLCOMMAND 0x7cc -#define MCACHE_CTL_IC_EN_OFFSET 0 -#define MCACHE_CTL_DC_EN_OFFSET 1 -#define MCACHE_CTL_CCTL_SUEN_OFFSET 8 -#define MCACHE_CTL_DC_COHEN_OFFSET 19 -#define MCACHE_CTL_DC_COHSTA_OFFSET 20 - -#define MCACHE_CTL_IC_EN BIT(MCACHE_CTL_IC_EN_OFFSET) -#define MCACHE_CTL_DC_EN BIT(MCACHE_CTL_DC_EN_OFFSET) -#define MCACHE_CTL_CCTL_SUEN BIT(MCACHE_CTL_CCTL_SUEN_OFFSET) -#define MCACHE_CTL_DC_COHEN BIT(MCACHE_CTL_DC_COHEN_OFFSET) -#define MCACHE_CTL_DC_COHSTA BIT(MCACHE_CTL_DC_COHSTA_OFFSET) +/* mcache_ctl register */ + +#define MCACHE_CTL_IC_EN BIT(0) +#define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_DC_COHENBIT(19) +#define MCACHE_CTL_DC_COHSTA BIT(20) + #define CCTL_L1D_WBINVAL_ALL 6 -- 2.34.1
[PATCH v2 2/2] riscv: ae350: Adjust the memory layout of ae350
Adjust the initial stack pointer address to 0x1000(256M) Signed-off-by: Leo Yu-Chi Liang --- Change v1 -> v2: * Modify the address from 0x100(16MB) to 0x1000(256MB) --- configs/ae350_rv32_spl_defconfig | 6 +++--- configs/ae350_rv32_spl_xip_defconfig | 6 +++--- configs/ae350_rv64_spl_defconfig | 6 +++--- configs/ae350_rv64_spl_xip_defconfig | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index e328308e097..f2fe276c5c8 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " @@ -12,8 +14,6 @@ CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index da8edf44d4c..4ed5e2cad99 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x8000 @@ -13,8 +15,6 @@ CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index 9c5018c4462..90dfc7d02ee 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " @@ -13,8 +15,6 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 CONFIG_SYS_MONITOR_BASE=0x8800 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index 9351deffa3b..f174638f692 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x8000 @@ -14,8 +16,6 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 CONFIG_SYS_MONITOR_BASE=0x8800 -- 2.38.0.68.ge85701b4af.dirty
[PATCH v2 1/2] riscv: Rename Andes cpu and board names
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Yu Chien Peter Lin
Reviewed-by: Rick Chen
---
arch/riscv/Kconfig | 8
arch/riscv/cpu/{ax25 => andesv5}/Kconfig | 0
arch/riscv/cpu/{ax25 => andesv5}/Makefile| 0
arch/riscv/cpu/{ax25 => andesv5}/cache.c | 0
arch/riscv/cpu/{ax25 => andesv5}/cpu.c | 0
arch/riscv/cpu/{ax25 => andesv5}/spl.c | 0
arch/riscv/dts/Makefile | 2 +-
board/AndesTech/{ax25-ae350 => ae350}/Kconfig| 8
.../AndesTech/{ax25-ae350 => ae350}/MAINTAINERS | 6 +++---
board/AndesTech/{ax25-ae350 => ae350}/Makefile | 2 +-
.../{ax25-ae350/ax25-ae350.c => ae350/ae350.c} | 0
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv32_spl_defconfig | 2 +-
configs/ae350_rv32_spl_xip_defconfig | 2 +-
configs/ae350_rv32_xip_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
configs/ae350_rv64_spl_defconfig | 2 +-
configs/ae350_rv64_spl_xip_defconfig | 2 +-
configs/ae350_rv64_xip_defconfig | 2 +-
.../AndesTech/{ax25-ae350.rst => ae350.rst} | 16
doc/board/AndesTech/index.rst| 2 +-
include/configs/{ax25-ae350.h => ae350.h}| 0
22 files changed, 30 insertions(+), 30 deletions(-)
rename arch/riscv/cpu/{ax25 => andesv5}/Kconfig (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/Makefile (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/cache.c (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/cpu.c (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/spl.c (100%)
rename board/AndesTech/{ax25-ae350 => ae350}/Kconfig (88%)
rename board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS (80%)
rename board/AndesTech/{ax25-ae350 => ae350}/Makefile (87%)
rename board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} (100%)
rename doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} (98%)
rename include/configs/{ax25-ae350.h => ae350.h} (100%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ebc4bef220e..48ca4ff4c4e 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,8 +8,8 @@ choice
prompt "Target select"
optional
-config TARGET_AX25_AE350
- bool "Support ax25-ae350"
+config TARGET_AE350
+ bool "Support ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
@@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF
Do not enable data cache in SPL.
# board-specific options below
-source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
@@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/andesv5/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
similarity index 100%
rename from arch/riscv/cpu/ax25/Kconfig
rename to arch/riscv/cpu/andesv5/Kconfig
diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile
similarity index 100%
rename from arch/riscv/cpu/ax25/Makefile
rename to arch/riscv/cpu/andesv5/Makefile
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/andesv5/cache.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cache.c
rename to arch/riscv/cpu/andesv5/cache.c
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cpu.c
rename to arch/riscv/cpu/andesv5/cpu.c
diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c
similarity index 100%
rename from arch/riscv/cpu/ax25/spl.c
rename to arch/riscv/cpu/andesv5/spl.c
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 5c15a0f303a..c576c55767f 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git
[V3,1/1] riscv: Increase the upper bound of NR_CPUS to 4095
From: Xiang W
The maximum hart number is 32 and is determined by
the type of gd->arch.available_harts. However, various
RISC-V specifications allow the hart number to be greater
than 32. We can eliminate this limitation through bitmaps.
The patch modifies the upper bound of the hart number to 4095,
which is also the maximum hart number RISC-V Advanced Core Local
Interruptor Specification gives.
Some defconfigs, (e.g. qemu-riscv32_smode_defconfig,
qemu-riscv64_smode_defconfig, openpiton_riscv64_defconfig, ...)
do not define CONFIG_NR_CPUS, and may result in compile error,
so define CONFIG_NR_CPUS to be 1 if CONFIG_NR_CPUS is not defined.
Tested on sifive unmatched.
Signed-off-by: Xiang W
Signed-off-by: Leo Yu-Chi Liang
---
Changes v2 -> v3:
- Fix the calculation of the GD_AVAILABLE_HARTS start address
- Fix compilation error for defconfigs that do not define CONFIG_NR_CPUS
---
arch/riscv/Kconfig | 4 ++--
arch/riscv/cpu/start.S | 20 +++-
arch/riscv/include/asm/global_data.h | 8 +++-
arch/riscv/lib/smp.c | 2 +-
4 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ebc4bef220..063734cbb9 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -232,8 +232,8 @@ config SPL_SMP
all, single processor machines.
config NR_CPUS
- int "Maximum number of CPUs (2-32)"
- range 2 32
+ int "Maximum number of CPUs (2-4095)"
+ range 2 4095
depends on SMP || SPL_SMP
default 8
help
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 4687bca3c9..ae19c2b43d 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -172,11 +172,21 @@ wait_for_gd_init:
bnezt1, 1b
/* register available harts in the available_harts mask */
- li t1, 1
- sll t1, t1, tp
- LREGt2, GD_AVAILABLE_HARTS(gp)
- or t2, t2, t1
- SREGt2, GD_AVAILABLE_HARTS(gp)
+ li t1, GD_AVAILABLE_HARTS
+ add t1, t1, gp
+#if defined(CONFIG_ARCH_RV64I)
+ srlit2, tp, 6
+ sllit2, t2, 3
+#elif defined(CONFIG_ARCH_RV32I)
+ srlit2, tp, 5
+ sllit2, t2, 2
+#endif
+ add t1, t1, t2
+ LREGt2, 0(t1)
+ li t3, 1
+ sll t3, t3, tp
+ or t2, t2, t3
+ SREGt2, 0(t1)
amoswap.w.rl zero, zero, 0(t0)
#endif
diff --git a/arch/riscv/include/asm/global_data.h
b/arch/riscv/include/asm/global_data.h
index 6fdc86dd8b..7e37e90db0 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -10,9 +10,15 @@
#ifndef__ASM_GBL_DATA_H
#define __ASM_GBL_DATA_H
+#include
#include
#include
#include
+#include
+
+#ifndef CONFIG_NR_CPUS
+#define CONFIG_NR_CPUS 1
+#endif
/* Architecture-specific global data */
struct arch_global_data {
@@ -29,7 +35,7 @@ struct arch_global_data {
#endif
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
- ulong available_harts;
+ ulong available_harts[BITS_TO_LONGS(CONFIG_NR_CPUS)];
#endif
#endif
};
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index 4f073a016f..511e3ed98d 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -48,7 +48,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
#if !CONFIG_IS_ENABLED(XIP)
#ifdef CONFIG_AVAILABLE_HARTS
/* skip if hart is not available */
- if (!(gd->arch.available_harts & (1 << reg)))
+ if (!test_bit(reg, gd->arch.available_harts))
continue;
#endif
#endif
--
2.38.0.68.ge85701b4af.dirty
[PATCH 2/2] riscv: ae350: Adjust the memory layout of ae350
Signed-off-by: Leo Yu-Chi Liang --- configs/ae350_rv32_spl_defconfig | 6 +++--- configs/ae350_rv32_spl_xip_defconfig | 6 +++--- configs/ae350_rv64_spl_defconfig | 6 +++--- configs/ae350_rv64_spl_xip_defconfig | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index d61f7f5d1d..fd9f100be3 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SYS_PROMPT="RISC-V # " @@ -12,8 +14,6 @@ CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index e59ba0c38a..16461e7bf9 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_32" CONFIG_SPL_TEXT_BASE=0x8000 @@ -13,8 +15,6 @@ CONFIG_TARGET_AE350=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00 CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig index cb69514a7e..c2793cd593 100644 --- a/configs/ae350_rv64_spl_defconfig +++ b/configs/ae350_rv64_spl_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SYS_PROMPT="RISC-V # " @@ -13,8 +15,6 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y # CONFIG_AVAILABLE_HARTS is not set CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x0020 CONFIG_SYS_MONITOR_BASE=0x8800 diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig index e0773fa0aa..bdc09d035d 100644 --- a/configs/ae350_rv64_spl_xip_defconfig +++ b/configs/ae350_rv64_spl_xip_defconfig @@ -1,7 +1,9 @@ CONFIG_RISCV=y -CONFIG_TEXT_BASE=0x0120 +CONFIG_TEXT_BASE=0x0180 CONFIG_SYS_MALLOC_LEN=0x8 CONFIG_NR_DRAM_BANKS=2 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100 CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_DEFAULT_DEVICE_TREE="ae350_64" CONFIG_SPL_TEXT_BASE=0x8000 @@ -14,8 +16,6 @@ CONFIG_ARCH_RV64I=y CONFIG_RISCV_SMODE=y CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x8001 CONFIG_SYS_MONITOR_BASE=0x8800 -- 2.38.0.68.ge85701b4af.dirty
[PATCH 1/2] riscv: Rename Andes cpu and board names
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/Kconfig | 8
arch/riscv/cpu/{ax25 => andesv5}/Kconfig | 0
arch/riscv/cpu/{ax25 => andesv5}/Makefile| 0
arch/riscv/cpu/{ax25 => andesv5}/cache.c | 0
arch/riscv/cpu/{ax25 => andesv5}/cpu.c | 0
arch/riscv/cpu/{ax25 => andesv5}/spl.c | 0
arch/riscv/dts/Makefile | 2 +-
board/AndesTech/{ax25-ae350 => ae350}/Kconfig| 8
.../AndesTech/{ax25-ae350 => ae350}/MAINTAINERS | 6 +++---
board/AndesTech/{ax25-ae350 => ae350}/Makefile | 2 +-
.../{ax25-ae350/ax25-ae350.c => ae350/ae350.c} | 0
configs/ae350_rv32_defconfig | 2 +-
configs/ae350_rv32_spl_defconfig | 2 +-
configs/ae350_rv32_spl_xip_defconfig | 2 +-
configs/ae350_rv32_xip_defconfig | 2 +-
configs/ae350_rv64_defconfig | 2 +-
configs/ae350_rv64_spl_defconfig | 2 +-
configs/ae350_rv64_spl_xip_defconfig | 2 +-
configs/ae350_rv64_xip_defconfig | 2 +-
.../AndesTech/{ax25-ae350.rst => ae350.rst} | 16
doc/board/AndesTech/index.rst| 2 +-
include/configs/{ax25-ae350.h => ae350.h}| 0
22 files changed, 30 insertions(+), 30 deletions(-)
rename arch/riscv/cpu/{ax25 => andesv5}/Kconfig (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/Makefile (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/cache.c (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/cpu.c (100%)
rename arch/riscv/cpu/{ax25 => andesv5}/spl.c (100%)
rename board/AndesTech/{ax25-ae350 => ae350}/Kconfig (88%)
rename board/AndesTech/{ax25-ae350 => ae350}/MAINTAINERS (80%)
rename board/AndesTech/{ax25-ae350 => ae350}/Makefile (87%)
rename board/AndesTech/{ax25-ae350/ax25-ae350.c => ae350/ae350.c} (100%)
rename doc/board/AndesTech/{ax25-ae350.rst => ae350.rst} (98%)
rename include/configs/{ax25-ae350.h => ae350.h} (100%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ebc4bef220..48ca4ff4c4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,8 +8,8 @@ choice
prompt "Target select"
optional
-config TARGET_AX25_AE350
- bool "Support ax25-ae350"
+config TARGET_AE350
+ bool "Support ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
@@ -58,7 +58,7 @@ config SPL_SYS_DCACHE_OFF
Do not enable data cache in SPL.
# board-specific options below
-source "board/AndesTech/ax25-ae350/Kconfig"
+source "board/AndesTech/ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
@@ -67,7 +67,7 @@ source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
-source "arch/riscv/cpu/ax25/Kconfig"
+source "arch/riscv/cpu/andesv5/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/andesv5/Kconfig
similarity index 100%
rename from arch/riscv/cpu/ax25/Kconfig
rename to arch/riscv/cpu/andesv5/Kconfig
diff --git a/arch/riscv/cpu/ax25/Makefile b/arch/riscv/cpu/andesv5/Makefile
similarity index 100%
rename from arch/riscv/cpu/ax25/Makefile
rename to arch/riscv/cpu/andesv5/Makefile
diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/andesv5/cache.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cache.c
rename to arch/riscv/cpu/andesv5/cache.c
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/andesv5/cpu.c
similarity index 100%
rename from arch/riscv/cpu/ax25/cpu.c
rename to arch/riscv/cpu/andesv5/cpu.c
diff --git a/arch/riscv/cpu/ax25/spl.c b/arch/riscv/cpu/andesv5/spl.c
similarity index 100%
rename from arch/riscv/cpu/ax25/spl.c
rename to arch/riscv/cpu/andesv5/spl.c
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 5c15a0f303..c576c55767 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ae350/Kc
[PATCH 1/1] riscv: ae350: Fix XIP config boot failure
The booting flow is SPL -> OpenSBI -> U-Boot.
The boot hart may change after OpenSBI and may not always be hart0,
so wrap the related branch instruction with M-MODE.
Current DTB setup for XIP is not valid.
There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used
in XIP mode, to be returned. Fix this.
Fixes: 2e8d2f88439d ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Rick Chen
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/start.S | 3 ++-
board/AndesTech/ax25-ae350/ax25-ae350.c | 17 +++--
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 76850ec9be..41c6f0858e 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -139,9 +139,10 @@ call_harts_early_init:
* accesses gd).
*/
mv gp, s0
+#if CONFIG_IS_ENABLED(RISCV_MMODE)
bneztp, secondary_hart_loop
#endif
-
+#endif
jal board_init_f_init_reserve
SREGs1, GD_FIRMWARE_FDT_ADDR(gp)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d6a4291379..36f0dd4b0f 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -54,17 +54,22 @@ ulong board_flash_get_legacy(ulong base, int banknum,
flash_info_t *info)
return 0;
}
+#define ANDES_HW_DTB_ADDRESS 0xF200
void *board_fdt_blob_setup(int *err)
{
*err = 0;
-#if defined(CONFIG_OF_BOARD)
- return (void *)(ulong)gd->arch.firmware_fdt_addr;
-#elif defined(CONFIG_OF_SEPARATE)
- return (void *)CONFIG_SYS_FDT_BASE;
-#else
+
+ if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
+ if (gd->arch.firmware_fdt_addr)
+ return (void *)(ulong)gd->arch.firmware_fdt_addr;
+ }
+
+ if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC)
+ return (void *)CONFIG_SYS_FDT_BASE;
+ return (void *)ANDES_HW_DTB_ADDRESS;
+
*err = -EINVAL;
return NULL;
-#endif
}
int smc_init(void)
--
2.34.1.390.g2ae0a9cb82
[PATCH v2, 1/1] riscv: Clean up asm/io.h
Clean up asm/io.h by
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa, mem_pci)
This massively improves the readability of the file.
Suggested by commits:
7ab2e47d27c9 ("arm: Clean up asm/io.h")
909d0399a519 ("ARM: asm/io.h: kill off confusing #ifdef __mem_pci block")
Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Bin Meng
---
arch/riscv/include/asm/io.h | 117 +---
1 file changed, 1 insertion(+), 116 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index fc39bb2c70..49bffac03c 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -7,8 +7,6 @@
#ifndef __ASM_RISCV_IO_H
#define __ASM_RISCV_IO_H
-#ifdef __KERNEL__
-
#include
#include
#include
@@ -39,11 +37,7 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
}
#endif
-/*
- * Generic virtual read/write. Note that we don't support half-word
- * read/writes. We define __arch_*[bl] here, and leave __arch_*w
- * to the architecture specific code.
- */
+/* Generic virtual read/write. */
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
@@ -352,115 +346,6 @@ static inline void writesl(unsigned int *addr, const void
*data, int longlen)
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
-/*
- * DMA-consistent mapping functions. These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices. This is the "generic" version. The PCI specific version
- * is in pci.h
- */
-
-/*
- * String version of IO memory access ops:
- */
-
-/*
- * If this architecture has PCI memory IO, then define the read/write
- * macros. These should only be used with the cookie passed from
- * ioremap.
- */
-#ifdef __mem_pci
-
-#define readb(c) ({ unsigned int __v = \
- __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = \
- le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = \
- le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
-
-#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
-#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
-#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
-
-#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
-#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
-#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
-
-#define eth_io_copy_and_sum(s, c, l, b) \
- eth_copy_and_sum((s), __mem_pci(c), (l), (b))
-
-static inline int check_signature(ulong io_addr, const uchar *s, int len)
-{
- int retval = 0;
-
- do {
- if (readb(io_addr) != *s)
- goto out;
- io_addr++;
- s++;
- len--;
- } while (len);
- retval = 1;
-out:
- return retval;
-}
-#endif /* __mem_pci */
-
-/*
- * If this architecture has ISA IO, then define the isa_read/isa_write
- * macros.
- */
-#ifdef __mem_isa
-
-#define isa_readb(addr)__raw_readb(__mem_isa(addr))
-#define isa_readw(addr)__raw_readw(__mem_isa(addr))
-#define isa_readl(addr)__raw_readl(__mem_isa(addr))
-#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
-#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
-#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
-#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
-#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
-#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
-
-#define isa_eth_io_copy_and_sum(a, b, c, d) \
- eth_copy_and_sum((a), __mem_isa(b), (c), (d))
-
-static inline int
-isa_check_signature(ulong io_addr, const uchar *s, int len)
-{
- int retval = 0;
-
- do {
- if (isa_readb(io_addr) != *s)
- goto out;
- io_addr++;
- s++;
- len--;
- } while (len);
- retval = 1;
-out:
- return retval;
-}
-
-#else /* __mem_isa */
-
-#define isa_readb(addr)(__readwrite_bug("isa_readb"),
0)
-#define isa_readw(addr)(__readwrite_bug("isa_readw"),
0)
-#define isa_readl(addr)(__readwrite_bug("isa_readl"),
0)
-#define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
-#define isa_writew(val, addr) __readwrite_bug("isa_writew"
[PATCH 1/1] riscv: Clean up asm/io.h
Clean up asm/io.h by
- removing commented code
- removing outdated comments
- removing unused definitions (for mem_isa, mem_pci)
Suggested by commits:
(7ab2e47d27) arm: Clean up asm/io.h
(909d0399a5) ARM: asm/io.h: kill off confusing #ifdef __mem_pci block
This massively improves the readability of the file.
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/include/asm/io.h | 117 +---
1 file changed, 1 insertion(+), 116 deletions(-)
diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index fc39bb2c70..49bffac03c 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -7,8 +7,6 @@
#ifndef __ASM_RISCV_IO_H
#define __ASM_RISCV_IO_H
-#ifdef __KERNEL__
-
#include
#include
#include
@@ -39,11 +37,7 @@ static inline phys_addr_t map_to_sysmem(const void *ptr)
}
#endif
-/*
- * Generic virtual read/write. Note that we don't support half-word
- * read/writes. We define __arch_*[bl] here, and leave __arch_*w
- * to the architecture specific code.
- */
+/* Generic virtual read/write. */
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
@@ -352,115 +346,6 @@ static inline void writesl(unsigned int *addr, const void
*data, int longlen)
#define insw_p(port, to, len) insw(port, to, len)
#define insl_p(port, to, len) insl(port, to, len)
-/*
- * DMA-consistent mapping functions. These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices. This is the "generic" version. The PCI specific version
- * is in pci.h
- */
-
-/*
- * String version of IO memory access ops:
- */
-
-/*
- * If this architecture has PCI memory IO, then define the read/write
- * macros. These should only be used with the cookie passed from
- * ioremap.
- */
-#ifdef __mem_pci
-
-#define readb(c) ({ unsigned int __v = \
- __raw_readb(__mem_pci(c)); __v; })
-#define readw(c) ({ unsigned int __v = \
- le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
-#define readl(c) ({ unsigned int __v = \
- le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
-
-#define writeb(v, c) __raw_writeb(v, __mem_pci(c))
-#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c))
-#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c))
-
-#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l))
-#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l))
-#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l))
-
-#define eth_io_copy_and_sum(s, c, l, b) \
- eth_copy_and_sum((s), __mem_pci(c), (l), (b))
-
-static inline int check_signature(ulong io_addr, const uchar *s, int len)
-{
- int retval = 0;
-
- do {
- if (readb(io_addr) != *s)
- goto out;
- io_addr++;
- s++;
- len--;
- } while (len);
- retval = 1;
-out:
- return retval;
-}
-#endif /* __mem_pci */
-
-/*
- * If this architecture has ISA IO, then define the isa_read/isa_write
- * macros.
- */
-#ifdef __mem_isa
-
-#define isa_readb(addr)__raw_readb(__mem_isa(addr))
-#define isa_readw(addr)__raw_readw(__mem_isa(addr))
-#define isa_readl(addr)__raw_readl(__mem_isa(addr))
-#define isa_writeb(val, addr) __raw_writeb(val, __mem_isa(addr))
-#define isa_writew(val, addr) __raw_writew(val, __mem_isa(addr))
-#define isa_writel(val, addr) __raw_writel(val, __mem_isa(addr))
-#define isa_memset_io(a, b, c) _memset_io(__mem_isa(a), (b), (c))
-#define isa_memcpy_fromio(a, b, c) _memcpy_fromio((a), __mem_isa(b), (c))
-#define isa_memcpy_toio(a, b, c) _memcpy_toio(__mem_isa((a)), (b), (c))
-
-#define isa_eth_io_copy_and_sum(a, b, c, d) \
- eth_copy_and_sum((a), __mem_isa(b), (c), (d))
-
-static inline int
-isa_check_signature(ulong io_addr, const uchar *s, int len)
-{
- int retval = 0;
-
- do {
- if (isa_readb(io_addr) != *s)
- goto out;
- io_addr++;
- s++;
- len--;
- } while (len);
- retval = 1;
-out:
- return retval;
-}
-
-#else /* __mem_isa */
-
-#define isa_readb(addr)(__readwrite_bug("isa_readb"),
0)
-#define isa_readw(addr)(__readwrite_bug("isa_readw"),
0)
-#define isa_readl(addr)(__readwrite_bug("isa_readl"),
0)
-#define isa_writeb(val, addr) __readwrite_bug("isa_writeb")
-#define isa_writew(val, addr) __readwrite_bug("isa_writew")
-#define isa_writel(val, addr)
[PATCH 1/1] board: ae350: Support autoboot from RAM
Add boot command "bootcmd_ram" to support autoboot from RAM.
This feature could be useful at the very initial state of chip design
when there is only a minimal set of peripheral. (e.g. without mmc and mac ..etc)
The kernel image is default to be loaded at 0x200 via debug port,
and the following script serves as an example:
spl()
{
cmd="riscv64-linux-gdb -q \
-ex \"target remote $host:$port\" \
-ex \"load\" \
-ex \"thread apply all set \\\$pc=&_start\" \
-ex \"thread apply all set \\\$a0=\\\$mhartid\" \
-ex \"thread apply all set \\\$a1=\" \
-ex \"restore u-boot.itb binary 0x20\" \
-ex \"restore Image binary 0x200\" \
-ex \"c\" \
spl/u-boot-spl
"
echo $cmd
eval $cmd
}
The address where the kernel is loaded can be altered by
changing the value of KERNEL_IMAGE_ADDR.
Signed-off-by: Leo Yu-Chi Liang
---
include/configs/ax25-ae350.h | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index bf3f34e428..1c3f957d32 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -119,12 +119,23 @@
/* Increase max gunzip size */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
+/* Support autoboot from RAM (kernel image is loaded via debug port) */
+#define KERNEL_IMAGE_ADDR "0x200 "
+#define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \
+ "ram "
+#define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \
+ "bootcmd_ram=" \
+ "booti " \
+ KERNEL_IMAGE_ADDR \
+ "- $fdtcontroladdr\0"
+
/* When we use RAM as ENV */
/* Enable distro boot */
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
- func(DHCP, dhcp, na)
+ func(DHCP, dhcp, na) \
+ func(RAM, ram, na)
#include
#define CONFIG_EXTRA_ENV_SETTINGS \
--
2.17.0
[PATCH v2] riscv: ae350: Use #if defined instead of CONFIG_IS_ENABLED
According to ./include/linux/kconfig.h,
CONFIG_IS_ENABLED(OF_BOARD) expands to 0
when CONFIG_SPL_BUILD is defined because
there is no CONFIG_SPL_OF_BOARD.
Use #if defined instead.
Fixes: 2e8d2f88439d ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards")
Signed-off-by: Leo Yu-Chi Liang
Reviewed-by: Rick Chen
Reviewed-by: Bin Meng
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index b28894ed46..58bf236497 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -56,9 +56,9 @@ ulong board_flash_get_legacy(ulong base, int banknum,
flash_info_t *info)
void *board_fdt_blob_setup(void)
{
-#if CONFIG_IS_ENABLED(OF_BOARD)
+#if defined(CONFIG_OF_BOARD)
return (void *)(ulong)gd->arch.firmware_fdt_addr;
-#elif CONFIG_IS_ENABLED(OF_SEPARATE)
+#elif defined(CONFIG_OF_SEPARATE)
return (void *)CONFIG_SYS_FDT_BASE;
#else
return NULL;
--
2.17.0
[PATCH] Fix syntax error
This statement has an unmatched parentheses, fix it.
Signed-off-by: Leo Yu-Chi Liang
---
common/image-board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/image-board.c b/common/image-board.c
index e7660352e9..ddf30c6730 100644
--- a/common/image-board.c
+++ b/common/image-board.c
@@ -898,7 +898,7 @@ int boot_get_kbd(struct lmb *lmb, struct bd_info **kbd)
debug("## kernel board info at 0x%08lx\n", (ulong)*kbd);
#if defined(DEBUG)
- if (IS_ENABLED(CONFIG_CMD_BDI)
+ if (IS_ENABLED(CONFIG_CMD_BDI))
do_bdinfo(NULL, 0, 0, NULL);
#endif
--
2.17.0
[PATCH] riscv: ae350: Use #if defined instead of CONFIG_IS_ENABLED
According to ./include/linux/kconfig.h,
CONFIG_IS_ENABLED(OF_BOARD) expands to 0
when CONFIG_SPL_BUILD is defined because
there is no CONFIG_SPL_OF_BOARD.
Use #if defined instead.
Signed-off-by: Leo Yu-Chi Liang
---
board/AndesTech/ax25-ae350/ax25-ae350.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index b28894ed46..58bf236497 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -56,9 +56,9 @@ ulong board_flash_get_legacy(ulong base, int banknum,
flash_info_t *info)
void *board_fdt_blob_setup(void)
{
-#if CONFIG_IS_ENABLED(OF_BOARD)
+#if defined(CONFIG_OF_BOARD)
return (void *)(ulong)gd->arch.firmware_fdt_addr;
-#elif CONFIG_IS_ENABLED(OF_SEPARATE)
+#elif defined(CONFIG_OF_SEPARATE)
return (void *)CONFIG_SYS_FDT_BASE;
#else
return NULL;
--
2.17.0
[PATCH 1/1] riscv: ae350: enable Coherence Manager for ae350
If Coherence Manager were not set in the beginning,
u-boot-spl would sometimes fail to boot to u-boot proper.
Enable CM and I/D cache at the same time in harts_early_init
Signed-off-by: Leo Yu-Chi Liang
---
arch/riscv/cpu/ax25/cpu.c | 42 +++
1 file changed, 42 insertions(+)
diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index f092600e14..c4c2de2ef0 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -9,6 +9,22 @@
#include
#include
#include
+#include
+
+#define CSR_MCACHE_CTL 0x7ca
+#define CSR_MMISC_CTL 0x7d0
+#define CSR_MARCHID0xf12
+
+#define V5_MCACHE_CTL_IC_EN_OFFSET 0
+#define V5_MCACHE_CTL_DC_EN_OFFSET 1
+#define V5_MCACHE_CTL_DC_COHEN_OFFSET 19
+#define V5_MCACHE_CTL_DC_COHSTA_OFFSET 20
+
+#define V5_MCACHE_CTL_IC_ENBIT(V5_MCACHE_CTL_IC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_EN
BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHEN_EN BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
+#define V5_MCACHE_CTL_DC_COHSTA_EN BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
+
/*
* cleanup_before_linux() is called just before we call linux
@@ -27,3 +43,29 @@ int cleanup_before_linux(void)
return 0;
}
+
+void harts_early_init(void)
+{
+ if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
+ unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
+ if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
+ mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
+ csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
+
+ /*
+* Check DC_COHEN_EN, if cannot write to mcache_ctl,
+* we assume this bitmap not support L2 CM
+*/
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
+ /* Wait for DC_COHSTA bit be set */
+ while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
+ mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
+ }
+ }
+}
--
2.17.0
[PATCH 1/1] riscv: Fix linking error when building u-boot-spl with no SMP support
Switch off SMP support when building u-boot-spl would cause linking error as follow: undefined reference to 'secondary hart relocate' and 'smp_call_function'. Add macro to wrap up proper code region that needs SMP configuration on. Signed-off by: Leo Liang Cc: r...@andestech.com --- arch/riscv/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5f1c220..e3222b1 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -191,6 +191,7 @@ spl_stack_gd_setup: mv sp, s0 #endif +#if CONFIG_IS_ENABLED(SMP) /* set new stack and global data pointer on secondary harts */ spl_secondary_hart_stack_gd_setup: la a0, secondary_hart_relocate @@ -205,6 +206,7 @@ spl_secondary_hart_stack_gd_setup: la a0, secondary_harts_relocation_error jal printf jal hang +#endif /* set new global data pointer on main hart */ 1: mv gp, s0 -- 2.7.4
