[PATCH] lx2162a : Rename emmc boot command variable
From: Meenakshi Aggarwal
Rename emmc_bootcmd environment variable to sd2_bootcmd
to fix emmc boot on lx2162aqds board.
Signed-off-by: Meenakshi Aggarwal
---
include/configs/lx2162aqds.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h
index 847534c550..d2145db6f1 100644
--- a/include/configs/lx2162aqds.h
+++ b/include/configs/lx2162aqds.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
*/
#ifndef __LX2162_QDS_H
@@ -65,7 +65,7 @@ u8 qixis_esdhc_detect_quirk(void);
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0" \
- "emmc_bootcmd=echo Trying load from emmc card..;" \
+ "sd2_bootcmd=echo Trying load from emmc card..;"\
"mmc dev 1; mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
--
2.25.1
RE: [PATCH v4 0/3] Add support for LX2162AQDS board
HI, Any review comment on this patch series? Thanks, Meenakshi > -Original Message- > From: Meenakshi Aggarwal > Sent: Thursday, October 29, 2020 7:17 PM > To: u-boot@lists.denx.de; tr...@konsulko.com; Priyanka Jain > > Cc: Varun Sethi ; Meenakshi Aggarwal > > Subject: [PATCH v4 0/3] Add support for LX2162AQDS board > > From: Meenakshi Aggarwal > > This patch set add support for LX2162AQDS board. > LX2162A is a variant of LX2160A. > > --- > Changes: > v2: > - Add Separate ARCH for LX2162A SoC > - Updated ReadMe of SoC and board > > v3: > - Fix compilation bug for ls1088 introduced > with lx2162 changes > > v4: > - Remove non-config options from config file > > > *** BLURB HERE *** > > Meenakshi Aggarwal (3): > drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig > armv8: lx2162a: Add Soc changes to support LX2162A > armv8: lx2162aqds: Add support for LX2162AQDS platform > > arch/arm/Kconfig | 12 + > arch/arm/cpu/armv8/Kconfig | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +- > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 + > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 7 +- > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ > .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +- > .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 4 +- > arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +- > arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 +- > arch/arm/dts/Makefile | 6 +- > arch/arm/dts/fsl-lx2160a-qds.dts | 3 - > arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- > arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + > arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + > arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + > arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ > arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ > arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + > arch/arm/dts/fsl-lx2162a-qds.dts | 34 + > arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +- > arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- > .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 +- > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +- > .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 +- > board/freescale/common/qixis.h | 25 + > board/freescale/common/vid.c | 3 +- > board/freescale/common/vid.h | 31 + > board/freescale/lx2160a/Kconfig| 16 + > board/freescale/lx2160a/MAINTAINERS| 26 + > board/freescale/lx2160a/Makefile | 1 + > board/freescale/lx2160a/README | 132 +++ > board/freescale/lx2160a/eth_lx2160ardb.c | 3 +- > board/freescale/lx2160a/eth_lx2162aqds.c | 974 > + > board/freescale/lx2160a/lx2160a.c | 43 +- > board/freescale/lx2160a/lx2160a.h | 61 ++ > configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + > configs/lx2160aqds_tfa_defconfig | 1 + > configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + > configs/lx2160ardb_tfa_defconfig | 1 + > configs/lx2160ardb_tfa_stmm_defconfig | 1 + > configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 98 +++ > configs/lx2162aqds_tfa_defconfig | 96 ++ > configs/lx2162aqds_tfa_verified_boot_defconfig | 103 +++ > drivers/ddr/fsl/Kconfig| 1 + > drivers/net/fsl-mc/Kconfig | 4 +- > drivers/net/ldpaa_eth/Makefile | 1 + > drivers/net/phy/Kconfig| 9 + > drivers/net/phy/cortina.c | 8 +- > drivers/pci/Kconfig| 4 +- > drivers/pci/pcie_layerscape_ep.c | 4 +- > drivers/pci/pcie_layerscape_fixup_common.c | 7 +- > include/configs/lx2160a_common.h | 2 + > include/configs/lx2160aqds.h | 76 -- > include/configs/lx2160ardb.h | 50 -- > include/configs/lx2162aqds.h | 78 ++ > 56 files changed, 2127 insertions(+), 198 deletions(-) create mode 100644 > arch/arm/dts/fsl-lx2162a-qds-17-x.dts > create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts > create mode 100644 arch/arm/dts/
RE: [PATCH v4 3/3] armv8: lx2162aqds: Add support for LX2162AQDS platform
Any comments? > -Original Message- > From: Meenakshi Aggarwal > Sent: Thursday, October 29, 2020 7:16 PM > To: u-boot@lists.denx.de; tr...@konsulko.com; Priyanka Jain > > Cc: Varun Sethi ; Meenakshi Aggarwal > ; Ioana Ciornei ; > Qiang Zhao ; Hui Song ; Manish > Tomar ; Vikas Singh > Subject: [PATCH v4 3/3] armv8: lx2162aqds: Add support for LX2162AQDS > platform > > From: Meenakshi Aggarwal > > This patch add base support for LX2162AQDS board. > LX2162AQDS board supports LX2162A family SoCs. > This patch add basic support of platform. > > Signed-off-by: Ioana Ciornei > Signed-off-by: Zhao Qiang > Signed-off-by: hui.song > Signed-off-by: Manish Tomar > Signed-off-by: Vikas Singh > Signed-off-by: Meenakshi Aggarwal > --- > arch/arm/Kconfig | 12 + > arch/arm/dts/Makefile | 6 +- > arch/arm/dts/fsl-lx2160a-qds.dts | 3 - > arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- > arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + > arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + > arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + > arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ > arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ > arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + > arch/arm/dts/fsl-lx2162a-qds.dts | 34 + > board/freescale/common/qixis.h | 25 + > board/freescale/common/vid.h | 31 + > board/freescale/lx2160a/Kconfig| 16 + > board/freescale/lx2160a/MAINTAINERS| 26 + > board/freescale/lx2160a/Makefile | 1 + > board/freescale/lx2160a/README | 132 > board/freescale/lx2160a/eth_lx2160ardb.c | 3 +- > board/freescale/lx2160a/eth_lx2162aqds.c | 974 > + > board/freescale/lx2160a/lx2160a.c | 43 +- > board/freescale/lx2160a/lx2160a.h | 61 ++ > configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 98 +++ > configs/lx2162aqds_tfa_defconfig | 96 +++ > configs/lx2162aqds_tfa_verified_boot_defconfig | 103 +++ > include/configs/lx2160a_common.h | 2 + > include/configs/lx2160aqds.h | 75 -- > include/configs/lx2160ardb.h | 49 -- > include/configs/lx2162aqds.h | 78 ++ > 28 files changed, 1936 insertions(+), 150 deletions(-) > create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts > create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts > create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts > create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi > create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi > create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi > create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts > create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c > create mode 100644 board/freescale/lx2160a/lx2160a.h > create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig > create mode 100644 configs/lx2162aqds_tfa_defconfig > create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig > create mode 100644 include/configs/lx2162aqds.h > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 80f0960..e055bd6 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS > is a high-performance development platform that supports the > QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. > > +config TARGET_LX2162AQDS > + bool "Support lx2162aqds" > + select ARCH_LX2162A > + select ARCH_MISC_INIT > + select ARM64 > + select ARMV8_MULTIENTRY > + select ARCH_SUPPORT_TFABOOT > + select BOARD_LATE_INIT > + help > + Support for NXP LX2162AQDS platform. > + The lx2162aqds support is based on LX2160A Layerscape Architecture > processor. > + > config TARGET_HIKEY > bool "Support HiKey 96boards Consumer Edition Platform" > select ARM64 > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile > index b195723..fc138a1 100644 > --- a/arch/arm/dts/Makefile > +++ b/arch/arm/dts/Makefile > @@ -411,7 +411,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ > fsl-lx2160a-qds-19-x-x.dtb \ > fsl-lx2160a-qds-19-11-x.dtb \ > fsl-lx2160a-qds-20-x-x.dtb \ > - fsl-lx2160a-qds-20-11-x.dtb > + fsl-lx2160a-qds-20-11-x.dtb \ > + fsl-lx2162a-qds.dtb\ > + fsl-lx2162a-qds-17-x.dtb\ > + fsl-lx2162a-qds-18-x.dtb\ > + fsl-lx2162a-qds-20-x.dtb
RE: [PATCH v4 2/3] armv8: lx2162a: Add Soc changes to support LX2162A
> -Original Message- > From: Tom Rini > Sent: Thursday, October 29, 2020 8:14 PM > To: Meenakshi Aggarwal > Cc: u-boot@lists.denx.de; Priyanka Jain ; Varun Sethi > > Subject: Re: [PATCH v4 2/3] armv8: lx2162a: Add Soc changes to support > LX2162A > > On Thu, Oct 29, 2020 at 07:16:16PM +0530, meenakshi.aggar...@nxp.com > wrote: > > > From: Meenakshi Aggarwal > > > > LX2162 is LX2160 based SoC, it has same die as of LX2160 with > > different packaging. > > > > LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, > > microSD card, eMMC support, serial console, qspi nor flash, qsgmii, > > sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes > > interface to support three PCIe gen3 interface. > > > > Signed-off-by: Meenakshi Aggarwal > > --- > > arch/arm/cpu/armv8/Kconfig | 2 +- > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +-- > > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++ > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 7 ++- > > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 > ++ > > A follow up to convert README.soc to rST and move it with the rest of our rST > documentation would be appreciated, thanks. [Meenakshi Aggarwal] We are planning this, but will be in a separate patch. > > -- > Tom
[PATCH v4 1/3] drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig
From: Meenakshi Aggarwal
Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can
be controlled via defconfig files.
Signed-off-by: Meenakshi Aggarwal
---
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 +
configs/lx2160aqds_tfa_defconfig | 1 +
configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 +
configs/lx2160ardb_tfa_defconfig | 1 +
configs/lx2160ardb_tfa_stmm_defconfig| 1 +
drivers/net/phy/Kconfig | 9 +
drivers/net/phy/cortina.c| 8
include/configs/lx2160aqds.h | 1 -
include/configs/lx2160ardb.h | 1 -
9 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 461d719..c90a7e2 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index 6dde093..900316b 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index 159ae9d..f7b2261 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -52,6 +52,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 8a4e6ef..388160e 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -59,6 +59,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig
b/configs/lx2160ardb_tfa_stmm_defconfig
index bd9c1e9..0767fca 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_CORTINA=y
+CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 4e1a93b..51733dd 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -100,6 +100,15 @@ config PHY_BROADCOM
config PHY_CORTINA
bool "Cortina Ethernet PHYs support"
+config SYS_CORTINA_NO_FW_UPLOAD
+ bool "Cortina firmware loading support"
+ default n
+ depends on PHY_CORTINA
+ help
+ Cortina phy has provision to store phy firmware in attached
dedicated
+ EEPROM. And boards designed with such EEPROM does not require
firmware
+ upload.
+
choice
prompt "Location of the Cortina firmware"
default SYS_CORTINA_FW_IN_NOR
diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c
index dbc20b1..b381a43 100644
--- a/drivers/net/phy/cortina.c
+++ b/drivers/net/phy/cortina.c
@@ -3,7 +3,7 @@
* Cortina CS4315/CS4340 10G PHY drivers
*
* Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
*
*/
@@ -29,7 +29,7 @@
#error The Cortina PHY needs 10G support
#endif
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
struct cortina_reg_config cortina_reg_cfg[] = {
/* CS4315_enable_sr_mode */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
@@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
int cs4340_phy_init(struct phy_device *phydev)
{
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
int timeout = 100; /* 100ms */
#endif
int reg_value;
@@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev)
* Boards designed with EEPROM attached to Cortina
* does not require FW upload.
*/
-#ifndef CORTINA_NO_FW_UPLOAD
+#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
/* step1: BIST test */
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x);
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 1cc015c..12884bc 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -93,7 +93,6 @@ u8 qixis_esdhc_detect_quirk(void);
#define AQ_PHY_ADDR3
[PATCH v4 2/3] armv8: lx2162a: Add Soc changes to support LX2162A
From: Meenakshi Aggarwal LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal --- arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +-- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 7 ++- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +-- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 4 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 ++- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 ++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +-- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++--- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 ++- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 ++-- board/freescale/common/vid.c | 3 +- drivers/ddr/fsl/Kconfig| 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/pci/Kconfig| 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 ++- 21 files changed, 173 insertions(+), 42 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3655990..f247441 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -115,7 +115,7 @@ config PSCI_RESET !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ - !TARGET_LX2160AQDS && \ + !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index be51b7d..4d46587 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -208,6 +208,35 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2162A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config ARCH_LX2160A bool select ARMV8_SET_SMPEN @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106 help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar - to erratum A-009007, but this one is for LX2160A, + to erratum A-009007, but this one is for LX2160A and LX2162A, and the register value is different. config SYS_FSL_ERRATUM_A010315 @@ -362,6 +391,7 @@ config MAX_CPUS default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A default 16 if ARCH_LX2160A + default 16 if ARCH_LX2162A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A default 4 if ARCH_LX2160A + default 4 if ARCH_LX2162A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV default 4 if ARCH_LS1012A
[PATCH v4 3/3] armv8: lx2162aqds: Add support for LX2162AQDS platform
From: Meenakshi Aggarwal
This patch add base support for LX2162AQDS board.
LX2162AQDS board supports LX2162A family SoCs.
This patch add basic support of platform.
Signed-off-by: Ioana Ciornei
Signed-off-by: Zhao Qiang
Signed-off-by: hui.song
Signed-off-by: Manish Tomar
Signed-off-by: Vikas Singh
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/Kconfig | 12 +
arch/arm/dts/Makefile | 6 +-
arch/arm/dts/fsl-lx2160a-qds.dts | 3 -
arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +-
arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 +
arch/arm/dts/fsl-lx2162a-qds.dts | 34 +
board/freescale/common/qixis.h | 25 +
board/freescale/common/vid.h | 31 +
board/freescale/lx2160a/Kconfig| 16 +
board/freescale/lx2160a/MAINTAINERS| 26 +
board/freescale/lx2160a/Makefile | 1 +
board/freescale/lx2160a/README | 132
board/freescale/lx2160a/eth_lx2160ardb.c | 3 +-
board/freescale/lx2160a/eth_lx2162aqds.c | 974 +
board/freescale/lx2160a/lx2160a.c | 43 +-
board/freescale/lx2160a/lx2160a.h | 61 ++
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 98 +++
configs/lx2162aqds_tfa_defconfig | 96 +++
configs/lx2162aqds_tfa_verified_boot_defconfig | 103 +++
include/configs/lx2160a_common.h | 2 +
include/configs/lx2160aqds.h | 75 --
include/configs/lx2160ardb.h | 49 --
include/configs/lx2162aqds.h | 78 ++
28 files changed, 1936 insertions(+), 150 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts
create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c
create mode 100644 board/freescale/lx2160a/lx2160a.h
create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/lx2162aqds_tfa_defconfig
create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig
create mode 100644 include/configs/lx2162aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80f0960..e055bd6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2162AQDS
+ bool "Support lx2162aqds"
+ select ARCH_LX2162A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2162AQDS platform.
+ The lx2162aqds support is based on LX2160A Layerscape Architecture
processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b195723..fc138a1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -411,7 +411,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2160a-qds-19-x-x.dtb \
fsl-lx2160a-qds-19-11-x.dtb \
fsl-lx2160a-qds-20-x-x.dtb \
- fsl-lx2160a-qds-20-11-x.dtb
+ fsl-lx2160a-qds-20-11-x.dtb \
+ fsl-lx2162a-qds.dtb\
+ fsl-lx2162a-qds-17-x.dtb\
+ fsl-lx2162a-qds-18-x.dtb\
+ fsl-lx2162a-qds-20-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts
index e0f5d5e..332c778 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@@ -13,7 +13,4 @@
/ {
model = "NXP Layerscape LX2160AQDS Board";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
- aliases {
- spi0 =
- };
};
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi
b/arch/arm/dts/fsl-lx2160a-qds.dtsi
index 96c9800..288607c 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -2,12 +2,18 @@
/*
* NXP LX2160AQDS common device tree source
*
- * Copyright 2018-2019 NXP
+ * Copyright 20
[PATCH v4 0/3] Add support for LX2162AQDS board
From: Meenakshi Aggarwal This patch set add support for LX2162AQDS board. LX2162A is a variant of LX2160A. --- Changes: v2: - Add Separate ARCH for LX2162A SoC - Updated ReadMe of SoC and board v3: - Fix compilation bug for ls1088 introduced with lx2162 changes v4: - Remove non-config options from config file *** BLURB HERE *** Meenakshi Aggarwal (3): drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig armv8: lx2162a: Add Soc changes to support LX2162A armv8: lx2162aqds: Add support for LX2162AQDS platform arch/arm/Kconfig | 12 + arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 7 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +- .../arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 4 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/fsl-lx2160a-qds.dts | 3 - arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + arch/arm/dts/fsl-lx2162a-qds.dts | 34 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 +- board/freescale/common/qixis.h | 25 + board/freescale/common/vid.c | 3 +- board/freescale/common/vid.h | 31 + board/freescale/lx2160a/Kconfig| 16 + board/freescale/lx2160a/MAINTAINERS| 26 + board/freescale/lx2160a/Makefile | 1 + board/freescale/lx2160a/README | 132 +++ board/freescale/lx2160a/eth_lx2160ardb.c | 3 +- board/freescale/lx2160a/eth_lx2162aqds.c | 974 + board/freescale/lx2160a/lx2160a.c | 43 +- board/freescale/lx2160a/lx2160a.h | 61 ++ configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 98 +++ configs/lx2162aqds_tfa_defconfig | 96 ++ configs/lx2162aqds_tfa_verified_boot_defconfig | 103 +++ drivers/ddr/fsl/Kconfig| 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/net/phy/Kconfig| 9 + drivers/net/phy/cortina.c | 8 +- drivers/pci/Kconfig| 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 +- include/configs/lx2160a_common.h | 2 + include/configs/lx2160aqds.h | 76 -- include/configs/lx2160ardb.h | 50 -- include/configs/lx2162aqds.h | 78 ++ 56 files changed, 2127 insertions(+), 198 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c create mode 100644 board/freescale/lx2160a/lx2160a.h create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/lx2162aqds_tfa_defconfig create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig create mode 100644 include/configs/lx2162aqds.h -- 2.7.4
RE: [PATCH] arm: fsl: common: Improve NXP VID driver PMBus support
> -Original Message- > From: Priyanka Jain (OSS) > Sent: Friday, October 23, 2020 11:54 AM > To: Stephen Carlson ; U-Boot Mailing List b...@lists.denx.de>; Meenakshi Aggarwal > Subject: RE: [PATCH] arm: fsl: common: Improve NXP VID driver PMBus support > > >-Original Message- > >From: U-Boot On Behalf Of Stephen > >Carlson > >Sent: Wednesday, August 19, 2020 12:00 AM > >To: U-Boot Mailing List > >Cc: Prabhakar Kushwaha ; Priyanka Jain > >; Sudhanshu Gupta > >Subject: [PATCH] arm: fsl: common: Improve NXP VID driver PMBus support > > > >[Resending as mailer dropped the Cc recipients] > > > >This patch adds support for more PMBus compatible devices to the NXP > >drivers for its QorIQ family devices. At runtime, the voltage regulator > >is queried over I2C, and the required voltage multiplier determined. > >This change supports the DIRECT and LINEAR PMBus voltage reporting modes. > > > >Previously, the driver only supported a few specific devices such as > >the > >IR36021 and LTC3882, so this change allows the QorIQ series to be used > >with a much larger variety of core voltage regulator devices. > > > >checkpatch warning "Use if (IS_DEFINED (...))" was ignored to maintain > >consistency with the existing code. > > > >Signed-off-by: Stephen Carlson > >--- > > board/freescale/common/Kconfig| 27 +- > > board/freescale/common/vid.c | 784 -- > > board/freescale/common/vid.h | 14 +- > > board/freescale/ls1028a/ls1028a.c | 42 ++ > > board/freescale/ls1088a/ls1088a.c | 40 ++ > > board/freescale/ls2080a/ls2080a.c | 49 ++ > > board/freescale/lx2160a/lx2160a.c | 42 ++ > > include/configs/ls1088aqds.h | 6 - > > include/configs/ls1088ardb.h | 8 +- > > 9 files changed, 521 insertions(+), 491 deletions(-) > > > >diff --git a/board/freescale/common/Kconfig > >b/board/freescale/common/Kconfig index 1b1fd69cb2..17db755951 100644 > >--- a/board/freescale/common/Kconfig > >+++ b/board/freescale/common/Kconfig > >@@ -21,18 +21,37 @@ config CMD_ESBC_VALIDATE > > esbc_validate - validate signature using RSA verification > > esbc_halt - put the core in spin loop (Secure Boot Only) > > > >+config VID > >+depends on DM_I2C > >+bool "Enable Freescale VID" > >+help > >+ This option enables setting core voltage based on individual > >+ values saved in SoC fuses. > >+ > > config VOL_MONITOR_LTC3882_READ > > depends on VID > > bool "Enable the LTC3882 voltage monitor read" > >-default n > > help > > This option enables LTC3882 voltage monitor read > >- functionality. It is used by common VID driver. > >+ functionality. It is used by the common VID driver. > > > > config VOL_MONITOR_LTC3882_SET > > depends on VID > > bool "Enable the LTC3882 voltage monitor set" > >-default n > > help > > This option enables LTC3882 voltage monitor set > >- functionality. It is used by common VID driver. > >+ functionality. It is used by the common VID driver. > >+ > >+config VOL_MONITOR_ISL68233_READ > >+depends on VID > >+bool "Enable the ISL68233 voltage monitor read" > >+help > >+ This option enables ISL68233 voltage monitor read > >+ functionality. It is used by the common VID driver. > >+ > >+config VOL_MONITOR_ISL68233_SET > >+depends on VID > >+bool "Enable the ISL68233 voltage monitor set" > >+help > >+ This option enables ISL68233 voltage monitor set > >+ functionality. It is used by the common VID driver. > >diff --git a/board/freescale/common/vid.c > >b/board/freescale/common/vid.c index ed0d9b471c..24f4d7c7b1 100644 > >--- a/board/freescale/common/vid.c > >+++ b/board/freescale/common/vid.c > >@@ -1,6 +1,8 @@ > > // SPDX-License-Identifier: GPL-2.0+ > > /* > > * Copyright 2014 Freescale Semiconductor, Inc. > >+ * > >+ * Copyright 2020 Stephen Carlson > > */ > > > > #include > >@@ -20,14 +22,22 @@ > > #include > > #include "vid.h" > > > >+/* Voltages are generally handled in mV to keep them as integers */ > >+#define MV_PER_V 1000 > >+ > >+/* > >+ * Select the channel on the I2C mux (on some NXP boards) that > >+contains > >+ * the voltage regulator to use for VID. Return 0 for
[PATCH] armv8: lx2160a: fix reset sequence
From: Meenakshi Aggarwal
Make sure that SW_RST_REQ and RST_REQ_MSK are cleared
before triggering hardware reset request.
Signed-off-by: Thirupathaiah Annapureddy
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8a2f404..e610528 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@@ -1229,13 +1229,15 @@ __efi_runtime_data u32 __iomem *rstcr = (u32
*)CONFIG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(ulong addr)
{
- u32 val;
-
#ifdef CONFIG_ARCH_LX2160A
- val = in_le32(rstcr);
- val |= 0x01;
- out_le32(rstcr, val);
+ /* clear the RST_REQ_MSK and SW_RST_REQ */
+ out_le32(rstcr, 0x0);
+
+ /* initiate the sw reset request */
+ out_le32(rstcr, 0x1);
#else
+ u32 val;
+
/* Raise RESET_REQ_B */
val = scfg_in32(rstcr);
val |= 0x02;
--
2.7.4
RE: [PATCH v3 2/2] armv8: lx2162aqds: Add support for LX2162AQDS platform
> -Original Message- > From: Tom Rini > Sent: Monday, September 7, 2020 6:43 PM > To: Meenakshi Aggarwal > Cc: u-boot@lists.denx.de; Priyanka Jain ; Varun Sethi > ; Ioana Ciornei ; Qiang Zhao > ; Hui Song ; Manish Tomar > ; Vikas Singh > Subject: Re: [PATCH v3 2/2] armv8: lx2162aqds: Add support for LX2162AQDS > platform > > On Mon, Sep 07, 2020 at 03:42:07PM +0530, meenakshi.aggar...@nxp.com > wrote: > > > From: Meenakshi Aggarwal > > > > This patch add base support for LX2162AQDS board. > > LX2162AQDS board supports LX2162A family SoCs. > > This patch add basic support of platform. > > > > Signed-off-by: Ioana Ciornei > > Signed-off-by: Zhao Qiang > > Signed-off-by: hui.song > > Signed-off-by: Manish Tomar > > Signed-off-by: Vikas Singh > > Signed-off-by: Meenakshi Aggarwal > > --- > > arch/arm/Kconfig | 12 + > > arch/arm/dts/Makefile | 6 +- > > arch/arm/dts/fsl-lx2160a-qds.dts | 3 - > > arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- > > arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + > > arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + > > arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + > > arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ > > arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ > > arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + > > arch/arm/dts/fsl-lx2162a-qds.dts | 34 + > > Most of these new dts* files are not added to MAINTAINERS entries and it > would be good to do so. [Meenakshi Aggarwal] Will add in next version > > > board/freescale/common/vid.c | 3 +- > > board/freescale/lx2160a/Kconfig| 16 + > > board/freescale/lx2160a/MAINTAINERS | 10 + > > board/freescale/lx2160a/Makefile | 1 + > > board/freescale/lx2160a/README | 132 > > This README also should get updated to rST and moved. [Meenakshi Aggarwal] OK, will plan it > > [snip] > > +/* > > + * Need to override existing (lx2160a) with lx2162aqds so > > +set_board_info will > > + * use proper prefix when creating full board_name (SYS_BOARD + type) > > +*/ #undef CONFIG_SYS_BOARD > > +#define CONFIG_SYS_BOARD"lx2162aqds" > > SYS_BOARD is under Kconfig, please just fix it there. [Meenakshi Aggarwal] LX2162 uses same die as of LX2160 so we are re-using LX2160 code. I have added SYS_BOARD (=lx2160a) in Kconfig but I will have to reassign(=lx2162a) it here else in environment variable it will show as lx2160. > > > + > > +#undef CONFIG_SYS_NXP_SRDS_3 > > + > > +/* Qixis */ > > +#define QIXIS_XMAP_MASK0x07 > > This is the start of adding tons of non-CONFIG information to the config > header. > Don't do this, it's going to make full migration to Kconfig harder. Please > audit > the whole file and anything that's not CONFIG_xxx needs to be somewhere else > really. Thanks. [Meenakshi Aggarwal] Will prefer to do this in a separate patch as it will impact all three LX2 based boards, because all use similar macros. > > -- > Tom
RE: [PATCH v3 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
Thanks Tom, We will plan it. -Original Message- From: Tom Rini Sent: Monday, September 7, 2020 6:42 PM To: Meenakshi Aggarwal Cc: u-boot@lists.denx.de; Priyanka Jain ; Varun Sethi Subject: Re: [PATCH v3 1/2] armv8: lx2162a: Add Soc changes to support LX2162A On Mon, Sep 07, 2020 at 03:42:06PM +0530, meenakshi.aggar...@nxp.com wrote: > From: Meenakshi Aggarwal > > LX2162 is LX2160 based SoC, it has same die as of LX2160 with > different packaging. > > LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, > microSD card, eMMC support, serial console, qspi nor flash, qsgmii, > sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes > interface to support three PCIe gen3 interface. > > Signed-off-by: Meenakshi Aggarwal > --- > arch/arm/cpu/armv8/Kconfig | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +-- > arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++ > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 9 ++-- > arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 > ++ I just want to make sure it's on the TODO list somewhere to convert this README.soc file to rST and move it under doc/board/ or similar, thanks! -- Tom
[PATCH v3 2/2] armv8: lx2162aqds: Add support for LX2162AQDS platform
From: Meenakshi Aggarwal
This patch add base support for LX2162AQDS board.
LX2162AQDS board supports LX2162A family SoCs.
This patch add basic support of platform.
Signed-off-by: Ioana Ciornei
Signed-off-by: Zhao Qiang
Signed-off-by: hui.song
Signed-off-by: Manish Tomar
Signed-off-by: Vikas Singh
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/Kconfig | 12 +
arch/arm/dts/Makefile | 6 +-
arch/arm/dts/fsl-lx2160a-qds.dts | 3 -
arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +-
arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 +
arch/arm/dts/fsl-lx2162a-qds.dts | 34 +
board/freescale/common/vid.c | 3 +-
board/freescale/lx2160a/Kconfig| 16 +
board/freescale/lx2160a/MAINTAINERS| 10 +
board/freescale/lx2160a/Makefile | 1 +
board/freescale/lx2160a/README | 132
board/freescale/lx2160a/eth_lx2162aqds.c | 974 +
board/freescale/lx2160a/lx2160a.c | 42 +-
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 97 +++
configs/lx2162aqds_tfa_defconfig | 95 +++
configs/lx2162aqds_tfa_verified_boot_defconfig | 102 +++
include/configs/lx2160a_common.h | 2 +
include/configs/lx2162aqds.h | 169 +
23 files changed, 1890 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts
create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c
create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/lx2162aqds_tfa_defconfig
create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig
create mode 100644 include/configs/lx2162aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80702c2..258babb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1321,6 +1321,18 @@ config TARGET_LX2160AQDS
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2162AQDS
+ bool "Support lx2162aqds"
+ select ARCH_LX2162A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2162AQDS platform.
+ The lx2162aqds support is based on LX2160A Layerscape Architecture
processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f8f5294..a34a56e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -409,7 +409,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2160a-qds-19-x-x.dtb \
fsl-lx2160a-qds-19-11-x.dtb \
fsl-lx2160a-qds-20-x-x.dtb \
- fsl-lx2160a-qds-20-11-x.dtb
+ fsl-lx2160a-qds-20-11-x.dtb \
+ fsl-lx2162a-qds.dtb\
+ fsl-lx2162a-qds-17-x.dtb\
+ fsl-lx2162a-qds-18-x.dtb\
+ fsl-lx2162a-qds-20-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts
index e0f5d5e..332c778 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@@ -13,7 +13,4 @@
/ {
model = "NXP Layerscape LX2160AQDS Board";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
- aliases {
- spi0 =
- };
};
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi
b/arch/arm/dts/fsl-lx2160a-qds.dtsi
index 96c9800..288607c 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -2,12 +2,18 @@
/*
* NXP LX2160AQDS common device tree source
*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
*/
#include "fsl-lx2160a.dtsi"
+/ {
+ aliases {
+ spi0 =
+ };
+};
+
{
status = "okay";
phy-handle = <_phy1>;
@@ -251,6 +257,20 @@
};
};
+ {
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ #address-cells
[PATCH v3 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
From: Meenakshi Aggarwal LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal --- arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +-- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 9 ++-- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +-- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 ++- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 ++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +-- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++--- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 ++- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 ++-- drivers/ddr/fsl/Kconfig| 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/pci/Kconfig| 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 ++- 19 files changed, 170 insertions(+), 40 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3655990..f247441 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -115,7 +115,7 @@ config PSCI_RESET !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ - !TARGET_LX2160AQDS && \ + !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index be51b7d..4d46587 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -208,6 +208,35 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2162A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config ARCH_LX2160A bool select ARMV8_SET_SMPEN @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106 help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar - to erratum A-009007, but this one is for LX2160A, + to erratum A-009007, but this one is for LX2160A and LX2162A, and the register value is different. config SYS_FSL_ERRATUM_A010315 @@ -362,6 +391,7 @@ config MAX_CPUS default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A default 16 if ARCH_LX2160A + default 16 if ARCH_LX2162A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A default 4 if ARCH_LX2160A + default 4 if ARCH_LX2162A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if AR
[PATCH v3 0/2] Add support for LX2162AQDS board
From: Meenakshi Aggarwal This patch set add support for LX2162AQDS board. LX2162A is a variant of LX2160A. --- Changes: v2: - Add Separate ARCH for LX2162A SoC - Updated ReadMe of SoC and board v3: - Fix compilation bug for ls1088 introduced with lx2162 changes Meenakshi Aggarwal (2): armv8: lx2162a: Add Soc changes to support LX2162A armv8: lx2162aqds: Add support for LX2162AQDS platform arch/arm/Kconfig | 12 + arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 5 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 9 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/fsl-lx2160a-qds.dts | 3 - arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + arch/arm/dts/fsl-lx2162a-qds.dts | 34 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 +- board/freescale/common/vid.c | 3 +- board/freescale/lx2160a/Kconfig| 16 + board/freescale/lx2160a/MAINTAINERS| 10 + board/freescale/lx2160a/Makefile | 1 + board/freescale/lx2160a/README | 132 +++ board/freescale/lx2160a/eth_lx2162aqds.c | 974 + board/freescale/lx2160a/lx2160a.c | 42 +- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 97 ++ configs/lx2162aqds_tfa_defconfig | 95 ++ configs/lx2162aqds_tfa_verified_boot_defconfig | 102 +++ drivers/ddr/fsl/Kconfig| 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/pci/Kconfig| 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 +- include/configs/lx2160a_common.h | 2 + include/configs/lx2162aqds.h | 169 42 files changed, 2060 insertions(+), 66 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/lx2162aqds_tfa_defconfig create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig create mode 100644 include/configs/lx2162aqds.h -- 2.7.4
[PATCH v2 2/2] armv8: lx2162aqds: Add support for LX2162AQDS platform
From: Meenakshi Aggarwal
This patch add base support for LX2162AQDS board.
LX2162AQDS board supports LX2162A family SoCs.
This patch add basic support of platform.
Signed-off-by: Ioana Ciornei
Signed-off-by: Zhao Qiang
Signed-off-by: hui.song
Signed-off-by: Manish Tomar
Signed-off-by: Vikas Singh
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/Kconfig | 12 +
arch/arm/dts/Makefile | 6 +-
arch/arm/dts/fsl-lx2160a-qds.dts | 3 -
arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +-
arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 +
arch/arm/dts/fsl-lx2162a-qds.dts | 34 +
board/freescale/common/vid.c | 3 +-
board/freescale/lx2160a/Kconfig| 16 +
board/freescale/lx2160a/MAINTAINERS| 10 +
board/freescale/lx2160a/Makefile | 1 +
board/freescale/lx2160a/README | 132
board/freescale/lx2160a/eth_lx2162aqds.c | 974 +
board/freescale/lx2160a/lx2160a.c | 42 +-
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 97 +++
configs/lx2162aqds_tfa_defconfig | 95 +++
configs/lx2162aqds_tfa_verified_boot_defconfig | 102 +++
include/configs/lx2160a_common.h | 2 +
include/configs/lx2162aqds.h | 169 +
23 files changed, 1890 insertions(+), 26 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts
create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c
create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/lx2162aqds_tfa_defconfig
create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig
create mode 100644 include/configs/lx2162aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80702c2..258babb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1321,6 +1321,18 @@ config TARGET_LX2160AQDS
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2162AQDS
+ bool "Support lx2162aqds"
+ select ARCH_LX2162A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2162AQDS platform.
+ The lx2162aqds support is based on LX2160A Layerscape Architecture
processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f8f5294..a34a56e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -409,7 +409,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2160a-qds-19-x-x.dtb \
fsl-lx2160a-qds-19-11-x.dtb \
fsl-lx2160a-qds-20-x-x.dtb \
- fsl-lx2160a-qds-20-11-x.dtb
+ fsl-lx2160a-qds-20-11-x.dtb \
+ fsl-lx2162a-qds.dtb\
+ fsl-lx2162a-qds-17-x.dtb\
+ fsl-lx2162a-qds-18-x.dtb\
+ fsl-lx2162a-qds-20-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts
index e0f5d5e..332c778 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dts
+++ b/arch/arm/dts/fsl-lx2160a-qds.dts
@@ -13,7 +13,4 @@
/ {
model = "NXP Layerscape LX2160AQDS Board";
compatible = "fsl,lx2160aqds", "fsl,lx2160a";
- aliases {
- spi0 =
- };
};
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi
b/arch/arm/dts/fsl-lx2160a-qds.dtsi
index 96c9800..288607c 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -2,12 +2,18 @@
/*
* NXP LX2160AQDS common device tree source
*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
*/
#include "fsl-lx2160a.dtsi"
+/ {
+ aliases {
+ spi0 =
+ };
+};
+
{
status = "okay";
phy-handle = <_phy1>;
@@ -251,6 +257,20 @@
};
};
+ {
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ #address-cells
[PATCH v2 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
From: Meenakshi Aggarwal LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by: Meenakshi Aggarwal --- arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +-- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 9 ++-- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +-- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 ++- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 ++-- arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +-- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 ++--- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 ++- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 ++-- drivers/ddr/fsl/Kconfig| 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/pci/Kconfig| 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 ++- 19 files changed, 166 insertions(+), 41 deletions(-) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3655990..f247441 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -115,7 +115,7 @@ config PSCI_RESET !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \ !TARGET_LS1046AFRWY && \ !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \ - !TARGET_LX2160AQDS && \ + !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \ !ARCH_UNIPHIER && !TARGET_S32V234EVB help Most armv8 systems have PSCI support enabled in EL3, either through diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index be51b7d..4d46587 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -208,6 +208,35 @@ config ARCH_LS2080A imply DISTRO_DEFAULTS imply PANIC_HANG +config ARCH_LX2162A + bool + select ARMV8_SET_SMPEN + select FSL_LSCH3 + select NXP_LSCH3_2 + select SYS_HAS_SERDES + select SYS_FSL_SRDS_1 + select SYS_FSL_SRDS_2 + select SYS_FSL_DDR + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_EC1 + select SYS_FSL_EC2 + select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_HAS_RGMII + select SYS_FSL_HAS_SEC + select SYS_FSL_HAS_CCN508 + select SYS_FSL_HAS_DDR4 + select SYS_FSL_SEC_COMPAT_5 + select SYS_FSL_SEC_LE + select ARCH_EARLY_INIT_R + select BOARD_EARLY_INIT_F + select SYS_I2C_MXC + select RESV_RAM if GIC_V3_ITS + imply DISTRO_DEFAULTS + imply PANIC_HANG + imply SCSI + imply SCSI_AHCI + config ARCH_LX2160A bool select ARMV8_SET_SMPEN @@ -345,7 +374,7 @@ config SYS_FSL_ERRATUM_A050106 help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar - to erratum A-009007, but this one is for LX2160A, + to erratum A-009007, but this one is for LX2160A and LX2162A, and the register value is different. config SYS_FSL_ERRATUM_A010315 @@ -362,6 +391,7 @@ config MAX_CPUS default 16 if ARCH_LS2080A default 8 if ARCH_LS1088A default 16 if ARCH_LX2160A + default 16 if ARCH_LX2162A default 1 help Set this number to the maximum number of possible CPUs in the SoC. @@ -491,6 +521,7 @@ config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" default 1 if ARCH_LS1043A default 4 if ARCH_LX2160A + default 4 if ARCH_LX2162A default 2 help This is the divider that is used to derive DUART clock from Platform @@ -502,6 +533,7 @@ config SYS_FSL_I2C_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if ARCH_LS1088A default 2 help @@ -514,6 +546,7 @@ config SYS_FSL_IFC_CLK_DIV default 4 if ARCH_LS1012A default 4 if ARCH_LS1028A default 8 if ARCH_LX2160A + default 8 if ARCH_LX2162A default 8 if AR
[PATCH v2 0/2] Add support for LX2162AQDS board
From: Meenakshi Aggarwal This patch set add support for LX2162AQDS board. LX2162A is a variant of LX2160A. --- Changes: v2: - Add Separate ARCH for LX2162A SoC - Updated ReadMe of SoC and board Meenakshi Aggarwal (2): armv8: lx2162a: Add Soc changes to support LX2162A armv8: lx2162aqds: Add support for LX2162AQDS platform arch/arm/Kconfig | 12 + arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 39 +- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 9 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 58 ++ .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c| 8 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c| 10 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/fsl-lx2160a-qds.dts | 3 - arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + arch/arm/dts/fsl-lx2162a-qds.dts | 34 + arch/arm/include/asm/arch-fsl-layerscape/config.h | 6 +- arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 4 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 12 +- arch/arm/include/asm/arch-fsl-layerscape/soc.h | 7 +- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 10 +- board/freescale/common/vid.c | 3 +- board/freescale/lx2160a/Kconfig| 16 + board/freescale/lx2160a/MAINTAINERS| 10 + board/freescale/lx2160a/Makefile | 1 + board/freescale/lx2160a/README | 132 +++ board/freescale/lx2160a/eth_lx2162aqds.c | 974 + board/freescale/lx2160a/lx2160a.c | 42 +- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 97 ++ configs/lx2162aqds_tfa_defconfig | 95 ++ configs/lx2162aqds_tfa_verified_boot_defconfig | 102 +++ drivers/ddr/fsl/Kconfig| 1 + drivers/net/fsl-mc/Kconfig | 4 +- drivers/net/ldpaa_eth/Makefile | 1 + drivers/pci/Kconfig| 4 +- drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 7 +- include/configs/lx2160a_common.h | 2 + include/configs/lx2162aqds.h | 169 42 files changed, 2056 insertions(+), 67 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/lx2162aqds_tfa_defconfig create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig create mode 100644 include/configs/lx2162aqds.h -- 2.7.4
RE: [PATCH 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
> -Original Message-
> From: Priyanka Jain
> Sent: Wednesday, September 2, 2020 12:49 PM
> To: Meenakshi Aggarwal ; u-
> b...@lists.denx.de
> Cc: Varun Sethi
> Subject: RE: [PATCH 1/2] armv8: lx2162a: Add Soc changes to support
> LX2162A
>
>
>
> >-Original Message-
> >From: Meenakshi Aggarwal
> >Sent: Tuesday, September 1, 2020 3:03 PM
> >To: u-boot@lists.denx.de; Priyanka Jain
> >Cc: Varun Sethi ; Meenakshi Aggarwal
> >
> >Subject: [PATCH 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
> >
> >From: Meenakshi Aggarwal
> >
> >LX2162 is LX2160 based SoC, it has same die as of LX2160 with different
> >packaging.
> >LX2162A support 4GB ddr memory, i2c, micro-click module, microSD card,
> >serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
> >interface,one usb 3.0 and serdes interface to support three x1 gen3
> >pcie interface.
> Are these Soc features or board features, please check. Similar description is
> used for both Soc and board patch
> >
> >Signed-off-by: Meenakshi Aggarwal
> >---
> > arch/arm/cpu/armv8/Kconfig | 2 +-
> > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 5 -
> > arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19
> >++-
> > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 5 -
> > drivers/pci/pcie_layerscape_ep.c | 4 +++-
> > drivers/pci/pcie_layerscape_fixup_common.c | 5 -
> > 6 files changed, 34 insertions(+), 6 deletions(-)
> >
> >diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
> >index 3655990..f247441 100644
> >--- a/arch/arm/cpu/armv8/Kconfig
> >+++ b/arch/arm/cpu/armv8/Kconfig
> >@@ -115,7 +115,7 @@ config PSCI_RESET
> >!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
> >!TARGET_LS1046AFRWY && \
> >!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
> >- !TARGET_LX2160AQDS && \
> >+ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
> >!ARCH_UNIPHIER && !TARGET_S32V234EVB
> > help
> > Most armv8 systems have PSCI support enabled in EL3, either
> through
> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >index 8a2f404..4fb222a 100644
> >--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >@@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> >- * Copyright 2017-2019 NXP
> >+ * Copyright 2017-2020 NXP
> > * Copyright 2014-2015 Freescale Semiconductor, Inc.
> > */
> >
> >@@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
> > CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
> > CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
> > CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
> >+CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
> >+CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
> >+CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
> > };
> >
> > #define EARLY_PGTABLE_SIZE 0x5000
> >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >index a04a370..b4dea80 100644
> >--- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
> >@@ -1,6 +1,6 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> >- * Copyright 2018 NXP
> >+ * Copyright 2018, 2020 NXP
> > */
> >
> > #include
> >@@ -11,6 +11,22 @@ struct serdes_config {
> > u8 lanes[SRDS_MAX_LANES];
> > };
> >
> >+#ifdef CONFIG_TARGET_LX2162AQDS
> Board change
These are SoC changes but as LX2162 is LX2160 bases so I didn't define a
separate config for LX2162A,
Rather used CONFIG_TARGET_LX2162AQDS.
Suggest if I should define one for LX2162A SOC?
> >+static struct serdes_config serdes1_cfg_tbl[] = {
> >+/* SerDes 1 */
> >+{0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
> >+{0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
> >+{0x03, {XFI6, XFI5, XFI4, XFI3 } },
> >+{0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
> >+{0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
> >+{0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
> >+{0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
> >+{0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
> >+{0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
> >+{0x14, {_40GE1, _40GE1, _40GE1, _
[PATCH 0/2] Add support for LX2162AQDS board
From: Meenakshi Aggarwal This patch set add support for LX2162AQDS board. LX2162A is a variant of LX2160A. Meenakshi Aggarwal (2): armv8: lx2162a: Add Soc changes to support LX2162A armv8: lx2162aqds: Add support for LX2162AQDS platform arch/arm/Kconfig | 12 + arch/arm/cpu/armv8/Kconfig | 2 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 5 +- arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +- arch/arm/dts/Makefile | 6 +- arch/arm/dts/fsl-lx2160a-qds.dtsi | 16 +- arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + arch/arm/dts/fsl-lx2162a-qds.dts | 36 + arch/arm/include/asm/arch-fsl-layerscape/soc.h | 5 +- board/freescale/lx2160a/Kconfig| 16 + board/freescale/lx2160a/MAINTAINERS| 12 +- board/freescale/lx2160a/Makefile | 1 + board/freescale/lx2160a/eth_lx2162aqds.c | 974 + board/freescale/lx2160a/lx2160a.c | 42 +- configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 97 ++ configs/lx2162aqds_tfa_defconfig | 95 ++ configs/lx2162aqds_tfa_verified_boot_defconfig | 102 +++ drivers/pci/pcie_layerscape_ep.c | 4 +- drivers/pci/pcie_layerscape_fixup_common.c | 5 +- include/configs/lx2160a_common.h | 2 + include/configs/lx2162aqds.h | 169 26 files changed, 1787 insertions(+), 29 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/lx2162aqds_tfa_defconfig create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig create mode 100644 include/configs/lx2162aqds.h -- 2.7.4
[PATCH 2/2] armv8: lx2162aqds: Add support for LX2162AQDS platform
From: Meenakshi Aggarwal
This patch add base support for LX2162AQDS board.
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
LX2162A support 4GB ddr memory, i2c, micro-click module, microSD card,
serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
interface,one usb 3.0 and serdes interface to support three x1gen3
pcie interface.
Signed-off-by: Ioana Ciornei
Signed-off-by: Zhao Qiang
Signed-off-by: hui.song
Signed-off-by: Manish Tomar
Signed-off-by: Vikas Singh
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/Kconfig | 12 +
arch/arm/dts/Makefile | 6 +-
arch/arm/dts/fsl-lx2160a-qds.dtsi | 16 +-
arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 +
arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++
arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 +
arch/arm/dts/fsl-lx2162a-qds.dts | 36 +
board/freescale/lx2160a/Kconfig| 16 +
board/freescale/lx2160a/MAINTAINERS| 12 +-
board/freescale/lx2160a/Makefile | 1 +
board/freescale/lx2160a/eth_lx2162aqds.c | 974 +
board/freescale/lx2160a/lx2160a.c | 42 +-
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 97 +++
configs/lx2162aqds_tfa_defconfig | 95 +++
configs/lx2162aqds_tfa_verified_boot_defconfig | 102 +++
include/configs/lx2160a_common.h | 2 +
include/configs/lx2162aqds.h | 169 +
20 files changed, 1753 insertions(+), 23 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi
create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts
create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c
create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/lx2162aqds_tfa_defconfig
create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig
create mode 100644 include/configs/lx2162aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80702c2..4bcbcc5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1321,6 +1321,18 @@ config TARGET_LX2160AQDS
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2162AQDS
+ bool "Support lx2162aqds"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2162AQDS platform.
+ The lx2162aqds support is based on LX2160A Layerscape Architecture
processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f8f5294..a34a56e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -409,7 +409,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-lx2160a-qds-19-x-x.dtb \
fsl-lx2160a-qds-19-11-x.dtb \
fsl-lx2160a-qds-20-x-x.dtb \
- fsl-lx2160a-qds-20-11-x.dtb
+ fsl-lx2160a-qds-20-11-x.dtb \
+ fsl-lx2162a-qds.dtb\
+ fsl-lx2162a-qds-17-x.dtb\
+ fsl-lx2162a-qds-18-x.dtb\
+ fsl-lx2162a-qds-20-x.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
fsl-ls1043a-qds-lpuart.dtb \
fsl-ls1043a-rdb.dtb \
diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi
b/arch/arm/dts/fsl-lx2160a-qds.dtsi
index 96c9800..370f116 100644
--- a/arch/arm/dts/fsl-lx2160a-qds.dtsi
+++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi
@@ -2,7 +2,7 @@
/*
* NXP LX2160AQDS common device tree source
*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*
*/
@@ -251,6 +251,20 @@
};
};
+ {
+ status = "okay";
+
+ mt35xu512aba0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <5000>;
+ reg = <0>;
+ spi-rx-bus-width = <8>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
{
status = "okay";
};
diff --git a/arch/arm/dts/fsl-lx2162a-qds-17-x.dts
b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts
new file mode 100644
index 000..8a8895f
--- /dev/null
+++ b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts
@@ -0
[PATCH 1/2] armv8: lx2162a: Add Soc changes to support LX2162A
From: Meenakshi Aggarwal
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
LX2162A support 4GB ddr memory, i2c, micro-click module, microSD card,
serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
interface,one usb 3.0 and serdes interface to support three x1 gen3
pcie interface.
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/cpu/armv8/Kconfig | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 5 -
arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 ++-
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 5 -
drivers/pci/pcie_layerscape_ep.c | 4 +++-
drivers/pci/pcie_layerscape_fixup_common.c | 5 -
6 files changed, 34 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 3655990..f247441 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -115,7 +115,7 @@ config PSCI_RESET
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
- !TARGET_LX2160AQDS && \
+ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 8a2f404..4fb222a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
+ CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
+ CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
+ CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
};
#define EARLY_PGTABLE_SIZE 0x5000
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
index a04a370..b4dea80 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
*/
#include
@@ -11,6 +11,22 @@ struct serdes_config {
u8 lanes[SRDS_MAX_LANES];
};
+#ifdef CONFIG_TARGET_LX2162AQDS
+static struct serdes_config serdes1_cfg_tbl[] = {
+ /* SerDes 1 */
+ {0x01, {PCIE1, PCIE1, PCIE1, PCIE1 } },
+ {0x02, {SGMII6, SGMII5, SGMII4, SGMII3 } },
+ {0x03, {XFI6, XFI5, XFI4, XFI3 } },
+ {0x09, {SGMII6, SGMII5, SGMII4, PCIE1 } },
+ {0x0B, {SGMII6, SGMII5, PCIE1, PCIE1 } },
+ {0x0F, {_50GE2, _50GE2, _50GE1, _50GE1 } },
+ {0x10, {_25GE6, _25GE5, _50GE1, _50GE1 } },
+ {0x11, {_25GE6, _25GE5, _25GE4, _25GE3 } },
+ {0x12, {_25GE6, _25GE5, XFI4, XFI3 } },
+ {0x14, {_40GE1, _40GE1, _40GE1, _40GE1 } },
+ {}
+};
+#else
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x01, {PCIE2, PCIE2, PCIE2, PCIE2, PCIE1, PCIE1, PCIE1, PCIE1 } },
@@ -48,6 +64,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x16, {XFI10, XFI9, PCIE2, PCIE2, XFI6, XFI5, XFI4, XFI3 } },
{}
};
+#endif
static struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 020548a..cbca43f 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2015 Freescale Semiconductor
*/
@@ -106,6 +106,9 @@ enum boot_src get_boot_src(void);
#define SVR_LX2160A0x873600
#define SVR_LX2120A0x873620
#define SVR_LX2080A0x873602
+#define SVR_LX2162A0x873608
+#define SVR_LX2122A0x873628
+#define SVR_LX2082A0x87360A
#define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
#define SVR_MIN(svr) (((svr) >> 0) & 0xf)
diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c
index eba230e..fd26ff7 100644
--- a/drivers/pci/pcie_layerscape_ep.c
+++ b/drivers/pci/pcie_layerscape_ep.c
@@ -272,7 +272,9 @@ static int ls_pcie_ep_probe(struct udevice *dev)
svr = SVR_SOC_VER(get_svr());
- if (svr == SVR_LX2160A)
+ if (svr == SVR_LX2160A || s
[PATCH] lx2160: Correct sd_boot environment variable
From: Meenakshi Aggarwal
Signed-off-by: Meenakshi Aggarwal
---
include/configs/lx2160aqds.h | 2 +-
include/configs/lx2160ardb.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 3dd071f..1cc015c 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -131,7 +131,7 @@ u8 qixis_esdhc_detect_quirk(void);
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$BOARD\0"\
"sd_bootcmd=echo Trying load from sd card..;" \
- "mmcinfo; mmc read $load_addr " \
+ "mmc dev 0; mmcinfo; mmc read $load_addr "
\
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index f54edf3..a51987e 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -101,7 +101,7 @@
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$BOARD\0"\
"sd_bootcmd=echo Trying load from sd card..;" \
- "mmcinfo; mmc read $load_addr " \
+ "mmc dev 0; mmcinfo; mmc read $load_addr "
\
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
--
2.7.4
RE: [EXT] [PATCH] armv8: lx2162aqds: Add support for LX2162AQDS platform
Thanks Kuldeep for the review, will do the changes.
> -Original Message-
> From: Kuldeep Singh
> Sent: Wednesday, August 26, 2020 3:48 PM
> To: u-boot@lists.denx.de; Meenakshi Aggarwal
>
> Cc: Ioana Ciornei ; Qiang Zhao
> ; Hui Song ; Manish Tomar
> ; Vikas Singh ; Priyanka
> Jain ; Ashish Kumar
> Subject: RE: [EXT] [PATCH] armv8: lx2162aqds: Add support for LX2162AQDS
> platform
>
> Hi Meenakshi,
>
> [..]
> > This patch add base support for LX2162 QDS board.
> > LX2162 is LX2160 based SoC, it has same die as of LX2160 with
> > different packaging.
> > Board support's 4GB ddr memory, i2c, micro-click module, microSD card,
> > serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
>
> s/qspi/flexspi
>
> > interface,one usb 3.0 and serdes interface to support three x1gen3
> > pcie interface.
>
> [...]
> > diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts
> > b/arch/arm/dts/fsl-lx2162a- qds.dts new file mode 100644 index
> > 000..2a498af
> > --- /dev/null
> > +++ b/arch/arm/dts/fsl-lx2162a-qds.dts
> > @@ -0,0 +1,107 @@
> > + {
> > + bus-num = <0>;
> > + status = "okay";
> > + fspi-has-second-chip;
> > +
> > + qflash0: mt35xu512g@0 {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + compatible = "spi-flash";
> > + spi-max-frequency = <2000>;
> > + reg = <0>;
> > + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode
> */
> > + fspi-rx-bus-width = <8>; /* 8 FSPI Rx lines */
> > + fspi-tx-bus-width = <1>; /* 1 FSPI Tx line */
> > + };
> > +
> > + /*
> > +* MCR2[SAMEDEVICEEN] bit is enabled in FlexSPI controller for
> > +* LX2160ARDB and LX2160AQDS board. Both these has same type
> > + of
> > flash
> > +* slave devices connected on both A0 and A1.
> > +* No need to provide node info for second flash device.
> > +*/
> > +};
>
> Please align fspi node properties with lx2160a-qds added in commit
> 4c1a52294f23 ("arm: dts: lx2160aqds: Add FSPI node properties").
> This version has few unused options which are not required by new driver
> anymore and also the comment related to MCR2[SAVEDEVICEEN] is not valid
> now.
>
> [..]
> > diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
> > b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
> > new file mode 100644
> > index 000..b2ae694
> > --- /dev/null
> > +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
> > @@ -0,0 +1,83 @@
> > +CONFIG_DM_SPI_FLASH=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_SPANSION=y
>
> No Spansion flash on lx2160/lx2162 qds boards. Please unset this option.
> Same goes with other defconfigs as well.
>
> And CONFIG_ENV_OVERWRITE is not required to reprogram "ethaddr"
> values?
>
> [..]
> > diff --git a/include/configs/lx2162aqds.h
> > b/include/configs/lx2162aqds.h new file mode 100644 index
> > 000..d364660
> > --- /dev/null
> > +++ b/include/configs/lx2162aqds.h
> > @@ -0,0 +1,175 @@
> > +/* DSPI */
> > +#ifdef CONFIG_FSL_DSPI
> > +#define CONFIG_SPI_FLASH_SST
> > +#define CONFIG_SPI_FLASH_EON
> > +#endif
>
> Please move these SPI_FLASH options from header to defconfig similar to
> lx2160a-qds.
>
> -Kuldeep
[PATCH] armv8: lx2162aqds: Add support for LX2162AQDS platform
From: Meenakshi Aggarwal
This patch add base support for LX2162 QDS board.
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.
Board support's 4GB ddr memory, i2c, micro-click module, microSD card,
serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network
interface,one usb 3.0 and serdes interface to support three x1gen3
pcie interface.
Signed-off-by: Ioana Ciornei
Signed-off-by: Zhao Qiang
Signed-off-by: hui.song
Signed-off-by: Manish Tomar
Signed-off-by: Vikas Singh
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/Kconfig | 12 +
arch/arm/cpu/armv8/Kconfig | 2 +-
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 5 +-
arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 19 +-
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-lx2162a-qds.dts | 107 +++
arch/arm/include/asm/arch-fsl-layerscape/soc.h | 5 +-
board/freescale/lx2160a/Kconfig| 16 +
board/freescale/lx2160a/MAINTAINERS| 14 +-
board/freescale/lx2160a/Makefile | 1 +
board/freescale/lx2160a/eth_lx2162aqds.c | 849 +
board/freescale/lx2160a/lx2160a.c | 42 +-
configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 83 ++
configs/lx2162aqds_tfa_defconfig | 83 ++
configs/lx2162aqds_tfa_verified_boot_defconfig | 93 +++
drivers/pci/pcie_layerscape.c | 4 +-
drivers/pci/pcie_layerscape_fixup_common.c | 5 +-
include/configs/lx2160a_common.h | 2 +
include/configs/lx2160aqds.h | 2 +-
include/configs/lx2160ardb.h | 2 +-
include/configs/lx2162aqds.h | 175 +
21 files changed, 1494 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts
create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c
create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
create mode 100644 configs/lx2162aqds_tfa_defconfig
create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig
create mode 100644 include/configs/lx2162aqds.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bbb1e27..492224f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1244,6 +1244,18 @@ config TARGET_LX2160AQDS
is a high-performance development platform that supports the
QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
+config TARGET_LX2162AQDS
+ bool "Support lx2162aqds"
+ select ARCH_LX2160A
+ select ARCH_MISC_INIT
+ select ARM64
+ select ARMV8_MULTIENTRY
+ select ARCH_SUPPORT_TFABOOT
+ select BOARD_LATE_INIT
+ help
+ Support for NXP LX2162AQDS platform.
+ The lx2162aqds support is based on LX2160A Layerscape Architecture
processor.
+
config TARGET_HIKEY
bool "Support HiKey 96boards Consumer Edition Platform"
select ARM64
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 16c83e8..a4fec59 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -109,7 +109,7 @@ config PSCI_RESET
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS1046AFRWY && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
- !TARGET_LX2160AQDS && \
+ !TARGET_LX2160AQDS && !TARGET_LX2162AQDS && \
!ARCH_UNIPHIER && !TARGET_S32V234EVB
help
Most armv8 systems have PSCI support enabled in EL3, either through
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index b443894..25449d0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2020 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@@ -75,6 +75,9 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
+ CPU_TYPE_ENTRY(LX2162A, LX2162A, 16),
+ CPU_TYPE_ENTRY(LX2122A, LX2122A, 12),
+ CPU_TYPE_ENTRY(LX2082A, LX2082A, 8),
};
#define EARLY_PGTABLE_SIZE 0x5000
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
index a04a370..b4dea80 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2020 NXP
*/
#include
@@ -11,6 +11,22 @@ struct serd
[PATCH v4] lx2160a : Update eMMC boot environment variable
Update mcinitcmd and bootcmd environment variable for emmc boot. Signed-off-by: Meenakshi Aggarwal --- Changes in V2: - Reword commit message Changes in V3: - Reword commit message - Add "mmc dev 1" in mcinitcmd variable to select eMMC Changes in V4: - Reword commit message ` --- include/configs/lx2160a_common.h | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index d47abf6..5ab9244 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -207,6 +207,16 @@ unsigned long get_board_ddr_clk(void); "esbc_validate 0x8068 ;"\ "fsl_mc start mc 0x80a0 0x80e0\0" +#define SD2_MC_INIT_CMD\ + "mmc dev 1; mmc read 0x80a0 0x5000 0x1200;" \ + "mmc read 0x80e0 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x8064 0x3200 0x20 && " \ + "mmc read 0x8068 0x3400 0x20 && " \ + "esbc_validate 0x8064 && " \ + "esbc_validate 0x8068 ;"\ + "fsl_mc start mc 0x80a0 0x80e0\0" + #define EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0"\ "ramdisk_addr=0x80\0" \ @@ -274,11 +284,11 @@ unsigned long get_board_ddr_clk(void); "env exists secureboot && esbc_halt;" #define SD2_BOOTCOMMAND\ - "env exists mcinitcmd && mmcinfo; " \ + "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80d0 0x6800 0x800; "\ "env exists mcinitcmd && env exists secureboot "\ - " && mmc read 0x8078 0x3C00 0x20 " \ - "&& esbc_validate 0x8078;env exists mcinitcmd " \ + " && mmc read 0x806C 0x3600 0x20 " \ + "&& esbc_validate 0x806C;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80d0;" \ "run distro_bootcmd;run sd2_bootcmd;" \ "env exists secureboot && esbc_halt;" -- 1.9.1
[PATCH v3] lx2160a : Update eMMC boot environment variable.
Update mcinitcmd and bootcmd environment variable emmc boot. Signed-off-by: Meenakshi Aggarwal --- Changes in V2: - Reword commit message. Changes in V3: - Reword commit message - Add "mmc dev 1" in mcinitcmd variable to select eMMC --- include/configs/lx2160a_common.h | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1907f93..c6a6a96 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -225,6 +225,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "esbc_validate 0x8068 ;"\ "fsl_mc start mc 0x80a0 0x80e0\0" +#define SD2_MC_INIT_CMD\ + "mmc dev 1; mmc read 0x80a0 0x5000 0x1200;" \ + "mmc read 0x80e0 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x8064 0x3200 0x20 && " \ + "mmc read 0x8068 0x3400 0x20 && " \ + "esbc_validate 0x8064 && " \ + "esbc_validate 0x8068 ;"\ + "fsl_mc start mc 0x80a0 0x80e0\0" + #define EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0"\ "ramdisk_addr=0x80\0" \ @@ -292,11 +302,11 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "env exists secureboot && esbc_halt;" #define SD2_BOOTCOMMAND\ - "env exists mcinitcmd && mmcinfo; " \ + "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80d0 0x6800 0x800; "\ "env exists mcinitcmd && env exists secureboot "\ - " && mmc read 0x8078 0x3C00 0x20 " \ - "&& esbc_validate 0x8078;env exists mcinitcmd " \ + " && mmc read 0x806C 0x3600 0x20 " \ + "&& esbc_validate 0x806C;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80d0;" \ "run distro_bootcmd;run emmc_bootcmd;" \ "env exists secureboot && esbc_halt;" -- 1.9.1
[PATCH v2] lx2160a : Update eMMC boot environment variables
Signed-off-by: Meenakshi Aggarwal --- Changes in V2: - Reword commit message. --- include/configs/lx2160a_common.h | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1907f93..6c3e647 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -225,6 +225,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "esbc_validate 0x8068 ;"\ "fsl_mc start mc 0x80a0 0x80e0\0" +#define SD2_MC_INIT_CMD\ + "mmc read 0x80a0 0x5000 0x1200;"\ + "mmc read 0x80e0 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x8064 0x3200 0x20 && " \ + "mmc read 0x8068 0x3400 0x20 && " \ + "esbc_validate 0x8064 && " \ + "esbc_validate 0x8068 ;"\ + "fsl_mc start mc 0x80a0 0x80e0\0" + #define EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0"\ "ramdisk_addr=0x80\0" \ @@ -292,11 +302,11 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "env exists secureboot && esbc_halt;" #define SD2_BOOTCOMMAND\ - "env exists mcinitcmd && mmcinfo; " \ + "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80d0 0x6800 0x800; "\ "env exists mcinitcmd && env exists secureboot "\ - " && mmc read 0x8078 0x3C00 0x20 " \ - "&& esbc_validate 0x8078;env exists mcinitcmd " \ + " && mmc read 0x806C 0x3600 0x20 " \ + "&& esbc_validate 0x806C;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80d0;" \ "run distro_bootcmd;run emmc_bootcmd;" \ "env exists secureboot && esbc_halt;" -- 1.9.1
[PATCH] lx2160a : Update environment variable.
Update environment variable for emmc boot. Signed-off-by: Meenakshi Aggarwal --- include/configs/lx2160a_common.h | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 1907f93..6c3e647 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -225,6 +225,16 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "esbc_validate 0x8068 ;"\ "fsl_mc start mc 0x80a0 0x80e0\0" +#define SD2_MC_INIT_CMD\ + "mmc read 0x80a0 0x5000 0x1200;"\ + "mmc read 0x80e0 0x7000 0x800;" \ + "env exists secureboot && " \ + "mmc read 0x8064 0x3200 0x20 && " \ + "mmc read 0x8068 0x3400 0x20 && " \ + "esbc_validate 0x8064 && " \ + "esbc_validate 0x8068 ;"\ + "fsl_mc start mc 0x80a0 0x80e0\0" + #define EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0"\ "ramdisk_addr=0x80\0" \ @@ -292,11 +302,11 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); "env exists secureboot && esbc_halt;" #define SD2_BOOTCOMMAND\ - "env exists mcinitcmd && mmcinfo; " \ + "mmc dev 1; env exists mcinitcmd && mmcinfo; " \ "mmc read 0x80d0 0x6800 0x800; "\ "env exists mcinitcmd && env exists secureboot "\ - " && mmc read 0x8078 0x3C00 0x20 " \ - "&& esbc_validate 0x8078;env exists mcinitcmd " \ + " && mmc read 0x806C 0x3600 0x20 " \ + "&& esbc_validate 0x806C;env exists mcinitcmd " \ "&& fsl_mc lazyapply dpl 0x80d0;" \ "run distro_bootcmd;run emmc_bootcmd;" \ "env exists secureboot && esbc_halt;" -- 1.9.1
[PATCH] lx2160a: Add dhcp in boot_targets
Add dhcp in supported boot_targets for lx2160. Signed-off-by: Meenakshi Aggarwal --- include/configs/lx2160a_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 0b0075a..ba10dc5 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -287,7 +287,8 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); #define BOOT_TARGET_DEVICES(func) \ func(USB, usb, 0) \ func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) + func(SCSI, scsi, 0) \ + func(DHCP, dhcp, na) #include #endif /* __LX2_COMMON_H */ -- 1.9.1
[PATCH] lx2160a : Remove default VID setting
Set VID to 800 mV for Rev1 and set VID as per switch settings
for Rev2.
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/lx2160a/lx2160a.c | 9 -
include/configs/lx2160aqds.h | 1 -
include/configs/lx2160ardb.h | 1 -
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 3deb76b..ba1cac2 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -297,7 +297,14 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int init_func_vid(void)
{
- if (adjust_vdd(0) < 0)
+ int set_vid;
+
+ if (IS_SVR_REV(get_svr(), 1, 0))
+ set_vid = adjust_vdd(800);
+ else
+ set_vid = adjust_vdd(0);
+
+ if (set_vid < 0)
printf("core voltage not adjusted\n");
return 0;
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 56a50d3..ddc76bd 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -127,7 +127,6 @@ u8 qixis_esdhc_detect_quirk(void);
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
- "lx2160aqds_vdd_mv=800\0" \
"boot_scripts=lx2160aqds_boot.scr\0"\
"boot_script_hdr=hdr_lx2160aqds_bs.out\0" \
"BOARD=lx2160aqds\0"\
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 5b530f0..e86102a 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -99,7 +99,6 @@
EXTRA_ENV_SETTINGS \
"boot_scripts=lx2160ardb_boot.scr\0"\
"boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
- "lx2160ardb_vdd_mv=800\0" \
"BOARD=lx2160ardb\0"\
"xspi_bootcmd=echo Trying load from flexspi..;" \
"sf probe 0:0 && sf read $load_addr " \
--
1.9.1
[PATCH] lx2160a : Add emmc in boot_targets environment variable
Add emmc in supported boot_targets and
Add bootcmd environment variable for emmc boot.
Signed-off-by: Meenakshi Aggarwal
---
include/configs/lx2160a_common.h | 11 +++
include/configs/lx2160aqds.h | 7 +++
include/configs/lx2160ardb.h | 7 +++
3 files changed, 25 insertions(+)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 0b0075a..bf1ba82 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -284,9 +284,20 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
"run distro_bootcmd;run sd_bootcmd;"\
"env exists secureboot && esbc_halt;"
+#define SD2_BOOTCOMMAND\
+ "env exists mcinitcmd && mmcinfo; " \
+ "mmc read 0x80d0 0x6800 0x800; "\
+ "env exists mcinitcmd && env exists secureboot "\
+ " && mmc read 0x8078 0x3C00 0x20 " \
+ "&& esbc_validate 0x8078;env exists mcinitcmd " \
+ "&& fsl_mc lazyapply dpl 0x80d0;" \
+ "run distro_bootcmd;run sd2_bootcmd;" \
+ "env exists secureboot && esbc_halt;"
+
#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
func(SCSI, scsi, 0)
#include
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 56a50d3..12783a8 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -143,6 +143,13 @@ u8 qixis_esdhc_detect_quirk(void);
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0" \
+ "sd2_bootcmd=echo Trying load from emmc card..;"\
+ "mmc dev 1; mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd "\
+ " && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0"
#include
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 5b530f0..ff92c0a 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -113,6 +113,13 @@
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd "\
" && esbc_validate ${kernelheader_addr_r};" \
+ "bootm $load_addr#$BOARD\0" \
+ "sd2_bootcmd=echo Trying load from emmc card..;"\
+ "mmc dev 1; mmcinfo; mmc read $load_addr " \
+ "$kernel_addr_sd $kernel_size_sd ;" \
+ "env exists secureboot && mmc read $kernelheader_addr_r "\
+ "$kernelhdr_addr_sd $kernelhdr_size_sd "\
+ " && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0"
#include
--
1.9.1
[PATCH v4] board: fsl: lx2160a: Add support to reset to eMMC
Add support of "qixis_reset emmc" command for lx2160a based platforms
Signed-off-by: Meenakshi Aggarwal
---
Changes:
v2:
- update in commit message
- using set_rcw_src() in place of QIXIS_WRITE()
v3:
- update in commit message
v4:
-incorporated review comments
---
board/freescale/common/qixis.c| 4
board/freescale/lx2160a/lx2160a.c | 2 ++
include/configs/lx2160aqds.h | 2 ++
include/configs/lx2160ardb.h | 2 ++
4 files changed, 10 insertions(+)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 716c93b..dd1ee90 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor
+ * Copyright 2020 NXP
* Author: Shengzhou Liu
*
* This file provides support for the QIXIS of some Freescale reference boards.
@@ -287,7 +288,9 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int
argc, char * const ar
#ifdef QIXIS_LBMAP_EMMC
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
+#ifndef NON_EXTENDED_DUTCFG
set_lbmap(QIXIS_LBMAP_EMMC);
+#endif
set_rcw_src(QIXIS_RCW_SRC_EMMC);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
@@ -365,6 +368,7 @@ U_BOOT_CMD(
"qixis watchdog - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
"qixis_reset dump - display the QIXIS registers\n"
+ "qixis_reset emmc - reset to emmc\n"
"qixis_reset switch - display switch\n"
);
#endif
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index dd3cd45..79abcd8 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -325,6 +325,8 @@ int checkboard(void)
if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
} else {
sw = QIXIS_READ(brdcfg[0]);
sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index f523b37..56a50d3 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
#define QIXIS_SDID_MASK0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 6ff1c24..5b530f0 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
/* VID */
--
1.9.1
RE: [PATCH v3] board: fsl: lx2160a: Add support to reset to eMMC
> -Original Message-
> From: Priyanka Jain (OSS)
> Sent: Wednesday, January 22, 2020 4:34 PM
> To: Meenakshi Aggarwal ; u-
> b...@lists.denx.de
> Subject: RE: [PATCH v3] board: fsl: lx2160a: Add support to reset to eMMC
>
>
>
> >-Original Message-----
> >From: U-Boot On Behalf Of Meenakshi
> >Aggarwal
> >Sent: Thursday, January 16, 2020 9:13 PM
> >To: u-boot@lists.denx.de; Priyanka Jain
> >Subject: [PATCH v3] board: fsl: lx2160a: Add support to reset to eMMC
> >
> >Add support of "qixis_reset emmc" command for lx2160a based platforms
> >
> >Signed-off-by: Meenakshi Aggarwal
> >
> >---
> >Changes:
> >
> > v2:
> > - Update in commit message
> > - using set_rcw_src() in place of QIXIS_WRITE()
> >
> > v3:
> > - update in commit message
> Whenever you send a next version , please mark previous version as superseded.
> It is sometimes difficult to isolate specially if subject is different.
Ok, will take care of same in future.
> >
> >Signed-off-by: Meenakshi Aggarwal
> >---
> > board/freescale/common/qixis.c| 6 ++
> > board/freescale/lx2160a/lx2160a.c | 2 ++
> > include/configs/lx2160aqds.h | 2 ++
> > include/configs/lx2160ardb.h | 2 ++
> > 4 files changed, 12 insertions(+)
> >
> >diff --git a/board/freescale/common/qixis.c
> >b/board/freescale/common/qixis.c index 716c93b..ab229b9 100644
> >--- a/board/freescale/common/qixis.c
> >+++ b/board/freescale/common/qixis.c
> >@@ -1,6 +1,7 @@
> > // SPDX-License-Identifier: GPL-2.0+
> > /*
> > * Copyright 2011 Freescale Semiconductor
> >+ * Copyright 2020 NXP
> > * Author: Shengzhou Liu
> > *
> > * This file provides support for the QIXIS of some Freescale reference
> > boards.
> >@@ -287,8 +288,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int
> >flag, int argc, char * const ar #ifdef QIXIS_LBMAP_EMMC
> > QIXIS_WRITE(rst_ctl, 0x30);
> > QIXIS_WRITE(rcfg_ctl, 0);
> >+#ifdef NON_EXTENDED_DUTCFG
> >+set_rcw_src(QIXIS_RCW_SRC_EMMC);
> >+#else
> > set_lbmap(QIXIS_LBMAP_EMMC);
> It would be better to just enclosed above in #ifndef
Ok
> > set_rcw_src(QIXIS_RCW_SRC_EMMC);
> >+#endif
> > QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
> > QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
> #else @@
> >-365,6 +370,7 @@ U_BOOT_CMD(
> > "qixis watchdog - set the watchdog period\n"
> > " period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
> > "qixis_reset dump - display the QIXIS registers\n"
> >+"qixis_reset emmc - reset to emmc\n"
> > "qixis_reset switch - display switch\n"
> > );
> > #endif
> >diff --git a/board/freescale/lx2160a/lx2160a.c
> >b/board/freescale/lx2160a/lx2160a.c
> >index dd3cd45..79abcd8 100644
> >--- a/board/freescale/lx2160a/lx2160a.c
> >+++ b/board/freescale/lx2160a/lx2160a.c
> >@@ -325,6 +325,8 @@ int checkboard(void)
> >
> > if (src == BOOT_SOURCE_SD_MMC) {
> > puts("SD\n");
> >+} else if (src == BOOT_SOURCE_SD_MMC2) {
> >+puts("eMMC\n");
> > } else {
> > sw = QIXIS_READ(brdcfg[0]);
> > sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK; diff --git
> >a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index
> >f523b37..56a50d3 100644
> >--- a/include/configs/lx2160aqds.h
> >+++ b/include/configs/lx2160aqds.h
> >@@ -22,7 +22,9 @@
> > #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
> > #define QIXIS_LBMAP_MASK0x0f
> > #define QIXIS_LBMAP_SD
> >+#define QIXIS_LBMAP_EMMC
> > #define QIXIS_RCW_SRC_SD0x08
> >+#define QIXIS_RCW_SRC_EMMC 0x09
> > #define NON_EXTENDED_DUTCFG
> > #define QIXIS_SDID_MASK 0x07
> > #define QIXIS_ESDHC_NO_ADAPTER 0x7
> >diff --git a/include/configs/lx2160ardb.h
> >b/include/configs/lx2160ardb.h index
> >6ff1c24..5b530f0 100644
> >--- a/include/configs/lx2160ardb.h
> >+++ b/include/configs/lx2160ardb.h
> >@@ -22,7 +22,9 @@
> > #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
> > #define QIXIS_LBMAP_MASK0x0f
> > #define QIXIS_LBMAP_SD
> >+#define QIXIS_LBMAP_EMMC
> > #define QIXIS_RCW_SRC_SD 0x08
> >+#define QIXIS_RCW_SRC_EMMC 0x09
> > #define NON_EXTENDED_DUTCFG
> >
> > /* VID */
> >--
> >1.9.1
> -Priyanka
[PATCH v3] board: fsl: lx2160a: Add support to reset to eMMC
Add support of "qixis_reset emmc" command for lx2160a based platforms
Signed-off-by: Meenakshi Aggarwal
---
Changes:
v2:
- Update in commit message
- using set_rcw_src() in place of QIXIS_WRITE()
v3:
- update in commit message
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/common/qixis.c| 6 ++
board/freescale/lx2160a/lx2160a.c | 2 ++
include/configs/lx2160aqds.h | 2 ++
include/configs/lx2160ardb.h | 2 ++
4 files changed, 12 insertions(+)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 716c93b..ab229b9 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor
+ * Copyright 2020 NXP
* Author: Shengzhou Liu
*
* This file provides support for the QIXIS of some Freescale reference boards.
@@ -287,8 +288,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int
argc, char * const ar
#ifdef QIXIS_LBMAP_EMMC
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
+#ifdef NON_EXTENDED_DUTCFG
+ set_rcw_src(QIXIS_RCW_SRC_EMMC);
+#else
set_lbmap(QIXIS_LBMAP_EMMC);
set_rcw_src(QIXIS_RCW_SRC_EMMC);
+#endif
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
@@ -365,6 +370,7 @@ U_BOOT_CMD(
"qixis watchdog - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
"qixis_reset dump - display the QIXIS registers\n"
+ "qixis_reset emmc - reset to emmc\n"
"qixis_reset switch - display switch\n"
);
#endif
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index dd3cd45..79abcd8 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -325,6 +325,8 @@ int checkboard(void)
if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
} else {
sw = QIXIS_READ(brdcfg[0]);
sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index f523b37..56a50d3 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
#define QIXIS_SDID_MASK0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 6ff1c24..5b530f0 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
/* VID */
--
1.9.1
[PATCH v2] lx2160a: Add support of emmc boot
Add support of "qixis_reset emmc" command for lx2160a based platforms
Signed-off-by: Meenakshi Aggarwal
---
Changes:
v2:
- Update in commit message
- using set_rcw_src() in place of QIXIS_WRITE()
---
board/freescale/common/qixis.c| 6 ++
board/freescale/lx2160a/lx2160a.c | 2 ++
include/configs/lx2160aqds.h | 2 ++
include/configs/lx2160ardb.h | 2 ++
4 files changed, 12 insertions(+)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 716c93b..ab229b9 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor
+ * Copyright 2020 NXP
* Author: Shengzhou Liu
*
* This file provides support for the QIXIS of some Freescale reference boards.
@@ -287,8 +288,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int
argc, char * const ar
#ifdef QIXIS_LBMAP_EMMC
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
+#ifdef NON_EXTENDED_DUTCFG
+ set_rcw_src(QIXIS_RCW_SRC_EMMC);
+#else
set_lbmap(QIXIS_LBMAP_EMMC);
set_rcw_src(QIXIS_RCW_SRC_EMMC);
+#endif
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
@@ -365,6 +370,7 @@ U_BOOT_CMD(
"qixis watchdog - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
"qixis_reset dump - display the QIXIS registers\n"
+ "qixis_reset emmc - reset to emmc\n"
"qixis_reset switch - display switch\n"
);
#endif
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index dd3cd45..79abcd8 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -325,6 +325,8 @@ int checkboard(void)
if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
} else {
sw = QIXIS_READ(brdcfg[0]);
sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index f523b37..56a50d3 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
#define QIXIS_SDID_MASK0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 6ff1c24..5b530f0 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
/* VID */
--
1.9.1
[PATCH] lx2160: Add support of emmc boot
Add support of "qixis_reset emmc" command for lx2160
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/common/qixis.c| 6 ++
board/freescale/lx2160a/lx2160a.c | 2 ++
include/configs/lx2160aqds.h | 2 ++
include/configs/lx2160ardb.h | 2 ++
4 files changed, 12 insertions(+)
diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c
index 716c93b..1899fd5 100644
--- a/board/freescale/common/qixis.c
+++ b/board/freescale/common/qixis.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor
+ * Copyright 2020 NXP
* Author: Shengzhou Liu
*
* This file provides support for the QIXIS of some Freescale reference boards.
@@ -287,8 +288,12 @@ static int qixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int
argc, char * const ar
#ifdef QIXIS_LBMAP_EMMC
QIXIS_WRITE(rst_ctl, 0x30);
QIXIS_WRITE(rcfg_ctl, 0);
+#ifdef NON_EXTENDED_DUTCFG
+ QIXIS_WRITE(dutcfg[0], QIXIS_RCW_SRC_EMMC);
+#else
set_lbmap(QIXIS_LBMAP_EMMC);
set_rcw_src(QIXIS_RCW_SRC_EMMC);
+#endif
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_IDLE);
QIXIS_WRITE(rcfg_ctl, QIXIS_RCFG_CTL_RECONFIG_START);
#else
@@ -365,6 +370,7 @@ U_BOOT_CMD(
"qixis watchdog - set the watchdog period\n"
" period: 1s 2s 4s 8s 16s 32s 1min 2min 4min 8min\n"
"qixis_reset dump - display the QIXIS registers\n"
+ "qixis_reset emmc - reset to emmc\n"
"qixis_reset switch - display switch\n"
);
#endif
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index dd3cd45..79abcd8 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -325,6 +325,8 @@ int checkboard(void)
if (src == BOOT_SOURCE_SD_MMC) {
puts("SD\n");
+ } else if (src == BOOT_SOURCE_SD_MMC2) {
+ puts("eMMC\n");
} else {
sw = QIXIS_READ(brdcfg[0]);
sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index f523b37..56a50d3 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
#define QIXIS_SDID_MASK0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index 6ff1c24..5b530f0 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -22,7 +22,9 @@
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
+#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
+#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
/* VID */
--
1.9.1
[PATCH] lx2160: Correct default environment variable
Create separate "boot_scripts" and "boot_script_hdr" environment
variable for LX2160A RDB and QDS board.
Signed-off-by: Meenakshi Aggarwal
---
include/configs/lx2160a_common.h | 4 +---
include/configs/lx2160aqds.h | 4 +++-
include/configs/lx2160ardb.h | 4 +++-
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 398b21d..909d047 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*/
#ifndef __LX2_COMMON_H
@@ -247,8 +247,6 @@ int select_i2c_ch_pca9547_sec(unsigned char ch);
BOOTENV \
"mcmemsize=0x7000\0"\
XSPI_MC_INIT_CMD\
- "boot_scripts=lx2160ardb_boot.scr\0"\
- "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
"scan_dev_for_boot_part=" \
"part list ${devtype} ${devnum} devplist; " \
"env exists devplist || setenv devplist 1; "\
diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h
index 60b13b4..f523b37 100644
--- a/include/configs/lx2160aqds.h
+++ b/include/configs/lx2160aqds.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018-2019 NXP
+ * Copyright 2018-2020 NXP
*/
#ifndef __LX2_QDS_H
@@ -126,6 +126,8 @@ u8 qixis_esdhc_detect_quirk(void);
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
"lx2160aqds_vdd_mv=800\0" \
+ "boot_scripts=lx2160aqds_boot.scr\0"\
+ "boot_script_hdr=hdr_lx2160aqds_bs.out\0" \
"BOARD=lx2160aqds\0"\
"xspi_bootcmd=echo Trying load from flexspi..;" \
"sf probe 0:0 && sf read $load_addr " \
diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h
index cd710c7..6ff1c24 100644
--- a/include/configs/lx2160ardb.h
+++ b/include/configs/lx2160ardb.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018,2020 NXP
*/
#ifndef __LX2_RDB_H
@@ -95,6 +95,8 @@
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
+ "boot_scripts=lx2160ardb_boot.scr\0"\
+ "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \
"lx2160ardb_vdd_mv=800\0" \
"BOARD=lx2160ardb\0"\
"xspi_bootcmd=echo Trying load from flexspi..;" \
--
1.9.1
[U-Boot] [PATCH] lx2160: Correct serdes frequency print.
Signed-off-by: Meenakshi Aggarwal
---
changed for v2:
- corrected typo in commit message.
---
board/freescale/lx2160a/lx2160a.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 8140f3e..eff5d9f 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -372,7 +372,7 @@ int checkboard(void)
puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
- puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100Hz\n");
+ puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
#endif
return 0;
}
--
1.9.1
___
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U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3] armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar Signed-off-by: Meenakshi Aggarwal --- changed for v2: - An increase in timeout doesn't ensure completion of L3 cache flushing operation. So checking the L3 cache status till it succedd. changed for v3: - Updated Copyright - add loop to poll for l3 dcache status in hnf_pstate_poll function - removed timeout related code as it is not needed --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 30 1 file changed, 8 insertions(+), 22 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6721a57..711ab87 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014-2015 Freescale Semiconductor + * Copyright 2019 NXP * * Extracted from armv8/start.S */ @@ -356,31 +357,22 @@ get_svr: #if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508) hnf_pstate_poll: - /* x0 has the desired status, return 0 for success, 1 for timeout -* clobber x1, x2, x3, x4, x6, x7 + /* x0 has the desired status, return only if operation succeed +* clobber x1, x2, x6 */ mov x1, x0 - mov x7, #0 /* flag for timeout */ - mrs x3, cntpct_el0 /* read timer */ - add x3, x3, #1200 /* timeout after 100 microseconds */ + mov w6, #8 /* HN-F node count */ mov x0, #0x18 movkx0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ - mov w6, #8 /* HN-F node count */ 1: ldr x2, [x0] cmp x2, x1 /* check status */ b.eq2f - mrs x4, cntpct_el0 - cmp x4, x3 - b.ls1b - mov x7, #1 /* timeout */ - b 3f + b 1b 2: add x0, x0, #0x1/* move to next node */ subsw6, w6, #1 cbnzw6, 1b -3: - mov x0, x7 ret hnf_set_pstate: @@ -405,10 +397,8 @@ ENTRY(__asm_flush_l3_dcache) /* * Return status in x0 *success 0 -*timeout 1 for setting SFONLY, 2 for FAM, 3 for both */ mov x29, lr - mov x8, #0 dsb sy mov x0, #0x1/* HNFPSTAT_SFONLY */ @@ -416,19 +406,15 @@ ENTRY(__asm_flush_l3_dcache) mov x0, #0x4/* SFONLY status */ bl hnf_pstate_poll - cbz x0, 1f - mov x8, #1 /* timeout */ -1: + dsb sy mov x0, #0x3/* HNFPSTAT_FAM */ bl hnf_set_pstate mov x0, #0xc/* FAM status */ bl hnf_pstate_poll - cbz x0, 1f - add x8, x8, #0x2 -1: - mov x0, x8 + + mov x0, #0 mov lr, x29 ret ENDPROC(__asm_flush_l3_dcache) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4] drivers: net: mc: Report extra memory to Linux
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
changed for v1:
- Incorporated review comments in one board, Missed for
other boards
changed for v2:
- Incorporated review comments in all boards
changed for v3:
- Include revision history in patch
changed for v4:
- Remove macro TRUE/FALSE
---
board/freescale/ls1088a/ls1088a.c | 31 ---
board/freescale/ls2080ardb/ls2080ardb.c | 32 +---
board/freescale/lx2160a/lx2160a.c | 31 ---
drivers/net/fsl-mc/mc.c | 10 ++
include/fsl-mc/fsl_mc.h | 1 +
5 files changed, 96 insertions(+), 9 deletions(-)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..db26938 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -738,11 +738,26 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank++;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -759,7 +774,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index ce419df..318ee65 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -409,11 +409,27 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ int i;
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank++;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@@ -430,7 +446,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, 2);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 3875d04..aa2ff74 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -520,11 +520,26 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ u16 mc_memory_bank = 0;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base
[U-Boot] [PATCH v2] armv8/fsl-layerscape : Add loop to check cache status
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic. Add loop to check status of L3 cache, it insures that L3 is flushed properly. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar Signed-off-by: Meenakshi Aggarwal --- changed for v2: - An increase in timeout doesn't ensure completion of L3 cache flushing operation. So checking the L3 cache status till it succedd. --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6721a57..2ba1a51 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -414,19 +414,23 @@ ENTRY(__asm_flush_l3_dcache) mov x0, #0x1/* HNFPSTAT_SFONLY */ bl hnf_set_pstate +loop1: mov x0, #0x4/* SFONLY status */ bl hnf_pstate_poll cbz x0, 1f mov x8, #1 /* timeout */ + b loop1 1: dsb sy mov x0, #0x3/* HNFPSTAT_FAM */ bl hnf_set_pstate +loop2: mov x0, #0xc/* FAM status */ bl hnf_pstate_poll cbz x0, 1f add x8, x8, #0x2 + b loop2 1: mov x0, x8 mov lr, x29 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3] drivers: net: mc: Report extra memory to Linux
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
changed for v1:
- Incorporated review comments in one board, Missed for
other boards
changed for v2:
- Incorporated review comments in all boards
changed for v3:
- Include revision history in patch
---
board/freescale/ls1088a/ls1088a.c | 34 +---
board/freescale/ls2080ardb/ls2080ardb.c | 35 ++---
board/freescale/lx2160a/lx2160a.c | 34 +---
drivers/net/fsl-mc/mc.c | 10 ++
include/fsl-mc/fsl_mc.h | 1 +
5 files changed, 105 insertions(+), 9 deletions(-)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..88c34cb 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -28,6 +28,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define TRUE 1
+#define FALSE 0
+
#ifdef CONFIG_TARGET_LS1088AQDS
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
@@ -738,11 +741,26 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memory_bank = FALSE;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = TRUE;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -759,7 +777,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index ce419df..b6b4e80 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -22,6 +22,9 @@
#include
#include
+#define TRUE 1
+#define FALSE 0
+
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
#include "ls2080ardb_qixis.h"
@@ -409,11 +412,27 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ int i;
+ bool mc_memory_bank = FALSE;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = TRUE;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@@ -430,7 +449,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, 2);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_m
[U-Boot] [PATCH] armv8/fsl-layerscape: increase timeout for l3 flush
Few platforms need longer timeout to flush l3 cache. This patch increase the timeout value for proper l3 cache flush operation. Signed-off-by: Udit Kumar Signed-off-by: Meenakshi Aggarwal --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6721a57..10aebbc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -362,7 +362,7 @@ hnf_pstate_poll: mov x1, x0 mov x7, #0 /* flag for timeout */ mrs x3, cntpct_el0 /* read timer */ - add x3, x3, #1200 /* timeout after 100 microseconds */ + add x3, x3, #4000 /* timeout after 333 microseconds */ mov x0, #0x18 movkx0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ mov w6, #8 /* HN-F node count */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] drivers: net: mc: Report extra memory to Linux
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/ls1088a/ls1088a.c | 34 +---
board/freescale/ls2080ardb/ls2080ardb.c | 35 ++---
board/freescale/lx2160a/lx2160a.c | 34 +---
drivers/net/fsl-mc/mc.c | 10 ++
include/fsl-mc/fsl_mc.h | 1 +
5 files changed, 105 insertions(+), 9 deletions(-)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..88c34cb 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -28,6 +28,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define TRUE 1
+#define FALSE 0
+
#ifdef CONFIG_TARGET_LS1088AQDS
#ifdef CONFIG_TFABOOT
struct ifc_regs ifc_cfg_ifc_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
@@ -738,11 +741,26 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memory_bank = FALSE;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = TRUE;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -759,7 +777,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index ce419df..b6b4e80 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -22,6 +22,9 @@
#include
#include
+#define TRUE 1
+#define FALSE 0
+
#ifdef CONFIG_FSL_QIXIS
#include "../common/qixis.h"
#include "ls2080ardb_qixis.h"
@@ -409,11 +412,27 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ int i;
+ bool mc_memory_bank = FALSE;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = TRUE;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@@ -430,7 +449,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, 2);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 3875d04..5f6099f 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -
[U-Boot] [PATCH v2] cover letter for drivers: net: mc: Report extra memory to linux
changes in different versions: v1 : Incorporated review comments in one board, Missed for other boards v2 : Incorporated review comments in all boards. Meenakshi Aggarwal (1): drivers: net: mc: Report extra memory to Linux board/freescale/ls1088a/ls1088a.c | 34 +--- board/freescale/ls2080ardb/ls2080ardb.c | 35 ++--- board/freescale/lx2160a/lx2160a.c | 34 +--- drivers/net/fsl-mc/mc.c | 10 ++ include/fsl-mc/fsl_mc.h | 1 + 5 files changed, 105 insertions(+), 9 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1] drivers: net: mc: Report extra memory to Linux
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/ls1088a/ls1088a.c | 31 +++---
board/freescale/ls2080ardb/ls2080ardb.c | 32 ---
board/freescale/lx2160a/lx2160a.c | 34 ++---
drivers/net/fsl-mc/mc.c | 10 ++
include/fsl-mc/fsl_mc.h | 1 +
5 files changed, 99 insertions(+), 9 deletions(-)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..96f0871 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -738,11 +738,26 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -759,7 +774,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index ce419df..3af83f9 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -409,11 +409,27 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ int i;
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@@ -430,7 +446,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, 2);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 3875d04..b44ca3f 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -30,6 +30,9 @@
#include "../common/emc2305.h"
#endif
+#define TRUE 1
+#define FALSE 0
+
#ifdef CONFIG_TARGET_LX2160AQDS
#define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
#define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
@@ -520,11 +523,26 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memor
[U-Boot] [PATCH] drivers: net: mc: Report extra memory to Linux
MC firmware need to be aligned to 512M, so minimum 512MB DDR is reserved.
But MC support to work with 128MB or 256MB DDR memory also, in this
case, rest of the memory is not usable.
So reporting this extra memory to Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/ls1088a/ls1088a.c | 31 ---
board/freescale/ls2080ardb/ls2080ardb.c | 32 +---
board/freescale/lx2160a/lx2160a.c | 31 ---
drivers/net/fsl-mc/mc.c | 10 ++
include/fsl-mc/fsl_mc.h | 1 +
5 files changed, 96 insertions(+), 9 deletions(-)
diff --git a/board/freescale/ls1088a/ls1088a.c
b/board/freescale/ls1088a/ls1088a.c
index 6d11a13..96f0871 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -738,11 +738,26 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
base[i] = gd->bd->bi_dram[i].start;
@@ -759,7 +774,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c
b/board/freescale/ls2080ardb/ls2080ardb.c
index ce419df..3af83f9 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -409,11 +409,27 @@ void fsl_fdt_fixup_flash(void *fdt)
int ft_board_setup(void *blob, bd_t *bd)
{
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ int i;
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
+
+ base = calloc(total_memory_banks, sizeof(u64));
+ size = calloc(total_memory_banks, sizeof(u64));
+
/* fixup DT for the two GPP DDR banks */
base[0] = gd->bd->bi_dram[0].start;
size[0] = gd->bd->bi_dram[0].size;
@@ -430,7 +446,17 @@ int ft_board_setup(void *blob, bd_t *bd)
size[1] = gd->arch.resv_ram - base[1];
#endif
- fdt_fixup_memory_banks(blob, base, size, 2);
+ if (mc_memory_base != 0) {
+ for (i = 0; i <= total_memory_banks; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = mc_memory_base;
+ size[i] = mc_memory_size;
+ break;
+ }
+ }
+ }
+
+ fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
fdt_fsl_mc_fixup_iommu_map_entry(blob);
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index 3875d04..93b5204 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -520,11 +520,26 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
- u64 base[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
+ bool mc_memory_bank = false;
+
+ u64 *base;
+ u64 *size;
+ u64 mc_memory_base = 0;
+ u64 mc_memory_size = 0;
+ u16 total_memory_banks;
ft_cpu_setup(blob, bd);
+ fdt_fixup_mc_ddr(_memory_base, _memory_size);
+
+ if (mc_memory_base != 0)
+ mc_memory_bank = true;
+
+ total_memory_banks = CONF
[U-Boot] [PATCH v3] MC : Report extra reserved memory to Linux
For MC, 512 MB DDR is reserved because of MC's alignment
requirement.
But for MC binaries needing 128MB or 256MB DDR memory, rest
of the memory is a waste. So reporting this extra memory to
Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
Reviewed-by: Ashish Kumar
---
board/freescale/lx2160a/lx2160a.c | 28 +++-
drivers/net/fsl-mc/mc.c | 13 +
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index ad72eed..b763f6d 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -532,8 +532,15 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
+ bool mc_memory_bank = false;
+
+#ifdef CONFIG_FSL_MC_ENET
+ u64 base[CONFIG_NR_DRAM_BANKS + 1];
+ u64 size[CONFIG_NR_DRAM_BANKS + 1];
+#else
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
+#endif
ft_cpu_setup(blob, bd);
@@ -556,7 +563,26 @@ int ft_board_setup(void *blob, bd_t *bd)
size[2] = gd->arch.resv_ram - base[2];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_mc_ddr([3], [3]);
+
+ if (base[3] != 0) {
+ for (i = 0; i <= CONFIG_NR_DRAM_BANKS; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = base[3];
+ size[i] = size[3];
+ break;
+ }
+ }
+ if (i == CONFIG_NR_DRAM_BANKS)
+ mc_memory_bank = true;
+ }
+#endif
+ if (mc_memory_bank)
+ fdt_fixup_memory_banks(
+blob, base, size, CONFIG_NR_DRAM_BANKS + 1);
+ else
+ fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
#ifdef CONFIG_USB
fsl_fdt_fixup_dr_usb(blob, bd);
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index dddc9cc..d7a2e8f 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -285,6 +285,19 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
MC_FIXUP_DPL);
}
+void fdt_fixup_mc_ddr(u64 *base, u64 *size)
+{
+ u64 mc_size = mc_get_dram_block_size();
+
+ if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
+ *base = mc_get_dram_addr() + mc_size;
+ *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
+ } else {
+ *base = 0;
+ *size = 0;
+ }
+}
+
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index aef40d3..492a714 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -54,6 +54,7 @@ struct mc_ccsr_registers {
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
+void fdt_fixup_mc_ddr(u64 *base, u64 *size);
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
--
1.9.1
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[U-Boot] [PATCH v2] MC : Report extra reserved memory to Linux
For MC, 512 MB DDR is reserved because of MC's alignment
requirement.
But for MC binaries needing 128MB or 256MB DDR memory, rest
of the memory is a waste. So reporting this extra memory to
Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/lx2160a/lx2160a.c | 28 +++-
drivers/net/fsl-mc/mc.c | 13 +
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index ad72eed..b763f6d 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -532,8 +532,15 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
+ bool mc_memory_bank = false;
+
+#ifdef CONFIG_FSL_MC_ENET
+ u64 base[CONFIG_NR_DRAM_BANKS + 1];
+ u64 size[CONFIG_NR_DRAM_BANKS + 1];
+#else
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
+#endif
ft_cpu_setup(blob, bd);
@@ -556,7 +563,26 @@ int ft_board_setup(void *blob, bd_t *bd)
size[2] = gd->arch.resv_ram - base[2];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_mc_ddr([3], [3]);
+
+ if (base[3] != 0) {
+ for (i = 0; i <= CONFIG_NR_DRAM_BANKS; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = base[3];
+ size[i] = size[3];
+ break;
+ }
+ }
+ if (i == CONFIG_NR_DRAM_BANKS)
+ mc_memory_bank = true;
+ }
+#endif
+ if (mc_memory_bank)
+ fdt_fixup_memory_banks(
+blob, base, size, CONFIG_NR_DRAM_BANKS + 1);
+ else
+ fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
#ifdef CONFIG_USB
fsl_fdt_fixup_dr_usb(blob, bd);
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index dddc9cc..d7a2e8f 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -285,6 +285,19 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
MC_FIXUP_DPL);
}
+void fdt_fixup_mc_ddr(u64 *base, u64 *size)
+{
+ u64 mc_size = mc_get_dram_block_size();
+
+ if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
+ *base = mc_get_dram_addr() + mc_size;
+ *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
+ } else {
+ *base = 0;
+ *size = 0;
+ }
+}
+
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index aef40d3..492a714 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -54,6 +54,7 @@ struct mc_ccsr_registers {
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
+void fdt_fixup_mc_ddr(u64 *base, u64 *size);
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
--
1.9.1
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Re: [U-Boot] [PATCH v2] board/fsl/lx2160a: Fix MC firmware loading during SD boot
+1 > -Original Message- > From: Pankaj Bansal > Sent: Tuesday, March 12, 2019 10:27 AM > To: Meenakshi Aggarwal ; Priyanka Jain > ; Prabhakar Kushwaha > > Cc: u-boot@lists.denx.de; Pankaj Bansal > Subject: [PATCH v2] board/fsl/lx2160a: Fix MC firmware loading during SD boot > > Issue: during SD boot, following error comes: > MMC read: dev # 0, block # 20480, count 2048 ... 2048 blocks read: OK > > MMC read: dev # 0, block # 28672, count 2048 ... 2048 blocks read: OK > fsl-mc: ERR: Bad firmware image (bad FIT header) > Hit any key to stop autoboot: 0 > > Cause: mc 10.14.3 file size is 1064880, the value is 0x820 blocks which is > more > than 0x800. The default DPC loading address 0x8010 has overlap with MC > loading address 0x8000, since the size of MC is over 1MB. > > Fix: update the MC and dpc address as per their addresses in XSPI flash. > i.e. in xspi flash MC address is 0x20a0 so corresponding address in dram > when loading MC firmware from mmc is 0x80a0. similarly dpc is @ > 0x20e0 in xspi flash and 0x80e0 in dram when loaded from mmc. > > This same approach is being followed in other cases also in same file, e.g. > esbc_validate 0x8074 <=> esbc_validate 0x2074 > > On same lines modify the address of dpl to 0x80d0 > > Signed-off-by: Pankaj Bansal > --- > > Notes: > V2: > - reduce the mc firmware size blocks from 0x1800 to 0x1200, to save on > boot time > - Fix the commit message to indicate that the patch is for LX2160A boards > only and for SD boot only > > include/configs/lx2160a_common.h | 10 +- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/include/configs/lx2160a_common.h > b/include/configs/lx2160a_common.h > index 17cfd7bfd7..98af24a45d 100644 > --- a/include/configs/lx2160a_common.h > +++ b/include/configs/lx2160a_common.h > @@ -217,14 +217,14 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); > "fsl_mc start mc 0x20a0 0x20e0\0" > > #define SD_MC_INIT_CMD \ > - "mmc read 0x8000 0x5000 0x800;" \ > - "mmc read 0x8010 0x7000 0x800;" \ > + "mmc read 0x80a0 0x5000 0x1200;"\ > + "mmc read 0x80e0 0x7000 0x800;" \ > "env exists secureboot && " \ > "mmc read 0x8070 0x3800 0x10 && " \ > "mmc read 0x8074 0x3A00 0x10 && " \ > "esbc_validate 0x8070 && " \ > "esbc_validate 0x8074 ;"\ > - "fsl_mc start mc 0x8000 0x8010\0" > + "fsl_mc start mc 0x80a0 0x80e0\0" > > #define EXTRA_ENV_SETTINGS \ > "hwconfig=fsl_ddr:bank_intlv=auto\0"\ > @@ -289,11 +289,11 @@ int select_i2c_ch_pca9547_sec(unsigned char ch); > > #define SD_BOOTCOMMAND \ > "env exists mcinitcmd && mmcinfo; " \ > - "mmc read 0x80001000 0x6800 0x800; "\ > + "mmc read 0x80d0 0x6800 0x800; "\ > "env exists mcinitcmd && env exists secureboot "\ > " && mmc read 0x8078 0x3C00 0x10 " \ > "&& esbc_validate 0x8078;env exists mcinitcmd " \ > - "&& fsl_mc lazyapply dpl 0x80001000;" \ > + "&& fsl_mc lazyapply dpl 0x80d0;" \ > "run distro_bootcmd;run sd_bootcmd;"\ > "env exists secureboot && esbc_halt;" > > -- > 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] MC : Report extra reserved memory to Linux
For MC, 512 MB DDR is reserved because of MC's alignment
requirement.
But for MC binaries needing 128MB or 256MB DDR memory, rest
of the memory is a waste. So reporting this extra memory to
Linux through dtb memory fixup.
Signed-off-by: Meenakshi Aggarwal
---
board/freescale/lx2160a/lx2160a.c | 27 ++-
drivers/net/fsl-mc/mc.c | 13 +
include/fsl-mc/fsl_mc.h | 1 +
3 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
b/board/freescale/lx2160a/lx2160a.c
index ad72eed..3cbb7d1 100644
--- a/board/freescale/lx2160a/lx2160a.c
+++ b/board/freescale/lx2160a/lx2160a.c
@@ -532,8 +532,15 @@ void board_quiesce_devices(void)
int ft_board_setup(void *blob, bd_t *bd)
{
int i;
+ bool mc_memory_bank = false;
+
+#ifdef CONFIG_FSL_MC_ENET
+ u64 base[CONFIG_NR_DRAM_BANKS + 1];
+ u64 size[CONFIG_NR_DRAM_BANKS + 1];
+#else
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
+#endif
ft_cpu_setup(blob, bd);
@@ -556,7 +563,25 @@ int ft_board_setup(void *blob, bd_t *bd)
size[2] = gd->arch.resv_ram - base[2];
#endif
- fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
+#ifdef CONFIG_FSL_MC_ENET
+ fdt_fixup_mc_ddr([3], [3]);
+
+ if (base[3] != 0) {
+ for (i = 0; i <= CONFIG_NR_DRAM_BANKS; i++) {
+ if (base[i] == 0 && size[i] == 0) {
+ base[i] = base[3];
+ size[i] = size[3];
+ break;
+ }
+ }
+ if (i == CONFIG_NR_DRAM_BANKS)
+ mc_memory_bank = true;
+ }
+#endif
+ if (mc_memory_bank)
+ fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS +
1);
+ else
+ fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
#ifdef CONFIG_USB
fsl_fdt_fixup_dr_usb(blob, bd);
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index dddc9cc..79a38d6 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -285,6 +285,19 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
MC_FIXUP_DPL);
}
+void fdt_fixup_mc_ddr(u64* base, u64* size)
+{
+ u64 mc_size = mc_get_dram_block_size();
+
+ if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) {
+ *base = mc_get_dram_addr() + mc_size;
+ *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size;
+ } else {
+ *base = 0;
+ *size = 0;
+ }
+}
+
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
{
u32 *prop;
diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h
index aef40d3..30f961b 100644
--- a/include/fsl-mc/fsl_mc.h
+++ b/include/fsl-mc/fsl_mc.h
@@ -54,6 +54,7 @@ struct mc_ccsr_registers {
void fdt_fsl_mc_fixup_iommu_map_entry(void *blob);
int get_mc_boot_status(void);
int get_dpl_apply_status(void);
+void fdt_fixup_mc_ddr(u64 *base, u64* size);
#ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET
int get_aiop_apply_status(void);
#endif
--
1.9.1
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Re: [U-Boot] [PATCH 1/2] cmd: efidebug: add memmap command
Please ignore, it is sent by mistake.
> -Original Message-
> From: U-Boot On Behalf Of Meenakshi
> Aggarwal
> Sent: Wednesday, February 27, 2019 2:41 PM
> To: u-boot@lists.denx.de; Prabhakar Kushwaha
>
> Subject: [U-Boot] [PATCH 1/2] cmd: efidebug: add memmap command
>
> From: AKASHI Takahiro
>
> "memmap" command prints uefi-specific memory map information.
> => efi memmap
> Type StartEnd Attributes
> ==
> CONVENTIONAL 4000-7de27000 WB
> RUNTIME DATA 7de27000-7de28000 WB|RT
> RESERVED 7de28000-7de2a000 WB
> RUNTIME DATA 7de2a000-7de2b000 WB|RT
> RESERVED 7de2b000-7de2c000 WB
> RUNTIME DATA 7de2c000-7de2d000 WB|RT
> LOADER DATA 7de2d000-7ff37000 WB
> RUNTIME CODE 7ff37000-7ff38000 WB|RT
> LOADER DATA 7ff38000-8000 WB
>
> Signed-off-by: AKASHI Takahiro
> Reviewed-by: Heinrich Schuchardt
> ---
> cmd/efidebug.c | 127
> -
> 1 file changed, 126 insertions(+), 1 deletion(-)
>
> diff --git a/cmd/efidebug.c b/cmd/efidebug.c index e3a2d09..5072a7b 100644
> --- a/cmd/efidebug.c
> +++ b/cmd/efidebug.c
> @@ -335,6 +335,127 @@ static int do_efi_show_images(cmd_tbl_t *cmdtp, int
> flag,
> return CMD_RET_SUCCESS;
> }
>
> +static const char * const efi_mem_type_string[] = {
> + [EFI_RESERVED_MEMORY_TYPE] = "RESERVED",
> + [EFI_LOADER_CODE] = "LOADER CODE",
> + [EFI_LOADER_DATA] = "LOADER DATA",
> + [EFI_BOOT_SERVICES_CODE] = "BOOT CODE",
> + [EFI_BOOT_SERVICES_DATA] = "BOOT DATA",
> + [EFI_RUNTIME_SERVICES_CODE] = "RUNTIME CODE",
> + [EFI_RUNTIME_SERVICES_DATA] = "RUNTIME DATA",
> + [EFI_CONVENTIONAL_MEMORY] = "CONVENTIONAL",
> + [EFI_UNUSABLE_MEMORY] = "UNUSABLE MEM",
> + [EFI_ACPI_RECLAIM_MEMORY] = "ACPI RECLAIM MEM",
> + [EFI_ACPI_MEMORY_NVS] = "ACPI NVS",
> + [EFI_MMAP_IO] = "IO",
> + [EFI_MMAP_IO_PORT] = "IO PORT",
> + [EFI_PAL_CODE] = "PAL",
> +};
> +
> +static const struct efi_mem_attrs {
> + const u64 bit;
> + const char *text;
> +} efi_mem_attrs[] = {
> + {EFI_MEMORY_UC, "UC"},
> + {EFI_MEMORY_UC, "UC"},
> + {EFI_MEMORY_WC, "WC"},
> + {EFI_MEMORY_WT, "WT"},
> + {EFI_MEMORY_WB, "WB"},
> + {EFI_MEMORY_UCE, "UCE"},
> + {EFI_MEMORY_WP, "WP"},
> + {EFI_MEMORY_RP, "RP"},
> + {EFI_MEMORY_XP, "WP"},
> + {EFI_MEMORY_NV, "NV"},
> + {EFI_MEMORY_MORE_RELIABLE, "REL"},
> + {EFI_MEMORY_RO, "RO"},
> + {EFI_MEMORY_RUNTIME, "RT"},
> +};
> +
> +/**
> + * print_memory_attributes() - print memory map attributes
> + * @attributes: Attribute value
> + *
> + * Print memory map attributes
> + */
> +static void print_memory_attributes(u64 attributes) {
> + int sep, i;
> +
> + for (sep = 0, i = 0; i < ARRAY_SIZE(efi_mem_attrs); i++)
> + if (attributes & efi_mem_attrs[i].bit) {
> + if (sep) {
> + putc('|');
> + } else {
> + putc(' ');
> + sep = 1;
> + }
> + puts(efi_mem_attrs[i].text);
> + }
> +}
> +
> +#define EFI_PHYS_ADDR_WIDTH (int)(sizeof(efi_physical_addr_t) * 2)
> +
> +/**
> + * do_efi_show_memmap() - show UEFI memory map
> + *
> + * @cmdtp: Command table
> + * @flag:Command flag
> + * @argc:Number of arguments
> + * @argv:Argument array
> + * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on
> failure
> + *
> + * Implement efidebug "memmap" sub-command.
> + * Show UEFI memory map.
> + */
> +static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag,
> + int argc, char * const argv[]) {
> + struct efi_mem_desc *memmap = NULL, *map;
> + efi_uintn_t map_size = 0;
> + const char *type;
> + int i;
> + efi_status_t ret;
> +
> + ret = EFI_CALL(BS->get_memory_map(_size, memmap, NULL,
> NULL, NULL));
> + if (ret == EFI_BUFFER_TOO_SMALL) {
> + map_size += sizeof(struct efi_mem_desc); /* for my
[U-Boot] [PATCH 2/2] mc : Reduce MC memory size to 128M
ls2088, ls1088 : minimum MC Memory size is 128 MB
lx2 : minimum MC memory size is 256 MB
Signed-off-by: Meenakshi Aggarwal
---
drivers/net/fsl-mc/mc.c | 23 +++
include/configs/ls1088a_common.h | 2 +-
include/configs/ls2080a_common.h | 2 +-
include/configs/lx2160a_common.h | 2 +-
4 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index a51b8a4..a56edc3 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -28,6 +28,7 @@
#define MC_MEM_SIZE_ENV_VAR"mcmemsize"
#define MC_BOOT_TIMEOUT_ENV_VAR"mcboottimeout"
#define MC_BOOT_ENV_VAR"mcinitcmd"
+#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
DECLARE_GLOBAL_DATA_PTR;
static int mc_memset_resv_ram;
@@ -680,7 +681,8 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
size_t mc_ram_size = mc_get_dram_block_size();
mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
- if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
+
+ if (mc_ram_num_256mb_blocks >= 0xff) {
error = -EINVAL;
printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
mc_ram_size);
@@ -688,6 +690,13 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
}
/*
+* To support 128 MB DDR Size for MC
+*/
+ if (mc_ram_num_256mb_blocks == 0) {
+ mc_ram_num_256mb_blocks = 0xFF;
+ }
+
+ /*
* Management Complex cores should be held at reset out of POR.
* U-Boot should be the first software to touch MC. To be safe,
* we reset all cores again by setting GCR1 to 0. It doesn't do
@@ -727,8 +736,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
/*
* Tell MC what is the address range of the DRAM block assigned to it:
*/
- reg_mcfbalr = (u32)mc_ram_addr |
- (mc_ram_num_256mb_blocks - 1);
+ if (mc_ram_num_256mb_blocks < 0xFF) {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks - 1);
+ } else {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks);
+ }
+
out_le32(_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(_ccsr_regs->reg_mcfbahr,
(u32)(mc_ram_addr >> 32));
@@ -878,7 +893,7 @@ unsigned long mc_get_dram_block_size(void)
"\' environment variable: %lu\n",
dram_block_size);
- dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+ dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
}
}
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index b663937..fa9c8c8 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -151,7 +151,7 @@ unsigned long long get_qixis_addr(void);
*/
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */
#define CONFIG_CMD_CACHE
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index 0a6c90d..682f068 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -155,7 +155,7 @@ unsigned long long get_qixis_addr(void);
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 4b5608b..637619c 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -100,7 +100,7 @@
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
#endif
/* I2C bus multiplexer */
--
1.9.1
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[U-Boot] [PATCH 1/2] cmd: efidebug: add memmap command
From: AKASHI Takahiro
"memmap" command prints uefi-specific memory map information.
=> efi memmap
Type StartEnd Attributes
==
CONVENTIONAL 4000-7de27000 WB
RUNTIME DATA 7de27000-7de28000 WB|RT
RESERVED 7de28000-7de2a000 WB
RUNTIME DATA 7de2a000-7de2b000 WB|RT
RESERVED 7de2b000-7de2c000 WB
RUNTIME DATA 7de2c000-7de2d000 WB|RT
LOADER DATA 7de2d000-7ff37000 WB
RUNTIME CODE 7ff37000-7ff38000 WB|RT
LOADER DATA 7ff38000-8000 WB
Signed-off-by: AKASHI Takahiro
Reviewed-by: Heinrich Schuchardt
---
cmd/efidebug.c | 127 -
1 file changed, 126 insertions(+), 1 deletion(-)
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index e3a2d09..5072a7b 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -335,6 +335,127 @@ static int do_efi_show_images(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_SUCCESS;
}
+static const char * const efi_mem_type_string[] = {
+ [EFI_RESERVED_MEMORY_TYPE] = "RESERVED",
+ [EFI_LOADER_CODE] = "LOADER CODE",
+ [EFI_LOADER_DATA] = "LOADER DATA",
+ [EFI_BOOT_SERVICES_CODE] = "BOOT CODE",
+ [EFI_BOOT_SERVICES_DATA] = "BOOT DATA",
+ [EFI_RUNTIME_SERVICES_CODE] = "RUNTIME CODE",
+ [EFI_RUNTIME_SERVICES_DATA] = "RUNTIME DATA",
+ [EFI_CONVENTIONAL_MEMORY] = "CONVENTIONAL",
+ [EFI_UNUSABLE_MEMORY] = "UNUSABLE MEM",
+ [EFI_ACPI_RECLAIM_MEMORY] = "ACPI RECLAIM MEM",
+ [EFI_ACPI_MEMORY_NVS] = "ACPI NVS",
+ [EFI_MMAP_IO] = "IO",
+ [EFI_MMAP_IO_PORT] = "IO PORT",
+ [EFI_PAL_CODE] = "PAL",
+};
+
+static const struct efi_mem_attrs {
+ const u64 bit;
+ const char *text;
+} efi_mem_attrs[] = {
+ {EFI_MEMORY_UC, "UC"},
+ {EFI_MEMORY_UC, "UC"},
+ {EFI_MEMORY_WC, "WC"},
+ {EFI_MEMORY_WT, "WT"},
+ {EFI_MEMORY_WB, "WB"},
+ {EFI_MEMORY_UCE, "UCE"},
+ {EFI_MEMORY_WP, "WP"},
+ {EFI_MEMORY_RP, "RP"},
+ {EFI_MEMORY_XP, "WP"},
+ {EFI_MEMORY_NV, "NV"},
+ {EFI_MEMORY_MORE_RELIABLE, "REL"},
+ {EFI_MEMORY_RO, "RO"},
+ {EFI_MEMORY_RUNTIME, "RT"},
+};
+
+/**
+ * print_memory_attributes() - print memory map attributes
+ * @attributes:Attribute value
+ *
+ * Print memory map attributes
+ */
+static void print_memory_attributes(u64 attributes)
+{
+ int sep, i;
+
+ for (sep = 0, i = 0; i < ARRAY_SIZE(efi_mem_attrs); i++)
+ if (attributes & efi_mem_attrs[i].bit) {
+ if (sep) {
+ putc('|');
+ } else {
+ putc(' ');
+ sep = 1;
+ }
+ puts(efi_mem_attrs[i].text);
+ }
+}
+
+#define EFI_PHYS_ADDR_WIDTH (int)(sizeof(efi_physical_addr_t) * 2)
+
+/**
+ * do_efi_show_memmap() - show UEFI memory map
+ *
+ * @cmdtp: Command table
+ * @flag: Command flag
+ * @argc: Number of arguments
+ * @argv: Argument array
+ * Return: CMD_RET_SUCCESS on success, CMD_RET_RET_FAILURE on failure
+ *
+ * Implement efidebug "memmap" sub-command.
+ * Show UEFI memory map.
+ */
+static int do_efi_show_memmap(cmd_tbl_t *cmdtp, int flag,
+ int argc, char * const argv[])
+{
+ struct efi_mem_desc *memmap = NULL, *map;
+ efi_uintn_t map_size = 0;
+ const char *type;
+ int i;
+ efi_status_t ret;
+
+ ret = EFI_CALL(BS->get_memory_map(_size, memmap, NULL, NULL, NULL));
+ if (ret == EFI_BUFFER_TOO_SMALL) {
+ map_size += sizeof(struct efi_mem_desc); /* for my own */
+ ret = EFI_CALL(BS->allocate_pool(EFI_LOADER_DATA,
+map_size, (void *)));
+ if (ret != EFI_SUCCESS)
+ return CMD_RET_FAILURE;
+ ret = EFI_CALL(BS->get_memory_map(_size, memmap,
+ NULL, NULL, NULL));
+ }
+ if (ret != EFI_SUCCESS) {
+ EFI_CALL(BS->free_pool(memmap));
+ return CMD_RET_FAILURE;
+ }
+
+ printf("Type Start%.*s End%.*s Attributes\n",
+ EFI_PHYS_ADDR_WIDTH - 5, spc, EFI_PHYS_ADDR_WIDTH - 3, spc);
+ printf(" %.*s %.*s ==\n",
+ EFI_PHYS_ADDR_WIDTH, sep, EFI_PHYS_ADDR_WIDTH, sep);
+ for (i = 0, map = memmap; i < map_size / sizeof(*map); map++, i++) {
+ if (map->type < EFI_MAX_MEMORY_TYPE)
+ type = efi_mem_type_string[map->type];
+ else
+ type = "(unknown)";
+
+ printf("%-16s %.*llx-%.*llx",
Re: [U-Boot] [PATCH v1] mc : Add support to run MC in 128 MB DDR size
> -Original Message-
> From: Ashish Kumar
> Sent: Tuesday, February 26, 2019 12:08 PM
> To: Meenakshi Aggarwal ; u-
> b...@lists.denx.de
> Subject: RE: [U-Boot] [PATCH v1] mc : Add support to run MC in 128 MB DDR
> size
>
>
> > -Original Message-
> > From: U-Boot On Behalf Of Meenakshi
> > Aggarwal
> > Sent: Wednesday, February 20, 2019 3:36 PM
> > To: u-boot@lists.denx.de
> > Subject: [U-Boot] [PATCH v1] mc : Add support to run MC in 128 MB DDR
> > size
> Ashish: Rephrase to "Reduce MC memory size to 128M" from the above it sound
> like system DDR is 128MB
>
Ok
> Regards
> Ashish
> >
> > ls2088, ls1088 : minimum DDR size for MC is 128 MB
> > lx2 : minimum DDR size for MC is 256 MB
> >
> > Signed-off-by: Meenakshi Aggarwal
> > ---
> > drivers/net/fsl-mc/mc.c | 23 +++
> > include/configs/ls1088a_common.h | 2 +-
> > include/configs/ls2080a_common.h
> > | 2 +- include/configs/lx2160a_common.h | 2 +-
> > 4 files changed, 22 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index
> > d0b8c03..7ba44cd 100644
> > --- a/drivers/net/fsl-mc/mc.c
> > +++ b/drivers/net/fsl-mc/mc.c
> > @@ -28,6 +28,7 @@
> > #define MC_MEM_SIZE_ENV_VAR"mcmemsize"
> > #define MC_BOOT_TIMEOUT_ENV_VAR"mcboottimeout"
> > #define MC_BOOT_ENV_VAR"mcinitcmd"
> > +#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
> >
> > DECLARE_GLOBAL_DATA_PTR;
> > static int mc_memset_resv_ram;
> > @@ -683,7 +684,8 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
> > size_t mc_ram_size = mc_get_dram_block_size();
> >
> > mc_ram_num_256mb_blocks = mc_ram_size /
> MC_RAM_SIZE_ALIGNMENT;
> > - if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks >
> > 0xff) {
> > +
> > + if (mc_ram_num_256mb_blocks >= 0xff) {
> > error = -EINVAL;
> > printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
> >mc_ram_size);
> > @@ -691,6 +693,13 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
> > }
> >
> > /*
> > +* To support 128 MB DDR Size for MC
> > +*/
> > + if (mc_ram_num_256mb_blocks == 0) {
> > + mc_ram_num_256mb_blocks = 0xFF;
> > + }
> > +
> > + /*
> > * Management Complex cores should be held at reset out of POR.
> > * U-Boot should be the first software to touch MC. To be safe,
> > * we reset all cores again by setting GCR1 to 0. It doesn't do @@
> > -730,8
> > +739,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
> > /*
> > * Tell MC what is the address range of the DRAM block assigned to it:
> > */
> > - reg_mcfbalr = (u32)mc_ram_addr |
> > - (mc_ram_num_256mb_blocks - 1);
> > + if (mc_ram_num_256mb_blocks < 0xFF) {
> > + reg_mcfbalr = (u32)mc_ram_addr |
> > + (mc_ram_num_256mb_blocks - 1);
> > + } else {
> > + reg_mcfbalr = (u32)mc_ram_addr |
> > + (mc_ram_num_256mb_blocks);
> > + }
> > +
> > out_le32(_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
> > out_le32(_ccsr_regs->reg_mcfbahr,
> > (u32)(mc_ram_addr >> 32));
> > @@ -876,7 +891,7 @@ unsigned long mc_get_dram_block_size(void)
> >"\' environment variable: %lu\n",
> >dram_block_size);
> >
> > - dram_block_size =
> > CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
> > + dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
> > }
> > }
> >
> > diff --git a/include/configs/ls1088a_common.h
> > b/include/configs/ls1088a_common.h
> > index 89133c2..1509292 100644
> > --- a/include/configs/ls1088a_common.h
> > +++ b/include/configs/ls1088a_common.h
> > @@ -154,7 +154,7 @@ unsigned long long get_qixis_addr(void);
> > */
> >
> > #if defined(CONFIG_FSL_MC_ENET)
> > -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
> (512UL *
> > 1024 * 1024)
> > +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
> (128UL *
> > 1024 * 1024)
> > #endif
> > /* Command line configuration */
> > #define CONFIG_CMD_CACHE
> > diff --git a/include/configs/ls2080a_common.h
> > b/include/configs/ls2080a_common.h
> > index ab38981..7c1
[U-Boot] [PATCH v1] mc : Add support to run MC in 128 MB DDR size
ls2088, ls1088 : minimum DDR size for MC is 128 MB
lx2 : minimum DDR size for MC is 256 MB
Signed-off-by: Meenakshi Aggarwal
---
drivers/net/fsl-mc/mc.c | 23 +++
include/configs/ls1088a_common.h | 2 +-
include/configs/ls2080a_common.h | 2 +-
include/configs/lx2160a_common.h | 2 +-
4 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index d0b8c03..7ba44cd 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -28,6 +28,7 @@
#define MC_MEM_SIZE_ENV_VAR"mcmemsize"
#define MC_BOOT_TIMEOUT_ENV_VAR"mcboottimeout"
#define MC_BOOT_ENV_VAR"mcinitcmd"
+#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
DECLARE_GLOBAL_DATA_PTR;
static int mc_memset_resv_ram;
@@ -683,7 +684,8 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
size_t mc_ram_size = mc_get_dram_block_size();
mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
- if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
+
+ if (mc_ram_num_256mb_blocks >= 0xff) {
error = -EINVAL;
printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
mc_ram_size);
@@ -691,6 +693,13 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
}
/*
+* To support 128 MB DDR Size for MC
+*/
+ if (mc_ram_num_256mb_blocks == 0) {
+ mc_ram_num_256mb_blocks = 0xFF;
+ }
+
+ /*
* Management Complex cores should be held at reset out of POR.
* U-Boot should be the first software to touch MC. To be safe,
* we reset all cores again by setting GCR1 to 0. It doesn't do
@@ -730,8 +739,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
/*
* Tell MC what is the address range of the DRAM block assigned to it:
*/
- reg_mcfbalr = (u32)mc_ram_addr |
- (mc_ram_num_256mb_blocks - 1);
+ if (mc_ram_num_256mb_blocks < 0xFF) {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks - 1);
+ } else {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks);
+ }
+
out_le32(_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(_ccsr_regs->reg_mcfbahr,
(u32)(mc_ram_addr >> 32));
@@ -876,7 +891,7 @@ unsigned long mc_get_dram_block_size(void)
"\' environment variable: %lu\n",
dram_block_size);
- dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+ dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
}
}
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 89133c2..1509292 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -154,7 +154,7 @@ unsigned long long get_qixis_addr(void);
*/
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */
#define CONFIG_CMD_CACHE
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index ab38981..7c1d35b 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -159,7 +159,7 @@ unsigned long long get_qixis_addr(void);
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 0f1a621..c4bbe96 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -102,7 +102,7 @@
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
#endif
/* I2C bus multiplexer */
--
1.9.1
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Re: [U-Boot] [PATCH] L3 cache : arch : arm : lib : Flush L3 after relocation
> -Original Message- > From: Prabhakar Kushwaha > Sent: Monday, February 18, 2019 6:37 PM > To: Meenakshi Aggarwal ; u- > b...@lists.denx.de; York Sun > Cc: Meenakshi Aggarwal ; Udit Kumar > > Subject: RE: [PATCH] L3 cache : arch : arm : lib : Flush L3 after relocation > > > > -Original Message- > > From: Meenakshi Aggarwal > > Sent: Tuesday, February 19, 2019 12:09 AM > > To: u-boot@lists.denx.de; Prabhakar Kushwaha > > ; York Sun > > Cc: Meenakshi Aggarwal ; Udit Kumar > > > > Subject: [PATCH] L3 cache : arch : arm : lib : Flush L3 after > > relocation > > > > Flush L3 cache after uboot relocated to DDR. > > > > Signed-off-by: Meenakshi Aggarwal > > Signed-off-by: Udit Kumar > > --- > > arch/arm/lib/relocate_64.S | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S > > index > > 171d094..7603f52 100644 > > --- a/arch/arm/lib/relocate_64.S > > +++ b/arch/arm/lib/relocate_64.S > > @@ -85,6 +85,7 @@ relocate_done: > > isb sy > > 4: ldp x0, x1, [sp, #16] > > bl __asm_flush_dcache_range > > + bl __asm_flush_l3_dcache > > This change is happening for every arm platform. > > There can be platform not having l3 cache. How It is taken care? > This function is defined as weak in arch/arm/cpu/armv8/cache.S for all other platforms except arch/arm/mach-mvebu/armada8k/cache_llc.S arch/arm/mach-tegra/tegra186/cache.S > --pk ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] L3 cache : arch : arm : lib : Flush L3 after relocation
Flush L3 cache after uboot relocated to DDR. Signed-off-by: Meenakshi Aggarwal Signed-off-by: Udit Kumar --- arch/arm/lib/relocate_64.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/lib/relocate_64.S b/arch/arm/lib/relocate_64.S index 171d094..7603f52 100644 --- a/arch/arm/lib/relocate_64.S +++ b/arch/arm/lib/relocate_64.S @@ -85,6 +85,7 @@ relocate_done: isb sy 4: ldp x0, x1, [sp, #16] bl __asm_flush_dcache_range + bl __asm_flush_l3_dcache 5: ldp x29, x30, [sp],#32 ret ENDPROC(relocate_code) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2] armv8 : fsl-layerscape : Fix hang when TFA is used.
When TFA is used as EL3 firmware, then u-boot is crashing
because DDR is not coherent.
Changing DDR memory attributes to device type fix the issue.
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Udit Kumar
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index be21685..32f3d2a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -100,9 +100,10 @@ static struct mm_region early_map[] = {
#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
-#if defined(CONFIG_TFABOOT) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#if defined(CONFIG_TFABOOT)
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE)
+#elif defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
+ PTE_BLOCK_MEMTYPE(MT_NORMAL)
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
#endif
--
1.9.1
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[U-Boot] [PATCH] mc : Add support to run MC in 128 MB DDR size
ls2088, ls1088 : minimum DDR size for MC is 128 MB
lx2 : minimum DDR size for MC is 256 MB
Alignment of MC Base Address is as per the MC size.
Signed-off-by: Meenakshi Aggarwal
---
drivers/net/fsl-mc/mc.c | 56 +++-
include/configs/ls1088a_common.h | 2 +-
include/configs/ls2080a_common.h | 2 +-
include/configs/lx2160a_common.h | 2 +-
4 files changed, 52 insertions(+), 10 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index d0b8c03..708472c 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -21,13 +21,24 @@
#include
#include
-#define MC_RAM_BASE_ADDR_ALIGNMENT (512UL * 1024 * 1024)
-#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK(~(MC_RAM_BASE_ADDR_ALIGNMENT -
1))
+#define MC_RAM_BASE_ADDR_ALIGNMENT_128 (128UL * 1024 * 1024)
+#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK_128 \
+ (~(MC_RAM_BASE_ADDR_ALIGNMENT_128 - 1))
+
+#define MC_RAM_BASE_ADDR_ALIGNMENT_256 (256UL * 1024 * 1024)
+#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK_256 \
+ (~(MC_RAM_BASE_ADDR_ALIGNMENT_256 - 1))
+
+#define MC_RAM_BASE_ADDR_ALIGNMENT_512 (512UL * 1024 * 1024)
+#define MC_RAM_BASE_ADDR_ALIGNMENT_MASK_512 \
+ (~(MC_RAM_BASE_ADDR_ALIGNMENT_512 - 1))
+
#define MC_RAM_SIZE_ALIGNMENT (256UL * 1024 * 1024)
#define MC_MEM_SIZE_ENV_VAR"mcmemsize"
#define MC_BOOT_TIMEOUT_ENV_VAR"mcboottimeout"
#define MC_BOOT_ENV_VAR"mcinitcmd"
+#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
DECLARE_GLOBAL_DATA_PTR;
static int mc_memset_resv_ram;
@@ -683,7 +694,15 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
size_t mc_ram_size = mc_get_dram_block_size();
mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
- if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
+
+ /*
+* To support 128 MB DDR Size for MC
+*/
+ if (mc_ram_num_256mb_blocks == 0) {
+ mc_ram_num_256mb_blocks = 0xFF;
+ }
+
+ if (mc_ram_num_256mb_blocks > 0xff) {
error = -EINVAL;
printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
mc_ram_size);
@@ -730,8 +749,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
/*
* Tell MC what is the address range of the DRAM block assigned to it:
*/
- reg_mcfbalr = (u32)mc_ram_addr |
- (mc_ram_num_256mb_blocks - 1);
+ if (mc_ram_num_256mb_blocks < 0xFF) {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks - 1);
+ } else {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks);
+ }
+
out_le32(_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(_ccsr_regs->reg_mcfbahr,
(u32)(mc_ram_addr >> 32));
@@ -838,6 +863,21 @@ int get_dpl_apply_status(void)
}
/*
+ * Return alignment for MC base address
+ */
+unsigned long get_base_address_alignment(unsigned long mc_ram_size)
+{
+ if (mc_ram_size == MC_RAM_BASE_ADDR_ALIGNMENT_128) {
+ return MC_RAM_BASE_ADDR_ALIGNMENT_MASK_128;
+ } else if (mc_ram_size > MC_RAM_BASE_ADDR_ALIGNMENT_128 &&
+mc_ram_size <= MC_RAM_BASE_ADDR_ALIGNMENT_256) {
+ return MC_RAM_BASE_ADDR_ALIGNMENT_MASK_256;
+ } else {
+ return MC_RAM_BASE_ADDR_ALIGNMENT_MASK_512;
+ }
+}
+
+/*
* Return the MC address of private DRAM block.
* As per MC design document, MC initial base address
* should be least significant 512MB address of MC private
@@ -847,14 +887,16 @@ int get_dpl_apply_status(void)
u64 mc_get_dram_addr(void)
{
size_t mc_ram_size = mc_get_dram_block_size();
+ unsigned long mc_alignment;
if (!mc_memset_resv_ram || (get_mc_boot_status() < 0)) {
mc_memset_resv_ram = 1;
memset((void *)gd->arch.resv_ram, 0, mc_ram_size);
}
+ mc_alignment = get_base_address_alignment(mc_ram_size);
return (gd->arch.resv_ram + mc_ram_size - 1) &
- MC_RAM_BASE_ADDR_ALIGNMENT_MASK;
+ mc_alignment;
}
/**
@@ -876,7 +918,7 @@ unsigned long mc_get_dram_block_size(void)
"\' environment variable: %lu\n",
dram_block_size);
- dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
+ dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
}
}
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 89133c2..1509292 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -154,7 +154,7 @@ unsigned long long get_qixis_addr(void);
*/
[U-Boot] [PATCH] Fix : Uboot crash when booting from SD.
Issue : In case of SD boot, u-boot was crashing due to DDR was not
coherent
Fix : Making DDR as device memory will make sure DDR is coherent
when we are relocating the code
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Udit Kumar
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b..cb1abf3 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -102,7 +102,7 @@ static struct mm_region early_map[] = {
CONFIG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_TFABOOT) || \
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
- PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
#else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
#endif
--
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Re: [U-Boot] [PATCH] mc : Add support to run MC in 128 MB DDR size
> -Original Message-
> From: Ashish Kumar
> Sent: Tuesday, February 12, 2019 10:12 AM
> To: Meenakshi Aggarwal ; u-
> b...@lists.denx.de; Prabhakar Kushwaha
> Cc: Meenakshi Aggarwal
> Subject: RE: [PATCH] mc : Add support to run MC in 128 MB DDR size
>
>
>
> > -Original Message-
> > From: Meenakshi Aggarwal
> > Sent: Tuesday, February 12, 2019 2:44 PM
> > To: u-boot@lists.denx.de; Prabhakar Kushwaha
> >
> > Cc: Meenakshi Aggarwal
> > Subject: [PATCH] mc : Add support to run MC in 128 MB DDR size
> Ashish: Rephrase to "Reduce MC memory size to 128M" from the above it sound
> like system DDR is 128MB
> >
> > ls2088, ls1088 : minimum DDR size for MC is 128 MB
> > lx2 : minimum DDR size for MC is 256 MB
> >
> > Signed-off-by: Meenakshi Aggarwal
> > ---
> > drivers/net/fsl-mc/mc.c | 20 +---
> > include/configs/ls1088a_common.h | 2 +-
> > include/configs/ls2080a_common.h
> > | 2 +- include/configs/lx2160a_common.h | 2 +-
> > 4 files changed, 20 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index
> > fa0a05d..98c57ed 100644
> > --- a/drivers/net/fsl-mc/mc.c
> > +++ b/drivers/net/fsl-mc/mc.c
> > @@ -684,7 +684,15 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
> > size_t mc_ram_size = mc_get_dram_block_size();
> >
> > mc_ram_num_256mb_blocks = mc_ram_size /
> MC_RAM_SIZE_ALIGNMENT;
> > - if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks >
> > 0xff) {
> > +
> > + /*
> > +* To support 128 MB DDR Size for MC
> > +*/
> Ashish: How does the MC grow now, wrt to MC base ?.
> Earlier it was 2 blocks of 256 up and rest down.
No changes done in this respect, it is same as before depending on MC size.
For 128 MB, we are reserving only 128 M up and rest down.
> Considering MC base alignment is 512. 256 MB is always wasted from top of the
> memory, now since the minimum block is 128MB
We are reserving only DDR memory according to the size of MC, so if it is 128
M,
then we are reserving only 128 M (surely, base address is 512 MB aligned).
Rest DDR memory is available for uboot to use and is marked as free.
> > + if (mc_ram_num_256mb_blocks == 0) {
> > + mc_ram_num_256mb_blocks = 0xFF;
> > + }
> > +
> > + if (mc_ram_num_256mb_blocks > 0xff) {
> > error = -EINVAL;
> > printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
> >mc_ram_size);
> > @@ -731,8 +739,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
> > /*
> > * Tell MC what is the address range of the DRAM block assigned to it:
> > */
> > - reg_mcfbalr = (u32)mc_ram_addr |
> > - (mc_ram_num_256mb_blocks - 1);
> > + if (mc_ram_num_256mb_blocks < 0xFF) {
> > + reg_mcfbalr = (u32)mc_ram_addr |
> > + (mc_ram_num_256mb_blocks - 1);
> > + } else {
> > + reg_mcfbalr = (u32)mc_ram_addr |
> > + (mc_ram_num_256mb_blocks);
> > + }
> > +
> > out_le32(_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
> > out_le32(_ccsr_regs->reg_mcfbahr,
> > (u32)(mc_ram_addr >> 32));
> > diff --git a/include/configs/ls1088a_common.h
> > b/include/configs/ls1088a_common.h
> > index 89133c2..1509292 100644
> > --- a/include/configs/ls1088a_common.h
> > +++ b/include/configs/ls1088a_common.h
> > @@ -154,7 +154,7 @@ unsigned long long get_qixis_addr(void);
> > */
> >
> > #if defined(CONFIG_FSL_MC_ENET)
> > -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
> (512UL *
> > 1024 * 1024)
> > +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
> (128UL *
> > 1024 * 1024)
> > #endif
> > /* Command line configuration */
> > #define CONFIG_CMD_CACHE
> > diff --git a/include/configs/ls2080a_common.h
> > b/include/configs/ls2080a_common.h
> > index ab38981..7c1d35b 100644
> > --- a/include/configs/ls2080a_common.h
> > +++ b/include/configs/ls2080a_common.h
> > @@ -159,7 +159,7 @@ unsigned long long get_qixis_addr(void);
> > * 512MB aligned, so the min size to hide is 512MB.
> > */
> > #ifdef CONFIG_FSL_MC_ENET
> > -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
> (512UL *
> > 1024 * 1024)
> > +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE
> (128UL *
> > 1024 * 1024)
> > #endif
> >
> > /* Command line configuration */
> >
[U-Boot] [PATCH] mc : Add support to run MC in 128 MB DDR size
ls2088, ls1088 : minimum DDR size for MC is 128 MB
lx2 : minimum DDR size for MC is 256 MB
Signed-off-by: Meenakshi Aggarwal
---
drivers/net/fsl-mc/mc.c | 20 +---
include/configs/ls1088a_common.h | 2 +-
include/configs/ls2080a_common.h | 2 +-
include/configs/lx2160a_common.h | 2 +-
4 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index fa0a05d..98c57ed 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -684,7 +684,15 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
size_t mc_ram_size = mc_get_dram_block_size();
mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
- if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
+
+ /*
+* To support 128 MB DDR Size for MC
+*/
+ if (mc_ram_num_256mb_blocks == 0) {
+ mc_ram_num_256mb_blocks = 0xFF;
+ }
+
+ if (mc_ram_num_256mb_blocks > 0xff) {
error = -EINVAL;
printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
mc_ram_size);
@@ -731,8 +739,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
/*
* Tell MC what is the address range of the DRAM block assigned to it:
*/
- reg_mcfbalr = (u32)mc_ram_addr |
- (mc_ram_num_256mb_blocks - 1);
+ if (mc_ram_num_256mb_blocks < 0xFF) {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks - 1);
+ } else {
+ reg_mcfbalr = (u32)mc_ram_addr |
+ (mc_ram_num_256mb_blocks);
+ }
+
out_le32(_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
out_le32(_ccsr_regs->reg_mcfbahr,
(u32)(mc_ram_addr >> 32));
diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h
index 89133c2..1509292 100644
--- a/include/configs/ls1088a_common.h
+++ b/include/configs/ls1088a_common.h
@@ -154,7 +154,7 @@ unsigned long long get_qixis_addr(void);
*/
#if defined(CONFIG_FSL_MC_ENET)
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */
#define CONFIG_CMD_CACHE
diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h
index ab38981..7c1d35b 100644
--- a/include/configs/ls2080a_common.h
+++ b/include/configs/ls2080a_common.h
@@ -159,7 +159,7 @@ unsigned long long get_qixis_addr(void);
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
#endif
/* Command line configuration */
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h
index 0f1a621..c4bbe96 100644
--- a/include/configs/lx2160a_common.h
+++ b/include/configs/lx2160a_common.h
@@ -102,7 +102,7 @@
* 512MB aligned, so the min size to hide is 512MB.
*/
#ifdef CONFIG_FSL_MC_ENET
-#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
+#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
#endif
/* I2C bus multiplexer */
--
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Re: [U-Boot] [PATCH 1/2] armv8: emc2305: add support for fan controller
Gentle reminter
> -Original Message-
> From: Meenakshi Aggarwal
> Sent: Friday, November 30, 2018 10:32 PM
> To: u-boot@lists.denx.de; York Sun
> Cc: Meenakshi Aggarwal
> Subject: [PATCH 1/2] armv8: emc2305: add support for fan controller
>
> Add support for fan controller emc2305.
>
> Signed-off-by: Sriram Dash
> Signed-off-by: Meenakshi Aggarwal
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +
> board/freescale/common/Makefile | 2 ++
> board/freescale/common/emc2305.c | 41
> +++
> board/freescale/common/emc2305.h | 23 +
> 4 files changed, 72 insertions(+)
> create mode 100644 board/freescale/common/emc2305.c create mode
> 100644 board/freescale/common/emc2305.h
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 5dba2af..b0e779d 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -346,6 +346,12 @@ config MAX_CPUS
> cores, count the reserved ports. This will allocate enough memory
> in spin table to properly handle all cores.
>
> +config EMC2305
> + bool "Fan controller"
> + help
> + Enable the EMC2305 fan controller for configuration of fan
> + speed.
> +
> config SECURE_BOOT
> bool "Secure Boot"
> help
> diff --git a/board/freescale/common/Makefile
> b/board/freescale/common/Makefile index e3c5eae..a9d61a8 100644
> --- a/board/freescale/common/Makefile
> +++ b/board/freescale/common/Makefile
> @@ -64,6 +64,8 @@ obj-$(CONFIG_POWER_MC34VR500) +=
> mc34vr500.o
>
> obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o
>
> +obj-$(CONFIG_EMC2305) += emc2305.o
> +
> # deal with common files for P-series corenet based devices
> obj-$(CONFIG_TARGET_P2041RDB)+= p_corenet/
> obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
> diff --git a/board/freescale/common/emc2305.c
> b/board/freescale/common/emc2305.c
> new file mode 100644
> index 000..8523084
> --- /dev/null
> +++ b/board/freescale/common/emc2305.c
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#include "emc2305.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void set_fan_speed(u8 data)
> +{
> + u8 index;
> + u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
> +I2C_EMC2305_FAN2,
> +I2C_EMC2305_FAN3,
> +I2C_EMC2305_FAN4,
> +I2C_EMC2305_FAN5};
> +
> + for (index = 0; index < NUM_OF_FANS; index++) {
> + if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, , 1) != 0)
> {
> + printf("Error: failed to change fan speed @%x\n",
> +Fan[index]);
> + }
> + }
> +}
> +
> +void emc2305_init(void)
> +{
> + u8 data;
> +
> + data = I2C_EMC2305_CMD;
> + if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, , 1) !=
> 0)
> + printf("Error: failed to configure EMC2305\n"); }
> diff --git a/board/freescale/common/emc2305.h
> b/board/freescale/common/emc2305.h
> new file mode 100644
> index 000..eddf537
> --- /dev/null
> +++ b/board/freescale/common/emc2305.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __EMC2305_H_
> +#define __EMC2305_H_
> +
> +#define I2C_EMC2305_CONF 0x20
> +#define I2C_EMC2305_FAN1 0x30
> +#define I2C_EMC2305_FAN2 0x40
> +#define I2C_EMC2305_FAN3 0x50
> +#define I2C_EMC2305_FAN4 0x60
> +#define I2C_EMC2305_FAN5 0x70
> +
> +#define NUM_OF_FANS 5
> +
> +void emc2305_init(void);
> +void set_fan_speed(u8 data);
> +
> +#endif /* __EMC2305_H_ */
> --
> 1.9.1
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[U-Boot] [PATCH 2/2] lx2160: Enable support of EMC2305
Enable support for FAN controller EMC2305 for LX2160A RDB board. Signed-off-by: Sriram Dash Signed-off-by: Meenakshi Aggarwal --- board/freescale/lx2160a/lx2160a.c | 11 +++ include/configs/lx2160ardb.h | 6 ++ 2 files changed, 17 insertions(+) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 530f658..07ca58e 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -26,6 +26,10 @@ #include "../common/vid.h" #include +#ifdef CONFIG_EMC2305 +#include "../common/emc2305.h" +#endif + #ifdef CONFIG_TARGET_LX2160AQDS #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) @@ -93,6 +97,13 @@ int board_early_init_f(void) /* get required clock for UART IP */ uart_get_clock(); +#ifdef CONFIG_EMC2305 + select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305); + emc2305_init(); + set_fan_speed(I2C_EMC2305_PWM); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +#endif + fsl_lsch3_early_init_f(); return 0; } diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 67d214d..818aa38 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -70,6 +70,12 @@ #endif +/* EMC2305 */ +#define I2C_MUX_CH_EMC2305 0x09 +#define I2C_EMC2305_ADDR 0x4D +#define I2C_EMC2305_CMD0x40 +#define I2C_EMC2305_PWM0x80 + /* EEPROM */ #define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] armv8: emc2305: add support for fan controller
Add support for fan controller emc2305.
Signed-off-by: Sriram Dash
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +
board/freescale/common/Makefile | 2 ++
board/freescale/common/emc2305.c | 41 +++
board/freescale/common/emc2305.h | 23 +
4 files changed, 72 insertions(+)
create mode 100644 board/freescale/common/emc2305.c
create mode 100644 board/freescale/common/emc2305.h
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5dba2af..b0e779d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -346,6 +346,12 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
+config EMC2305
+ bool "Fan controller"
+ help
+Enable the EMC2305 fan controller for configuration of fan
+speed.
+
config SECURE_BOOT
bool "Secure Boot"
help
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index e3c5eae..a9d61a8 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -64,6 +64,8 @@ obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
obj-$(CONFIG_LS102XA_STREAM_ID)+= ls102xa_stream_id.o
+obj-$(CONFIG_EMC2305) += emc2305.o
+
# deal with common files for P-series corenet based devices
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c
new file mode 100644
index 000..8523084
--- /dev/null
+++ b/board/freescale/common/emc2305.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+#include "emc2305.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void set_fan_speed(u8 data)
+{
+ u8 index;
+ u8 Fan[NUM_OF_FANS] = {I2C_EMC2305_FAN1,
+ I2C_EMC2305_FAN2,
+ I2C_EMC2305_FAN3,
+ I2C_EMC2305_FAN4,
+ I2C_EMC2305_FAN5};
+
+ for (index = 0; index < NUM_OF_FANS; index++) {
+ if (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, , 1) != 0) {
+ printf("Error: failed to change fan speed @%x\n",
+ Fan[index]);
+ }
+ }
+}
+
+void emc2305_init(void)
+{
+ u8 data;
+
+ data = I2C_EMC2305_CMD;
+ if (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, , 1) != 0)
+ printf("Error: failed to configure EMC2305\n");
+}
diff --git a/board/freescale/common/emc2305.h b/board/freescale/common/emc2305.h
new file mode 100644
index 000..eddf537
--- /dev/null
+++ b/board/freescale/common/emc2305.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EMC2305_H_
+#define __EMC2305_H_
+
+#define I2C_EMC2305_CONF 0x20
+#define I2C_EMC2305_FAN1 0x30
+#define I2C_EMC2305_FAN2 0x40
+#define I2C_EMC2305_FAN3 0x50
+#define I2C_EMC2305_FAN4 0x60
+#define I2C_EMC2305_FAN5 0x70
+
+#define NUM_OF_FANS5
+
+void emc2305_init(void);
+void set_fan_speed(u8 data);
+
+#endif /* __EMC2305_H_ */
--
1.9.1
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[U-Boot] [PATCH] armv8: emc2305: add support for fan controller
Add support for fan controller emc2305.
Enable support of FAN controller for LX2160A RDB board.
Signed-off-by: Meenakshi Aggarwal
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 22 +
board/freescale/common/Makefile | 2 +
board/freescale/common/emc2305.c | 75 +++
board/freescale/common/emc2305.h | 20 +
board/freescale/lx2160a/lx2160a.c | 9
5 files changed, 128 insertions(+)
create mode 100644 board/freescale/common/emc2305.c
create mode 100644 board/freescale/common/emc2305.h
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 5dba2af..d746e78 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -346,6 +346,28 @@ config MAX_CPUS
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
+config EMC2305
+ bool "Fan controller"
+ help
+Enable the EMC2305 fan controller for configuration of fan
+speed.
+
+config I2C_MUX_CH_EMC2305
+ hex "I2C channel where EMC2305 is connected"
+ default 0x9 if ARCH_LX2160A
+
+config I2C_EMC2305_ADDR
+ hex "I2C channel where EMC2305 is connected"
+ default 0x4D if ARCH_LX2160A
+
+config I2C_EMC2305_CMD
+ hex "EMC2305 made I2C compliant"
+ default 0x40 if ARCH_LX2160A
+
+config I2C_EMC2305_PWM
+ hex "Speed settings for Fan controller"
+ default 0x80 if ARCH_LX2160A
+
config SECURE_BOOT
bool "Secure Boot"
help
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index e3c5eae..a9d61a8 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -64,6 +64,8 @@ obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o
obj-$(CONFIG_LS102XA_STREAM_ID)+= ls102xa_stream_id.o
+obj-$(CONFIG_EMC2305) += emc2305.o
+
# deal with common files for P-series corenet based devices
obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/
obj-$(CONFIG_TARGET_P3041DS) += p_corenet/
diff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c
new file mode 100644
index 000..46f43e0
--- /dev/null
+++ b/board/freescale/common/emc2305.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#ifdef CONFIG_FSL_LSCH2
+#include
+#elif defined(CONFIG_FSL_LSCH3)
+#include
+#else
+#include
+#endif
+#include "emc2305.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void configure_emc2305(void)
+{
+ u8 data;
+
+ data = CONFIG_I2C_EMC2305_CMD;
+ if (i2c_write(CONFIG_I2C_EMC2305_ADDR,
+ I2C_EMC2305_CONF, 1, , 1) != 0){
+ printf("Error: failed to configure I2C fan @%x\n",
+ CONFIG_I2C_EMC2305_ADDR);
+ }
+}
+
+void set_fan_speed(void)
+{
+ u8 data;
+
+ data = CONFIG_I2C_EMC2305_PWM;
+ if (i2c_write(CONFIG_I2C_EMC2305_ADDR,
+ I2C_EMC2305_FAN1, 1, , 1) != 0){
+ printf("Error: failed to change fan speed @%x\n",
+ I2C_EMC2305_FAN1);
+ }
+
+ if (i2c_write(CONFIG_I2C_EMC2305_ADDR,
+ I2C_EMC2305_FAN2, 1, , 1) != 0){
+ printf("Error: failed to change fan speed @%x\n",
+ I2C_EMC2305_FAN2);
+ }
+
+ if (i2c_write(CONFIG_I2C_EMC2305_ADDR,
+ I2C_EMC2305_FAN3, 1, , 1) != 0){
+ printf("Error: failed to change fan speed @%x\n",
+ I2C_EMC2305_FAN3);
+ }
+
+ if (i2c_write(CONFIG_I2C_EMC2305_ADDR,
+ I2C_EMC2305_FAN4, 1, , 1) != 0){
+ printf("Error: failed to change fan speed @%x\n",
+ I2C_EMC2305_FAN4);
+ }
+
+ if (i2c_write(CONFIG_I2C_EMC2305_ADDR,
+ I2C_EMC2305_FAN5, 1, , 1) != 0){
+ printf("Error: failed to change fan speed @%x\n",
+ I2C_EMC2305_FAN5);
+ }
+}
+
+void emc2305_init(void)
+{
+ configure_emc2305();
+ set_fan_speed();
+}
diff --git a/board/freescale/common/emc2305.h b/board/freescale/common/emc2305.h
new file mode 100644
index 000..ebbe20f
--- /dev/null
+++ b/board/freescale/common/emc2305.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __EMC2305_H_
+#define __EMC2305_H_
+
+#define I2C_EMC2305_CONF 0x20
+#define I2C_EMC2305_FAN1 0x30
+#define I2C_EMC2305_FAN2 0x40
+#define I2C_EMC2305_FAN3 0x50
+#define I2C_EMC2305_FAN4 0x60
+#define
