Re: [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
Hi,
2008/8/20 thaoth [EMAIL PROTECTED]:
Hi Nobuhiro Iwamatsu,
1. Clock frequency of board.
#define CONFIG_SYS_CLK_FREQ
#define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */
#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
I don't understand how to set CONFIG_SYS_CLK_FREQ value. From T-Engine
support, they said clock frequency of board is 144MHz.
Please set outside clock to CONFIG_SYS_CLK_FREQ.
2. Cross compiler tool chain : GCC vs T-Engine toolchain
There are two tool chains
-
http://www.superh-linux.org/archive/bsp/sh7721_se/toolchain_sh3_gcc4.2.tar.gz
support elf32-sh-linux target.
- Tool chain from T-Engine forum support elf32-sh-tkernel
Using both cross compilers, we could turn on LED on debug board by setting
correct value LED_A and LED_B value.
3. ICE or JTAG debugger and LED debugging.
I don't have these debug tools, and so hard for debugging. T-Engine/SH7727
DevKit has debug board with 8 LEDs. I could turn on/off these LEDs by
setting correct value to 0xA160 memory. But C function turn on/off LED
cannot work. For example
int cpu_init(void)
{
// Turn off LED 1 to notify cpu_init is called.
outw(0x00 0xFF, 0xa160);
return 0;
}
I don't know why it isn't called?
I think that cpu_init is not carried out.
I think that u-boot stopped on lowlevel_init function.
Would you please give me your ideas? Thank you a lot.
I will get T-Engine board ..
Please wait.
Best regards,
Nobuhiro
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[U-Boot] [PATCH] sh: Renesas Solutions AP325RXA board support
From 1f6ce000f4071e86bb6bfead6e7d30efa84f3824 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu [EMAIL PROTECTED] Date: Fri, 22 Aug 2008 17:39:09 +0900 Subject: [PATCH] sh: Renesas Solutions AP325RXA board support AP325RXA is SH7723's reference board. This has SCIF, NOR Flash, Ethernet, USB host, LCDC, SD Host, Camera and other. In this patch, support SCIF, NOR Flash, and Ethernet. Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- MAINTAINERS|1 + MAKEALL|1 + Makefile |5 + board/ap325rxa/Makefile| 51 + board/ap325rxa/ap325rxa.c | 162 ++ board/ap325rxa/config.mk | 26 + board/ap325rxa/cpld-ap325rxa.c | 206 ++ board/ap325rxa/lowlevel_init.S | 243 board/ap325rxa/u-boot.lds | 106 + include/configs/ap325rxa.h | 177 + 10 files changed, 978 insertions(+), 0 deletions(-) create mode 100644 board/ap325rxa/Makefile create mode 100644 board/ap325rxa/ap325rxa.c create mode 100644 board/ap325rxa/config.mk create mode 100644 board/ap325rxa/cpld-ap325rxa.c create mode 100644 board/ap325rxa/lowlevel_init.S create mode 100644 board/ap325rxa/u-boot.lds create mode 100644 include/configs/ap325rxa.h diff --git a/MAINTAINERS b/MAINTAINERS index 323a3a6..0f2e33c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -739,6 +739,7 @@ Nobuhiro Iwamatsu [EMAIL PROTECTED] R7780MP SH7780 R2DPlus SH7751R SH7763RDP SH7763 + AP320A SH7723 Mark Jonas [EMAIL PROTECTED] diff --git a/MAKEALL b/MAKEALL index ad68152..3fca1bb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -748,6 +748,7 @@ LIST_sh4= \ r7780mp \ r2dplus \ sh7763rdp \ + ap325rxa\ LIST_sh= \ diff --git a/Makefile b/Makefile index 24700f9..1fa869e 100644 --- a/Makefile +++ b/Makefile @@ -3025,6 +3025,11 @@ sh7763rdp_config : unconfig @echo #define CONFIG_SH7763RDP 1 $(obj)include/config.h @./mkconfig -a $(@:_config=) sh sh4 sh7763rdp +ap325rxa_config : unconfig + @mkdir -p $(obj)include + @echo #define CONFIG_AP325RXA 1 $(obj)include/config.h + @./mkconfig -a $(@:_config=) sh sh4 ap325rxa + # # SPARC # diff --git a/board/ap325rxa/Makefile b/board/ap325rxa/Makefile new file mode 100644 index 000..21f3e6e --- /dev/null +++ b/board/ap325rxa/Makefile @@ -0,0 +1,51 @@ +# +# +# Copyright (C) 2008 Renesas Solutions Corp. +# Copyright (C) 2008 Nobuhiro Iwamatsu [EMAIL PROTECTED] +# +# board/ap325rxa/Makefile +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := ap325rxa.o cpld-ap325rxa.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/ap325rxa/ap325rxa.c b/board/ap325rxa/ap325rxa.c new file mode 100644 index 000..cfa0261 --- /dev/null +++ b/board/ap325rxa/ap325rxa.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2008 Renesas Solutions Corp. + * Copyright (C) 2008 Nobuhiro Iwamatsu [EMAIL PROTECTED] + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT
[U-Boot] [PATCH 1/2] net: smc911x: Add pkt_data_pull and pkt_data_push function
The RSK7203 board has the SMSC9118 wired up 'incorrectly'. Byte-swapping is necessary, and so poor performance is inevitable. This problem cannot evade by the swap function of CHIP, this can evade by software Byte-swapping. And this has problem by FIFO access only. pkt_data_pull/pkt_data_push functions necessary to solve this problem. Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- drivers/net/smc911x.c |9 +++-- 1 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 0fff820..648c94c 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -57,6 +57,11 @@ static inline void reg_write(u32 addr, u32 val) #error SMC911X: undefined bus width #endif /* CONFIG_DRIVER_SMC911X_16_BIT */ +u32 pkt_data_pull(u32 addr) \ + __attribute__ ((weak, alias (reg_read))); +void pkt_data_push(u32 addr, u32 val) \ + __attribute__ ((weak, alias (reg_write))); + #define mdelay(n) udelay((n)*1000) /* Below are the register offsets and bit definitions @@ -641,7 +646,7 @@ int eth_send(volatile void *packet, int length) tmplen = (length + 3) / 4; while (tmplen--) - reg_write(TX_DATA_FIFO, *data++); + pkt_data_push(TX_DATA_FIFO, *data++); /* wait for transmission */ while (!((reg_read(TX_FIFO_INF) TX_FIFO_INF_TSUSED) 16)); @@ -684,7 +689,7 @@ int eth_rx(void) tmplen = (pktlen + 2+ 3) / 4; while (tmplen--) - *data++ = reg_read(RX_DATA_FIFO); + *data++ = pkt_data_pull(RX_DATA_FIFO); if (status RX_STS_ES) printf(DRIVERNAME -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Add support sh2 to MAKEALL
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- MAKEALL |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/MAKEALL b/MAKEALL index 56cc38d..752ed68 100755 --- a/MAKEALL +++ b/MAKEALL @@ -803,7 +803,7 @@ do |mips|mips_el \ |nios|nios2 \ |ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \ - |sh|sh3|sh4 \ + |sh|sh2|sh3|sh4 \ |sparc \ |x86|I486 \ ) -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Fix compile error sh7785lcr board
This boards used old type preprocessor.
This patch fix compile error.
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED]
---
include/configs/sh7785lcr.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
index e27c5d1..c4cb065 100644
--- a/include/configs/sh7785lcr.h
+++ b/include/configs/sh7785lcr.h
@@ -76,7 +76,7 @@
#define CFG_BAUDRATE_TABLE { 115200 }
/* SCIF */
-#define CFG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_CONSOLE1
#define CONFIG_CONS_SCIF1 1
#define CONFIG_SCIF_EXT_CLOCK 1
#undef CFG_CONSOLE_INFO_QUIET
@@ -103,8 +103,8 @@
#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
#undef CFG_FLASH_QUIET_TEST
#define CFG_FLASH_EMPTY_INFO
#define CFG_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
--
1.5.6.3
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[U-Boot] [PATCH] sh: Remove CC line from board's Makefile
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- board/rsk7203/Makefile |3 --- board/sh7785lcr/Makefile |3 --- 2 files changed, 0 insertions(+), 6 deletions(-) diff --git a/board/rsk7203/Makefile b/board/rsk7203/Makefile index a44f9ca..7365d19 100644 --- a/board/rsk7203/Makefile +++ b/board/rsk7203/Makefile @@ -37,9 +37,6 @@ distclean:clean # -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $@ - # defines $(obj).depend target include $(SRCTREE)/rules.mk diff --git a/board/sh7785lcr/Makefile b/board/sh7785lcr/Makefile index 43688d5..b1b538c 100644 --- a/board/sh7785lcr/Makefile +++ b/board/sh7785lcr/Makefile @@ -34,9 +34,6 @@ distclean:clean # -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) $@ - # defines $(obj).depend target include $(SRCTREE)/rules.mk -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [T-Engine] UBoot configuration for T-Engine/SH7727 MS7727CP02 DevKit
Hi, thaoth. Shimoda-san is USB developper on U-Boot in Renesas. Shimoda-san, please give us comments this problem. Best regards, Nobuhiro On Wed, 10 Sep 2008 04:51:40 -0700 (PDT) thaoth [EMAIL PROTECTED] wrote: Hi, I got USB issue and here is an error message: ERROR: CTL:TIMEOUT USB device not responding, giving up (status=20) 3 USB Device(s) found scanning bus for storage devices... 0 Storage Device(s) found For detail, TEngine/SH7727 has one USB host controller, when I plugged USB Flash Memory there were 3 devices. And No unplugged USB device, they said 2 devices. -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Remove re-defined CONFIG_FLASH_CFI_DRIVER from config
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- include/configs/ap325rxa.h |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 3db609b..c961908 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -117,7 +117,6 @@ /* FLASH */ #define CONFIG_FLASH_CFI_DRIVER 1 #define CFG_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER #undef CFG_FLASH_QUIET_TEST /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_EMPTY_INFO -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Fix compile error for r2dplus
netdev.h was not include by r2dplus. Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- board/r2dplus/r2dplus.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c index b962dd1..4e0c66a 100644 --- a/board/r2dplus/r2dplus.c +++ b/board/r2dplus/r2dplus.c @@ -23,6 +23,7 @@ #include common.h #include ide.h +#include netdev.h #include asm/processor.h #include asm/io.h #include asm/pci.h -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Add support any page size and empty_zero_page to SH Linux uImage
Old U-Boot supported 4KB page size only. If this version, Linux
kernel can not get command line from U-Boot.
SH Linux kernel can change page size and empty_zero_page.
This patch support this function and fix promlem.
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED]
---
lib_sh/bootm.c | 44 ++--
1 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/lib_sh/bootm.c b/lib_sh/bootm.c
index bc1c3da..d5056ae 100644
--- a/lib_sh/bootm.c
+++ b/lib_sh/bootm.c
@@ -2,6 +2,9 @@
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, [EMAIL PROTECTED]
*
+ * (c) Copyright 2008 Nobuhiro Iwamatsu [EMAIL PROTECTED]
+ * (c) Copyright 2008 Renesas Solutions Corp.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -25,47 +28,36 @@
#include command.h
#include asm/byteorder.h
-/* The SH kernel reads arguments from the empty zero page at location
- * 0 at the start of SDRAM. The following are copied from
- * arch/sh/kernel/setup.c and may require tweaking if the kernel sources
- * change.
- */
-#define PARAM ((unsigned char *)CFG_SDRAM_BASE + 0x1000)
-
-#define MOUNT_ROOT_RDONLY (*(unsigned long *) (PARAM+0x000))
-#define RAMDISK_FLAGS (*(unsigned long *) (PARAM+0x004))
-#define ORIG_ROOT_DEV (*(unsigned long *) (PARAM+0x008))
-#define LOADER_TYPE (*(unsigned long *) (PARAM+0x00c))
-#define INITRD_START (*(unsigned long *) (PARAM+0x010))
-#define INITRD_SIZE (*(unsigned long *) (PARAM+0x014))
-/* ... */
-#define COMMAND_LINE ((char *) (PARAM+0x100))
-
-#define RAMDISK_IMAGE_START_MASK 0x07FF
-
#ifdef CFG_DEBUG
-static void hexdump (unsigned char *buf, int len)
+static void hexdump(unsigned char *buf, int len)
{
int i;
for (i = 0; i len; i++) {
if ((i % 16) == 0)
- printf (%s%08x: , i ? \n : , (unsigned int)
buf[i]);
- printf (%02x , buf[i]);
+ printf(%s%08x: , i ? \n : ,
+ (unsigned int)buf[i]);
+ printf(%02x , buf[i]);
}
- printf (\n);
+ printf(\n);
}
#endif
int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
{
- char*bootargs = getenv(bootargs);
-
+ /* Linux kernel load address */
void (*kernel) (void) = (void (*)(void))images-ep;
+ /* empty_zero_page */
+ unsigned char *param = (unsigned char *)image_get_ep(images);
+ /* Linux kernel command line */
+ unsigned char *cmdline = param + 0x100;
+ /* PAGE_SIZE */
+ unsigned long size = images-ep - image_get_ep(images);
+ char *bootargs = getenv(bootargs);
/* Setup parameters */
- memset(PARAM, 0, 0x1000); /* Clear zero page */
- strcpy(COMMAND_LINE, bootargs);
+ memset(param, 0, size); /* Clear zero page */
+ strcpy(cmdline, bootargs);
kernel();
/* does not return */
--
1.5.6.3
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[U-Boot] [PATCH] sh: Fix typo in SH console driver
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- drivers/serial/serial_sh.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 61c2b82..f30532b 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -76,7 +76,7 @@ # define FIFOLEVEL_MASK0xFF # endif #elif defined(CONFIG_CPU_SH7723) -# if defined(CONIFG_SCIF_A) +# if defined(CONFIG_SCIF_A) # define SCLSR SCFSR # define LSR_ORER 0x0200 # define FIFOLEVEL_MASK0x3F -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Add support watchdog for SH4A core
Add support watchdog for SH4A core (SH7763, SH7780 and SH7785).
And fix some compile warning.
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED]
---
cpu/sh4/watchdog.c | 48
lib_sh/board.c | 89 +++-
2 files changed, 87 insertions(+), 50 deletions(-)
diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c
index 346e217..6fbb069 100644
--- a/cpu/sh4/watchdog.c
+++ b/cpu/sh4/watchdog.c
@@ -17,32 +17,52 @@
#include common.h
#include asm/processor.h
+#include asm/io.h
#define WDT_BASE WTCNT
-static unsigned char cnt_read (void){
- return *((volatile unsigned char *)(WDT_BASE + 0x00));
+#define WDT_WD (1 6)
+#define WDT_RST_P (0)
+#define WDT_RST_M (1 5)
+#define WDT_ENABLE (1 7)
+
+#if defined(CONFIG_WATCHDOG)
+static unsigned char csr_read (void)
+{
+ return inb(WDT_BASE + 0x04);
}
-static unsigned char csr_read (void){
- return *((volatile unsigned char *)(WDT_BASE + 0x04));
+static void cnt_write (unsigned char value)
+{
+ outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
}
-static void cnt_write (unsigned char value){
- while (csr_read() (1 5)) {
- /* delay */
- }
- *((volatile unsigned short *)(WDT_BASE + 0x00))
- = ((unsigned short) value) | 0x5A00;
+static void csr_write (unsigned char value)
+{
+ outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
}
-static void csr_write (unsigned char value){
- *((volatile unsigned short *)(WDT_BASE + 0x04))
- = ((unsigned short) value) | 0xA500;
+void watchdog_reset(void)
+{
+ outl(0x5500, WDT_BASE + 0x08);
}
+int watchdog_init (void)
+{
+ /* Set overflow time*/
+ cnt_write(0);
+ /* Power on reset */
+ csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
+
+ return 0;
+}
-int watchdog_init (void){ return 0; }
+int watchdog_disable (void)
+{
+ csr_write(csr_read() ~WDT_ENABLE);
+ return 0;
+}
+#endif
void reset_cpu (unsigned long ignored)
{
diff --git a/lib_sh/board.c b/lib_sh/board.c
index eb81bd9..c678120 100644
--- a/lib_sh/board.c
+++ b/lib_sh/board.c
@@ -23,6 +23,7 @@
#include malloc.h
#include devices.h
#include version.h
+#include watchdog.h
#include net.h
#include environment.h
@@ -30,7 +31,6 @@ extern void malloc_bin_reloc (void);
extern int cpu_init(void);
extern int board_init(void);
extern int dram_init(void);
-extern int watchdog_init(void);
extern int timer_init(void);
const char version_string[] = U_BOOT_VERSION ( __DATE__ - __TIME__ );
@@ -70,37 +70,45 @@ static int sh_flash_init(void)
DECLARE_GLOBAL_DATA_PTR;
gd-bd-bi_flashsize = flash_init();
- printf(FLASH: %dMB\n, gd-bd-bi_flashsize / (1024*1024));
+ printf(FLASH: %ldMB\n, gd-bd-bi_flashsize / (1024*1024));
return 0;
}
#if defined(CONFIG_CMD_NAND)
-#include nand.h
-static int sh_nand_init(void)
-{
- printf(NAND: );
- nand_init();/* go init the NAND */
- return 0;
-}
+# include nand.h
+# define INIT_FUNC_NAND_INIT nand_init,
+#else
+# define INIT_FUNC_NAND_INIT
#endif /* CONFIG_CMD_NAND */
+#if defined(CONFIG_WATCHDOG)
+extern int watchdog_init(void);
+extern int watchdog_disable(void);
+# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
+# define WATCHDOG_DISABLE watchdog_disable
+#else
+# define INIT_FUNC_WATCHDOG_INIT
+# define WATCHDOG_DISABLE
+#endif /* CONFIG_WATCHDOG */
+
#if defined(CONFIG_CMD_IDE)
-#include ide.h
-static int sh_marubun_init(void)
-{
- puts (IDE: );
- ide_init();
- return 0;
-}
-#endif /* (CONFIG_CMD_IDE) */
+# include ide.h
+# define INIT_FUNC_IDE_INITide_init,
+#else
+# define INIT_FUNC_IDE_INIT
+#endif /* CONFIG_CMD_IDE */
#if defined(CONFIG_PCI)
+#include pci.h
static int sh_pci_init(void)
{
pci_init();
return 0;
}
+# define INIT_FUNC_PCI_INIT sh_pci_init,
+#else
+# define INIT_FUNC_PCI_INIT
#endif /* CONFIG_PCI */
static int sh_mem_env_init(void)
@@ -136,24 +144,20 @@ init_fnc_t *init_sequence[] =
{
cpu_init, /* basic cpu dependent setup */
board_init, /* basic board dependent setup */
- interrupt_init, /* set up exceptions */
+ interrupt_init, /* set up exceptions */
env_init, /* event init */
- serial_init,/* SCIF init */
- watchdog_init, /* watchdog init */
+ serial_init,/* SCIF init */
+ INIT_FUNC_WATCHDOG_INIT /* watchdog init */
console_init_f,
display_options,
checkcpu,
checkboard, /* Check support board */
dram_init, /* SDRAM init */
timer_init, /* SuperH Timer (TCNT0 only) init */
- sh_flash_init, /* Flash memory(NOR) init*/
+ sh_flash_init, /* Flash memory(NOR) init*/
sh_mem_env_init,
-#if defined
[U-Boot] [PATCH v2] sh: Add support watchdog for SH4A core
Add support watchdog for SH4A core (SH7763, SH7780 and SH7785).
And fix some compile warning.
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED]
---
- Fix checkpatch warning
cpu/sh4/watchdog.c | 53 +---
lib_sh/board.c | 115 ++--
2 files changed, 104 insertions(+), 64 deletions(-)
diff --git a/cpu/sh4/watchdog.c b/cpu/sh4/watchdog.c
index 346e217..f692429 100644
--- a/cpu/sh4/watchdog.c
+++ b/cpu/sh4/watchdog.c
@@ -17,34 +17,55 @@
#include common.h
#include asm/processor.h
+#include asm/io.h
#define WDT_BASE WTCNT
-static unsigned char cnt_read (void){
- return *((volatile unsigned char *)(WDT_BASE + 0x00));
+#define WDT_WD (1 6)
+#define WDT_RST_P (0)
+#define WDT_RST_M (1 5)
+#define WDT_ENABLE (1 7)
+
+#if defined(CONFIG_WATCHDOG)
+static unsigned char csr_read(void)
+{
+ return inb(WDT_BASE + 0x04);
}
-static unsigned char csr_read (void){
- return *((volatile unsigned char *)(WDT_BASE + 0x04));
+static void cnt_write(unsigned char value)
+{
+ outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
}
-static void cnt_write (unsigned char value){
- while (csr_read() (1 5)) {
- /* delay */
- }
- *((volatile unsigned short *)(WDT_BASE + 0x00))
- = ((unsigned short) value) | 0x5A00;
+static void csr_write(unsigned char value)
+{
+ outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
}
-static void csr_write (unsigned char value){
- *((volatile unsigned short *)(WDT_BASE + 0x04))
- = ((unsigned short) value) | 0xA500;
+void watchdog_reset(void)
+{
+ outl(0x5500, WDT_BASE + 0x08);
}
+int watchdog_init(void)
+{
+ /* Set overflow time*/
+ cnt_write(0);
+ /* Power on reset */
+ csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
+
+ return 0;
+}
-int watchdog_init (void){ return 0; }
+int watchdog_disable(void)
+{
+ csr_write(csr_read() ~WDT_ENABLE);
+ return 0;
+}
+#endif
-void reset_cpu (unsigned long ignored)
+void reset_cpu(unsigned long ignored)
{
- while(1);
+ while (1)
+ ;
}
diff --git a/lib_sh/board.c b/lib_sh/board.c
index eb81bd9..6dfab4e 100644
--- a/lib_sh/board.c
+++ b/lib_sh/board.c
@@ -23,6 +23,7 @@
#include malloc.h
#include devices.h
#include version.h
+#include watchdog.h
#include net.h
#include environment.h
@@ -30,7 +31,6 @@ extern void malloc_bin_reloc (void);
extern int cpu_init(void);
extern int board_init(void);
extern int dram_init(void);
-extern int watchdog_init(void);
extern int timer_init(void);
const char version_string[] = U_BOOT_VERSION ( __DATE__ - __TIME__ );
@@ -41,17 +41,17 @@ static unsigned long mem_malloc_start;
static unsigned long mem_malloc_end;
static unsigned long mem_malloc_brk;
-static void mem_malloc_init (void)
+static void mem_malloc_init(void)
{
mem_malloc_start = (TEXT_BASE - CFG_GBL_DATA_SIZE - CFG_MALLOC_LEN);
mem_malloc_end = (mem_malloc_start + CFG_MALLOC_LEN - 16);
mem_malloc_brk = mem_malloc_start;
- memset ((void *) mem_malloc_start, 0,
+ memset((void *) mem_malloc_start, 0,
(mem_malloc_end - mem_malloc_start));
}
-void *sbrk (ptrdiff_t increment)
+void *sbrk(ptrdiff_t increment)
{
unsigned long old = mem_malloc_brk;
unsigned long new = old + increment;
@@ -70,37 +70,45 @@ static int sh_flash_init(void)
DECLARE_GLOBAL_DATA_PTR;
gd-bd-bi_flashsize = flash_init();
- printf(FLASH: %dMB\n, gd-bd-bi_flashsize / (1024*1024));
+ printf(FLASH: %ldMB\n, gd-bd-bi_flashsize / (1024*1024));
return 0;
}
#if defined(CONFIG_CMD_NAND)
-#include nand.h
-static int sh_nand_init(void)
-{
- printf(NAND: );
- nand_init();/* go init the NAND */
- return 0;
-}
+# include nand.h
+# define INIT_FUNC_NAND_INIT nand_init,
+#else
+# define INIT_FUNC_NAND_INIT
#endif /* CONFIG_CMD_NAND */
+#if defined(CONFIG_WATCHDOG)
+extern int watchdog_init(void);
+extern int watchdog_disable(void);
+# define INIT_FUNC_WATCHDOG_INIT watchdog_init,
+# define WATCHDOG_DISABLE watchdog_disable
+#else
+# define INIT_FUNC_WATCHDOG_INIT
+# define WATCHDOG_DISABLE
+#endif /* CONFIG_WATCHDOG */
+
#if defined(CONFIG_CMD_IDE)
-#include ide.h
-static int sh_marubun_init(void)
-{
- puts (IDE: );
- ide_init();
- return 0;
-}
-#endif /* (CONFIG_CMD_IDE) */
+# include ide.h
+# define INIT_FUNC_IDE_INITide_init,
+#else
+# define INIT_FUNC_IDE_INIT
+#endif /* CONFIG_CMD_IDE */
#if defined(CONFIG_PCI)
+#include pci.h
static int sh_pci_init(void)
{
pci_init();
return 0;
}
+# define INIT_FUNC_PCI_INIT sh_pci_init,
+#else
+# define INIT_FUNC_PCI_INIT
#endif /* CONFIG_PCI */
static int sh_mem_env_init(void)
@@ -123,7 +131,8 @@ static int sh_net_init(void)
s = getenv(ethaddr);
for (i = 0; i
[U-Boot] [PATCH] sh: Fix compile warning
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- board/ms7722se/lowlevel_init.S | 56 + board/r7780mp/lowlevel_init.S |3 +- board/sh7785lcr/selfcheck.c|4 +- drivers/pci/pci_sh7751.c | 24 + drivers/pci/pci_sh7780.c | 15 +++--- include/asm-sh/cache.h | 14 +++-- include/asm-sh/io.h| 109 +-- include/asm-sh/pci.h |1 + lib_sh/bootm.c |7 ++- 9 files changed, 133 insertions(+), 100 deletions(-) diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S index 332f65a..8b46595 100644 --- a/board/ms7722se/lowlevel_init.S +++ b/board/ms7722se/lowlevel_init.S @@ -43,48 +43,61 @@ lowlevel_init: - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D, r0 ! Instruction Cache Invalidate + /* Address of Cache Control Register */ + mov.l CCR_A, r1 + /*Instruction Cache Invalidate */ + mov.l CCR_D, r0 mov.l r0, @r1 - mov.l MMUCR_A, r1 ! Address of MMU Control Register - mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit + /* Address of MMU Control Register */ + mov.l MMUCR_A, r1 + /* TI == TLB Invalidate bit */ + mov.l MMUCR_D, r0 mov.l r0, @r1 - mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 - mov.l MSTPCR0_D, r0 ! + /* Address of Power Control Register 0 */ + mov.l MSTPCR0_A, r1 + mov.l MSTPCR0_D, r0 mov.l r0, @r1 - mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 - mov.l MSTPCR2_D, r0 ! + /* Address of Power Control Register 2 */ + mov.l MSTPCR2_A, r1 + mov.l MSTPCR2_D, r0 mov.l r0, @r1 - mov.l SBSCR_A, r1 ! - mov.w SBSCR_D, r0 ! + mov.l SBSCR_A, r1 + mov.w SBSCR_D, r0 mov.w r0, @r1 - mov.l PSCR_A, r1 ! - mov.w PSCR_D, r0 ! + mov.l PSCR_A, r1 + mov.w PSCR_D, r0 mov.w r0, @r1 -! mov.l RWTCSR_A, r1! 0xA4520004 (Watchdog Control / Status Register) -! mov.w RWTCSR_D_1, r0 ! 0xA507 - timer_STOP/WDT_CLK=max + /* 0xA4520004 (Watchdog Control / Status Register) */ +! mov.l RWTCSR_A, r1 + /* 0xA507 - timer_STOP/WDT_CLK=max */ +! mov.w RWTCSR_D_1, r0 ! mov.w r0, @r1 - mov.l RWTCNT_A, r1! 0xA452 (Watchdog Count Register) - mov.w RWTCNT_D, r0! 0x5A00 - Clear + /* 0xA452 (Watchdog Count Register) */ + mov.l RWTCNT_A, r1 + /*0x5A00 - Clear */ + mov.w RWTCNT_D, r0 mov.w r0, @r1 - mov.l RWTCSR_A, r1! 0xA4520004 (Watchdog Control / Status Register) - mov.w RWTCSR_D_2, r0 ! 0xA504 - timer_STOP/CLK=500ms + /* 0xA4520004 (Watchdog Control / Status Register) */ + mov.l RWTCSR_A, r1 + /* 0xA504 - timer_STOP/CLK=500ms */ + mov.w RWTCSR_D_2, r0 mov.w r0, @r1 - mov.l FRQCR_A, r1 ! 0xA415 Frequency control register + /* 0xA415 Frequency control register */ + mov.l FRQCR_A, r1 mov.l FRQCR_D, r0 ! mov.l r0, @r1 - mov.l CCR_A, r1 ! Address of Cache Control Register - mov.l CCR_D_2, r0 ! ?? + mov.l CCR_A, r1 + mov.l CCR_D_2, r0 mov.l r0, @r1 bsc_init: @@ -290,5 +303,6 @@ PSCR_D: .word 0x RWTCSR_D_1:.word 0xA507 RWTCSR_D_2:.word 0xA507 RWTCNT_D: .word 0x5A00 + .align 2 SR_MASK_D: .long 0xEF0F diff --git a/board/r7780mp/lowlevel_init.S b/board/r7780mp/lowlevel_init.S index 05c075b..ab0499a 100644 --- a/board/r7780mp/lowlevel_init.S +++ b/board/r7780mp/lowlevel_init.S @@ -325,8 +325,9 @@ repeat2: RWTCSR_D_1:.word 0xA507 RWTCSR_D_2:.word 0xA507 RWTCNT_D: .word 0x5A00 + .align 2 -BBG_PMMR_A:.long 0xFF800010 +BBG_PMMR_A:.long 0xFF800010 BBG_PMSR1_A: .long 0xFF800014 BBG_PMSR2_A: .long 0xFF800018 BBG_PMSR3_A: .long 0xFF80001C diff --git a/board/sh7785lcr/selfcheck.c b/board/sh7785lcr/selfcheck.c index d924595..ce0620f 100644 --- a/board/sh7785lcr/selfcheck.c +++ b/board/sh7785lcr/selfcheck.c @@ -84,7 +84,7 @@ static void test_net(void) if (data == 0x816910ec) printf(Ethernet OK\n); else - printf(Ethernet NG, data = %08x\n, data); + printf(Ethernet NG, data = %08x\n, (unsigned int)data); } static void test_sata(void) @@ -96,7 +96,7 @@ static void test_sata(void) if (data == 0x35121095) printf(SATA OK\n); else - printf(SATA NG
[U-Boot] [PATCH] usb: Fix compile warning of r8a66597-hcd
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED]
---
drivers/usb/r8a66597-hcd.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/r8a66597-hcd.c b/drivers/usb/r8a66597-hcd.c
index 0d3931e..a2e1fff 100644
--- a/drivers/usb/r8a66597-hcd.c
+++ b/drivers/usb/r8a66597-hcd.c
@@ -530,7 +530,7 @@ static int check_usb_device_connecting(struct
r8a66597 *r8a66597)
/* based on usb_ohci.c */
#define min_t(type, x, y) \
- ({ type __x = (x); type __y = (y); __x __y ? __x: __y; })
+ ({ type __x = (x); type __y = (y); __x __y ? __x : __y; })
/*-*
* Virtual Root Hub
*-*/
@@ -794,7 +794,7 @@ static int r8a66597_submit_rh_msg(struct
usb_device *dev, unsigned long pipe,
case RH_SET_CONFIGURATION:
break;
default:
- dbg(unsupported root hub command);
+ R8A66597_DPRINT(unsupported root hub command);
stat = USB_ST_STALLED;
}
--
1.5.6.3
___
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[U-Boot] [PATCH] ppc: Fix typo in include/mpc83xx.h
Fixed typo from CONIFG_MPC837X to CONFIG_MPC837X Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- include/mpc83xx.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 5d82bb4..7f30d68 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -528,7 +528,7 @@ #if defined(CONFIG_MPC834X) #define HRCWH_ROM_LOC_PCI2 0x0020 #endif -#if defined(CONIFG_MPC837X) +#if defined(CONFIG_MPC837X) #define HRCWH_ROM_LOC_ON_CHIP_ROM 0x0030 #endif #define HRCWH_ROM_LOC_LOCAL_8BIT 0x0050 -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBoot] Hows to boot Linux Kernel from USB
2008/10/1 thaoth [EMAIL PROTECTED]: Can you retry and copy-paste the console output? ... (Re)start USB... USB: scanning bus for devices... cannot reset port 1!? 2 USB Device(s) found scanning bus for storage devices... 1 Storage Device(s) found = fatload usb 0:1 0x8e00 uImage reading uImage . . . . 1278020 bytes read = bootm * kernel: default image load address = 0x8e00 Wrong Image Format for bootm command ERROR: can't get kernel image! ... can you do a 'file uImage' and copy the result ? ... [EMAIL PROTECTED] boot]# file uImage uImage: PPCBoot image ... I tried and send you its log. What is the kernel version that you use? -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [UBoot] Hows to boot Linux Kernel from USB
2008/10/1 thaoth [EMAIL PROTECTED]: [EMAIL PROTECTED] boot]# file uImage uImage: PPCBoot image ... I tried and send you its log. What is the kernel version that you use? I'm using version 2.6.22.11. I think that your linux kernel is too old. Please use newest linux kernel or backport arch/sh/boot/Makefile to your kernel. Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] net: ne2000: Divided a function of NE2000 driver
Hi, all 2008/10/3 Ben Warren [EMAIL PROTECTED]: Jean-Christophe PLAGNIOL-VILLARD wrote: On 23:07 Wed 01 Oct , Ben Warren wrote: Hi Nobuhiro-san, Nobuhiro Iwamatsu wrote: get_prom function was used __attriute__ , but it is not enable. ax88796.o does not do link besides ne2000.o. When ld is carried out, get_prom function of ax88796.c is ignored. This problem is a thing by specifications of ld. I checked and test this patch on SuperH and MIPS. You're seeing a common problem with weak functions - namely that they don't always get overridden. If there was a single function in ax88796.c that had strong static linkage there wouldn't be a problem. Using the weak attribute for get_prom() is an elegant solution that improves code re-use, so I'm wondering if there's a way it can be made to work. If nobody has any suggestions over the next couple of days, I'll pull in this patch. This get_prom() function was set as weak in commit 2ef7503a593c77a80c2a054011970227c4b62774, labeled NE2000: Fix regresssion introduced by e710185aae90 on non AX88796 by Jean-Christophe PLAGNIOL-VILLARD. It's a shame that this was done without testing... The NE2000 is tested every modification and Release on qemu_mips by myself And I've no problem on this board. Sorry, I have a hard time believing that this works if you enable CONFIG_DRIVER_AX88796L. Are you sure that the weak get_prom() is overridden? Thank you for your check. When I enabled CONFIG_DRIVER_AX88796L on SH and MIPS, and checked ne2000.o by nm, get_prom is set in WEAK. But get_prom is not linked, and __get_prom is linked in u-boot. With the current code, get_prom of AX88796L is not linked. If need nm and objdump output , I can attach. Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: Fix cannot execute a stand-alone application
Address calculated in EXPORT_FUNC in SuperH was wrong, I revised it. Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- examples/stubs.c |6 -- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/examples/stubs.c b/examples/stubs.c index ec53532..a8cb954 100644 --- a/examples/stubs.c +++ b/examples/stubs.c @@ -162,11 +162,13 @@ gd_t *global_data; #x :\n\ mov r13, r1\n \ add %0, r1\n \ - add %1, r1\n \ + mov.l @r1, r2\n\ + add %1, r2\n \ + mov.l @r2, r1\n\ jmp @r1\n \ nop\n \ nop\n \ - : : i(offsetof(gd_t, jt)), i(XF_ ## x * sizeof(void *)) : r1); + : : i(offsetof(gd_t, jt)), i(XF_ ## x * sizeof(void *)) : r1, r2); #elif defined(CONFIG_SPARC) /* * g7 holds the pointer to the global_data. g1 is call clobbered. -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Run hello world with Uboot !
Hi, all. 2008/10/8 thaoth [EMAIL PROTECTED]: 6. I didn't have JTAG interface so I couldn't debug it. Could I have a help? Anyone had same issue please tell me your idea? Thank you alot. This same the porting of UBoot on TEngine/SH7727 has the issue. But we don't know what trouble shooting steps. This problem is SuperH specific. I fixed it and send patch. Thaoth , Please apply patch to your source code, and do test. Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] sh: rsk7203: Add smc911x driver support to board config file
Signed-off-by: Nobuhiro Iwamatsu [EMAIL PROTECTED] --- include/configs/rsk7203.h |5 + 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index d99e4f3..1f20e57 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -104,4 +104,9 @@ #define CMT_CLK_DIVIDER32 /* 8 (default), 32, 128 or 512 */ #define CFG_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER) +/* Network interface */ +#define CONFIG_DRIVER_SMC911X +#define CONFIG_DRIVER_SMC911X_16_BIT +#define CONFIG_DRIVER_SMC911X_BASE (0x2400) + #endif /* __RSK7203_H */ -- 1.5.6.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: sh_eth: Remove unnecessary return
--- drivers/net/sh_eth.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 1bc44a8..8d3dac2 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -94,7 +94,6 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) if (port_info-tx_desc_cur = port_info-tx_desc_base + NUM_TX_DESC) port_info-tx_desc_cur = port_info-tx_desc_base; - return ret; err: return ret; } -- 1.7.7.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: sh_eth: Add support SH7734 Ethernet device
SH7734 has one channel ethernet device.
This support 10/100/1000Base, and RMII/MII/GMII.
And this has the same structure as SH7763.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 17 +-
drivers/net/sh_eth.h | 85 ++
2 files changed, 74 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 8d3dac2..c1abe7c 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -59,7 +59,7 @@ int sh_eth_send(struct eth_device *dev, volatile void
*packet, int len)
}
/* packet must be a 4 byte boundary */
- if ((int)packet (4 - 1)) {
+ if ((int)packet 3) {
printf(SHETHER_NAME : %s: packet not 4 byte alligned\n,
__func__);
ret = -EFAULT;
goto err;
@@ -138,7 +138,7 @@ int sh_eth_recv(struct eth_device *dev)
static int sh_eth_reset(struct sh_eth_dev *eth)
{
int port = eth-port;
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
@@ -208,7 +208,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the tx descriptor list. Must use physical
addresses */
outl(ADDR_TO_PHY(port_info-tx_desc_base), TDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(ADDR_TO_PHY(port_info-tx_desc_base), TDFAR(port));
outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
outl(0x01, TDFFR(port));/* Last discriptor bit */
@@ -276,7 +276,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
/* Point the controller to the rx descriptor list */
outl(ADDR_TO_PHY(port_info-rx_desc_base), RDLAR(port));
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(ADDR_TO_PHY(port_info-rx_desc_base), RDFAR(port));
outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
outl(RDFFR_RDLF, RDFFR(port));
@@ -346,7 +346,8 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
struct eth_device *dev = port_info-dev;
struct phy_device *phydev;
- phydev = phy_connect(miiphy_get_dev_by_name(dev-name),
+ phydev = phy_connect(
+ miiphy_get_dev_by_name(dev-name),
port_info-phy_addr, dev, PHY_INTERFACE_MODE_MII);
port_info-phydev = phydev;
phy_config(phydev);
@@ -398,7 +399,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
outl(APR_AP, APR(port));
outl(MPR_MP, MPR(port));
#endif
-#if defined(CONFIG_CPU_SH7763)
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(TPAUSER_TPAUSE, TPAUSER(port));
#elif defined(CONFIG_CPU_SH7757)
outl(TPAUSER_UNLIMITED, TPAUSER(port));
@@ -418,7 +419,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
/* Set the transfer speed */
if (phy-speed == 100) {
printf(SHETHER_NAME : 100Base/);
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(GECMR_100B, GECMR(port));
#elif defined(CONFIG_CPU_SH7757)
outl(1, RTRATE(port));
@@ -427,7 +428,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
#endif
} else if (phy-speed == 10) {
printf(SHETHER_NAME : 10Base/);
-#ifdef CONFIG_CPU_SH7763
+#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
outl(GECMR_10B, GECMR(port));
#elif defined(CONFIG_CPU_SH7757)
outl(0, RTRATE(port));
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 27fde05..1f646e2 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -188,13 +188,51 @@ struct sh_eth_dev {
#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
#define MALR(port) (BASE_IO_ADDR + 0x01c8)
+
+#elif defined(CONFIG_CPU_SH7734)
+#define BASE_IO_ADDR 0xFEE0
+
+#define EDSR(port) (BASE_IO_ADDR)
+
+#define TDLAR(port)(BASE_IO_ADDR + 0x0010)
+#define TDFAR(port)(BASE_IO_ADDR + 0x0014)
+#define TDFXR(port)(BASE_IO_ADDR + 0x0018)
+#define TDFFR(port)(BASE_IO_ADDR + 0x001c)
+#define RDLAR(port)(BASE_IO_ADDR + 0x0030)
+#define RDFAR(port)(BASE_IO_ADDR + 0x0034)
+#define RDFXR(port)(BASE_IO_ADDR + 0x0038)
+#define RDFFR(port)(BASE_IO_ADDR + 0x003c)
+
+#define EDMR(port) (BASE_IO_ADDR + 0x0400)
+#define EDTRR(port)(BASE_IO_ADDR + 0x0408)
+#define EDRRR(port)(BASE_IO_ADDR + 0x0410)
+#define EESR(port) (BASE_IO_ADDR + 0x0428)
+#define EESIPR(port) (BASE_IO_ADDR + 0x0430)
+#define TRSCER(port) (BASE_IO_ADDR + 0x0438)
+#define
[U-Boot] [PATCH] sh: Add support for r0p7734 board
The r0p7734 board has SH7734, 128MB DDR2-SDRAM, USB, Ethernet, and more. This patch supports the following functions: - 128MB DDR2-SDRAM - 32MB NOR Flash memory - Serial console (SCIF) - Ethernet (SH-Ether/SMSC) Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- MAINTAINERS |1 + board/renesas/r0p7734/Makefile| 40 +++ board/renesas/r0p7734/lowlevel_init.S | 606 + board/renesas/r0p7734/r0p7734.c | 78 + boards.cfg|1 + include/configs/r0p7734.h | 167 + 6 files changed, 893 insertions(+), 0 deletions(-) create mode 100644 board/renesas/r0p7734/Makefile create mode 100644 board/renesas/r0p7734/lowlevel_init.S create mode 100644 board/renesas/r0p7734/r0p7734.c create mode 100644 include/configs/r0p7734.h diff --git a/MAINTAINERS b/MAINTAINERS index 4bf12b5..44394a8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1069,6 +1069,7 @@ Nobuhiro Iwamatsu iwama...@nigauri.org AP325RXASH7723 SHMIN SH7706 ECOVEC SH7724 + R0P7734 SH7734 Mark Jonas mark.jo...@de.bosch.com diff --git a/board/renesas/r0p7734/Makefile b/board/renesas/r0p7734/Makefile new file mode 100644 index 000..b8c0353 --- /dev/null +++ b/board/renesas/r0p7734/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2011 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := r0p7734.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/renesas/r0p7734/lowlevel_init.S b/board/renesas/r0p7734/lowlevel_init.S new file mode 100644 index 000..1a7f1ac --- /dev/null +++ b/board/renesas/r0p7734/lowlevel_init.S @@ -0,0 +1,606 @@ +/* + * Copyright (C) 2011 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include config.h +#include version.h +#include asm/processor.h +#include asm/macro.h + +#include asm/processor.h + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + /* WDT */ + write32 WDTCSR_A, WDTCSR_D + + /* MMU */ + write32 MMUCR_A, MMUCR_D + + write32 FRQCR2_A, FRQCR2_D + write32 FRQCR0_A, FRQCR0_D + + write32 CS0CTRL_A, CS0CTRL_D + write32 CS1CTRL_A, CS1CTRL_D + write32 CS0CTRL2_A, CS0CTRL2_D + + write32 CSPWCR0_A, CSPWCR0_D + write32 CSPWCR1_A, CSPWCR1_D + write32 CS1GDST_A, CS1GDST_D + + # clock mode check + mov.l MODEMR, r1 + mov.l @r1, r0 + and #6, r0 /* Check 1 and 2 bit.*/ + cmp/eq #2, r0 /* 0x02 is 533Mhz mode */ + bt init_lbsc_533 + +init_lbsc_400: + + write32 CSWCR0_A, CSWCR0_D_400 + write32 CSWCR1_A, CSWCR1_D + + bra init_dbsc3_400_pad + nop + + .align 2 + +MODEMR:.long 0xFFCC0020 +WDTCSR_A: .long 0xFFCC0004 +WDTCSR_D: .long 0xA500 +MMUCR_A: .long 0xFF10 +MMUCR_D: .long
[U-Boot] [PATCH] net: sh_eth: Fix build warnings and whitespace for sh_eth
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 27 +--
1 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index c1abe7c..e29061c 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -60,7 +60,8 @@ int sh_eth_send(struct eth_device *dev, volatile void
*packet, int len)
/* packet must be a 4 byte boundary */
if ((int)packet 3) {
- printf(SHETHER_NAME : %s: packet not 4 byte alligned\n,
__func__);
+ printf(SHETHER_NAME
+ : %s: packet not 4 byte alligned\n , __func__);
ret = -EFAULT;
goto err;
}
@@ -141,6 +142,8 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
int ret = 0, i;
+ port = eth-port;
+
/* Start e-dmac transmitter and receiver */
outl(EDSR_ENALL, EDSR(port));
@@ -159,6 +162,8 @@ static int sh_eth_reset(struct sh_eth_dev *eth)
return ret;
#else
+ port = eth-port;
+
outl(inl(EDMR(port)) | EDMR_SRST, EDMR(port));
udelay(3000);
outl(inl(EDMR(port)) ~EDMR_SRST, EDMR(port));
@@ -564,8 +569,10 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
outl(inl(PIR(port)) | PIR_MMD, PIR(port));
@@ -574,8 +581,10 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
outl(inl(PIR(port)) ~PIR_MMD, PIR(port));
@@ -584,8 +593,10 @@ static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus
*bus)
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
if (v)
outl(inl(PIR(port)) | PIR_MDO, PIR(port));
@@ -597,8 +608,10 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus,
int v)
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
*v = (inl(PIR(port)) PIR_MDI) 3;
@@ -607,8 +620,10 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus,
int *v)
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
+ int port;
struct sh_eth_dev *eth = bus-priv;
- int port = eth-port;
+
+ port = eth-port;
if (v)
outl(inl(PIR(port)) | PIR_MDC, PIR(port));
--
1.7.7.3
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[U-Boot] [PATCH] sh: i2c: Add support I2C controller of SH7734
Renesas SH7734 has two I2C interfaceis.
This supports these I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/i2c/Makefile|1 +
drivers/i2c/sh_sh7734_i2c.c | 468 +++
2 files changed, 469 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/sh_sh7734_i2c.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 504db03..506269d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
+COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c
new file mode 100644
index 000..6c514b4
--- /dev/null
+++ b/drivers/i2c/sh_sh7734_i2c.c
@@ -0,0 +1,468 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+
+struct sh_i2c {
+ u8 iccr1;
+ u8 iccr2;
+ u8 icmr;
+ u8 icier;
+ u8 icsr;
+ u8 sar;
+ u8 icdrt;
+ u8 icdrr;
+ u8 nf2cyc;
+ u8 __pad0;
+ u8 __pad1;
+};
+
+static struct sh_i2c *base;
+static u8 iccr1_cks, nf2cyc;
+
+/* ICCR1 */
+#define SH_I2C_ICCR1_ICE (1 7)
+#define SH_I2C_ICCR1_RCVD (1 6)
+#define SH_I2C_ICCR1_MST (1 5)
+#define SH_I2C_ICCR1_TRS (1 4)
+#define SH_I2C_ICCR1_MTRS \
+ (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
+
+/* ICCR1 */
+#define SH_I2C_ICCR2_BBSY (1 7)
+#define SH_I2C_ICCR2_SCP (1 6)
+#define SH_I2C_ICCR2_SDAO (1 5)
+#define SH_I2C_ICCR2_SDAOP (1 4)
+#define SH_I2C_ICCR2_SCLO (1 3)
+#define SH_I2C_ICCR2_IICRST(1 1)
+
+#define SH_I2C_ICIER_TIE (1 7)
+#define SH_I2C_ICIER_TEIE (1 6)
+#define SH_I2C_ICIER_RIE (1 5)
+#define SH_I2C_ICIER_NAKIE (1 4)
+#define SH_I2C_ICIER_STIE (1 3)
+#define SH_I2C_ICIER_ACKE (1 2)
+#define SH_I2C_ICIER_ACKBR (1 1)
+#define SH_I2C_ICIER_ACKBT (1 0)
+
+#define SH_I2C_ICSR_TDRE (1 7)
+#define SH_I2C_ICSR_TEND (1 6)
+#define SH_I2C_ICSR_RDRF (1 5)
+#define SH_I2C_ICSR_NACKF (1 4)
+#define SH_I2C_ICSR_STOP (1 3)
+#define SH_I2C_ICSR_ALOVE (1 2)
+#define SH_I2C_ICSR_AAS(1 1)
+#define SH_I2C_ICSR_ADZ(1 0)
+
+#define IRQ_WAIT 1000
+
+
+static void sh_i2c_send_stop(struct sh_i2c *base)
+{
+ writeb(readb(base-iccr2) ~(SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP),
+ base-iccr2);
+}
+
+static int check_stop(struct sh_i2c *base)
+{
+ int i, ret = 1;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_STOP readb(base-icsr)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ writeb(readb(base-icsr) ~SH_I2C_ICSR_STOP, base-icsr);
+
+ return ret;
+}
+
+static int check_tend(struct sh_i2c *base, int stop)
+{
+ int i, ret = 1;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_TEND readb(base-icsr)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ if (stop) {
+ u8 data;
+
+ writeb(readb(base-icsr) ~SH_I2C_ICSR_STOP, base-icsr);
+
+ sh_i2c_send_stop(base);
+ }
+
+ writeb(readb(base-icsr) ~SH_I2C_ICSR_TEND, base-icsr);
+
+ return ret;
+}
+
+static int check_tdre(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_TDRE readb(base-icsr))
+ return 0;
+ udelay(10);
+ }
+
+ return 1;
+}
+
+static int check_rdrf(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_RDRF readb(base-icsr))
+ return 0;
+ udelay(10);
+ }
+
+ return 1;
+}
+
+static int check_bbsy(struct sh_i2c *base
[U-Boot] [PATCH] sh: r0p7734: Add support I2C and set MAC address
r0p7734 board stores away MAC address in EEPROM.
This sets an MAC address to reading, environment variable
from an EEPROM by supporting I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/renesas/r0p7734/r0p7734.c | 19 ++-
include/configs/r0p7734.h | 16
2 files changed, 34 insertions(+), 1 deletions(-)
diff --git a/board/renesas/r0p7734/r0p7734.c b/board/renesas/r0p7734/r0p7734.c
index 80f4329..656b9ee 100644
--- a/board/renesas/r0p7734/r0p7734.c
+++ b/board/renesas/r0p7734/r0p7734.c
@@ -24,6 +24,7 @@
#include common.h
#include asm/io.h
#include asm/processor.h
+#include i2c.h
#include netdev.h
DECLARE_GLOBAL_DATA_PTR;
@@ -50,11 +51,28 @@ int checkboard(void)
int board_init(void)
{
+ u8 mac[6];
+ char env_mac[17];
+ int i;
+
#if defined(CONFIG_SH_ETHER)
u32 r = readl(MSTPSR1);
if (r MSTPSR1_GETHER)
writel((r ~MSTPSR1_GETHER), MSTPCR1);
#endif
+
+ /* Read MAC address */
+ i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 0 */
+
+ i2c_read(0x50, 0x10, 0, mac, 6);
+
+ /* Set MAC address */
+ printf(%02X:%02X:%02X:%02X:%02X:%02X\n,
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+ sprintf(env_mac, %02X:%02X:%02X:%02X:%02X:%02X,
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
+
return 0;
}
@@ -75,4 +93,3 @@ int board_eth_init(bd_t *bis)
return rc;
}
#endif
-
diff --git a/include/configs/r0p7734.h b/include/configs/r0p7734.h
index d73cc4d..22c1ef7 100644
--- a/include/configs/r0p7734.h
+++ b/include/configs/r0p7734.h
@@ -34,6 +34,7 @@
#define CONFIG_400MHZ_MODE 1
/* #define CONFIG_533MHZ_MODE 1 */
+#define BOARD_LATE_INIT1
#define CONFIG_SYS_TEXT_BASE 0x8FFC
#define CONFIG_CMD_FLASH
@@ -53,6 +54,21 @@
#define CONFIG_VERSION_VARIABLE
#undef CONFIG_SHOW_BOOT_PROGRESS
+/* I2C */
+#define CONFIG_CMD_I2C
+#define CONFIG_SH_SH7734_I2C 1
+#define CONFIG_HARD_I2C 1
+#define CONFIG_I2C_MULTI_BUS1
+#define CONFIG_SYS_MAX_I2C_BUS 2
+#define CONFIG_SYS_I2C_MODULE 0
+#define CONFIG_SYS_I2C_SPEED10 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE0x50
+#define CONFIG_SH_I2C_DATA_HIGH 4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK 5
+#define CONFIG_SH_I2C_BASE0 0xFFC7
+#define CONFIG_SH_I2C_BASE1 0xFFC71000
+
/* Ether */
#define CONFIG_SH_ETHER 1
#define CONFIG_SH_ETHER_USE_PORT (0)
--
1.7.7.3
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Re: [U-Boot] [PATCH] sh: i2c: Add support I2C controller of SH7734
Hi,
Thanks for your comment.
2012/2/6 Heiko Schocher h...@denx.de:
Hello Nobuhiro,
Nobuhiro Iwamatsu wrote:
Renesas SH7734 has two I2C interfaceis.
This supports these I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
 drivers/i2c/Makefile     |   1 +
 drivers/i2c/sh_sh7734_i2c.c |  468
+++
 2 files changed, 469 insertions(+), 0 deletions(-)
 create mode 100644 drivers/i2c/sh_sh7734_i2c.c
[...]
diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c
new file mode 100644
index 000..6c514b4
--- /dev/null
+++ b/drivers/i2c/sh_sh7734_i2c.c
@@ -0,0 +1,468 @@
[...]
+static void sh_i2c_send_stop(struct sh_i2c *base)
+{
+ Â Â writeb(readb(base-iccr2) ~(SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP),
+ Â Â Â Â Â Â base-iccr2);
Please use clrbits_*
OK, but clrbits_* functions is not implement to SuperH and other.
I will implement these functions to SuperH.
[...]
+static int check_tend(struct sh_i2c *base, int stop)
+{
+ Â Â int i, ret = 1;
+
+ Â Â for (i = 0 ; i IRQ_WAIT ; i++) {
+ Â Â Â Â Â Â if (SH_I2C_ICSR_TEND readb(base-icsr)) {
+ Â Â Â Â Â Â Â Â Â Â ret = 0;
+ Â Â Â Â Â Â Â Â Â Â break;
+ Â Â Â Â Â Â }
+ Â Â Â Â Â Â udelay(10);
+ Â Â }
+
+ Â Â if (stop) {
+ Â Â Â Â Â Â u8 data;
+
+ Â Â Â Â Â Â writeb(readb(base-icsr) ~SH_I2C_ICSR_STOP, base-icsr);
+
+ Â Â Â Â Â Â sh_i2c_send_stop(base);
+ Â Â }
+
+ Â Â writeb(readb(base-icsr) ~SH_I2C_ICSR_TEND, base-icsr);
here too... please check globally.
OK. I will changed from writeb to clr|set|clrsetbits_*.
[...]
+#ifdef CONFIG_I2C_MULTI_BUS
+static unsigned int current_bus;
+
+/**
wrong comment style.
OK.
[...]
+/**
here too.
OK.
+ * i2c_get_bus_num - returns index of active I2C bus
+ */
+unsigned int i2c_get_bus_num(void)
[...]
+int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
+{
+ Â Â int i = 0;
new line please.
OK.
+ Â Â for (i = 0 ; i len ; i++)
+ Â Â Â Â Â Â buffer[i] = i2c_raw_read(base, chip, addr + i);
[...]
Beside of this minor comments patch looks good, thanks!
Thanks!
Nobuhiro
--
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[U-Boot] [PATCH v2] sh: i2c: Add support I2C controller of SH7734
Renesas SH7734 has two I2C interfaceis.
This supports these I2C.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
V2: - Changed bit control to use the clr|set|clrsetbits_* functions.
- Fix wrong comment style.
- Add new line before for loop in i2c_read.
drivers/i2c/Makefile|1 +
drivers/i2c/sh_sh7734_i2c.c | 445 +++
2 files changed, 446 insertions(+), 0 deletions(-)
create mode 100644 drivers/i2c/sh_sh7734_i2c.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 504db03..506269d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o
COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
+COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c
new file mode 100644
index 000..ac21b67
--- /dev/null
+++ b/drivers/i2c/sh_sh7734_i2c.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+
+struct sh_i2c {
+ u8 iccr1;
+ u8 iccr2;
+ u8 icmr;
+ u8 icier;
+ u8 icsr;
+ u8 sar;
+ u8 icdrt;
+ u8 icdrr;
+ u8 nf2cyc;
+ u8 __pad0;
+ u8 __pad1;
+};
+
+static struct sh_i2c *base;
+static u8 iccr1_cks, nf2cyc;
+
+/* ICCR1 */
+#define SH_I2C_ICCR1_ICE (1 7)
+#define SH_I2C_ICCR1_RCVD (1 6)
+#define SH_I2C_ICCR1_MST (1 5)
+#define SH_I2C_ICCR1_TRS (1 4)
+#define SH_I2C_ICCR1_MTRS \
+ (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
+
+/* ICCR1 */
+#define SH_I2C_ICCR2_BBSY (1 7)
+#define SH_I2C_ICCR2_SCP (1 6)
+#define SH_I2C_ICCR2_SDAO (1 5)
+#define SH_I2C_ICCR2_SDAOP (1 4)
+#define SH_I2C_ICCR2_SCLO (1 3)
+#define SH_I2C_ICCR2_IICRST(1 1)
+
+#define SH_I2C_ICIER_TIE (1 7)
+#define SH_I2C_ICIER_TEIE (1 6)
+#define SH_I2C_ICIER_RIE (1 5)
+#define SH_I2C_ICIER_NAKIE (1 4)
+#define SH_I2C_ICIER_STIE (1 3)
+#define SH_I2C_ICIER_ACKE (1 2)
+#define SH_I2C_ICIER_ACKBR (1 1)
+#define SH_I2C_ICIER_ACKBT (1 0)
+
+#define SH_I2C_ICSR_TDRE (1 7)
+#define SH_I2C_ICSR_TEND (1 6)
+#define SH_I2C_ICSR_RDRF (1 5)
+#define SH_I2C_ICSR_NACKF (1 4)
+#define SH_I2C_ICSR_STOP (1 3)
+#define SH_I2C_ICSR_ALOVE (1 2)
+#define SH_I2C_ICSR_AAS(1 1)
+#define SH_I2C_ICSR_ADZ(1 0)
+
+#define IRQ_WAIT 1000
+
+
+static void sh_i2c_send_stop(struct sh_i2c *base)
+{
+ clrbits_le8(base-iccr2, (SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP));
+}
+
+static int check_stop(struct sh_i2c *base)
+{
+ int i, ret = 1;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_STOP readb(base-icsr)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ clrbits_le8(base-icsr, SH_I2C_ICSR_STOP);
+
+ return ret;
+}
+
+static int check_tend(struct sh_i2c *base, int stop)
+{
+ int i, ret = 1;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_TEND readb(base-icsr)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ }
+
+ if (stop) {
+ u8 data;
+
+ clrbits_le8(base-icsr, SH_I2C_ICSR_STOP);
+
+ sh_i2c_send_stop(base);
+ }
+
+ clrbits_le8(base-icsr, SH_I2C_ICSR_TEND);
+
+ return ret;
+}
+
+static int check_tdre(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_TDRE readb(base-icsr))
+ return 0;
+ udelay(10);
+ }
+
+ return 1;
+}
+
+static int check_rdrf(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_I2C_ICSR_RDRF readb(base-icsr))
+ return 0;
+ udelay(10
[U-Boot] [PATCH] sh: Add bit control functions
This provide bit control functions as clrbits_*, setbits_* and
clrsetbits_*.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/sh/include/asm/io.h | 37 +
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index ca598a6..79cb098 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -237,6 +237,43 @@ static inline void sync(void)
{
}
+
+/* Clear and set bits in one shot. These macros can be used to clear and
+ * set multiple bits in a register using a single call. These macros can
+ * also be used to set a multiple-bit bit pattern using a mask, by
+ * specifying the mask in the 'clear' parameter and the new bit pattern
+ * in the 'set' parameter.
+ */
+
+#define clrbits(type, addr, clear) \
+ out_##type((addr), in_##type(addr) ~(clear))
+
+#define setbits(type, addr, set) \
+ out_##type((addr), in_##type(addr) | (set))
+
+#define clrsetbits(type, addr, clear, set) \
+ out_##type((addr), (in_##type(addr) ~(clear)) | (set))
+
+#define clrbits_be32(addr, clear) clrbits(be32, addr, clear)
+#define setbits_be32(addr, set) setbits(be32, addr, set)
+#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
+
+#define clrbits_le32(addr, clear) clrbits(le32, addr, clear)
+#define setbits_le32(addr, set) setbits(le32, addr, set)
+#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
+
+#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
+#define setbits_be16(addr, set) setbits(be16, addr, set)
+#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
+
+#define clrbits_le16(addr, clear) clrbits(le16, addr, clear)
+#define setbits_le16(addr, set) setbits(le16, addr, set)
+#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
+
+#define clrbits_8(addr, clear) clrbits(8, addr, clear)
+#define setbits_8(addr, set) setbits(8, addr, set)
+#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
+
/*
* Given a physical address and a length, return a virtual address
* that can be used to access the memory range with the caching
--
1.7.7.3
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Re: [U-Boot] [PATCH] net: sh_eth: Fix build warnings and whitespace for sh_eth
Hi,
2012/2/3 Mike Frysinger vap...@gentoo.org:
On Friday 03 February 2012 02:30:48 Nobuhiro Iwamatsu wrote:
@@ -564,8 +569,10 @@ static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
 static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
 {
+ Â Â int port;
   struct sh_eth_dev *eth = bus-priv;
- Â Â int port = eth-port;
+
+ Â Â port = eth-port;
   outl(inl(PIR(port)) | PIR_MMD, PIR(port));
@@ -574,8 +581,10 @@ static int sh_eth_bb_mdio_active(struct bb_miiphy_bus
*bus)
 static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
 {
+ Â Â int port;
   struct sh_eth_dev *eth = bus-priv;
- Â Â int port = eth-port;
+
+ Â Â port = eth-port;
   outl(inl(PIR(port)) ~PIR_MMD, PIR(port));
@@ -584,8 +593,10 @@ static int sh_eth_bb_mdio_tristate(struct
bb_miiphy_bus *bus)
 static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
 {
+ Â Â int port;
   struct sh_eth_dev *eth = bus-priv;
- Â Â int port = eth-port;
+
+ Â Â port = eth-port;
   if (v)
       outl(inl(PIR(port)) | PIR_MDO, PIR(port));
@@ -597,8 +608,10 @@ static int sh_eth_bb_set_mdio(struct bb_miiphy_bus
*bus, int v)
 static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
 {
+ Â Â int port;
   struct sh_eth_dev *eth = bus-priv;
- Â Â int port = eth-port;
+
+ Â Â port = eth-port;
   *v = (inl(PIR(port)) PIR_MDI) 3;
@@ -607,8 +620,10 @@ static int sh_eth_bb_get_mdio(struct bb_miiphy_bus
*bus, int *v)
 static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
 {
+ Â Â int port;
   struct sh_eth_dev *eth = bus-priv;
- Â Â int port = eth-port;
+
+ Â Â port = eth-port;
   if (v)
       outl(inl(PIR(port)) | PIR_MDC, PIR(port));
i don't see why any of these changes are necessary ... the old code looks fine
to me (from a warning and style pov)
-mike
I do not seem to have any problem with the former cord, too either.
But when I dont apply this patch, I get the following warning.
-
sh4-linux-gnu-gcc -g -Os -ffixed-r13 -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x8FFC
-I/home/iwamatsu/work/u-boot/u-boot-sh/include -fno-builtin
-ffreestanding -nostdinc -isystem
/usr/lib/gcc/sh4-linux-gnu/4.4.6/include -pipe -DCONFIG_SH -D__SH__
-m4-nofpu -Wall -Wstrict-prototypes -fno-stack-protector
-Wno-format-nonliteral -Wno-format-security -o sh_eth.o sh_eth.c
-c
sh_eth.c: In function ‘sh_eth_reset’:
sh_eth.c:140: warning: unused variable ‘port’
sh_eth.c: In function ‘sh_eth_bb_mdio_active’:
sh_eth.c:568: warning: unused variable ‘port’
sh_eth.c: In function ‘sh_eth_bb_mdio_tristate’:
sh_eth.c:578: warning: unused variable ‘port’
sh_eth.c: In function ‘sh_eth_bb_set_mdio’:
sh_eth.c:588: warning: unused variable ‘port’
sh_eth.c: In function ‘sh_eth_bb_get_mdio’:
sh_eth.c:601: warning: unused variable ‘port’
sh_eth.c: In function ‘sh_eth_bb_set_mdc’:
sh_eth.c:611: warning: unused variable ‘port’
sh4-linux-gnu-ld -e 0x8FFC --defsym reloc_dst=0x8FFC -r -o
libnet.o sh_eth.o
-
Best regards,
Nobuhiro
--
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Re: [U-Boot] [PATCH] sh: Fix sh7264 clock speed and related serial setting
Hi,
Applied this patch to my repository.
Thanks!
Nobuhiro
2012/2/13 Phil Edworthy phil.edwor...@renesas.com:
The generalised calculation of the serial bit rate reg also applies
to sh7264, it was just the clock speed that was set incorrectly.
Signed-off-by: Phil Edworthy phil.edwor...@renesas.com
---
 drivers/serial/serial_sh.h |   2 --
 include/configs/rsk7264.h  |   2 +-
 2 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 4e16e48..0b3e779 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -686,8 +686,6 @@ static inline int scbrr_calc(struct uart_port port, int
bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_CPU_SH7264)
-#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps))
 #else /* Generic SH */
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 #endif
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index c1ffc34..af9524e 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -65,7 +65,7 @@
 #define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 /* Board Clock */
-#define CONFIG_SYS_CLK_FREQ Â Â
+#define CONFIG_SYS_CLK_FREQ Â Â 3600
 #define CMT_CLK_DIVIDER         32    /* 8 (default), 32, 128 or
512 */
 #define CONFIG_SYS_HZ      (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
--
1.7.0.4
--
Nobuhiro Iwamatsu
  iwamatsu at {nigauri.org / debian.org}
  GPG ID: 40AD1FA6
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Re: [U-Boot] [PATCH v2 07/10] net: pcnet: use pci_virt_to_mem to obtain buffer addresses
Hi, all.
This is only tested with the qemu-malta target. The change
might break real platforms, however I have no suitable board
to test it.
the consumers of pcnet and NE2000 are qemu-mips, R7780MP and SHMIN.
Nobuhiro, could you comment this change?
This patch appears to have nothing to do with NE2000.
I think that this is pcnet only.
Best regards,
Nobuhiro
On Sun, Feb 3, 2013 at 4:42 AM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
2013/2/2 Gabor Juhos juh...@openwrt.org:
The pcnet driver uses the pci_phys_to_mem function
to get the memory address of the DMA buffers. This
This assumes an 1:1 mapping between the PCI and
physical memory which is not true on all platforms.
On MIPS platform U-Boot is running within a mapped
memory region, and the pci_phys_to_mem macro can't
be used to obtain the memory address of the buffers.
Signed-off-by: Gabor Juhos juh...@openwrt.org
Cc: Daniel Schwierzeck daniel.schwierz...@googlemail.com
---
Changes since v1:
- rebased against mips/testing
Changes since RFC: ---
---
Note:
This is only tested with the qemu-malta target. The change
might break real platforms, however I have no suitable board
to test it.
the consumers of pcnet and NE2000 are qemu-mips, R7780MP and SHMIN.
Nobuhiro, could you comment this change?
-Gabor
---
drivers/net/pcnet.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c
index c028a44..45a66fb 100644
--- a/drivers/net/pcnet.c
+++ b/drivers/net/pcnet.c
@@ -146,7 +146,7 @@ static int pcnet_recv (struct eth_device *dev);
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
-#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d-priv, (u_long)(a))
+#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d-priv, (a))
#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
static struct pci_device_id supported[] = {
--
1.7.10
--
Best regards,
Daniel
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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Re: [U-Boot] [PATCH v3] arm: rmobile: Add support Renesas SH73A0
Hi, Thanks for your review. On Sat, Aug 11, 2012 at 12:52 AM, Mike Frysinger vap...@gentoo.org wrote: On Friday 10 August 2012 03:41:17 Nobuhiro Iwamatsu wrote: --- a/arch/arm/cpu/armv7/rmobile/Makefile +++ b/arch/arm/cpu/armv7/rmobile/Makefile +clean: + rm -f $(SOBJS) $(OBJS) + dead code - delete -mike Thanks. I will remove these line. Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5] arm: rmobile: Add support Renesas SH73A0
From: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Renesas SH73A0 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu iwama...@nigauri.org
---
V5: Remove dead code.
V4: Revert ICCICR.
V3: Set COBJS one object per line, and sort the list.
Remove ICCICR and ICCPMR.
Remove white space.
v2: Remove white space.
Code which can be communalized was moved to lowlevel_init.
arch/arm/cpu/armv7/rmobile/Makefile | 14 +-
arch/arm/cpu/armv7/rmobile/board.c | 33 ++
arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c| 50 ++
arch/arm/cpu/armv7/rmobile/cpu_info.c | 36 +-
arch/arm/cpu/armv7/rmobile/lowlevel_init.S | 95
arch/arm/include/asm/arch-rmobile/rmobile.h |4 +
arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h | 553 +++
arch/arm/include/asm/arch-rmobile/sh73a0.h | 281
arch/arm/include/asm/arch-rmobile/sys_proto.h | 29 ++
9 files changed, 1071 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/cpu/armv7/rmobile/board.c
create mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
create mode 100644 arch/arm/cpu/armv7/rmobile/lowlevel_init.S
create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0.h
create mode 100644 arch/arm/include/asm/arch-rmobile/sys_proto.h
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile
b/arch/arm/cpu/armv7/rmobile/Makefile
index e7eb90f..b27d143 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -25,11 +25,17 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-COBJS += cpu_info.o
-COBJS += timer.o
+SOBJS = lowlevel_init.o
+COBJS-y += board.o
+COBJS-y += cpu_info.o
+COBJS-y += timer.o
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y))
+COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
+
+COBJS := $(COBJS-y)
+SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/rmobile/board.c
b/arch/arm/cpu/armv7/rmobile/board.c
new file mode 100644
index 000..55dc6be
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/board.c
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include common.h
+#include asm/io.h
+#include asm/arch/sys_proto.h
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf(Board: %s\n, sysinfo.board_string);
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
new file mode 100644
index 000..f5273cf
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include common.h
+#include asm/io.h
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+u32 rmobile_get_cpu_type(void)
+{
+ u32 id
Re: [U-Boot] [PATCH 25/37] arm: rmobile: Add support TMU base timer function
Hi,
Thanks for your review.
On Tue, Aug 14, 2012 at 8:26 AM, Kim Phillips
kim.phill...@freescale.com wrote:
patch 25/37 showing up in an otherwise unnumbered patchseries of 6,
and with the cover letter set to 'v3' where all 6 patches are at v2
makes for a highly confusing patchset.
Sorry, this is my mistake.
On Fri, 10 Aug 2012 16:16:12 +0900
Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote:
Some rmobile SoC has TMU base timer function. This supports TMU.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
V2: Set COBJS one object per line, and sort the list.
arch/arm/cpu/armv7/rmobile/Makefile |4 +-
arch/arm/cpu/armv7/rmobile/timer_tmu.c| 161
+
this is a copy of arch/sh/lib/time.c but with proper struct tmu_regs
instead of #defines; is it not possible to refactor merge the two?
I am going to merge next work.
+int timer_init(void)
+{
+ /* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
+ u16 bit = 0;
+
+ switch (CONFIG_SYS_TMU_CLK_DIV) {
+ case 1024:
+ bit = 4;
+ break;
+ case 256:
+ bit = 3;
+ break;
+ case 64:
+ bit = 2;
+ break;
+ case 16:
+ bit = 1;
+ break;
+ case 4:
+ default:
+ break;
+ }
Can this be broken down into a shift operation?
Sorry, I can not understand this.
This means not using swtich but using shift operation?
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH 2/2] rmobile: Add README
On Sat, Aug 11, 2012 at 12:07 AM, Tom Rini tr...@ti.com wrote:
On 08/10/2012 12:19 AM, Nobuhiro Iwamatsu wrote:
Hi,
On Fri, Aug 10, 2012 at 2:03 AM, Tom Rini tr...@ti.com wrote:
On Thu, Aug 09, 2012 at 11:30:24PM +0900, Nobuhiro Iwamatsu wrote:
This add README of Renesas RMOBILE.
Based doc/README.omap3.
Signed-off-by: Nobuhiro Iwamatsu iwama...@nigauri.org
---
doc/README.rmobile | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 doc/README.rmobile
diff --git a/doc/README.rmobile b/doc/README.rmobile
new file mode 100644
index 000..b6acb28
--- /dev/null
+++ b/doc/README.rmobile
@@ -0,0 +1,46 @@
+Summary
+===
+
+This README is about U-Boot support for Renesas's ARM Cortex-A9 based
RMOBILE[1]
+family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9.
+
+Currently the following boards are supported:
+
+* KMC KZM-A9-GT [2]
+
+* Atmark-Techno Armadillo-800-EVA [3]
+
+Toolchain
+=
+
+While ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a) we
compile
+with -march=armv5 to allow more compilers to work. For U-Boot code this
has
+no performance impact.
Is this really an issue today? Between ELDK, Linaro and CodeSourcey
(and many other options too) it's really easy to get a v7 toolchain.
You are right. I will fix this sentence.
Was the doc wrong or do you mean you'll change the Makefile as well? :)
Thanks!
No, I don' t change Makefile. I will add infomation about how to get compiler.
Nobuhiro
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Re: [U-Boot] [PATCH 25/37] arm: rmobile: Add support TMU base timer function
Hi,
On Tue, Aug 21, 2012 at 9:18 AM, Kim Phillips
kim.phill...@freescale.com wrote:
On Mon, 20 Aug 2012 00:21:10 +0900
Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote:
On Tue, Aug 14, 2012 at 8:26 AM, Kim Phillips
kim.phill...@freescale.com wrote:
On Fri, 10 Aug 2012 16:16:12 +0900
Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote:
Some rmobile SoC has TMU base timer function. This supports TMU.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
V2: Set COBJS one object per line, and sort the list.
arch/arm/cpu/armv7/rmobile/Makefile |4 +-
arch/arm/cpu/armv7/rmobile/timer_tmu.c| 161
+
this is a copy of arch/sh/lib/time.c but with proper struct tmu_regs
instead of #defines; is it not possible to refactor merge the two?
I am going to merge next work.
not sure what this means, but usually u-boot development favours
initially refactoring common code rather than duplicating it, and
then refactoring it (although I wouldn't know where common timer code
across arches could live).
OK, I will work about this.
maybe, I think that timer common code of SH was moved to drivers/timer.
+int timer_init(void)
+{
+ /* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
+ u16 bit = 0;
+
+ switch (CONFIG_SYS_TMU_CLK_DIV) {
+ case 1024:
+ bit = 4;
+ break;
+ case 256:
+ bit = 3;
+ break;
+ case 64:
+ bit = 2;
+ break;
+ case 16:
+ bit = 1;
+ break;
+ case 4:
+ default:
+ break;
+ }
Can this be broken down into a shift operation?
Sorry, I can not understand this.
This means not using swtich but using shift operation?
Sorry, I meant this: (ffs(CONFIG_SYS_TMU_CLK_DIV) 1) - 1
I see. Thanks for your point. I forgot ffs().
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH v5] arm: rmobile: Add support Renesas SH73A0
Hi,
Thanks for your review.
On Mon, Aug 20, 2012 at 12:00 PM, Mike Frysinger vap...@gentoo.org wrote:
On Sunday 19 August 2012 10:40:05 Nobuhiro Iwamatsu wrote:
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/board.c
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf(Board: %s\n, sysinfo.board_string);
+ return 0;
+}
+#endif /* CONFIG_DISPLAY_BOARDINFO */
seems like you could have the makefile do:
COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
then you wouldn't need these ifdefs in this file
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
+#ifdef CONFIG_DISPLAY_CPUINFO
+u32 rmobile_get_cpu_type(void)
+{
+ u32 id;
+ u32 type;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(hpb-cccr);
+ type = (id 8) 0xFF;
+
+ return type;
+}
+
+u32 get_cpu_rev(void)
+{
+ u32 id;
+ u32 rev;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE;
+
+ id = readl(hpb-cccr);
+ rev = (id 4) 0xF;
+
+ return rev;
+}
+#endif /* CONFIG_DISPLAY_CPUINFO */
seems like you could have the makefile do:
COBJS-$(CONFIG_DISPLAY_CPUINFO) += board.o
then you wouldn't need these ifdefs in this file
-mike
Thanks, I will fix these.
Nobuhiro
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[U-Boot] [PATCH 1/5] sh: tmu: Changed TMU driver using array of structures
This changed into access using array of structure from access to the register
using the definition of the register by macro.
And removed white space.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/sh/include/asm/clk.h|5 ---
arch/sh/include/asm/cpu_sh7706.h |5 +--
arch/sh/include/asm/cpu_sh7710.h |5 +--
arch/sh/include/asm/cpu_sh7720.h | 10 -
arch/sh/include/asm/cpu_sh7722.h | 11 +-
arch/sh/include/asm/cpu_sh7723.h | 11 +-
arch/sh/include/asm/cpu_sh7724.h | 11 +-
arch/sh/include/asm/cpu_sh7734.h |4 +-
arch/sh/include/asm/cpu_sh7750.h | 21 +--
arch/sh/include/asm/cpu_sh7757.h | 14 +--
arch/sh/include/asm/cpu_sh7763.h |5 +--
arch/sh/include/asm/cpu_sh7780.h | 24 +---
arch/sh/include/asm/cpu_sh7785.h | 24 +---
arch/sh/lib/time.c | 27 --
include/sh_tmu.h | 75 ++
15 files changed, 101 insertions(+), 151 deletions(-)
create mode 100644 include/sh_tmu.h
diff --git a/arch/sh/include/asm/clk.h b/arch/sh/include/asm/clk.h
index 9cac6b0..2164bfb 100644
--- a/arch/sh/include/asm/clk.h
+++ b/arch/sh/include/asm/clk.h
@@ -27,9 +27,4 @@ static inline unsigned long get_peripheral_clk_rate(void)
return CONFIG_SYS_CLK_FREQ;
}
-static inline unsigned long get_tmu0_clk_rate(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#endif /* __ASM_SH_CLK_H__ */
diff --git a/arch/sh/include/asm/cpu_sh7706.h b/arch/sh/include/asm/cpu_sh7706.h
index d093f88..8066ff7 100644
--- a/arch/sh/include/asm/cpu_sh7706.h
+++ b/arch/sh/include/asm/cpu_sh7706.h
@@ -41,10 +41,7 @@
#define SCIF0_BASE SCSMR_2
/* Timer */
-#define TSTR0 0xFE92
-#define TSTR TSTR0
-#define TCNT0 0xFE98
-#define TCR0 0xFE9C
+#define TMU_BASE 0xFE90
/* On chip oscillator circuits */
#defineWTCNT 0xFF84
diff --git a/arch/sh/include/asm/cpu_sh7710.h b/arch/sh/include/asm/cpu_sh7710.h
index e223f1c..e4ecef7 100644
--- a/arch/sh/include/asm/cpu_sh7710.h
+++ b/arch/sh/include/asm/cpu_sh7710.h
@@ -51,10 +51,7 @@
#define SCIF1_BASE SCSMR_1
/* Timer */
-#define TSTR0 0xA412FE92
-#define TSTR TSTR0
-#define TCNT0 0xa412FE98
-#define TCR0 0xa412FE9C
+#define TMU_BASE 0xA412FE90
/* On chip oscillator circuits */
#define FRQCR 0xA415FF80
diff --git a/arch/sh/include/asm/cpu_sh7720.h b/arch/sh/include/asm/cpu_sh7720.h
index 1b393b8..a8013cc 100644
--- a/arch/sh/include/asm/cpu_sh7720.h
+++ b/arch/sh/include/asm/cpu_sh7720.h
@@ -105,16 +105,6 @@
/* TMU */
#define TMU_BASE 0xA412FE90
-#define TSTR (TMU_BASE + 0x02)
-#define TCOR0 (TMU_BASE + 0x04)
-#define TCNT0 (TMU_BASE + 0x08)
-#define TCR0 (TMU_BASE + 0x0C)
-#define TCOR1 (TMU_BASE + 0x10)
-#define TCNT1 (TMU_BASE + 0x14)
-#define TCR1 (TMU_BASE + 0x18)
-#define TCOR2 (TMU_BASE + 0x1C)
-#define TCNT2 (TMU_BASE + 0x20)
-#define TCR2 (TMU_BASE + 0x24)
/* TPU */
#define TPU_BASE 0xA448
diff --git a/arch/sh/include/asm/cpu_sh7722.h b/arch/sh/include/asm/cpu_sh7722.h
index 3157dcb..92dfe27 100644
--- a/arch/sh/include/asm/cpu_sh7722.h
+++ b/arch/sh/include/asm/cpu_sh7722.h
@@ -226,16 +226,7 @@
/* TMU */
-#define TSTR0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR00xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR10xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR20xFFD80028
+#define TMU_BASE 0xFFD8
/* TPU */
#define TPU_TSTR0xA4C9
diff --git a/arch/sh/include/asm/cpu_sh7723.h b/arch/sh/include/asm/cpu_sh7723.h
index 6dac6e9..2595f29 100644
--- a/arch/sh/include/asm/cpu_sh7723.h
+++ b/arch/sh/include/asm/cpu_sh7723.h
@@ -95,16 +95,7 @@
#define WTCNT RWTCNT
/* TMU */
-#define TSTR0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR00xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR10xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR20xFFD80028
+#define TMU_BASE 0xFFD8
/* TPU */
diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h
index 3bb51d3..cd40b6d 100644
--- a/arch/sh/include/asm/cpu_sh7724.h
+++ b/arch/sh/include/asm/cpu_sh7724.h
@@ -116,16 +116,7 @@
#define WTCNT RWTCNT
/* TMU */
-#define TSTR0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR00xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR10xFFD8001C
-#define TCOR2 0xFFD80020
-#define
[U-Boot] [PATCH 3/5] sh: tmu: Removed arch/sh/include/asm/clk.h
asm/clk.h was included get_peripheral_clk_rate function. But this
is not used from anywhere.
This removed asm/clk.h, and deleted include line from arch/sh/lib/time.c
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/sh/include/asm/clk.h | 30 --
arch/sh/lib/time.c|1 -
2 files changed, 31 deletions(-)
delete mode 100644 arch/sh/include/asm/clk.h
diff --git a/arch/sh/include/asm/clk.h b/arch/sh/include/asm/clk.h
deleted file mode 100644
index 2164bfb..000
--- a/arch/sh/include/asm/clk.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __ASM_SH_CLK_H__
-#define __ASM_SH_CLK_H__
-
-static inline unsigned long get_peripheral_clk_rate(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-#endif /* __ASM_SH_CLK_H__ */
diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index 00230c3..2cc61dd 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -30,7 +30,6 @@
#include common.h
#include div64.h
#include asm/processor.h
-#include asm/clk.h
#include asm/io.h
#include sh_tmu.h
--
1.7.10
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[U-Boot] [PATCH 2/5] sh: tmu: Changed switch statement to shift operation
Calculation of the bit position using switch statement can substitute
shift operation using ffs.
And removed unsed macro and variable.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/sh/lib/time.c | 48 ++--
1 file changed, 18 insertions(+), 30 deletions(-)
diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index 4840472..00230c3 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -36,23 +36,26 @@
static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
-#define TMU_MAX_COUNTER (~0UL)
-
-static ulong timer_freq;
+static u16 bit;
static unsigned long last_tcnt;
static unsigned long long overflow_ticks;
+unsigned long get_tbclk(void)
+{
+ return get_tmu0_clk_rate() ((bit + 1) * 2);
+}
+
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, timer_freq);
+ do_div(tick, get_tbclk());
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
- usec *= timer_freq;
+ usec *= get_tbclk();
do_div(usec, 100);
return usec;
@@ -74,31 +77,9 @@ static void tmu_timer_stop(unsigned int timer)
int timer_init(void)
{
- /* Divide clock by CONFIG_SYS_TMU_CLK_DIV */
- u16 bit = 0;
-
- switch (CONFIG_SYS_TMU_CLK_DIV) {
- case 1024:
- bit = 4;
- break;
- case 256:
- bit = 3;
- break;
- case 64:
- bit = 2;
- break;
- case 16:
- bit = 1;
- break;
- case 4:
- default:
- break;
- }
+ bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) 1) - 1;
writew(readw(tmu-tcr0) | bit, tmu-tcr0);
- /* Calc clock rate */
- timer_freq = get_tmu0_clk_rate() ((bit + 1) * 2);
-
tmu_timer_stop(0);
tmu_timer_start(0);
@@ -137,7 +118,14 @@ unsigned long get_timer(unsigned long base)
return tick_to_time(get_ticks()) - base;
}
-unsigned long get_tbclk(void)
+void set_timer(unsigned long t)
+{
+ writel((0 - t), tmu-tcnt0);
+}
+
+void reset_timer(void)
{
- return timer_freq;
+ tmu_timer_stop(0);
+ set_timer(0);
+ tmu_timer_start(0);
}
--
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[U-Boot] [PATCH v3] arm: rmobile: Add support TMU base timer function
Some rmobile SoC has TMU base timer function. This supports TMU.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu iwama...@nigauri.org
---
V3: Merged arch/sh/lib/time.c
Need patches
* sh: tmu: Removed arch/sh/include/asm/clk.h
* sh: tmu: Changed switch statement to shift operation
* sh: tmu: Changed TMU driver using array of structures
V2: Set COBJS one object per line, and sort the list.
arch/arm/cpu/armv7/rmobile/Makefile |3 ++-
include/sh_tmu.h|2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile
b/arch/arm/cpu/armv7/rmobile/Makefile
index a522872..dd0aede 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -27,11 +27,12 @@ LIB = $(obj)lib$(SOC).o
SOBJS = lowlevel_init.o
COBJS-y += cpu_info.o
-COBJS-y += timer.o
COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+COBJS-$(CONFIG_GLOBAL_TIMER) += timer.o
COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
COBJS-$(CONFIG_SH73A0) += pfc-sh73a0.o
+COBJS-$(CONFIG_TMU_TIMER) += $(TOPDIR)/arch/sh/lib/time.o
COBJS := $(COBJS-y)
SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/include/sh_tmu.h b/include/sh_tmu.h
index a55d141..96c589d 100644
--- a/include/sh_tmu.h
+++ b/include/sh_tmu.h
@@ -47,7 +47,7 @@ struct tmu_regs {
};
#endif /* CONFIG_SH3 */
-#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
+#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) || defined(CONFIG_RMOBILE)
struct tmu_regs {
u32 reserved;
u8 tstr;
--
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[U-Boot] [PATCH v6] arm: rmobile: Add support Renesas SH73A0
Renesas SH73A0 is CPU with Cortex-A9.
This supports the basic register definition and GPIO.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu iwama...@nigauri.org
---
V6: Changed Makefile that using config.
Removed unnecessary ifdefs.
V5: Remove dead code.
V4: Revert ICCICR.
V3: Set COBJS one object per line, and sort the list.
Remove ICCICR and ICCPMR.
Remove white space.
v2: Remove white space.
Code which can be communalized was moved to lowlevel_init.
arch/arm/cpu/armv7/rmobile/Makefile | 14 +-
arch/arm/cpu/armv7/rmobile/board.c | 31 ++
arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c| 48 ++
arch/arm/cpu/armv7/rmobile/cpu_info.c | 36 +-
arch/arm/cpu/armv7/rmobile/lowlevel_init.S | 95
arch/arm/include/asm/arch-rmobile/rmobile.h |4 +
arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h | 553 +++
arch/arm/include/asm/arch-rmobile/sh73a0.h | 281
arch/arm/include/asm/arch-rmobile/sys_proto.h | 29 ++
9 files changed, 1067 insertions(+), 24 deletions(-)
create mode 100644 arch/arm/cpu/armv7/rmobile/board.c
create mode 100644 arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
create mode 100644 arch/arm/cpu/armv7/rmobile/lowlevel_init.S
create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
create mode 100644 arch/arm/include/asm/arch-rmobile/sh73a0.h
create mode 100644 arch/arm/include/asm/arch-rmobile/sys_proto.h
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile
b/arch/arm/cpu/armv7/rmobile/Makefile
index e7eb90f..77eca4b 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -25,11 +25,17 @@ include $(TOPDIR)/config.mk
LIB= $(obj)lib$(SOC).o
-COBJS += cpu_info.o
-COBJS += timer.o
+SOBJS = lowlevel_init.o
+COBJS-y += cpu_info.o
+COBJS-y += timer.o
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y))
+COBJS-$(CONFIG_DISPLAY_BOARDINFO) += board.o
+COBJS-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
+
+COBJS := $(COBJS-y)
+SRCS:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(LIB)
diff --git a/arch/arm/cpu/armv7/rmobile/board.c
b/arch/arm/cpu/armv7/rmobile/board.c
new file mode 100644
index 000..2622590
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/board.c
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include common.h
+#include asm/io.h
+#include asm/arch/sys_proto.h
+
+int checkboard(void)
+{
+ printf(Board: %s\n, sysinfo.board_string);
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
new file mode 100644
index 000..3086dd8
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ * (C) Copyright 2012 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include common.h
+#include asm/io.h
+
+u32 rmobile_get_cpu_type(void)
+{
+ u32 id;
+ u32 type;
+ struct sh73a0_hpb *hpb = (struct sh73a0_hpb
[U-Boot] [PATCH v2] rmobile: Add README
From: Nobuhiro Iwamatsu iwama...@nigauri.org This add README of Renesas RMOBILE. Based doc/README.omap3. Signed-off-by: Nobuhiro Iwamatsu iwama...@nigauri.org --- V2: Added more compiler infomation. doc/README.rmobile | 65 1 file changed, 65 insertions(+) create mode 100644 doc/README.rmobile diff --git a/doc/README.rmobile b/doc/README.rmobile new file mode 100644 index 000..7ec63f1 --- /dev/null +++ b/doc/README.rmobile @@ -0,0 +1,65 @@ +Summary +=== + +This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1] +family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9. + +Currently the following boards are supported: + +* KMC KZM-A9-GT [2] + +* Atmark-Techno Armadillo-800-EVA [3] + +Toolchain += + +ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a). +But currently we compile with -march=armv5 to allow more compilers to work. +(For U-Boot code this has no performance impact.) +Because there was no compiler which is supporting armv7a not much before. +Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a +and you can get. + +Build += + +* KZM-A9-GT + +make kzm9g_config +make + +* Armadillo-800-EVA + +make armadillo-800eva_config +make + +Links += + +[1] Renesas RMOBILE: + +http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp + +[2] KZM-A9-GT + +http://www.kmckk.co.jp/kzma9-gt/index.html + +[3] Armadillo-800-EVA + +http://armadillo.atmark-techno.com/armadillo-800-EVA + +[4] ELDK + +http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6. + +[5] Linaro + +http://www.linaro.org/downloads/ + +[6] CodeSourcey + +http://www.mentor.com/embedded-software/codesourcery + +[7] Emdebian + +http://www.emdebian.org/crosstools.html -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Request pull: u-boot-sh
Dear Wolfgang.
Please pull u-boot-sh master branch.
Best regards,
Nobuhiro
The following changes since commit e66443fdb5355e68cfdbbdd37248c4b7eb4968f5:
Makefile: fix HAVE_VENDOR_COMMON_LIB (2012-08-17 18:07:12 +0200)
are available in the git repository at:
git://git.denx.de/u-boot-sh.git master
for you to fetch changes up to 31d4fe8d405c4b9e27f7eca6c6710092ba14b49d:
sh: tmu: Removed arch/sh/include/asm/clk.h (2012-08-21 15:00:34 +0900)
Nobuhiro Iwamatsu (3):
sh: tmu: Changed TMU driver using array of structures
sh: tmu: Changed switch statement to shift operation
sh: tmu: Removed arch/sh/include/asm/clk.h
arch/sh/include/asm/clk.h| 35
arch/sh/include/asm/cpu_sh7706.h |5 +---
arch/sh/include/asm/cpu_sh7710.h |5 +---
arch/sh/include/asm/cpu_sh7720.h | 10
arch/sh/include/asm/cpu_sh7722.h | 11 +
arch/sh/include/asm/cpu_sh7723.h | 11 +
arch/sh/include/asm/cpu_sh7724.h | 11 +
arch/sh/include/asm/cpu_sh7734.h |4 +---
arch/sh/include/asm/cpu_sh7750.h | 21 +
arch/sh/include/asm/cpu_sh7757.h | 14 +---
arch/sh/include/asm/cpu_sh7763.h |5 +---
arch/sh/include/asm/cpu_sh7780.h | 24 +--
arch/sh/include/asm/cpu_sh7785.h | 24 +--
arch/sh/lib/time.c | 72
+
include/sh_tmu.h | 75
15 files changed, 117 insertions(+), 210 deletions(-)
delete mode 100644 arch/sh/include/asm/clk.h
create mode 100644 include/sh_tmu.h
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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[U-Boot] How to manage RMOBILE patches?
Dear, Wolfgang Denk. I am working supporting Renesas RMOBILE to U-Boot. Renesas's RMOBILE SoC family contains an ARM Cortex-A9, and this uses the same IP as SH. (For example, timer, ether, serial, etc.) I already sent to patches of rmobile, I got review from some developers. And the patch is managed by the arm/rmobile branch of u-boot-sh[0] which I have maintained, now. Since I had you take the patch of rmobile into an ARM repository, I consulted with Albert about the future development approach. We thought two methods are considered. One is Albert picks up a patch from ML to ARM repository, Another is whether to have pull from the repository by having a repository for rmobile made. And we decided to consult by ML. What do you think about this? Best regards, Nobuhiro --- [0]: git://git.denx.de/u-boot-sh.git arm/rmobile Hideyuki Sano (1): arm: rmobile: Add support for ATMARK-TECHNO Armadillo-800EVA board Nobuhiro Iwamatsu (20): ARMv7: Add register definition of global timer arm: rmobile: Add basic support for Renesas R-Mobile arm: rmobile: Add support Renesas SH73A0 arm: rmobile: Add support PFC of Renesas SH73A0 arm: rmobile: Add supoprt for KMC KZM-A9-GT board arm: rmobile: Support build with gcc-4.6 or later arm: rmobile: kzm9g: Add LIBFDT support arm: rmobile: kzm9g: remove unrelated config arm: rmobile: Change initializing ICCICR register arm: rmobile: Add support TMU base timer function arm: rmobile: kzm9g: Add CONFIG_GLOBAL_TIMER to board config file arm: rmobile: Add support Renesas R8A7740 arm: rmobile: Add support PFC of Renesas R8A7740 arm: rmobile: armadillo-800eva Remove board_eth_init arm: rmobile: Add cpu_eth_init function rmobile: armadillo-800eva: Change init function of SCIFA1 rmobile: armadillo-800eva: Add Support CONFIG_OF_LIBFDT rmobile: armadillo-800eva: Add Support NFS and BOOTZ command rmobile: armadillo-800eva: Remove CONFIG_SYS_NO_L2CACHE rmobile: Add README Tetsuyuki Kobayashi (11): arm: rmobile: kzm9g: Modify sdram area arm: rmobile: kzm9g: Adjust low level hardware setting arm: rmobile: kzm9g: change prompt to board specific arm: rmobile: kzm9g: Modify bus controller setting for CS4 arm: rmobile: kzm9g: enable reset command arm: rmobile: kzm9g: Add dummy member to struct sh73a0_rwdt arm: rmobile: kzm9g: Fix CONFIG_BAUDRATE setting arm: rmobile: kzm9g: add NFS_TIMEOUT in config file arm: rmobile: kzm9g: remove unrelated config arm: rmobile: kzm9g: fix CPU info arm: rmobile: kzm9g: separate cpu_rev to integer and fraction MAINTAINERS |8 + arch/arm/cpu/armv7/rmobile/Makefile | 59 +++ arch/arm/cpu/armv7/rmobile/board.c | 31 ++ arch/arm/cpu/armv7/rmobile/config.mk| 26 ++ arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c | 48 +++ arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c| 60 arch/arm/cpu/armv7/rmobile/cpu_info.c | 85 + arch/arm/cpu/armv7/rmobile/emac.c | 36 ++ arch/arm/cpu/armv7/rmobile/lowlevel_init.S | 98 + arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c| 2612 arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c | 2807 ++ arch/arm/cpu/armv7/rmobile/timer.c | 97 + arch/arm/include/asm/arch-armv7/globaltimer.h | 36 ++ arch/arm/include/asm/arch-rmobile/gpio.h| 12 + arch/arm/include/asm/arch-rmobile/irqs.h| 18 + arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h| 584 ++ arch/arm/include/asm/arch-rmobile/r8a7740.h | 287 +++ arch/arm/include/asm/arch-rmobile/rmobile.h | 14 + arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h | 553 arch/arm/include/asm/arch-rmobile/sh73a0.h | 289 +++ arch/arm/include/asm/arch-rmobile/sys_proto.h | 29 ++ arch/arm/include/asm/mach-types.h | 26 ++ board/atmark-techno/armadillo-800eva/Makefile | 46 +++ board/atmark-techno/armadillo-800eva/armadillo-800eva.c | 328 + board/kmc/kzm9g/Makefile| 50 +++ board/kmc/kzm9g/kzm9g.c | 377 +++ boards.cfg |2 + doc/README.rmobile | 65 include/configs/armadillo
Re: [U-Boot] How to manage RMOBILE patches?
Hi,
On Tue, Sep 4, 2012 at 4:15 AM, Wolfgang Denk w...@denx.de wrote:
Dear Nobuhiro Iwamatsu,
In message
CABMQnVLBEEjcEtfTzdeThHfTLp=b24qsognfjbzr-8ywytj...@mail.gmail.com you
wrote:
I am working supporting Renesas RMOBILE to U-Boot.
Renesas's RMOBILE SoC family contains an ARM Cortex-A9, and this uses
the same IP as SH.
(For example, timer, ether, serial, etc.)
I already sent to patches of rmobile, I got review from some developers.
And the patch is managed by the arm/rmobile branch of u-boot-sh[0]
which I have maintained, now.
Since I had you take the patch of rmobile into an ARM repository, I
consulted with Albert about the
future development approach.
We thought two methods are considered.
One is Albert picks up a patch from ML to ARM repository,
As this is ARM code, this appears the most natural approach to me.
Another is whether to have pull from the repository by having a
repository for rmobile made.
If this is an ARM SoC, then it should go through the ARM repo - even
if we should later decide that there is so much traffic that a
separate rmobile repo would be sustified, thi would still be a
sub-repo, which Albert would pull from.
Yes, I understood these. But Albert said I won't pull from
u-boot-sh.git. becauase this
repository is not ARM tree. in the inside of mail with him.
I think that I also want rmobile to receive request-pull like other
ARM SoCs if possible.
Of course, I want to take precedence to the code of rmobile being taken in.
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
___
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Re: [U-Boot] How to manage RMOBILE patches?
Hi,
On Wed, Sep 5, 2012 at 2:36 AM, Tom Rini tr...@ti.com wrote:
On Mon, Sep 03, 2012 at 09:15:56PM +0200, Wolfgang Denk wrote:
Dear Nobuhiro Iwamatsu,
In message
CABMQnVLBEEjcEtfTzdeThHfTLp=b24qsognfjbzr-8ywytj...@mail.gmail.com you
wrote:
I am working supporting Renesas RMOBILE to U-Boot.
Renesas's RMOBILE SoC family contains an ARM Cortex-A9, and this uses
the same IP as SH.
(For example, timer, ether, serial, etc.)
I already sent to patches of rmobile, I got review from some developers.
And the patch is managed by the arm/rmobile branch of u-boot-sh[0]
which I have maintained, now.
Since I had you take the patch of rmobile into an ARM repository, I
consulted with Albert about the
future development approach.
We thought two methods are considered.
One is Albert picks up a patch from ML to ARM repository,
As this is ARM code, this appears the most natural approach to me.
Another is whether to have pull from the repository by having a
repository for rmobile made.
If this is an ARM SoC, then it should go through the ARM repo - even
if we should later decide that there is so much traffic that a
separate rmobile repo would be sustified, thi would still be a
sub-repo, which Albert would pull from.
Another option, which Mike is using for, iirc, sf and blackfin, is just
to add rmobile-master / rmobile-next as branches to the u-boot-sh
repository.
Yes, this is one of easy way. But Albert won't pull form u-boot-sh, if
If my understanding is not wrong.
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
___
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Re: [U-Boot] How to manage RMOBILE patches?
Hi, Tom.
On Wed, Sep 5, 2012 at 11:17 PM, Tom Rini tr...@ti.com wrote:
On 09/05/2012 04:18 AM, Albert ARIBAUD wrote:
Hi Nobuhiro,
On Wed, 5 Sep 2012 11:26:37 +0900, Nobuhiro Iwamatsu
iwama...@nigauri.org wrote:
Hi,
On Wed, Sep 5, 2012 at 2:36 AM, Tom Rini tr...@ti.com wrote:
On Mon, Sep 03, 2012 at 09:15:56PM +0200, Wolfgang Denk wrote:
Dear Nobuhiro Iwamatsu,
In message
CABMQnVLBEEjcEtfTzdeThHfTLp=b24qsognfjbzr-8ywytj...@mail.gmail.com
you wrote:
I am working supporting Renesas RMOBILE to U-Boot.
Renesas's RMOBILE SoC family contains an ARM Cortex-A9, and this
uses the same IP as SH.
(For example, timer, ether, serial, etc.)
I already sent to patches of rmobile, I got review from some
developers. And the patch is managed by the arm/rmobile branch
of u-boot-sh[0] which I have maintained, now.
Since I had you take the patch of rmobile into an ARM
repository, I consulted with Albert about the
future development approach.
We thought two methods are considered.
One is Albert picks up a patch from ML to ARM repository,
As this is ARM code, this appears the most natural approach to me
Another is whether to have pull from the repository by having a
repository for rmobile made.
If this is an ARM SoC, then it should go through the ARM repo -
even if we should later decide that there is so much traffic that a
separate rmobile repo would be sustified, thi would still be a
sub-repo, which Albert would pull from.
Another option, which Mike is using for, iirc, sf and blackfin, is
just to add rmobile-master / rmobile-next as branches to the
u-boot-sh repository.
Yes, this is one of easy way. But Albert won't pull form u-boot-sh,
if If my understanding is not wrong.
This just means that they'll end up on u-boot/master from u-boot.sh (and
from there into u-boot-arm later on).
To be clear, what I'm saying is just add a few more branches to
u-boot-sh that Albert will pull (since they're ARM stuff). Say
u-boot-sh/rmobile/master and u-boot-sh/rmobile/next. Then not get too
hung up on which repository a merge message comes from. :)
I was going to do by how to explain you.
However, I think that Albert mistook by my shortage of explanation.
Thank you for following up.
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
___
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[U-Boot] [PATCH] sh: ap_sh4a_4a: Fixed initialization value of DDR memory
The wrong value was set as value of column of DDR memory for ap_sh4a_4a. 10 is the right value. This fixed this problem. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- board/alphaproject/ap_sh4a_4a/lowlevel_init.S |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S index f04b36b..cf9c225 100644 --- a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S +++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S @@ -330,7 +330,7 @@ init_dbsc3_ctrl_533: DBKIND_A: .long 0xFE800020 DBKIND_D: .long 0x0005 DBCONF_A: .long 0xFE800024 -DBCONF_D: .long 0x0D020901 +DBCONF_D: .long 0x0D020A01 DBTR0_A: .long 0xFE800040 DBTR0_D_533:.long 0x0004 -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] How to manage RMOBILE patches?
HI, Albert.
On Fri, Sep 7, 2012 at 4:28 AM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Nobuhiro,
On Thu, 6 Sep 2012 08:20:59 +0900, Nobuhiro Iwamatsu
iwama...@nigauri.org wrote:
Hi, Tom.
On Wed, Sep 5, 2012 at 11:17 PM, Tom Rini tr...@ti.com wrote:
On 09/05/2012 04:18 AM, Albert ARIBAUD wrote:
Hi Nobuhiro,
On Wed, 5 Sep 2012 11:26:37 +0900, Nobuhiro Iwamatsu
iwama...@nigauri.org wrote:
Hi,
On Wed, Sep 5, 2012 at 2:36 AM, Tom Rini tr...@ti.com wrote:
On Mon, Sep 03, 2012 at 09:15:56PM +0200, Wolfgang Denk wrote:
Dear Nobuhiro Iwamatsu,
In message
CABMQnVLBEEjcEtfTzdeThHfTLp=b24qsognfjbzr-8ywytj...@mail.gmail.com
you wrote:
I am working supporting Renesas RMOBILE to U-Boot.
Renesas's RMOBILE SoC family contains an ARM Cortex-A9, and
this uses the same IP as SH.
(For example, timer, ether, serial, etc.)
I already sent to patches of rmobile, I got review from some
developers. And the patch is managed by the arm/rmobile branch
of u-boot-sh[0] which I have maintained, now.
Since I had you take the patch of rmobile into an ARM
repository, I consulted with Albert about the
future development approach.
We thought two methods are considered.
One is Albert picks up a patch from ML to ARM repository,
As this is ARM code, this appears the most natural approach to
me
Another is whether to have pull from the repository by having a
repository for rmobile made.
If this is an ARM SoC, then it should go through the ARM repo -
even if we should later decide that there is so much traffic
that a separate rmobile repo would be sustified, thi would
still be a sub-repo, which Albert would pull from.
Another option, which Mike is using for, iirc, sf and blackfin,
is just to add rmobile-master / rmobile-next as branches to the
u-boot-sh repository.
Yes, this is one of easy way. But Albert won't pull form
u-boot-sh, if If my understanding is not wrong.
This just means that they'll end up on u-boot/master from
u-boot.sh (and from there into u-boot-arm later on).
To be clear, what I'm saying is just add a few more branches to
u-boot-sh that Albert will pull (since they're ARM stuff). Say
u-boot-sh/rmobile/master and u-boot-sh/rmobile/next. Then not get
too hung up on which repository a merge message comes from. :)
I was going to do by how to explain you.
However, I think that Albert mistook by my shortage of explanation.
Thank you for following up.
Nobuhiro
I understand that some ARM patches would be stored in some branch
(say rmobile/master) of the u-boot-sh repo and pull-requested to me
from there.
What I still don't understand is *why* this should be done. Before they
get on this branch, the patches would still have to go through the
mailing list for review, just like the ARM patches that end up applied
to u-boot-arm/master, except they'd have to do through an intermediate
branch. If there are benefits in this, someone will have to lay them
out for me, because right now I don't see them.
Because I thought that it was easier to manage patches as Tom was also written.
OK, I understood your thought.
Best regards,
Nobuhiro
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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Re: [U-Boot] How to manage RMOBILE patches?
Hi,
On Sat, Sep 8, 2012 at 2:09 AM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
Hi Tom,
On Thu, 6 Sep 2012 13:58:57 -0700, Tom Rini tr...@ti.com wrote:
On 09/06/2012 12:28 PM, Albert ARIBAUD wrote:
Hi Nobuhiro,
On Thu, 6 Sep 2012 08:20:59 +0900, Nobuhiro Iwamatsu
iwama...@nigauri.org wrote:
Hi, Tom.
On Wed, Sep 5, 2012 at 11:17 PM, Tom Rini tr...@ti.com wrote:
On 09/05/2012 04:18 AM, Albert ARIBAUD wrote:
Hi Nobuhiro,
On Wed, 5 Sep 2012 11:26:37 +0900, Nobuhiro Iwamatsu
iwama...@nigauri.org wrote:
Hi,
On Wed, Sep 5, 2012 at 2:36 AM, Tom Rini tr...@ti.com wrote:
On Mon, Sep 03, 2012 at 09:15:56PM +0200, Wolfgang Denk wrote:
Dear Nobuhiro Iwamatsu,
In message
CABMQnVLBEEjcEtfTzdeThHfTLp=b24qsognfjbzr-8ywytj...@mail.gmail.com
you wrote:
I am working supporting Renesas RMOBILE to U-Boot.
Renesas's RMOBILE SoC family contains an ARM Cortex-A9, and
this uses the same IP as SH.
(For example, timer, ether, serial, etc.)
I already sent to patches of rmobile, I got review from some
developers. And the patch is managed by the arm/rmobile
branch of u-boot-sh[0] which I have maintained, now.
Since I had you take the patch of rmobile into an ARM
repository, I consulted with Albert about the
future development approach.
We thought two methods are considered.
One is Albert picks up a patch from ML to ARM repository,
As this is ARM code, this appears the most natural approach to
me
Another is whether to have pull from the repository by
having a repository for rmobile made.
If this is an ARM SoC, then it should go through the ARM repo
- even if we should later decide that there is so much traffic
that a separate rmobile repo would be sustified, thi would
still be a sub-repo, which Albert would pull from.
Another option, which Mike is using for, iirc, sf and blackfin,
is just to add rmobile-master / rmobile-next as branches to the
u-boot-sh repository.
Yes, this is one of easy way. But Albert won't pull form
u-boot-sh, if If my understanding is not wrong.
This just means that they'll end up on u-boot/master from
u-boot.sh (and from there into u-boot-arm later on).
To be clear, what I'm saying is just add a few more branches to
u-boot-sh that Albert will pull (since they're ARM stuff). Say
u-boot-sh/rmobile/master and u-boot-sh/rmobile/next. Then not get
too hung up on which repository a merge message comes from. :)
I was going to do by how to explain you.
However, I think that Albert mistook by my shortage of explanation.
Thank you for following up.
Nobuhiro
I understand that some ARM patches would be stored in some branch
(say rmobile/master) of the u-boot-sh repo and pull-requested to me
from there.
What I still don't understand is *why* this should be done. Before
they get on this branch, the patches would still have to go through
the mailing list for review, just like the ARM patches that end up
applied to u-boot-arm/master, except they'd have to do through an
intermediate branch. If there are benefits in this, someone will
have to lay them out for me, because right now I don't see them.
I think the answer is, given how you wish to work, there's not. It's
a workflow problem only. If it's no easier for you to get a pull
request from Nobuhiro once the patches have been reviewed than for
you to pull them out of patchwork once they have been reviewed, then
since your preference is for patchwork, via patchwork and into
u-boot-arm is how they'll work.
Thanks for this answer. I personally prefer applying patches from
patchwork directly into u-boot-arm/master.
OK, could you pickup rmobile patches from patchwork, please?
But I already archived rmobile patches in patchwork..
Best regards,
Nobuhiro
--
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iwamatsu at {nigauri.org / debian.org}
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Re: [U-Boot] [PATCH 2/3] i2c: sh_i2c.c: correct BUSY bit define in ICSR
Hi, I add Heiko Schocher h...@denx.de to Cc: Heiko is I2C maintainer. On Tue, Sep 11, 2012 at 2:58 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote: Correct BUSY bit define in ICSR from (13) to (14). Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Iwamatsu-san, I guess this was mistake. But I don't have technical document other than SH73A0. Could you verify? Yes, this is typo. 3 is AL bit. Thanks! Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com drivers/i2c/sh_i2c.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 59402ba..84f1f5b 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -43,7 +43,7 @@ static struct sh_i2c *base; #define SH_I2C_ICCR_SCP(1 0) /* ICSR / ICIC */ -#define SH_IC_BUSY (1 3) +#define SH_IC_BUSY (1 4) #define SH_IC_TACK (1 2) #define SH_IC_WAIT (1 1) #define SH_IC_DTE (1 0) -- 1.7.9.5 -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] i2c: sh_i2c.c: support iccl and icch extension
Hi,
I add Heiko Schocher h...@denx.de to Cc:
Heiko is I2C maintainer.
On Tue, Sep 11, 2012 at 2:58 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote:
R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl
and icch.
This patch add support for the extentin bits.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
drivers/i2c/sh_i2c.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index fd8cb92..59402ba 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -48,7 +48,15 @@ static struct sh_i2c *base;
#define SH_IC_WAIT (1 1)
#define SH_IC_DTE (1 0)
-static u8 iccl, icch;
+#if defined(CONFIG_SH73A0)
+#define HAS_ICIC67
+#endif
+#ifdef HAS_ICIC67
+#define SH_I2C_ICIC_ICCLB8 (1 7)
+#define SH_I2C_ICIC_ICCHB8 (1 6)
+#endif
I think that it was better to define CONFIG_SH_I2C_8BIT or
CONFIG_SH_I2C_HAS_ICIC67 in board config.
Because R8A7740 have this function too. I am working to support i2c of this CPU.
For example
#define CONFIG_SH_I2C_8BIT
#define SH_I2C_ICIC_ICCLB8 (1 7)
#define SH_I2C_ICIC_ICCHB8 (1 6)
#endif
I think that this is too simple.
+
+static u16 iccl, icch;
#define IRQ_WAIT 1000
@@ -92,12 +100,20 @@ static void irq_busy(struct sh_i2c *base)
static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
+ u8 icic = 0;
+
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
- writeb(iccl, base-iccl);
- writeb(icch, base-icch);
- writeb(0, base-icic);
+ writeb(iccl 0xff, base-iccl);
+ writeb(icch 0xff, base-icch);
+#ifdef HAS_ICIC67
+ if (iccl 0xff)
+ icic |= SH_I2C_ICIC_ICCLB8;
+ if (icch 0xff)
+ icic |= SH_I2C_ICIC_ICCHB8;
+#endif
+ writeb(icic, base-icic);
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY),
base-iccr);
irq_dte(base);
@@ -222,18 +238,18 @@ void i2c_init(int speed, int slaveaddr)
denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- iccl = (u8)((num/denom) + 1);
+ iccl = (u16)((num/denom) + 1);
else
- iccl = (u8)(num/denom);
+ iccl = (u16)(num/denom);
/* Calculate the value for icch. From the data sheet:
icch = (p clock / transfer rate) * (H / (L + H)) */
num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- icch = (u8)((num/denom) + 1);
+ icch = (u16)((num/denom) + 1);
else
- icch = (u8)(num/denom);
+ icch = (u16)(num/denom);
}
/*
--
1.7.9.5
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH 3/3] i2c: sh_i2c.c: adjust for SH73A0
Hi,
I add Heiko Schocher h...@denx.de to Cc:
Heiko is I2C maintainer.
On Tue, Sep 11, 2012 at 2:58 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote:
Adjust i2c_raw_read() in sh_i2c.c to work for SH73A0.
After this patch, i2c md and i2c mw command on U-Boot work properly on
KZM-A9-GT board.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/i2c/sh_i2c.c|4
include/configs/kzm9g.h |2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 84f1f5b..e8efdc9 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -153,8 +153,12 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8
reg)
{
u8 ret;
+#if defined(CONFIG_SH73A0)
+ i2c_set_addr(base, id, reg, 0);
+#else
i2c_set_addr(base, id, reg, 1);
udelay(100);
+#endif
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY),
base-iccr);
irq_dte(base);
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index a1ae718..5eccd29 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -163,7 +163,7 @@
#define CONFIG_SYS_I2C_SLAVE(0x7F)
#define CONFIG_SH_I2C_DATA_HIGH (4)
#define CONFIG_SH_I2C_DATA_LOW (5)
-#define CONFIG_SH_I2C_CLOCK (4166)
+#define CONFIG_SH_I2C_CLOCK (10400) /* 104 MHz */
#define CONFIG_SH_I2C_BASE0 (0xE682)
#define CONFIG_SH_I2C_BASE1 (0xE6822000)
--
1.7.9.5
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH v2 4/9] i2c: sh_i2c.c: support I2C2, I2C3 and I2C4
On Wed, Sep 12, 2012 at 5:21 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote: sh_i2c.c support I2C0 and I2C1. This patch extends it to I2C4. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new drivers/i2c/sh_i2c.c| 15 +++ include/configs/kzm9g.h |5 - 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c index 6c6a141..d524619 100644 --- a/drivers/i2c/sh_i2c.c +++ b/drivers/i2c/sh_i2c.c @@ -200,6 +200,21 @@ int i2c_set_bus_num(unsigned int bus) case 1: base = (void *)CONFIG_SH_I2C_BASE1; break; +#ifdef CONFIG_SH_I2C_BASE2 + case 2: + base = (void *)CONFIG_SH_I2C_BASE2; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE3 + case 3: + base = (void *)CONFIG_SH_I2C_BASE3; + break; +#endif +#ifdef CONFIG_SH_I2C_BASE4 + case 4: + base = (void *)CONFIG_SH_I2C_BASE4; + break; +#endif default: return -1; } diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index abeab69..6a0b6c5 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -158,7 +158,7 @@ #define CONFIG_SH_I2C_8BIT #define CONFIG_HARD_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_MAX_I2C_BUS (2) +#define CONFIG_SYS_MAX_I2C_BUS (5) #define CONFIG_SYS_I2C_MODULE #define CONFIG_SYS_I2C_SPEED(10) /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE(0x7F) @@ -167,5 +167,8 @@ #define CONFIG_SH_I2C_CLOCK (10400) /* 104 MHz */ #define CONFIG_SH_I2C_BASE0 (0xE682) #define CONFIG_SH_I2C_BASE1 (0xE6822000) +#define CONFIG_SH_I2C_BASE2 (0xE6824000) +#define CONFIG_SH_I2C_BASE3 (0xE6826000) +#define CONFIG_SH_I2C_BASE4 (0xE6828000) #endif /* __KZM9G_H */ -- 1.7.9.5 Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/9] i2c: sh_i2c: enable i2c_probe
On Wed, Sep 12, 2012 at 5:46 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote:
Before this patch i2c_probe() always returned 0 and i2c probe command did
not work properly.
Modify i2c_set_addr() to check TACK when waiting DTE and make i2c_probe()
call this function.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 29 -
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index d524619..25dbc43 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -85,6 +85,21 @@ static void irq_dte(struct sh_i2c *base)
}
}
+static int irq_dte_with_tack(struct sh_i2c *base)
+{
+ int i;
+ int ret = 0;
+
+ for (i = 0 ; i IRQ_WAIT ; i++) {
+ if (SH_IC_DTE readb(base-icsr))
+ break;
+ if (SH_IC_TACK readb(base-icsr))
+ return -1;
+ udelay(10);
+ }
+ return ret;
+}
+
static void irq_busy(struct sh_i2c *base)
{
int i;
@@ -96,9 +111,9 @@ static void irq_busy(struct sh_i2c *base)
}
}
-static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
- u8 icic = 0;
+ u8 icic = SH_IC_TACK;
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
@@ -116,14 +131,18 @@ static void i2c_set_addr(struct sh_i2c *base, u8 id, u8
reg, int stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY),
base-iccr);
irq_dte(base);
+ writeb(readb(base-icsr) ~SH_IC_TACK, base-icsr);
writeb(id 1, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb(reg, base-icdr);
if (stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
+ return 0;
}
static void i2c_finish(struct sh_i2c *base)
@@ -321,5 +340,5 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer,
int len)
*/
int i2c_probe(u8 chip)
{
- return 0;
+ return i2c_set_addr(base, chip, 0, 1);
}
--
1.7.9.5
Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH v2 1/9] i2c: sh_i2c.c: support iccl and icch extension
On Wed, Sep 12, 2012 at 5:46 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote:
R-mobile SoC (at least SH73A0) has extension bits to store 8th bit of iccl
and icch.
This patch add support for the extentin bits.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- define CONFIG_SH_I2C_8BIT at board config file and replace HAS_ICIC67.
drivers/i2c/sh_i2c.c| 30 ++
include/configs/kzm9g.h |1 +
2 files changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index fd8cb92..b98fce5 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -48,7 +48,13 @@ static struct sh_i2c *base;
#define SH_IC_WAIT (1 1)
#define SH_IC_DTE (1 0)
-static u8 iccl, icch;
+#ifdef CONFIG_SH_I2C_8BIT
+/* store 8th bit of iccl and icch in ICIC register */
+#define SH_I2C_ICIC_ICCLB8 (1 7)
+#define SH_I2C_ICIC_ICCHB8 (1 6)
+#endif
+
+static u16 iccl, icch;
#define IRQ_WAIT 1000
@@ -92,12 +98,20 @@ static void irq_busy(struct sh_i2c *base)
static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
+ u8 icic = 0;
+
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
- writeb(iccl, base-iccl);
- writeb(icch, base-icch);
- writeb(0, base-icic);
+ writeb(iccl 0xff, base-iccl);
+ writeb(icch 0xff, base-icch);
+#ifdef CONFIG_SH_I2C_8BIT
+ if (iccl 0xff)
+ icic |= SH_I2C_ICIC_ICCLB8;
+ if (icch 0xff)
+ icic |= SH_I2C_ICIC_ICCHB8;
+#endif
+ writeb(icic, base-icic);
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY),
base-iccr);
irq_dte(base);
@@ -222,18 +236,18 @@ void i2c_init(int speed, int slaveaddr)
denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- iccl = (u8)((num/denom) + 1);
+ iccl = (u16)((num/denom) + 1);
else
- iccl = (u8)(num/denom);
+ iccl = (u16)(num/denom);
/* Calculate the value for icch. From the data sheet:
icch = (p clock / transfer rate) * (H / (L + H)) */
num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
tmp = num * 10 / denom;
if (tmp % 10 = 5)
- icch = (u8)((num/denom) + 1);
+ icch = (u16)((num/denom) + 1);
else
- icch = (u8)(num/denom);
+ icch = (u16)(num/denom);
}
/*
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index a1ae718..8877516 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -155,6 +155,7 @@
/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SH_I2C 1
+#define CONFIG_SH_I2C_8BIT
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS (2)
--
1.7.9.5
Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH v2 6/9] i2c: sh_i2c.c: check error in i2c_read and i2c_write
On Wed, Sep 12, 2012 at 5:21 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote:
Before this patch, i2c_{read,write} always returned 0.
Check TACK in i2c_raw_{read,write} so that i2c_{read,write} return non-zero
when error.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 44
1 file changed, 28 insertions(+), 16 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index 25dbc43..e3ee804 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -151,29 +151,35 @@ static void i2c_finish(struct sh_i2c *base)
writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
}
-static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
{
- i2c_set_addr(base, id, reg, 0);
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ return -1;
udelay(10);
writeb(val, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
irq_busy(base);
i2c_finish(base);
+ return 0;
}
-static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
{
- u8 ret;
+ int ret;
#if defined(CONFIG_SH73A0)
- i2c_set_addr(base, id, reg, 0);
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ return -1;
#else
- i2c_set_addr(base, id, reg, 1);
+ if (i2c_set_addr(base, id, reg, 1) != 0)
+ return -1;
udelay(100);
#endif
@@ -181,12 +187,14 @@ static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8
reg)
irq_dte(base);
writeb(id 1 | 0x01, base-icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), base-iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
- ret = readb(base-icdr);
+ ret = readb(base-icdr) 0xff;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), base-iccr);
readb(base-icdr); /* Dummy read */
@@ -303,10 +311,14 @@ void i2c_init(int speed, int slaveaddr)
*/
int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
{
+ int ret;
int i = 0;
- for (i = 0 ; i len ; i++)
- buffer[i] = i2c_raw_read(base, chip, addr + i);
-
+ for (i = 0 ; i len ; i++) {
+ ret = i2c_raw_read(base, chip, addr + i);
+ if (ret 0)
+ return -1;
+ buffer[i] = ret 0xff;
+ }
return 0;
}
@@ -327,8 +339,8 @@ int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer,
int len)
{
int i = 0;
for (i = 0; i len ; i++)
- i2c_raw_write(base, chip, addr + i, buffer[i]);
-
+ if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
+ return -1;
return 0;
}
--
1.7.9.5
Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH v2 7/9] i2c: sh_i2c.c: remove unused function
On Wed, Sep 12, 2012 at 5:46 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote:
irq_wait() was not used. So removed it to elminate compiler warnings.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v2:
- new
drivers/i2c/sh_i2c.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index e3ee804..60bad52 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -58,22 +58,6 @@ static u16 iccl, icch;
#define IRQ_WAIT 1000
-static void irq_wait(struct sh_i2c *base)
-{
- int i;
- u8 status;
-
- for (i = 0 ; i IRQ_WAIT ; i++) {
- status = readb(base-icsr);
- if (SH_IC_WAIT status)
- break;
-
- udelay(10);
- }
-
- writeb(status ~SH_IC_WAIT, base-icsr);
-}
-
static void irq_dte(struct sh_i2c *base)
{
int i;
--
1.7.9.5
Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Best regards,
Nobuhiro
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Re: [U-Boot] [PATCH v2 8/9] arm: rmobile: kzm9g: enable I2C1
On Wed, Sep 12, 2012 at 5:46 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote: Supply clock to I2C1 and release resetting. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new board/kmc/kzm9g/kzm9g.c |5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 0679be6..93ca9d7 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -43,6 +43,7 @@ DECLARE_GLOBAL_DATA_PTR; #define SMSTPCR1_CMT0 (1 24) #define SMSTPCR1_I2C0 (1 16) #define SMSTPCR3_USB (1 22) +#define SMSTPCR3_I2C1 (1 23) #define PORT32CR (0xE6051020) #define PORT33CR (0xE6051021) @@ -300,8 +301,8 @@ int board_early_init_f(void) clrbits_le32(cpg-smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); clrbits_le32(cpg_srcr-srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(cpg-smstpcr3, SMSTPCR3_USB); - clrbits_le32(cpg_srcr-srcr3, SMSTPCR3_USB); + clrbits_le32(cpg-smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); + clrbits_le32(cpg_srcr-srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); writel(VCLKCR1_D, cpg-vclkcr1); /* Setup SCIF4 / workaround */ -- 1.7.9.5 Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v2 0/9] i2c for R-mobile
Hi, Thank you for this work. If you have a time, could you update sh_i2c using set/clrbits functions? these functions is included in asm/io.h. For example, you can change from writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr); to clrbits_8(base-iccr, SH_I2C_ICCR_ICE); . Best regards, Nobuhiro On Wed, Sep 12, 2012 at 5:46 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote: Some mails seems to be missing. I am sending again.. Hi, Iwamatsu-san Hello, Heiko Iwamatu-san, thank you for review. This is v2 patch for sh_i2c. Now i2c dev and i2c probe also work properly on KZM-A9-GT board. I think this modification is common for R-mobile, but I have SH73A0 document only. Iwamatu-san, please review this. This patch set is based on arm/rmobile branch of u-boot-sh.git. Tetsuyuki Kobayashi (9): i2c: sh_i2c.c: support iccl and icch extension i2c: sh_i2c.c: correct BUSY bit define in ICSR i2c: sh_i2c.c: adjust for SH73A0 i2c: sh_i2c.c: support I2C2, I2C3 and I2C4 i2c: sh_i2c: enable i2c_probe i2c: sh_i2c.c: check error in i2c_read and i2c_write i2c: sh_i2c.c: remove unused function arm: rmobile: kzm9g: enable I2C1 arm: rmobile: kzm9g: enable I2C2 board/kmc/kzm9g/kzm9g.c |7 ++- drivers/i2c/sh_i2c.c| 120 +-- include/configs/kzm9g.h |8 +++- 3 files changed, 95 insertions(+), 40 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 9/9] arm: rmobile: kzm9g: enable I2C2
On Wed, Sep 12, 2012 at 5:46 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote: Set gpio config for I2C2. Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp --- Changes for v2: - new board/kmc/kzm9g/kzm9g.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c index 93ca9d7..22f581a 100644 --- a/board/kmc/kzm9g/kzm9g.c +++ b/board/kmc/kzm9g/kzm9g.c @@ -370,6 +370,8 @@ int board_init(void) gpio_direction_output(GPIO_PORT15, 1); /* I2C */ + gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); + gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); -- 1.7.9.5 Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 10/10] i2c: sh_i2c: use setbits/clrbits macro
On Fri, Sep 14, 2012 at 2:08 PM, Tetsuyuki Kobayashi k...@kmckk.co.jp wrote:
Use setbits/clrbits macro when read-modify-write register.
Signed-off-by: Tetsuyuki Kobayashi k...@kmckk.co.jp
---
Changes for v3:
- new
drivers/i2c/sh_i2c.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/sh_i2c.c b/drivers/i2c/sh_i2c.c
index afcb503..44ba90e 100644
--- a/drivers/i2c/sh_i2c.c
+++ b/drivers/i2c/sh_i2c.c
@@ -98,8 +98,8 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg,
int stop)
{
u8 icic = SH_IC_TACK;
- writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
- writeb(readb(base-iccr) | SH_I2C_ICCR_ICE, base-iccr);
+ clrbits_8(base-iccr, SH_I2C_ICCR_ICE);
+ setbits_8(base-iccr, SH_I2C_ICCR_ICE);
writeb(iccl 0xff, base-iccl);
writeb(icch 0xff, base-icch);
@@ -114,7 +114,7 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8
reg, int stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY),
base-iccr);
irq_dte(base);
- writeb(readb(base-icsr) ~SH_IC_TACK, base-icsr);
+ clrbits_8(base-icsr, SH_IC_TACK);
writeb(id 1, base-icdr);
if (irq_dte_with_tack(base) != 0)
return -1;
@@ -131,7 +131,7 @@ static int i2c_set_addr(struct sh_i2c *base, u8 id, u8
reg, int stop)
static void i2c_finish(struct sh_i2c *base)
{
writeb(0, base-icsr);
- writeb(readb(base-iccr) ~SH_I2C_ICCR_ICE, base-iccr);
+ clrbits_8(base-iccr, SH_I2C_ICCR_ICE);
}
static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
--
1.7.9.5
Acked-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Thanks!
Nobuhiro
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Re: [U-Boot] [PATCH 61/71] serial: sh: Implement CONFIG_SERIAL_MULTI into sh serial driver
On Mon, Sep 17, 2012 at 8:21 AM, Marek Vasut ma...@denx.de wrote:
Implement support for CONFIG_SERIAL_MULTI into sh serial driver.
This driver was so far only usable directly, but this patch also adds
support for the multi method. This allows using more than one serial
driver alongside the sh driver. Also, add a weak implementation
of default_serial_console() returning this driver.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Marek Vasut marek.va...@gmail.com
Cc: Tom Rini tr...@ti.com
Cc: Phil Edworthy phil.edwor...@renesas.com
Cc: Nobuhiro Iwamatsu iwama...@nigauri.org
Acked-by: Nobuhiro Iwamatsu iwama...@nigauri.org
---
common/serial.c|2 ++
drivers/serial/serial_sh.c | 65
2 files changed, 61 insertions(+), 6 deletions(-)
diff --git a/common/serial.c b/common/serial.c
index 3dae01b..631af65 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -91,6 +91,7 @@ serial_initfunc(netarm_serial_initialize);
serial_initfunc(pl01x_serial_initialize);
serial_initfunc(s3c44b0_serial_initialize);
serial_initfunc(sa1100_serial_initialize);
+serial_initfunc(sh_serial_initialize);
void serial_register(struct serial_device *dev)
{
@@ -160,6 +161,7 @@ void serial_initialize(void)
pl01x_serial_initialize();
s3c44b0_serial_initialize();
sa1100_serial_initialize();
+ sh_serial_initialize();
serial_assign(default_serial_console()-name);
}
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 13919c6..8c30397 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -55,13 +55,13 @@ static struct uart_port sh_sci = {
.type = SCIF_BASE_PORT,
};
-void serial_setbrg(void)
+static void sh_serial_setbrg(void)
{
DECLARE_GLOBAL_DATA_PTR;
sci_out(sh_sci, SCBRR, SCBRR_VALUE(gd-baudrate,
CONFIG_SYS_CLK_FREQ));
}
-int serial_init(void)
+static int sh_serial_init(void)
{
sci_out(sh_sci, SCSCR , SCSCR_INIT(sh_sci));
sci_out(sh_sci, SCSCR , SCSCR_INIT(sh_sci));
@@ -127,21 +127,21 @@ void serial_raw_putc(const char c)
sci_out(sh_sci, SCxSR, sci_in(sh_sci, SCxSR)
~SCxSR_TEND(sh_sci));
}
-void serial_putc(const char c)
+static void sh_serial_putc(const char c)
{
if (c == '\n')
serial_raw_putc('\r');
serial_raw_putc(c);
}
-void serial_puts(const char *s)
+static void sh_serial_puts(const char *s)
{
char c;
while ((c = *s++) != 0)
serial_putc(c);
}
-int serial_tstc(void)
+static int sh_serial_tstc(void)
{
return serial_rx_fifo_level() ? 1 : 0;
}
@@ -167,7 +167,7 @@ int serial_getc_check(void)
return status (SCIF_DR | SCxSR_RDxF(sh_sci));
}
-int serial_getc(void)
+static int sh_serial_getc(void)
{
unsigned short status;
char ch;
@@ -187,3 +187,56 @@ int serial_getc(void)
handle_error();
return ch;
}
+
+#ifdef CONFIG_SERIAL_MULTI
+static struct serial_device sh_serial_drv = {
+ .name = sh_serial,
+ .start = sh_serial_init,
+ .stop = NULL,
+ .setbrg = sh_serial_setbrg,
+ .putc = sh_serial_putc,
+ .puts = sh_serial_puts,
+ .getc = sh_serial_getc,
+ .tstc = sh_serial_tstc,
+};
+
+void sh_serial_initialize(void)
+{
+ serial_register(sh_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return sh_serial_drv;
+}
+#else
+int serial_init(void)
+{
+ return sh_serial_init();
+}
+
+void serial_setbrg(void)
+{
+ sh_serial_setbrg();
+}
+
+void serial_putc(const char c)
+{
+ sh_serial_putc(c);
+}
+
+void serial_puts(const char *s)
+{
+ sh_serial_puts(s);
+}
+
+int serial_getc(void)
+{
+ return sh_serial_getc();
+}
+
+int serial_tstc(void)
+{
+ return sh_serial_tstc();
+}
+#endif
--
1.7.10.4
Best regards,
Nobuhiro
--
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Re: [U-Boot] [PATCH] sh: ap_sh4a_4a: Fixed initialization value of DDR memory
Appled, thanks.
Best regards,
NObuhiro
On Thu, Sep 6, 2012 at 9:36 AM, Nobuhiro Iwamatsu
nobuhiro.iwamatsu...@renesas.com wrote:
The wrong value was set as value of column of DDR memory for ap_sh4a_4a.
10 is the right value. This fixed this problem.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/alphaproject/ap_sh4a_4a/lowlevel_init.S |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
index f04b36b..cf9c225 100644
--- a/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
+++ b/board/alphaproject/ap_sh4a_4a/lowlevel_init.S
@@ -330,7 +330,7 @@ init_dbsc3_ctrl_533:
DBKIND_A: .long 0xFE800020
DBKIND_D: .long 0x0005
DBCONF_A: .long 0xFE800024
-DBCONF_D: .long 0x0D020901
+DBCONF_D: .long 0x0D020A01
DBTR0_A: .long 0xFE800040
DBTR0_D_533:.long 0x0004
--
1.7.10.4
--
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Re: [U-Boot] [PATCH] net: sh_eth: Add support R8A7740 of rmobile (arm core)
Hi, Joe.
Could you pick this patch to your repository?
Best regards,
Nobuhiro
On Fri, Aug 3, 2012 at 5:08 PM, Nobuhiro Iwamatsu
nobuhiro.iwamatsu...@renesas.com wrote:
R8A7740 of rmobile has ethernet device, and this is same IP of
sh-ether. This support R8A7740 of rmobile.
Signed-off-by: Hideyuki Sano hideyuki.sano...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c |2 +-
drivers/net/sh_eth.h | 14 --
2 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 09af860..2d9cc32 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -394,7 +394,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
#endif
-#if defined(CONFIG_CPU_SH7734)
+#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
#endif
/* Configure phy */
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 3703c55..61d2df9 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -1,8 +1,8 @@
/*
* sh_eth.h - Driver for Renesas SuperH ethernet controler.
*
- * Copyright (C) 2008, 2011 Renesas Solutions Corp.
- * Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
+ * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz car...@kenati.com
*
* This program is free software; you can redistribute it and/or modify
@@ -25,6 +25,7 @@
#define SHETHER_NAME sh_eth
+#if defined(CONFIG_SH)
/* Malloc returns addresses in the P1 area (cacheable). However we need to
use area P2 (non-cacheable) */
#define ADDR_TO_P2(addr) int)(addr) ~0xe000) | 0xa000))
@@ -35,6 +36,12 @@
#else
#define ADDR_TO_PHY(addr) ((int)(addr) ~0xe000)
#endif
+#elif defined(CONFIG_ARM)
+#define inlreadl
+#define outl writel
+#define ADDR_TO_PHY(addr) ((int)(addr))
+#define ADDR_TO_P2(addr) (addr)
+#endif /* defined(CONFIG_SH) */
/* Number of supported ports */
#define MAX_PORT_NUM 2
@@ -292,6 +299,9 @@ static const u16
sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#elif defined(CONFIG_CPU_SH7724)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xA460
+#elif defined(CONFIG_R8A7740)
+#define SH_ETH_TYPE_GETHER
+#define BASE_IO_ADDR 0xE9A0
#endif
/*
--
1.7.10
--
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[U-Boot] [PATCH] spi: Add support SH Queued SPI driver
This patch adds a driver for Renesas SoC's Queued SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe kouei.abe...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/spi/Makefile | 1 +
drivers/spi/sh_qspi.c | 204 ++
drivers/spi/sh_qspi.h | 56 ++
3 files changed, 261 insertions(+)
create mode 100644 drivers/spi/sh_qspi.c
create mode 100644 drivers/spi/sh_qspi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 019132e..f71c089 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 000..82bb49f
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,204 @@
+/*
+ * drivers/spi/sh_qspi.c
+ * SH QSPI driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include sh_qspi.h
+
+static void sh_qspi_writeb(unsigned char data, unsigned char *reg)
+{
+ writeb(data, reg);
+}
+
+static void sh_qspi_writew(unsigned short data, unsigned short *reg)
+{
+ writew(data, reg);
+}
+
+static void sh_qspi_writel(unsigned long data, unsigned long *reg)
+{
+ writel(data, reg);
+}
+
+static unsigned char sh_qspi_readb(unsigned char *reg)
+{
+ return readb(reg);
+}
+
+static unsigned short sh_qspi_readw(unsigned short *reg)
+{
+ return readw(reg);
+}
+
+void spi_init(void)
+{
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sh_qspi *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = spi_alloc_slave(struct sh_qspi, bus, cs);
+ if (!ss)
+ return NULL;
+
+ ss-regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
+
+ /* QSPI initialize */
+ sh_qspi_writeb(0x08, ss-regs-spcr);
+ sh_qspi_writeb(0x00, ss-regs-sslp);
+ sh_qspi_writeb(0x06, ss-regs-sppcr);
+ sh_qspi_writeb(0x01, ss-regs-spbr);
+ sh_qspi_writeb(0x00, ss-regs-spdcr);
+ sh_qspi_writeb(0x00, ss-regs-spckd);
+ sh_qspi_writeb(0x00, ss-regs-sslnd);
+ sh_qspi_writeb(0x00, ss-regs-spnd);
+ sh_qspi_writew(0xe084, ss-regs-spcmd0);
+ sh_qspi_writew(0x8084, ss-regs-spcmd0);
+ sh_qspi_writeb(0xc0, ss-regs-spbfcr);
+ sh_qspi_writeb(0x00, ss-regs-spbfcr);
+ sh_qspi_writeb(0x00, ss-regs-spscr);
+ sh_qspi_writeb(0x48, ss-regs-spcr);
+
+ return ss-slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct sh_qspi *spi = to_sh_qspi(slave);
+
+ free(spi);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+static int sh_qspi_xfer(struct sh_qspi *ss, unsigned char *tdata,
+ unsigned char *rdata, unsigned long flags)
+{
+ while (!(sh_qspi_readb(ss-regs-spsr) SH_QSPI_SPTEF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+
+ sh_qspi_writeb(*tdata, (unsigned char *)(ss-regs-spdr));
+
+ while ((sh_qspi_readw(ss-regs-spbdcr) != 0x01)) {
+ int i = 100;
+
+ if (ctrlc())
+ return 1;
+ while (i--)
+ ;
+ }
+
+ while (!(sh_qspi_readb(ss-regs-spsr) SH_QSPI_SPRFF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+
+ *rdata = sh_qspi_readb((unsigned char *)(ss-regs-spdr));
+
+ return 0;
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+void *din, unsigned long flags)
+{
+ struct sh_qspi *ss = to_sh_qspi(slave);
+ unsigned int nbyte;
+ int ret = 0;
+ unsigned char *tdata, *rdata, dtdata = 0, drdata;
+
+ if (dout == NULL din == NULL) {
+ if (flags SPI_XFER_END)
+ sh_qspi_writeb(0x08, ss-regs-spcr);
+ return 0;
+ }
+
+ if (bitlen % 8) {
+ printf(spi_xfer: bitlen is not 8bit alined %d, bitlen);
+ return 1;
+ }
+
+ nbyte = bitlen / 8;
+
+ if (flags SPI_XFER_BEGIN) {
+ sh_qspi_writeb(0x08, ss-regs-spcr);
+
+ sh_qspi_writew(0xe084, ss-regs-spcmd0
[U-Boot] [PATCH] sf: spansion: Add support for S25FL512S_256K
Add support for Spansion S25FL512S_256K SPI flash.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/mtd/spi/spansion.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 47a4897..a7dc096 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -1,4 +1,5 @@
/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* Author: Mingkai Hu (mingkai...@freescale.com)
@@ -101,6 +102,13 @@ static const struct spansion_spi_flash_params
spansion_spi_flash_table[] = {
.nr_sectors = 1024,
.name = S25FL512S_64K,
},
+ {
+ .idcode1 = 0x0220,
+ .idcode2 = 0x4d00,
+ .pages_per_sector = 1024,
+ .nr_sectors = 256,
+ .name = S25FL512S_256K,
+ },
};
struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode)
--
1.8.3.2
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Re: [U-Boot] [PATCH] sf: spansion: Add support for S25FL512S_256K
Hi,
Thank you for your review.
2013/7/31 Michal Simek mon...@monstr.eu:
On 07/31/2013 09:43 AM, Nobuhiro Iwamatsu wrote:
Add support for Spansion S25FL512S_256K SPI flash.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/mtd/spi/spansion.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/mtd/spi/spansion.c b/drivers/mtd/spi/spansion.c
index 47a4897..a7dc096 100644
--- a/drivers/mtd/spi/spansion.c
+++ b/drivers/mtd/spi/spansion.c
@@ -1,4 +1,5 @@
/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
I don't think that this is huge contribution that you should also update
header.
Hm, OK. I remove this line.
* Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* Author: Mingkai Hu (mingkai...@freescale.com)
@@ -101,6 +102,13 @@ static const struct spansion_spi_flash_params
spansion_spi_flash_table[] = {
.nr_sectors = 1024,
.name = S25FL512S_64K,
},
+ {
+ .idcode1 = 0x0220,
+ .idcode2 = 0x4d00,
+ .pages_per_sector = 1024,
+ .nr_sectors = 256,
+ .name = S25FL512S_256K,
+ },
Jagan sent very similar patch
http://lists.denx.de/pipermail/u-boot/2013-May/155501.html
but nr_sectors and pages_per_sector are swapped.
I did not notice this patch, thanks.
I wait patch of Jagan to be merged.
Best regards,
Nobuhiro
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP - KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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--
Nobuhiro Iwamatsu
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[U-Boot] [PATCH v2] spi: Add support SH Queued SPI driver
This patch adds a driver for Renesas SoC's Queued SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe kouei.abe...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
v2: Change SH QSPI to SH QSPI (Queued SPI).
Remove magic number.
drivers/spi/Makefile | 1 +
drivers/spi/sh_qspi.c | 232 ++
drivers/spi/sh_qspi.h | 52 +++
3 files changed, 285 insertions(+)
create mode 100644 drivers/spi/sh_qspi.c
create mode 100644 drivers/spi/sh_qspi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 019132e..f71c089 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 000..25ce60a
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,232 @@
+/*
+ * drivers/spi/sh_qspi.c
+ * SH QSPI (Queued SPI) driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include sh_qspi.h
+
+static void sh_qspi_writeb(unsigned char data, unsigned char *reg)
+{
+ writeb(data, reg);
+}
+
+static void sh_qspi_writew(unsigned short data, unsigned short *reg)
+{
+ writew(data, reg);
+}
+
+static void sh_qspi_writel(unsigned long data, unsigned long *reg)
+{
+ writel(data, reg);
+}
+
+static unsigned char sh_qspi_readb(unsigned char *reg)
+{
+ return readb(reg);
+}
+
+static unsigned short sh_qspi_readw(unsigned short *reg)
+{
+ return readw(reg);
+}
+
+void spi_init(void)
+{
+}
+
+/* SPCR */
+#define SPCR_MSTR 0x08
+#define SPCR_SPE 0x40
+/* SPSR */
+#define SPSR_SPRFF 0x80
+#define SPSR_SPTEF 0x20
+/* SPPCR */
+#define SPPCR_IO3FV 0x04
+#define SPPCR_IO2FV 0x02
+#define SPPCR_IO1FV 0x01
+/* SPBDCR */
+#define SPBDCR_RXBC0 (1 0)
+/* SPCMD */
+#define SPCMD_SCKDEN (1 15)
+#define SPCMD_SLNDEN (1 14)
+#define SPCMD_SPNDEN (1 13)
+#define SPCMD_SSLKP (1 7)
+#define SPCMD_BRDV0 (1 2)
+#define SPCMD_INIT1 \
+ (SPCMD_SCKDEN|SPCMD_SLNDEN|SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+#define SPCMD_INIT2 (SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+/* SPBFCR */
+#define SPBFCR_TXRST (1 7)
+#define SPBFCR_RXRST (1 6)
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sh_qspi *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = spi_alloc_slave(struct sh_qspi, bus, cs);
+ if (!ss)
+ return NULL;
+
+ ss-regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
+
+ /* QSPI initialize */
+ sh_qspi_writeb(SPCR_MSTR, ss-regs-spcr);
+ sh_qspi_writeb(0x00, ss-regs-sslp);
+ sh_qspi_writeb(SPPCR_IO3FV|SPPCR_IO2FV, ss-regs-sppcr);
+
+ /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
+ sh_qspi_writeb(0x01, ss-regs-spbr);
+
+ sh_qspi_writeb(0x00, ss-regs-spdcr);
+ sh_qspi_writeb(0x00, ss-regs-spckd);
+ sh_qspi_writeb(0x00, ss-regs-sslnd);
+ sh_qspi_writeb(0x00, ss-regs-spnd);
+ sh_qspi_writew(SPCMD_INIT1, ss-regs-spcmd0);
+ sh_qspi_writew(SPCMD_INIT2, ss-regs-spcmd0);
+ sh_qspi_writeb(SPBFCR_TXRST|SPBFCR_RXRST, ss-regs-spbfcr);
+ sh_qspi_writeb(0x00, ss-regs-spbfcr);
+ sh_qspi_writeb(0x00, ss-regs-spscr);
+ sh_qspi_writeb(SPCR_SPE|SPCR_MSTR, ss-regs-spcr);
+
+ return ss-slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ struct sh_qspi *spi = to_sh_qspi(slave);
+
+ free(spi);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+static int sh_qspi_xfer(struct sh_qspi *ss, unsigned char *tdata,
+ unsigned char *rdata, unsigned long flags)
+{
+ while (!(sh_qspi_readb(ss-regs-spsr) SPSR_SPTEF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+
+ sh_qspi_writeb(*tdata, (unsigned char *)(ss-regs-spdr));
+
+ while ((sh_qspi_readw(ss-regs-spbdcr) != SPBDCR_RXBC0)) {
+ int i = 100;
+
+ if (ctrlc())
+ return 1;
+ while (i--)
+ ;
+ }
+
+ while (!(sh_qspi_readb(ss-regs-spsr) SPSR_SPRFF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10
Re: [U-Boot] [PATCH v2] spi: Add support SH Queued SPI driver
Hi,
Thanks for your comment.
2013/8/9 Jagan Teki jagannadh.t...@gmail.com:
Hi,
On 08-08-2013 15:02, Nobuhiro Iwamatsu wrote:
This patch adds a driver for Renesas SoC's Queued SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe kouei.abe...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
v2: Change SH QSPI to SH QSPI (Queued SPI).
Remove magic number.
drivers/spi/Makefile | 1 +
drivers/spi/sh_qspi.c | 232
++
drivers/spi/sh_qspi.h | 52 +++
Please move the structure decelerations on to sh_qspi.c
OK. I will move to .c .
FYI: I am trying to prepare the spi driver code to more readable
header file inclusion
Register bit masks
MISC macro definitions
controller reg structure
controller private slave structure
inline func defination
spi_xfer_sub()
spi_setup_slave_sub
spi_cs_is_valid
spi_cs_activate
spi_cs_deactivate
spi_init
spi_setup_slave
{
spi_setup_slave_sub()
}
spi_free_slave
spi_claim_bus
spi_release_bus
spi_xfer code
{
spi_xfer_sub()
}
I am just trying to do the above format atleast from the drivers which are
pushing now onwards.
Please see the reff driver
http://git.denx.de/?p=u-boot/u-boot-spi.git;a=commitdiff;h=1465d055f9d7a81edacf30c9d20a1b51dfcbfa8d
Let me know your views.
3 files changed, 285 insertions(+)
create mode 100644 drivers/spi/sh_qspi.c
create mode 100644 drivers/spi/sh_qspi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 019132e..f71c089 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 000..25ce60a
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,232 @@
+/*
+ * drivers/spi/sh_qspi.c
Not required, i guess.
Removed.
+ * SH QSPI (Queued SPI) driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu
nobuhiro.iwamatsu...@renesas.com
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include sh_qspi.h
+
+static void sh_qspi_writeb(unsigned char data, unsigned char *reg)
+{
+ writeb(data, reg);
+}
+
+static void sh_qspi_writew(unsigned short data, unsigned short *reg)
+{
+ writew(data, reg);
+}
+
+static void sh_qspi_writel(unsigned long data, unsigned long *reg)
+{
+ writel(data, reg);
+}
+
+static unsigned char sh_qspi_readb(unsigned char *reg)
+{
+ return readb(reg);
+}
+
+static unsigned short sh_qspi_readw(unsigned short *reg)
+{
+ return readw(reg);
+}
+
+void spi_init(void)
+{
+}
Can you use read* and write* directly instead of sh_qspi_write*
sh_qspi_read*
Do you have any specific reason for using these?
No reason. I will change to use read* and write*.
+
+/* SPCR */
+#define SPCR_MSTR 0x08
+#define SPCR_SPE 0x40
+/* SPSR */
+#define SPSR_SPRFF 0x80
+#define SPSR_SPTEF 0x20
+/* SPPCR */
+#define SPPCR_IO3FV 0x04
+#define SPPCR_IO2FV 0x02
+#define SPPCR_IO1FV 0x01
+/* SPBDCR */
+#define SPBDCR_RXBC0 (1 0)
+/* SPCMD */
+#define SPCMD_SCKDEN (1 15)
+#define SPCMD_SLNDEN (1 14)
+#define SPCMD_SPNDEN (1 13)
+#define SPCMD_SSLKP (1 7)
+#define SPCMD_BRDV0 (1 2)
+#define SPCMD_INIT1 \
+ (SPCMD_SCKDEN|SPCMD_SLNDEN|SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+#define SPCMD_INIT2 (SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+/* SPBFCR */
+#define SPBFCR_TXRST (1 7)
+#define SPBFCR_RXRST (1 6)
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sh_qspi *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = spi_alloc_slave(struct sh_qspi, bus, cs);
+ if (!ss)
+ return NULL;
+
+ ss-regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
+
+ /* QSPI initialize */
+ sh_qspi_writeb(SPCR_MSTR, ss-regs-spcr);
+ sh_qspi_writeb(0x00, ss-regs-sslp);
+ sh_qspi_writeb(SPPCR_IO3FV|SPPCR_IO2FV, ss-regs-sppcr);
+
+ /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
+ sh_qspi_writeb(0x01, ss-regs-spbr);
+
+ sh_qspi_writeb(0x00, ss-regs-spdcr);
+ sh_qspi_writeb(0x00, ss-regs-spckd);
+ sh_qspi_writeb(0x00, ss-regs-sslnd);
+ sh_qspi_writeb(0x00, ss-regs-spnd
[U-Boot] [PATCH v3] spi: Add support SH Quad SPI driver
This patch adds a driver for Renesas SoC's Quad SPI bus.
This supports with 8 bits per transfer to use with SPI flash.
Signed-off-by: Kouei Abe kouei.abe...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
v3: Change Queued to Quad.
Remove path of file from file header.
Use read* and write* directly instead of sh_qspi_write* sh_qspi_read*.
Change driver format.
v2: Change SH QSPI to SH QSPI (Queued SPI).
Remove magic number.
drivers/spi/Makefile | 1 +
drivers/spi/sh_qspi.c | 248 ++
2 files changed, 249 insertions(+)
create mode 100644 drivers/spi/sh_qspi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 91d24ce..c44f851 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o
COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o
COBJS-$(CONFIG_SH_SPI) += sh_spi.o
+COBJS-$(CONFIG_SH_QSPI) += sh_qspi.o
COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o
COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o
COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
new file mode 100644
index 000..2efaea8
--- /dev/null
+++ b/drivers/spi/sh_qspi.c
@@ -0,0 +1,248 @@
+/*
+ * SH QSPI (Quad SPI) driver
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+
+/* SPCR */
+#define SPCR_MSTR 0x08
+#define SPCR_SPE 0x40
+
+/* SPSR */
+#define SPSR_SPRFF 0x80
+#define SPSR_SPTEF 0x20
+
+/* SPPCR */
+#define SPPCR_IO3FV 0x04
+#define SPPCR_IO2FV 0x02
+#define SPPCR_IO1FV 0x01
+
+/* SPBDCR */
+#define SPBDCR_RXBC0 (1 0)
+
+/* SPCMD */
+#define SPCMD_SCKDEN (1 15)
+#define SPCMD_SLNDEN (1 14)
+#define SPCMD_SPNDEN (1 13)
+#define SPCMD_SSLKP (1 7)
+#define SPCMD_BRDV0 (1 2)
+#define SPCMD_INIT1 \
+ (SPCMD_SCKDEN|SPCMD_SLNDEN|SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+#define SPCMD_INIT2 (SPCMD_SPNDEN|SPCMD_SSLKP|SPCMD_BRDV0)
+
+/* SPBFCR */
+#define SPBFCR_TXRST (1 7)
+#define SPBFCR_RXRST (1 6)
+
+/* SH QSPI register set */
+struct sh_qspi_regs {
+ unsigned char spcr;
+ unsigned char sslp;
+ unsigned char sppcr;
+ unsigned char spsr;
+ unsigned long spdr;
+ unsigned char spscr;
+ unsigned char spssr;
+ unsigned char spbr;
+ unsigned char spdcr;
+ unsigned char spckd;
+ unsigned char sslnd;
+ unsigned char spnd;
+ unsigned char dummy0;
+ unsigned short spcmd0;
+ unsigned short spcmd1;
+ unsigned short spcmd2;
+ unsigned short spcmd3;
+ unsigned char spbfcr;
+ unsigned char dummy1;
+ unsigned short spbdcr;
+ unsigned long spbmul0;
+ unsigned long spbmul1;
+ unsigned long spbmul2;
+ unsigned long spbmul3;
+};
+
+struct sh_qspi {
+ struct spi_slaveslave;
+ struct sh_qspi_regs *regs;
+};
+
+static inline struct sh_qspi *to_sh_qspi(struct spi_slave *slave)
+{
+ return container_of(slave, struct sh_qspi, slave);
+}
+
+static int sh_qspi_xfer(struct sh_qspi *ss, unsigned char *tdata,
+ unsigned char *rdata, unsigned long flags)
+{
+ while (!(readb(ss-regs-spsr) SPSR_SPTEF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+
+ writeb(*tdata, (unsigned char *)(ss-regs-spdr));
+
+ while ((readw(ss-regs-spbdcr) != SPBDCR_RXBC0)) {
+ int i = 100;
+
+ if (ctrlc())
+ return 1;
+ while (i--)
+ ;
+ }
+
+ while (!(readb(ss-regs-spsr) SPSR_SPRFF)) {
+ if (ctrlc())
+ return 1;
+ udelay(10);
+ }
+
+ *rdata = readb((unsigned char *)(ss-regs-spdr));
+
+ return 0;
+}
+
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return 1;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+}
+
+void spi_init(void)
+{
+ /* nothing to do */
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct sh_qspi *ss;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ ss = spi_alloc_slave(struct sh_qspi, bus, cs);
+ if (!ss)
+ return NULL;
+
+ ss-regs = (struct sh_qspi_regs *)CONFIG_SH_QSPI_BASE;
+
+ /* QSPI initialize */
+ writeb(SPCR_MSTR, ss-regs-spcr);
+ writeb(0x00, ss-regs-sslp);
+ writeb(SPPCR_IO3FV|SPPCR_IO2FV, ss-regs-sppcr);
+
+ /* Set bit rate. See 58.3.8 Quad Serial Peripheral Interface */
+ writeb(0x01, ss-regs
[U-Boot] [PATCH 6/6] sh: boards: Change clock definition of SCIF and TMU
This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to CONFIG_SH_TMU_CLK_FREQ for boards. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- include/configs/MigoR.h | 2 ++ include/configs/ap325rxa.h | 2 ++ include/configs/ap_sh4a_4a.h | 2 ++ include/configs/ecovec.h | 2 ++ include/configs/espt.h | 2 ++ include/configs/mpr2.h | 2 ++ include/configs/ms7720se.h | 2 ++ include/configs/ms7722se.h | 2 ++ include/configs/ms7750se.h | 2 ++ include/configs/r0p7734.h| 2 ++ include/configs/r2dplus.h| 2 ++ include/configs/r7780mp.h| 2 ++ include/configs/rsk7203.h| 2 ++ include/configs/rsk7264.h| 2 ++ include/configs/rsk7269.h| 2 ++ include/configs/sh7752evb.h | 2 ++ include/configs/sh7757lcr.h | 2 ++ include/configs/sh7763rdp.h | 2 ++ include/configs/sh7785lcr.h | 2 ++ include/configs/shmin.h | 2 ++ 20 files changed, 40 insertions(+) diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index dc4a768..d536ebd 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -123,6 +123,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index af3a427..07ec8a7 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -155,6 +155,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ap_sh4a_4a.h b/include/configs/ap_sh4a_4a.h index b911291..ada42d7 100644 --- a/include/configs/ap_sh4a_4a.h +++ b/include/configs/ap_sh4a_4a.h @@ -158,6 +158,8 @@ #else #define CONFIG_SYS_CLK_FREQ #endif +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h index 2c9594b..34bd0b3 100644 --- a/include/configs/ecovec.h +++ b/include/configs/ecovec.h @@ -179,6 +179,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ 4166 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/espt.h b/include/configs/espt.h index e906efb..f1a44bc 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -98,6 +98,8 @@ /* Clock */ #define CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index 7e18723..b0b23a6 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -67,6 +67,8 @@ /* Clocks */ #define CONFIG_SYS_CLK_FREQ2400 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index bc8bb8d..d6b1762 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -85,6 +85,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 /* 4 (default), 16, 64, 256 or 1024 */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index a757737..787c255 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -111,6 +111,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index c4c96bf..37ef02e 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -82,6 +82,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define
[U-Boot] [PATCH 2/6] sh: timer: Remove static global variable
static u16 bit is not necessary to use this as static global variable.
This patch fixes this.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/sh/lib/time.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index 8f83d46..c554fe8 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -21,13 +21,13 @@
static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
-static u16 bit;
static unsigned long last_tcnt;
static unsigned long long overflow_ticks;
unsigned long get_tbclk(void)
{
- return get_tmu0_clk_rate() ((bit + 1) * 2);
+ u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) 1) - 1;
+ return get_tmu0_clk_rate() ((tmu_bit + 1) * 2);
}
static inline unsigned long long tick_to_time(unsigned long long tick)
@@ -62,8 +62,8 @@ static void tmu_timer_stop(unsigned int timer)
int timer_init(void)
{
- bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) 1) - 1;
- writew((readw(tmu-tcr0) ~TCR_TPSC) | bit, tmu-tcr0);
+ u16 tmu_bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) 1) - 1;
+ writew((readw(tmu-tcr0) ~TCR_TPSC) | tmu_bit, tmu-tcr0);
tmu_timer_stop(0);
tmu_timer_start(0);
--
1.8.3.2
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[U-Boot] [PATCH 5/6] serial: sh: Change The definition of clock of SCIF
The former SH/SCIF driver had calculated baudrate based on CONFIG_SYS_CLK_FREQ.
The newest SH/SCIF needs calculation of the clock for SCIF.
This patch defines clock CONFIG_SH_SCIF_CLK_FREQ for SCIF and changes it to
CONFIG_SH_SCIF_CLK_FREQ from CONFIG_SYS_CLK_FREQ.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/serial/serial_sh.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index ff2cdc5..67cc0dc 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -48,7 +48,9 @@ static struct uart_port sh_sci = {
static void sh_serial_setbrg(void)
{
DECLARE_GLOBAL_DATA_PTR;
- sci_out(sh_sci, SCBRR, SCBRR_VALUE(gd-baudrate, CONFIG_SYS_CLK_FREQ));
+
+ sci_out(sh_sci, SCBRR,
+ SCBRR_VALUE(gd-baudrate, CONFIG_SH_SCIF_CLK_FREQ));
}
static int sh_serial_init(void)
--
1.8.3.2
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[U-Boot] [PATCH 3/6] sh: cache: Change cache API to defines as U-Boot
A chache API of SH is developped by reference in linux kernel.
And API was the same as the linux kernel.
This patch change cache API to defines as U-Boot.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/sh/cpu/sh4/cache.c | 4 ++--
arch/sh/cpu/sh4/cpu.c | 2 +-
arch/sh/include/asm/cache.h | 3 ---
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index 1947ec8..e1ee970 100644
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -91,7 +91,7 @@ int cache_control(unsigned int cmd)
return 0;
}
-void dcache_wback_range(u32 start, u32 end)
+void flush_dcache_range(unsigned long start, unsigned long end)
{
u32 v;
@@ -102,7 +102,7 @@ void dcache_wback_range(u32 start, u32 end)
}
}
-void dcache_invalid_range(u32 start, u32 end)
+void invalidate_dcache_range(unsigned long start, unsigned long end)
{
u32 v;
diff --git a/arch/sh/cpu/sh4/cpu.c b/arch/sh/cpu/sh4/cpu.c
index 9fae614..91133a3 100644
--- a/arch/sh/cpu/sh4/cpu.c
+++ b/arch/sh/cpu/sh4/cpu.c
@@ -41,7 +41,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
void flush_cache (unsigned long addr, unsigned long size)
{
- dcache_invalid_range( addr , addr + size );
+ invalidate_dcache_range(addr , addr + size);
}
void icache_enable (void)
diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h
index 24941b3..b21dc44 100644
--- a/arch/sh/include/asm/cache.h
+++ b/arch/sh/include/asm/cache.h
@@ -10,9 +10,6 @@ int cache_control(unsigned int cmd);
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
-void dcache_wback_range(u32 start, u32 end);
-void dcache_invalid_range(u32 start, u32 end);
-
#else
/*
--
1.8.3.2
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[U-Boot] [PATCH 1/6] sh: timer: Mask bit of timer prescaler
timer_init function sets timer prescaler bit.
The previous code so did not mask this bit, this function was to overwrite
the bit. This will fix this problem.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/sh/lib/time.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c
index 1fe537e..8f83d46 100644
--- a/arch/sh/lib/time.c
+++ b/arch/sh/lib/time.c
@@ -17,6 +17,8 @@
#include asm/io.h
#include sh_tmu.h
+#define TCR_TPSC 0x07
+
static struct tmu_regs *tmu = (struct tmu_regs *)TMU_BASE;
static u16 bit;
@@ -61,7 +63,7 @@ static void tmu_timer_stop(unsigned int timer)
int timer_init(void)
{
bit = (ffs(CONFIG_SYS_TMU_CLK_DIV) 1) - 1;
- writew(readw(tmu-tcr0) | bit, tmu-tcr0);
+ writew((readw(tmu-tcr0) ~TCR_TPSC) | bit, tmu-tcr0);
tmu_timer_stop(0);
tmu_timer_start(0);
--
1.8.3.2
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[U-Boot] [PATCH 4/6] sh: timer: Change The definition of clock of TMU
The former SH/TMU driver had calculated timer based on CONFIG_SYS_CLK_FREQ.
The newest SH/TMU newly needs calculation of the clock for TMU.
This patch defines clock CONFIG_SH_TMU_CLK_FREQ for TMU and changes it to
CONFIG_SH_TMU_CLK_FREQ from CONFIG_SYS_CLK_FREQ.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
include/sh_tmu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/sh_tmu.h b/include/sh_tmu.h
index 96c589d..f5b42fa 100644
--- a/include/sh_tmu.h
+++ b/include/sh_tmu.h
@@ -69,7 +69,7 @@ struct tmu_regs {
static inline unsigned long get_tmu0_clk_rate(void)
{
- return CONFIG_SYS_CLK_FREQ;
+ return CONFIG_SH_TMU_CLK_FREQ;
}
#endif /* __SH_TMU_H */
--
1.8.3.2
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[U-Boot] [PATCH 1/2] arm: rmobile: kzm9g: Change clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- include/configs/kzm9g.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 222725c..6323050 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -125,6 +125,7 @@ #define CONFIG_GLOBAL_TIMER #define CONFIG_SYS_CLK_FREQ(4800) #define CONFIG_SYS_CPU_CLK (119600) +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define TMU_CLK_DIVIDER(4) /* 4 (default), 16, 64, 256 or 1024 */ #define CFG_HZ (1000) #define CONFIG_SYS_HZ CFG_HZ -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] arm: rmobile: armadillo-800eva: Change clock definition of SCIF and TMU
This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to CONFIG_SH_TMU_CLK_FREQ, Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- include/configs/armadillo-800eva.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 9f357ea..7a264b0 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -138,6 +138,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ5000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 #define CONFIG_SYS_HZ 1000 -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] net: sh-eth: Add control for padding size of packet descriptor
sh-eth can change the alignment size of a packet descriptor according to BUS
size. This patch adds this function.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 13 -
drivers/net/sh_eth.h | 27 ++-
2 files changed, 30 insertions(+), 10 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 4cfd1e5..c038929 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -238,15 +238,17 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
* Allocate rx data buffers. They must be 32 bytes aligned and in
* P2 area
*/
- port_info-rx_buf_malloc = malloc(NUM_RX_DESC * MAX_BUF_SIZE + 31);
+ port_info-rx_buf_malloc = malloc(
+ NUM_RX_DESC * MAX_BUF_SIZE + RX_BUF_ALIGNE_SIZE - 1);
if (!port_info-rx_buf_malloc) {
printf(SHETHER_NAME : malloc failed\n);
ret = -ENOMEM;
goto err_buf_malloc;
}
- tmp_addr = (u32)(((int)port_info-rx_buf_malloc + (32 - 1))
- ~(32 - 1));
+ tmp_addr = (u32)(((int)port_info-rx_buf_malloc
+ + (RX_BUF_ALIGNE_SIZE - 1))
+ ~(RX_BUF_ALIGNE_SIZE - 1));
port_info-rx_buf_base = (u8 *)ADDR_TO_P2(tmp_addr);
/* Initialize all descriptors */
@@ -352,8 +354,9 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
struct phy_device *phy;
/* Configure e-dmac registers */
- sh_eth_write(eth, (sh_eth_read(eth, EDMR) ~EMDR_DESC_R) | EDMR_EL,
-EDMR);
+ sh_eth_write(eth, (sh_eth_read(eth, EDMR) ~EMDR_DESC_R) |
+ (EMDR_DESC | EDMR_EL), EDMR);
+
sh_eth_write(eth, 0, EESIPR);
sh_eth_write(eth, 0, TRSCER);
sh_eth_write(eth, 0, TFTR);
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 9ad800e..35a1eee 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -31,6 +31,11 @@
#define ADDR_TO_P2(addr) (addr)
#endif /* defined(CONFIG_SH) */
+/* base padding size is 16 */
+#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#endif
+
/* Number of supported ports */
#define MAX_PORT_NUM 2
@@ -45,15 +50,16 @@
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING4
-#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
+#define TX_DESC_PADDING(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
+#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
volatile u32 td0;
u32 td1;
u32 td2;/* Buffer start */
- u32 padding;
+ u8 padding[TX_DESC_PADDING];/* aligned cache line size */
};
/* There is no limitation in the number of rx descriptors */
@@ -61,15 +67,18 @@ struct tx_desc_s {
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING4
+#define RX_DESC_PADDING(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
+/* aligned cache line size */
+#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE 32 ? 64 : 32)
/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
volatile u32 rd0;
volatile u32 rd1;
u32 rd2;/* Buffer start */
- u32 padding;
+ u8 padding[TX_DESC_PADDING];/* aligned cache line size */
};
struct sh_eth_info {
@@ -320,6 +329,14 @@ enum DMAC_M_BIT {
#endif
};
+#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+# define EMDR_DESC EDMR_DL1
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+# define EMDR_DESC EDMR_DL0
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+# define EMDR_DESC 0
+#endif
+
/* RFLR */
#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
--
1.8.3.2
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[U-Boot] [PATCH 4/4] net: sh-eth: Add support R8A7790
R8A7790 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7790.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 5 -
drivers/net/sh_eth.h | 7 +++
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index b7dc625..b936808 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -4,6 +4,7 @@
* Copyright (C) 2008, 2011 Renesas Solutions Corp.
* Copyright (c) 2008, 2011 Nobuhiro Iwamatsu
* Copyright (c) 2007 Carlos Munoz car...@kenati.com
+ * Copyright (C) 2013 Renesas Electronics Corporation
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -409,6 +410,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
+#elif defined(CONFIG_R8A7790)
+ sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
ret = sh_eth_phy_config(eth);
@@ -432,7 +435,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724)
+#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790)
val = ECMR_RTM;
#endif
} else if (phy-speed == 10) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 35a1eee..43b8ac9 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -166,6 +166,7 @@ enum {
TLFRCR,
CERCR,
CEECR,
+ RMIIMR, /* R8A7790 */
MAFCR,
RTRATE,
CSMR,
@@ -272,6 +273,7 @@ static const u16
sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMCR] = 0x0058,
[TFUCR] = 0x0064,
[RFOCR] = 0x0068,
+ [RMIIMR] = 0x006C,
[FCFTR] = 0x0070,
[RPADIR]= 0x0078,
[TRIMD] = 0x007c,
@@ -299,6 +301,9 @@ static const u16
sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A0
+#elif defined(CONFIG_R8A7790)
+#define SH_ETH_TYPE_ETHER
+#define BASE_IO_ADDR 0xEE700200
#endif
/*
@@ -502,6 +507,8 @@ enum FELIC_MODE_BIT {
ECMR_PRM = 0x0001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x0010,
+#elif defined(CONFIG_R8A7790)
+ ECMR_RTM = 0x0004,
#endif
};
--
1.8.3.2
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[U-Boot] [PATCH 3/4] net: sh-eth: Add invalidate cache control for rmobile (ARM SoC)
The sh-eth of rmobile needs to use invalidate_cache* function.
This patch adds invalidate_cache* function.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/net/sh_eth.c | 31 ++-
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index c038929..b7dc625 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -26,13 +26,30 @@
# error Please define CONFIG_SH_ETHER_PHY_ADDR
#endif
-#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
-#define flush_cache_wback(addr, len) \
- flush_dcache_range((u32)addr, (u32)(addr + len - 1))
+#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) !defined(CONFIG_SYS_DCACHE_OFF)
+#define flush_cache_wback(addr, len)\
+ flush_dcache_range((u32)addr, (u32)(addr + len - 1))
#else
#define flush_cache_wback(...)
#endif
+#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) defined(CONFIG_ARM)
+#define invalidate_cache(addr, len)\
+ { \
+ u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE;\
+ u32 start, end; \
+ \
+ start = (u32)addr; \
+ end = start + len; \
+ start = ~(line_size - 1); \
+ end = ((end + line_size - 1) ~(line_size - 1)); \
+ \
+ invalidate_dcache_range(start, end);\
+ }
+#else
+#define invalidate_cache(...)
+#endif
+
#define TIMEOUT_CNT 1000
int sh_eth_send(struct eth_device *dev, void *packet, int len)
@@ -70,8 +87,11 @@ int sh_eth_send(struct eth_device *dev, void *packet, int
len)
/* Wait until packet is transmitted */
timeout = TIMEOUT_CNT;
- while (port_info-tx_desc_cur-td0 TD_TACT timeout--)
+ do {
+ invalidate_cache(port_info-tx_desc_cur,
+ sizeof(struct tx_desc_s));
udelay(100);
+ } while (port_info-tx_desc_cur-td0 TD_TACT timeout--);
if (timeout 0) {
printf(SHETHER_NAME : transmit timeout\n);
@@ -95,12 +115,14 @@ int sh_eth_recv(struct eth_device *dev)
uchar *packet;
/* Check if the rx descriptor is ready */
+ invalidate_cache(port_info-rx_desc_cur, sizeof(struct rx_desc_s));
if (!(port_info-rx_desc_cur-rd0 RD_RACT)) {
/* Check for errors */
if (!(port_info-rx_desc_cur-rd0 RD_RFE)) {
len = port_info-rx_desc_cur-rd1 0x;
packet = (uchar *)
ADDR_TO_P2(port_info-rx_desc_cur-rd2);
+ invalidate_cache(packet, len);
NetReceive(packet, len);
}
@@ -109,7 +131,6 @@ int sh_eth_recv(struct eth_device *dev)
port_info-rx_desc_cur-rd0 = RD_RACT | RD_RDLE;
else
port_info-rx_desc_cur-rd0 = RD_RACT;
-
/* Point to the next descriptor */
port_info-rx_desc_cur++;
if (port_info-rx_desc_cur =
--
1.8.3.2
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[U-Boot] [PATCH 1/4] net: sh-eth: Change cache API of SH
The cache API of SH was changed from dcache_wback_range to flush_dcache_range. sh-eth uses dcache_wback_range. This patch changes to flush_dcache_range. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- drivers/net/sh_eth.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index d5a83e0..4cfd1e5 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -25,9 +25,10 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error Please define CONFIG_SH_ETHER_PHY_ADDR #endif + #ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK #define flush_cache_wback(addr, len) \ - dcache_wback_range((u32)addr, (u32)(addr + len - 1)) + flush_dcache_range((u32)addr, (u32)(addr + len - 1)) #else #define flush_cache_wback(...) #endif -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] serial: sh: Add support R8A7790
This adds the preset value to register, and setup of baudrate.
Signed-off-by: Kouei Abe kouei.abe...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/serial/serial_sh.c | 1 +
drivers/serial/serial_sh.h | 13 +
2 files changed, 14 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 67cc0dc..0826d59 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -1,5 +1,6 @@
/*
* SuperH SCIF device driver.
+ * Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
* Copyright (C) 2002 - 2008 Paul Mundt
*
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 7e38a3f..a6558af 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -224,6 +224,9 @@ struct uart_port {
# define SCSPTR3 0xffc60020/* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_R8A7790)
+# define SCIF_ORER 0x0001
+# define SCSCR_INIT(port) 0x32/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
# error CPU subtype not defined
#endif
@@ -298,6 +301,9 @@ struct uart_port {
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
+#elif defined(CONFIG_R8A7790)
+# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
+# define SCIF_RFDC_MASK0x003f
#else
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x001f
@@ -579,6 +585,10 @@ SCIF_FNS(SCSPTR,0, 0, 0, 0)
#else
SCIF_FNS(SCSPTR,0, 0, 0x20, 16)
#endif
+#if defined(CONFIG_R8A7790)
+SCIF_FNS(DL, 0, 0, 0x30, 16)
+SCIF_FNS(CKS, 0, 0, 0x34, 16)
+#endif
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
#endif
@@ -720,6 +730,9 @@ static inline int scbrr_calc(struct uart_port port, int
bps, int clk)
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
+#elif defined(CONFIG_R8A7790)
+#define SCBRR DL
+#define SCBRR_VALUE(bps, clk) (clk / bps / 16)
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
--
1.8.3.2
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[U-Boot] [PATCH] arm: omap5: echi: Add GPL-2.0+ SPDX-License-Identifier
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- arch/arm/include/asm/arch-omap5/ehci.h | 15 +-- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h index 3921e4a..63aaa02 100644 --- a/arch/arm/include/asm/arch-omap5/ehci.h +++ b/arch/arm/include/asm/arch-omap5/ehci.h @@ -2,20 +2,7 @@ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com* * Author: Govindraj R govindraj.r...@ti.com * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _EHCI_H -- 1.8.4.rc3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] arm: rmobile: Add support lager board
Hi, Albert. (2013/09/19 18:04), Albert ARIBAUD wrote: Hi Nobuhiro, On Thu, 22 Aug 2013 13:23:28 +0900, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 440b041..67b88ad 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -1106,6 +1106,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP5_SEVM 3777 #define MACH_TYPE_ARMADILLO_800EVA 3863 #define MACH_TYPE_KZM9G4140 +#define MACH_TYPE_LAGER4538 Do not modify mach-types.h; if the machine type was reserved but is not yet in machine-types, then you should define the machine type in the board's header file, possibly with preprocessing directives to #error when the same definition appears in mach-types.h making the board's one obsolete. OK, I will remove this from patch. diff --git a/boards.cfg b/boards.cfg index be810c7..8e38d3c 100644 --- a/boards.cfg +++ b/boards.cfg @@ -341,6 +341,8 @@ u8500_href arm armv7 u8500 st-eric snowball arm armv7 snowball st-ericssonu8500 kzm9garm armv7 kzm9g kmc rmobile armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile +lagerarm armv7 lager renesasrmobile +lager_norarm armv7 lager renesasrmobile lager:NORFLASH Please rebase as boards.cfg has changed, and do add maintainer addresses to these two lines. I see. I will update my patches and re-send. Thank you for your review! Amicalement, Best regards, Nobuhiro ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] arm: rmobile: kzm9g: Change clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ
Hi, Albert. (2013/09/19 18:09), Albert ARIBAUD wrote: Hi Nobuhiro, On Thu, 22 Aug 2013 13:05:49 +0900, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: Signed-off-by: Nobuhiro Iwamatsunobuhiro.iwamatsu...@renesas.com --- include/configs/kzm9g.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h index 222725c..6323050 100644 --- a/include/configs/kzm9g.h +++ b/include/configs/kzm9g.h @@ -125,6 +125,7 @@ #define CONFIG_GLOBAL_TIMER #define CONFIG_SYS_CLK_FREQ (4800) #define CONFIG_SYS_CPU_CLK(119600) +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ #define CFG_HZ (1000) #define CONFIG_SYS_HZ CFG_HZ What's the point of this series? It only adds a define, but the current codebase does not use it anywhere, so obviously it's dead code. This is used by drivers/serial/serial_sh.c. http://lists.denx.de/pipermail/u-boot/2013-August/161276.html I already applied this to my u-boot-sh repository. But I dont pull-request yet. I want to include in the next version of this change. If there is a further series which needs this define, then include these patches in that further series. I see. I will be from next time, Is it OK? Amicalement, Best regards, Nobuhiro ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] serial: sh: Add support R8A7790
This adds the preset value to register, and setup of baudrate.
Signed-off-by: Kouei Abe kouei.abe...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
v2: no changes
drivers/serial/serial_sh.c | 1 +
drivers/serial/serial_sh.h | 13 +
2 files changed, 14 insertions(+)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 67cc0dc..0826d59 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -1,5 +1,6 @@
/*
* SuperH SCIF device driver.
+ * Copyright (C) 2013 Renesas Electronics Corporation
* Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu
* Copyright (C) 2002 - 2008 Paul Mundt
*
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 7e38a3f..a6558af 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -224,6 +224,9 @@ struct uart_port {
# define SCSPTR3 0xffc60020/* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
+#elif defined(CONFIG_R8A7790)
+# define SCIF_ORER 0x0001
+# define SCSCR_INIT(port) 0x32/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
# error CPU subtype not defined
#endif
@@ -298,6 +301,9 @@ struct uart_port {
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
+#elif defined(CONFIG_R8A7790)
+# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
+# define SCIF_RFDC_MASK0x003f
#else
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK 0x001f
@@ -579,6 +585,10 @@ SCIF_FNS(SCSPTR,0, 0, 0, 0)
#else
SCIF_FNS(SCSPTR,0, 0, 0x20, 16)
#endif
+#if defined(CONFIG_R8A7790)
+SCIF_FNS(DL, 0, 0, 0x30, 16)
+SCIF_FNS(CKS, 0, 0, 0x34, 16)
+#endif
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
#endif
@@ -720,6 +730,9 @@ static inline int scbrr_calc(struct uart_port port, int
bps, int clk)
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
+#elif defined(CONFIG_R8A7790)
+#define SCBRR DL
+#define SCBRR_VALUE(bps, clk) (clk / bps / 16)
#else /* Generic SH */
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
#endif
--
1.8.4.rc3
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Re: [U-Boot] [UBOOT][PATCHv3 5/7] spi: add TI QSPI driver
Hi, 2013/9/18 Sourav Poddar sourav.pod...@ti.com: From: Matt Porter matt.por...@linaro.org Adds a SPI master driver for the TI QSPI peripheral. Signed-off-by: Matt Porter matt.por...@linaro.org Signed-off-by: Sourav Poddar sourav.pod...@ti.com [Added quad read support and memory mapped support). --- drivers/spi/Makefile |1 + drivers/spi/ti_qspi.c | 324 + 2 files changed, 325 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/ti_qspi.c diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 91d24ce..e5941b0 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_FDT_SPI) += fdt_spi.o COBJS-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o COBJS-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o COBJS-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o +COBJS-$(CONFIG_TI_QSPI) += ti_qspi.o COBJS-$(CONFIG_XILINX_SPI) += xilinx_spi.o COBJS-$(CONFIG_ZYNQ_SPI) += zynq_spi.o diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c new file mode 100644 index 000..3e88cf4 --- /dev/null +++ b/drivers/spi/ti_qspi.c @@ -0,0 +1,324 @@ +/* + * TI QSPI driver + * + * Copyright (C) 2013, Texas Instruments, Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + */ Could you change to 'SPDX-License-Identifier:GPL-2.0+', please? Best regards, Nobuhiro -- Nobuhiro Iwamatsu ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/4] arm: rmobile: Add support Koelsch board
The koelsch board has R8A7791, 2GB DDR3-SDRAM, USB,
Quad SPI, Ethernet, and more.
This patch supports the following functions:
- DDR3-SDRAM
- SCIF
- Quad SPI
- Ether
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
CC: Nobuhiro Iwamatsu iwama...@nigauri.org
CC: Albert Aribaud albert.u.b...@aribaud.net
---
board/renesas/koelsch/Makefile | 34
board/renesas/koelsch/koelsch.c | 360
board/renesas/koelsch/qos.c | 148 +
board/renesas/koelsch/qos.h | 12 ++
boards.cfg | 2 +
include/configs/koelsch.h | 182
6 files changed, 738 insertions(+)
create mode 100644 board/renesas/koelsch/Makefile
create mode 100644 board/renesas/koelsch/koelsch.c
create mode 100644 board/renesas/koelsch/qos.c
create mode 100644 board/renesas/koelsch/qos.h
create mode 100644 include/configs/koelsch.h
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
new file mode 100644
index 000..e0efbc4
--- /dev/null
+++ b/board/renesas/koelsch/Makefile
@@ -0,0 +1,34 @@
+#
+# board/renesas/koelsch/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+include$(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := koelsch.o qos.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
new file mode 100644
index 000..73cad66
--- /dev/null
+++ b/board/renesas/koelsch/koelsch.c
@@ -0,0 +1,360 @@
+/*
+ * board/renesas/koelsch/koelsch.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include common.h
+#include malloc.h
+#include asm/processor.h
+#include asm/mach-types.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/arch/sys_proto.h
+#include asm/gpio.h
+#include asm/arch/rmobile.h
+#include netdev.h
+#include miiphy.h
+#include i2c.h
+#include qos.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+ ({ \
+ u32 i = 0x1 * cnt; \
+ while (i 0) \
+ i--;\
+ })
+
+
+#define dbpdrgd_check(bsc) \
+ ({ \
+ while ((readl(bsc-dbpdrgd) 0x1) != 0x1) \
+ ; \
+ })
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+ struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
+ struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
+
+ /* LBSC */
+ writel(0x0020, lbsc-cs0ctrl);
+ writel(0x0020, lbsc-cs1ctrl);
+ writel(0x2020, lbsc-ecs0ctrl);
+ writel(0x2020, lbsc-ecs1ctrl);
+
+ writel(0x077F077F, lbsc-cswcr0);
+ writel(0x077F077F, lbsc-cswcr1);
+ writel(0x077F077F, lbsc-ecswcr0);
+ writel(0x077F077F, lbsc-ecswcr1);
+
+ /* DBSC3 */
+ s_init_wait(10);
+
+ writel(0xA55A, dbsc3_0-dbpdlck);
+ writel(0x0001, dbsc3_0-dbpdrga);
+ writel(0x8000, dbsc3_0-dbpdrgd);
+ writel(0x0004, dbsc3_0-dbpdrga);
+ dbpdrgd_check(dbsc3_0);
+
+ writel(0x0006, dbsc3_0-dbpdrga);
+ writel(0x0001C000, dbsc3_0-dbpdrgd);
+
+ writel(0x0023, dbsc3_0-dbpdrga);
+ writel(0x00FD2480, dbsc3_0-dbpdrgd);
+
+ writel(0x0010, dbsc3_0-dbpdrga);
+ writel(0xF004649B, dbsc3_0-dbpdrgd);
+
+ writel(0x000F, dbsc3_0-dbpdrga);
+ writel(0x00181EE4, dbsc3_0-dbpdrgd);
+
+ writel(0x000E, dbsc3_0-dbpdrga);
+ writel(0x33C03812, dbsc3_0-dbpdrgd);
+
+ writel(0x0003, dbsc3_0-dbpdrga);
+ writel(0x0300C481, dbsc3_0-dbpdrgd);
+
+ writel(0x0007, dbsc3_0-dbkind);
+ writel(0x10030A02, dbsc3_0-dbconf0);
+ writel(0x0001, dbsc3_0-dbphytype);
+ writel(0x, dbsc3_0-dbbl);
+ writel(0x000B, dbsc3_0-dbtr0);
+ writel(0x0008, dbsc3_0-dbtr1);
+ writel(0x, dbsc3_0-dbtr2);
+ writel(0x000B, dbsc3_0-dbtr3);
+ writel(0x000C000B, dbsc3_0-dbtr4);
+ writel(0x0027, dbsc3_0-dbtr5);
+ writel(0x001C, dbsc3_0-dbtr6);
+ writel(0x0005, dbsc3_0-dbtr7);
+ writel(0x0018, dbsc3_0-dbtr8);
+ writel(0x0008, dbsc3_0-dbtr9);
+ writel(0x000C, dbsc3_0-dbtr10);
+ writel
[U-Boot] [PATCH 1/4] serial: sh: Add support R8A7791
This adds the preset value to register for R8A7791.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
CC: Nobuhiro Iwamatsu iwama...@nigauri.org
---
drivers/serial/serial_sh.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index a6558af..556b868 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -224,7 +224,7 @@ struct uart_port {
# define SCSPTR3 0xffc60020/* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* Overrun error bit */
# define SCSCR_INIT(port) 0x38/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_R8A7790)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
# define SCIF_ORER 0x0001
# define SCSCR_INIT(port) 0x32/* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */
#else
@@ -301,7 +301,7 @@ struct uart_port {
/* SH7763 SCIF2 support */
# define SCIF2_RFDC_MASK 0x001f
# define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
# define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
# define SCIF_RFDC_MASK0x003f
#else
@@ -585,7 +585,7 @@ SCIF_FNS(SCSPTR,0, 0, 0, 0)
#else
SCIF_FNS(SCSPTR,0, 0, 0x20, 16)
#endif
-#if defined(CONFIG_R8A7790)
+#if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
SCIF_FNS(DL, 0, 0, 0x30, 16)
SCIF_FNS(CKS, 0, 0, 0x34, 16)
#endif
@@ -730,7 +730,7 @@ static inline int scbrr_calc(struct uart_port port, int
bps, int clk)
#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk)
#elif defined(__H8300H__) || defined(__H8300S__)
#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
#define SCBRR DL
#define SCBRR_VALUE(bps, clk) (clk / bps / 16)
#else /* Generic SH */
--
1.8.4.rc3
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[U-Boot] [PATCH 2/4] net: sh-eth: Add support R8A7791
R8A7791 has the same sh-ether IP core as other SH/rmobile.
This patch adds support of R8A7791.
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
CC: Nobuhiro Iwamatsu iwama...@nigauri.org
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/sh_eth.c | 5 +++--
drivers/net/sh_eth.h | 4 ++--
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index b936808..8c23e30 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -410,7 +410,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
-#elif defined(CONFIG_R8A7790)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR);
#endif
/* Configure phy */
@@ -435,7 +435,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
sh_eth_write(eth, GECMR_100B, GECMR);
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
sh_eth_write(eth, 1, RTRATE);
-#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790)
+#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \
+ defined(CONFIG_R8A7791)
val = ECMR_RTM;
#endif
} else if (phy-speed == 10) {
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 43b8ac9..8aa7109 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -301,7 +301,7 @@ static const u16
sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A0
-#elif defined(CONFIG_R8A7790)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
#endif
@@ -507,7 +507,7 @@ enum FELIC_MODE_BIT {
ECMR_PRM = 0x0001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x0010,
-#elif defined(CONFIG_R8A7790)
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
ECMR_RTM = 0x0004,
#endif
--
1.8.4.rc3
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[U-Boot] [PATCH] i2c: Add support for Renesas rcar
This supports i2c controller for Renesas rcar.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
drivers/i2c/Makefile | 1 +
drivers/i2c/rcar_i2c.c | 289 +
2 files changed, 290 insertions(+)
create mode 100644 drivers/i2c/rcar_i2c.c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 37ccbd1..f7cbd62 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -26,6 +26,7 @@ COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
+COBJS-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
new file mode 100644
index 000..92f0700
--- /dev/null
+++ b/drivers/i2c/rcar_i2c.c
@@ -0,0 +1,289 @@
+/*
+ * drivers/i2c/rcar_i2c.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include common.h
+#include i2c.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rcar_i2c {
+ u32 icscr;
+ u32 icmcr;
+ u32 icssr;
+ u32 icmsr;
+ u32 icsier;
+ u32 icmier;
+ u32 icccr;
+ u32 icsar;
+ u32 icmar;
+ u32 icrxdtxd;
+ u32 icccr2;
+ u32 icmpr;
+ u32 ichpr;
+ u32 iclpr;
+};
+
+#define MCR_MDBS 0x80/* non-fifo mode switch */
+#define MCR_FSCL 0x40/* override SCL pin */
+#define MCR_FSDA 0x20/* override SDA pin */
+#define MCR_OBPC 0x10/* override pins*/
+#define MCR_MIE0x08/* master if enable */
+#define MCR_TSBE 0x04
+#define MCR_FSB0x02/* force stop bit */
+#define MCR_ESG0x01/* en startbit gen. */
+
+#define MSR_MASK 0x7f
+#define MSR_MNR0x40/* nack received*/
+#define MSR_MAL0x20/* arbitration lost */
+#define MSR_MST0x10/* sent a stop */
+#define MSR_MDE0x08
+#define MSR_MDT0x04
+#define MSR_MDR0x02
+#define MSR_MAT0x01/* slave addr xfer done */
+
+static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
+};
+
+static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
+{
+ /* set slave address */
+ writel(chip 1, dev-icmar);
+ /* set register address */
+ writel(addr, dev-icrxdtxd);
+ /* clear status */
+ writel(0, dev-icmsr);
+ /* start master send */
+ writel(MCR_MDBS | MCR_MIE | MCR_ESG, dev-icmcr);
+
+ while ((readl(dev-icmsr) (MSR_MAT | MSR_MDE))
+ != (MSR_MAT | MSR_MDE))
+ udelay(10);
+
+ /* clear ESG */
+ writel(MCR_MDBS | MCR_MIE, dev-icmcr);
+ /* start SCLclk */
+ writel(~(MSR_MAT | MSR_MDE), dev-icmsr);
+
+ while (!(readl(dev-icmsr) MSR_MDE))
+ udelay(10);
+}
+
+static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev)
+{
+ while (!(readl(dev-icmsr) MSR_MST))
+ udelay(10);
+
+ writel(0, dev-icmcr);
+}
+
+static int
+rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size)
+{
+ rcar_i2c_raw_rw_common(dev, chip, addr);
+
+ /* set send date */
+ writel(*val, dev-icrxdtxd);
+ /* start SCLclk */
+ writel(~MSR_MDE, dev-icmsr);
+
+ while (!(readl(dev-icmsr) MSR_MDE))
+ udelay(10);
+
+ /* set stop condition */
+ writel(MCR_MDBS | MCR_MIE | MCR_FSB, dev-icmcr);
+ /* start SCLclk */
+ writel(~MSR_MDE, dev-icmsr);
+
+ rcar_i2c_raw_rw_finish(dev);
+
+ return 0;
+}
+
+static u8
+rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
+{
+ u8 ret;
+
+ rcar_i2c_raw_rw_common(dev, chip, addr);
+
+ /* set slave address, receive */
+ writel((chip 1) | 1, dev-icmar);
+ /* start master receive */
+ writel(MCR_MDBS | MCR_MIE | MCR_ESG, dev-icmcr);
+
+ while ((readl(dev-icmsr) (MSR_MAT | MSR_MDE))
+ != (MSR_MAT | MSR_MDE))
+ udelay(10);
+
+ /* clear ESG */
+ writel(MCR_MDBS | MCR_MIE, dev-icmcr);
+ /* prepare stop condition */
+ writel(MCR_MDBS | MCR_MIE | MCR_FSB, dev-icmcr);
+ /* start SCLclk */
+ writel(~(MSR_MAT | MSR_MDR), dev-icmsr);
+
+ while (!(readl(dev-icmsr
Re: [U-Boot] [PATCH] i2c: Add support for Renesas rcar
Hi, Heiko.
Thank you for your review.
(2013/09/27 12:37), Heiko Schocher wrote:
Hello Nobuhiro,
Am 27.09.2013 01:21, schrieb Nobuhiro Iwamatsu:
This supports i2c controller for Renesas rcar.
Signed-off-by: Hisashi Nakamurahisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsunobuhiro.iwamatsu...@renesas.com
---
drivers/i2c/Makefile | 1 +
drivers/i2c/rcar_i2c.c | 289 +
2 files changed, 290 insertions(+)
create mode 100644 drivers/i2c/rcar_i2c.c
Thanks! Patch looks good to me, just some nitpicking comments:
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 37ccbd1..f7cbd62 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -26,6 +26,7 @@ COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o
COBJS-$(CONFIG_SH_I2C) += sh_i2c.o
COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
+COBJS-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
Please keep this list sorted ...
OK, I will fix.
COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
new file mode 100644
index 000..92f0700
--- /dev/null
+++ b/drivers/i2c/rcar_i2c.c
@@ -0,0 +1,289 @@
[...]
+static u8
+rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr)
+{
+ u8 ret;
+
+ rcar_i2c_raw_rw_common(dev, chip, addr);
+
+ /* set slave address, receive */
+ writel((chip 1) | 1,dev-icmar);
^ ^
space please, please fix globally
Hmm.. checkpatch says for your patch:
total: 0 errors, 0 warnings, 0 checks, 296 lines checked
NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX
MULTISTATEMENT_MACRO_USE_DO_WHILE NETWORKING_BLOCK_COMMENT_STYLE USLEEP_RANGE
mbox has no obvious style problems and is ready for submission.
Seems checpatch did not check this ...
this is my mistake. I will fix and recheck.
+ /* start master receive */
+ writel(MCR_MDBS | MCR_MIE | MCR_ESG,dev-icmcr);
+
+ while ((readl(dev-icmsr) (MSR_MAT | MSR_MDE))
+ != (MSR_MAT | MSR_MDE))
+ udelay(10);
+
+ /* clear ESG */
+ writel(MCR_MDBS | MCR_MIE,dev-icmcr);
+ /* prepare stop condition */
+ writel(MCR_MDBS | MCR_MIE | MCR_FSB,dev-icmcr);
+ /* start SCLclk */
+ writel(~(MSR_MAT | MSR_MDR),dev-icmsr);
+
+ while (!(readl(dev-icmsr) MSR_MDR))
+ udelay(10);
+
+ /* get receive data */
+ ret = (u8)readl(dev-icrxdtxd);
+ /* start SCLclk */
+ writel(~MSR_MDR,dev-icmsr);
+
+ rcar_i2c_raw_rw_finish(dev);
+
+ return ret;
+}
+
+
Please only one empty line.
[...]
OK, I will remove this line.
bye,
Heiko
Best regards,
Nobuhiro
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[U-Boot] [PATCH v2] i2c: Add support for Renesas rcar
This supports i2c controller for Renesas rcar.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
v2:
- Add infomation about rcar_i2c to README.
- Remove empty line.
- Fix space.
- Keep list sorted in Makefile
README | 14 +++
drivers/i2c/Makefile | 1 +
drivers/i2c/rcar_i2c.c | 288 +
3 files changed, 303 insertions(+)
create mode 100644 drivers/i2c/rcar_i2c.c
diff --git a/README b/README
index ccd47fa..98c385a 100644
--- a/README
+++ b/README
@@ -1995,6 +1995,20 @@ CBFS (Coreboot Filesystem) support
- CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
- CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
+ - drivers/i2c/rcar_i2c.c:
+ - activate this driver with CONFIG_SYS_I2C_RCAR
+ - This driver adds 4 i2c buses
+
+ - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
+ - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
+ - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
+ - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
+ - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
+ - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
+ - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
+ - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
+ - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for nummber of i2c buses
+
additional defines:
CONFIG_SYS_NUM_I2C_BUSES
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 37ccbd1..e028534 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_SYS_I2C) += i2c_core.o
COBJS-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
COBJS-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
COBJS-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
+COBJS-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
COBJS-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
COBJS-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
COBJS-$(CONFIG_ZYNQ_I2C) += zynq_i2c.o
diff --git a/drivers/i2c/rcar_i2c.c b/drivers/i2c/rcar_i2c.c
new file mode 100644
index 000..ba2cadb
--- /dev/null
+++ b/drivers/i2c/rcar_i2c.c
@@ -0,0 +1,288 @@
+/*
+ * drivers/i2c/rcar_i2c.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include common.h
+#include i2c.h
+#include asm/io.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rcar_i2c {
+ u32 icscr;
+ u32 icmcr;
+ u32 icssr;
+ u32 icmsr;
+ u32 icsier;
+ u32 icmier;
+ u32 icccr;
+ u32 icsar;
+ u32 icmar;
+ u32 icrxdtxd;
+ u32 icccr2;
+ u32 icmpr;
+ u32 ichpr;
+ u32 iclpr;
+};
+
+#define MCR_MDBS 0x80/* non-fifo mode switch */
+#define MCR_FSCL 0x40/* override SCL pin */
+#define MCR_FSDA 0x20/* override SDA pin */
+#define MCR_OBPC 0x10/* override pins*/
+#define MCR_MIE0x08/* master if enable */
+#define MCR_TSBE 0x04
+#define MCR_FSB0x02/* force stop bit */
+#define MCR_ESG0x01/* en startbit gen. */
+
+#define MSR_MASK 0x7f
+#define MSR_MNR0x40/* nack received*/
+#define MSR_MAL0x20/* arbitration lost */
+#define MSR_MST0x10/* sent a stop */
+#define MSR_MDE0x08
+#define MSR_MDT0x04
+#define MSR_MDR0x02
+#define MSR_MAT0x01/* slave addr xfer done */
+
+static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = {
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE,
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE,
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE,
+ (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE,
+};
+
+static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr)
+{
+ /* set slave address */
+ writel(chip 1, dev-icmar);
+ /* set register address */
+ writel(addr, dev-icrxdtxd);
+ /* clear status */
+ writel(0, dev-icmsr);
+ /* start master send */
+ writel(MCR_MDBS | MCR_MIE | MCR_ESG, dev-icmcr);
+
+ while ((readl(dev-icmsr) (MSR_MAT | MSR_MDE))
+ != (MSR_MAT | MSR_MDE))
+ udelay(10);
+
+ /* clear ESG */
+ writel(MCR_MDBS | MCR_MIE, dev-icmcr);
+ /* start SCLclk */
+ writel(~(MSR_MAT | MSR_MDE), dev-icmsr);
+
+ while (!(readl(dev-icmsr) MSR_MDE))
+ udelay(10);
+}
+
+static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev
[U-Boot] [PATCH v2 4/4] arm: rmobile: armadillo-800eva: Change clock definition of SCIF and TMU
This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to CONFIG_SH_TMU_CLK_FREQ, Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com CC: Nobuhiro Iwamatsu iwama...@nigauri.org CC: Albert Aribaud albert.u.b...@aribaud.net --- v2: no changes. re-send as further series. include/configs/armadillo-800eva.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h index 9f357ea..7a264b0 100644 --- a/include/configs/armadillo-800eva.h +++ b/include/configs/armadillo-800eva.h @@ -138,6 +138,8 @@ /* Board Clock */ #define CONFIG_SYS_CLK_FREQ5000 +#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ #define CONFIG_SYS_TMU_CLK_DIV 4 #define CONFIG_SYS_HZ 1000 -- 1.8.4.rc3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
