Re: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

2014-10-09 Thread Peng Fan

Hi,

Any reply about this patch? It is long time since this patch was sent out.

Regards,
Peng.
On 09/11/2014 10:30 AM, Fan Peng-B51431 wrote:
 Just CC Stefano Babic sba...@denx.de
 
 Regards,
 Peng.
 
 -Original Message-
 From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On 
 Behalf Of Peng Fan
 Sent: Thursday, September 11, 2014 9:56 AM
 To: Estevam Fabio-R49496; Li Ye-B37916
 Cc: u-boot@lists.denx.de
 Subject: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support
 
 Configure the pad setting and enable qspi clock to support qspi flashes 
 access.
 
 This patch has been tested on mx6sxsabresd board.
 
 Signed-off-by: Peng Fan peng@freescale.com
 ---
 
 Changelog v2:
  Take Fabio's suggestion, split soc code and board code into two patches.
  This patch needs 'ARM:MX6SX Add QSPI support' patch.
 
  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 
 +
  include/configs/mx6sxsabresd.h  | 14 ++
  2 files changed, 54 insertions(+)
 
 diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
 b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
 index 5eaec1b..f9cad5a 100644
 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
 +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
 @@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
   return fsl_esdhc_initialize(bis, usdhc_cfg[0]);  }
  
 +#ifdef CONFIG_FSL_QSPI
 +
 +#define QSPI_PAD_CTRL1   \
 + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
 +  PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
 +
 +static iomux_v3_cfg_t const quadspi_pads[] = {
 + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_CLE__QSPI2_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA05__QSPI2_B_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 +};
 +
 +int board_qspi_init(void)
 +{
 + /* Set the iomux */
 + imx_iomux_v3_setup_multiple_pads(quadspi_pads,
 +  ARRAY_SIZE(quadspi_pads));
 +
 + /* Set the clock */
 + enable_qspi_clk(1);
 +
 + return 0;
 +}
 +#endif
 +
  int board_init(void)
  {
   /* Address of boot parameters */
   gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
  
 +#ifdef CONFIG_FSL_QSPI
 + board_qspi_init();
 +#endif
 +
   return 0;
  }
  
 diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h 
 index 1eda65e..00031ec 100644
 --- a/include/configs/mx6sxsabresd.h
 +++ b/include/configs/mx6sxsabresd.h
 @@ -201,6 +201,20 @@
  /* FLASH and environment organization */  #define CONFIG_SYS_NO_FLASH
  
 +#define CONFIG_FSL_QSPI
 +
 +#ifdef CONFIG_FSL_QSPI
 +#define CONFIG_CMD_SF
 +#define CONFIG_SPI_FLASH
 +#define CONFIG_SPI_FLASH_SPANSION
 +#define CONFIG_SPI_FLASH_STMICRO
 +#define CONFIG_SYS_FSL_QSPI_LE
 +#define CONFIG_QSPI_BASE QSPI2_BASE_ADDR
 +#define CONFIG_QSPI_MEMMAP_BASE  QSPI2_ARB_BASE_ADDR
 +#define FSL_QSPI_FLASH_SIZE  SZ_16M
 +#define FSL_QSPI_FLASH_NUM   2
 +#endif
 +
  #define CONFIG_ENV_OFFSET(6 * SZ_64K)
  #define CONFIG_ENV_SIZE  SZ_8K
  #define CONFIG_ENV_IS_IN_MMC
 --
 1.8.4
 
 
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Re: [U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

2014-10-09 Thread Peng Fan
Hi,

just ping, Any comments about this patch? 

Regards,
Peng.
On 09/11/2014 09:54 AM, Peng Fan wrote:
 Add QSPI support for mx6solox.
 
 Signed-off-by: Peng Fan peng@freescale.com
 ---
 
 Changelog v2:
  Take Fabio's suggestion, split soc code and board code into two patches.
 
  arch/arm/cpu/armv7/mx6/clock.c| 50 
 +++
  arch/arm/include/asm/arch-mx6/clock.h |  3 +++
  drivers/spi/fsl_qspi.c| 29 
  3 files changed, 82 insertions(+)
 
 diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
 index 820b8d5..8caa61d 100644
 --- a/arch/arm/cpu/armv7/mx6/clock.c
 +++ b/arch/arm/cpu/armv7/mx6/clock.c
 @@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void)
  }
  #endif
  
 +#ifdef CONFIG_MX6SX
 +/* qspi_num can be from 0 - 1 */
 +void enable_qspi_clk(int qspi_num)
 +{
 + u32 reg = 0;
 + /* Enable QuadSPI clock */
 + switch (qspi_num) {
 + case 0:
 + /* disable the clock gate */
 + clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 +
 + /* set 50M  : (50 = 396 / 2 / 4) */
 + reg = readl(imx_ccm-cscmr1);
 + reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
 +  MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
 + reg |= ((1  MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
 + (2  MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
 + writel(reg, imx_ccm-cscmr1);
 +
 + /* enable the clock gate */
 + setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
 + break;
 + case 1:
 + /*
 +  * disable the clock gate
 +  * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
 +  * disable both of them.
 +  */
 + clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 +  
 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 +
 + /* set 50M  : (50 = 396 / 2 / 4) */
 + reg = readl(imx_ccm-cs2cdr);
 + reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
 +  MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
 +  MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
 + reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
 + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
 + writel(reg, imx_ccm-cs2cdr);
 +
 + /*enable the clock gate*/
 + setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
 +  
 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
 + break;
 + default:
 + break;
 + }
 +}
 +#endif
 +
  #ifdef CONFIG_FEC_MXC
  int enable_fec_anatop_clock(enum enet_freq freq)
  {
 diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
 b/arch/arm/include/asm/arch-mx6/clock.h
 index 339c789..9d0ba7a 100644
 --- a/arch/arm/include/asm/arch-mx6/clock.h
 +++ b/arch/arm/include/asm/arch-mx6/clock.h
 @@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  int enable_spi_clk(unsigned char enable, unsigned spi_num);
  void enable_ipu_clock(void);
  int enable_fec_anatop_clock(enum enet_freq freq);
 +#ifdef CONFIG_MX6SX
 +void enable_qspi_clk(int qspi_num);
 +#endif
  #endif /* __ASM_ARCH_CLOCK_H */
 diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
 index ba20bef..7c8d065 100644
 --- a/drivers/spi/fsl_qspi.c
 +++ b/drivers/spi/fsl_qspi.c
 @@ -14,7 +14,11 @@
  #include fsl_qspi.h
  
  #define RX_BUFFER_SIZE   0x80
 +#ifdef CONFIG_MX6SX
 +#define TX_BUFFER_SIZE   0x200
 +#else
  #define TX_BUFFER_SIZE   0x40
 +#endif
  
  #define OFFSET_BITS_MASK 0x00ff
  
 @@ -52,11 +56,19 @@
  #endif
  
  static unsigned long spi_bases[] = {
 +#ifdef CONFIG_MX6SX
 + CONFIG_QSPI_BASE,
 +#else
   QSPI0_BASE_ADDR,
 +#endif
  };
  
  static unsigned long amba_bases[] = {
 +#ifdef CONFIG_MX6SX
 + CONFIG_QSPI_MEMMAP_BASE,
 +#else
   QSPI0_AMBA_BASE,
 +#endif
  };
  
  struct fsl_qspi {
 @@ -157,8 +169,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_PP_4B) |
   PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
   PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 +#ifdef CONFIG_MX6SX
 + /* Use IDATSZ in IPCR to determine the size */
 + qspi_write32(regs-lut[lut_base + 1], OPRND0(0) |
 + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 +#else
   qspi_write32(regs-lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
   PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
 +#endif
   qspi_write32(regs-lut[lut_base + 2], 0);
   qspi_write32(regs-lut[lut_base + 3], 0);
  
 @@ -192,6 +210,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
 unsigned int cs,
   if (bus = ARRAY_SIZE(spi_bases))
   return NULL;
  
 +#ifdef CONFIG_MX6SX
 + /* cs should be 0

Re: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

2014-10-09 Thread Peng Fan
Hi,

On 10/09/2014 06:37 PM, Jagan Teki wrote:
 Hi Peng Fan,
 
 Before reviewing these two patches, I'm requesting some sort work from
 your side like
 Can you update/fix the driver drivers/spi/fsl_qspi.c without using
 flash opcodes.
 
 Using flash opcode's with in the (q)spi driver is not recommended
 please think on that
 direction.
Yeah, many OPCODE_XX are used in this driver. 

There is a LUT table containing 16 entries in the QSPI Controller. 
The Look-up-table or LUT consists of a number of pre-programmed sequences. Each
sequence is basically a sequence of instruction-operand pairs which when 
executed
sequentially generates a valid serial flash transaction. Each sequence can have 
a
maximum of 8 instruction-operand pairs. 
The instruction holds the flash opcode that should be pre-programmed, and the
qspi_set_lut in drivers/spi/fsl_qspi.c does this work.

It is not easy to program the lut dynamically in the driver without using the 
flash opcodes.
So I wonder whether CMD_xxx in drivers/mtd/spi/sf_internal.h can be used or 
not. Or,
can QSPI_CMD_xxx be used but not OPCODE_xx?  Actually if QSPI_CMD_xx can be 
used, the value
QSPI_CMD_xx is the same with OPCODE_xx, just different macro names.

Regards,
Peng.

 
 On 9 October 2014 14:37, Peng Fan b51...@freescale.com wrote:

 Hi,

 Any reply about this patch? It is long time since this patch was sent out.

 Regards,
 Peng.
 On 09/11/2014 10:30 AM, Fan Peng-B51431 wrote:
 Just CC Stefano Babic sba...@denx.de

 Regards,
 Peng.

 -Original Message-
 From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On 
 Behalf Of Peng Fan
 Sent: Thursday, September 11, 2014 9:56 AM
 To: Estevam Fabio-R49496; Li Ye-B37916
 Cc: u-boot@lists.denx.de
 Subject: [U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

 Configure the pad setting and enable qspi clock to support qspi flashes 
 access.

 This patch has been tested on mx6sxsabresd board.

 Signed-off-by: Peng Fan peng@freescale.com
 ---

 Changelog v2:
  Take Fabio's suggestion, split soc code and board code into two patches.
  This patch needs 'ARM:MX6SX Add QSPI support' patch.

  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 
 +
  include/configs/mx6sxsabresd.h  | 14 ++
  2 files changed, 54 insertions(+)

 diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
 b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
 index 5eaec1b..f9cad5a 100644
 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
 +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
 @@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
   return fsl_esdhc_initialize(bis, usdhc_cfg[0]);  }

 +#ifdef CONFIG_FSL_QSPI
 +
 +#define QSPI_PAD_CTRL1   \
 + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
 +  PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
 +
 +static iomux_v3_cfg_t const quadspi_pads[] = {
 + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0   | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2  | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3  | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_CLE__QSPI2_A_SCLK  | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA07__QSPI2_A_DQS| 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2   | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3   | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B  | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK   | 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 + MX6_PAD_NAND_DATA05__QSPI2_B_DQS| 
 MUX_PAD_CTRL(QSPI_PAD_CTRL1),
 +};
 +
 +int board_qspi_init(void)
 +{
 + /* Set the iomux */
 + imx_iomux_v3_setup_multiple_pads(quadspi_pads,
 +  ARRAY_SIZE(quadspi_pads));
 +
 + /* Set the clock */
 + enable_qspi_clk(1);
 +
 + return 0;
 +}
 +#endif
 +
  int board_init(void)
  {
   /* Address of boot parameters */
   gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;

 +#ifdef CONFIG_FSL_QSPI
 + board_qspi_init();
 +#endif
 +
   return 0;
  }

 diff --git a/include/configs/mx6sxsabresd.h 
 b/include/configs/mx6sxsabresd.h index 1eda65e..00031ec 100644
 --- a/include/configs/mx6sxsabresd.h
 +++ b/include/configs/mx6sxsabresd.h
 @@ -201,6 +201,20 @@
  /* FLASH and environment organization */  #define CONFIG_SYS_NO_FLASH

 +#define CONFIG_FSL_QSPI
 +
 +#ifdef CONFIG_FSL_QSPI
 +#define CONFIG_CMD_SF
 +#define CONFIG_SPI_FLASH
 +#define CONFIG_SPI_FLASH_SPANSION
 +#define CONFIG_SPI_FLASH_STMICRO

[U-Boot] [PATCH v3 1/4] QuadSPI: use QSPI_CMD_xx instead of flash opcodes

2014-10-14 Thread Peng Fan
Use QSPI_CMD_xx instead of flash opcodes

Signed-off-by: Peng Fan peng@freescale.com
---

Changelog v3:
 Use QSPI_CMD_XX instead of flash opcodes. To fsl qspi controller, the LUT
 should be pre programmed with QSPI CMD.

Changelog v2:
 none

 drivers/spi/fsl_qspi.c | 64 ++
 1 file changed, 33 insertions(+), 31 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ba20bef..61490c9 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -29,19 +29,19 @@
 #define SEQID_PP   6
 #define SEQID_RDID 7
 
-/* Flash opcodes */
-#define OPCODE_PP  0x02/* Page program (up to 256 bytes) */
-#define OPCODE_RDSR0x05/* Read status register */
-#define OPCODE_WREN0x06/* Write enable */
-#define OPCODE_FAST_READ   0x0b/* Read data bytes (high frequency) */
-#define OPCODE_CHIP_ERASE  0xc7/* Erase whole flash chip */
-#define OPCODE_SE  0xd8/* Sector erase (usually 64KiB) */
-#define OPCODE_RDID0x9f/* Read JEDEC ID */
-
-/* 4-byte address opcodes - used on Spansion and some Macronix flashes */
-#define OPCODE_FAST_READ_4B0x0c/* Read data bytes (high frequency) */
-#define OPCODE_PP_4B   0x12/* Page program (up to 256 bytes) */
-#define OPCODE_SE_4B   0xdc/* Sector erase (usually 64KiB) */
+/* QSPI CMD */
+#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
+#define QSPI_CMD_RDSR  0x05/* Read status register */
+#define QSPI_CMD_WREN  0x06/* Write enable */
+#define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
+#define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
+#define QSPI_CMD_RDID  0x9f/* Read JEDEC ID */
+
+/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
+#define QSPI_CMD_FAST_READ_4B  0x0c/* Read data bytes (high frequency) */
+#define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
+#define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
 
 #ifdef CONFIG_SYS_FSL_QSPI_LE
 #define qspi_read32in_le32
@@ -94,7 +94,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
 
/* Write Enable */
lut_base = SEQID_WREN * 4;
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_WREN) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_WREN) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(regs-lut[lut_base + 1], 0);
qspi_write32(regs-lut[lut_base + 2], 0);
@@ -103,13 +103,15 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
/* Fast Read */
lut_base = SEQID_FAST_READ * 4;
if (FSL_QSPI_FLASH_SIZE  = SZ_16M)
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_FAST_READ) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) |
-   PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
-   PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+   qspi_write32(regs-lut[lut_base],
+OPRND0(QSPI_CMD_FAST_READ_4B) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
+OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
+INSTR1(LUT_ADDR));
qspi_write32(regs-lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
INSTR1(LUT_READ));
@@ -118,7 +120,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_RDSR) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
qspi_write32(regs-lut[lut_base + 1], 0);
@@ -128,11 +130,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
/* Erase a sector */
lut_base = SEQID_SE * 4;
if (FSL_QSPI_FLASH_SIZE  = SZ_16M)
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_SE) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_SE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_SE_4B) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD

[U-Boot] [PATCH v3 2/4] QuadSPI: use correct amba_base

2014-10-14 Thread Peng Fan
According cs, use different amba_base to choose the corresponding
flash devices.  If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.

Signed-off-by: Peng Fan peng@freescale.com
---

Changelog v3:
 none

Changelog v2:
 none

 drivers/spi/fsl_qspi.c | 30 +-
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 61490c9..eae2f3a 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -194,12 +194,22 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
if (bus = ARRAY_SIZE(spi_bases))
return NULL;
 
+   if (cs = FSL_QSPI_FLASH_NUM)
+   return NULL;
+
qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
if (!qspi)
return NULL;
 
qspi-reg_base = spi_bases[bus];
-   qspi-amba_base = amba_bases[bus];
+   /*
+* According cs, use different amba_base to choose the
+* corresponding flash devices.
+*
+* If not, only one flash device is used even if passing
+* different cs using `sf probe`
+*/
+   qspi-amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 
qspi-slave.max_write_size = TX_BUFFER_SIZE;
 
@@ -212,10 +222,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
qspi_write32(regs-mcr, QSPI_MCR_RESERVED_MASK);
 
total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
-   qspi_write32(regs-sfa1ad, FSL_QSPI_FLASH_SIZE | qspi-amba_base);
-   qspi_write32(regs-sfa2ad, FSL_QSPI_FLASH_SIZE | qspi-amba_base);
-   qspi_write32(regs-sfb1ad, total_size | qspi-amba_base);
-   qspi_write32(regs-sfb2ad, total_size | qspi-amba_base);
+   /*
+* Any read access to non-implemented addresses will provide
+* undefined results.
+*
+* In case single die flash devices, TOP_ADDR_MEMA2 and
+* TOP_ADDR_MEMB2 should be initialized/programmed to
+* TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
+* setting the size of these devices to 0.  This would ensure
+* that the complete memory map is assigned to only one flash device.
+*/
+   qspi_write32(regs-sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+   qspi_write32(regs-sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+   qspi_write32(regs-sfb1ad, total_size | amba_bases[bus]);
+   qspi_write32(regs-sfb2ad, total_size | amba_bases[bus]);
 
qspi_set_lut(qspi);
 
-- 
1.8.4


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[U-Boot] [PATCH v3 3/4] arm:mx6sx add QSPI support

2014-10-14 Thread Peng Fan
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan peng@freescale.com
---

Changelog v3:
 none

Changelog v2:
 Take Fabio's suggestion, split soc code and board code into two patches.

 arch/arm/cpu/armv7/mx6/clock.c   | 50 
 arch/arm/include/asm/arch-mx6/clock.h|  1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h | 12 
 drivers/spi/fsl_qspi.c   | 19 
 4 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index d200531..d11f98e 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -430,6 +430,56 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+   u32 reg = 0;
+   /* Enable QuadSPI clock */
+   switch (qspi_num) {
+   case 0:
+   /* disable the clock gate */
+   clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cscmr1);
+   reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+   reg |= ((1  MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+   (2  MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+   writel(reg, imx_ccm-cscmr1);
+
+   /* enable the clock gate */
+   setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+   break;
+   case 1:
+   /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+   clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cs2cdr);
+   reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+   reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+   MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+   writel(reg, imx_ccm-cs2cdr);
+
+   /*enable the clock gate*/
+   setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+   break;
+   default:
+   break;
+   }
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 3c58a0a..4eb5ba4 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -66,4 +66,5 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index a159309..5d07904 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -92,10 +92,10 @@
 #define AIPS3_END_ADDR 0x022F
 #define WEIM_ARB_BASE_ADDR  0x5000
 #define WEIM_ARB_END_ADDR   0x57FF
-#define QSPI1_ARB_BASE_ADDR 0x6000
-#define QSPI1_ARB_END_ADDR  0x6FFF
-#define QSPI2_ARB_BASE_ADDR 0x7000
-#define QSPI2_ARB_END_ADDR  0x7FFF
+#define QSPI0_AMBA_BASE0x6000
+#define QSPI0_AMBA_END 0x6FFF
+#define QSPI1_AMBA_BASE0x7000
+#define QSPI1_AMBA_END 0x7FFF
 #else
 #define SATA_ARB_BASE_ADDR  0x0220
 #define SATA_ARB_END_ADDR   0x02203FFF
@@ -262,8 +262,8 @@
 #define AUDMUX_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x58000)
 #ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6)
-#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6)
+#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x6)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index eae2f3a..e9c45de 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,11 @@
 #include fsl_qspi.h
 
 #define RX_BUFFER_SIZE

[U-Boot] [PATCH v3 4/4] imx:mx6sxsabresd add qspi support

2014-10-14 Thread Peng Fan
Configure the pad setting and enable qspi clock to support qspi
flashes access.

Signed-off-by: Peng Fan peng@freescale.com
---

Changelog v3:
 none

Changelog v2:
 Take Fabio's suggestion, split soc code and board code into two patches.

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +
 include/configs/mx6sxsabresd.h  | 12 +
 2 files changed, 52 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 68d3718..0d8b214 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
 }
 
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+   (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+   MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CLE__QSPI2_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA02__QSPI2_B_SCLK   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA05__QSPI2_B_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+   /* Set the iomux */
+   imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ARRAY_SIZE(quadspi_pads));
+
+   /* Set the clock */
+   enable_qspi_clk(1);
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* Address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_FSL_QSPI
+   board_qspi_init();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index e02ea18..032be89 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -211,6 +211,18 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_FSL_QSPI_LE
+#define FSL_QSPI_FLASH_SIZESZ_16M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
 #define CONFIG_ENV_OFFSET  (6 * SZ_64K)
 #define CONFIG_ENV_SIZESZ_8K
 #define CONFIG_ENV_IS_IN_MMC
-- 
1.8.4


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Re: [U-Boot] MMU Mapping

2014-08-22 Thread Peng Fan
Hi,

On 08/21/2014 06:44 PM, Stefano Babic wrote:
 Hi Alexandre,
 
 On 21/08/2014 11:08, Alexandre Delove wrote:
 Hello

 I am trying to disable the memory management unit on my sabreLite board, but 
 i don't find what i should do. I also want to change the mapping of the MMU, 
 but i don't know where it is.

 
 MMU is off in U-Boot. It is turned on by kernel. Or what do you mind ?

To ARM, if not defined CONFIG_SYS_DCACHE_OFF, 
dcache_enable-cache_enable(CR_C)-mmu_setup will enable mmu and build section 
mapping. U can try #define CONFIG_SYS_DCACHE_OFF if it is an ARM SoC board. mmu 
related code locates at arch/arm/lib/cache-cp15.c

Regards,
Peng.
 
 Best regards,
 Stefano Babic
 
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[U-Boot] [PATCH] kgdb: Remove first_entry for kgdb

2014-09-01 Thread Peng Fan
There are two ways to run into handle_exception, run command 'kgdb' and
encounter a breakpoint which triggers exception handling.

The origin source code only saves regs when first run command 'kgdb'.
Take the following for example, When run 'kgdb', regs is saved to entry_regs.
When run 'bootz', regs is not saved. However, if we set a breakpoint, then
continue. When breakpoint is reached, run `quit`, and Now return to the
instruction which follows kgdb, but not bootz.This may cause errors. So,
save regs for each handle_exception call to return to the correct place.
Example:
Target  |Host
=kgdb  |(gdb)b bootz
|(gdb)c
=bootz |
|(gdb)Here stop because of breakpoint
|(gdb)q

Signed-off-by: Peng Fan van.free...@gmail.com
---
 common/kgdb.c | 14 ++
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/common/kgdb.c b/common/kgdb.c
index 8a621ad..d357463 100644
--- a/common/kgdb.c
+++ b/common/kgdb.c
@@ -103,7 +103,7 @@ static char remcomOutBuffer[BUFMAX];
 static char remcomRegBuffer[BUFMAX];
 
 static int initialized = 0;
-static int kgdb_active = 0, first_entry = 1;
+static int kgdb_active;
 static struct pt_regs entry_regs;
 static long error_jmp_buf[BUFMAX/2];
 static int longjmp_on_fault = 0;
@@ -348,16 +348,7 @@ handle_exception (struct pt_regs *regs)
 
kgdb_enter(regs, kd);
 
-   if (first_entry) {
-   /*
-* the first time we enter kgdb, we save the processor
-* state so that we can return to the monitor if the
-* remote end quits gdb (or at least, tells us to quit
-* with the 'k' packet)
-*/
-   entry_regs = *regs;
-   first_entry = 0;
-   }
+   entry_regs = *regs;
 
ptr = remcomOutBuffer;
 
@@ -459,7 +450,6 @@ handle_exception (struct pt_regs *regs)
case 'k':/* kill the program, actually return to monitor */
kd.extype = KGDBEXIT_KILL;
*regs = entry_regs;
-   first_entry = 1;
goto doexit;
 
case 'C':/* CSS  continue with signal SS */
-- 
1.8.4

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[U-Boot] [PATCH 3/3] QSPI: Enable QSPI AHB read for MX6SX

2014-09-10 Thread Peng Fan
From: Peng Fan van.free...@gmail.com

There are two different ways to read out the data from the flash:
the IP Command Read and the AHB Command Read.

The IC guy suggests we use the AHB Command Read which is faster
then the IP Command Read. (What's more is that there is a bug in
the IP Command Read in the Vybrid.)

After we set up the registers for the AHB Command Read, we can use
the memcpy to read the data directly. A missed access to the buffer
causes the controller to clear the buffer, and use the sequence pointed
by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.

Signed-off-by: Peng Fan van.free...@gmail.com
---
 drivers/spi/fsl_qspi.c | 81 ++
 drivers/spi/fsl_qspi.h | 11 +++
 2 files changed, 92 insertions(+)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index b1d75e7..95b36f0 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -215,6 +215,52 @@ void spi_init()
/* do nothing */
 }
 
+#ifdef CONFIG_MX6SX
+static void qspi_ahb_read(struct fsl_qspi *qspi, u8 *rxbuf, u32 len)
+{
+   struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+   u32 mcr_reg;
+   u32 to_or_from;
+
+   to_or_from = qspi-sf_addr + qspi-amba_base;
+
+   mcr_reg = qspi_read32(regs-mcr);
+   qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK |
+QSPI_MCR_CLR_TXF_MASK | QSPI_MCR_RESERVED_MASK |
+QSPI_MCR_END_CFD_LE_64);
+
+   /* Read out the data directly from the AHB buffer.*/
+   memcpy(rxbuf, (u8 *)to_or_from, len);
+
+   qspi_write32(regs-mcr, mcr_reg);
+}
+
+/*
+ * If we have changed the content of the flash by writing or erasing,
+ * we need to invalidate the AHB buffer. If we do not do so, we may read out
+ * the wrong data. The spec tells us reset the AHB domain and Serial Flash
+ * domain at the same time.
+ */
+static inline void qspi_invalid_buf(struct fsl_qspi *qspi)
+{
+   struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+   u32 mcr_reg;
+
+   mcr_reg = qspi_read32(regs-mcr);
+   mcr_reg |= QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK;
+   qspi_write32(regs-mcr, mcr_reg);
+
+   /*
+* The minimum delay : 1 AHB + 2 SFCK clocks.
+* Delay 1 us is enough.
+*/
+   udelay(1);
+
+   mcr_reg = ~(QSPI_MCR_SWRSTHD_MASK | QSPI_MCR_SWRSTSD_MASK);
+   qspi_write32(regs-mcr, mcr_reg);
+}
+#endif
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
 {
@@ -266,9 +312,30 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
smpr_val = qspi_read32(regs-smpr);
smpr_val = ~QSPI_SMPR_DDRSMP_MASK;
qspi_write32(regs-smpr, smpr_val);
+
+#ifdef CONFIG_MX6SX
+   qspi_write32(regs-mcr, QSPI_MCR_RESERVED_MASK |
+QSPI_MCR_END_CFD_LE  QSPI_MCR_END_CFD_SHIFT);
+#else
qspi_write32(regs-mcr, QSPI_MCR_RESERVED_MASK);
+#endif
 
+#ifdef CONFIG_MX6SX
+   /* AHB configuration for access buffer 0/1/2 */
+   qspi_write32(regs-buf0cr, QSPI_BUFXCR_INVALID_MSTRID);
+   qspi_write32(regs-buf1cr, QSPI_BUFXCR_INVALID_MSTRID);
+   qspi_write32(regs-buf2cr, QSPI_BUFXCR_INVALID_MSTRID);
+   qspi_write32(regs-buf3cr, QSPI_BUF3CR_ALLMST_MASK |
+(0x80  QSPI_BUF3CR_ADATSZ_SHIFT));
+
+   qspi_write32(regs-buf0ind, 0);
+   qspi_write32(regs-buf1ind, 0);
+   qspi_write32(regs-buf2ind, 0);
+
+   seq_id = SEQID_FAST_READ;
+#else
seq_id = 0;
+#endif
reg_val = qspi_read32(regs-bfgencr);
reg_val = ~QSPI_BFGENCR_SEQID_MASK;
reg_val |= (seq_id  QSPI_BFGENCR_SEQID_SHIFT);
@@ -324,6 +391,7 @@ static void qspi_op_rdid(struct fsl_qspi *qspi, u32 *rxbuf, 
u32 len)
qspi_write32(regs-mcr, mcr_reg);
 }
 
+#ifndef CONFIG_MX6SX
 static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, u32 len)
 {
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
@@ -367,6 +435,7 @@ static void qspi_op_read(struct fsl_qspi *qspi, u32 *rxbuf, 
u32 len)
 
qspi_write32(regs-mcr, mcr_reg);
 }
+#endif
 
 static void qspi_op_wrr(struct fsl_qspi *qspi, u8 *txbuf, u32 len)
 {
@@ -470,6 +539,10 @@ static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, 
u32 len)
;
 
qspi_write32(regs-mcr, mcr_reg);
+
+#ifdef CONFIG_MX6SX
+   qspi_invalid_buf(qspi);
+#endif
 }
 
 static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
@@ -529,6 +602,10 @@ static void qspi_op_se(struct fsl_qspi *qspi)
;
 
qspi_write32(regs-mcr, mcr_reg);
+
+#ifdef CONFIG_MX6SX
+   qspi_invalid_buf(qspi);
+#endif
 }
 
 int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
@@ -567,7 +644,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
if (din) {
if (qspi-cur_seqid == OPCODE_FAST_READ)
+#ifdef CONFIG_MX6SX

[U-Boot] [PATCH 0/3] Add QSPI support for mx6sxsabresd board

2014-09-10 Thread Peng Fan
From: Peng Fan van.free...@gmail.com

This patch set is to support QSPI for mx6sxsabresd board. And
register read/write is implmented. AHB read is also supported to
improve flash read performance.

All the three patches have been tested on mx6sxsabresd board.

Peng Fan (3):
  ARM:MX6SX Add QuadSPI support for mx6sxsabresd
  QSPI: Enable write device registers
  QSPI: Enable QSPI AHB read for MX6SX

 arch/arm/cpu/armv7/mx6/clock.c  |  50 
 arch/arm/include/asm/arch-mx6/clock.h   |   3 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c |  40 ++
 drivers/spi/fsl_qspi.c  | 188 +++-
 drivers/spi/fsl_qspi.h  |  11 ++
 include/configs/mx6sxsabresd.h  |  14 +++
 6 files changed, 303 insertions(+), 3 deletions(-)

-- 
1.8.4


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[U-Boot] [PATCH 1/3] ARM:MX6SX Add QuadSPI support for mx6sxsabresd

2014-09-10 Thread Peng Fan
From: Peng Fan van.free...@gmail.com

Add QuadSPI support for mx6sxsabresd board.

There are two 16MB S25FL128S flashes on board. They are connected to
QSPI2 interface. i.MX6SX supports two QuadSPI interfaces, QSPI1/2.
The two flash devices are connected to A1/B1 of QSPI2.

Signed-off-by: Peng Fan van.free...@gmail.com
---
 arch/arm/cpu/armv7/mx6/clock.c  | 50 +
 arch/arm/include/asm/arch-mx6/clock.h   |  3 ++
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++
 drivers/spi/fsl_qspi.c  | 30 +
 include/configs/mx6sxsabresd.h  | 14 
 5 files changed, 137 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..8caa61d 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+   u32 reg = 0;
+   /* Enable QuadSPI clock */
+   switch (qspi_num) {
+   case 0:
+   /* disable the clock gate */
+   clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cscmr1);
+   reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+   reg |= ((1  MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+   (2  MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+   writel(reg, imx_ccm-cscmr1);
+
+   /* enable the clock gate */
+   setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+   break;
+   case 1:
+   /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+   clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cs2cdr);
+   reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+   reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+   MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+   writel(reg, imx_ccm-cs2cdr);
+
+   /*enable the clock gate*/
+   setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+   break;
+   default:
+   break;
+   }
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 339c789..9d0ba7a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
+#ifdef CONFIG_MX6SX
+void enable_qspi_clk(int qspi_num);
+#endif
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 5eaec1b..f9cad5a 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
 }
 
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+   (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+   MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CLE__QSPI2_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3   | MUX_PAD_CTRL(QSPI_PAD_CTRL1

[U-Boot] [PATCH 2/3] QSPI: Enable write device registers

2014-09-10 Thread Peng Fan
From: Peng Fan van.free...@gmail.com

Add qspi_op_wrr to support status and configuration register write in
flash devices.

Signed-off-by: Peng Fan van.free...@gmail.com
---
 drivers/spi/fsl_qspi.c | 77 --
 1 file changed, 74 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 7e8d07e..b1d75e7 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -32,12 +32,16 @@
 #define SEQID_CHIP_ERASE   5
 #define SEQID_PP   6
 #define SEQID_RDID 7
+#define SEQID_WRR  8
+#define SEQID_RDCR 9
 
 /* Flash opcodes */
+#define OPCODE_WRR 0x01/* Write status/config register */
 #define OPCODE_PP  0x02/* Page program (up to 256 bytes) */
 #define OPCODE_RDSR0x05/* Read status register */
 #define OPCODE_WREN0x06/* Write enable */
 #define OPCODE_FAST_READ   0x0b/* Read data bytes (high frequency) */
+#define OPCODE_RDCR0x35/* Read configuration register */
 #define OPCODE_CHIP_ERASE  0xc7/* Erase whole flash chip */
 #define OPCODE_SE  0xd8/* Sector erase (usually 64KiB) */
 #define OPCODE_RDID0x9f/* Read JEDEC ID */
@@ -189,6 +193,18 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lut[lut_base + 2], 0);
qspi_write32(regs-lut[lut_base + 3], 0);
 
+   /* Write Register */
+   lut_base = SEQID_WRR * 4;
+   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_WRR) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(LUT_WRITE) |
+PAD1(LUT_PAD1) | INSTR1(0x2));
+
+   /* Read Configuration Register */
+   lut_base = SEQID_RDCR * 4;
+   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_RDCR) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(LUT_READ) |
+PAD1(LUT_PAD1) | INSTR1(0x1));
+
/* Lock the LUT */
qspi_write32(regs-lutkey, LUT_KEY_VALUE);
qspi_write32(regs-lckcr, QSPI_LCKCR_LOCK);
@@ -352,6 +368,55 @@ static void qspi_op_read(struct fsl_qspi *qspi, u32 
*rxbuf, u32 len)
qspi_write32(regs-mcr, mcr_reg);
 }
 
+static void qspi_op_wrr(struct fsl_qspi *qspi, u8 *txbuf, u32 len)
+{
+   struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
+   u32 mcr_reg, data, reg, status_reg;
+   u32 to_or_from;
+
+   mcr_reg = qspi_read32(regs-mcr);
+   qspi_write32(regs-mcr, QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK |
+QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE);
+   qspi_write32(regs-rbct, QSPI_RBCT_RXBRD_USEIPS);
+
+   status_reg = 0;
+   while ((status_reg  FLASH_STATUS_WEL) != FLASH_STATUS_WEL) {
+   qspi_write32(regs-ipcr,
+(SEQID_WREN  QSPI_IPCR_SEQID_SHIFT) | 0);
+   while (qspi_read32(regs-sr)  QSPI_SR_BUSY_MASK)
+   ;
+
+   qspi_write32(regs-ipcr,
+(SEQID_RDSR  QSPI_IPCR_SEQID_SHIFT) | 1);
+   while (qspi_read32(regs-sr)  QSPI_SR_BUSY_MASK)
+   ;
+
+   reg = qspi_read32(regs-rbsr);
+   if (reg  QSPI_RBSR_RDBFL_MASK) {
+   status_reg = qspi_read32(regs-rbdr[0]);
+   status_reg = qspi_endian_xchg(status_reg);
+   }
+   qspi_write32(regs-mcr,
+qspi_read32(regs-mcr) | QSPI_MCR_CLR_RXF_MASK);
+   }
+
+   to_or_from = qspi-amba_base;
+   qspi_write32(regs-sfar, to_or_from);
+
+   /* The max len is 2 for OPCODE_WRR */
+   data = 0;
+   memcpy(data, txbuf, len);
+   data = qspi_endian_xchg(data);
+   qspi_write32(regs-tbdr, data);
+
+   qspi_write32(regs-ipcr,
+(SEQID_WRR  QSPI_IPCR_SEQID_SHIFT) | len);
+   while (qspi_read32(regs-sr)  QSPI_SR_BUSY_MASK)
+   ;
+
+   qspi_write32(regs-mcr, mcr_reg);
+}
+
 static void qspi_op_pp(struct fsl_qspi *qspi, u32 *txbuf, u32 len)
 {
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
@@ -476,11 +541,17 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
if (dout) {
memcpy(txbuf, dout, 4);
-   qspi-cur_seqid = *(u8 *)dout;
+   /* extract cmd when SPI_XFER_BEGIN is set */
+   if (flags  SPI_XFER_BEGIN)
+   qspi-cur_seqid = *(u8 *)dout;
 
if (flags == SPI_XFER_END) {
-   qspi-sf_addr = pp_sfaddr;
-   qspi_op_pp(qspi, (u32 *)dout, bytes);
+   if (qspi-cur_seqid == OPCODE_WRR) {
+   qspi_op_wrr(qspi, (u8 *)dout, bytes);
+   } else if (qspi-cur_seqid == OPCODE_PP) {
+   qspi-sf_addr = pp_sfaddr

Re: [U-Boot] [PATCH 1/3] ARM:MX6SX Add QuadSPI support for mx6sxsabresd

2014-09-10 Thread Peng Fan


On 09/10/2014 08:40 PM, Fabio Estevam wrote:
 On Wed, Sep 10, 2014 at 3:16 AM, Peng Fan peng@freescale.com wrote:
 From: Peng Fan van.free...@gmail.com

 Add QuadSPI support for mx6sxsabresd board.

 There are two 16MB S25FL128S flashes on board. They are connected to
 QSPI2 interface. i.MX6SX supports two QuadSPI interfaces, QSPI1/2.
 The two flash devices are connected to A1/B1 of QSPI2.

 Signed-off-by: Peng Fan van.free...@gmail.com
 ---
  arch/arm/cpu/armv7/mx6/clock.c  | 50 
 +
  arch/arm/include/asm/arch-mx6/clock.h   |  3 ++
  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +++
  drivers/spi/fsl_qspi.c  | 30 +
  include/configs/mx6sxsabresd.h  | 14 
 
 I would split this in two patches: one that adds qspi support for the
 mx6solox SoC and another one that adds qspi support to the
 mx6sxsabresd board.
ok. I'll correct this. Thanks for reviewing.

Regards,
Peng.
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[U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

2014-09-10 Thread Peng Fan
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan peng@freescale.com
---

Changelog v2:
 Take Fabio's suggestion, split soc code and board code into two patches.

 arch/arm/cpu/armv7/mx6/clock.c| 50 +++
 arch/arm/include/asm/arch-mx6/clock.h |  3 +++
 drivers/spi/fsl_qspi.c| 29 
 3 files changed, 82 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..8caa61d 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -340,6 +340,56 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+   u32 reg = 0;
+   /* Enable QuadSPI clock */
+   switch (qspi_num) {
+   case 0:
+   /* disable the clock gate */
+   clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cscmr1);
+   reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+   reg |= ((1  MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+   (2  MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+   writel(reg, imx_ccm-cscmr1);
+
+   /* enable the clock gate */
+   setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+   break;
+   case 1:
+   /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+   clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cs2cdr);
+   reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+   reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+   MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+   writel(reg, imx_ccm-cs2cdr);
+
+   /*enable the clock gate*/
+   setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+   break;
+   default:
+   break;
+   }
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 339c789..9d0ba7a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -60,4 +60,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
+#ifdef CONFIG_MX6SX
+void enable_qspi_clk(int qspi_num);
+#endif
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ba20bef..7c8d065 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,11 @@
 #include fsl_qspi.h
 
 #define RX_BUFFER_SIZE 0x80
+#ifdef CONFIG_MX6SX
+#define TX_BUFFER_SIZE 0x200
+#else
 #define TX_BUFFER_SIZE 0x40
+#endif
 
 #define OFFSET_BITS_MASK   0x00ff
 
@@ -52,11 +56,19 @@
 #endif
 
 static unsigned long spi_bases[] = {
+#ifdef CONFIG_MX6SX
+   CONFIG_QSPI_BASE,
+#else
QSPI0_BASE_ADDR,
+#endif
 };
 
 static unsigned long amba_bases[] = {
+#ifdef CONFIG_MX6SX
+   CONFIG_QSPI_MEMMAP_BASE,
+#else
QSPI0_AMBA_BASE,
+#endif
 };
 
 struct fsl_qspi {
@@ -157,8 +169,14 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_PP_4B) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+#ifdef CONFIG_MX6SX
+   /* Use IDATSZ in IPCR to determine the size */
+   qspi_write32(regs-lut[lut_base + 1], OPRND0(0) |
+   PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#else
qspi_write32(regs-lut[lut_base + 1], OPRND0(TX_BUFFER_SIZE) |
PAD0(LUT_PAD1) | INSTR0(LUT_WRITE));
+#endif
qspi_write32(regs-lut[lut_base + 2], 0);
qspi_write32(regs-lut[lut_base + 3], 0);
 
@@ -192,6 +210,12 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
if (bus = ARRAY_SIZE(spi_bases))
return NULL;
 
+#ifdef CONFIG_MX6SX
+   /* cs should be 0 - (FSL_QSPI_FLASH_NUM - 1) */
+   if (cs = FSL_QSPI_FLASH_NUM)
+   return NULL;
+#endif
+
qspi = spi_alloc_slave(struct fsl_qspi, bus, cs

[U-Boot] [PATCH v2 2/2] imx:mx6sxsabresd add qspi support

2014-09-10 Thread Peng Fan
Configure the pad setting and enable qspi clock to support qspi
flashes access.

This patch has been tested on mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
---

Changelog v2:
 Take Fabio's suggestion, split soc code and board code into two patches.
 This patch needs 'ARM:MX6SX Add QSPI support' patch.

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +
 include/configs/mx6sxsabresd.h  | 14 ++
 2 files changed, 54 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 5eaec1b..f9cad5a 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -272,11 +272,51 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
 }
 
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+   (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+   MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CLE__QSPI2_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA02__QSPI2_B_SCLK   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA05__QSPI2_B_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+   /* Set the iomux */
+   imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ARRAY_SIZE(quadspi_pads));
+
+   /* Set the clock */
+   enable_qspi_clk(1);
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* Address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_FSL_QSPI
+   board_qspi_init();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e..00031ec 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -201,6 +201,20 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_FSL_QSPI_LE
+#define CONFIG_QSPI_BASE   QSPI2_BASE_ADDR
+#define CONFIG_QSPI_MEMMAP_BASEQSPI2_ARB_BASE_ADDR
+#define FSL_QSPI_FLASH_SIZESZ_16M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
 #define CONFIG_ENV_OFFSET  (6 * SZ_64K)
 #define CONFIG_ENV_SIZESZ_8K
 #define CONFIG_ENV_IS_IN_MMC
-- 
1.8.4


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[U-Boot] [PATCH 0/3] imx:mx6: change CONFIG_SYS_FSL_ESDHC_ADDR

2014-09-15 Thread Peng Fan
If board_mmc_init failed and returns with -1, cpu_mmc_init will invoke
fsl_esdhc_mmc_init. fsl_esdhc_mmc_init will use CONFIG_SYS_FSL_ESDHC_ADDR
to initialize SDHCx, so use USDHCx_BASE_ADDR to redefine the config macro.

If not use USDHCx_BASE_ADDR to define CONFIG_SYS_FSL_ESDHC_ADDR,
fsl_esdhc_mmc_init will use wrong base address to initialize SDHCx.

Peng Fan (3):
  imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDR
  imx:mx6qarm2: change CONFIG_SYS_FSL_ESDHC_ADDR
  imx:mx6slevk: change CONFIG_SYS_FSL_ESDHC_ADDR

 include/configs/mx6qarm2.h | 2 +-
 include/configs/mx6slevk.h | 2 +-
 include/configs/mx6sxsabresd.h | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

-- 
1.8.4


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[U-Boot] [PATCH 3/3] imx:mx6slevk: change CONFIG_SYS_FSL_ESDHC_ADDR

2014-09-15 Thread Peng Fan
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC2_BASE_ADDR which is
used in board_mmc_init.

Signed-off-by: Peng Fan peng@freescale.com
---
 include/configs/mx6slevk.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 3d05a64..9a21605 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -38,7 +38,7 @@
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
+#define CONFIG_SYS_FSL_ESDHC_ADDR  USDHC2_BASE_ADDR
 
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
-- 
1.8.4


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[U-Boot] [PATCH 1/3] imx:mx6sxsabresd: change CONFIG_SYS_FSL_ESDHC_ADDR

2014-09-15 Thread Peng Fan
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR which is used
in board_mmc_init.

If board_mmc_init failed, cpu_mmc_init-fsl_esdhc_mmc_init will use
CONFIG_SYS_FSL_ESDHC_ADDR to initialize sdhc. So set this macro to
correct value.

Signed-off-by: Peng Fan peng@freescale.com
---
 include/configs/mx6sxsabresd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e..c36ab23 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -159,7 +159,7 @@
 /* MMC Configuration */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
+#define CONFIG_SYS_FSL_ESDHC_ADDR  USDHC4_BASE_ADDR
 
 #define CONFIG_MMC
 #define CONFIG_CMD_MMC
-- 
1.8.4


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[U-Boot] [PATCH 2/3] imx:mx6qarm2: change CONFIG_SYS_FSL_ESDHC_ADDR

2014-09-15 Thread Peng Fan
Define CONFIG_SYS_FSL_ESDHC_ADDR using USDHC4_BASE_ADDR.

USDHC3 and USDHC4 are both initialized in board_mmc_init. There is
no restriction on USDHC3 addr or USDHC4 addr should be assigned to
CONFIG_SYS_FSL_ESDHC_ADDR. So, just choose USDHC4_BASE_ADDR to avoid
errors when fsl_esdhc_mmc_init is invoked.

Signed-off-by: Peng Fan peng@freescale.com
---
 include/configs/mx6qarm2.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index fd651cf..fc0e284 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -35,7 +35,7 @@
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR  0
+#define CONFIG_SYS_FSL_ESDHC_ADDR  USDHC4_BASE_ADDR
 #define CONFIG_SYS_FSL_USDHC_NUM   2
 
 #define CONFIG_MMC
-- 
1.8.4


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[U-Boot] [PATCH] imx:mx6sxsabresd fix pfuz probe failed

2014-10-30 Thread Peng Fan
The PFUZ probe failed with the following msg:
 wait_for_sr_state: failed sr=81 cr=a0 state=2020
  i2c_init_transfer: failed for chip 0x8 retry=0
  wait_for_sr_state: failed sr=81 cr=a0 state=2020
  i2c_init_transfer: failed for chip 0x8 retry=1
  wait_for_sr_state: failed sr=81 cr=a0 state=2020
  i2c_init_transfer: failed for chip 0x8 retry=2
  i2c_init_transfer: give up i2c_regs=021a
  Can't find PMIC:PFUZE100 

board_early_init_f is too early to call i2c related setting, because
init_func_i2c is called after board_early_init_f being invoked. Thus
move setup_i2c into board_init.

Also PFUZ is connected to I2C bus 0, so change 1 - 0.

Using this patch PFUZ can be correctly probed:
PMIC:  PFUZE100 ID=0x11

Signed-off-by: Peng Fan peng@freescale.com
---
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 68d3718..256ea29 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -243,7 +243,6 @@ int board_phy_config(struct phy_device *phydev)
 int board_early_init_f(void)
 {
setup_iomux_uart();
-   setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
 
/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
@@ -277,6 +276,10 @@ int board_init(void)
/* Address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_SYS_I2C_MXC
+   setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
+#endif
+
return 0;
 }
 
-- 
1.8.4


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Re: [U-Boot] [PATCH] imx:mx6sxsabresd fix pfuz probe failed

2014-10-31 Thread Peng Fan


On 10/31/2014 08:01 PM, Fabio Estevam wrote:
 On Fri, Oct 31, 2014 at 1:08 AM, Peng Fan peng@freescale.com wrote:
 The PFUZ probe failed with the following msg:
  wait_for_sr_state: failed sr=81 cr=a0 state=2020
   i2c_init_transfer: failed for chip 0x8 retry=0
   wait_for_sr_state: failed sr=81 cr=a0 state=2020
   i2c_init_transfer: failed for chip 0x8 retry=1
   wait_for_sr_state: failed sr=81 cr=a0 state=2020
   i2c_init_transfer: failed for chip 0x8 retry=2
   i2c_init_transfer: give up i2c_regs=021a
   Can't find PMIC:PFUZE100 

 board_early_init_f is too early to call i2c related setting, because
 init_func_i2c is called after board_early_init_f being invoked. Thus
 move setup_i2c into board_init.

 Also PFUZ is connected to I2C bus 0, so change 1 - 0.

 Using this patch PFUZ can be correctly probed:
 PMIC:  PFUZE100 ID=0x11

 Signed-off-by: Peng Fan peng@freescale.com
 
 Maybe this is a difference between RevA versus RevB board?

I checked SCH-27962 REV A and SCH-27962 REV B. There is no different to I2C 
part. PMIC is connected to the first I2C bus. You can check page 22.

 
 I have a RevA and PMIC works fine here:
I tried on RevA and RevB. Both can not work.
The following is the msg on RevA:

U-Boot 2014.10-00435-g571bdf1 (Nov 01 2014 - 07:39:47)

CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
Reset cause: POR
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
MMC:   FSL_SDHC: 0
*** Warning - bad CRC, using default environment

In:serial
Out:   serial
Err:   serial
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0x8 retry=0
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0x8 retry=1
wait_for_sr_state: failed sr=81 cr=a0 state=2020
i2c_init_transfer: failed for chip 0x8 retry=2
i2c_init_transfer: give up i2c_regs=021a
Can't find PMIC:PFUZE100
Net:   FEC [PRIME]
Hit any key to stop autoboot:  0

After applying this patch, all is fine. I am not sure whether your board has 
been reworked. But PMIC is connected to the first I2C bus, thus I think 
setup_i2c(0,) is correct, but not setup_i2c(1,xxx). And I think it is too 
early to call setup_i2c in board_early_init_f.

 
 U-Boot 2014.10-rc2-17115-g718b923 (Sep 30 2014 - 14:03:24)
 
 CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
 Reset cause: WDOG
 Board: MX6SX SABRE SDB
 I2C:   ready
 DRAM:  1 GiB
 MMC:   FSL_SDHC: 0
 In:serial
 Out:   serial
 Err:   serial
 PMIC:  PFUZE100 ID=0x10
 Net:   FEC [PRIME]
 Hit any key to stop autoboot:  0
 =
 
 = pmic PFUZE100 dump
 PMIC: PFUZE100
 
 0x00: 0010   0021  0001 003f 0001
 0x08:  007f      0081
 0x10:   003f     
 0x18:    0010    
 0x20: 002b 001b 002b 0008 0044   
 0x28:       002b 001b
 0x30: 002b 0008 0044   0072 0072 0072
 0x38: 0008 0054   0026 0026 0026 0008
 0x40: 0064   0026 0026 0026 0008 0064
 0x48:   0038 0038 0038 0008 0074 
 0x50:        
 0x58:        
 0x60:        
 0x68:   0010 0006 0018 000e 001a 0010
 0x70: 001f 001c      
 0x78:       
 =
 
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[U-Boot] [PATCH 1/5] imx:mx6sxsabresd add usb support

2014-10-31 Thread Peng Fan
Add usb support for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 29 +
 include/configs/mx6sxsabresd.h  | 14 ++
 2 files changed, 43 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 256ea29..016b8e8 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -296,3 +296,32 @@ int checkboard(void)
 
return 0;
 }
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+   MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+   MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+   switch (port) {
+   case 0:
+   imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
+ARRAY_SIZE(usb_otg1_pads));
+   break;
+   case 1:
+   imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+ARRAY_SIZE(usb_otg2_pads));
+   break;
+   default:
+   printf(MXC USB port %d not yet supported\n, port);
+   return 1;
+   }
+   return 0;
+}
+#endif
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index e02ea18..8edf187 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,20 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
 #define CONFIG_CMD_PCI
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI
-- 
1.8.4.5

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[U-Boot] [PATCH 4/5] imx:mx6qarm2 add usb support

2014-10-31 Thread Peng Fan
Add usb support for mx6qarm2 board.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
 board/freescale/mx6qarm2/mx6qarm2.c | 27 +++
 include/configs/mx6qarm2.h  | 14 ++
 2 files changed, 41 insertions(+)

diff --git a/board/freescale/mx6qarm2/mx6qarm2.c 
b/board/freescale/mx6qarm2/mx6qarm2.c
index 667dca5..3108750 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -237,3 +237,30 @@ int checkboard(void)
 
return 0;
 }
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_otg_pads[] = {
+   MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+   switch (port) {
+   case 0:
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+
+   /*
+* set daisy chain for otg_pin_id on 6q.
+* for 6dl, this bit is reserved
+*/
+   mxc_iomux_set_gpr_register(1, 13, 1, 1);
+   break;
+   default:
+   printf(MXC USB port %d not yet supported\n, port);
+   return 1;
+   }
+   return 0;
+}
+#endif
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 6e01fa0..76cfef1 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -189,4 +189,18 @@
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.8.4.5

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[U-Boot] [PATCH 2/5] imx:mx6slevk add usb support

2014-10-31 Thread Peng Fan
Add usb support for mx6slevk board.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
 board/freescale/mx6slevk/mx6slevk.c | 29 +
 include/configs/mx6slevk.h  | 14 ++
 2 files changed, 43 insertions(+)

diff --git a/board/freescale/mx6slevk/mx6slevk.c 
b/board/freescale/mx6slevk/mx6slevk.c
index a500133..6d972e8 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -182,3 +182,32 @@ int checkboard(void)
 
return 0;
 }
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+   switch (port) {
+   case 0:
+   imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
+ARRAY_SIZE(usb_otg1_pads));
+   break;
+   case 1:
+   imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+ARRAY_SIZE(usb_otg2_pads));
+   break;
+   default:
+   printf(MXC USB port %d not yet supported\n, port);
+   return 1;
+   }
+   return 0;
+}
+#endif
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index fddedf1..021dc0e 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -210,4 +210,18 @@
 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
 #endif
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.8.4.5

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[U-Boot] [PATCH 5/5] imx:mx6sabresd add usb support

2014-10-31 Thread Peng Fan
Add usb support for mx6sabresd.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
 board/freescale/mx6sabresd/mx6sabresd.c | 53 +
 include/configs/mx6sabresd.h| 14 +
 2 files changed, 67 insertions(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index 81dcd6e..6bf9b25 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -546,3 +546,56 @@ int checkboard(void)
puts(Board: MX6-SabreSD\n);
return 0;
 }
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_otg_pads[] = {
+   MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const usb_hc1_pads[] = {
+   MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+   switch (port) {
+   case 0:
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+
+   /*
+* set daisy chain for otg_pin_id on 6q.
+* for 6dl, this bit is reserved.
+*/
+   mxc_iomux_set_gpr_register(1, 13, 1, 0);
+   break;
+   case 1:
+   imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+ARRAY_SIZE(usb_hc1_pads));
+   break;
+   default:
+   printf(MXC USB port %d not yet supported\n, port);
+   return 1;
+   }
+   return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+   switch (port) {
+   case 0:
+   break;
+   case 1:
+   if (on)
+   gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+   else
+   gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+   break;
+   default:
+   printf(MXC USB port %d not yet supported\n, port);
+   return 1;
+   }
+   return 0;
+}
+#endif
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 938030d..da870f3 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -54,4 +54,18 @@
 #define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1 /* Enabled USB controller 
number */
+#endif
+
 #endif /* __MX6QSABRESD_CONFIG_H */
-- 
1.8.4.5

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[U-Boot] [PATCH 0/5] add usb support for mx6 board

2014-10-31 Thread Peng Fan
Add usb support for mx6qarm2 mx6sabresd mx6sxsabresd mx6slevk. Mainly add
pad settings and ehci power settings. Also introduce a new function to
set IOMUXC GPR registers, because mx6sabresd usb needs that function to work.

This patch set only contains board related settings for usb and a new gpr
function. ehci_hcd_init and otg power polarity in ehci-mx6.c are not touched.
Thus usb start can not work fine. As this is new feature support, post
this patch set for review first.

In future patch, related patch that maybe bugfix to make `usb start` fine
will be sent out. 

Peng Fan (5):
  imx:mx6sxsabresd add usb support
  imx:mx6slevk add usb support
  arm:imx-common introduce a new function to set gpr
  imx:mx6qarm2 add usb support
  imx:mx6sabresd add usb support

 arch/arm/imx-common/iomux-v3.c  | 25 ++
 board/freescale/mx6qarm2/mx6qarm2.c | 27 +++
 board/freescale/mx6sabresd/mx6sabresd.c | 53 +
 board/freescale/mx6slevk/mx6slevk.c | 29 
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 29 
 include/configs/mx6qarm2.h  | 14 
 include/configs/mx6sabresd.h| 14 
 include/configs/mx6slevk.h  | 14 
 include/configs/mx6sxsabresd.h  | 14 
 9 files changed, 219 insertions(+)

-- 
1.8.4.5

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[U-Boot] [PATCH 3/5] arm:imx-common introduce a new function to set gpr

2014-10-31 Thread Peng Fan
Add a new function mxc_iomux_set_gpr_register to
set the iomux gpr register.

32-bit general purpose registers according to SoC
requirements for any usage.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
 arch/arm/imx-common/iomux-v3.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 22cd11a..b27aab8 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -77,3 +77,28 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const 
*pad_list,
p += stride;
}
 }
+
+/*
+ * Configure the IOMUX General Purpose Registers.
+ *
+ * @group, which gpr register to configure.
+ * @start_bit, the first bit to set
+ * @num_bits, how many bits to set
+ * @value, the value will be set to [start_bits...start_bits+num_bits-1]
+ */
+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,
+   int value)
+{
+   int i = 0;
+   u32 reg;
+
+   reg = readl(base + group * 4);
+   while (num_bits) {
+   reg = ~(1  (start_bit + i));
+   i++;
+   num_bits--;
+   }
+
+   reg |= (value  start_bit);
+   writel(reg, base + group * 4);
+}
-- 
1.8.4.5

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[U-Boot] [PATCH 2/2] arm:imx-common add function prototype for gpr set

2014-10-31 Thread Peng Fan
This patch arm:imx-common introduce a new function to set gpr
missed to add the function prototype.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/include/asm/imx-common/iomux-v3.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h 
b/arch/arm/include/asm/imx-common/iomux-v3.h
index a8ca49c..23421b5 100644
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -182,6 +182,9 @@ typedef u64 iomux_v3_cfg_t;
 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 unsigned count);
+/* Set bits for general purpose registers */
+void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,
+   int value);
 
 /* macros for declaring and using pinmux array */
 #if defined(CONFIG_MX6QDL)
-- 
1.8.4.5

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[U-Boot] [PATCH 1/2] imx:mx6sl_pins add pad settings for usb

2014-10-31 Thread Peng Fan
Add pad settings for usb support.

This patch imx:mx6slevk add usb support missed to add pad
definition.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..17b4798 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT= 
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19= 
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21   = 
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID  = 
IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR   = 
IOMUX_PAD(0x0484, 0x017C, 6, 0x, 0, 0),
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR   = 
IOMUX_PAD(0x0488, 0x0180, 6, 0x, 0, 0),
 };
 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
-- 
1.8.4.5

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[U-Boot] [RFC PATCH v1 0/2] kgdb:add breakpoint and arm support

2014-10-31 Thread Peng Fan
There were patches about this part before, such as
http://lists.denx.de/pipermail/u-boot/2010-April/069592.html
https://www.mail-archive.com/u-boot@lists.denx.de/msg13464.html
And I reference that piece of code.

I have verified this patch set on freescale mx6sxsabresd revb board.
Because the board related kgdb serial code is not fine for patch review,
I just sent out the common code for review.

I am not sure whether this patch set will break other platform's kgdb support
or not, so request for comment.


Peng Fan (2):
  kgdb: add breakpoint support
  arm:kgdb add KGDB support for arm platform

 arch/arm/include/asm/proc-armv/ptrace.h |   2 +-
 arch/arm/include/asm/signal.h   |   1 +
 arch/arm/lib/Makefile   |   3 +
 arch/arm/lib/crt0.S |   4 +
 arch/arm/lib/interrupts.c   |  24 +++
 arch/arm/lib/kgdb/kgdb.c| 231 +++
 arch/arm/lib/kgdb/setjmp.S  |  20 +++
 arch/arm/lib/vectors.S  |  28 
 common/kgdb.c   | 273 
 include/kgdb.h  |  35 
 10 files changed, 620 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/include/asm/signal.h
 create mode 100644 arch/arm/lib/kgdb/kgdb.c
 create mode 100644 arch/arm/lib/kgdb/setjmp.S

-- 
1.8.4.5

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[U-Boot] [RFC PATCH v1 2/2] arm:kgdb add KGDB support for arm platform

2014-10-31 Thread Peng Fan
The register save/restore:
Use get_bad_stack and bad_save_user_regs to save regs.
Introduce und_restore_regs to restore the previous regs before
trigger a breakpoint.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/include/asm/proc-armv/ptrace.h |   2 +-
 arch/arm/include/asm/signal.h   |   1 +
 arch/arm/lib/Makefile   |   3 +
 arch/arm/lib/crt0.S |   4 +
 arch/arm/lib/interrupts.c   |  24 
 arch/arm/lib/kgdb/kgdb.c| 231 
 arch/arm/lib/kgdb/setjmp.S  |  20 +++
 arch/arm/lib/vectors.S  |  28 
 8 files changed, 312 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/proc-armv/ptrace.h 
b/arch/arm/include/asm/proc-armv/ptrace.h
index 71df5a9..33fe587 100644
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -58,7 +58,7 @@ struct pt_regs {
stack during a system call. */
 
 struct pt_regs {
-   long uregs[18];
+   unsigned long uregs[18];
 };
 
 #define ARM_cpsr   uregs[16]
diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h
new file mode 100644
index 000..7b1573c
--- /dev/null
+++ b/arch/arm/include/asm/signal.h
@@ -0,0 +1 @@
+#include asm-generic/signal.h
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 1ef2400..c543563 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -52,3 +52,6 @@ endif
 ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
 extra-y+= eabi_compat.o
 endif
+
+obj-$(CONFIG_CMD_KGDB) += kgdb/setjmp.o
+obj-$(CONFIG_CMD_KGDB) += kgdb/kgdb.o
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 29cdad0..d96e70b 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -99,9 +99,13 @@ clr_gd:
sub r9, r9, #GD_SIZE/* new GD is below bd */
 
adr lr, here
+#ifndef CONFIG_CMD_KGDB
ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd-reloc_off */
add lr, lr, r0
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+#else
+  ldr r0, =__image_copy_start
+#endif
b   relocate_code
 here:
 
diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 4dacfd9..d16bd58 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -22,6 +22,7 @@
 #include common.h
 #include asm/proc-armv/ptrace.h
 #include asm/u-boot-arm.h
+#include kgdb.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -160,9 +161,32 @@ void show_regs (struct pt_regs *regs)
 
 void do_undefined_instruction (struct pt_regs *pt_regs)
 {
+#if defined(CONFIG_CMD_KGDB)
+   unsigned long *tmp_pc = NULL;
+
+   pt_regs-ARM_pc -= 4;
+   tmp_pc = (unsigned long *)pt_regs-ARM_pc;
+
+   if (*tmp_pc == 0xe7ffdeff) {
+   pt_regs-ARM_pc += 4;
+   if (debugger_exception_handler 
+   debugger_exception_handler(pt_regs)) {
+   return;
+   }
+   } else if (*tmp_pc == 0xe7ffdefe) {
+   if (debugger_exception_handler 
+   debugger_exception_handler(pt_regs)) {
+   return;
+   }
+   } else {
+   printf(DCache/ICACHE May need flush\n);
+   return;
+   }
+#else
printf (undefined instruction\n);
show_regs (pt_regs);
bad_mode ();
+#endif
 }
 
 void do_software_interrupt (struct pt_regs *pt_regs)
diff --git a/arch/arm/lib/kgdb/kgdb.c b/arch/arm/lib/kgdb/kgdb.c
new file mode 100644
index 000..6b2e542
--- /dev/null
+++ b/arch/arm/lib/kgdb/kgdb.c
@@ -0,0 +1,231 @@
+#include common.h
+#include command.h
+#include kgdb.h
+#include asm/signal.h
+#include asm/processor.h
+
+#define KGDB_ARM_GP_REGS   16
+#define KGDB_ARM_FP_REGS   8
+#define KGDB_ARM_EXTRA_REGS2
+#define KGDB_ARM_MAX_REGS  (KGDB_ARM_GP_REGS +\
+(KGDB_ARM_FP_REGS * 3) +\
+ KGDB_ARM_EXTRA_REGS)
+#define KGDB_NUMREGBYTES   (KGDB_ARM_MAX_REGS  2)
+
+enum arm_regs {
+   KGDB_ARM_R0,
+   KGDB_ARM_R1,
+   KGDB_ARM_R2,
+   KGDB_ARM_R3,
+   KGDB_ARM_R4,
+   KGDB_ARM_R5,
+   KGDB_ARM_R6,
+   KGDB_ARM_R7,
+   KGDB_ARM_R8,
+   KGDB_ARM_R9,
+   KGDB_ARM_R10,
+   KGDB_ARM_FP,
+   KGDB_ARM_IP,
+   KGDB_ARM_SP,
+   KGDB_ARM_LR,
+   KGDB_ARM_PC,
+   KGDB_ARM_CPSR = KGDB_ARM_MAX_REGS - 1
+};
+
+void kgdb_enter(struct pt_regs *regs, kgdb_data *kdp)
+{
+   disable_interrupts();
+
+   kdp-sigval = kgdb_trap(regs);
+   kdp-nregs = 2;
+   kdp-regs[0].num = KGDB_ARM_PC;
+   kdp-regs[0].val = regs-ARM_pc;
+
+   kdp-regs[1].num = KGDB_ARM_SP;
+   kdp-regs[1].val = regs-ARM_sp;
+
+   return;
+}
+
+void kgdb_exit(struct pt_regs *regs, kgdb_data *kdp)
+{
+   /* Mark Not sure ??? */
+
+   if (kdp-extype  KGDBEXIT_WITHADDR

[U-Boot] [RFC PATCH v1 1/2] kgdb: add breakpoint support

2014-10-31 Thread Peng Fan
Add Z/z protocal support for breakpoint set/remove.

Signed-off-by: Peng Fan peng@freescale.com
---
 common/kgdb.c  | 273 +
 include/kgdb.h |  35 
 2 files changed, 308 insertions(+)

diff --git a/common/kgdb.c b/common/kgdb.c
index d357463..fd83ccd 100644
--- a/common/kgdb.c
+++ b/common/kgdb.c
@@ -92,6 +92,8 @@
 #include kgdb.h
 #include command.h
 
+#include asm-generic/errno.h
+
 #undef KGDB_DEBUG
 
 /*
@@ -111,6 +113,17 @@ static int longjmp_on_fault = 0;
 static int kdebug = 1;
 #endif
 
+struct kgdb_bkpt kgdb_break[KGDB_MAX_BREAKPOINTS] = {
+   [0 ... KGDB_MAX_BREAKPOINTS-1] = { .state = BP_UNDEFINED }
+};
+
+#ifdef CONFIG_ARM
+unsigned char gdb_bpt_instr[4] = {0xfe, 0xde, 0xff, 0xe7};
+#else
+#error Please implement gdb_bpt_instr!
+#endif
+
+
 static const char hexchars[]=0123456789abcdef;
 
 /* Convert ch from a hex digit to an int */
@@ -309,6 +322,200 @@ putpacket(unsigned char *buffer)
} while ((recv  0x7f) != '+');
 }
 
+int kgdb_validate_break_address(unsigned addr)
+{
+   /* Need More */
+   return 0;
+}
+
+static int probe_kernel_read(unsigned char *dst, void *src, size_t size)
+{
+   int i;
+   unsigned char *dst_ptr = dst;
+   unsigned char *src_ptr = src;
+
+   for (i = 0; i  size; i++)
+   *dst_ptr++ = *src_ptr++;
+
+   return 0;
+}
+
+static int probe_kernel_write(char *dst, void *src, size_t size)
+{
+   int i;
+   char *dst_ptr = dst;
+   char *src_ptr = src;
+
+   for (i = 0; i  size; i++)
+   *dst_ptr++ = *src_ptr++;
+
+   return 0;
+}
+
+__weak int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
+{
+   int err;
+
+   err = probe_kernel_read(bpt-saved_instr, (char *)bpt-bpt_addr,
+   BREAK_INSTR_SIZE);
+   if (err)
+   return err;
+
+   err = probe_kernel_write((char *)bpt-bpt_addr, gdb_bpt_instr,
+BREAK_INSTR_SIZE);
+
+   return err;
+}
+
+/*
+ * Set the breakpoints whose state is BP_SET to BP_ACTIVE
+ */
+int kgdb_active_sw_breakpoints(void)
+{
+   int err;
+   int ret = 0;
+   int i;
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   if (kgdb_break[i].state != BP_SET)
+   continue;
+
+   err = kgdb_arch_set_breakpoint(kgdb_break[i]);
+   if (err) {
+   ret = err;
+   printf(KGDB: BP install failed: %lx\n,
+  kgdb_break[i].bpt_addr);
+   continue;
+   }
+
+   kgdb_break[i].state = BP_ACTIVE;
+
+   /*
+* kgdb_arch_set_breakpoint touched dcache and memory.
+* cache should be flushed to let icache can see the updated
+* inst.
+*/
+   /* flush work is done in do_exit */
+   kgdb_flush_cache_all();
+   }
+
+   return ret;
+}
+
+/*
+ * Set state from BP_SET to BP_REMOVED
+ */
+int kgdb_remove_sw_breakpoint(unsigned int addr)
+{
+   int i;
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   if ((kgdb_break[i].state == BP_SET) 
+   (kgdb_break[i].bpt_addr == addr)) {
+   kgdb_break[i].state = BP_REMOVED;
+   return 0;
+   }
+   }
+
+   return -ENOENT;
+}
+
+int kgdb_set_sw_breakpoint(unsigned int addr)
+{
+   int err = kgdb_validate_break_address(addr);
+   int breakno = -1;
+   int i;
+
+   if (err)
+   return err;
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   if ((kgdb_break[i].state == BP_SET) 
+   (kgdb_break[i].bpt_addr == addr))
+   return -EEXIST;
+   }
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   /* removed or unused, use it */
+   if ((kgdb_break[i].state == BP_REMOVED) ||
+   (kgdb_break[i].state == BP_UNDEFINED)) {
+   breakno = i;
+   break;
+   }
+   }
+
+   if (breakno == -1)
+   return -E2BIG;
+
+   kgdb_break[breakno].state = BP_SET;
+   kgdb_break[breakno].type = BP_BREAKPOINT;
+   kgdb_break[breakno].bpt_addr = addr;
+
+   return 0;
+}
+
+__weak int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
+{
+   return probe_kernel_write((char *)bpt-bpt_addr,
+ (char *)bpt-saved_instr, BREAK_INSTR_SIZE);
+}
+
+/*
+ * set breakpoints whose state is BP_ACTIVE to BP_SET
+ */
+int kgdb_deactivate_sw_breakpoints(void)
+{
+   int err;
+   int ret = 0;
+   int i;
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   if (kgdb_break[i].state != BP_ACTIVE)
+   continue;
+
+   err = kgdb_arch_remove_breakpoint(kgdb_break[i

Re: [U-Boot] [PATCH 3/5] arm:imx-common introduce a new function to set gpr

2014-11-01 Thread Peng Fan


On 11/01/2014 03:39 PM, Li Ye-B37916 wrote:
 Hi Peng,
 
  
 
 On 11/1/2014 10:19 AM, Peng Fan wrote:
 Add a new function mxc_iomux_set_gpr_register to
 set the iomux gpr register.

 32-bit general purpose registers according to SoC
 requirements for any usage.

 Signed-off-by: Peng Fan peng@freescale.com
 Signed-off-by: Ye.Li b37...@freescale.com
 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 ---
  arch/arm/imx-common/iomux-v3.c | 25 +
  1 file changed, 25 insertions(+)

 diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
 index 22cd11a..b27aab8 100644
 --- a/arch/arm/imx-common/iomux-v3.c
 +++ b/arch/arm/imx-common/iomux-v3.c
 @@ -77,3 +77,28 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t 
 const *pad_list,
  p += stride;
  }
  }
 +
 +/*
 + * Configure the IOMUX General Purpose Registers.
 + *
 + * @group, which gpr register to configure.
 + * @start_bit, the first bit to set
 + * @num_bits, how many bits to set
 + * @value, the value will be set to [start_bits...start_bits+num_bits-1]
 + */
 +void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits,
 +int value)
 +{
 +int i = 0;
 +u32 reg;
 +
 +reg = readl(base + group * 4);
 +while (num_bits) {
 +reg = ~(1  (start_bit + i));
 +i++;
 +num_bits--;
 +}
 +
 +reg |= (value  start_bit);
 +writel(reg, base + group * 4);
 +}
 This function is already in my previous patch 
 (http://patchwork.ozlabs.org/patch/405013/). The function name is changed to 
 imx_iomux_set_gpr_register. 
 

oh. I missed this piece of code.
Then please ignore this patch set. Sorry for troubles.

Regards,
Peng.
  
 
 Best regards,
 
 Ye Li
 
 
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Re: [U-Boot] [PATCH 1/5] imx:mx6sxsabresd add usb support

2014-11-03 Thread Peng Fan


Hi,

在 11/3/2014 8:28 PM, Stefano Babic 写道:

Hi Peng,

On 01/11/2014 03:19, Peng Fan wrote:

Add usb support for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 29 +
  include/configs/mx6sxsabresd.h  | 14 ++
  2 files changed, 43 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 256ea29..016b8e8 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -296,3 +296,32 @@ int checkboard(void)

return 0;
  }
+
+#ifdef CONFIG_USB_EHCI_MX6
+iomux_v3_cfg_t const usb_otg1_pads[] = {
+   MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+iomux_v3_cfg_t const usb_otg2_pads[] = {
+   MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_ehci_hcd_init(int port)
+{
+   switch (port) {
+   case 0:
+   imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
+ARRAY_SIZE(usb_otg1_pads));
+   break;
+   case 1:
+   imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
+ARRAY_SIZE(usb_otg2_pads));
+   break;
+   default:
+   printf(MXC USB port %d not yet supported\n, port);
+   return 1;
+   }
+   return 0;
+}
+#endif


Frankly, I am expecting that this function power up the bus instead of
pin multiplexing. If the pins are reserved for USB, why should we set
the pinmux each time board_ehci_hcd_init() is called ? And, in any case,
pins are not reset after their usage for USB. You can move this setup in
board_init() or in another init function.


Because otg power problem which is pointed out by Ye Li, I'll do power 
enable/disable in board_ehci_power function and move the pin settings to 
board_init.

And sent patch v2.

Thanks,
Peng.


Best regards,
Stefano Babic


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[U-Boot] [PATCH v2 0/3] imx:mx6 add usb support

2014-11-03 Thread Peng Fan
Changes v2:
 - move pinmux setting into board_init
 - add otg polarity setting in board_ehci_hcd_init
 - Introduce a new weak function to give board a choice to decide the work mode
   of the otg port, since a otg port can also work in host mode without
   touch ID pin.

Peng Fan (3):
  usb:ehci-mx6 add board_ehci_usb_mode function
  imx:mx6sxsabresd add usb support
  imx:mx6slevk add usb support

 arch/arm/include/asm/arch-mx6/mx6sl_pins.h  |  5 +++
 board/freescale/mx6slevk/mx6slevk.c | 51 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 51 +
 drivers/usb/host/ehci-mx6.c |  7 
 include/configs/mx6slevk.h  | 14 
 include/configs/mx6sxsabresd.h  | 14 
 6 files changed, 142 insertions(+)

-- 
1.8.4.5

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[U-Boot] [PATCH v2 1/3] usb:ehci-mx6 add board_ehci_usb_mode function

2014-11-03 Thread Peng Fan
Include a weak function board_ehci_usb_mode to gives board code
a choice. If the board want the otg port work in host mode but not
device mode, this should be handled.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v2:
 Introduce a new weak function to let board have a choice to decide which mode
 to work at. 

 drivers/usb/host/ehci-mx6.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 9ec5a0a..3662a80 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -193,6 +193,11 @@ static void usb_oc_config(int index)
__raw_writel(val, ctrl);
 }
 
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+
 int __weak board_ehci_hcd_init(int port)
 {
return 0;
@@ -223,6 +228,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_internal_phy_clock_gate(index, 1);
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
 
+   board_ehci_usb_mode(index, type);
+
*hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
-- 
1.8.4.5

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[U-Boot] [PATCH v2 3/3] imx:mx6slevk add usb support

2014-11-03 Thread Peng Fan
Add usb support for mx6slevk board.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v2:
 Add otg polarity setting
 move pinmux into board_init

 arch/arm/include/asm/arch-mx6/mx6sl_pins.h |  5 +++
 board/freescale/mx6slevk/mx6slevk.c| 51 ++
 include/configs/mx6slevk.h | 14 
 3 files changed, 70 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..17b4798 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT= 
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19= 
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21   = 
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID  = 
IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR   = 
IOMUX_PAD(0x0484, 0x017C, 6, 0x, 0, 0),
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR   = 
IOMUX_PAD(0x0488, 0x0180, 6, 0x, 0, 0),
 };
 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c 
b/board/freescale/mx6slevk/mx6slevk.c
index a500133..360599e 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -20,6 +20,7 @@
 #include fsl_esdhc.h
 #include mmc.h
 #include netdev.h
+#include usb.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -150,6 +151,51 @@ static int setup_fec(void)
 }
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL  (1  9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   /* OTG1 */
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* OTG2 */
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_ehci_usb_mode(int port, enum usb_init_type *type)
+{
+   if (port != 1)
+   return -EINVAL;
+
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port != 1)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   /* Set Power polarity */
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+#endif
 
 int board_early_init_f(void)
 {
@@ -168,6 +214,11 @@ int board_init(void)
 #ifdef CONFIG_FEC_MXC
setup_fec();
 #endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index fddedf1..021dc0e 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -210,4 +210,18 @@
 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
 #endif
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.8.4.5

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[U-Boot] [PATCH v2 2/3] imx:mx6sxsabresd add usb support

2014-11-03 Thread Peng Fan
Add usb support for mx6sxsabresd board.

There are two usb port on mx6sxsabresd board:
1. OTG
2. OTG
The second port is actually an otg port with a USB A type interface on
the board.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v2:
 Add otg polarity setting
 Move pinmux setting into board_init

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 51 +
 include/configs/mx6sxsabresd.h  | 14 
 2 files changed, 65 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 256ea29..81619bd 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -25,6 +25,7 @@
 #include netdev.h
 #include power/pmic.h
 #include power/pfuze100_pmic.h
+#include usb.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -271,6 +272,52 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL  (1  9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   /* OGT1 */
+   MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* OTG2 */
+   MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_ehci_usb_mode(int port, enum usb_init_type *type)
+{
+   if (port != 1)
+   return -EINVAL;
+
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port != 1)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   /* Set Power polarity */
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* Address of boot parameters */
@@ -280,6 +327,10 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index e02ea18..8edf187 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,20 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
 #define CONFIG_CMD_PCI
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI
-- 
1.8.4.5

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Re: [U-Boot] [PATCH v2 1/3] usb:ehci-mx6 add board_ehci_usb_mode function

2014-11-04 Thread Peng Fan



在 11/4/2014 6:33 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 08:50:00 AM, Peng Fan wrote:

Include a weak function board_ehci_usb_mode to gives board code
a choice.


What choice?


If the board want the otg port work in host mode but not
device mode, this should be handled.


How?

Also, isn't usb_phy_enable() supposed to do exactly this kind of selection
between device and host mode ?


In mx6sxsabresd board, there are two usb port, one used for otg, the 
other used for host. However they are connected to SOC USB controller 
otg1 core and otg2 core respectively. Like following:


OTG1 CORE  board otg port
OTG2 CORE  board host port

However the board do not have ID pin set for board host port. If just 
use usb_phy_enable, the board host port will not work, because
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST; 
will always set type with USB_INIT_DEVICE.


Because i did not find way to handle this situation in 
board/freescale/mx6sxsabresd/mx6sxsabresd.c, add this function to let 
board level code handle handle 'type', if board level code want to set 
it's own 'type'.





Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v2:
  Introduce a new weak function to let board have a choice to decide which
mode to work at.

  drivers/usb/host/ehci-mx6.c | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 9ec5a0a..3662a80 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -193,6 +193,11 @@ static void usb_oc_config(int index)
__raw_writel(val, ctrl);
  }

+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+
  int __weak board_ehci_hcd_init(int port)
  {
return 0;
@@ -223,6 +228,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_internal_phy_clock_gate(index, 1);
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;

+   board_ehci_usb_mode(index, type);
+
*hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));


Best regards,
Marek Vasut


Regards,
Peng.
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Re: [U-Boot] [PATCH v2 0/3] imx:mx6 add usb support

2014-11-04 Thread Peng Fan



在 11/4/2014 6:31 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 08:49:59 AM, Peng Fan wrote:

So uh, what exactly does this patchset do ? It's not clear at all from the
subject and any description is completely missing.

To my knowledge, i.MX6 already does have USB support in U-Boot, so the subject
is misleading as well.
mx6sxsasbresd board and mx6slevk board does not have board level support 
for usb. This patchset is mainly to add pinmux and implement 
board_ehci_hcd_init and board_echi_power and add USB CONFIG in header 
file to make usb work fine.


I'll send another patch for review, if usb:ehci-mx6 add 
board_ehci_usb_mode function is fine.



Changes v2:
  - move pinmux setting into board_init
  - add otg polarity setting in board_ehci_hcd_init
  - Introduce a new weak function to give board a choice to decide the work
mode of the otg port, since a otg port can also work in host mode without
touch ID pin.

Peng Fan (3):
   usb:ehci-mx6 add board_ehci_usb_mode function
   imx:mx6sxsabresd add usb support
   imx:mx6slevk add usb support

  arch/arm/include/asm/arch-mx6/mx6sl_pins.h  |  5 +++
  board/freescale/mx6slevk/mx6slevk.c | 51
+ board/freescale/mx6sxsabresd/mx6sxsabresd.c
| 51 + drivers/usb/host/ehci-mx6.c
 |  7 
  include/configs/mx6slevk.h  | 14 
  include/configs/mx6sxsabresd.h  | 14 
  6 files changed, 142 insertions(+)


Best regards,
Marek Vasut


Regards,
Peng.
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Re: [U-Boot] [RFC PATCH v1 1/2] kgdb: add breakpoint support

2014-11-04 Thread Peng Fan

Hi Simon,

在 11/4/2014 2:46 PM, Simon Glass 写道:

Hi Peng,

On 31 October 2014 23:12, Peng Fan peng@freescale.com wrote:

Add Z/z protocal support for breakpoint set/remove.

Signed-off-by: Peng Fan peng@freescale.com


This looks good to me - I just have a few bits below.


---
  common/kgdb.c  | 273 +
  include/kgdb.h |  35 
  2 files changed, 308 insertions(+)

diff --git a/common/kgdb.c b/common/kgdb.c
index d357463..fd83ccd 100644
--- a/common/kgdb.c
+++ b/common/kgdb.c
@@ -92,6 +92,8 @@
  #include kgdb.h
  #include command.h

+#include asm-generic/errno.h


#include errno.h would do

Ok.



+
  #undef KGDB_DEBUG


Where is this used?


You mean KGDB_DEBUG?


  /*
@@ -111,6 +113,17 @@ static int longjmp_on_fault = 0;
  static int kdebug = 1;
  #endif

+struct kgdb_bkpt kgdb_break[KGDB_MAX_BREAKPOINTS] = {
+   [0 ... KGDB_MAX_BREAKPOINTS-1] = { .state = BP_UNDEFINED }
+};
+
+#ifdef CONFIG_ARM
+unsigned char gdb_bpt_instr[4] = {0xfe, 0xde, 0xff, 0xe7};
+#else
+#error Please implement gdb_bpt_instr!
+#endif
+
+
  static const char hexchars[]=0123456789abcdef;

  /* Convert ch from a hex digit to an int */
@@ -309,6 +322,200 @@ putpacket(unsigned char *buffer)
 } while ((recv  0x7f) != '+');
  }

+int kgdb_validate_break_address(unsigned addr)
+{
+   /* Need More */


?
I'll remove the comment. Actually i just want to validate whether the 
add parameter is fine or not using this function.



+   return 0;
+}
+
+static int probe_kernel_read(unsigned char *dst, void *src, size_t size)
+{
+   int i;
+   unsigned char *dst_ptr = dst;
+   unsigned char *src_ptr = src;
+
+   for (i = 0; i  size; i++)
+   *dst_ptr++ = *src_ptr++;
+
+   return 0;
+}
+
+static int probe_kernel_write(char *dst, void *src, size_t size)


These two above are strange function names - why 'kernel' - what does
it mean in this context? Also could you must use memcpy(), either in
the functions or instead of them?
Ok. memcpy is better. I just use the function name in linux kernel, 
maybe misleading here. how about probe_mem_read?



+{
+   int i;
+   char *dst_ptr = dst;
+   char *src_ptr = src;
+
+   for (i = 0; i  size; i++)
+   *dst_ptr++ = *src_ptr++;
+
+   return 0;
+}
+
+__weak int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
+{
+   int err;
+
+   err = probe_kernel_read(bpt-saved_instr, (char *)bpt-bpt_addr,
+   BREAK_INSTR_SIZE);
+   if (err)
+   return err;
+
+   err = probe_kernel_write((char *)bpt-bpt_addr, gdb_bpt_instr,
+BREAK_INSTR_SIZE);
+
+   return err;
+}
+
+/*
+ * Set the breakpoints whose state is BP_SET to BP_ACTIVE
+ */
+int kgdb_active_sw_breakpoints(void)
+{
+   int err;
+   int ret = 0;
+   int i;
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   if (kgdb_break[i].state != BP_SET)
+   continue;
+
+   err = kgdb_arch_set_breakpoint(kgdb_break[i]);
+   if (err) {
+   ret = err;
+   printf(KGDB: BP install failed: %lx\n,
+  kgdb_break[i].bpt_addr);
+   continue;
+   }
+
+   kgdb_break[i].state = BP_ACTIVE;
+
+   /*
+* kgdb_arch_set_breakpoint touched dcache and memory.
+* cache should be flushed to let icache can see the updated
+* inst.


instruction


+*/
+   /* flush work is done in do_exit */
+   kgdb_flush_cache_all();
+   }
+
+   return ret;
+}
+
+/*
+ * Set state from BP_SET to BP_REMOVED
+ */
+int kgdb_remove_sw_breakpoint(unsigned int addr)
+{
+   int i;
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   if ((kgdb_break[i].state == BP_SET) 
+   (kgdb_break[i].bpt_addr == addr)) {
+   kgdb_break[i].state = BP_REMOVED;
+   return 0;
+   }
+   }
+
+   return -ENOENT;
+}
+
+int kgdb_set_sw_breakpoint(unsigned int addr)
+{
+   int err = kgdb_validate_break_address(addr);
+   int breakno = -1;
+   int i;
+
+   if (err)
+   return err;
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   if ((kgdb_break[i].state == BP_SET) 
+   (kgdb_break[i].bpt_addr == addr))
+   return -EEXIST;
+   }
+
+   for (i = 0; i  KGDB_MAX_BREAKPOINTS; i++) {
+   /* removed or unused, use it */
+   if ((kgdb_break[i].state == BP_REMOVED) ||
+   (kgdb_break[i].state == BP_UNDEFINED)) {
+   breakno = i;
+   break;
+   }
+   }
+
+   if (breakno == -1)
+   return -E2BIG;
+
+   kgdb_break[breakno].state

Re: [U-Boot] [RFC PATCH v1 2/2] arm:kgdb add KGDB support for arm platform

2014-11-04 Thread Peng Fan

Hi Simon,

在 11/4/2014 2:58 PM, Simon Glass 写道:

HI Peng,

On 31 October 2014 23:12, Peng Fan peng@freescale.com wrote:

The register save/restore:
Use get_bad_stack and bad_save_user_regs to save regs.
Introduce und_restore_regs to restore the previous regs before
trigger a breakpoint.

Signed-off-by: Peng Fan peng@freescale.com


Looks good so far as I understand it. A few nits below and maybe you
can integrate better with the ptrace register numbering.


---
  arch/arm/include/asm/proc-armv/ptrace.h |   2 +-
  arch/arm/include/asm/signal.h   |   1 +
  arch/arm/lib/Makefile   |   3 +
  arch/arm/lib/crt0.S |   4 +
  arch/arm/lib/interrupts.c   |  24 
  arch/arm/lib/kgdb/kgdb.c| 231 
  arch/arm/lib/kgdb/setjmp.S  |  20 +++
  arch/arm/lib/vectors.S  |  28 
  8 files changed, 312 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/proc-armv/ptrace.h 
b/arch/arm/include/asm/proc-armv/ptrace.h
index 71df5a9..33fe587 100644
--- a/arch/arm/include/asm/proc-armv/ptrace.h
+++ b/arch/arm/include/asm/proc-armv/ptrace.h
@@ -58,7 +58,7 @@ struct pt_regs {
 stack during a system call. */

  struct pt_regs {
-   long uregs[18];
+   unsigned long uregs[18];
  };

  #define ARM_cpsr   uregs[16]
diff --git a/arch/arm/include/asm/signal.h b/arch/arm/include/asm/signal.h
new file mode 100644
index 000..7b1573c
--- /dev/null
+++ b/arch/arm/include/asm/signal.h
@@ -0,0 +1 @@
+#include asm-generic/signal.h
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 1ef2400..c543563 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -52,3 +52,6 @@ endif
  ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
  extra-y+= eabi_compat.o
  endif
+
+obj-$(CONFIG_CMD_KGDB) += kgdb/setjmp.o
+obj-$(CONFIG_CMD_KGDB) += kgdb/kgdb.o
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 29cdad0..d96e70b 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -99,9 +99,13 @@ clr_gd:
 sub r9, r9, #GD_SIZE/* new GD is below bd */

 adr lr, here
+#ifndef CONFIG_CMD_KGDB
 ldr r0, [r9, #GD_RELOC_OFF] /* r0 = gd-reloc_off */
 add lr, lr, r0
 ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd-relocaddr */
+#else
+  ldr r0, =__image_copy_start
+#endif
 b   relocate_code
  here:

diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c
index 4dacfd9..d16bd58 100644
--- a/arch/arm/lib/interrupts.c
+++ b/arch/arm/lib/interrupts.c
@@ -22,6 +22,7 @@
  #include common.h
  #include asm/proc-armv/ptrace.h
  #include asm/u-boot-arm.h
+#include kgdb.h

  DECLARE_GLOBAL_DATA_PTR;

@@ -160,9 +161,32 @@ void show_regs (struct pt_regs *regs)

  void do_undefined_instruction (struct pt_regs *pt_regs)
  {
+#if defined(CONFIG_CMD_KGDB)
+   unsigned long *tmp_pc = NULL;
+
+   pt_regs-ARM_pc -= 4;
+   tmp_pc = (unsigned long *)pt_regs-ARM_pc;
+
+   if (*tmp_pc == 0xe7ffdeff) {
+   pt_regs-ARM_pc += 4;
+   if (debugger_exception_handler 
+   debugger_exception_handler(pt_regs)) {
+   return;
+   }
+   } else if (*tmp_pc == 0xe7ffdefe) {
+   if (debugger_exception_handler 
+   debugger_exception_handler(pt_regs)) {
+   return;
+   }
+   } else {
+   printf(DCache/ICACHE May need flush\n);
+   return;
+   }
+#else
 printf (undefined instruction\n);
 show_regs (pt_regs);
 bad_mode ();
+#endif
  }

  void do_software_interrupt (struct pt_regs *pt_regs)
diff --git a/arch/arm/lib/kgdb/kgdb.c b/arch/arm/lib/kgdb/kgdb.c
new file mode 100644
index 000..6b2e542
--- /dev/null
+++ b/arch/arm/lib/kgdb/kgdb.c
@@ -0,0 +1,231 @@
+#include common.h
+#include command.h
+#include kgdb.h
+#include asm/signal.h
+#include asm/processor.h
+
+#define KGDB_ARM_GP_REGS   16
+#define KGDB_ARM_FP_REGS   8
+#define KGDB_ARM_EXTRA_REGS2
+#define KGDB_ARM_MAX_REGS  (KGDB_ARM_GP_REGS +\
+(KGDB_ARM_FP_REGS * 3) +\
+ KGDB_ARM_EXTRA_REGS)
+#define KGDB_NUMREGBYTES   (KGDB_ARM_MAX_REGS  2)
+
+enum arm_regs {
+   KGDB_ARM_R0,
+   KGDB_ARM_R1,
+   KGDB_ARM_R2,
+   KGDB_ARM_R3,
+   KGDB_ARM_R4,
+   KGDB_ARM_R5,
+   KGDB_ARM_R6,
+   KGDB_ARM_R7,
+   KGDB_ARM_R8,
+   KGDB_ARM_R9,
+   KGDB_ARM_R10,
+   KGDB_ARM_FP,
+   KGDB_ARM_IP,
+   KGDB_ARM_SP,
+   KGDB_ARM_LR,
+   KGDB_ARM_PC,


So in here there are the FP and EXTRA regs? If you added them to this
enum it would be clearer.
I did not test FP and other extra regs. Actually in uboot, the FP and 
extra regs are used? I am not sure.


Also these mirror the numbers in ptrace.h so I

Re: [U-Boot] [PATCH v2 1/3] usb:ehci-mx6 add board_ehci_usb_mode function

2014-11-04 Thread Peng Fan


Hi Marek,

在 11/4/2014 7:01 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 11:50:29 AM, Peng Fan wrote:

在 11/4/2014 6:33 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 08:50:00 AM, Peng Fan wrote:

Include a weak function board_ehci_usb_mode to gives board code
a choice.


What choice?


If the board want the otg port work in host mode but not
device mode, this should be handled.


How?

Also, isn't usb_phy_enable() supposed to do exactly this kind of
selection between device and host mode ?


In mx6sxsabresd board, there are two usb port, one used for otg, the
other used for host. However they are connected to SOC USB controller
otg1 core and otg2 core respectively. Like following:

OTG1 CORE  board otg port
OTG2 CORE  board host port

However the board do not have ID pin set for board host port. If just
use usb_phy_enable, the board host port will not work, because
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
will always set type with USB_INIT_DEVICE.

Because i did not find way to handle this situation in
board/freescale/mx6sxsabresd/mx6sxsabresd.c, add this function to let
board level code handle handle 'type', if board level code want to set
it's own 'type'.


This part in usb_phy_enable()

163 return val  USBPHY_CTRL_OTG_ID;

should be replaced by some kind of a board-specific callback then, with
default implmentation being the above (reading the phy ctrl register).



How about using the following piece of code?
in ehci-mx6.c

unsigned int __weak board_usb_phy_mode(int index, unsigned int val)
{
return val  USBPHY_CTRL_OTG_ID;
}

replace return val  USBPHY_CTRL_OTG_ID; using 
return board_usb_phy_mode(index, val);

In board file,
unsigned int board_usb_phy_mode(int index, unsigned int val)
{
if (index == 1)
return 0; /* HOST */
else
return 1; /* DEVICE */
}


Best regards,
Marek Vasut


Regards,
Peng.
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Re: [U-Boot] [PATCH v2 1/3] usb:ehci-mx6 add board_ehci_usb_mode function

2014-11-04 Thread Peng Fan


Hi Jeroen,

在 11/4/2014 7:40 PM, Jeroen Hofstee 写道:

Hello Peng,

On 04-11-14 08:50, Peng Fan wrote:

Include a weak function board_ehci_usb_mode to gives board code
a choice. If the board want the otg port work in host mode but not
device mode, this should be handled.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v2:
   Introduce a new weak function to let board have a choice to decide which mode
   to work at.

   drivers/usb/host/ehci-mx6.c | 7 +++
   1 file changed, 7 insertions(+)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 9ec5a0a..3662a80 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -193,6 +193,11 @@ static void usb_oc_config(int index)
__raw_writel(val, ctrl);
   }

+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+
   int __weak board_ehci_hcd_init(int port)
   {
return 0;
@@ -223,6 +228,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_internal_phy_clock_gate(index, 1);
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;

+   board_ehci_usb_mode(index, type);
+
*hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));


Can you add a prototype type as well and make sure it is included?
I did not find a good place for the prototype type. I think ehci.h is 
not fine to include this prototype. Any suggestions?


Thanks,
Jeroen


Regards,
Peng.
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Re: [U-Boot] [PATCH v2 1/3] usb:ehci-mx6 add board_ehci_usb_mode function

2014-11-04 Thread Peng Fan



在 11/5/2014 1:33 AM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 02:29:56 PM, Peng Fan wrote:

Hi Marek,

在 11/4/2014 7:01 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 11:50:29 AM, Peng Fan wrote:

在 11/4/2014 6:33 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 08:50:00 AM, Peng Fan wrote:

Include a weak function board_ehci_usb_mode to gives board code
a choice.


What choice?


If the board want the otg port work in host mode but not
device mode, this should be handled.


How?

Also, isn't usb_phy_enable() supposed to do exactly this kind of
selection between device and host mode ?


In mx6sxsabresd board, there are two usb port, one used for otg, the
other used for host. However they are connected to SOC USB controller
otg1 core and otg2 core respectively. Like following:

OTG1 CORE  board otg port
OTG2 CORE  board host port

However the board do not have ID pin set for board host port. If just
use usb_phy_enable, the board host port will not work, because
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
will always set type with USB_INIT_DEVICE.

Because i did not find way to handle this situation in
board/freescale/mx6sxsabresd/mx6sxsabresd.c, add this function to let
board level code handle handle 'type', if board level code want to set
it's own 'type'.


This part in usb_phy_enable()

163 return val  USBPHY_CTRL_OTG_ID;

should be replaced by some kind of a board-specific callback then, with
default implmentation being the above (reading the phy ctrl register).


How about using the following piece of code?
in ehci-mx6.c

unsigned int __weak board_usb_phy_mode(int index, unsigned int val)
{
return val  USBPHY_CTRL_OTG_ID;
}

replace return val  USBPHY_CTRL_OTG_ID; using 
return board_usb_phy_mode(index, val);

In board file,
unsigned int board_usb_phy_mode(int index, unsigned int val)


Why not pass in full struct usb_ehci * instead ? Passing some ad-hoc $val into
the function doesn't seem like a scalable future-proof solution.
[...]


Passing struct usb_ehci * to board code seems exports ehci register 
definition to board layer. How about just use
int board_usb_phy_mode(int index) without using 'val' or 'struct 
usb_ehci *ehci'.



Best regards,
Marek Vasut


Regards,
Peng.
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Re: [U-Boot] [PATCH v2 1/3] usb:ehci-mx6 add board_ehci_usb_mode function

2014-11-05 Thread Peng Fan



在 11/5/2014 5:03 PM, Marek Vasut 写道:

On Wednesday, November 05, 2014 at 07:00:32 AM, Peng Fan wrote:

在 11/5/2014 1:33 AM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 02:29:56 PM, Peng Fan wrote:

Hi Marek,

在 11/4/2014 7:01 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 11:50:29 AM, Peng Fan wrote:

在 11/4/2014 6:33 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 08:50:00 AM, Peng Fan wrote:

Include a weak function board_ehci_usb_mode to gives board code
a choice.


What choice?


If the board want the otg port work in host mode but not
device mode, this should be handled.


How?

Also, isn't usb_phy_enable() supposed to do exactly this kind of
selection between device and host mode ?


In mx6sxsabresd board, there are two usb port, one used for otg, the
other used for host. However they are connected to SOC USB controller
otg1 core and otg2 core respectively. Like following:

OTG1 CORE  board otg port
OTG2 CORE  board host port

However the board do not have ID pin set for board host port. If just
use usb_phy_enable, the board host port will not work, because
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST; will always set type with USB_INIT_DEVICE.

Because i did not find way to handle this situation in
board/freescale/mx6sxsabresd/mx6sxsabresd.c, add this function to let
board level code handle handle 'type', if board level code want to set
it's own 'type'.


This part in usb_phy_enable()

163 return val  USBPHY_CTRL_OTG_ID;

should be replaced by some kind of a board-specific callback then, with
default implmentation being the above (reading the phy ctrl register).


How about using the following piece of code?
in ehci-mx6.c

unsigned int __weak board_usb_phy_mode(int index, unsigned int val)
{

return val  USBPHY_CTRL_OTG_ID;

}

replace return val  USBPHY_CTRL_OTG_ID; using 
return board_usb_phy_mode(index, val);

In board file,
unsigned int board_usb_phy_mode(int index, unsigned int val)


Why not pass in full struct usb_ehci * instead ? Passing some ad-hoc $val
into the function doesn't seem like a scalable future-proof solution.
[...]


Passing struct usb_ehci * to board code seems exports ehci register
definition to board layer.


Yeah.


How about just use
int board_usb_phy_mode(int index) without using 'val' or 'struct
usb_ehci *ehci'.


The board part might need to read the EHCI registers though. How would the
board part be able to do it if you didn't pass the *ehci in ?
To imx6, the ID bit is in PHY ctrl reg 'USBPHYx_CTRLn', also the phy 
regs definition are not included in struct usb_ehci. I just think 
expose the ehci register to board layer is not fine and 
board_usb_phy_mode does not need this. I define this just as 
board_ehci_hcd_init and board_ehci_power. Their prototype are

int __weak board_ehci_hcd_init(int port);
int __weak board_ehci_power(int port, int on);

My implementation is the following:

replace return val  USBPHY_CTRL_OTG_ID; using return 
board_usb_phy_mode(index); in usb_phy_enable


In drivers/usb/host/ehci-mx6.c:
116 int __weak board_usb_phy_mode(int index)
117 {
118 void __iomem *phy_reg;
119 void __iomem *phy_ctrl;
120 u32 val;
121
122 phy_reg = (void __iomem *)phy_bases[index];
123 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
124
125 val = __raw_readl(phy_ctrl);
126
127 return val  USBPHY_CTRL_OTG_ID;
128 }

In board/freescale/mx6sxsabresd/mx6sxsabresd.c:
295 int board_usb_phy_mode(int port)
296 {
297 void __iomem *phy_reg;
298 void __iomem *phy_ctrl;
299 u32 val;
300
301 switch (port) {
302 case 0:
303 phy_reg = (void __iomem *)USB_PHY0_BASE_ADDR;
304 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
305 val = __raw_readl(phy_ctrl);
306 return val  USBPHY_CTRL_OTG_ID;
307 case 1:
308 /* Work in HOST mode. */
309 return 0;
310 }
311
312 /* suppress warning msg */
313 return 0;
314 }

Is this piece of code fine?



Regards,
Peng.
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[U-Boot] [PATCH v3 3/3] imx:mx6slevk add board level support for usb

2014-11-06 Thread Peng Fan
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return 0 to let
ehci-mx6.c driver decide otg2 core to works in host mode.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v3:
 implement board_usb_phy_mode
Changes v2:
 Add otg polarity setting
 move pinmux into board_init
 set pinmux setting static

 arch/arm/include/asm/arch-mx6/mx6sl_pins.h |  5 +++
 board/freescale/mx6slevk/mx6slevk.c| 63 ++
 include/configs/mx6slevk.h | 14 +++
 3 files changed, 82 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index 045ccc4..17b4798 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -34,5 +34,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT= 
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19= 
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21   = 
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID  = 
IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR   = 
IOMUX_PAD(0x0484, 0x017C, 6, 0x, 0, 0),
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR   = 
IOMUX_PAD(0x0488, 0x0180, 6, 0x, 0, 0),
 };
 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c 
b/board/freescale/mx6slevk/mx6slevk.c
index a500133..e9ec77e 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -20,6 +20,7 @@
 #include fsl_esdhc.h
 #include mmc.h
 #include netdev.h
+#include usb.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -150,6 +151,63 @@ static int setup_fec(void)
 }
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define USBPHY_CTRL0x30
+#define UCTRL_PWR_POL  (1  9)
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   /* OTG1 */
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* OTG2 */
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   switch (port) {
+   case 0:
+   phy_reg = (void __iomem *)USB_PHY0_BASE_ADDR;
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+   val = __raw_readl(phy_ctrl);
+   return val  USBPHY_CTRL_OTG_ID;
+   case 1:
+   /* Work in HOST mode. */
+   return 0;
+   }
+
+   /* suppress warning msg */
+   return 0;
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port  1)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   /* Set Power polarity */
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+#endif
 
 int board_early_init_f(void)
 {
@@ -168,6 +226,11 @@ int board_init(void)
 #ifdef CONFIG_FEC_MXC
setup_fec();
 #endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index fddedf1..021dc0e 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -210,4 +210,18 @@
 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
 #endif
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.8.4.5

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[U-Boot] [PATCH v3 2/3] imx:mx6sxsabresd add board level support for usb

2014-11-06 Thread Peng Fan
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6sxsabresd board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return 0 to let
ehci-mx6.c driver decide otg2 core to works in host mode.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v3:
 implement board_usb_phy_mode
Changes v2:
 Add otg polarity setting
 Move pinmux setting into board_init
 set pinmux setting struct static

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 63 +
 include/configs/mx6sxsabresd.h  | 14 +++
 2 files changed, 77 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 256ea29..5fe58f6 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -25,6 +25,7 @@
 #include netdev.h
 #include power/pmic.h
 #include power/pfuze100_pmic.h
+#include usb.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -271,6 +272,64 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define USBPHY_CTRL0x30
+#define UCTRL_PWR_POL  (1  9)
+#define USBPHY_CTRL_OTG_ID 0x0800
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   /* OGT1 */
+   MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* OTG2 */
+   MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   switch (port) {
+   case 0:
+   phy_reg = (void __iomem *)USB_PHY0_BASE_ADDR;
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+   val = __raw_readl(phy_ctrl);
+   return val  USBPHY_CTRL_OTG_ID;
+   case 1:
+   /* Work in HOST mode. */
+   return 0;
+   }
+
+   /* suppress warning msg */
+   return 0;
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port  1)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   /* Set Power polarity */
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* Address of boot parameters */
@@ -280,6 +339,10 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index e02ea18..8edf187 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,20 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
 #define CONFIG_CMD_PCI
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI
-- 
1.8.4.5

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[U-Boot] [PATCH v3 0/3] Add board level usb supporrt for mxsxsabresd and mx6slevk

2014-11-06 Thread Peng Fan
This patch set is mainly to add board level usb support for mx6sxsabresd and
mx6slevk. Add pin mux settings and implement board_ehci_hcd_init and board_usb
_phy_mode.

Also in order to make the host port work for these two boards. A new weak
function is introduced. Detailed info about this is in the usb:ehci-mx6
add board_usb_phy_mode function patch commit log.

This patch set has already been tested on mx6sxsabresd and mx6slevk board.

Changes v3:
 Take Marek's suggestions, replace 'return val  USBPHY_CTRL_OTG_ID' with
 this new function like 'return board_usb_phy_mode(index);'
 Detailed discussion here:
 http://lists.denx.de/pipermail/u-boot/2014-November/194131.html

Changes v2:
 Introduce a new weak function to let board have a choice to decide which mode
 to work at. 
 move pinmux setting into board_init
 add otg polarity setting in board_ehci_hcd_init
 set pinmux struct static

Peng Fan (3):
  usb:ehci-mx6 add board_usb_phy_mode function
  imx:mx6sxsabresd add board level support for usb
  imx:mx6slevk add board level support for usb

 arch/arm/include/asm/arch-mx6/mx6sl_pins.h  |  5 +++
 board/freescale/mx6slevk/mx6slevk.c | 63 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 63 +
 drivers/usb/host/ehci-mx6.c | 16 +++-
 include/configs/mx6slevk.h  | 14 +++
 include/configs/mx6sxsabresd.h  | 14 +++
 6 files changed, 174 insertions(+), 1 deletion(-)

-- 
1.8.4.5

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[U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

2014-11-06 Thread Peng Fan
Include a weak function board_usb_phy_mode.

usb_phy_enable decide whether the controller in device mode or in host mode by
'*phy_ctrl  USBPHY_CTRL_OTG_ID'.

There are two usb port on mx6sxsabresd and also mx6slevk.
1. OTG port
2. HOST port
There are connected to SOC USB controller OTG1 core and OTG2 core as following:
OTG1 core  board OTG port
OTG2 core  board HOST port

However to these two board, no ID pin for the board host port. If only use
'*phy_ctrl  USBPHY_CTRL_OTG_ID' to decide the work mode, the host port will
not work, because type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST; will always set 'type' with USB_INIT_DEVICE.

So introduce this weak function to let board level code can decide to work
in host or device mode, if board level code want to implement this function.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v3:
 Take Marek's suggestions, replace 'return val  USBPHY_CTRL_OTG_ID' with
 this new function like 'return board_usb_phy_mode(index);'
 Here board_usb_phy_mode only has one parameter 'index' as board_ehci_power and
 board_echi_hcd_init do.
 http://lists.denx.de/pipermail/u-boot/2014-November/194183.html; has detailed
 discussion.

Changes v2:
 Introduce a new weak function to let board have a choice to decide which mode
 to work at. 

 drivers/usb/host/ehci-mx6.c | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 9ec5a0a..e2a247e 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -113,6 +113,20 @@ static void usb_power_config(int index)
 pll_480_ctrl_set);
 }
 
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val  USBPHY_CTRL_OTG_ID;
+}
+
 /* Return 0 : host node, 0 : device mode */
 static int usb_phy_enable(int index, struct usb_ehci *ehci)
 {
@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(val, phy_ctrl);
 
-   return val  USBPHY_CTRL_OTG_ID;
+   return board_usb_phy_mode(index);
 }
 
 /* Base address for this IP block is 0x02184800 */
-- 
1.8.4.5

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Re: [U-Boot] [PATCH v2 1/3] usb:ehci-mx6 add board_ehci_usb_mode function

2014-11-06 Thread Peng Fan



在 11/7/2014 4:20 AM, Marek Vasut 写道:

On Wednesday, November 05, 2014 at 10:18:25 AM, Peng Fan wrote:

在 11/5/2014 5:03 PM, Marek Vasut 写道:

On Wednesday, November 05, 2014 at 07:00:32 AM, Peng Fan wrote:

在 11/5/2014 1:33 AM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 02:29:56 PM, Peng Fan wrote:

Hi Marek,

在 11/4/2014 7:01 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 11:50:29 AM, Peng Fan wrote:

在 11/4/2014 6:33 PM, Marek Vasut 写道:

On Tuesday, November 04, 2014 at 08:50:00 AM, Peng Fan wrote:

Include a weak function board_ehci_usb_mode to gives board code
a choice.


What choice?


If the board want the otg port work in host mode but not
device mode, this should be handled.


How?

Also, isn't usb_phy_enable() supposed to do exactly this kind of
selection between device and host mode ?


In mx6sxsabresd board, there are two usb port, one used for otg, the
other used for host. However they are connected to SOC USB
controller otg1 core and otg2 core respectively. Like following:

OTG1 CORE  board otg port
OTG2 CORE  board host port

However the board do not have ID pin set for board host port. If
just use usb_phy_enable, the board host port will not work, because
type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST; will always set type with USB_INIT_DEVICE.

Because i did not find way to handle this situation in
board/freescale/mx6sxsabresd/mx6sxsabresd.c, add this function to
let board level code handle handle 'type', if board level code want
to set it's own 'type'.


This part in usb_phy_enable()

163 return val  USBPHY_CTRL_OTG_ID;

should be replaced by some kind of a board-specific callback then,
with default implmentation being the above (reading the phy ctrl
register).


How about using the following piece of code?
in ehci-mx6.c

unsigned int __weak board_usb_phy_mode(int index, unsigned int val)
{

return val  USBPHY_CTRL_OTG_ID;

}

replace return val  USBPHY_CTRL_OTG_ID; using 
return board_usb_phy_mode(index, val);

In board file,
unsigned int board_usb_phy_mode(int index, unsigned int val)


Why not pass in full struct usb_ehci * instead ? Passing some ad-hoc
$val into the function doesn't seem like a scalable future-proof
solution. [...]


Passing struct usb_ehci * to board code seems exports ehci register
definition to board layer.


Yeah.


How about just use
int board_usb_phy_mode(int index) without using 'val' or 'struct
usb_ehci *ehci'.


The board part might need to read the EHCI registers though. How would
the board part be able to do it if you didn't pass the *ehci in ?


To imx6, the ID bit is in PHY ctrl reg 'USBPHYx_CTRLn', also the phy
regs definition are not included in struct usb_ehci. I just think
expose the ehci register to board layer is not fine and
board_usb_phy_mode does not need this. I define this just as
board_ehci_hcd_init and board_ehci_power. Their prototype are
int __weak board_ehci_hcd_init(int port);
int __weak board_ehci_power(int port, int on);

My implementation is the following:

replace return val  USBPHY_CTRL_OTG_ID; using return
board_usb_phy_mode(index); in usb_phy_enable

In drivers/usb/host/ehci-mx6.c:
116 int __weak board_usb_phy_mode(int index)
117 {
118 void __iomem *phy_reg;
119 void __iomem *phy_ctrl;
120 u32 val;
121
122 phy_reg = (void __iomem *)phy_bases[index];
123 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
124
125 val = __raw_readl(phy_ctrl);
126
127 return val  USBPHY_CTRL_OTG_ID;
128 }

In board/freescale/mx6sxsabresd/mx6sxsabresd.c:
295 int board_usb_phy_mode(int port)
296 {
297 void __iomem *phy_reg;
298 void __iomem *phy_ctrl;
299 u32 val;
300
301 switch (port) {
302 case 0:
303 phy_reg = (void __iomem *)USB_PHY0_BASE_ADDR;
304 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
305 val = __raw_readl(phy_ctrl);
306 return val  USBPHY_CTRL_OTG_ID;
307 case 1:
308 /* Work in HOST mode. */
309 return 0;
310 }
311
312 /* suppress warning msg */
313 return 0;
314 }

Is this piece of code fine?


These ad-hoc hooks are starting to become absolute horror, but I guess
this one (if properly documented) might just work. Let's see what will
come out of this approach.


Sent out v3 patch set just now. Please review.

Thanks,
Peng.
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

2014-11-07 Thread Peng Fan



在 11/7/2014 4:25 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 02:08:12 AM, Peng Fan wrote:

Include a weak function board_usb_phy_mode.

usb_phy_enable decide whether the controller in device mode or in host mode
by '*phy_ctrl  USBPHY_CTRL_OTG_ID'.

There are two usb port on mx6sxsabresd and also mx6slevk.
1. OTG port
2. HOST port
There are connected to SOC USB controller OTG1 core and OTG2 core as
following: OTG1 core  board OTG port
OTG2 core  board HOST port


This patch has nothing to do with any board, so this part should not
be in the commit message.


However to these two board, no ID pin for the board host port. If only use
'*phy_ctrl  USBPHY_CTRL_OTG_ID' to decide the work mode, the host port
will not work, because type = usb_phy_enable(index, ehci) ?
USB_INIT_DEVICE : USB_INIT_HOST; will always set 'type' with
USB_INIT_DEVICE.

So introduce this weak function to let board level code can decide to work
in host or device mode, if board level code want to implement this
function.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v3:
  Take Marek's suggestions, replace 'return val  USBPHY_CTRL_OTG_ID' with
  this new function like 'return board_usb_phy_mode(index);'
  Here board_usb_phy_mode only has one parameter 'index' as board_ehci_power
and board_echi_hcd_init do.
  http://lists.denx.de/pipermail/u-boot/2014-November/194183.html; has
detailed discussion.

Changes v2:
  Introduce a new weak function to let board have a choice to decide which
mode to work at.

  drivers/usb/host/ehci-mx6.c | 16 +++-
  1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 9ec5a0a..e2a247e 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -113,6 +113,20 @@ static void usb_power_config(int index)
 pll_480_ctrl_set);
  }

+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val  USBPHY_CTRL_OTG_ID;
+}
+
  /* Return 0 : host node, 0 : device mode */
  static int usb_phy_enable(int index, struct usb_ehci *ehci)
  {
@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct usb_ehci
*ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(val, phy_ctrl);

-   return val  USBPHY_CTRL_OTG_ID;
+   return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after usb_phy_enable().
Afterall, the mode detection has nothing to do with the PHY enabling.

This back to what I did in patch v2. right after usb_phy_enable(), just 
paste that piece of code here:


The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : 
USB_INIT_HOST;


+   board_usb_phy_mode(index, type);
+

What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+   if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent 
this patch set.

btw. an idea for a separate patch(set) -- the PHY registers should be
converted to struct-based access.

Yeah, struct based access PHY register should be done. After this board 
level usb support patch is finished.

  }

  /* Base address for this IP block is 0x02184800 */

Regards,
Peng.
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Re: [U-Boot] [PATCH v3 3/3] imx:mx6slevk add board level support for usb

2014-11-07 Thread Peng Fan



在 11/7/2014 4:26 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 02:08:14 AM, Peng Fan wrote:

Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return 0 to let
ehci-mx6.c driver decide otg2 core to works in host mode.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---


[...]


@@ -150,6 +151,63 @@ static int setup_fec(void)
  }
  #endif

+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define USBPHY_CTRL0x30
+#define UCTRL_PWR_POL  (1  9)
+#define USBPHY_CTRL_OTG_ID 0x0800


This looks like an duplication. Aren't those bits defined somewhere in
generic code already ?
If this way 'int board_usb_phy_mode(int port, enum usb_init_type *type)' 
can be accpeted, these bits are not needed and I'll move these bits in 
the seperate PHY register struct access patch. Anyway, after the board 
level usb support patch.

[...]
Best regards,
Marek Vasut


Regards,
Peng.
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

2014-11-07 Thread Peng Fan



在 11/7/2014 7:09 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:

[...]


@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct usb_ehci
*ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);

__raw_writel(val, phy_ctrl);

-   return val  USBPHY_CTRL_OTG_ID;
+   return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after usb_phy_enable().
Afterall, the mode detection has nothing to do with the PHY enabling.


This back to what I did in patch v2. right after usb_phy_enable(), just
paste that piece of code here:

The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

  type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;

+   board_usb_phy_mode(index, type);
+


The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.


ok. got it.

What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+   if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.


It should really explicitly set it, not modify it, see above.


I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : 
USB_INIT_HOST; with usb_phy_enable(index, ehci).
3. right after usb_phy_enable, add this line type = 
board_usb_phy_mode(index) or type = board_usb_phy_mode((struct usb_phy 
*)PHY_ADDRESS). Here I also think pass phy register definition to board 
level code is not fine just as what we talked about passing ehci struct 
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function int __weak 
board_usb_phy_mode(xxx), and it's return value is the mode, HOST or 
DEVICE. If the board code want to implement this function, just return 
what the board want.


After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val  USBPHY_CTRL_OTG_ID;
+}
+

- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);

in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+   if (port == 1)
+   return USB_INIT_HOST;
+   else
+   return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register 
in board code.


Any ideas?

[...]


Regards,
Peng.
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Re: [U-Boot] [PATCH v3 3/3] imx:mx6slevk add board level support for usb

2014-11-07 Thread Peng Fan



在 11/7/2014 7:10 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:08:03 PM, Peng Fan wrote:

在 11/7/2014 4:26 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 02:08:14 AM, Peng Fan wrote:

Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return 0 to let
ehci-mx6.c driver decide otg2 core to works in host mode.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---


[...]


@@ -150,6 +151,63 @@ static int setup_fec(void)

   }
   #endif

+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define USBPHY_CTRL0x30
+#define UCTRL_PWR_POL  (1  9)
+#define USBPHY_CTRL_OTG_ID 0x0800


This looks like an duplication. Aren't those bits defined somewhere in
generic code already ?


If this way 'int board_usb_phy_mode(int port, enum usb_init_type *type)'
can be accpeted, these bits are not needed and I'll move these bits in
the seperate PHY register struct access patch. Anyway, after the board
level usb support patch.


What about abstracting that stuff into a function which returns the PHY's
idea of the current mode instead. That way, you can determine the PHY's
idea of the mode from both board code and the driver code.

struct phy register is good, but I prefer not to include this in board 
level code, see my reply in this patch usb:ehci-mx6 add 
board_usb_phy_mode function just as board_ehci_power and 
board_ehci_hcd_init do. I think it is good to make it a seperate patch.

Best regards,
Marek Vasut


Regards,
Peng.
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

2014-11-07 Thread Peng Fan



在 11/7/2014 8:17 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:

在 11/7/2014 7:09 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:

[...]


@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct
usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 |
USBPHY_CTRL_ENUTMILEVEL3);

__raw_writel(val, phy_ctrl);

-   return val  USBPHY_CTRL_OTG_ID;
+   return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after
usb_phy_enable(). Afterall, the mode detection has nothing to do with
the PHY enabling.


This back to what I did in patch v2. right after usb_phy_enable(), just
paste that piece of code here:

The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;

+   board_usb_phy_mode(index, type);
+


The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.


ok. got it.


What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+   if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.


It should really explicitly set it, not modify it, see above.


I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST; with usb_phy_enable(index, ehci).
3. right after usb_phy_enable, add this line type =
board_usb_phy_mode(index) or type = board_usb_phy_mode((struct usb_phy
*)PHY_ADDRESS). Here I also think pass phy register definition to board
level code is not fine just as what we talked about passing ehci struct
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function int __weak
board_usb_phy_mode(xxx), and it's return value is the mode, HOST or
DEVICE. If the board code want to implement this function, just return
what the board want.

After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val  USBPHY_CTRL_OTG_ID;
+}
+

- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);

in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+   if (port == 1)
+   return USB_INIT_HOST;
+   else
+   return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register
in board code.

Any ideas?


This seems OKish for all but the part where usb_phy_enable() shouldn't be
touched. The return value of usb_phy_enable() should really be a regular
return code, not the PHY mode.


ok. I'll fix this.

You can also still implement a function to query a PHY for it's mode, so you
don't need to explicitly read the USBPHY_CTRL_OTG_ID in the board code.



I am not sure whether this following way is fine or not.
+int board_usb_phy_mode(int index)
+   __attribute__((weak, alias(usb_phy_mode)));
+
in usb_phy_mode, query a PHY for it's mode.

And righter after usb_phy_enable in ehci-mx6.c.
-   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : 
USB_INIT_HOST;

+   usb_phy_enable(index, ehci);
+   type = usb_phy_mode(index);

usb_phy_enable return 0 but not return val  USBPHY_CTRL_OTG_ID. There 
is no status bit for query enabled or not, so just return 0.


In board file:
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return usb_phy_mode(port);
}

I think this is better way then previous patch, but i did not find where 
to put the usb_phy_mode prototype type, since board file will use it.


Regards,
Peng.
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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

2014-11-07 Thread Peng Fan



在 11/8/2014 12:07 PM, Peng Fan 写道:



在 11/7/2014 8:17 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:

在 11/7/2014 7:09 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:

[...]


@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct
usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 |
USBPHY_CTRL_ENUTMILEVEL3);

__raw_writel(val, phy_ctrl);

-return val  USBPHY_CTRL_OTG_ID;
+return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after
usb_phy_enable(). Afterall, the mode detection has nothing to do with
the PHY enabling.


This back to what I did in patch v2. right after usb_phy_enable(),
just
paste that piece of code here:

The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;

+   board_usb_phy_mode(index, type);
+


The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.


ok. got it.


What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.


It should really explicitly set it, not modify it, see above.


I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST; with usb_phy_enable(index, ehci).
3. right after usb_phy_enable, add this line type =
board_usb_phy_mode(index) or type = board_usb_phy_mode((struct usb_phy
*)PHY_ADDRESS). Here I also think pass phy register definition to board
level code is not fine just as what we talked about passing ehci struct
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function int __weak
board_usb_phy_mode(xxx), and it's return value is the mode, HOST or
DEVICE. If the board code want to implement this function, just return
what the board want.

After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val  USBPHY_CTRL_OTG_ID;
+}
+

- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);

in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+if (port == 1)
+return USB_INIT_HOST;
+else
+return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register
in board code.

Any ideas?


This seems OKish for all but the part where usb_phy_enable() shouldn't be
touched. The return value of usb_phy_enable() should really be a regular
return code, not the PHY mode.


ok. I'll fix this.

You can also still implement a function to query a PHY for it's mode,
so you
don't need to explicitly read the USBPHY_CTRL_OTG_ID in the board code.



I am not sure whether this following way is fine or not.
+int board_usb_phy_mode(int index)
+   __attribute__((weak, alias(usb_phy_mode)));
+
in usb_phy_mode, query a PHY for it's mode.

And righter after usb_phy_enable in ehci-mx6.c.
-   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;
+   usb_phy_enable(index, ehci);
+   type = usb_phy_mode(index);

This should be 'type = board_usb_phy_mode(index);'


usb_phy_enable return 0 but not return val  USBPHY_CTRL_OTG_ID. There
is no status bit for query enabled or not, so just return 0.

In board file:
int board_usb_phy_mode(int port)
{
 if (port == 1)
 return USB_INIT_HOST;
 else
 return usb_phy_mode(port);
}

I think this is better way then previous patch, but i did not find where
to put the usb_phy_mode prototype type, since board file will use it.

Regards,
Peng.

Regards,
Peng.
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[U-Boot] [PATCH v4 0/3] Add board level usb support for mxsxsabresd and mx6slevk

2014-11-09 Thread Peng Fan
Changes v4:
 - Take Marek's suggestions, implement usb_phy_mode function and
 introduce a weak function board_usb_phy_mode.
 - change usb_phy_enable's return value with 0.
 - reimplement board_usb_phy_mode in board code.
 - add prototype type for board_usb_phy_mode and usb_phy_mode

Changes v3:
 - Take Marek's suggestions, replace 'return val  USBPHY_CTRL_OTG_ID' with
 this new function like 'return board_usb_phy_mode(index);'
 Detailed discussion here:
 http://lists.denx.de/pipermail/u-boot/2014-November/194131.html

Changes v2:
 - Introduce a new weak function to let board have a choice to decide which mode
 to work at. 
 - move pinmux setting into board_init
 - add otg polarity setting in board_ehci_hcd_init
 - set pinmux struct static

Peng Fan (3):
  usb:ehci-mx6 add phy mode query function
  imx:mx6sxsabresd add board level support for usb
  imx:mx6slevk add board level support for usb

 arch/arm/include/asm/arch-mx6/mx6sl_pins.h  |  5 +++
 board/freescale/mx6slevk/mx6slevk.c | 49 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 49 +
 drivers/usb/host/ehci-mx6.c | 27 ++--
 include/configs/mx6slevk.h  | 14 +
 include/configs/mx6sxsabresd.h  | 14 +
 include/usb/ehci-fsl.h  |  2 ++
 7 files changed, 158 insertions(+), 2 deletions(-)

-- 
1.8.4


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[U-Boot] [PATCH v4 2/3] imx:mx6sxsabresd add board level support for usb

2014-11-09 Thread Peng Fan
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6sxsabresd board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to make host port work in HOST mode.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v4:
 reimplement board_usb_phy_mode.

Changes v3:
 Take Marek's suggestions, replace 'return val  USBPHY_CTRL_OTG_ID' with
 this new function like 'return board_usb_phy_mode(index);'
 Here board_usb_phy_mode only has one parameter 'index' as board_ehci_power and
 board_echi_hcd_init do.
 http://lists.denx.de/pipermail/u-boot/2014-November/194183.html; has detailed
 discussion.

Changes v2:
 Introduce a new weak function to let board have a choice to decide which mode
 to work at. 

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 49 +
 include/configs/mx6sxsabresd.h  | 14 +
 2 files changed, 63 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 256ea29..5aed8d2 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -25,6 +25,8 @@
 #include netdev.h
 #include power/pmic.h
 #include power/pfuze100_pmic.h
+#include usb.h
+#include usb/ehci-fsl.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -271,6 +273,49 @@ int board_mmc_init(bd_t *bis)
return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL  (1  9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   /* OGT1 */
+   MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* OTG2 */
+   MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+   if (port == 1)
+   return USB_INIT_HOST;
+   else
+   return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port  1)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   /* Set Power polarity */
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* Address of boot parameters */
@@ -280,6 +325,10 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index e02ea18..8edf187 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -198,6 +198,20 @@
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 
+
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
 #define CONFIG_CMD_PCI
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI
-- 
1.8.4


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[U-Boot] [PATCH v4 1/3] usb:ehci-mx6 add phy mode query function

2014-11-09 Thread Peng Fan
usb_phy_enable should return status bit, but not phy mode bit, thus
add a new function usb_phy_mode to query the PHY for it's mode and
make usb_phy_enable just return 0 but not 'phy_ctrl  USBPHY_CTRL_OTG_ID'.

Include a new board weak function board_usb_phy_mode. If board code
does not reimplement this function, it just call usb_phy_mode and return
usb_phy_mode's return value. The reason to include such a weak function
is:  SOC OTG core --connect-- board HOST port, but no pin id for
the board host port, so board can not use usb_phy_mode to return the
phy mode, but define it's own rule.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v4:
 - Take Marek's suggestions, implement usb_phy_mode function and
 introduce a weak function board_usb_phy_mode.
 - change usb_phy_enable's return value with 0.
 - add prototype for board_usb_phy_mode and usb_phy_mode

Changes v3:
 - Take Marek's suggestions, replace 'return val  USBPHY_CTRL_OTG_ID' with
 this new function like 'return board_usb_phy_mode(index);'
 Here board_usb_phy_mode only has one parameter 'index' as board_ehci_power and
 board_echi_hcd_init do.
 http://lists.denx.de/pipermail/u-boot/2014-November/194183.html; has detailed
 discussion.

Changes v2:
 - Introduce a new weak function to let board have a choice to decide which mode
 to work at. 

 drivers/usb/host/ehci-mx6.c | 27 +--
 include/usb/ehci-fsl.h  |  2 ++
 2 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 9ec5a0a..951dd3b 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -160,7 +160,7 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
__raw_writel(val, phy_ctrl);
 
-   return val  USBPHY_CTRL_OTG_ID;
+   return 0;
 }
 
 /* Base address for this IP block is 0x02184800 */
@@ -193,6 +193,28 @@ static void usb_oc_config(int index)
__raw_writel(val, ctrl);
 }
 
+int usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   if (val  USBPHY_CTRL_OTG_ID)
+   return USB_INIT_DEVICE;
+   else
+   return USB_INIT_HOST;
+}
+
+int __weak board_usb_phy_mode(int port)
+{
+   return usb_phy_mode(port);
+}
+
 int __weak board_ehci_hcd_init(int port)
 {
return 0;
@@ -221,7 +243,8 @@ int ehci_hcd_init(int index, enum usb_init_type init,
usb_power_config(index);
usb_oc_config(index);
usb_internal_phy_clock_gate(index, 1);
-   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+   usb_phy_enable(index, ehci);
+   type = board_usb_phy_mode(index);
 
*hccr = (struct ehci_hccr *)((uint32_t)ehci-caplength);
*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index dd77ad6..22114c1 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -277,7 +277,9 @@ struct usb_ehci {
 #define MXC_EHCI_IPPUE_DOWN(1  10)
 #define MXC_EHCI_IPPUE_UP  (1  11)
 
+int usb_phy_mode(int port);
 /* Board-specific initialization */
 int board_ehci_hcd_init(int port);
+int board_usb_phy_mode(int port);
 
 #endif /* _EHCI_FSL_H */
-- 
1.8.4


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[U-Boot] [PATCH 3/3] imx:mx6slevk add board level support for usb

2014-11-09 Thread Peng Fan
Add pinmux settings, implement board_ehci_hcd_init, board_usb_phy_mode

There are two usb port on mx6slevk board:
1. otg port
2. host port
The following are the connection between usb controller and board usb
interface, host port has not ID pin set:
otg1 core --- board otg port
otg2 core --- board host port
In order to make host port work, board_usb_phy_mode return USB_INIT_HOST
to let host port work in host mode.

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye Li b37...@freescale.com
---

Changes v4:
 reimplement board_usb_phy_mode

Changes v3:
 implement board_usb_phy_mode

Changes v2:
 Add otg polarity setting
 move pinmux into board_init
 set pinmux setting static

 arch/arm/include/asm/arch-mx6/mx6sl_pins.h |  5 +++
 board/freescale/mx6slevk/mx6slevk.c| 49 ++
 include/configs/mx6slevk.h | 14 +
 3 files changed, 68 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h 
b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
index d9db58c..9ded3d8 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h
@@ -53,5 +53,10 @@ enum {
MX6_PAD_FEC_REF_CLK__FEC_REF_OUT= 
IOMUX_PAD(0x424, 0x134, 0x10, 0x000, 0, 0),
MX6_PAD_FEC_RX_ER__GPIO_4_19= 
IOMUX_PAD(0x0428, 0x0138, 5, 0x, 0, 0),
MX6_PAD_FEC_TX_CLK__GPIO_4_21   = 
IOMUX_PAD(0x0434, 0x0144, 5, 0x, 0, 0),
+
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID  = 
IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0),
+
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR   = 
IOMUX_PAD(0x0484, 0x017C, 6, 0x, 0, 0),
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR   = 
IOMUX_PAD(0x0488, 0x0180, 6, 0x, 0, 0),
 };
 #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */
diff --git a/board/freescale/mx6slevk/mx6slevk.c 
b/board/freescale/mx6slevk/mx6slevk.c
index e76c343..3ae2c46 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -20,6 +20,8 @@
 #include fsl_esdhc.h
 #include mmc.h
 #include netdev.h
+#include usb.h
+#include usb/ehci-fsl.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -243,6 +245,48 @@ static int setup_fec(void)
 }
 #endif
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL  (1  9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   /* OTG1 */
+   MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* OTG2 */
+   MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+   if (port == 1)
+   return USB_INIT_HOST;
+   else
+   return usb_phy_mode(port);
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port  1)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   /* Set Power polarity */
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+#endif
 
 int board_early_init_f(void)
 {
@@ -261,6 +305,11 @@ int board_init(void)
 #ifdef CONFIG_FEC_MXC
setup_fec();
 #endif
+
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index 4fcaf51..bd57159 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -209,6 +209,20 @@
 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
 #endif
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT2
+#endif
+
 #define CONFIG_SYS_FSL_USDHC_NUM   3
 #if defined(CONFIG_ENV_IS_IN_MMC)
 #define CONFIG_SYS_MMC_ENV_DEV 1   /* SDHC2*/
-- 
1.8.4


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Re: [U-Boot] [PATCH v3 1/3] usb:ehci-mx6 add board_usb_phy_mode function

2014-11-09 Thread Peng Fan



On 11/8/2014 7:33 PM, Marek Vasut wrote:

On Saturday, November 08, 2014 at 05:07:21 AM, Peng Fan wrote:

在 11/7/2014 8:17 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:45:51 PM, Peng Fan wrote:

在 11/7/2014 7:09 PM, Marek Vasut 写道:

On Friday, November 07, 2014 at 12:03:30 PM, Peng Fan wrote:

[...]


@@ -160,7 +174,7 @@ static int usb_phy_enable(int index, struct
usb_ehci *ehci) val |= (USBPHY_CTRL_ENUTMILEVEL2 |
USBPHY_CTRL_ENUTMILEVEL3);

__raw_writel(val, phy_ctrl);

-   return val  USBPHY_CTRL_OTG_ID;
+   return board_usb_phy_mode(index);


This should be called from ehci_hcd_init() right after
usb_phy_enable(). Afterall, the mode detection has nothing to do with
the PHY enabling.


This back to what I did in patch v2. right after usb_phy_enable(),
just paste that piece of code here:

The weak function:
+int __weak board_ehci_usb_mode(int index, enum usb_init_type *type)
+{
+   return 0;
+}
+

type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;

+   board_usb_phy_mode(index, type);
+


The usb_phy_enable() should not return the PHY mode at all though.
It should be the board_usb_phy_mode() which adjusts the PHY type.
The usb_phy_enable() should return just a success/failure return
value.


ok. got it.


What need to do is to let board can modify the `type` like following:
+int board_usb_phy_mode(int port, enum usb_init_type *type)
+{
+   if (port == 1)
+   /* port1 works in HOST Mode */
+   *type = USB_INIT_HOST;
+
+   return 0;
+}
+
This is the way that I did in patch v2. If this is fine, I'll resent
this patch set.


It should really explicitly set it, not modify it, see above.


I have an idea about this patch:
1. usb_phy_enable will not be touched.
2. replace type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST; with usb_phy_enable(index, ehci).
3. right after usb_phy_enable, add this line type =
board_usb_phy_mode(index) or type = board_usb_phy_mode((struct usb_phy
*)PHY_ADDRESS). Here I also think pass phy register definition to board
level code is not fine just as what we talked about passing ehci struct
to board level code in patch v2.
4. in ehci-mx6.c, implement the weak function int __weak
board_usb_phy_mode(xxx), and it's return value is the mode, HOST or
DEVICE. If the board code want to implement this function, just return
what the board want.

After all, this patch may looks like this:
In ehci-mx6.c
+int __weak board_usb_phy_mode(int port)
+{
+   void __iomem *phy_reg;
+   void __iomem *phy_ctrl;
+   u32 val;
+
+   phy_reg = (void __iomem *)phy_bases[port];
+   phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
+
+   val = __raw_readl(phy_ctrl);
+
+   return val  USBPHY_CTRL_OTG_ID;
+}
+

- type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE : USB_INIT_HOST;
+ usb_phy_enable(index, ehci);
+ type = board_usb_phy_mode(index);

in board code, which is not in this patch, just list here:
+int board_usb_phy_mode(int port)
+{
+   if (port == 1)
+   return USB_INIT_HOST;
+   else
+   return USB_INIT_DEVICE;
+}
I just want to keep it simple and do not want to touch usb phy register
in board code.

Any ideas?


This seems OKish for all but the part where usb_phy_enable() shouldn't be
touched. The return value of usb_phy_enable() should really be a regular
return code, not the PHY mode.


ok. I'll fix this.


You can also still implement a function to query a PHY for it's mode, so
you don't need to explicitly read the USBPHY_CTRL_OTG_ID in the board
code.


I am not sure whether this following way is fine or not.
+int board_usb_phy_mode(int index)
+   __attribute__((weak, alias(usb_phy_mode)));


__weak board_usb_phy_mode(int index) is fine.


+
in usb_phy_mode, query a PHY for it's mode.

And righter after usb_phy_enable in ehci-mx6.c.
-   type = usb_phy_enable(index, ehci) ? USB_INIT_DEVICE :
USB_INIT_HOST;
+   usb_phy_enable(index, ehci);
+   type = usb_phy_mode(index);

usb_phy_enable return 0 but not return val  USBPHY_CTRL_OTG_ID. There
is no status bit for query enabled or not, so just return 0.

In board file:
int board_usb_phy_mode(int port)
{
  if (port == 1)
  return USB_INIT_HOST;
  else
  return usb_phy_mode(port);
}

I think this is better way then previous patch, but i did not find where
to put the usb_phy_mode prototype type, since board file will use it.


Looks OK otherwise.


Sent out v4 patch, please review.

Thanks,
Peng.
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Re: [U-Boot] [PATCH] imx:mx6sxsabresd fix pfuz probe failed

2014-11-16 Thread Peng Fan

Hi Stefano,

Would you please help reviewing this patch?

On 11/1/2014 8:16 AM, Fabio Estevam wrote:

On Fri, Oct 31, 2014 at 1:08 AM, Peng Fan peng@freescale.com wrote:

The PFUZ probe failed with the following msg:
 wait_for_sr_state: failed sr=81 cr=a0 state=2020
   i2c_init_transfer: failed for chip 0x8 retry=0
   wait_for_sr_state: failed sr=81 cr=a0 state=2020
   i2c_init_transfer: failed for chip 0x8 retry=1
   wait_for_sr_state: failed sr=81 cr=a0 state=2020
   i2c_init_transfer: failed for chip 0x8 retry=2
   i2c_init_transfer: give up i2c_regs=021a
   Can't find PMIC:PFUZE100 

board_early_init_f is too early to call i2c related setting, because
init_func_i2c is called after board_early_init_f being invoked. Thus
move setup_i2c into board_init.

Also PFUZ is connected to I2C bus 0, so change 1 - 0.

Using this patch PFUZ can be correctly probed:
PMIC:  PFUZE100 ID=0x11

Signed-off-by: Peng Fan peng@freescale.com


Acked-by: Fabio Estevam fabio.este...@freescale.com


Regards,
Peng.
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[U-Boot] [PATCH] imx:mx6 fix return value of mxc_get_clock

2014-11-22 Thread Peng Fan
mxc_get_clock's return type is unsigned int. 'return -1' is same with
'return 0x', so 0 should be used as the return value when
unsupported mxc_clock type is passed to mxc_get_clock.

Also include an err message when unsupported mxc_clock type is passed
to mxc_get_clock.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/cpu/armv7/mx6/clock.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 80b11aa..99dba07 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -738,10 +738,11 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
case MXC_SATA_CLK:
return get_ahb_clk();
default:
+   printf(Unsupported MXC CLK: %d\n, clk);
break;
}
 
-   return -1;
+   return 0;
 }
 
 /*
-- 
1.8.4


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[U-Boot] [PATCH 2/2] imx:mx6qarm2 add board level support for usb

2014-12-01 Thread Peng Fan
Add pinmux settings and implement board_ehci_hcd_init

Signed-off-by: Peng Fan peng@freescale.com
---
 board/freescale/mx6qarm2/mx6qarm2.c | 42 +
 include/configs/mx6qarm2.h  | 14 +
 2 files changed, 56 insertions(+)

diff --git a/board/freescale/mx6qarm2/mx6qarm2.c 
b/board/freescale/mx6qarm2/mx6qarm2.c
index 3a5b26d..98ccdb7 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -16,6 +16,7 @@
 #include fsl_esdhc.h
 #include miiphy.h
 #include netdev.h
+#include usb.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -213,6 +214,43 @@ int board_eth_init(bd_t *bis)
return 0;
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL  (1  9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+
+   /*
+* set daisy chain for otg_pin_id on 6q.
+* for 6dl, this bit is reserved
+*/
+   imx_iomux_set_gpr_register(1, 13, 1, 1);
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port  0)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
setup_iomux_uart();
@@ -226,6 +264,10 @@ int board_init(void)
/* address of boot parameters */
gd-bd-bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 6e01fa0..76cfef1 100644
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -189,4 +189,18 @@
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1
+#endif
+
 #endif /* __CONFIG_H */
-- 
1.8.4


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[U-Boot] [PATCH 1/2] imx:mx6sabresd add board level support for usb

2014-12-01 Thread Peng Fan
Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power

Signed-off-by: Peng Fan peng@freescale.com
---
 board/freescale/mx6sabresd/mx6sabresd.c | 68 +
 include/configs/mx6sabresd.h| 14 +++
 2 files changed, 82 insertions(+)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c 
b/board/freescale/mx6sabresd/mx6sabresd.c
index ac3757f..2f7198d 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -29,6 +29,7 @@
 #include power/pfuze100_pmic.h
 #include ../common/pfuze.h
 #include asm/arch/mx6-ddr.h
+#include usb.h
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -537,6 +538,69 @@ int board_eth_init(bd_t *bis)
return cpu_eth_init(bis);
 }
 
+#ifdef CONFIG_USB_EHCI_MX6
+#define USB_OTHERREGS_OFFSET   0x800
+#define UCTRL_PWR_POL  (1  9)
+
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+   MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+   MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usb_hc1_pads[] = {
+   MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_usb(void)
+{
+   imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+ARRAY_SIZE(usb_otg_pads));
+
+   /*
+* set daisy chain for otg_pin_id on 6q.
+* for 6dl, this bit is reserved
+*/
+   imx_iomux_set_gpr_register(1, 13, 1, 0);
+
+   imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
+ARRAY_SIZE(usb_hc1_pads));
+}
+
+int board_ehci_hcd_init(int port)
+{
+   u32 *usbnc_usb_ctrl;
+
+   if (port  1)
+   return -EINVAL;
+
+   usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
+port * 4);
+
+   setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
+
+   return 0;
+}
+
+int board_ehci_power(int port, int on)
+{
+   switch (port) {
+   case 0:
+   break;
+   case 1:
+   if (on)
+   gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
+   else
+   gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
+   break;
+   default:
+   printf(MXC USB port %d not yet supported\n, port);
+   return -EINVAL;
+   }
+
+   return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
setup_iomux_uart();
@@ -557,6 +621,10 @@ int board_init(void)
 #endif
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
 
+#ifdef CONFIG_USB_EHCI_MX6
+   setup_usb();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index a346542..99d9d4d 100644
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -60,4 +60,18 @@
 #define CONFIG_POWER_PFUZE100
 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
 
+/* USB Configs */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT1 /* Enabled USB controller 
number */
+#endif
+
 #endif /* __MX6QSABRESD_CONFIG_H */
-- 
1.8.4


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[U-Boot] [PATCH 1/2] mtd:mxs:nand calculate ecc strength dynamically

2014-12-18 Thread Peng Fan
Calculate ecc strength according oobsize, but not hardcoded
which is not aligned with kernel driver

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
 drivers/mtd/nand/mxs_nand.c | 22 --
 1 file changed, 4 insertions(+), 18 deletions(-)

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 7a064ab..a45fcf9 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -146,26 +146,12 @@ static uint32_t mxs_nand_aux_status_offset(void)
 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
uint32_t page_oob_size)
 {
-   if (page_data_size == 2048) {
-   if (page_oob_size == 64)
-   return 8;
+   int ecc_strength;
 
-   if (page_oob_size == 112)
-   return 14;
-   }
-
-   if (page_data_size == 4096) {
-   if (page_oob_size == 128)
-   return 8;
-
-   if (page_oob_size == 218)
-   return 16;
+   ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
+   / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
 
-   if (page_oob_size == 224)
-   return 16;
-   }
-
-   return 0;
+   return round_down(ecc_strength, 2);
 }
 
 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
-- 
1.8.4


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[U-Boot] [PATCH 2/2] mtd:mxs:nand support oobsize bigger than 512

2014-12-18 Thread Peng Fan
If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.

The following graph is modified from kernel gpmi-nand.c driver with each data
block 512 bytes.
We can see that Block Mark conflicts with ecc area from bch view.
We can enlarge the ecc chunk size to avoid this problem to those oobsize
which is larger than 512.

   |  P|
   |-|
   |   |
   |(Block Mark)   |
   |  P' |   | |   |
   |---| D | | O'|
   | |-| |-|
   V V   V V   V
   +---+--+-+--+-+--+-+--+-+---+
   | M |   data   |E|   data   |E|   data   |E|   data   |E|   |
   +---+--+-+--+-+--+-+--+-+---+
^  ^
| O|
||

   P : the page size for BCH module.
   E : The ECC strength.
   G : the length of Galois Field.
   N : The chunk count of per page.
   M : the metasize of per page.
   C : the ecc chunk size, aka the data above.
   P': the nand chip's page size.
   O : the nand chip's oob size.
   O': the free oob.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/include/asm/imx-common/regs-bch.h |  2 ++
 drivers/mtd/nand/mxs_nand.c| 33 ++
 2 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/imx-common/regs-bch.h 
b/arch/arm/include/asm/imx-common/regs-bch.h
index a33d341..5c47783 100644
--- a/arch/arm/include/asm/imx-common/regs-bch.h
+++ b/arch/arm/include/asm/imx-common/regs-bch.h
@@ -148,6 +148,7 @@ struct mxs_bch_regs {
 #defineBCH_FLASHLAYOUT0_ECC0_ECC30 (0xf  12)
 #defineBCH_FLASHLAYOUT0_ECC0_ECC32 (0x10  12)
 #defineBCH_FLASHLAYOUT0_GF13_0_GF14_1  (1  10)
+#defineBCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET   10
 #defineBCH_FLASHLAYOUT0_DATA0_SIZE_MASK0xfff
 #defineBCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET  0
 
@@ -178,6 +179,7 @@ struct mxs_bch_regs {
 #defineBCH_FLASHLAYOUT1_ECCN_ECC30 (0xf  12)
 #defineBCH_FLASHLAYOUT1_ECCN_ECC32 (0x10  12)
 #defineBCH_FLASHLAYOUT1_GF13_0_GF14_1  (1  10)
+#defineBCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET   10
 #defineBCH_FLASHLAYOUT1_DATAN_SIZE_MASK0xfff
 #defineBCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET  0
 
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index a45fcf9..0db9eb3 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -29,6 +29,7 @@
 
 #defineMXS_NAND_DMA_DESCRIPTOR_COUNT   4
 
+#defineMXS_NAND_MAX_CHUNK_DATA_CHUNK_SIZE  1024
 #defineMXS_NAND_CHUNK_DATA_CHUNK_SIZE  512
 #if defined(CONFIG_MX6)
 #defineMXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT2
@@ -68,6 +69,8 @@ struct mxs_nand_info {
 };
 
 struct nand_ecclayout fake_ecc_layout;
+static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+static int gf_len = 13;
 
 /*
  * Cache management functions
@@ -130,12 +133,12 @@ static void mxs_nand_return_dma_descs(struct 
mxs_nand_info *info)
 
 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
 {
-   return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+   return page_data_size / chunk_data_size;
 }
 
 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
 {
-   return ecc_strength * 13;
+   return ecc_strength * gf_len;
 }
 
 static uint32_t mxs_nand_aux_status_offset(void)
@@ -149,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t 
page_data_size,
int ecc_strength;
 
ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
-   / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
+   / (gf_len * mxs_nand_ecc_chunk_cnt(page_data_size));
 
return round_down(ecc_strength, 2);
 }
@@ -164,7 +167,7 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t 
page_data_size,
uint32_t block_mark_chunk_bit_offset;
uint32_t block_mark_bit_offset;
 
-   chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8

[U-Boot] [PATCH] imx:mx6slevk add spi nor boot support

2014-12-29 Thread Peng Fan
Add spi nor boot support for mx6slevk board.

Signed-off-by: Peng Fan peng@freescale.com
---
 board/freescale/mx6slevk/MAINTAINERS |  1 +
 configs/mx6slevk_spinor_defconfig|  3 +++
 include/configs/mx6slevk.h   | 13 -
 3 files changed, 16 insertions(+), 1 deletion(-)
 create mode 100644 configs/mx6slevk_spinor_defconfig

diff --git a/board/freescale/mx6slevk/MAINTAINERS 
b/board/freescale/mx6slevk/MAINTAINERS
index 660af91..18d31a8 100644
--- a/board/freescale/mx6slevk/MAINTAINERS
+++ b/board/freescale/mx6slevk/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
 F: board/freescale/mx6slevk/
 F: include/configs/mx6slevk.h
 F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spinor_defconfig
diff --git a/configs/mx6slevk_spinor_defconfig 
b/configs/mx6slevk_spinor_defconfig
new file mode 100644
index 000..93efe73
--- /dev/null
+++ b/configs/mx6slevk_spinor_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SLEVK=y
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index e3e7f76..e6c4130 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -187,9 +187,20 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
 #define CONFIG_ENV_SIZESZ_8K
+
+#if defined CONFIG_SYS_BOOT_SPINOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET   (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE(64 * 1024)
+#define CONFIG_ENV_SPI_BUS  CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS   CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED
+#else
+#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
 #define CONFIG_ENV_IS_IN_MMC
+#endif
 
 #define CONFIG_OF_LIBFDT
 #define CONFIG_CMD_BOOTZ
-- 
1.8.4


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[U-Boot] [PATCH 2/6] imx:mx6sxsabresd select SUPPORT_SPL

2014-12-30 Thread Peng Fan
select SUPPORT_SPL for mx6sxsabresd.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5eb1d03..46e708f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -637,6 +637,7 @@ config TARGET_MX6SLEVK
 config TARGET_MX6SXSABRESD
bool Support mx6sxsabresd
select CPU_V7
+   select SUPPORT_SPL
 
 config TARGET_GW_VENTANA
bool Support gw_ventana
-- 
1.8.4


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[U-Boot] [PATCH 3/6] imx:mx6sxsabresd spl support in header file

2014-12-30 Thread Peng Fan
Add SPL support in mx6sxsabresd header file.

Signed-off-by: Peng Fan peng@freescale.com
---
 include/configs/mx6sxsabresd.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 61a7a7a..19ac3dc 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -18,6 +18,12 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#include imx6_spl.h
+#endif
+
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
-- 
1.8.4


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[U-Boot] [PATCH 5/6] imx:mx6 add mx6sx in imx spl header file

2014-12-30 Thread Peng Fan
Since mx6sx's memory space is different to mx6dq, redefine the SPL
related macro for mx6sx chip.

Signed-off-by: Peng Fan peng@freescale.com
---
 include/configs/imx6_spl.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index 1b9c277..21c5dce 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -61,11 +61,19 @@
 #define CONFIG_SPL_LIBDISK_SUPPORT
 #endif
 
+#if defined(CONFIG_MX6SX)
+#define CONFIG_SPL_BSS_START_ADDR  0x8820
+#define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START0x8830
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x320   /* 50 MB */
+#define CONFIG_SYS_TEXT_BASE   0x8780
+#else
 #define CONFIG_SPL_BSS_START_ADDR  0x1820
 #define CONFIG_SPL_BSS_MAX_SIZE0x10/* 1 MB */
 #define CONFIG_SYS_SPL_MALLOC_START0x1830
 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x320   /* 50 MB */
 #define CONFIG_SYS_TEXT_BASE   0x1780
 #endif
+#endif
 
 #endif
-- 
1.8.4


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[U-Boot] [PATCH 6/6] imx:mx6sxsabresd board spl support

2014-12-30 Thread Peng Fan
Add board level spl support for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
---
 board/freescale/mx6sxsabresd/MAINTAINERS|   1 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 
 2 files changed, 169 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS 
b/board/freescale/mx6sxsabresd/MAINTAINERS
index f52f300..c0f5d9c 100644
--- a/board/freescale/mx6sxsabresd/MAINTAINERS
+++ b/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
 F: board/freescale/mx6sxsabresd/
 F: include/configs/mx6sxsabresd.h
 F: configs/mx6sxsabresd_defconfig
+F: configs/mx6sxsabresd_spl_defconfig
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index fd8bc72..74f6d40 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc)
 
 int board_mmc_init(bd_t *bis)
 {
+#ifndef CONFIG_SPL_BUILD
int i, ret;
 
/*
@@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis)
}
 
return 0;
+#else
+   struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+   u32 val;
+   u32 port;
+
+   val = readl(src_regs-sbmr1);
+
+   if ((val  0xc0) != 0x40) {
+   printf(Not boot from USDHC!\n);
+   return -EINVAL;
+   }
+
+   port = (val  11)  0x3;
+   printf(port %d\n, port);
+   switch (port) {
+   case 1:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+   break;
+   case 2:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+   gpio_direction_input(USDHC3_CD_GPIO);
+   gpio_direction_output(USDHC3_PWR_GPIO, 1);
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+   break;
+   case 3:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+   gpio_direction_input(USDHC4_CD_GPIO);
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+   break;
+   }
+
+   gd-arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+   return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
+#endif
 }
 
 int board_init(void)
@@ -394,3 +436,129 @@ int checkboard(void)
 
return 0;
 }
+
+#ifdef CONFIG_SPL_BUILD
+#include libfdt.h
+#include spl.h
+#include asm/arch/mx6-ddr.h
+
+const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+   .dram_dqm0 = 0x0028,
+   .dram_dqm1 = 0x0028,
+   .dram_dqm2 = 0x0028,
+   .dram_dqm3 = 0x0028,
+   .dram_ras = 0x0020,
+   .dram_cas = 0x0020,
+   .dram_odt0 = 0x0020,
+   .dram_odt1 = 0x0020,
+   .dram_sdba2 = 0x,
+   .dram_sdcke0 = 0x3000,
+   .dram_sdcke1 = 0x3000,
+   .dram_sdclk_0 = 0x0030,
+   .dram_sdqs0 = 0x0028,
+   .dram_sdqs1 = 0x0028,
+   .dram_sdqs2 = 0x0028,
+   .dram_sdqs3 = 0x0028,
+   .dram_reset = 0x0020,
+};
+
+const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+   .grp_addds = 0x0020,
+   .grp_ddrmode_ctl = 0x0002,
+   .grp_ddrpke = 0x,
+   .grp_ddrmode = 0x0002,
+   .grp_b0ds = 0x0028,
+   .grp_b1ds = 0x0028,
+   .grp_ctlds = 0x0020,
+   .grp_ddr_type = 0x000c,
+   .grp_b2ds = 0x0028,
+   .grp_b3ds = 0x0028,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+   .p0_mpwldectrl0 = 0x00290025,
+   .p0_mpwldectrl1 = 0x00220022,
+   .p0_mpdgctrl0 = 0x41480144,
+   .p0_mpdgctrl1 = 0x01340130,
+   .p0_mprddlctl = 0x3C3E4244,
+   .p0_mpwrdlctl = 0x34363638,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+   .mem_speed = 1600,
+   .density = 4,
+   .width = 32,
+   .banks = 8,
+   .rowaddr = 15,
+   .coladdr = 10,
+   .pagesz = 2,
+   .trcd = 1375,
+   .trcmin = 4875,
+   .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   writel(0x, ccm-CCGR0);
+   writel(0x, ccm-CCGR1);
+   writel(0x, ccm-CCGR2);
+   writel(0x, ccm-CCGR3);
+   writel(0x, ccm-CCGR4);
+   writel(0x, ccm-CCGR5);
+   writel(0x, ccm-CCGR6);
+   writel(0x, ccm-CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+   struct mx6_ddr_sysinfo sysinfo = {
+   .dsize = mem_ddr.width/32,
+   .cs_density

[U-Boot] [PATCH 1/6] imx:mx6sxsabresd add spl config file

2014-12-30 Thread Peng Fan
Add a SPL default configuration file for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
---
 configs/mx6sxsabresd_spl_defconfig | 4 
 1 file changed, 4 insertions(+)
 create mode 100644 configs/mx6sxsabresd_spl_defconfig

diff --git a/configs/mx6sxsabresd_spl_defconfig 
b/configs/mx6sxsabresd_spl_defconfig
new file mode 100644
index 000..6b36e06
--- /dev/null
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_MX6SXSABRESD=y
-- 
1.8.4


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[U-Boot] [PATCH 0/6] imx:mx6 spl support for mx6sxsabresd

2014-12-30 Thread Peng Fan
This patch set is to make mx6sxsabresd spl boot capable from USDHC.
SPL image is burned to sector 2 of SD card. u-boot.img is burned to
sector 138.

Since i.MX 6SoloX chip only supports one mmdc channel, in order to reuse
mx6_dram_cfg, define a new macro MMDC1. To i.MX 6SoloX, MMDC1 does nothing;
to others, MMDC1 effects as the original mmdc1-entry = value.

Peng Fan (6):
  imx:mx6sxsabresd add spl config file
  imx:mx6sxsabresd select SUPPORT_SPL
  imx:mx6sxsabresd spl support in header file
  imx:mx6sx add dram io configure for mx6sx
  imx:mx6 add mx6sx in imx spl header file
  imx:mx6sxsabresd board spl support

 arch/arm/Kconfig|   1 +
 arch/arm/cpu/armv7/mx6/ddr.c|  96 +---
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |  46 
 board/freescale/mx6sxsabresd/MAINTAINERS|   1 +
 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 
 configs/mx6sxsabresd_spl_defconfig  |   4 +
 include/configs/imx6_spl.h  |   8 ++
 include/configs/mx6sxsabresd.h  |   6 +
 8 files changed, 316 insertions(+), 14 deletions(-)
 create mode 100644 configs/mx6sxsabresd_spl_defconfig

-- 
1.8.4


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[U-Boot] [PATCH 4/6] imx:mx6sx add dram io configure for mx6sx

2014-12-30 Thread Peng Fan
Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs.
Add a new function mx6sx_dram_iocfg to configure dram io.

Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1
to replace mmdc1-entry=value for mx6sx. And to other mx6 soc, MMDC1
effects as mmdc1-entry=value.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/cpu/armv7/mx6/ddr.c| 96 -
 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 46 
 2 files changed, 128 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7a9b03a..fef2231 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -12,6 +12,65 @@
 #include asm/io.h
 #include asm/types.h
 
+#if defined(CONFIG_MX6SX)
+/* Configure MX6SX mmdc iomux */
+void mx6sx_dram_iocfg(unsigned width,
+ const struct mx6sx_iomux_ddr_regs *ddr,
+ const struct mx6sx_iomux_grp_regs *grp)
+{
+   struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
+   struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
+
+   mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
+   mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
+
+   /* DDR IO TYPE */
+   writel(grp-grp_ddr_type, mx6_grp_iomux-grp_ddr_type);
+   writel(grp-grp_ddrpke, mx6_grp_iomux-grp_ddrpke);
+
+   /* CLOCK */
+   writel(ddr-dram_sdclk_0, mx6_ddr_iomux-dram_sdclk_0);
+
+   /* ADDRESS */
+   writel(ddr-dram_cas, mx6_ddr_iomux-dram_cas);
+   writel(ddr-dram_ras, mx6_ddr_iomux-dram_ras);
+   writel(grp-grp_addds, mx6_grp_iomux-grp_addds);
+
+   /* Control */
+   writel(ddr-dram_reset, mx6_ddr_iomux-dram_reset);
+   writel(ddr-dram_sdba2, mx6_ddr_iomux-dram_sdba2);
+   writel(ddr-dram_sdcke0, mx6_ddr_iomux-dram_sdcke0);
+   writel(ddr-dram_sdcke1, mx6_ddr_iomux-dram_sdcke1);
+   writel(ddr-dram_odt0, mx6_ddr_iomux-dram_odt0);
+   writel(ddr-dram_odt1, mx6_ddr_iomux-dram_odt1);
+   writel(grp-grp_ctlds, mx6_grp_iomux-grp_ctlds);
+
+   /* Data Strobes */
+   writel(grp-grp_ddrmode_ctl, mx6_grp_iomux-grp_ddrmode_ctl);
+   writel(ddr-dram_sdqs0, mx6_ddr_iomux-dram_sdqs0);
+   writel(ddr-dram_sdqs1, mx6_ddr_iomux-dram_sdqs1);
+   if (width = 32) {
+   writel(ddr-dram_sdqs2, mx6_ddr_iomux-dram_sdqs2);
+   writel(ddr-dram_sdqs3, mx6_ddr_iomux-dram_sdqs3);
+   }
+
+   /* Data */
+   writel(grp-grp_ddrmode, mx6_grp_iomux-grp_ddrmode);
+   writel(grp-grp_b0ds, mx6_grp_iomux-grp_b0ds);
+   writel(grp-grp_b1ds, mx6_grp_iomux-grp_b1ds);
+   if (width = 32) {
+   writel(grp-grp_b2ds, mx6_grp_iomux-grp_b2ds);
+   writel(grp-grp_b3ds, mx6_grp_iomux-grp_b3ds);
+   }
+   writel(ddr-dram_dqm0, mx6_ddr_iomux-dram_dqm0);
+   writel(ddr-dram_dqm1, mx6_ddr_iomux-dram_dqm1);
+   if (width = 32) {
+   writel(ddr-dram_dqm2, mx6_ddr_iomux-dram_dqm2);
+   writel(ddr-dram_dqm3, mx6_ddr_iomux-dram_dqm3);
+   }
+}
+#endif
+
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
@@ -184,12 +243,19 @@ void mx6sdl_dram_iocfg(unsigned width,
  */
 #define MR(val, ba, cmd, cs1) \
((val  16) | (1  15) | (cmd  4) | (cs1  3) | ba)
+#ifdef CONFIG_MX6SX
+#define MMDC1(entry, value)do {} while (0)
+#else
+#define MMDC1(entry, value) do { mmdc1-entry = value; } while (0)
+#endif
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  const struct mx6_mmdc_calibration *calib,
  const struct mx6_ddr3_cfg *ddr3_cfg)
 {
volatile struct mmdc_p_regs *mmdc0;
+#ifndef CONFIG_MX6SX
volatile struct mmdc_p_regs *mmdc1;
+#endif
u32 val;
u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
@@ -203,7 +269,9 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
int cs;
 
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+#ifndef CONFIG_MX6SX
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+#endif
 
/* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
@@ -362,12 +430,12 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
mmdc0-mprddlctl = calib-p0_mprddlctl;
mmdc0-mpwrdlctl = calib-p0_mpwrdlctl;
if (sysinfo-dsize  1) {
-   mmdc1-mpwldectrl0 = calib-p1_mpwldectrl0;
-   mmdc1-mpwldectrl1 = calib-p1_mpwldectrl1;
-   mmdc1-mpdgctrl0 = calib-p1_mpdgctrl0;
-   mmdc1-mpdgctrl1 = calib-p1_mpdgctrl1;
-   mmdc1-mprddlctl = calib-p1_mprddlctl;
-   mmdc1-mpwrdlctl = calib-p1_mpwrdlctl;
+   MMDC1(mpwldectrl0, calib-p1_mpwldectrl0

[U-Boot] [PATCH v4 0/5] qspi: qspi support for mx6sxsabresd

2014-12-30 Thread Peng Fan
This patch set is to support qspi for mx6sxsabresd board.

To mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT
initialization qspi_set_lut function uses 32BIT addr, however
CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to access
bigger than 16MB size flash, and BRRD/BRWR should also be supported.
Future patches will fix this.

Since flash opcodes are not recommended to use in driver level, use
QSPI_CMD_xx to replace OPCODE_xx. It is qspi controller's feature
to program LUT with QSPI_CMD_xx which same value with OPCODE_xx.

Since Revb board's qspi flash support 4K erase, 4K erase is added in driver.

Peng Fan (5):
  QuadSPI: use QSPI_CMD_xx instead of flash opcodes
  QuadSPI: use correct amba_base
  arm:mx6sx add QSPI support
  imx:qspi add 4K erase support
  imx:mx6sxsabresd add qspi support

 arch/arm/cpu/armv7/mx6/clock.c  |  50 ++
 arch/arm/include/asm/arch-mx6/clock.h   |   1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h|  12 +--
 board/freescale/mx6sxsabresd/mx6sxsabresd.c |  40 
 drivers/spi/fsl_qspi.c  | 137 +++-
 include/configs/mx6sxsabresd.h  |  12 +++
 6 files changed, 205 insertions(+), 47 deletions(-)

-- 
1.8.4


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[U-Boot] [PATCH v4 1/5] QuadSPI: use QSPI_CMD_xx instead of flash opcodes

2014-12-30 Thread Peng Fan
Use QSPI_CMD_xx instead of flash opcodes

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
  None

Changes v3:
  Use QSPI_CMD_XX instead of flash opcodes. To fsl qspi controller,
  the LUT  should be pre programmed with QSPI CMD.

Changes v2:
 None

 drivers/spi/fsl_qspi.c | 64 ++
 1 file changed, 33 insertions(+), 31 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index ba20bef..61490c9 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -29,19 +29,19 @@
 #define SEQID_PP   6
 #define SEQID_RDID 7
 
-/* Flash opcodes */
-#define OPCODE_PP  0x02/* Page program (up to 256 bytes) */
-#define OPCODE_RDSR0x05/* Read status register */
-#define OPCODE_WREN0x06/* Write enable */
-#define OPCODE_FAST_READ   0x0b/* Read data bytes (high frequency) */
-#define OPCODE_CHIP_ERASE  0xc7/* Erase whole flash chip */
-#define OPCODE_SE  0xd8/* Sector erase (usually 64KiB) */
-#define OPCODE_RDID0x9f/* Read JEDEC ID */
-
-/* 4-byte address opcodes - used on Spansion and some Macronix flashes */
-#define OPCODE_FAST_READ_4B0x0c/* Read data bytes (high frequency) */
-#define OPCODE_PP_4B   0x12/* Page program (up to 256 bytes) */
-#define OPCODE_SE_4B   0xdc/* Sector erase (usually 64KiB) */
+/* QSPI CMD */
+#define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
+#define QSPI_CMD_RDSR  0x05/* Read status register */
+#define QSPI_CMD_WREN  0x06/* Write enable */
+#define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
+#define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
+#define QSPI_CMD_RDID  0x9f/* Read JEDEC ID */
+
+/* 4-byte address QSPI CMD - used on Spansion and some Macronix flashes */
+#define QSPI_CMD_FAST_READ_4B  0x0c/* Read data bytes (high frequency) */
+#define QSPI_CMD_PP_4B 0x12/* Page program (up to 256 bytes) */
+#define QSPI_CMD_SE_4B 0xdc/* Sector erase (usually 64KiB) */
 
 #ifdef CONFIG_SYS_FSL_QSPI_LE
 #define qspi_read32in_le32
@@ -94,7 +94,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
 
/* Write Enable */
lut_base = SEQID_WREN * 4;
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_WREN) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_WREN) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD));
qspi_write32(regs-lut[lut_base + 1], 0);
qspi_write32(regs-lut[lut_base + 2], 0);
@@ -103,13 +103,15 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
/* Fast Read */
lut_base = SEQID_FAST_READ * 4;
if (FSL_QSPI_FLASH_SIZE  = SZ_16M)
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_FAST_READ) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_FAST_READ) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_FAST_READ_4B) |
-   PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
-   PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+   qspi_write32(regs-lut[lut_base],
+OPRND0(QSPI_CMD_FAST_READ_4B) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) |
+OPRND1(ADDR32BIT) | PAD1(LUT_PAD1) |
+INSTR1(LUT_ADDR));
qspi_write32(regs-lut[lut_base + 1], OPRND0(8) | PAD0(LUT_PAD1) |
INSTR0(LUT_DUMMY) | OPRND1(RX_BUFFER_SIZE) | PAD1(LUT_PAD1) |
INSTR1(LUT_READ));
@@ -118,7 +120,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
 
/* Read Status */
lut_base = SEQID_RDSR * 4;
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_RDSR) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_RDSR) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(1) |
PAD1(LUT_PAD1) | INSTR1(LUT_READ));
qspi_write32(regs-lut[lut_base + 1], 0);
@@ -128,11 +130,11 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
/* Erase a sector */
lut_base = SEQID_SE * 4;
if (FSL_QSPI_FLASH_SIZE  = SZ_16M)
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_SE) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_SE) |
PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
else
-   qspi_write32(regs-lut[lut_base], OPRND0(OPCODE_SE_4B) |
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_SE_4B) |
PAD0(LUT_PAD1

[U-Boot] [PATCH v4 2/5] QuadSPI: use correct amba_base

2014-12-30 Thread Peng Fan
According cs, use different amba_base to choose the corresponding
flash devices.  If not, `sf probe 1:0` and `sf probe 1:1` will
choose the same flash device, but not different flash devices.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 None

Changes v3:
 None

Changes v2:
 None

 drivers/spi/fsl_qspi.c | 30 +-
 1 file changed, 25 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 61490c9..eae2f3a 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -194,12 +194,22 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
if (bus = ARRAY_SIZE(spi_bases))
return NULL;
 
+   if (cs = FSL_QSPI_FLASH_NUM)
+   return NULL;
+
qspi = spi_alloc_slave(struct fsl_qspi, bus, cs);
if (!qspi)
return NULL;
 
qspi-reg_base = spi_bases[bus];
-   qspi-amba_base = amba_bases[bus];
+   /*
+* According cs, use different amba_base to choose the
+* corresponding flash devices.
+*
+* If not, only one flash device is used even if passing
+* different cs using `sf probe`
+*/
+   qspi-amba_base = amba_bases[bus] + cs * FSL_QSPI_FLASH_SIZE;
 
qspi-slave.max_write_size = TX_BUFFER_SIZE;
 
@@ -212,10 +222,20 @@ struct spi_slave *spi_setup_slave(unsigned int bus, 
unsigned int cs,
qspi_write32(regs-mcr, QSPI_MCR_RESERVED_MASK);
 
total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM;
-   qspi_write32(regs-sfa1ad, FSL_QSPI_FLASH_SIZE | qspi-amba_base);
-   qspi_write32(regs-sfa2ad, FSL_QSPI_FLASH_SIZE | qspi-amba_base);
-   qspi_write32(regs-sfb1ad, total_size | qspi-amba_base);
-   qspi_write32(regs-sfb2ad, total_size | qspi-amba_base);
+   /*
+* Any read access to non-implemented addresses will provide
+* undefined results.
+*
+* In case single die flash devices, TOP_ADDR_MEMA2 and
+* TOP_ADDR_MEMB2 should be initialized/programmed to
+* TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect,
+* setting the size of these devices to 0.  This would ensure
+* that the complete memory map is assigned to only one flash device.
+*/
+   qspi_write32(regs-sfa1ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+   qspi_write32(regs-sfa2ad, FSL_QSPI_FLASH_SIZE | amba_bases[bus]);
+   qspi_write32(regs-sfb1ad, total_size | amba_bases[bus]);
+   qspi_write32(regs-sfb2ad, total_size | amba_bases[bus]);
 
qspi_set_lut(qspi);
 
-- 
1.8.4


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[U-Boot] [PATCH v4 4/5] imx:qspi add 4K erase support

2014-12-30 Thread Peng Fan
Add 4k erase command support for qspi driver. reuse the 64k erase function,
but change the function name from qspi_op_se to qspi_op_erase, since it
supports 64k and 4k erase.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 New patch in v4. This patch is to support 4k erase.

 drivers/spi/fsl_qspi.c | 24 +++-
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e9c45de..d12f420 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -32,12 +32,14 @@
 #define SEQID_CHIP_ERASE   5
 #define SEQID_PP   6
 #define SEQID_RDID 7
+#define SEQID_BE_4K8
 
 /* QSPI CMD */
 #define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */
 #define QSPI_CMD_RDSR  0x05/* Read status register */
 #define QSPI_CMD_WREN  0x06/* Write enable */
 #define QSPI_CMD_FAST_READ 0x0b/* Read data bytes (high frequency) */
+#define QSPI_CMD_BE_4K 0x20/* 4K erase */
 #define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */
 #define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */
 #define QSPI_CMD_RDID  0x9f/* Read JEDEC ID */
@@ -192,6 +194,12 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
qspi_write32(regs-lut[lut_base + 2], 0);
qspi_write32(regs-lut[lut_base + 3], 0);
 
+   /* SUB SECTOR 4K ERASE */
+   lut_base = SEQID_BE_4K * 4;
+   qspi_write32(regs-lut[lut_base], OPRND0(QSPI_CMD_BE_4K) |
+PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) |
+PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
+
/* Lock the LUT */
qspi_write32(regs-lutkey, LUT_KEY_VALUE);
qspi_write32(regs-lckcr, QSPI_LCKCR_LOCK);
@@ -450,7 +458,7 @@ static void qspi_op_rdsr(struct fsl_qspi *qspi, u32 *rxbuf)
qspi_write32(regs-mcr, mcr_reg);
 }
 
-static void qspi_op_se(struct fsl_qspi *qspi)
+static void qspi_op_erase(struct fsl_qspi *qspi)
 {
struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
u32 mcr_reg;
@@ -469,8 +477,13 @@ static void qspi_op_se(struct fsl_qspi *qspi)
while (qspi_read32(regs-sr)  QSPI_SR_BUSY_MASK)
;
 
-   qspi_write32(regs-ipcr,
-   (SEQID_SE  QSPI_IPCR_SEQID_SHIFT) | 0);
+   if (qspi-cur_seqid == QSPI_CMD_SE) {
+   qspi_write32(regs-ipcr,
+(SEQID_SE  QSPI_IPCR_SEQID_SHIFT) | 0);
+   } else if (qspi-cur_seqid == QSPI_CMD_BE_4K) {
+   qspi_write32(regs-ipcr,
+(SEQID_BE_4K  QSPI_IPCR_SEQID_SHIFT) | 0);
+   }
while (qspi_read32(regs-sr)  QSPI_SR_BUSY_MASK)
;
 
@@ -497,9 +510,10 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 
if (qspi-cur_seqid == QSPI_CMD_FAST_READ) {
qspi-sf_addr = swab32(txbuf)  OFFSET_BITS_MASK;
-   } else if (qspi-cur_seqid == QSPI_CMD_SE) {
+   } else if ((qspi-cur_seqid == QSPI_CMD_SE) ||
+  (qspi-cur_seqid == QSPI_CMD_BE_4K)) {
qspi-sf_addr = swab32(txbuf)  OFFSET_BITS_MASK;
-   qspi_op_se(qspi);
+   qspi_op_erase(qspi);
} else if (qspi-cur_seqid == QSPI_CMD_PP) {
pp_sfaddr = swab32(txbuf)  OFFSET_BITS_MASK;
}
-- 
1.8.4


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[U-Boot] [PATCH v4 3/5] arm:mx6sx add QSPI support

2014-12-30 Thread Peng Fan
Add QSPI support for mx6solox.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 None

Changes v3:
 None

Changes v2:
 Take Fabio's suggestion, split soc code and board code into two patches.

 arch/arm/cpu/armv7/mx6/clock.c   | 50 
 arch/arm/include/asm/arch-mx6/clock.h|  1 +
 arch/arm/include/asm/arch-mx6/imx-regs.h | 12 
 drivers/spi/fsl_qspi.c   | 19 
 4 files changed, 76 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 93a02ad..a05dca3 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -434,6 +434,56 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
+#ifdef CONFIG_MX6SX
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+   u32 reg = 0;
+   /* Enable QuadSPI clock */
+   switch (qspi_num) {
+   case 0:
+   /* disable the clock gate */
+   clrbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cscmr1);
+   reg = ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+   reg |= ((1  MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+   (2  MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+   writel(reg, imx_ccm-cscmr1);
+
+   /* enable the clock gate */
+   setbits_le32(imx_ccm-CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+   break;
+   case 1:
+   /*
+* disable the clock gate
+* QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+* disable both of them.
+*/
+   clrbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+   /* set 50M  : (50 = 396 / 2 / 4) */
+   reg = readl(imx_ccm-cs2cdr);
+   reg = ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+   reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+   MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+   writel(reg, imx_ccm-cs2cdr);
+
+   /*enable the clock gate*/
+   setbits_le32(imx_ccm-CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+   break;
+   default:
+   break;
+   }
+}
+#endif
+
 #ifdef CONFIG_FEC_MXC
 int enable_fec_anatop_clock(enum enet_freq freq)
 {
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 226a4cd..a6de5ee 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -67,5 +67,6 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h 
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5314298..c968600 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -92,10 +92,10 @@
 #define AIPS3_END_ADDR 0x022F
 #define WEIM_ARB_BASE_ADDR  0x5000
 #define WEIM_ARB_END_ADDR   0x57FF
-#define QSPI1_ARB_BASE_ADDR 0x6000
-#define QSPI1_ARB_END_ADDR  0x6FFF
-#define QSPI2_ARB_BASE_ADDR 0x7000
-#define QSPI2_ARB_END_ADDR  0x7FFF
+#define QSPI0_AMBA_BASE0x6000
+#define QSPI0_AMBA_END 0x6FFF
+#define QSPI1_AMBA_BASE0x7000
+#define QSPI1_AMBA_END 0x7FFF
 #else
 #define SATA_ARB_BASE_ADDR  0x0220
 #define SATA_ARB_END_ADDR   0x02203FFF
@@ -262,8 +262,8 @@
 #define AUDMUX_BASE_ADDR(AIPS2_OFF_BASE_ADDR + 0x58000)
 #ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6)
-#define QSPI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6)
+#define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x6)
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index eae2f3a..e9c45de 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,11

[U-Boot] [PATCH v4 5/5] imx:mx6sxsabresd add qspi support

2014-12-30 Thread Peng Fan
Configure the pad setting and enable qspi clock to support qspi
flashes access.

Add QSPI related macro in configuration header file.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v4:
 None

Changes v3:
 None

Changes v2:
 Take Fabio's suggestion, split soc code and board code into two patches.

 board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 +
 include/configs/mx6sxsabresd.h  | 12 +
 2 files changed, 52 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index fd8bc72..5cc58ac 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -371,6 +371,42 @@ int board_mmc_init(bd_t *bis)
return 0;
 }
 
+#ifdef CONFIG_FSL_QSPI
+
+#define QSPI_PAD_CTRL1 \
+   (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
+PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
+
+static iomux_v3_cfg_t const quadspi_pads[] = {
+   MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_CLE__QSPI2_A_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA07__QSPI2_A_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA02__QSPI2_B_SCLK   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+   MX6_PAD_NAND_DATA05__QSPI2_B_DQS| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+
+int board_qspi_init(void)
+{
+   /* Set the iomux */
+   imx_iomux_v3_setup_multiple_pads(quadspi_pads,
+ARRAY_SIZE(quadspi_pads));
+
+   /* Set the clock */
+   enable_qspi_clk(1);
+
+   return 0;
+}
+#endif
+
 int board_init(void)
 {
/* Address of boot parameters */
@@ -380,6 +416,10 @@ int board_init(void)
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, i2c_pad_info1);
 #endif
 
+#ifdef CONFIG_FSL_QSPI
+   board_qspi_init();
+#endif
+
return 0;
 }
 
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 61a7a7a..469d250 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -235,6 +235,18 @@
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
 
+#define CONFIG_FSL_QSPI
+
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_FSL_QSPI_LE
+#define FSL_QSPI_FLASH_SIZESZ_16M
+#define FSL_QSPI_FLASH_NUM 2
+#endif
+
 #define CONFIG_ENV_OFFSET  (6 * SZ_64K)
 #define CONFIG_ENV_SIZESZ_8K
 #define CONFIG_ENV_IS_IN_MMC
-- 
1.8.4


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Re: [U-Boot] [PATCH v2 1/2] arm:mx6sx add QSPI support

2014-12-30 Thread Peng Fan

Hi,

On 12/30/2014 9:19 PM, Fabio Estevam wrote:

On Tue, Dec 30, 2014 at 11:16 AM, Jagan Teki jagannadh.t...@gmail.com wrote:


Please rebase and send the patches again, I have some issues while applying.
I will pick these on my tree.


Peng, please rebase and resend the series. Thanks


After rebasing, I sent a v4 patch set. Please review.

Thanks,
Peng Fan.
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Re: [U-Boot] [PATCH] imx:mx6slevk add spi nor boot support

2014-12-30 Thread Peng Fan

Hi Jagan,

On 12/30/2014 8:38 PM, Jagan Teki wrote:

On 30 December 2014 at 08:44, Peng Fan peng@freescale.com wrote:

Add spi nor boot support for mx6slevk board.

Signed-off-by: Peng Fan peng@freescale.com
---
  board/freescale/mx6slevk/MAINTAINERS |  1 +
  configs/mx6slevk_spinor_defconfig|  3 +++
  include/configs/mx6slevk.h   | 13 -
  3 files changed, 16 insertions(+), 1 deletion(-)
  create mode 100644 configs/mx6slevk_spinor_defconfig

diff --git a/board/freescale/mx6slevk/MAINTAINERS 
b/board/freescale/mx6slevk/MAINTAINERS
index 660af91..18d31a8 100644
--- a/board/freescale/mx6slevk/MAINTAINERS
+++ b/board/freescale/mx6slevk/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
  F: board/freescale/mx6slevk/
  F: include/configs/mx6slevk.h
  F: configs/mx6slevk_defconfig
+F: configs/mx6slevk_spinor_defconfig
diff --git a/configs/mx6slevk_spinor_defconfig 
b/configs/mx6slevk_spinor_defconfig
new file mode 100644
index 000..93efe73
--- /dev/null
+++ b/configs/mx6slevk_spinor_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL,SYS_BOOT_SPINOR
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SLEVK=y
diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index e3e7f76..e6c4130 100644
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -187,9 +187,20 @@
  /* FLASH and environment organization */
  #define CONFIG_SYS_NO_FLASH

-#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
  #define CONFIG_ENV_SIZESZ_8K
+
+#if defined CONFIG_SYS_BOOT_SPINOR
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET   (768 * 1024)
+#define CONFIG_ENV_SECT_SIZE(64 * 1024)
+#define CONFIG_ENV_SPI_BUS  CONFIG_SF_DEFAULT_BUS
+#define CONFIG_ENV_SPI_CS   CONFIG_SF_DEFAULT_CS
+#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
+#define CONFIG_ENV_SPI_MAX_HZ   CONFIG_SF_DEFAULT_SPEED


If you need default values may be you couldn't define these so-that
common/env_sf.c
will take the defaults for undefs - please check.



Default values are defined in mx6slevk.h

#define CONFIG_SF_DEFAULT_BUS  0
#define CONFIG_SF_DEFAULT_CS   0
#define CONFIG_SF_DEFAULT_SPEED 2000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0

In env_sf.c
I did not see any undefs, there is only a piece of code like:
#ifndef CONFIG_ENV_SPI_BUS
#define CONFIG_ENV_SPI_BUS 0
#endif


+#else
+#define CONFIG_ENV_OFFSET  (6 * SZ_64K)
  #define CONFIG_ENV_IS_IN_MMC
+#endif

  #define CONFIG_OF_LIBFDT
  #define CONFIG_CMD_BOOTZ
--
1.8.4



thanks!


Regards,
Peng Fan
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Re: [U-Boot] [PATCH v4 0/5] qspi: qspi support for mx6sxsabresd

2014-12-31 Thread Peng Fan



On 12/31/2014 5:35 PM, Jagan Teki wrote:

On 31 December 2014 at 08:31, Peng Fan peng@freescale.com wrote:

This patch set is to support qspi for mx6sxsabresd board.

To mx6sxsabresd Revb board, 32M flash is used, but in header file,
CONFIG_SPI_FLASH_BAR is not defined, and we still use SZ_16M. The LUT
initialization qspi_set_lut function uses 32BIT addr, however
CONFIG_SPI_FLASH_BAR  and 24BIT addr should be used to access
bigger than 16MB size flash, and BRRD/BRWR should also be supported.
Future patches will fix this.


Please do remember your self, for next patches. of-course I have added this
note on [U-Boot,v4,5/5] imx:mx6sxsabresd add qspi support commit body.



Thanks. Actually I am doing the work.



Since flash opcodes are not recommended to use in driver level, use
QSPI_CMD_xx to replace OPCODE_xx. It is qspi controller's feature
to program LUT with QSPI_CMD_xx which same value with OPCODE_xx.

Since Revb board's qspi flash support 4K erase, 4K erase is added in driver.

Peng Fan (5):
   QuadSPI: use QSPI_CMD_xx instead of flash opcodes
   QuadSPI: use correct amba_base
   arm:mx6sx add QSPI support
   imx:qspi add 4K erase support
   imx:mx6sxsabresd add qspi support

  arch/arm/cpu/armv7/mx6/clock.c  |  50 ++
  arch/arm/include/asm/arch-mx6/clock.h   |   1 +
  arch/arm/include/asm/arch-mx6/imx-regs.h|  12 +--
  board/freescale/mx6sxsabresd/mx6sxsabresd.c |  40 
  drivers/spi/fsl_qspi.c  | 137 +++-
  include/configs/mx6sxsabresd.h  |  12 +++
  6 files changed, 205 insertions(+), 47 deletions(-)

--
1.8.4




Applied to u-boot-spi/master

thanks!


Regards,
Peng.
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Re: [U-Boot] [PATCH v3 1/4] dm: introduce dev_get_addr interface

2015-02-05 Thread Peng Fan

Hi, Simon

On 1/23/2015 5:25 AM, Simon Glass wrote:

Hi,

On 21 January 2015 at 04:09, Peng Fan peng@freescale.com wrote:

Abstracting dev_get_addr can improve drivers that want to
get device's address.

Signed-off-by: Peng Fan peng@freescale.com
---
  drivers/core/device.c | 19 +++
  1 file changed, 19 insertions(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index 963b16f..0ba5c76 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -12,6 +12,7 @@
  #include common.h
  #include fdtdec.h
  #include malloc.h
+#include libfdt.h
  #include dm/device.h
  #include dm/device-internal.h
  #include dm/lists.h
@@ -390,3 +391,21 @@ ulong dev_get_of_data(struct udevice *dev)
  {
 return dev-of_id-data;
  }
+
+#ifdef CONFIG_OF_CONTROL
+void *dev_get_addr(struct udevice *dev)

My approach so far has been to use a ulong for the device address
(e.g. in platform data) and only use a pointer when we know the type
(e.g. struct disp_ctlr *), typically in driver-private data.

So do you think it would be better to return FDT_ADDR_T_NONE?

Sorry for the long time delay to reply.
Do you agree this way using ulong as the return type?

#ifdef CONFIG_OF_CONTROL
unsigned long dev_get_addr(struct udevice *dev)
{
fdt_addr_t addr;
addr = fdtdec_get_addr(gd-fdt_blob, dev-of_offset, reg);
return addr;
}
#else
unsigned long dev_get_addr(struct udevice *dev)
{
return FDT_ADDR_T_NONE;
}
#endif

Is it better to move this piece of code to include/dm/device.h and using 
static inline prototype? or put them still in driver/core/device.c?

+{
+   fdt_addr_t addr;
+
+   addr = fdtdec_get_addr(gd-fdt_blob, dev-of_offset, reg);
+   if (addr == FDT_ADDR_T_NONE)
+   return NULL;
+   else
+   return (void *)addr;
+}
+#else
+void *dev_get_addr(struct udevice *dev)
+{
+   return NULL;
+}
+#endif
--
1.8.4



Regards,
Simon

Thanks,
Peng.
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Re: [U-Boot] [PATCH 6/6] imx:mx6sxsabresd board spl support

2015-02-05 Thread Peng Fan

Hi Nikolay,

On 2/2/2015 6:24 PM, Nikolay Dimitrov wrote:

Hi Peng,

On 01/19/2015 10:29 AM, Peng Fan wrote:

Hi  Stefano,

On 1/19/2015 4:18 PM, Stefano Babic wrote:

Hi Peng,

series looks ok to me - just a small question:

On 30/12/2014 10:24, Peng Fan wrote:

Add board level spl support for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
---
  board/freescale/mx6sxsabresd/MAINTAINERS|   1 +
  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168

  2 files changed, 169 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS
b/board/freescale/mx6sxsabresd/MAINTAINERS
index f52f300..c0f5d9c 100644
--- a/board/freescale/mx6sxsabresd/MAINTAINERS
+++ b/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -4,3 +4,4 @@ S:Maintained
  F:board/freescale/mx6sxsabresd/
  F:include/configs/mx6sxsabresd.h
  F:configs/mx6sxsabresd_defconfig
+F:configs/mx6sxsabresd_spl_defconfig
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index fd8bc72..74f6d40 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc)
  int board_mmc_init(bd_t *bis)
  {
+#ifndef CONFIG_SPL_BUILD
  int i, ret;
  /*
@@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis)
  }
  return 0;
+#else
+struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+u32 val;
+u32 port;
+
+val = readl(src_regs-sbmr1);
+
+if ((val  0xc0) != 0x40) {
+printf(Not boot from USDHC!\n);
+return -EINVAL;
+}
+
+port = (val  11)  0x3;
+printf(port %d\n, port);
+switch (port) {
+case 1:
+imx_iomux_v3_setup_multiple_pads(
+usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+break;
+case 2:
+imx_iomux_v3_setup_multiple_pads(
+usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+gpio_direction_input(USDHC3_CD_GPIO);
+gpio_direction_output(USDHC3_PWR_GPIO, 1);
+usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+break;
+case 3:
+imx_iomux_v3_setup_multiple_pads(
+usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+gpio_direction_input(USDHC4_CD_GPIO);
+usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+break;
+}
+
+gd-arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
+#endif
  }
  int board_init(void)
@@ -394,3 +436,129 @@ int checkboard(void)
  return 0;
  }
+
+#ifdef CONFIG_SPL_BUILD
+#include libfdt.h
+#include spl.h
+#include asm/arch/mx6-ddr.h
+
+const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+.dram_dqm0 = 0x0028,
+.dram_dqm1 = 0x0028,
+.dram_dqm2 = 0x0028,
+.dram_dqm3 = 0x0028,
+.dram_ras = 0x0020,
+.dram_cas = 0x0020,
+.dram_odt0 = 0x0020,
+.dram_odt1 = 0x0020,
+.dram_sdba2 = 0x,
+.dram_sdcke0 = 0x3000,
+.dram_sdcke1 = 0x3000,
+.dram_sdclk_0 = 0x0030,
+.dram_sdqs0 = 0x0028,
+.dram_sdqs1 = 0x0028,
+.dram_sdqs2 = 0x0028,
+.dram_sdqs3 = 0x0028,
+.dram_reset = 0x0020,
+};
+
+const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+.grp_addds = 0x0020,
+.grp_ddrmode_ctl = 0x0002,
+.grp_ddrpke = 0x,
+.grp_ddrmode = 0x0002,
+.grp_b0ds = 0x0028,
+.grp_b1ds = 0x0028,
+.grp_ctlds = 0x0020,
+.grp_ddr_type = 0x000c,
+.grp_b2ds = 0x0028,
+.grp_b3ds = 0x0028,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+.p0_mpwldectrl0 = 0x00290025,
+.p0_mpwldectrl1 = 0x00220022,
+.p0_mpdgctrl0 = 0x41480144,
+.p0_mpdgctrl1 = 0x01340130,
+.p0_mprddlctl = 0x3C3E4244,
+.p0_mpwrdlctl = 0x34363638,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+.mem_speed = 1600,
+.density = 4,
+.width = 32,
+.banks = 8,
+.rowaddr = 15,
+.coladdr = 10,
+.pagesz = 2,
+.trcd = 1375,
+.trcmin = 4875,
+.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+writel(0x, ccm-CCGR0);
+writel(0x, ccm-CCGR1);
+writel(0x, ccm-CCGR2);
+writel(0x, ccm-CCGR3);
+writel(0x, ccm-CCGR4);
+writel(0x, ccm-CCGR5);
+writel(0x, ccm-CCGR6);
+writel(0x, ccm-CCGR7);
+}
+

Is it ok to enable all clocks ? This is quite uncommon in U-Boot and it
can raise some issues when Linux is booted because it assumes that
clocks are turned off. Anyway, this is only a question: if this is ok
for you (I do not test on this board

[U-Boot] [PATCH] ARM: HYP/non-sec: relocation before enable secondary cores

2015-02-04 Thread Peng Fan
If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined,
smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr(
_smp_pen), before code is relocated to secure ram.
So need relocation to secure ram before enable secondary cores.

Signed-off-by: Peng Fan peng@freescale.com
---
 arch/arm/cpu/armv7/virt-v7.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index b69fd37..4cb8806 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -112,13 +112,20 @@ int armv7_init_nonsec(void)
for (i = 1; i = itlinesnr; i++)
writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i);
 
+   /*
+* Relocate secure section before any cpu runs in secure ram.
+* smp_kick_all_cpus may enable other cores and runs into secure
+* ram, so need to relocate secure section before enabling other
+* cores.
+*/
+   relocate_secure_section();
+
 #ifndef CONFIG_ARMV7_PSCI
smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1);
smp_kick_all_cpus();
 #endif
 
/* call the non-sec switching code on this CPU also */
-   relocate_secure_section();
secure_ram_addr(_nonsec_init)();
return 0;
 }
-- 
1.8.4


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Re: [U-Boot] [PATCH] dm:gpio:mxc get configuration from dtb

2015-01-19 Thread Peng Fan

Hi Simon,

On 1/20/2015 3:45 AM, Simon Glass wrote:

Hi Peng.

On 18 January 2015 at 23:11, Peng Fan peng@freescale.com wrote:

This patch supports getting gpios' configuration from dtb.
CONFIG_OF_CONTROL is used to indicated which part is for device tree,
and which is not.

This patch is already tested on mx6sxsabresd board. Since device tree
has not been upstreamed, if want to test this patch. The followings
need to be done.
  + pieces of code does not gpio_request when using gpio_direction_xxx and
etc, need to request gpio.
  + move the gpio settings from board_early_init_f to board_init
  + define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL
  + Add device tree file and do related configuration in
`make ARCH=arm menuconfig`


Sorry I am going to repeat some of Igor's comments...

I've seen Igor's comments.I'll address them.



Signed-off-by: Peng Fan peng@freescale.com
---
  drivers/gpio/mxc_gpio.c | 76 +
  1 file changed, 76 insertions(+)

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 8bb9e39..8603068 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -14,6 +14,10 @@
  #include asm/arch/imx-regs.h
  #include asm/gpio.h
  #include asm/io.h
+#ifdef CONFIG_OF_CONTROL
+#include fdtdec.h
+DECLARE_GLOBAL_DATA_PTR;
+#endif

Hopefully #ifdef not needed.

Ok. I'll try to remove them in v2 patch.



  enum mxc_gpio_direction {
 MXC_GPIO_DIRECTION_IN,
@@ -258,6 +262,7 @@ static const struct dm_gpio_ops gpio_mxc_ops = {
 .get_function   = mxc_gpio_get_function,
  };

+#ifndef CONFIG_OF_CONTROL
  static const struct mxc_gpio_plat mxc_plat[] = {
 { (struct gpio_regs *)GPIO1_BASE_ADDR },
 { (struct gpio_regs *)GPIO2_BASE_ADDR },
@@ -274,6 +279,7 @@ static const struct mxc_gpio_plat mxc_plat[] = {
 { (struct gpio_regs *)GPIO7_BASE_ADDR },
  #endif

Same here.


  };
+#endif

  static int mxc_gpio_probe(struct udevice *dev)
  {
@@ -283,7 +289,19 @@ static int mxc_gpio_probe(struct udevice *dev)
 int banknum;
 char name[18], *str;

+#ifdef CONFIG_OF_CONTROL
+   /*
+* In dts file add:
+* aliases {
+*  gpio0 = gpio1;
+*  gpio1 = gpio2;
+*  .
+* };
+* Then set banknum accoring dev's seq number. */
+   banknum = dev-seq;
+#else
 banknum = plat - mxc_plat;
+#endif
 sprintf(name, GPIO%d_, banknum + 1);
 str = strdup(name);
 if (!str)
@@ -295,14 +313,71 @@ static int mxc_gpio_probe(struct udevice *dev)
 return 0;
  }

+#ifdef CONFIG_OF_CONTROL
+static int mxc_gpio_bind(struct udevice *device)
+{
+   struct mxc_gpio_plat *plat = device-platdata;
+   struct gpio_regs *ctrl;
+
+   if (plat)
+   return 0;
+   /*
+* In the dts file, gpiox bank are as following:
+*  gpio1: gpio@0209c000 {
+*  compatible = fsl,imx6q-gpio, fsl,imx35-gpio;
+*  reg = 0x0209c000 0x4000;
+*  interrupts = 0 66 0x04 0 67 0x04;
+*  gpio-controller;
+*  #gpio-cells = 2;
+*  interrupt-controller;
+*  #interrupt-cells = 2;
+*  };
+*
+*  gpio2: gpio@020a {
+*  compatible = fsl,imx6q-gpio, fsl,imx35-gpio;
+*  reg = 0x020a 0x4000;
+*  interrupts = 0 68 0x04 0 69 0x04;
+*  gpio-controller;
+*  #gpio-cells = 2;
+*  interrupt-controller;
+*  #interrupt-cells = 2;
+*  };
+*
+* gpio1 is the 1st bank, gpio2 is the 2nd bank and gpio3 
+*/
+
+   ctrl = (struct gpio_regs *)fdtdec_get_addr(gd-fdt_blob,
+  device-of_offset, reg);
+   plat = calloc(1, sizeof(*plat));
+   if (!plat)
+   return -ENOMEM;
+
+   plat-regs = ctrl;
+
+   device-platdata = plat;
+
+   return 0;
+}
+
+static const struct udevice_id mxc_gpio_ids[] = {
+   { .compatible = fsl,imx35-gpio },
+   { }
+};
+#endif
+
  U_BOOT_DRIVER(gpio_mxc) = {
 .name   = gpio_mxc,
 .id = UCLASS_GPIO,
 .ops= gpio_mxc_ops,
 .probe  = mxc_gpio_probe,
 .priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+#ifdef CONFIG_OF_CONTROL
+   .of_match = mxc_gpio_ids,
+   .bind   = mxc_gpio_bind,
+#endif
  };

+#ifndef CONFIG_OF_CONTROL
  U_BOOT_DEVICES(mxc_gpios) = {
 { gpio_mxc, mxc_plat[0] },
 { gpio_mxc, mxc_plat[1] },
@@ -320,3 +395,4 @@ U_BOOT_DEVICES(mxc_gpios) = {
  #endif
  };
  #endif
+#endif

Overall I wonder why you don't just convert the boards to device tree?
It might be more work, but it would be a lot cleaner.
Yeah. Agree. Converting the boards to device tree may

Re: [U-Boot] [PATCH 6/6] imx:mx6sxsabresd board spl support

2015-01-19 Thread Peng Fan

Hi  Stefano,

On 1/19/2015 4:18 PM, Stefano Babic wrote:

Hi Peng,

series looks ok to me - just a small question:

On 30/12/2014 10:24, Peng Fan wrote:

Add board level spl support for mx6sxsabresd board.

Signed-off-by: Peng Fan peng@freescale.com
---
  board/freescale/mx6sxsabresd/MAINTAINERS|   1 +
  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 
  2 files changed, 169 insertions(+)

diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS 
b/board/freescale/mx6sxsabresd/MAINTAINERS
index f52f300..c0f5d9c 100644
--- a/board/freescale/mx6sxsabresd/MAINTAINERS
+++ b/board/freescale/mx6sxsabresd/MAINTAINERS
@@ -4,3 +4,4 @@ S:  Maintained
  F:board/freescale/mx6sxsabresd/
  F:include/configs/mx6sxsabresd.h
  F:configs/mx6sxsabresd_defconfig
+F: configs/mx6sxsabresd_spl_defconfig
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c 
b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index fd8bc72..74f6d40 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc)
  
  int board_mmc_init(bd_t *bis)

  {
+#ifndef CONFIG_SPL_BUILD
int i, ret;
  
  	/*

@@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis)
}
  
  	return 0;

+#else
+   struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+   u32 val;
+   u32 port;
+
+   val = readl(src_regs-sbmr1);
+
+   if ((val  0xc0) != 0x40) {
+   printf(Not boot from USDHC!\n);
+   return -EINVAL;
+   }
+
+   port = (val  11)  0x3;
+   printf(port %d\n, port);
+   switch (port) {
+   case 1:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+   break;
+   case 2:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+   gpio_direction_input(USDHC3_CD_GPIO);
+   gpio_direction_output(USDHC3_PWR_GPIO, 1);
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
+   break;
+   case 3:
+   imx_iomux_v3_setup_multiple_pads(
+   usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+   gpio_direction_input(USDHC4_CD_GPIO);
+   usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+   usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
+   break;
+   }
+
+   gd-arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+   return fsl_esdhc_initialize(bis, usdhc_cfg[0]);
+#endif
  }
  
  int board_init(void)

@@ -394,3 +436,129 @@ int checkboard(void)
  
  	return 0;

  }
+
+#ifdef CONFIG_SPL_BUILD
+#include libfdt.h
+#include spl.h
+#include asm/arch/mx6-ddr.h
+
+const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+   .dram_dqm0 = 0x0028,
+   .dram_dqm1 = 0x0028,
+   .dram_dqm2 = 0x0028,
+   .dram_dqm3 = 0x0028,
+   .dram_ras = 0x0020,
+   .dram_cas = 0x0020,
+   .dram_odt0 = 0x0020,
+   .dram_odt1 = 0x0020,
+   .dram_sdba2 = 0x,
+   .dram_sdcke0 = 0x3000,
+   .dram_sdcke1 = 0x3000,
+   .dram_sdclk_0 = 0x0030,
+   .dram_sdqs0 = 0x0028,
+   .dram_sdqs1 = 0x0028,
+   .dram_sdqs2 = 0x0028,
+   .dram_sdqs3 = 0x0028,
+   .dram_reset = 0x0020,
+};
+
+const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+   .grp_addds = 0x0020,
+   .grp_ddrmode_ctl = 0x0002,
+   .grp_ddrpke = 0x,
+   .grp_ddrmode = 0x0002,
+   .grp_b0ds = 0x0028,
+   .grp_b1ds = 0x0028,
+   .grp_ctlds = 0x0020,
+   .grp_ddr_type = 0x000c,
+   .grp_b2ds = 0x0028,
+   .grp_b3ds = 0x0028,
+};
+
+const struct mx6_mmdc_calibration mx6_mmcd_calib = {
+   .p0_mpwldectrl0 = 0x00290025,
+   .p0_mpwldectrl1 = 0x00220022,
+   .p0_mpdgctrl0 = 0x41480144,
+   .p0_mpdgctrl1 = 0x01340130,
+   .p0_mprddlctl = 0x3C3E4244,
+   .p0_mpwrdlctl = 0x34363638,
+};
+
+static struct mx6_ddr3_cfg mem_ddr = {
+   .mem_speed = 1600,
+   .density = 4,
+   .width = 32,
+   .banks = 8,
+   .rowaddr = 15,
+   .coladdr = 10,
+   .pagesz = 2,
+   .trcd = 1375,
+   .trcmin = 4875,
+   .trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+   struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   writel(0x, ccm-CCGR0);
+   writel(0x, ccm-CCGR1);
+   writel(0x, ccm-CCGR2);
+   writel(0x, ccm-CCGR3);
+   writel(0x, ccm-CCGR4);
+   writel(0x, ccm-CCGR5);
+   writel(0x, ccm-CCGR6);
+   writel(0x, ccm

[U-Boot] [PATCH] dm:gpio:mxc get configuration from dtb

2015-01-18 Thread Peng Fan
This patch supports getting gpios' configuration from dtb.
CONFIG_OF_CONTROL is used to indicated which part is for device tree,
and which is not.

This patch is already tested on mx6sxsabresd board. Since device tree
has not been upstreamed, if want to test this patch. The followings
need to be done.
 + pieces of code does not gpio_request when using gpio_direction_xxx and
   etc, need to request gpio.
 + move the gpio settings from board_early_init_f to board_init
 + define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL
 + Add device tree file and do related configuration in
   `make ARCH=arm menuconfig`

Signed-off-by: Peng Fan peng@freescale.com
---
 drivers/gpio/mxc_gpio.c | 76 +
 1 file changed, 76 insertions(+)

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 8bb9e39..8603068 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -14,6 +14,10 @@
 #include asm/arch/imx-regs.h
 #include asm/gpio.h
 #include asm/io.h
+#ifdef CONFIG_OF_CONTROL
+#include fdtdec.h
+DECLARE_GLOBAL_DATA_PTR;
+#endif
 
 enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
@@ -258,6 +262,7 @@ static const struct dm_gpio_ops gpio_mxc_ops = {
.get_function   = mxc_gpio_get_function,
 };
 
+#ifndef CONFIG_OF_CONTROL
 static const struct mxc_gpio_plat mxc_plat[] = {
{ (struct gpio_regs *)GPIO1_BASE_ADDR },
{ (struct gpio_regs *)GPIO2_BASE_ADDR },
@@ -274,6 +279,7 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ (struct gpio_regs *)GPIO7_BASE_ADDR },
 #endif
 };
+#endif
 
 static int mxc_gpio_probe(struct udevice *dev)
 {
@@ -283,7 +289,19 @@ static int mxc_gpio_probe(struct udevice *dev)
int banknum;
char name[18], *str;
 
+#ifdef CONFIG_OF_CONTROL
+   /*
+* In dts file add:
+* aliases {
+*  gpio0 = gpio1;
+*  gpio1 = gpio2;
+*  .
+* };
+* Then set banknum accoring dev's seq number. */
+   banknum = dev-seq;
+#else
banknum = plat - mxc_plat;
+#endif
sprintf(name, GPIO%d_, banknum + 1);
str = strdup(name);
if (!str)
@@ -295,14 +313,71 @@ static int mxc_gpio_probe(struct udevice *dev)
return 0;
 }
 
+#ifdef CONFIG_OF_CONTROL
+static int mxc_gpio_bind(struct udevice *device)
+{
+   struct mxc_gpio_plat *plat = device-platdata;
+   struct gpio_regs *ctrl;
+
+   if (plat)
+   return 0;
+   /*
+* In the dts file, gpiox bank are as following:
+*  gpio1: gpio@0209c000 {
+*  compatible = fsl,imx6q-gpio, fsl,imx35-gpio;
+*  reg = 0x0209c000 0x4000;
+*  interrupts = 0 66 0x04 0 67 0x04;
+*  gpio-controller;
+*  #gpio-cells = 2;
+*  interrupt-controller;
+*  #interrupt-cells = 2;
+*  };
+*
+*  gpio2: gpio@020a {
+*  compatible = fsl,imx6q-gpio, fsl,imx35-gpio;
+*  reg = 0x020a 0x4000;
+*  interrupts = 0 68 0x04 0 69 0x04;
+*  gpio-controller;
+*  #gpio-cells = 2;
+*  interrupt-controller;
+*  #interrupt-cells = 2;
+*  };
+*
+* gpio1 is the 1st bank, gpio2 is the 2nd bank and gpio3 
+*/
+
+   ctrl = (struct gpio_regs *)fdtdec_get_addr(gd-fdt_blob,
+  device-of_offset, reg);
+   plat = calloc(1, sizeof(*plat));
+   if (!plat)
+   return -ENOMEM;
+
+   plat-regs = ctrl;
+
+   device-platdata = plat;
+
+   return 0;
+}
+
+static const struct udevice_id mxc_gpio_ids[] = {
+   { .compatible = fsl,imx35-gpio },
+   { }
+};
+#endif
+
 U_BOOT_DRIVER(gpio_mxc) = {
.name   = gpio_mxc,
.id = UCLASS_GPIO,
.ops= gpio_mxc_ops,
.probe  = mxc_gpio_probe,
.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+#ifdef CONFIG_OF_CONTROL
+   .of_match = mxc_gpio_ids,
+   .bind   = mxc_gpio_bind,
+#endif
 };
 
+#ifndef CONFIG_OF_CONTROL
 U_BOOT_DEVICES(mxc_gpios) = {
{ gpio_mxc, mxc_plat[0] },
{ gpio_mxc, mxc_plat[1] },
@@ -320,3 +395,4 @@ U_BOOT_DEVICES(mxc_gpios) = {
 #endif
 };
 #endif
+#endif
-- 
1.8.4


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Re: [U-Boot] [RFC PATCH] dm:spi:fsl_qspi add DM support

2015-01-18 Thread Peng Fan

Hi Jagan,

On 1/19/2015 2:47 PM, Jagan Teki wrote:

Hi Peng,

On 17 January 2015 at 11:29, Peng Fan peng@freescale.com wrote:

Hi Simon ,Jagan

This patch is based on git://git.denx.de/u-boot-spi.git master branch,
since some fsl_qspi's new feature is still in this git repo and have
not been merged to mainline.
I saw Simon sent out a new patch that remove the per_child_auto_alloc_size
from the platforms' driver code and move it to spi uclass driver. In
this patch I do not remove it, since this is a RFC version, and Jagan's
spi git repo still has it. I can remove it in formal version if needed.
Please take your time to review and comment this patch.

Appreciate for your work on adding dm on fsl-qspi.
But, I'm sending v2 RFC for spi-nor stuff where your driver be part of that
instead of drivers/spi - I'm planning to send it in this MW.

ok.

My plan is we review this dm stuff but in anyway if the new spi-nor is been
merged you'r driver needs to move on spi-nor with relevant changes.

Comments?


ok. I can do some work to make the driver match the new spi-nor stuff. 
If you have anytime, you can review the dm stuff.
There are small issues about register configuration in this patch, and I 
am fixing it in my side. Anyway, I'll wait your v2 patch, and based on 
your spi-nor stuff to add the dm stuff for fsl_qspi driver.



This patch adds DM support for fsl_qspi driver, the DM part needs
device tree support.

Partial of the original driver code is reused, such as the AHB part,
the LUT initialization and etc. The driver now supports new DM and original
driver by define CONFIG_DM_SPI. Until device tree is integrated, the
original part can be discarded.

The driver code file is now as following:
  

  Common code that needs both by DM or original driver code.

  #if defined(CONFIG_DM_SPI)

  DM part

  #else

  Original driver code

  #endif


In DM part, some reconstruction is done. A fsl_qspi_runcmd is included to
simplify the code, but not the original qspi_op_s. fsl_qspi_get_seqid
is included to get seqid, but not hardcoded in original qspi_op_s.

Signed-off-by: Peng Fan peng@freescale.com
---
  drivers/spi/fsl_qspi.c | 420 +++--
  drivers/spi/fsl_qspi.h |   1 +
  2 files changed, 405 insertions(+), 16 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 5e0b069..ee151b3 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -13,6 +13,13 @@
  #include linux/sizes.h
  #include fsl_qspi.h

+#ifdef CONFIG_DM_SPI
+#include dm.h
+#include fdtdec.h
+#include asm/errno.h
+#include spi_flash.h
+#endif
+
  #define RX_BUFFER_SIZE 0x80
  #ifdef CONFIG_MX6SX
  #define TX_BUFFER_SIZE 0x200
@@ -71,27 +78,41 @@
  #define qspi_write32   out_be32
  #endif

-static unsigned long spi_bases[] = {
-   QSPI0_BASE_ADDR,
-#ifdef CONFIG_MX6SX
-   QSPI1_BASE_ADDR,
-#endif
-};
+#ifdef CONFIG_DM_SPI
+DECLARE_GLOBAL_DATA_PTR;
+#define QUADSPI_AHBMAP_BANK_MAXSIZESZ_64M

-static unsigned long amba_bases[] = {
-   QSPI0_AMBA_BASE,
-#ifdef CONFIG_MX6SX
-   QSPI1_AMBA_BASE,
-#endif
+struct fsl_qspi_platdata {
+   u32 max_hz;
+   u32 reg_base;
+   u32 amba_base;
+   u32 flash_num;
  };

  struct fsl_qspi {
+   u32 reg_base;
+   u32 amba_base;
+   size_t  cmd_len;
+   u8  cmd_buf[32];
+   size_t  data_len;
+   int qspi_is_init;
+   size_t  flash_size;
+   u32 bank_memmap_phy[4];
+   int cs;
+   u32 sf_addr;
+   int flash_num;
+   u8  cur_seqid;
+   u32 freq;
+};
+#else
+struct fsl_qspi {
 struct spi_slave slave;
 unsigned long reg_base;
 unsigned long amba_base;
 u32 sf_addr;
 u8 cur_seqid;
  };
+#endif

  /* QSPI support swapping the flash read/write data
   * in hardware for LS102xA, but not for VF610 */
@@ -104,11 +125,6 @@ static inline u32 qspi_endian_xchg(u32 data)
  #endif
  }

-static inline struct fsl_qspi *to_qspi_spi(struct spi_slave *slave)
-{
-   return container_of(slave, struct fsl_qspi, slave);
-}
-
  static void qspi_set_lut(struct fsl_qspi *qspi)
  {
 struct fsl_qspi_regs *regs = (struct fsl_qspi_regs *)qspi-reg_base;
@@ -367,6 +383,377 @@ static void qspi_init_ahb_read(struct fsl_qspi_regs *regs)
  }
  #endif

+#ifdef CONFIG_DM_SPI
+/* Get the SEQID for the command */
+static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
+{
+   switch (cmd) {
+   case QSPI_CMD_FAST_READ:
+   case QSPI_CMD_FAST_READ_4B:
+   return SEQID_FAST_READ;
+   case QSPI_CMD_WREN:
+   return SEQID_WREN;
+   case QSPI_CMD_RDSR:
+   return SEQID_RDSR;
+   case QSPI_CMD_SE:
+   return SEQID_SE;
+   case QSPI_CMD_PP

Re: [U-Boot] [PATCH 2/2] mtd:mxs:nand support oobsize bigger than 512

2015-01-19 Thread Peng Fan

Hi Marek,

And this one.

On 12/19/2014 12:39 PM, Peng Fan wrote:

If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.

The following graph is modified from kernel gpmi-nand.c driver with each data
block 512 bytes.
We can see that Block Mark conflicts with ecc area from bch view.
We can enlarge the ecc chunk size to avoid this problem to those oobsize
which is larger than 512.

|  P|
|-|
|   |
|(Block Mark)   |
|  P' |   | |   |
|---| D | | O'|
| |-| |-|
V V   V V   V
+---+--+-+--+-+--+-+--+-+---+
| M |   data   |E|   data   |E|   data   |E|   data   |E|   |
+---+--+-+--+-+--+-+--+-+---+
 ^  ^
 | O|
 ||

P : the page size for BCH module.
E : The ECC strength.
G : the length of Galois Field.
N : The chunk count of per page.
M : the metasize of per page.
C : the ecc chunk size, aka the data above.
P': the nand chip's page size.
O : the nand chip's oob size.
O': the free oob.

Signed-off-by: Peng Fan peng@freescale.com
---
  arch/arm/include/asm/imx-common/regs-bch.h |  2 ++
  drivers/mtd/nand/mxs_nand.c| 33 ++
  2 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/imx-common/regs-bch.h 
b/arch/arm/include/asm/imx-common/regs-bch.h
index a33d341..5c47783 100644
--- a/arch/arm/include/asm/imx-common/regs-bch.h
+++ b/arch/arm/include/asm/imx-common/regs-bch.h
@@ -148,6 +148,7 @@ struct mxs_bch_regs {
  #define   BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf  12)
  #define   BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10  12)
  #define   BCH_FLASHLAYOUT0_GF13_0_GF14_1  (1  10)
+#defineBCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET   10
  #define   BCH_FLASHLAYOUT0_DATA0_SIZE_MASK0xfff
  #define   BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET  0
  
@@ -178,6 +179,7 @@ struct mxs_bch_regs {

  #define   BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf  12)
  #define   BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10  12)
  #define   BCH_FLASHLAYOUT1_GF13_0_GF14_1  (1  10)
+#defineBCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET   10
  #define   BCH_FLASHLAYOUT1_DATAN_SIZE_MASK0xfff
  #define   BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET  0
  
diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c

index a45fcf9..0db9eb3 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -29,6 +29,7 @@
  
  #define	MXS_NAND_DMA_DESCRIPTOR_COUNT		4
  
+#define	MXS_NAND_MAX_CHUNK_DATA_CHUNK_SIZE	1024

  #define   MXS_NAND_CHUNK_DATA_CHUNK_SIZE  512
  #if defined(CONFIG_MX6)
  #define   MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT2
@@ -68,6 +69,8 @@ struct mxs_nand_info {
  };
  
  struct nand_ecclayout fake_ecc_layout;

+static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+static int gf_len = 13;
  
  /*

   * Cache management functions
@@ -130,12 +133,12 @@ static void mxs_nand_return_dma_descs(struct 
mxs_nand_info *info)
  
  static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)

  {
-   return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
+   return page_data_size / chunk_data_size;
  }
  
  static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)

  {
-   return ecc_strength * 13;
+   return ecc_strength * gf_len;
  }
  
  static uint32_t mxs_nand_aux_status_offset(void)

@@ -149,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t 
page_data_size,
int ecc_strength;
  
  	ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)

-   / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
+   / (gf_len * mxs_nand_ecc_chunk_cnt(page_data_size));
  
  	return round_down(ecc_strength, 2);

  }
@@ -164,7 +167,7 @@ static inline uint32_t mxs_nand_get_mark_offset(uint32_t 
page_data_size,
uint32_t block_mark_chunk_bit_offset;
uint32_t block_mark_bit_offset

Re: [U-Boot] [PATCH 1/2] mtd:mxs:nand calculate ecc strength dynamically

2015-01-19 Thread Peng Fan

Hi Marek,

Since you are familiar with this driver, would you please help review 
this patch?


On 12/19/2014 12:39 PM, Peng Fan wrote:

Calculate ecc strength according oobsize, but not hardcoded
which is not aligned with kernel driver

Signed-off-by: Peng Fan peng@freescale.com
Signed-off-by: Ye.Li b37...@freescale.com
---
  drivers/mtd/nand/mxs_nand.c | 22 --
  1 file changed, 4 insertions(+), 18 deletions(-)

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 7a064ab..a45fcf9 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -146,26 +146,12 @@ static uint32_t mxs_nand_aux_status_offset(void)
  static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
uint32_t page_oob_size)
  {
-   if (page_data_size == 2048) {
-   if (page_oob_size == 64)
-   return 8;
+   int ecc_strength;
  
-		if (page_oob_size == 112)

-   return 14;
-   }
-
-   if (page_data_size == 4096) {
-   if (page_oob_size == 128)
-   return 8;
-
-   if (page_oob_size == 218)
-   return 16;
+   ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
+   / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
  
-		if (page_oob_size == 224)

-   return 16;
-   }
-
-   return 0;
+   return round_down(ecc_strength, 2);
  }
  
  static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,

Thanks,
Peng.
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[U-Boot] [PATCH v2] dm:gpio:mxc add DT support

2015-01-19 Thread Peng Fan
This patch add DT support for mxc gpio driver.

Include a bank_index entry in platdata. This can avoid using
`plat - mxc_plat` to calculate bank number. Also this can simplify code.

There are two places still using CONFIG_OF_CONTROL macro, just to
shrink code size if only support DM but not support DT.
1. The U_BOOT_DEVICES and mxc_plat array are complied out. To DT,
   platdata is alloced using calloc, so there is no need to use mxc_plat.
2. add a function mxc_get_gpio_addr to get reg property if DT support.
   If no DT, this function just returns NULL.

The following situations are tested:
1. with DM, without DT
2. with DM and DT
3. without DM
Since device tree has not been upstreamed, if want to test this patch.
The followings need to be done.
 + pieces of code does not gpio_request when using gpio_direction_xxx and
   etc, need to request gpio.
 + move the gpio settings from board_early_init_f to board_init
 + define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL
 + Add device tree file and do related configuration in
   `make ARCH=arm menuconfig`
These will be done in future patches by step.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
 1. remove uneccessary #ifdef
 2. add more stuff in commit log
 3. include a new function mxc_get_gpio_addr to get register base.
This function is different for DT and not DT, by `#ifdef`.
If using one implementation for DT and not DT, final image will be big.
 4. include a new entry in platdata, named bank_index. it can simplify DT
support. To no DT, bank_index is static initilized; to DT, bank_index
is get from device's req_seq.

 drivers/gpio/mxc_gpio.c | 89 +++--
 1 file changed, 71 insertions(+), 18 deletions(-)

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 8bb9e39..5826620 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -23,6 +23,7 @@ enum mxc_gpio_direction {
 #define GPIO_PER_BANK  32
 
 struct mxc_gpio_plat {
+   int bank_index;
struct gpio_regs *regs;
 };
 
@@ -150,6 +151,9 @@ int gpio_direction_output(unsigned gpio, int value)
 #endif
 
 #ifdef CONFIG_DM_GPIO
+#include fdtdec.h
+DECLARE_GLOBAL_DATA_PTR;
+
 static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
 {
u32 val;
@@ -258,23 +262,6 @@ static const struct dm_gpio_ops gpio_mxc_ops = {
.get_function   = mxc_gpio_get_function,
 };
 
-static const struct mxc_gpio_plat mxc_plat[] = {
-   { (struct gpio_regs *)GPIO1_BASE_ADDR },
-   { (struct gpio_regs *)GPIO2_BASE_ADDR },
-   { (struct gpio_regs *)GPIO3_BASE_ADDR },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-   defined(CONFIG_MX53) || defined(CONFIG_MX6)
-   { (struct gpio_regs *)GPIO4_BASE_ADDR },
-#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
-   { (struct gpio_regs *)GPIO5_BASE_ADDR },
-   { (struct gpio_regs *)GPIO6_BASE_ADDR },
-#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
-   { (struct gpio_regs *)GPIO7_BASE_ADDR },
-#endif
-};
-
 static int mxc_gpio_probe(struct udevice *dev)
 {
struct mxc_bank_info *bank = dev_get_priv(dev);
@@ -283,7 +270,7 @@ static int mxc_gpio_probe(struct udevice *dev)
int banknum;
char name[18], *str;
 
-   banknum = plat - mxc_plat;
+   banknum = plat-bank_index;
sprintf(name, GPIO%d_, banknum + 1);
str = strdup(name);
if (!str)
@@ -295,12 +282,77 @@ static int mxc_gpio_probe(struct udevice *dev)
return 0;
 }
 
+#ifdef CONFIG_OF_CONTROL
+static struct gpio_regs *mxc_get_gpio_addr(struct udevice *device)
+{
+   fdt_addr_t addr;
+   addr = fdtdec_get_addr(gd-fdt_blob, device-of_offset, reg);
+   if (addr == FDT_ADDR_T_NONE)
+   return NULL;
+   else
+   return (struct gpio_regs *)addr;
+}
+#else
+static struct gpio_regs *mxc_get_gpio_addr(struct udevice *device)
+{
+   return NULL;
+}
+#endif
+
+static int mxc_gpio_bind(struct udevice *device)
+{
+   struct mxc_gpio_plat *plat = device-platdata;
+   struct gpio_regs *regs;
+
+   if (plat)
+   return 0;
+
+   regs = mxc_get_gpio_addr(device);
+   if (!regs)
+   return -ENXIO;
+
+   plat = calloc(1, sizeof(*plat));
+   if (!plat)
+   return -ENOMEM;
+
+   plat-regs = regs;
+   plat-bank_index = device-req_seq;
+   device-platdata = plat;
+
+   return 0;
+}
+
+static const struct udevice_id mxc_gpio_ids[] = {
+   { .compatible = fsl,imx35-gpio },
+   { }
+};
+
 U_BOOT_DRIVER(gpio_mxc) = {
.name   = gpio_mxc,
.id = UCLASS_GPIO,
.ops= gpio_mxc_ops,
.probe  = mxc_gpio_probe,
.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+   .of_match = mxc_gpio_ids,
+   .bind   = mxc_gpio_bind,
+};
+
+#ifndef CONFIG_OF_CONTROL
+static

Re: [U-Boot] [PATCH 1/2] mtd:mxs:nand calculate ecc strength dynamically

2015-01-20 Thread Peng Fan

Hi, Marek

On 1/20/2015 7:04 PM, Marek Vasut wrote:

On Tuesday, January 20, 2015 at 07:35:26 AM, Peng Fan wrote:

Hi Marek,

Since you are familiar with this driver, would you please help review
this patch?

Hi!

I commented on both. Next time, please CC me and Stefano, since the patches
might slip just like this one did.

Thank you for this work !

Sorry for this and thanks for this tip.


Best regards,
Marek Vasut

Best regards,
Peng.
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Re: [U-Boot] [PATCH 2/2] mtd:mxs:nand support oobsize bigger than 512

2015-01-20 Thread Peng Fan

Hi, Marek

On 1/20/2015 7:03 PM, Marek Vasut wrote:

On Friday, December 19, 2014 at 05:39:13 AM, Peng Fan wrote:

If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.

The following graph is modified from kernel gpmi-nand.c driver with each
data block 512 bytes.
We can see that Block Mark conflicts with ecc area from bch view.
We can enlarge the ecc chunk size to avoid this problem to those oobsize
which is larger than 512.

What exactly is the impact of this patch for current installations of U-Boot?
Does the NAND need to be rewritten with new content? Is the format introduced
by this patch compatible with Linux?
The patch does not affect current installations of U-boot.  The NAND 
will not be rewritten with new content for chips whose oobsize is 
smaller than 512. To chips whose oobsize is bigger than 512, new 
format(saying gf_len is 14 and ecc chunk data size is 1024) introduced 
in this patch will be used.


This patch is to support nand chips whose oobsize bigger than 512, since 
the current mxs nand driver only supports oobisze smaller than 512. Data 
maybe corrupted if oobsize is bigger than 512 while ecc chunk data size 
is still 512, this is what this patch is try to fix. Yeah the format is 
compatible with gpmi-nand.c in linux.

Thanks!

Best regards,
Marek Vasut

Thanks,
Peng.
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Re: [U-Boot] [PATCH v3 4/4] dm:gpio:mxc add DT support

2015-01-21 Thread Peng Fan

Hi Igor,

Just kindly remind, did you miss this one? Since you ack the other 
patches in this patch set.


On 1/21/2015 7:09 PM, Peng Fan wrote:

This patch add DT support for mxc gpio driver.

There are one place using CONFIG_OF_CONTROL macro.
1. The U_BOOT_DEVICES and mxc_plat array are complied out. To DT,
platdata is alloced using calloc, so there is no need to use mxc_plat.

The following situations are tested, and all work fine:
1. with DM, without DT
2. with DM and DT
3. without DM
Since device tree has not been upstreamed, if want to test this patch.
The followings need to be done.
  + pieces of code does not gpio_request when using gpio_direction_xxx and
etc, need to request gpio.
  + move the gpio settings from board_early_init_f to board_init
  + define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL
  + Add device tree file and do related configuration in
`make ARCH=arm menuconfig`
These will be done in future patches by step.

Signed-off-by: Peng Fan peng@freescale.com
---
  drivers/gpio/mxc_gpio.c | 69 +
  1 file changed, 52 insertions(+), 17 deletions(-)

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index c52dd19..0766b78 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -151,6 +151,9 @@ int gpio_direction_output(unsigned gpio, int value)
  #endif
  
  #ifdef CONFIG_DM_GPIO

+#include fdtdec.h
+DECLARE_GLOBAL_DATA_PTR;
+
  static int mxc_gpio_is_output(struct gpio_regs *regs, int offset)
  {
u32 val;
@@ -259,23 +262,6 @@ static const struct dm_gpio_ops gpio_mxc_ops = {
.get_function   = mxc_gpio_get_function,
  };
  
-static const struct mxc_gpio_plat mxc_plat[] = {

-   { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
-   { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
-   { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-   defined(CONFIG_MX53) || defined(CONFIG_MX6)
-   { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
-#endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
-   { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
-   { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
-#endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
-   { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
-#endif
-};
-
  static int mxc_gpio_probe(struct udevice *dev)
  {
struct mxc_bank_info *bank = dev_get_priv(dev);
@@ -296,12 +282,60 @@ static int mxc_gpio_probe(struct udevice *dev)
return 0;
  }
  
+static int mxc_gpio_bind(struct udevice *device)

+{
+   struct mxc_gpio_plat *plat = device-platdata;
+   struct gpio_regs *regs;
+
+   if (plat)
+   return 0;
+
+   regs = dev_get_addr(device);
+   if (!regs)
+   return -ENXIO;
+
+   plat = calloc(1, sizeof(*plat));
+   if (!plat)
+   return -ENOMEM;
+
+   plat-regs = regs;
+   plat-bank_index = device-req_seq;
+   device-platdata = plat;
+
+   return 0;
+}
+
+static const struct udevice_id mxc_gpio_ids[] = {
+   { .compatible = fsl,imx35-gpio },
+   { }
+};
+
  U_BOOT_DRIVER(gpio_mxc) = {
.name   = gpio_mxc,
.id = UCLASS_GPIO,
.ops= gpio_mxc_ops,
.probe  = mxc_gpio_probe,
.priv_auto_alloc_size = sizeof(struct mxc_bank_info),
+   .of_match = mxc_gpio_ids,
+   .bind   = mxc_gpio_bind,
+};
+
+#ifndef CONFIG_OF_CONTROL
+static const struct mxc_gpio_plat mxc_plat[] = {
+   { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
+   { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
+   { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
+#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+   defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   { 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
+   { 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
+#endif
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+   { 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
+#endif
  };
  
  U_BOOT_DEVICES(mxc_gpios) = {

@@ -321,3 +355,4 @@ U_BOOT_DEVICES(mxc_gpios) = {
  #endif
  };
  #endif
+#endif

Thanks,
Peng.
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Re: [U-Boot] [PATCH v2 2/3] pmic:pfuze implement regulator mode set

2015-01-15 Thread Peng Fan

Hi, Przemyslaw

On 1/15/2015 10:58 PM, Przemyslaw Marczak wrote:

Hello Peng,

On 01/15/2015 11:18 AM, Peng Fan wrote:

This patch is to implement pfuze_mode_init and pfuze_regulator_mode_set
function, and add prototype in header file.

pfuze_mode_init is to set switching mode for all buck regulators to
improve system efficiency.
pfuze_regulator_mode_set is to set the regulator's mode according input
parameter.

Mode:
OFF: The regulator is switched off and the output voltage is discharged.
PFM: In this mode, the regulator is always in PFM mode, which
  is useful at light loads for optimized efficiency.
PWM: In this mode, the regulator is always in PWM mode operation
  regardless of load conditions.
APS: In this mode, the regulator moves automatically between
  pulse skipping mode and PWM mode depending on load conditions.

Signed-off-by: Peng Fan peng@freescale.com
---

Changes v2:
  implement one function mode for one regulator.

  board/freescale/common/pfuze.c | 43 
++

  board/freescale/common/pfuze.h |  2 ++
  2 files changed, 45 insertions(+)

diff --git a/board/freescale/common/pfuze.c 
b/board/freescale/common/pfuze.c

index 2cd1794..f2fffc1 100644
--- a/board/freescale/common/pfuze.c
+++ b/board/freescale/common/pfuze.c
@@ -8,6 +8,49 @@
  #include power/pmic.h
  #include power/pfuze100_pmic.h

+/* Set one switch regulator's mode */


This is not exactly what I mean.
Actually by doing this, we have pmic_reg_write() function with just 
the other name.



+int pfuze_regulator_mode_set(struct pmic *p, u32 regulator, u32 mode)
+{
+return pmic_reg_write(p, regulator, mode);
+}


The 'u32 regulator' suggests to pass the regulator number rather than 
defined mode register address - little unclear.


And the pfuze.. function name is general and should be implemented 
by pfuze driver, which could be 'temporary' implemented in:


drivers/power/pmic/pmic_pfuze100.c

And this driver should take care of the PFUZE id and write the given 
mode to proper pmic register address.


I mean 'temporary' because, soon we will move to the next pmic 
framework, finally I hope to send it at the end of the next week.



+
+/* Set all switch regulators' working mode */


So I think, that the below function without the loop could be 
implemented in the pfuze driver file.



+int pfuze_mode_init(struct pmic *p, u32 mode)


Starting with some like this:

int pfuze_sw_regulator_mode_set(struct pmic *p, u32 ??switch_num??, 
u32 mode)



+{
+unsigned char offset, i, switch_num;
+u32 id, ret;
+
+pmic_reg_read(p, PFUZE100_DEVICEID, id);
+id = id  0xf;
+
+if (id == 0) {
+switch_num = 6;
+offset = PFUZE100_SW1CMODE;
+} else if (id == 1) {
+switch_num = 4;
+offset = PFUZE100_SW2MODE;
+} else {
+printf(Not supported, id=%d\n, id);
+return -1;
+}
+

Ending with something like this:
ret = pmic_reg_write(p, offset + switch_num * 7, mode);
if (ret ...
...
}

And this code below can stay in the 'common.c' code, with small changes:
ret = pfuze_sw_regulator_mode_set(p, 1, mode);

+ret = pfuze_regulator_mode_set(p, PFUZE100_SW1ABMODE, mode);
+if (ret  0) {
+printf(Set SW1AB mode error!\n);
+return ret;
+}
+
+for (i = 0; i  switch_num - 1; i++) {


ret = pfuze_sw_regulator_mode_set(p, i, mode);


+ret = pfuze_regulator_mode_set(p, offset + i * 7, mode);
+if (ret  0) {
+printf(Set switch%x mode error!\n, offset + i * 7);
+return ret;
+}
+}
+
+return ret;
+}
+
  struct pmic *pfuze_common_init(unsigned char i2cbus)
  {
  struct pmic *p;
diff --git a/board/freescale/common/pfuze.h 
b/board/freescale/common/pfuze.h

index 7a4126c..7c316c6 100644
--- a/board/freescale/common/pfuze.h
+++ b/board/freescale/common/pfuze.h
@@ -8,5 +8,7 @@
  #define __PFUZE_BOARD_HELPER__

  struct pmic *pfuze_common_init(unsigned char i2cbus);
+int pfuze_mode_init(struct pmic *p, u32 mode);



+int pfuze_regulator_mode_set(struct pmic *p, u32 regulator, u32 mode);


And this:

int pfuze_sw_regulator_mode_set(...);

should go here:
include/power/pfuze100_pmic.h



  #endif



I suggested the 'sw' in the function name for the switching regulator 
type, so then we can pass just switching regulator number as an 
argument: e.g. 1,2,3...


And maybe in the future you will need ldo or some else regulator type,
so adding 'pfuze_ldo_regulator_mode_set' function, will keep the code 
consistence.


I would like to keep the driver specific code in driver file and 
common code in the common file.

Thanks for your review.
Get it.  I think this first version is fine for me now, this new feature 
can be done in future patch.


I think it is reasonable. If you now prefer to keep the first version 
of this patch set, then you have still my ACK for it:).


Best regards,

Regards,
Peng.
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