RE: [PATCH v3 00/21] imx9: various update
Hi Fabio, > Subject: Re: [PATCH v3 00/21] imx9: various update > > On Wed, Sep 18, 2024 at 11:58 PM Peng Fan (OSS) > wrote: > > > > Several updates to i.MX9 SOC and i.MX93 EVK, the related code has > been > > in NXP downstream for some time and gone through several public > > releases. Some are directly cherry-picked(with R-b kept), some are > > modified from downstream. > > Applied all to u-boot-imx/next, thanks. Thanks for your quick action. > > Next time, please send the contributions in smaller chunks. It is easier > to review and process. Indeed. We have lots of patches in downstream that we wanna upstream, we could separate in small patchsets, but that will also be many patchsets. such as patchset 1 is under reviewing, patchset 2 depends on patchset 1. Anyway, we will take care in future patches. Thanks, Peng.
[PATCH v3 21/21] imx93_evk: add back Low drive mode ddr timing file
From: Peng Fan
Add back low drive mode 1866mts ddr timing file, no need
CONFIG_IMX9_LOW_DRIVE_MODE anymore, using runtime selection.
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/Makefile |2 +-
board/freescale/imx93_evk/lpddr4x_timing_1866mts.c | 1995
board/freescale/imx93_evk/spl.c|9 +-
3 files changed, 2004 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx93_evk/Makefile
b/board/freescale/imx93_evk/Makefile
index 575f8e94604..ede8d20ff5c 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,5 +8,5 @@ obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o
endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
new file mode 100644
index 000..f4e910b2536
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.4.0_8.3-4e2b550a.
+ * DDR PHY FW2022.01
+ */
+
+#include
+#include
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x4411},
+ {0x4e30, 0x8000ff},
+ {0x4e38, 0x0},
+ {0x4e300080, 0x8512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x12552100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816B4AA},
+ {0x4e30010C, 0x0051E1E6},
+ {0x4e300124, 0x0E3A},
+ {0x4e300160, 0x9101},
+ {0x4e30016C, 0x3090},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x0014},
+ {0x4e300254, 0x00AA00AA},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ {0x4e300300, 0x11281109},
+ {0x4e300304, 0x00AA140A},
+ {0x4e300308, 0x063C071E},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x010A1000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x9492AA58},
+ {0x4e30010C, 0x00310113},
+ {0x4e300124, 0x071E},
+ {0x4e300160, 0x9100},
+ {0x4e30016C, 0x3020},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x000A},
+ {0x4e300254, 0x00510051},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C5},
+ {0x4e300160, 0x9100},
+ {0x4e30016C, 0x3000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x0007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11
[PATCH v3 20/21] imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig
From: Peng Fan
Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and
imx93_11x11_evk_ld_defconfig.
Remove the ld timing file.
The LD mode support will be added back with runtime detection later.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Kconfig|5 -
board/freescale/imx93_evk/Makefile|4 -
board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 -
configs/imx93_11x11_evk_ld_defconfig | 127 ---
4 files changed, 1632 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 63e75b6806e..4d32c28670d 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -5,11 +5,6 @@ config AHAB_BOOT
help
This option enables the support for AHAB secure boot.
-config IMX9_LOW_DRIVE_MODE
-bool "Configure to i.MX9 low drive mode"
-help
-This option enables the settings for iMX9 low drive mode.
-
config IMX9
bool
select BINMAN
diff --git a/board/freescale/imx93_evk/Makefile
b/board/freescale/imx93_evk/Makefile
index 17956d24bf7..575f8e94604 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,9 +8,5 @@ obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-ifdef CONFIG_IMX9_LOW_DRIVE_MODE
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o
-else
obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
endif
-endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
b/board/freescale/imx93_evk/lpddr4x_timing_ld.c
deleted file mode 100644
index f080322f112..000
--- a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
+++ /dev/null
@@ -1,1496 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2022 NXP
- *
- * Generated code from IMX_DDR_tool
- *
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
- */
-
-#include
-#include
-
-struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
- { 0x4e300110, 0x44140001 },
- { 0x4e301000, 0x0 },
- { 0x4e30, 0x8000ff },
- { 0x4e38, 0x0 },
- { 0x4e300080, 0x8512 },
- { 0x4e300084, 0x0 },
- { 0x4e300114, 0x2 },
- { 0x4e300260, 0x0 },
- { 0x4e30017c, 0x0 },
- { 0x4e300f04, 0x80 },
- { 0x4e300104, 0xaa77000e },
- { 0x4e300108, 0x1816b1aa },
- { 0x4e30010c, 0x5101e6 },
- { 0x4e300100, 0x12552100 },
- { 0x4e300160, 0x9002 },
- { 0x4e30016c, 0x3090 },
- { 0x4e300250, 0x14 },
- { 0x4e300254, 0xaa00aa },
- { 0x4e300258, 0x8 },
- { 0x4e30025c, 0x400 },
- { 0x4e300300, 0x11281109 },
- { 0x4e300304, 0xaa110a },
- { 0x4e300308, 0x620071e },
- { 0x4e300170, 0x8a0a0508 },
- { 0x4e300124, 0xe3c },
- { 0x4e300804, 0x1f1f1f1f },
- { 0x4e301240, 0x0 },
- { 0x4e301244, 0x0 },
- { 0x4e301248, 0x0 },
- { 0x4e30124c, 0x0 },
- { 0x4e301250, 0x0 },
- { 0x4e301254, 0x0 },
- { 0x4e301258, 0x0 },
- { 0x4e30125c, 0x0 },
-};
-
-/* PHY Initialize Configuration */
-struct dram_cfg_param ddr_ddrphy_cfg[] = {
- { 0x100a0, 0x4 },
- { 0x100a1, 0x5 },
- { 0x100a2, 0x6 },
- { 0x100a3, 0x7 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x1 },
- { 0x100a6, 0x2 },
- { 0x100a7, 0x3 },
- { 0x110a0, 0x3 },
- { 0x110a1, 0x2 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x1 },
- { 0x110a4, 0x7 },
- { 0x110a5, 0x6 },
- { 0x110a6, 0x4 },
- { 0x110a7, 0x5 },
- { 0x1005f, 0x5ff },
- { 0x1015f, 0x5ff },
- { 0x1105f, 0x5ff },
- { 0x1115f, 0x5ff },
- { 0x55, 0x1ff },
- { 0x1055, 0x1ff },
- { 0x2055, 0x1ff },
- { 0x200c5, 0xb },
- { 0x2002e, 0x2 },
- { 0x90204, 0x0 },
- { 0x20024, 0x1e3 },
- { 0x2003a, 0x2 },
- { 0x2007d, 0x212 },
- { 0x2007c, 0x61 },
- { 0x20056, 0x3 },
- { 0x1004d, 0xe00 },
- { 0x1014d, 0xe00 },
- { 0x1104d, 0xe00 },
- { 0x1114d, 0xe00 },
- { 0x10049, 0xe00 },
- { 0x10149, 0xe00 },
- { 0x11049, 0xe00 },
- { 0x11149, 0xe00 },
- { 0x43, 0x60 },
- { 0x1043, 0x60 },
- { 0x2043, 0x60 },
- { 0x20018, 0x1 },
- { 0x20075, 0x4 },
- { 0x20050, 0x0 },
- { 0x2009b, 0x2 },
- { 0x20008, 0x1d3 },
- { 0x20088, 0x9 },
- { 0x200b2, 0x10c },
- { 0x10043, 0x5a1 },
- { 0x10143, 0x5a1 },
- { 0x11043, 0x5a1 },
- { 0x11143, 0x5a1 },
- { 0x200fa, 0x2 },
- { 0x20019, 0x1 },
- { 0x200f0, 0x0 },
- { 0x200f1, 0x0 },
- { 0x200f2, 0x },
- { 0x200f3, 0x },
- { 0x200f4, 0x },
- { 0x200f5, 0x0 },
- { 0x200f6, 0x0 },
- { 0x200f7, 0xf000 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x
[PATCH v3 19/21] imx93_evk: spl: update pmic settings
From: Peng Fan
1. Use runtime voltage selection for LD/OD/ND mode.
2. According to latest PE/TE report, the voltages of VDD_SOC for
LD and ND mode need add 50mv margin, so LD voltage is 0.75v->0.8v,
ND voltage is 0.8v->0.85v.
3. Use TOFF_DEB to differentiate new trimmed pmic and old pmic
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/spl.c | 42 +++--
include/power/pca9450.h | 2 ++
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2ad7489ada7..503286ce3af 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -62,6 +62,7 @@ int power_init_board(void)
{
struct udevice *dev;
int ret;
+ unsigned int val = 0, buck_val;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
@@ -77,20 +78,41 @@ int power_init_board(void)
/* enable DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
- if (is_voltage_mode(VOLT_LOW_DRIVE))
- /* 0.75v for Low drive mode
-*/
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
+ ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ buck_val = 0x0c; /* 0.8v for Low drive mode */
+ printf("PMIC: Low Drive Voltage Mode\n");
+ } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+ buck_val = 0x10; /* 0.85v for Nominal drive mode */
+ printf("PMIC: Nominal Voltage Mode\n");
+ } else {
+ buck_val = 0x14; /* 0.9v for Over drive mode */
+ printf("PMIC: Over Drive Voltage Mode\n");
+ }
+
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
} else {
- /* 0.9v for Over drive mode
-*/
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+ }
+
+ if (IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)) {
+ /* Set VDDQ to 1.1V from buck2 */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
}
/* set standby voltage to 0.65v */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index b8219d535ad..f896d829d37 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -54,6 +54,8 @@ enum {
PCA9450_REG_NUM,
};
+#define PCA9450_REG_PWRCTRL_TOFF_DEBBIT(5)
+
int power_pca9450_init(unsigned char bus, unsigned char addr);
enum {
--
2.35.3
[PATCH v3 18/21] imx9: trdc: introduce trdc_mbc_blk_num
From: Peng Fan
Add trdc_mbc_blk_num to get num blks in a MBC mem slot, then drop
the hardcoded value '40' for NIC OCRAM configuration.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/trdc.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index ae1a46d1331..ef0f8b52a4d 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -19,6 +19,7 @@
#define MRC_MAX_NUM 2
#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+#define MBC_BLK_NUM(GLBCFG)((GLBCFG) & 0x3FF)
enum {
/* Order following ELE API Spec, not change */
@@ -154,6 +155,22 @@ static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
return trdc_reg + 0x1 + 0x2000 * mbc_num + 0x1000 * mrc_x;
}
+static u32 trdc_mbc_blk_num(ulong trdc_reg, u32 mbc_x, u32 mem_x)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc
*)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 glbcfg;
+
+ if (mbc_base == 0)
+ return 0;
+
+ /* only first dom has the glbcfg */
+ mbc_dom = &mbc_base->mem_dom[0];
+ glbcfg = readl((uintptr_t)&mbc_dom->mem_glbcfg[mem_x]);
+
+ return MBC_BLK_NUM(glbcfg);
+}
+
int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32
glbac_val)
{
struct trdc_mbc *mbc_base = (struct trdc_mbc
*)trdc_get_mbc_base(trdc_reg, mbc_x);
@@ -383,6 +400,7 @@ int release_rdc(u8 xrdc)
void trdc_early_init(void)
{
int ret = 0, i;
+ u32 blks;
ret |= release_rdc(TRDC_A);
ret |= release_rdc(TRDC_M);
@@ -397,7 +415,8 @@ void trdc_early_init(void)
/* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
trdc_mbc_set_control(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0), PERM(0x7700));
- for (i = 0; i < 40; i++) {
+ blks = trdc_mbc_blk_num(TRDC_NIC_BASE, MBC(3), MEM(0));
+ for (i = 0; i < blks; i++) {
trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i,
true, GLOBAL_ID(0));
--
2.35.3
[PATCH v3 17/21] imx9: trdc: cleanup code
From: Peng Fan
Replace magic number with meaningful macros.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 5 +
arch/arm/mach-imx/imx9/trdc.c | 156 ++
2 files changed, 101 insertions(+), 60 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index cb6b8a59cad..ef9538bd42e 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -50,6 +50,11 @@
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 1)
#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN(0x1 << 0)
+#define TRDC_AON_BASE (0x4427UL)
+#define TRDC_WAKEUP_BASE (0x4246UL)
+#define TRDC_MEGA_BASE (0x4281UL)
+#define TRDC_NIC_BASE (0x4901UL)
+
#define MARKETING_GRADING_MASK GENMASK(5, 4)
#define SPEED_GRADING_MASK GENMASK(11, 6)
#define NUM_WORDS_PER_BANK 8
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index 8cdb28459a3..ae1a46d1331 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -4,12 +4,13 @@
*/
#include
+#include
+#include
#include
#include
#include
#include
#include
-#include
#include
#include
@@ -19,6 +20,25 @@
#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+enum {
+ /* Order following ELE API Spec, not change */
+ TRDC_A,
+ TRDC_W,
+ TRDC_M,
+ TRDC_N,
+};
+
+/* Just make it easier to know what the parameter is */
+#define MBC(X) (X)
+#define MRC(X) (X)
+#define GLOBAL_ID(X) (X)
+#define MEM(X) (X)
+#define DOM(X) (X)
+/*
+ *0|SPR|SPW|SPX,0|SUR|SUW|SWX, 0|NPR|NPW|NPX, 0|NUR|NUW|NUX
+ */
+#define PERM(X)(X)
+
struct mbc_mem_dom {
u32 mem_glbcfg[4];
u32 nse_blk_index;
@@ -364,68 +384,84 @@ void trdc_early_init(void)
{
int ret = 0, i;
- ret |= release_rdc(0);
- ret |= release_rdc(2);
- ret |= release_rdc(1);
- ret |= release_rdc(3);
+ ret |= release_rdc(TRDC_A);
+ ret |= release_rdc(TRDC_M);
+ ret |= release_rdc(TRDC_W);
+ ret |= release_rdc(TRDC_N);
- if (!ret) {
- /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX
only */
- trdc_mbc_set_control(0x4901, 3, 0, 0x7700);
+ if (ret) {
+ hang();
+ return;
+ }
+
+ /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+ trdc_mbc_set_control(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0), PERM(0x7700));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 3, 0, i, true, 0);
+ for (i = 0; i < 40; i++) {
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 3, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(1), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 0, 0, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 0, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(1), i,
+ true, GLOBAL_ID(0));
}
}
void trdc_init(void)
{
/* TRDC mega */
- if (trdc_mrc_enabled(0x4901)) {
+ if (trdc_mrc_enabled(TRDC_NIC_BASE)) {
/* DDR */
- trdc_mrc_set_control(0x4901, 0, 0, 0x);
+ trdc_mrc_set_control(TRDC_NIC_BASE, MRC(0), GLOBAL_ID(0),
PERM(0x));
/* ELE */
- trdc_mrc_region_config(0x4901, 0, 0, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(0),
0x8000,
+ 0x, false, GLOBAL_ID(0));
/* MTR */
- trdc_mrc_region_config(0x4901, 0, 1, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(1),
0x8000,
+ 0x, false, GLOBAL_ID(0));
/* M33 */
- trdc_mrc_region_config(0x4901, 0, 2, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(2),
0x8000,
+ 0x,
[PATCH v3 16/21] imx: Generalize fixup_thermal_trips
From: Peng Fan
i.MX8M and i.MX9 have duplicated fixup_thermal_trips, so move it
to arch/arm/mach-imx/fdt.c to avoid duplicated code.
The critial temperature point for i.MX9 set to "maxc - 5" back to give
some margin.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
arch/arm/mach-imx/fdt.c | 42 +++
arch/arm/mach-imx/imx8m/soc.c | 42 ---
arch/arm/mach-imx/imx9/soc.c | 42 ---
4 files changed, 43 insertions(+), 84 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index c146a223b71..31ace977d2b 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -280,4 +280,5 @@ enum boot_device get_boot_device(void);
int disable_cpu_nodes(void *blob, const char * const *nodes_path,
u32 num_disabled_cores, u32 max_cores);
+int fixup_thermal_trips(void *blob, const char *name);
#endif
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
index df6fbf51dba..ac782e3ee63 100644
--- a/arch/arm/mach-imx/fdt.c
+++ b/arch/arm/mach-imx/fdt.c
@@ -85,3 +85,45 @@ int disable_cpu_nodes(void *blob, const char * const
*nodes_path, u32 num_disabl
return 0;
}
+
+int fixup_thermal_trips(void *blob, const char *name)
+{
+ int minc, maxc;
+ int node, trip;
+
+ node = fdt_path_offset(blob, "/thermal-zones");
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, name);
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, "trips");
+ if (node < 0)
+ return node;
+
+ get_cpu_temp_grade(&minc, &maxc);
+
+ fdt_for_each_subnode(trip, blob, node) {
+ const char *type;
+ int temp, ret;
+
+ type = fdt_getprop(blob, trip, "type", NULL);
+ if (!type)
+ continue;
+
+ temp = 0;
+ if (!strcmp(type, "critical"))
+ temp = 1000 * (maxc - 5);
+ else if (!strcmp(type, "passive"))
+ temp = 1000 * (maxc - 10);
+ if (temp) {
+ ret = fdt_setprop_u32(blob, trip, "temperature", temp);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index b8a026fb840..46974bf0618 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1215,48 +1215,6 @@ static int cleanup_nodes_for_efi(void *blob)
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
-{
- int minc, maxc;
- int node, trip;
-
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
-
- get_cpu_temp_grade(&minc, &maxc);
-
- fdt_for_each_subnode(trip, blob, node) {
- const char *type;
- int temp, ret;
-
- type = fdt_getprop(blob, trip, "type", NULL);
- if (!type)
- continue;
-
- temp = 0;
- if (!strcmp(type, "critical"))
- temp = 1000 * maxc;
- else if (!strcmp(type, "passive"))
- temp = 1000 * (maxc - 10);
- if (temp) {
- ret = fdt_setprop_u32(blob, trip, "temperature", temp);
- if (ret)
- return ret;
- }
- }
-
- return 0;
-}
-
#define OPTEE_SHM_SIZE 0x0040
static int ft_add_optee_node(void *fdt, struct bd_info *bd)
{
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 63647092782..04b21207a28 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -538,48 +538,6 @@ int print_cpuinfo(void)
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
-{
- int minc, maxc;
- int node, trip;
-
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
-
- get_
[PATCH v3 15/21] imx93: Add Low performance parts 9302/9301 support
From: Ye Li
Add support for iMX93 low performance parts 9302 and 9301 which
restrict to low drive voltage only.
The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU
and A55 core1 (9301) disabled.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 2 ++
arch/arm/include/asm/mach-imx/sys_proto.h | 5 -
arch/arm/mach-imx/imx9/Kconfig| 1 +
arch/arm/mach-imx/imx9/soc.c | 6 +-
drivers/cpu/imx8_cpu.c| 4
5 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index cbd2717f97c..b0468a1a136 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -68,6 +68,8 @@
#define MXC_CPU_IMX93210xC6 /* dummy ID */
#define MXC_CPU_IMX93120xC7 /* dummy ID */
#define MXC_CPU_IMX93110xC8 /* dummy ID */
+#define MXC_CPU_IMX93020xC9 /* dummy ID */
+#define MXC_CPU_IMX93010xCA /* dummy ID */
#define MXC_SOC_MX60x60
#define MXC_SOC_MX70x70
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index d93e095e191..c146a223b71 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -85,7 +85,8 @@ struct bd_info;
#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331)
|| \
is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
- is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
+ is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311) || \
+ is_cpu_type(MXC_CPU_IMX9302) || is_cpu_type(MXC_CPU_IMX9301))
#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
@@ -93,6 +94,8 @@ struct bd_info;
#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
+#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
+#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index e892da80fe8..63e75b6806e 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -30,6 +30,7 @@ choice
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
+ select OF_BOARD_FIXUP
select IMX93
imply OF_UPSTREAM
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index e3bfc8d51c5..63647092782 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -191,6 +191,10 @@ static u32 get_cpu_variant_type(u32 type)
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+ /* Low performance 93 part */
+ if (((val >> 6) & 0x3F) == 0xE && npu_disable)
+ return core1_disable ? MXC_CPU_IMX9301 : MXC_CPU_IMX9302;
+
if ((val2 & pack_9x9_fused) == pack_9x9_fused)
type = MXC_CPU_IMX9322;
@@ -704,7 +708,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
- if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311())
+ if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311() ||
is_imx9301())
disable_cpu_nodes(blob, nodes_path, 1, 2);
if (is_voltage_mode(VOLT_LOW_DRIVE))
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 60deca963a6..6c0a8c0cbe4 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -60,6 +60,10 @@ static const char *get_imx_type_str(u32 imxtype)
return "93(12)";/* iMX93 9x9 Dual core without NPU */
case MXC_CPU_IMX9311:
return "93(11)";/* iMX93 9x9 Single core without NPU */
+ case MXC_CPU_IMX9302:
+ return "93(02)";/* iMX93 900Mhz Low performance Dual core
without NPU */
+ case MXC_CPU_IMX9301:
+ return "93(01)";/* iMX93 900Mhz Low performance Single core
without NPU */
default:
return "??";
}
--
2.35.3
[PATCH v3 14/21] imx9: soc: Disable cpu1 for variants that only has one A55 core
From: Peng Fan
Disale CPU1 for i.MX93 variants that only has one A55 core and update
cooling maps.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/Makefile | 7 ++-
arch/arm/mach-imx/imx9/soc.c | 8
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 47e2cb8d943..f8903afc92e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,6 @@ endif
ifeq ($(SOC),$(filter $(SOC),imx8m))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
-obj-y += fdt.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
@@ -22,6 +21,12 @@ obj-$(CONFIG_IMX_HAB) += hab.o
obj-y += cpu.o
endif
+ifeq ($(SOC),$(filter $(SOC),imx8m imx9))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += fdt.o
+endif
+endif
+
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += cpu.o speed.o
ifneq ($(CONFIG_MX51),y)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 0d909c3e853..e3bfc8d51c5 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -696,9 +696,17 @@ int board_fix_fdt(void *fdt)
int ft_system_setup(void *blob, struct bd_info *bd)
{
+ static const char * const nodes_path[] = {
+ "/cpus/cpu@0",
+ "/cpus/cpu@100",
+ };
+
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
+ if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311())
+ disable_cpu_nodes(blob, nodes_path, 1, 2);
+
if (is_voltage_mode(VOLT_LOW_DRIVE))
low_drive_freq_update(blob);
--
2.35.3
[PATCH v3 13/21] imx: Generalize disable_cpu_nodes
From: Peng Fan
disable_cpu_nodes could be reused by i.MX9, so move disable_cpu_nodes
out from mach-imx/imx8m/soc.c to mach-imx/fdt.c and update
disable_cpu_nodes to make it easy to support different socs.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 +
arch/arm/mach-imx/Makefile| 1 +
arch/arm/mach-imx/fdt.c | 87 +++
arch/arm/mach-imx/imx8m/soc.c | 99 ---
4 files changed, 103 insertions(+), 86 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 31ae179b211..d93e095e191 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -275,4 +275,6 @@ void enable_ca7_smp(void);
enum boot_device get_boot_device(void);
+int disable_cpu_nodes(void *blob, const char * const *nodes_path,
+ u32 num_disabled_cores, u32 max_cores);
#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5262dca4ffd..47e2cb8d943 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,6 +12,7 @@ endif
ifeq ($(SOC),$(filter $(SOC),imx8m))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-y += fdt.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
new file mode 100644
index 000..df6fbf51dba
--- /dev/null
+++ b/arch/arm/mach-imx/fdt.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+static void disable_thermal_cpu_nodes(void *blob, u32 num_disabled_cores, u32
max_cores)
+{
+ static const char * const thermal_path[] = {
+ "/thermal-zones/cpu-thermal/cooling-maps/map0"
+ };
+
+ int nodeoff, cnt, i, ret, j;
+ u32 num_le32 = max_cores * 3;
+ u32 *cooling_dev = (u32 *)malloc(num_le32 * sizeof(__le32));
+
+ if (!cooling_dev) {
+ printf("failed to alloc cooling dev\n");
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+ nodeoff = fdt_path_offset(blob, thermal_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ cnt = fdtdec_get_int_array_count(blob, nodeoff,
"cooling-device",
+cooling_dev, num_le32);
+ if (cnt < 0)
+ continue;
+
+ if (cnt != num_le32)
+ printf("Warning: %s, cooling-device count %d\n",
thermal_path[i], cnt);
+
+ for (j = 0; j < cnt; j++)
+ cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+ ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+ sizeof(__le32) * (num_le32 -
num_disabled_cores * 3));
+ if (ret < 0) {
+ printf("Warning: %s, cooling-device setprop failed
%d\n",
+ thermal_path[i], ret);
+ continue;
+ }
+
+ printf("Update node %s, cooling-device prop\n",
thermal_path[i]);
+ }
+
+ free(cooling_dev);
+}
+
+int disable_cpu_nodes(void *blob, const char * const *nodes_path, u32
num_disabled_cores,
+ u32 max_cores)
+{
+ u32 i = 0;
+ int rc;
+ int nodeoff;
+
+ if (max_cores == 0 || (num_disabled_cores > (max_cores - 1)))
+ return -EINVAL;
+
+ i = max_cores - num_disabled_cores;
+
+ for (; i < max_cores; i++) {
+ nodeoff = fdt_path_offset(blob, nodes_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ debug("Found %s node\n", nodes_path[i]);
+
+ rc = fdt_del_node(blob, nodeoff);
+ if (rc < 0) {
+ printf("Unable to delete node %s, err=%s\n",
+ nodes_path[i], fdt_strerror(rc));
+ } else {
+ printf("Delete node %s\n", nodes_path[i]);
+ }
+ }
+
+ disable_thermal_cpu_nodes(blob, num_disabled_cores, max_cores);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 3a582cb43b5..b8a026fb840 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1184,79 +1184,6 @@ int disable_dsp_nodes(void *blob)
return disable_fdt_nodes(blob, nodes_path_8mp,
ARRAY_SIZE(nodes_path_8mp));
}
-static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char
[PATCH v3 12/21] imx8m: soc: Drop disable_pmu_cpu_nodes
From: Peng Fan
i.MX8M use PPI for PMU interrupts, there is no reason to update
interrupt-affinity for PMU even interrupt-affinity was wrongly added
to device tree before.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 38 --
1 file changed, 38 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 986687e9ce4..3a582cb43b5 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1220,43 +1220,6 @@ static void disable_thermal_cpu_nodes(void *blob, u32
disabled_cores)
}
}
-static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char * const pmu_path[] = {
- "/pmu"
- };
-
- int nodeoff, cnt, i, ret, j;
- u32 irq_affinity[4];
-
- for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
- nodeoff = fdt_path_offset(blob, pmu_path[i]);
- if (nodeoff < 0)
- continue; /* Not found, skip it */
-
- cnt = fdtdec_get_int_array_count(blob, nodeoff,
"interrupt-affinity",
-irq_affinity, 4);
- if (cnt < 0)
- continue;
-
- if (cnt != 4)
- printf("Warning: %s, interrupt-affinity count %d\n",
pmu_path[i], cnt);
-
- for (j = 0; j < cnt; j++)
- irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
-
- ret = fdt_setprop(blob, nodeoff, "interrupt-affinity",
&irq_affinity,
-sizeof(u32) * (4 - disabled_cores));
- if (ret < 0) {
- printf("Warning: %s, interrupt-affinity setprop failed
%d\n",
- pmu_path[i], ret);
- continue;
- }
-
- printf("Update node %s, interrupt-affinity prop\n",
pmu_path[i]);
- }
-}
-
static int disable_cpu_nodes(void *blob, u32 disabled_cores)
{
static const char * const nodes_path[] = {
@@ -1290,7 +1253,6 @@ static int disable_cpu_nodes(void *blob, u32
disabled_cores)
}
disable_thermal_cpu_nodes(blob, disabled_cores);
- disable_pmu_cpu_nodes(blob, disabled_cores);
return 0;
}
--
2.35.3
[PATCH v3 11/21] imx9: Add 233Mhz DDR PLL frequency
From: Ye Li
To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/clock.c | 1 +
drivers/ddr/imx/phy/ddrphy_utils.c | 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 76d19f1cba3..12685f970de 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -41,6 +41,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(46600U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(4U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(3U, 1, 150, 12, 0, 1),
+ FRAC_PLL_RATE(23300U, 1, 174, 18, 3, 4), /* 233Mhz */
};
/* return in khz */
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c
b/drivers/ddr/imx/phy/ddrphy_utils.c
index cf5bdad7abe..14278f5ad8f 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(266));
dram_disable_bypass();
break;
+ case 933:
+ dram_pll_init(MHZ(233));
+ dram_disable_bypass();
+ break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();
--
2.35.3
[PATCH v3 10/21] imx9: soc: Mask the wdog reset in src by default on i.mx9
From: Jacky Bai
Normally, the wdog will be used for trigger external PMIC reset
through the WDOG_ANY pin. If the PMIC chip has debounce logic for
the reset signal, in some corner case the wdog can NOT trigger
external PMIC reset if the SoC has been reset internal before the
PMIC captures the WDOG_ANY pin reset, so need to keep the WDOG3-5
reset masked in the SRC to let the PMIC to do the reset safely.
Reviewed-by: Ye Li
Signed-off-by: Jacky Bai
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 44e2166509d..0d909c3e853 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -240,15 +240,9 @@ static void disable_wdog(void __iomem *wdog_base)
void init_wdog(void)
{
- u32 src_val;
-
disable_wdog((void __iomem *)WDG3_BASE_ADDR);
disable_wdog((void __iomem *)WDG4_BASE_ADDR);
disable_wdog((void __iomem *)WDG5_BASE_ADDR);
-
- src_val = readl(0x54460018); /* reset mask */
- src_val &= ~0x1c;
- writel(src_val, 0x54460018);
}
static struct mm_region imx93_mem_map[] = {
--
2.35.3
[PATCH v3 09/21] imx9: clock: Update clock init function and sequence
From: Ye Li
Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 3 ++-
arch/arm/mach-imx/imx9/clock.c | 22 ++
arch/arm/mach-imx/imx9/soc.c | 2 +-
board/freescale/imx93_evk/spl.c| 4 +++-
board/phytec/phycore_imx93/spl.c | 2 +-
5 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index 1ce6ac4c3a8..76f12118592 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -211,7 +211,8 @@ struct imx_clk_setting {
u32 div;
};
-int clock_init(void);
+int clock_init_early(void);
+int clock_init_late(void);
u32 get_clk_src_rate(enum ccm_clk_src source);
u32 get_lpuart_clk(void);
void init_uart_clk(u32 index);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 1433e68874d..76d19f1cba3 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -782,17 +782,10 @@ void bus_clock_init(void)
}
}
-int clock_init(void)
+int clock_init_early(void)
{
int i;
- if (is_voltage_mode(VOLT_LOW_DRIVE)) {
- bus_clock_init_low_drive();
- set_arm_clk(MHZ(900));
- } else {
- bus_clock_init();
- }
-
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
ccm_clk_src_tz_access(i, true, false, false);
@@ -809,6 +802,19 @@ int clock_init(void)
return 0;
}
+/* Set bus and A55 core clock per voltage mode */
+int clock_init_late(void)
+{
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ bus_clock_init_low_drive();
+ set_arm_core_max_clk();
+ } else {
+ bus_clock_init();
+ }
+
+ return 0;
+}
+
int set_clk_eqos(enum enet_freq type)
{
u32 eqos_post_div;
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 52aafcbf99c..44e2166509d 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -741,7 +741,7 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
- clock_init();
+ clock_init_early();
trdc_early_init();
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index e4999baa95f..2ad7489ada7 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -123,9 +123,11 @@ void board_init_f(ulong dummy)
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
+ clock_init_late();
+
power_init_board();
- if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (!is_voltage_mode(VOLT_LOW_DRIVE))
set_arm_clk(get_cpu_speed_grade_hz());
/* Init power of mix */
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 5efa38a1442..17a8736c73f 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -130,7 +130,7 @@ void board_init_f(ulong dummy)
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
- clock_init();
+ clock_init_late();
power_init_board();
--
2.35.3
[PATCH v3 08/21] imx9: soc: Add function to get target voltage mode
From: Ye Li
Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target
voltage mode by checking the part's SPEED GRADE fuse.
SPL will configure to highest A55 speed which is indicated by the SPEED
fuse and select corresponding voltage mode.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/sys_proto.h | 11 +++
arch/arm/mach-imx/imx9/clock.c | 31 +++--
arch/arm/mach-imx/imx9/soc.c | 107 +
board/freescale/imx93_evk/spl.c| 2 +-
4 files changed, 143 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 2f7a1292758..e4bf6a63424 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -8,7 +8,18 @@
#include
+enum imx9_soc_voltage_mode {
+ VOLT_LOW_DRIVE = 0,
+ VOLT_NOMINAL_DRIVE,
+ VOLT_OVER_DRIVE,
+};
+
void soc_power_init(void);
bool m33_is_rom_kicked(void);
int m33_prepare(void);
+
+enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
+
+#define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
+
#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 0abf4579a1e..1433e68874d 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -603,7 +603,7 @@ void init_clk_usdhc(u32 index)
{
u32 div;
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
div = 3; /* 266.67 Mhz */
else
div = 2; /* 400 Mhz */
@@ -700,8 +700,7 @@ void set_arm_core_max_clk(void)
#endif
-#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)
-struct imx_clk_setting imx_clk_settings[] = {
+struct imx_clk_setting imx_clk_ld_settings[] = {
/* Set A55 clk to 500M */
{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
/* Set A55 periphal to 200M */
@@ -728,7 +727,7 @@ struct imx_clk_setting imx_clk_settings[] = {
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#else
+
struct imx_clk_setting imx_clk_settings[] = {
/*
* Set A55 clk to 500M. This clock root is normally used as intermediate
@@ -762,9 +761,18 @@ struct imx_clk_setting imx_clk_settings[] = {
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#endif
-int clock_init(void)
+void bus_clock_init_low_drive(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
+ ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
+imx_clk_ld_settings[i].src,
imx_clk_ld_settings[i].div);
+ }
+}
+
+void bus_clock_init(void)
{
int i;
@@ -772,9 +780,18 @@ int clock_init(void)
ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
imx_clk_settings[i].src,
imx_clk_settings[i].div);
}
+}
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+int clock_init(void)
+{
+ int i;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ bus_clock_init_low_drive();
set_arm_clk(MHZ(900));
+ } else {
+ bus_clock_init();
+ }
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index ba04abff262..52aafcbf99c 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -615,11 +615,99 @@ int arch_misc_init(void)
return 0;
}
+struct low_drive_freq_entry {
+ const char *node_path;
+ u32 clk;
+ u32 new_rate;
+};
+
+static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32
new_rate)
+{
+#define MAX_ASSIGNED_CLKS 8
+ int cnt, j;
+ u32 assignedclks[MAX_ASSIGNED_CLKS]; /* max 8 clocks*/
+
+ cnt = fdtdec_get_int_array_count(fdt, node_off, "assigned-clock-rates",
+assignedclks, MAX_ASSIGNED_CLKS);
+ if (cnt > 0) {
+ if (cnt <= clk_index)
+ return -ENOENT;
+
+ if (assignedclks[clk_index] <= new_rate)
+ return 0;
+
+ assignedclks[clk_index] = new_rate;
+ for (j = 0; j < cnt; j++)
+ assignedclks[j] = cpu_to_fdt32(assignedclks[j]);
+
+ return fdt_setprop(fdt, node_off, "assigned-clock-rates",
&assignedclks,
+ cnt * sizeof(u32));
+ }
+
+ return -ENOENT;
+}
+
+static int low_drive_freq_update(void *blob)
+{
+ int nodeoff, ret;
+ int i;
+
+ /* Update kernel dtb clocks for low drive mode */
+ struct low_drive_freq_entry table[] = {
+ {"/soc@0/bus@4280/mmc@4285", 0, 2
[PATCH v3 07/21] imx9: soc: Print ELE information
From: Peng Fan
The boot image includes Edgelock Enclave(ELE) Firmware. Print the
information out to let user know which version firmware is being used.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9494c739969..ba04abff262 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -582,6 +582,39 @@ static int fixup_thermal_trips(void *blob, const char
*name)
return 0;
}
+void build_info(void)
+{
+ u32 fw_version, sha1, res, status;
+ int ret;
+
+ printf("\nBuildInfo:\n");
+
+ ret = ele_get_fw_status(&status, &res);
+ if (ret) {
+ printf(" - ELE firmware status failed %d, 0x%x\n", ret, res);
+ } else if ((status & 0xff) == 1) {
+ ret = ele_get_fw_version(&fw_version, &sha1, &res);
+ if (ret) {
+ printf(" - ELE firmware version failed %d, 0x%x\n",
ret, res);
+ } else {
+ printf(" - ELE firmware version %u.%u.%u-%x",
+ (fw_version & (0x00ff)) >> 16,
+ (fw_version & (0xfff0)) >> 4,
+ (fw_version & (0x000f)), sha1);
+ ((fw_version & (0x8000)) >> 31) == 1 ?
puts("-dirty\n") : puts("\n");
+ }
+ } else {
+ printf(" - ELE firmware not included\n");
+ }
+ puts("\n");
+}
+
+int arch_misc_init(void)
+{
+ build_info();
+ return 0;
+}
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
if (fixup_thermal_trips(blob, "cpu-thermal"))
--
2.35.3
[PATCH v3 06/21] imx9: soc: Change second Ethernet MAC fuse layout
From: Ye Li
The second Ethernet MAC (eQOS) fuse layout is changed since i.MX93 A1
following other i.MX platforms, for example i.MX8MP.
Order for A0:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
Order since A1:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
MAC2_ADDR[47:32]
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 5699623027e..9494c739969 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -504,12 +504,21 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
if (ret)
goto err;
- mac[0] = val[1] >> 24;
- mac[1] = val[1] >> 16;
- mac[2] = val[0] >> 24;
- mac[3] = val[0] >> 16;
- mac[4] = val[0] >> 8;
- mac[5] = val[0];
+ if (is_imx93() && is_soc_rev(CHIP_REV_1_0)) {
+ mac[0] = val[1] >> 24;
+ mac[1] = val[1] >> 16;
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+ } else {
+ mac[0] = val[0] >> 24;
+ mac[1] = val[0] >> 16;
+ mac[2] = val[0] >> 8;
+ mac[3] = val[0];
+ mac[4] = val[1] >> 24;
+ mac[5] = val[1] >> 16;
+ }
}
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
--
2.35.3
[PATCH v3 05/21] imx9: soc: Change FSB directly access to fuse API
From: Peng Fan
To support OSCCA enabled part which has disabled FSB access from SOC,
change directly read from FSB to use fuse_read API.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 3 +++
arch/arm/mach-imx/imx9/soc.c | 38 +--
2 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index fb6de533d12..cb6b8a59cad 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -52,6 +52,9 @@
#define MARKETING_GRADING_MASK GENMASK(5, 4)
#define SPEED_GRADING_MASK GENMASK(11, 6)
+#define NUM_WORDS_PER_BANK 8
+#define HW_CFG119
+#define HW_CFG220
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index bdc569b4ae4..5699623027e 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -96,10 +96,16 @@ int mmc_get_env_dev(void)
*/
u32 get_cpu_speed_grade_hz(void)
{
- u32 speed, max_speed;
+ int ret;
+ u32 bank, word, speed, max_speed;
u32 val;
- fuse_read(2, 3, &val);
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF;
speed = MHZ(2300) - val * MHZ(100);
@@ -122,9 +128,15 @@ u32 get_cpu_speed_grade_hz(void)
*/
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
- u32 val;
+ int ret;
+ u32 bank, word, val;
+
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
- fuse_read(2, 3, &val);
val = FIELD_GET(MARKETING_GRADING_MASK, val);
if (minc && maxc) {
@@ -160,9 +172,21 @@ static void set_cpu_info(struct ele_get_info_data *info)
static u32 get_cpu_variant_type(u32 type)
{
- /* word 19 */
- u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
- u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
+ u32 bank, word, val, val2;
+ int ret;
+
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
+ bank = HW_CFG2 / NUM_WORDS_PER_BANK;
+ word = HW_CFG2 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val2);
+ if (ret)
+ val2 = 0; /* If read fuse failed, return as blank fuse */
+
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
--
2.35.3
[PATCH v3 04/21] imx9: soc: Print UID in big endian format for EL2GO
From: Ye Li
Print UID in big endian format and as one buffer of bytes, so customer
can directly use it for EdgeLock 2GO.
Before:
UID: 0xf6c8ae93 0x0f46b326 0x10d61eb3 0x0583c2d2
Become:
UID: 93aec8f626b3460fb31ed610d2c28305
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 6dcf0c4612d..bdc569b4ae4 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -560,8 +560,9 @@ int ft_system_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
void get_board_serial(struct tag_serialnr *serialnr)
{
- printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
- gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
+ printf("UID: %08x%08x%08x%08x\n", __be32_to_cpu(gd->arch.uid[0]),
+ __be32_to_cpu(gd->arch.uid[1]), __be32_to_cpu(gd->arch.uid[2]),
+ __be32_to_cpu(gd->arch.uid[3]));
serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
--
2.35.3
[PATCH v3 03/21] imx9: soc: imx9: soc: Align UID endianness with ROM
From: Frank Li
ROM use UID[0] and UID[1] as serial number with big endian when usb serial
download.
After update this, uuu(>1.6) can use below command to filter out devices
when multi boards connected.
uuu -ms ...
[sudo] uuu -lsusb can list known devices with serial# informaiton.
Signed-off-by: Frank Li
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 06032f2ff59..6dcf0c4612d 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -563,8 +563,8 @@ void get_board_serial(struct tag_serialnr *serialnr)
printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
- serialnr->low = gd->arch.uid[0];
- serialnr->high = gd->arch.uid[3];
+ serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
+ serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
}
#endif
--
2.35.3
[PATCH v3 02/21] imx9: soc: Configure TRDC for M33 TCM access
From: Ye Li
On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM.
So after release TRDC, we need to configure TRDC for M33 TCM,
otherwise A55 can't access the TCM.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 14 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 9953c33b73b..fb6de533d12 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -25,6 +25,7 @@
#define ANATOP_BASE_ADDR0x4448UL
#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x4242
+#define BLK_CTRL_NS_ANOMIX_BASE_ADDR 0x4421
#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f
#define SRC_IPS_BASE_ADDR (0x4446)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 3ee2f3d881f..06032f2ff59 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -792,7 +792,7 @@ int m33_prepare(void)
(struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
- u32 val;
+ u32 val, i;
if (m33_is_rom_kicked())
return -EPERM;
@@ -817,6 +817,18 @@ int m33_prepare(void)
/* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+ /* OSCCA enabled, reconfigure TRDC for TCM access, otherwise ECC init
will raise error */
+ val = readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28);
+ if (val & BIT(0)) {
+ trdc_mbc_set_control(0x4427, 1, 0, 0x6600);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x4427, 1, 3, 0, i, true, 0);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x4427, 1, 3, 1, i, true, 0);
+ }
+
/* Clear M33 TCM for ECC */
memset((void *)(ulong)0x201e, 0, 0x4);
--
2.35.3
[PATCH v3 01/21] imx9: soc: wait ssar when power on power domain
From: Peng Fan
SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.
Fixes: 0256577a83b ("imx: imx9: Add MIX power init")
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 76d241eab09..9953c33b73b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -38,6 +38,7 @@
#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
#define IMG_CONTAINER_BASE (0x8000UL)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f88e7a222dd..3ee2f3d881f 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -752,7 +752,7 @@ static int mix_power_init(enum mix_power_domain pd)
/* power on */
clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
val = readl(&mix_regs->func_stat);
- while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT)
+ while (val & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT)
val = readl(&mix_regs->func_stat);
return 0;
--
2.35.3
[PATCH v3 00/21] imx9: various update
Several updates to i.MX9 SOC and i.MX93 EVK, the related code has been in NXP downstream for some time and gone through several public releases. Some are directly cherry-picked(with R-b kept), some are modified from downtream. This patchset includes: power domain on fixes TRDC cleanup and update MAC address update i.MX9301/9302 included. runtime detection of voltage mode PMIC update generalize some code for i.MX8M and i.MX9 i.MX93 EVK update and misc. CI passed. Signed-off-by: Peng Fan --- Changes in v3: - Rebased to Tom's next tree to avoid conflict - Change back i.MX9 critical temperature to 'maxc - 5' following i.MX8M to give some margin in patch 16 - Link to v2: https://lore.kernel.org/r/20240919-imx9-update-v2-0-0d798d9e0...@nxp.com Changes in v2: - Improve subject to patch 3 - 'EL2GO' -> 'EdgeLock 2GO' in patch 4 commit log - Use HW_CFG1/HW_CFG2 to replace bank2,work[3,4] in patch 5 - Separate patch 6 into two patches, one is MAC update, one is print ELE information - Typo fix in patch 12 - Drop patch 21 "imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST", this needs kernel dts update first, then U-Boot could follow that logic. - Link to v1: https://lore.kernel.org/r/20240917-imx9-update-v1-0-4fe8effc9...@nxp.com --- Frank Li (1): imx9: soc: imx9: soc: Align UID endianness with ROM Jacky Bai (1): imx9: soc: Mask the wdog reset in src by default on i.mx9 Peng Fan (12): imx9: soc: wait ssar when power on power domain imx9: soc: Change FSB directly access to fuse API imx9: soc: Print ELE information imx8m: soc: Drop disable_pmu_cpu_nodes imx: Generalize disable_cpu_nodes imx9: soc: Disable cpu1 for variants that only has one A55 core imx: Generalize fixup_thermal_trips imx9: trdc: cleanup code imx9: trdc: introduce trdc_mbc_blk_num imx93_evk: spl: update pmic settings imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig imx93_evk: add back Low drive mode ddr timing file Ye Li (7): imx9: soc: Configure TRDC for M33 TCM access imx9: soc: Print UID in big endian format for EL2GO imx9: soc: Change second Ethernet MAC fuse layout imx9: soc: Add function to get target voltage mode imx9: clock: Update clock init function and sequence imx9: Add 233Mhz DDR PLL frequency imx93: Add Low performance parts 9302/9301 support arch/arm/include/asm/arch-imx/cpu.h|2 + arch/arm/include/asm/arch-imx9/clock.h |3 +- arch/arm/include/asm/arch-imx9/imx-regs.h | 10 + arch/arm/include/asm/arch-imx9/sys_proto.h | 11 + arch/arm/include/asm/mach-imx/sys_proto.h |8 +- arch/arm/mach-imx/Makefile |6 + arch/arm/mach-imx/fdt.c| 129 ++ arch/arm/mach-imx/imx8m/soc.c | 179 +- arch/arm/mach-imx/imx9/Kconfig |6 +- arch/arm/mach-imx/imx9/clock.c | 40 +- arch/arm/mach-imx/imx9/soc.c | 258 ++- arch/arm/mach-imx/imx9/trdc.c | 175 +- board/freescale/imx93_evk/Makefile |6 +- board/freescale/imx93_evk/lpddr4x_timing_1866mts.c | 1995 board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 --- board/freescale/imx93_evk/spl.c| 55 +- board/phytec/phycore_imx93/spl.c |2 +- configs/imx93_11x11_evk_ld_defconfig | 127 -- drivers/cpu/imx8_cpu.c |4 + drivers/ddr/imx/phy/ddrphy_utils.c |4 + include/power/pca9450.h|2 + 21 files changed, 2582 insertions(+), 1936 deletions(-) --- base-commit: c17805e19b9335e1fb5295c81b59eddf88d1b9ec change-id: 20240916-imx9-update-0ce38f6ccd3d Best regards, -- Peng Fan
RE: [PATCH v2 00/21] imx9: various update
Hi Fabio, > -Original Message- > From: Fabio Estevam > Sent: Thursday, September 19, 2024 10:36 AM > To: Peng Fan (OSS) > Cc: Stefano Babic ; dl-uboot-imx i...@nxp.com>; u-boot@lists.denx.de; Peng Fan ; > Ye Li ; Frank Li ; Jacky Bai > > Subject: Re: [PATCH v2 00/21] imx9: various update > > Hi Peng, > > On Wed, Sep 18, 2024 at 9:14 PM Peng Fan (OSS) > wrote: > > > Peng Fan (12): > > imx9: soc: wait ssar when power on power domain > > imx9: soc: Change FSB directly access to fuse API > > imx9: soc: Print ELE information > > imx8m: soc: Drop disable_pmu_cpu_nodes > > imx: Generalize disable_cpu_nodes > > imx9: soc: Disable cpu1 for variants that only has one A55 core > > imx: Generalize fixup_thermal_trips > > This one fails to apply to the next branch. > > Please rebase and resend. Based on Tom's next branch, right? Thanks, Peng.
[PATCH v2 21/21] imx93_evk: add back Low drive mode ddr timing file
From: Peng Fan
Add back low drive mode 1866mts ddr timing file, no need
CONFIG_IMX9_LOW_DRIVE_MODE anymore, using runtime selection.
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/Makefile |2 +-
board/freescale/imx93_evk/lpddr4x_timing_1866mts.c | 1995
board/freescale/imx93_evk/spl.c|9 +-
3 files changed, 2004 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx93_evk/Makefile
b/board/freescale/imx93_evk/Makefile
index 575f8e94604..ede8d20ff5c 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,5 +8,5 @@ obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o
endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
new file mode 100644
index 000..f4e910b2536
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.4.0_8.3-4e2b550a.
+ * DDR PHY FW2022.01
+ */
+
+#include
+#include
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x4411},
+ {0x4e30, 0x8000ff},
+ {0x4e38, 0x0},
+ {0x4e300080, 0x8512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x12552100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816B4AA},
+ {0x4e30010C, 0x0051E1E6},
+ {0x4e300124, 0x0E3A},
+ {0x4e300160, 0x9101},
+ {0x4e30016C, 0x3090},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x0014},
+ {0x4e300254, 0x00AA00AA},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ {0x4e300300, 0x11281109},
+ {0x4e300304, 0x00AA140A},
+ {0x4e300308, 0x063C071E},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x010A1000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x9492AA58},
+ {0x4e30010C, 0x00310113},
+ {0x4e300124, 0x071E},
+ {0x4e300160, 0x9100},
+ {0x4e30016C, 0x3020},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x000A},
+ {0x4e300254, 0x00510051},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C5},
+ {0x4e300160, 0x9100},
+ {0x4e30016C, 0x3000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x0007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11
[PATCH v2 20/21] imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig
From: Peng Fan
Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and
imx93_11x11_evk_ld_defconfig.
Remove the ld timing file.
The LD mode support will be added back with runtime detection later.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Kconfig|5 -
board/freescale/imx93_evk/Makefile|4 -
board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 -
configs/imx93_11x11_evk_ld_defconfig | 126 ---
4 files changed, 1631 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 63e75b6806e..4d32c28670d 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -5,11 +5,6 @@ config AHAB_BOOT
help
This option enables the support for AHAB secure boot.
-config IMX9_LOW_DRIVE_MODE
-bool "Configure to i.MX9 low drive mode"
-help
-This option enables the settings for iMX9 low drive mode.
-
config IMX9
bool
select BINMAN
diff --git a/board/freescale/imx93_evk/Makefile
b/board/freescale/imx93_evk/Makefile
index 17956d24bf7..575f8e94604 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,9 +8,5 @@ obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-ifdef CONFIG_IMX9_LOW_DRIVE_MODE
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o
-else
obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
endif
-endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
b/board/freescale/imx93_evk/lpddr4x_timing_ld.c
deleted file mode 100644
index f080322f112..000
--- a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
+++ /dev/null
@@ -1,1496 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2022 NXP
- *
- * Generated code from IMX_DDR_tool
- *
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
- */
-
-#include
-#include
-
-struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
- { 0x4e300110, 0x44140001 },
- { 0x4e301000, 0x0 },
- { 0x4e30, 0x8000ff },
- { 0x4e38, 0x0 },
- { 0x4e300080, 0x8512 },
- { 0x4e300084, 0x0 },
- { 0x4e300114, 0x2 },
- { 0x4e300260, 0x0 },
- { 0x4e30017c, 0x0 },
- { 0x4e300f04, 0x80 },
- { 0x4e300104, 0xaa77000e },
- { 0x4e300108, 0x1816b1aa },
- { 0x4e30010c, 0x5101e6 },
- { 0x4e300100, 0x12552100 },
- { 0x4e300160, 0x9002 },
- { 0x4e30016c, 0x3090 },
- { 0x4e300250, 0x14 },
- { 0x4e300254, 0xaa00aa },
- { 0x4e300258, 0x8 },
- { 0x4e30025c, 0x400 },
- { 0x4e300300, 0x11281109 },
- { 0x4e300304, 0xaa110a },
- { 0x4e300308, 0x620071e },
- { 0x4e300170, 0x8a0a0508 },
- { 0x4e300124, 0xe3c },
- { 0x4e300804, 0x1f1f1f1f },
- { 0x4e301240, 0x0 },
- { 0x4e301244, 0x0 },
- { 0x4e301248, 0x0 },
- { 0x4e30124c, 0x0 },
- { 0x4e301250, 0x0 },
- { 0x4e301254, 0x0 },
- { 0x4e301258, 0x0 },
- { 0x4e30125c, 0x0 },
-};
-
-/* PHY Initialize Configuration */
-struct dram_cfg_param ddr_ddrphy_cfg[] = {
- { 0x100a0, 0x4 },
- { 0x100a1, 0x5 },
- { 0x100a2, 0x6 },
- { 0x100a3, 0x7 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x1 },
- { 0x100a6, 0x2 },
- { 0x100a7, 0x3 },
- { 0x110a0, 0x3 },
- { 0x110a1, 0x2 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x1 },
- { 0x110a4, 0x7 },
- { 0x110a5, 0x6 },
- { 0x110a6, 0x4 },
- { 0x110a7, 0x5 },
- { 0x1005f, 0x5ff },
- { 0x1015f, 0x5ff },
- { 0x1105f, 0x5ff },
- { 0x1115f, 0x5ff },
- { 0x55, 0x1ff },
- { 0x1055, 0x1ff },
- { 0x2055, 0x1ff },
- { 0x200c5, 0xb },
- { 0x2002e, 0x2 },
- { 0x90204, 0x0 },
- { 0x20024, 0x1e3 },
- { 0x2003a, 0x2 },
- { 0x2007d, 0x212 },
- { 0x2007c, 0x61 },
- { 0x20056, 0x3 },
- { 0x1004d, 0xe00 },
- { 0x1014d, 0xe00 },
- { 0x1104d, 0xe00 },
- { 0x1114d, 0xe00 },
- { 0x10049, 0xe00 },
- { 0x10149, 0xe00 },
- { 0x11049, 0xe00 },
- { 0x11149, 0xe00 },
- { 0x43, 0x60 },
- { 0x1043, 0x60 },
- { 0x2043, 0x60 },
- { 0x20018, 0x1 },
- { 0x20075, 0x4 },
- { 0x20050, 0x0 },
- { 0x2009b, 0x2 },
- { 0x20008, 0x1d3 },
- { 0x20088, 0x9 },
- { 0x200b2, 0x10c },
- { 0x10043, 0x5a1 },
- { 0x10143, 0x5a1 },
- { 0x11043, 0x5a1 },
- { 0x11143, 0x5a1 },
- { 0x200fa, 0x2 },
- { 0x20019, 0x1 },
- { 0x200f0, 0x0 },
- { 0x200f1, 0x0 },
- { 0x200f2, 0x },
- { 0x200f3, 0x },
- { 0x200f4, 0x },
- { 0x200f5, 0x0 },
- { 0x200f6, 0x0 },
- { 0x200f7, 0xf000 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x
[PATCH v2 19/21] imx93_evk: spl: update pmic settings
From: Peng Fan
1. Use runtime voltage selection for LD/OD/ND mode.
2. According to latest PE/TE report, the voltages of VDD_SOC for
LD and ND mode need add 50mv margin, so LD voltage is 0.75v->0.8v,
ND voltage is 0.8v->0.85v.
3. Use TOFF_DEB to differentiate new trimmed pmic and old pmic
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/spl.c | 42 +++--
include/power/pca9450.h | 2 ++
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2ad7489ada7..503286ce3af 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -62,6 +62,7 @@ int power_init_board(void)
{
struct udevice *dev;
int ret;
+ unsigned int val = 0, buck_val;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
@@ -77,20 +78,41 @@ int power_init_board(void)
/* enable DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
- if (is_voltage_mode(VOLT_LOW_DRIVE))
- /* 0.75v for Low drive mode
-*/
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
+ ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ buck_val = 0x0c; /* 0.8v for Low drive mode */
+ printf("PMIC: Low Drive Voltage Mode\n");
+ } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+ buck_val = 0x10; /* 0.85v for Nominal drive mode */
+ printf("PMIC: Nominal Voltage Mode\n");
+ } else {
+ buck_val = 0x14; /* 0.9v for Over drive mode */
+ printf("PMIC: Over Drive Voltage Mode\n");
+ }
+
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
} else {
- /* 0.9v for Over drive mode
-*/
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+ }
+
+ if (IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)) {
+ /* Set VDDQ to 1.1V from buck2 */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
}
/* set standby voltage to 0.65v */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index b8219d535ad..f896d829d37 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -54,6 +54,8 @@ enum {
PCA9450_REG_NUM,
};
+#define PCA9450_REG_PWRCTRL_TOFF_DEBBIT(5)
+
int power_pca9450_init(unsigned char bus, unsigned char addr);
enum {
--
2.35.3
[PATCH v2 18/21] imx9: trdc: introduce trdc_mbc_blk_num
From: Peng Fan
Add trdc_mbc_blk_num to get num blks in a MBC mem slot, then drop
the hardcoded value '40' for NIC OCRAM configuration.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/trdc.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index ae1a46d1331..ef0f8b52a4d 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -19,6 +19,7 @@
#define MRC_MAX_NUM 2
#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+#define MBC_BLK_NUM(GLBCFG)((GLBCFG) & 0x3FF)
enum {
/* Order following ELE API Spec, not change */
@@ -154,6 +155,22 @@ static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
return trdc_reg + 0x1 + 0x2000 * mbc_num + 0x1000 * mrc_x;
}
+static u32 trdc_mbc_blk_num(ulong trdc_reg, u32 mbc_x, u32 mem_x)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc
*)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 glbcfg;
+
+ if (mbc_base == 0)
+ return 0;
+
+ /* only first dom has the glbcfg */
+ mbc_dom = &mbc_base->mem_dom[0];
+ glbcfg = readl((uintptr_t)&mbc_dom->mem_glbcfg[mem_x]);
+
+ return MBC_BLK_NUM(glbcfg);
+}
+
int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32
glbac_val)
{
struct trdc_mbc *mbc_base = (struct trdc_mbc
*)trdc_get_mbc_base(trdc_reg, mbc_x);
@@ -383,6 +400,7 @@ int release_rdc(u8 xrdc)
void trdc_early_init(void)
{
int ret = 0, i;
+ u32 blks;
ret |= release_rdc(TRDC_A);
ret |= release_rdc(TRDC_M);
@@ -397,7 +415,8 @@ void trdc_early_init(void)
/* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
trdc_mbc_set_control(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0), PERM(0x7700));
- for (i = 0; i < 40; i++) {
+ blks = trdc_mbc_blk_num(TRDC_NIC_BASE, MBC(3), MEM(0));
+ for (i = 0; i < blks; i++) {
trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i,
true, GLOBAL_ID(0));
--
2.35.3
[PATCH v2 17/21] imx9: trdc: cleanup code
From: Peng Fan
Replace magic number with meaningful macros.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 5 +
arch/arm/mach-imx/imx9/trdc.c | 156 ++
2 files changed, 101 insertions(+), 60 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index cb6b8a59cad..ef9538bd42e 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -50,6 +50,11 @@
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 1)
#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN(0x1 << 0)
+#define TRDC_AON_BASE (0x4427UL)
+#define TRDC_WAKEUP_BASE (0x4246UL)
+#define TRDC_MEGA_BASE (0x4281UL)
+#define TRDC_NIC_BASE (0x4901UL)
+
#define MARKETING_GRADING_MASK GENMASK(5, 4)
#define SPEED_GRADING_MASK GENMASK(11, 6)
#define NUM_WORDS_PER_BANK 8
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index 8cdb28459a3..ae1a46d1331 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -4,12 +4,13 @@
*/
#include
+#include
+#include
#include
#include
#include
#include
#include
-#include
#include
#include
@@ -19,6 +20,25 @@
#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+enum {
+ /* Order following ELE API Spec, not change */
+ TRDC_A,
+ TRDC_W,
+ TRDC_M,
+ TRDC_N,
+};
+
+/* Just make it easier to know what the parameter is */
+#define MBC(X) (X)
+#define MRC(X) (X)
+#define GLOBAL_ID(X) (X)
+#define MEM(X) (X)
+#define DOM(X) (X)
+/*
+ *0|SPR|SPW|SPX,0|SUR|SUW|SWX, 0|NPR|NPW|NPX, 0|NUR|NUW|NUX
+ */
+#define PERM(X)(X)
+
struct mbc_mem_dom {
u32 mem_glbcfg[4];
u32 nse_blk_index;
@@ -364,68 +384,84 @@ void trdc_early_init(void)
{
int ret = 0, i;
- ret |= release_rdc(0);
- ret |= release_rdc(2);
- ret |= release_rdc(1);
- ret |= release_rdc(3);
+ ret |= release_rdc(TRDC_A);
+ ret |= release_rdc(TRDC_M);
+ ret |= release_rdc(TRDC_W);
+ ret |= release_rdc(TRDC_N);
- if (!ret) {
- /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX
only */
- trdc_mbc_set_control(0x4901, 3, 0, 0x7700);
+ if (ret) {
+ hang();
+ return;
+ }
+
+ /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+ trdc_mbc_set_control(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0), PERM(0x7700));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 3, 0, i, true, 0);
+ for (i = 0; i < 40; i++) {
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 3, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(1), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 0, 0, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 0, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(1), i,
+ true, GLOBAL_ID(0));
}
}
void trdc_init(void)
{
/* TRDC mega */
- if (trdc_mrc_enabled(0x4901)) {
+ if (trdc_mrc_enabled(TRDC_NIC_BASE)) {
/* DDR */
- trdc_mrc_set_control(0x4901, 0, 0, 0x);
+ trdc_mrc_set_control(TRDC_NIC_BASE, MRC(0), GLOBAL_ID(0),
PERM(0x));
/* ELE */
- trdc_mrc_region_config(0x4901, 0, 0, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(0),
0x8000,
+ 0x, false, GLOBAL_ID(0));
/* MTR */
- trdc_mrc_region_config(0x4901, 0, 1, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(1),
0x8000,
+ 0x, false, GLOBAL_ID(0));
/* M33 */
- trdc_mrc_region_config(0x4901, 0, 2, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(2),
0x8000,
+ 0x,
[PATCH v2 16/21] imx: Generalize fixup_thermal_trips
From: Peng Fan
i.MX8M and i.MX9 have duplicated fixup_thermal_trips, so move it
to arch/arm/mach-imx/fdt.c to avoid duplicated code.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
arch/arm/mach-imx/fdt.c | 42 +++
arch/arm/mach-imx/imx8m/soc.c | 42 ---
arch/arm/mach-imx/imx9/soc.c | 42 ---
4 files changed, 43 insertions(+), 84 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index c146a223b71..31ace977d2b 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -280,4 +280,5 @@ enum boot_device get_boot_device(void);
int disable_cpu_nodes(void *blob, const char * const *nodes_path,
u32 num_disabled_cores, u32 max_cores);
+int fixup_thermal_trips(void *blob, const char *name);
#endif
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
index df6fbf51dba..ac782e3ee63 100644
--- a/arch/arm/mach-imx/fdt.c
+++ b/arch/arm/mach-imx/fdt.c
@@ -85,3 +85,45 @@ int disable_cpu_nodes(void *blob, const char * const
*nodes_path, u32 num_disabl
return 0;
}
+
+int fixup_thermal_trips(void *blob, const char *name)
+{
+ int minc, maxc;
+ int node, trip;
+
+ node = fdt_path_offset(blob, "/thermal-zones");
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, name);
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, "trips");
+ if (node < 0)
+ return node;
+
+ get_cpu_temp_grade(&minc, &maxc);
+
+ fdt_for_each_subnode(trip, blob, node) {
+ const char *type;
+ int temp, ret;
+
+ type = fdt_getprop(blob, trip, "type", NULL);
+ if (!type)
+ continue;
+
+ temp = 0;
+ if (!strcmp(type, "critical"))
+ temp = 1000 * (maxc - 5);
+ else if (!strcmp(type, "passive"))
+ temp = 1000 * (maxc - 10);
+ if (temp) {
+ ret = fdt_setprop_u32(blob, trip, "temperature", temp);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 68d5762c2ce..dd2d1796e3d 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1166,48 +1166,6 @@ static int cleanup_nodes_for_efi(void *blob)
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
-{
- int minc, maxc;
- int node, trip;
-
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
-
- get_cpu_temp_grade(&minc, &maxc);
-
- fdt_for_each_subnode(trip, blob, node) {
- const char *type;
- int temp, ret;
-
- type = fdt_getprop(blob, trip, "type", NULL);
- if (!type)
- continue;
-
- temp = 0;
- if (!strcmp(type, "critical"))
- temp = 1000 * maxc;
- else if (!strcmp(type, "passive"))
- temp = 1000 * (maxc - 10);
- if (temp) {
- ret = fdt_setprop_u32(blob, trip, "temperature", temp);
- if (ret)
- return ret;
- }
- }
-
- return 0;
-}
-
#define OPTEE_SHM_SIZE 0x0040
static int ft_add_optee_node(void *fdt, struct bd_info *bd)
{
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 23e81caa8ec..04b21207a28 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -538,48 +538,6 @@ int print_cpuinfo(void)
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
-{
- int minc, maxc;
- int node, trip;
-
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
-
- get_cpu_temp_grade(&minc, &maxc);
-
- fdt_for_each_subnode(trip, blob, node)
[PATCH v2 15/21] imx93: Add Low performance parts 9302/9301 support
From: Ye Li
Add support for iMX93 low performance parts 9302 and 9301 which
restrict to low drive voltage only.
The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU
and A55 core1 (9301) disabled.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 2 ++
arch/arm/include/asm/mach-imx/sys_proto.h | 5 -
arch/arm/mach-imx/imx9/Kconfig| 1 +
arch/arm/mach-imx/imx9/soc.c | 6 +-
drivers/cpu/imx8_cpu.c| 4
5 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index cbd2717f97c..b0468a1a136 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -68,6 +68,8 @@
#define MXC_CPU_IMX93210xC6 /* dummy ID */
#define MXC_CPU_IMX93120xC7 /* dummy ID */
#define MXC_CPU_IMX93110xC8 /* dummy ID */
+#define MXC_CPU_IMX93020xC9 /* dummy ID */
+#define MXC_CPU_IMX93010xCA /* dummy ID */
#define MXC_SOC_MX60x60
#define MXC_SOC_MX70x70
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index d93e095e191..c146a223b71 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -85,7 +85,8 @@ struct bd_info;
#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331)
|| \
is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
- is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
+ is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311) || \
+ is_cpu_type(MXC_CPU_IMX9302) || is_cpu_type(MXC_CPU_IMX9301))
#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
@@ -93,6 +94,8 @@ struct bd_info;
#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
+#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
+#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index e892da80fe8..63e75b6806e 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -30,6 +30,7 @@ choice
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
+ select OF_BOARD_FIXUP
select IMX93
imply OF_UPSTREAM
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 4ee40c2da32..23e81caa8ec 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -191,6 +191,10 @@ static u32 get_cpu_variant_type(u32 type)
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+ /* Low performance 93 part */
+ if (((val >> 6) & 0x3F) == 0xE && npu_disable)
+ return core1_disable ? MXC_CPU_IMX9301 : MXC_CPU_IMX9302;
+
if ((val2 & pack_9x9_fused) == pack_9x9_fused)
type = MXC_CPU_IMX9322;
@@ -704,7 +708,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
- if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311())
+ if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311() ||
is_imx9301())
disable_cpu_nodes(blob, nodes_path, 1, 2);
if (is_voltage_mode(VOLT_LOW_DRIVE))
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 60deca963a6..6c0a8c0cbe4 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -60,6 +60,10 @@ static const char *get_imx_type_str(u32 imxtype)
return "93(12)";/* iMX93 9x9 Dual core without NPU */
case MXC_CPU_IMX9311:
return "93(11)";/* iMX93 9x9 Single core without NPU */
+ case MXC_CPU_IMX9302:
+ return "93(02)";/* iMX93 900Mhz Low performance Dual core
without NPU */
+ case MXC_CPU_IMX9301:
+ return "93(01)";/* iMX93 900Mhz Low performance Single core
without NPU */
default:
return "??";
}
--
2.35.3
[PATCH v2 14/21] imx9: soc: Disable cpu1 for variants that only has one A55 core
From: Peng Fan
Disale CPU1 for i.MX93 variants that only has one A55 core and update
cooling maps.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/Makefile | 7 ++-
arch/arm/mach-imx/imx9/soc.c | 8
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 47e2cb8d943..f8903afc92e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,6 @@ endif
ifeq ($(SOC),$(filter $(SOC),imx8m))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
-obj-y += fdt.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
@@ -22,6 +21,12 @@ obj-$(CONFIG_IMX_HAB) += hab.o
obj-y += cpu.o
endif
+ifeq ($(SOC),$(filter $(SOC),imx8m imx9))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += fdt.o
+endif
+endif
+
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += cpu.o speed.o
ifneq ($(CONFIG_MX51),y)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index df259c26ad8..4ee40c2da32 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -696,9 +696,17 @@ int board_fix_fdt(void *fdt)
int ft_system_setup(void *blob, struct bd_info *bd)
{
+ static const char * const nodes_path[] = {
+ "/cpus/cpu@0",
+ "/cpus/cpu@100",
+ };
+
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
+ if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311())
+ disable_cpu_nodes(blob, nodes_path, 1, 2);
+
if (is_voltage_mode(VOLT_LOW_DRIVE))
low_drive_freq_update(blob);
--
2.35.3
[PATCH v2 13/21] imx: Generalize disable_cpu_nodes
From: Peng Fan
disable_cpu_nodes could be reused by i.MX9, so move disable_cpu_nodes
out from mach-imx/imx8m/soc.c to mach-imx/fdt.c and update
disable_cpu_nodes to make it easy to support different socs.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 +
arch/arm/mach-imx/Makefile| 1 +
arch/arm/mach-imx/fdt.c | 87 +++
arch/arm/mach-imx/imx8m/soc.c | 99 ---
4 files changed, 103 insertions(+), 86 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 31ae179b211..d93e095e191 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -275,4 +275,6 @@ void enable_ca7_smp(void);
enum boot_device get_boot_device(void);
+int disable_cpu_nodes(void *blob, const char * const *nodes_path,
+ u32 num_disabled_cores, u32 max_cores);
#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5262dca4ffd..47e2cb8d943 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,6 +12,7 @@ endif
ifeq ($(SOC),$(filter $(SOC),imx8m))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-y += fdt.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
new file mode 100644
index 000..df6fbf51dba
--- /dev/null
+++ b/arch/arm/mach-imx/fdt.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+static void disable_thermal_cpu_nodes(void *blob, u32 num_disabled_cores, u32
max_cores)
+{
+ static const char * const thermal_path[] = {
+ "/thermal-zones/cpu-thermal/cooling-maps/map0"
+ };
+
+ int nodeoff, cnt, i, ret, j;
+ u32 num_le32 = max_cores * 3;
+ u32 *cooling_dev = (u32 *)malloc(num_le32 * sizeof(__le32));
+
+ if (!cooling_dev) {
+ printf("failed to alloc cooling dev\n");
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+ nodeoff = fdt_path_offset(blob, thermal_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ cnt = fdtdec_get_int_array_count(blob, nodeoff,
"cooling-device",
+cooling_dev, num_le32);
+ if (cnt < 0)
+ continue;
+
+ if (cnt != num_le32)
+ printf("Warning: %s, cooling-device count %d\n",
thermal_path[i], cnt);
+
+ for (j = 0; j < cnt; j++)
+ cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+ ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+ sizeof(__le32) * (num_le32 -
num_disabled_cores * 3));
+ if (ret < 0) {
+ printf("Warning: %s, cooling-device setprop failed
%d\n",
+ thermal_path[i], ret);
+ continue;
+ }
+
+ printf("Update node %s, cooling-device prop\n",
thermal_path[i]);
+ }
+
+ free(cooling_dev);
+}
+
+int disable_cpu_nodes(void *blob, const char * const *nodes_path, u32
num_disabled_cores,
+ u32 max_cores)
+{
+ u32 i = 0;
+ int rc;
+ int nodeoff;
+
+ if (max_cores == 0 || (num_disabled_cores > (max_cores - 1)))
+ return -EINVAL;
+
+ i = max_cores - num_disabled_cores;
+
+ for (; i < max_cores; i++) {
+ nodeoff = fdt_path_offset(blob, nodes_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ debug("Found %s node\n", nodes_path[i]);
+
+ rc = fdt_del_node(blob, nodeoff);
+ if (rc < 0) {
+ printf("Unable to delete node %s, err=%s\n",
+ nodes_path[i], fdt_strerror(rc));
+ } else {
+ printf("Delete node %s\n", nodes_path[i]);
+ }
+ }
+
+ disable_thermal_cpu_nodes(blob, num_disabled_cores, max_cores);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 9ed27b59303..68d5762c2ce 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1135,79 +1135,6 @@ int disable_dsp_nodes(void *blob)
return disable_fdt_nodes(blob, nodes_path_8mp,
ARRAY_SIZE(nodes_path_8mp));
}
-static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char
[PATCH v2 12/21] imx8m: soc: Drop disable_pmu_cpu_nodes
From: Peng Fan
i.MX8M use PPI for PMU interrupts, there is no reason to update
interrupt-affinity for PMU even interrupt-affinity was wrongly added
to device tree before.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 38 --
1 file changed, 38 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index be38ca52885..9ed27b59303 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1171,43 +1171,6 @@ static void disable_thermal_cpu_nodes(void *blob, u32
disabled_cores)
}
}
-static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char * const pmu_path[] = {
- "/pmu"
- };
-
- int nodeoff, cnt, i, ret, j;
- u32 irq_affinity[4];
-
- for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
- nodeoff = fdt_path_offset(blob, pmu_path[i]);
- if (nodeoff < 0)
- continue; /* Not found, skip it */
-
- cnt = fdtdec_get_int_array_count(blob, nodeoff,
"interrupt-affinity",
-irq_affinity, 4);
- if (cnt < 0)
- continue;
-
- if (cnt != 4)
- printf("Warning: %s, interrupt-affinity count %d\n",
pmu_path[i], cnt);
-
- for (j = 0; j < cnt; j++)
- irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
-
- ret = fdt_setprop(blob, nodeoff, "interrupt-affinity",
&irq_affinity,
-sizeof(u32) * (4 - disabled_cores));
- if (ret < 0) {
- printf("Warning: %s, interrupt-affinity setprop failed
%d\n",
- pmu_path[i], ret);
- continue;
- }
-
- printf("Update node %s, interrupt-affinity prop\n",
pmu_path[i]);
- }
-}
-
static int disable_cpu_nodes(void *blob, u32 disabled_cores)
{
static const char * const nodes_path[] = {
@@ -1241,7 +1204,6 @@ static int disable_cpu_nodes(void *blob, u32
disabled_cores)
}
disable_thermal_cpu_nodes(blob, disabled_cores);
- disable_pmu_cpu_nodes(blob, disabled_cores);
return 0;
}
--
2.35.3
[PATCH v2 11/21] imx9: Add 233Mhz DDR PLL frequency
From: Ye Li
To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/clock.c | 1 +
drivers/ddr/imx/phy/ddrphy_utils.c | 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 76d19f1cba3..12685f970de 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -41,6 +41,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(46600U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(4U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(3U, 1, 150, 12, 0, 1),
+ FRAC_PLL_RATE(23300U, 1, 174, 18, 3, 4), /* 233Mhz */
};
/* return in khz */
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c
b/drivers/ddr/imx/phy/ddrphy_utils.c
index cf5bdad7abe..14278f5ad8f 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(266));
dram_disable_bypass();
break;
+ case 933:
+ dram_pll_init(MHZ(233));
+ dram_disable_bypass();
+ break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();
--
2.35.3
[PATCH v2 09/21] imx9: clock: Update clock init function and sequence
From: Ye Li
Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 3 ++-
arch/arm/mach-imx/imx9/clock.c | 22 ++
arch/arm/mach-imx/imx9/soc.c | 2 +-
board/freescale/imx93_evk/spl.c| 4 +++-
board/phytec/phycore_imx93/spl.c | 2 +-
5 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index 1ce6ac4c3a8..76f12118592 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -211,7 +211,8 @@ struct imx_clk_setting {
u32 div;
};
-int clock_init(void);
+int clock_init_early(void);
+int clock_init_late(void);
u32 get_clk_src_rate(enum ccm_clk_src source);
u32 get_lpuart_clk(void);
void init_uart_clk(u32 index);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 1433e68874d..76d19f1cba3 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -782,17 +782,10 @@ void bus_clock_init(void)
}
}
-int clock_init(void)
+int clock_init_early(void)
{
int i;
- if (is_voltage_mode(VOLT_LOW_DRIVE)) {
- bus_clock_init_low_drive();
- set_arm_clk(MHZ(900));
- } else {
- bus_clock_init();
- }
-
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
ccm_clk_src_tz_access(i, true, false, false);
@@ -809,6 +802,19 @@ int clock_init(void)
return 0;
}
+/* Set bus and A55 core clock per voltage mode */
+int clock_init_late(void)
+{
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ bus_clock_init_low_drive();
+ set_arm_core_max_clk();
+ } else {
+ bus_clock_init();
+ }
+
+ return 0;
+}
+
int set_clk_eqos(enum enet_freq type)
{
u32 eqos_post_div;
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 331c73675ff..112773f98f6 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -741,7 +741,7 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
- clock_init();
+ clock_init_early();
trdc_early_init();
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index e4999baa95f..2ad7489ada7 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -123,9 +123,11 @@ void board_init_f(ulong dummy)
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
+ clock_init_late();
+
power_init_board();
- if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (!is_voltage_mode(VOLT_LOW_DRIVE))
set_arm_clk(get_cpu_speed_grade_hz());
/* Init power of mix */
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 5efa38a1442..17a8736c73f 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -130,7 +130,7 @@ void board_init_f(ulong dummy)
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
- clock_init();
+ clock_init_late();
power_init_board();
--
2.35.3
[PATCH v2 10/21] imx9: soc: Mask the wdog reset in src by default on i.mx9
From: Jacky Bai
Normally, the wdog will be used for trigger external PMIC reset
through the WDOG_ANY pin. If the PMIC chip has debounce logic for
the reset signal, in some corner case the wdog can NOT trigger
external PMIC reset if the SoC has been reset internal before the
PMIC captures the WDOG_ANY pin reset, so need to keep the WDOG3-5
reset masked in the SRC to let the PMIC to do the reset safely.
Reviewed-by: Ye Li
Signed-off-by: Jacky Bai
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 112773f98f6..df259c26ad8 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -240,15 +240,9 @@ static void disable_wdog(void __iomem *wdog_base)
void init_wdog(void)
{
- u32 src_val;
-
disable_wdog((void __iomem *)WDG3_BASE_ADDR);
disable_wdog((void __iomem *)WDG4_BASE_ADDR);
disable_wdog((void __iomem *)WDG5_BASE_ADDR);
-
- src_val = readl(0x54460018); /* reset mask */
- src_val &= ~0x1c;
- writel(src_val, 0x54460018);
}
static struct mm_region imx93_mem_map[] = {
--
2.35.3
[PATCH v2 08/21] imx9: soc: Add function to get target voltage mode
From: Ye Li
Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target
voltage mode by checking the part's SPEED GRADE fuse.
SPL will configure to highest A55 speed which is indicated by the SPEED
fuse and select corresponding voltage mode.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/sys_proto.h | 11 +++
arch/arm/mach-imx/imx9/clock.c | 31 +++--
arch/arm/mach-imx/imx9/soc.c | 107 +
board/freescale/imx93_evk/spl.c| 2 +-
4 files changed, 143 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 2f7a1292758..e4bf6a63424 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -8,7 +8,18 @@
#include
+enum imx9_soc_voltage_mode {
+ VOLT_LOW_DRIVE = 0,
+ VOLT_NOMINAL_DRIVE,
+ VOLT_OVER_DRIVE,
+};
+
void soc_power_init(void);
bool m33_is_rom_kicked(void);
int m33_prepare(void);
+
+enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
+
+#define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
+
#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 0abf4579a1e..1433e68874d 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -603,7 +603,7 @@ void init_clk_usdhc(u32 index)
{
u32 div;
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
div = 3; /* 266.67 Mhz */
else
div = 2; /* 400 Mhz */
@@ -700,8 +700,7 @@ void set_arm_core_max_clk(void)
#endif
-#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)
-struct imx_clk_setting imx_clk_settings[] = {
+struct imx_clk_setting imx_clk_ld_settings[] = {
/* Set A55 clk to 500M */
{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
/* Set A55 periphal to 200M */
@@ -728,7 +727,7 @@ struct imx_clk_setting imx_clk_settings[] = {
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#else
+
struct imx_clk_setting imx_clk_settings[] = {
/*
* Set A55 clk to 500M. This clock root is normally used as intermediate
@@ -762,9 +761,18 @@ struct imx_clk_setting imx_clk_settings[] = {
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#endif
-int clock_init(void)
+void bus_clock_init_low_drive(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
+ ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
+imx_clk_ld_settings[i].src,
imx_clk_ld_settings[i].div);
+ }
+}
+
+void bus_clock_init(void)
{
int i;
@@ -772,9 +780,18 @@ int clock_init(void)
ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
imx_clk_settings[i].src,
imx_clk_settings[i].div);
}
+}
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+int clock_init(void)
+{
+ int i;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ bus_clock_init_low_drive();
set_arm_clk(MHZ(900));
+ } else {
+ bus_clock_init();
+ }
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 0b791568170..331c73675ff 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -615,11 +615,99 @@ int arch_misc_init(void)
return 0;
}
+struct low_drive_freq_entry {
+ const char *node_path;
+ u32 clk;
+ u32 new_rate;
+};
+
+static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32
new_rate)
+{
+#define MAX_ASSIGNED_CLKS 8
+ int cnt, j;
+ u32 assignedclks[MAX_ASSIGNED_CLKS]; /* max 8 clocks*/
+
+ cnt = fdtdec_get_int_array_count(fdt, node_off, "assigned-clock-rates",
+assignedclks, MAX_ASSIGNED_CLKS);
+ if (cnt > 0) {
+ if (cnt <= clk_index)
+ return -ENOENT;
+
+ if (assignedclks[clk_index] <= new_rate)
+ return 0;
+
+ assignedclks[clk_index] = new_rate;
+ for (j = 0; j < cnt; j++)
+ assignedclks[j] = cpu_to_fdt32(assignedclks[j]);
+
+ return fdt_setprop(fdt, node_off, "assigned-clock-rates",
&assignedclks,
+ cnt * sizeof(u32));
+ }
+
+ return -ENOENT;
+}
+
+static int low_drive_freq_update(void *blob)
+{
+ int nodeoff, ret;
+ int i;
+
+ /* Update kernel dtb clocks for low drive mode */
+ struct low_drive_freq_entry table[] = {
+ {"/soc@0/bus@4280/mmc@4285", 0, 2
[PATCH v2 07/21] imx9: soc: Print ELE information
From: Peng Fan
The boot image includes Edgelock Enclave(ELE) Firmware. Print the
information out to let user know which version firmware is being used.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7bc896b74da..0b791568170 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -582,6 +582,39 @@ static int fixup_thermal_trips(void *blob, const char
*name)
return 0;
}
+void build_info(void)
+{
+ u32 fw_version, sha1, res, status;
+ int ret;
+
+ printf("\nBuildInfo:\n");
+
+ ret = ele_get_fw_status(&status, &res);
+ if (ret) {
+ printf(" - ELE firmware status failed %d, 0x%x\n", ret, res);
+ } else if ((status & 0xff) == 1) {
+ ret = ele_get_fw_version(&fw_version, &sha1, &res);
+ if (ret) {
+ printf(" - ELE firmware version failed %d, 0x%x\n",
ret, res);
+ } else {
+ printf(" - ELE firmware version %u.%u.%u-%x",
+ (fw_version & (0x00ff)) >> 16,
+ (fw_version & (0xfff0)) >> 4,
+ (fw_version & (0x000f)), sha1);
+ ((fw_version & (0x8000)) >> 31) == 1 ?
puts("-dirty\n") : puts("\n");
+ }
+ } else {
+ printf(" - ELE firmware not included\n");
+ }
+ puts("\n");
+}
+
+int arch_misc_init(void)
+{
+ build_info();
+ return 0;
+}
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
if (fixup_thermal_trips(blob, "cpu-thermal"))
--
2.35.3
[PATCH v2 06/21] imx9: soc: Change second Ethernet MAC fuse layout
From: Ye Li
The second Ethernet MAC (eQOS) fuse layout is changed since i.MX93 A1
following other i.MX platforms, for example i.MX8MP.
Order for A0:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
Order since A1:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
MAC2_ADDR[47:32]
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f3d6c7f84cb..7bc896b74da 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -504,12 +504,21 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
if (ret)
goto err;
- mac[0] = val[1] >> 24;
- mac[1] = val[1] >> 16;
- mac[2] = val[0] >> 24;
- mac[3] = val[0] >> 16;
- mac[4] = val[0] >> 8;
- mac[5] = val[0];
+ if (is_imx93() && is_soc_rev(CHIP_REV_1_0)) {
+ mac[0] = val[1] >> 24;
+ mac[1] = val[1] >> 16;
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+ } else {
+ mac[0] = val[0] >> 24;
+ mac[1] = val[0] >> 16;
+ mac[2] = val[0] >> 8;
+ mac[3] = val[0];
+ mac[4] = val[1] >> 24;
+ mac[5] = val[1] >> 16;
+ }
}
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
--
2.35.3
[PATCH v2 05/21] imx9: soc: Change FSB directly access to fuse API
From: Peng Fan
To support OSCCA enabled part which has disabled FSB access from SOC,
change directly read from FSB to use fuse_read API.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 3 +++
arch/arm/mach-imx/imx9/soc.c | 38 +--
2 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index fb6de533d12..cb6b8a59cad 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -52,6 +52,9 @@
#define MARKETING_GRADING_MASK GENMASK(5, 4)
#define SPEED_GRADING_MASK GENMASK(11, 6)
+#define NUM_WORDS_PER_BANK 8
+#define HW_CFG119
+#define HW_CFG220
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7df3c686350..f3d6c7f84cb 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -96,10 +96,16 @@ int mmc_get_env_dev(void)
*/
u32 get_cpu_speed_grade_hz(void)
{
- u32 speed, max_speed;
+ int ret;
+ u32 bank, word, speed, max_speed;
u32 val;
- fuse_read(2, 3, &val);
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF;
speed = MHZ(2300) - val * MHZ(100);
@@ -122,9 +128,15 @@ u32 get_cpu_speed_grade_hz(void)
*/
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
- u32 val;
+ int ret;
+ u32 bank, word, val;
+
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
- fuse_read(2, 3, &val);
val = FIELD_GET(MARKETING_GRADING_MASK, val);
if (minc && maxc) {
@@ -160,9 +172,21 @@ static void set_cpu_info(struct ele_get_info_data *info)
static u32 get_cpu_variant_type(u32 type)
{
- /* word 19 */
- u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
- u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
+ u32 bank, word, val, val2;
+ int ret;
+
+ bank = HW_CFG1 / NUM_WORDS_PER_BANK;
+ word = HW_CFG1 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
+ bank = HW_CFG2 / NUM_WORDS_PER_BANK;
+ word = HW_CFG2 % NUM_WORDS_PER_BANK;
+ ret = fuse_read(bank, word, &val2);
+ if (ret)
+ val2 = 0; /* If read fuse failed, return as blank fuse */
+
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
--
2.35.3
[PATCH v2 04/21] imx9: soc: Print UID in big endian format for EL2GO
From: Ye Li
Print UID in big endian format and as one buffer of bytes, so customer
can directly use it for EdgeLock 2GO.
Before:
UID: 0xf6c8ae93 0x0f46b326 0x10d61eb3 0x0583c2d2
Become:
UID: 93aec8f626b3460fb31ed610d2c28305
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f458fc0564e..7df3c686350 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -560,8 +560,9 @@ int ft_system_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
void get_board_serial(struct tag_serialnr *serialnr)
{
- printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
- gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
+ printf("UID: %08x%08x%08x%08x\n", __be32_to_cpu(gd->arch.uid[0]),
+ __be32_to_cpu(gd->arch.uid[1]), __be32_to_cpu(gd->arch.uid[2]),
+ __be32_to_cpu(gd->arch.uid[3]));
serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
--
2.35.3
[PATCH v2 03/21] imx9: soc: imx9: soc: Align UID endianness with ROM
From: Frank Li
ROM use UID[0] and UID[1] as serial number with big endian when usb serial
download.
After update this, uuu(>1.6) can use below command to filter out devices
when multi boards connected.
uuu -ms ...
[sudo] uuu -lsusb can list known devices with serial# informaiton.
Signed-off-by: Frank Li
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 25b9116f2a6..f458fc0564e 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -563,8 +563,8 @@ void get_board_serial(struct tag_serialnr *serialnr)
printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
- serialnr->low = gd->arch.uid[0];
- serialnr->high = gd->arch.uid[3];
+ serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
+ serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
}
#endif
--
2.35.3
[PATCH v2 02/21] imx9: soc: Configure TRDC for M33 TCM access
From: Ye Li
On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM.
So after release TRDC, we need to configure TRDC for M33 TCM,
otherwise A55 can't access the TCM.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 14 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 9953c33b73b..fb6de533d12 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -25,6 +25,7 @@
#define ANATOP_BASE_ADDR0x4448UL
#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x4242
+#define BLK_CTRL_NS_ANOMIX_BASE_ADDR 0x4421
#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f
#define SRC_IPS_BASE_ADDR (0x4446)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9b6ba5609d2..25b9116f2a6 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -792,7 +792,7 @@ int m33_prepare(void)
(struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
- u32 val;
+ u32 val, i;
if (m33_is_rom_kicked())
return -EPERM;
@@ -817,6 +817,18 @@ int m33_prepare(void)
/* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+ /* OSCCA enabled, reconfigure TRDC for TCM access, otherwise ECC init
will raise error */
+ val = readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28);
+ if (val & BIT(0)) {
+ trdc_mbc_set_control(0x4427, 1, 0, 0x6600);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x4427, 1, 3, 0, i, true, 0);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x4427, 1, 3, 1, i, true, 0);
+ }
+
/* Clear M33 TCM for ECC */
memset((void *)(ulong)0x201e, 0, 0x4);
--
2.35.3
[PATCH v2 01/21] imx9: soc: wait ssar when power on power domain
From: Peng Fan
SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.
Fixes: 0256577a83b ("imx: imx9: Add MIX power init")
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 76d241eab09..9953c33b73b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -38,6 +38,7 @@
#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
#define IMG_CONTAINER_BASE (0x8000UL)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 32208220b20..9b6ba5609d2 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -752,7 +752,7 @@ static int mix_power_init(enum mix_power_domain pd)
/* power on */
clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
val = readl(&mix_regs->func_stat);
- while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT)
+ while (val & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT)
val = readl(&mix_regs->func_stat);
return 0;
--
2.35.3
[PATCH v2 00/21] imx9: various update
Several updates to i.MX9 SOC and i.MX93 EVK, the related code has been in NXP downstream for some time and gone through several public releases. Some are directly cherry-picked(with R-b kept), some are modified from downtream. This patchset includes: power domain on fixes TRDC cleanup and update MAC address update i.MX9301/9302 included. runtime detection of voltage mode PMIC update generalize some code for i.MX8M and i.MX9 i.MX93 EVK update and misc. CI passed. Signed-off-by: Peng Fan --- Changes in v2: - Improve subject to patch 3 - 'EL2GO' -> 'EdgeLock 2GO' in patch 4 commit log - Use HW_CFG1/HW_CFG2 to replace bank2,work[3,4] in patch 5 - Separate patch 6 into two patches, one is MAC update, one is print ELE information - Typo fix in patch 12 - Drop patch 21 "imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST", this needs kernel dts update first, then U-Boot could follow that logic. - Link to v1: https://lore.kernel.org/r/20240917-imx9-update-v1-0-4fe8effc9...@nxp.com --- Frank Li (1): imx9: soc: imx9: soc: Align UID endianness with ROM Jacky Bai (1): imx9: soc: Mask the wdog reset in src by default on i.mx9 Peng Fan (12): imx9: soc: wait ssar when power on power domain imx9: soc: Change FSB directly access to fuse API imx9: soc: Print ELE information imx8m: soc: Drop disable_pmu_cpu_nodes imx: Generalize disable_cpu_nodes imx9: soc: Disable cpu1 for variants that only has one A55 core imx: Generalize fixup_thermal_trips imx9: trdc: cleanup code imx9: trdc: introduce trdc_mbc_blk_num imx93_evk: spl: update pmic settings imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig imx93_evk: add back Low drive mode ddr timing file Ye Li (7): imx9: soc: Configure TRDC for M33 TCM access imx9: soc: Print UID in big endian format for EL2GO imx9: soc: Change second Ethernet MAC fuse layout imx9: soc: Add function to get target voltage mode imx9: clock: Update clock init function and sequence imx9: Add 233Mhz DDR PLL frequency imx93: Add Low performance parts 9302/9301 support arch/arm/include/asm/arch-imx/cpu.h|2 + arch/arm/include/asm/arch-imx9/clock.h |3 +- arch/arm/include/asm/arch-imx9/imx-regs.h | 10 + arch/arm/include/asm/arch-imx9/sys_proto.h | 11 + arch/arm/include/asm/mach-imx/sys_proto.h |8 +- arch/arm/mach-imx/Makefile |6 + arch/arm/mach-imx/fdt.c| 129 ++ arch/arm/mach-imx/imx8m/soc.c | 179 +- arch/arm/mach-imx/imx9/Kconfig |6 +- arch/arm/mach-imx/imx9/clock.c | 40 +- arch/arm/mach-imx/imx9/soc.c | 258 ++- arch/arm/mach-imx/imx9/trdc.c | 175 +- board/freescale/imx93_evk/Makefile |6 +- board/freescale/imx93_evk/lpddr4x_timing_1866mts.c | 1995 board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 --- board/freescale/imx93_evk/spl.c| 55 +- board/phytec/phycore_imx93/spl.c |2 +- configs/imx93_11x11_evk_ld_defconfig | 126 -- drivers/cpu/imx8_cpu.c |4 + drivers/ddr/imx/phy/ddrphy_utils.c |4 + include/power/pca9450.h|2 + 21 files changed, 2582 insertions(+), 1935 deletions(-) --- base-commit: 1630ff26cc960439b5949b80cfc604a2c8aa47dd change-id: 20240916-imx9-update-0ce38f6ccd3d Best regards, -- Peng Fan
RE: [PATCH 21/21] imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
> Subject: Re: [PATCH 21/21] imx93_evk: Enable M.2 VPCIe_3V3 and > deassert SD3_nRST > > On Tue, Sep 17, 2024 at 9:21 PM Peng Fan > wrote: > > > The linux changes still in downstream as below: > > /* > > * For this spi-nor on M.2 card, need first enable the VPCIe_3.3v. > > * Note, VPCIe_3.3v need about 1.74ms to change from 0v to > 3.3v. > > * U-boot already enable VPCIe_3.3v, so in linux, can ignore this > > * 1.7ms, if u-boot do not eanble VPCIe_3.3v first, then need to > > * take care of the 1.74ms delay, better to build the flexspi driver > > * as module in driver to avoid spi-nor probe fail. > > */ > > pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>, /* > enable VPCIe_3v3 */ > > This 'pinctrl-assert-gpios' is a NXP hack. It only exists in the NXP kernel. Yeah, reset-gpios should be used here. Regards, Peng.
RE: [PATCH 21/21] imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
Hi Fabio,
> Subject: Re: [PATCH 21/21] imx93_evk: Enable M.2 VPCIe_3V3 and
> deassert SD3_nRST
>
> Hi Peng,
>
> On Mon, Sep 16, 2024 at 11:31 PM Peng Fan (OSS)
> wrote:
>
> > + /* Enable EXT1_PWREN for PCIE_3.3V */
> > + ret = dm_gpio_lookup_name("gpio@22_13", &desc);
> > + if (ret)
> > + return;
> > +
> > + ret = dm_gpio_request(&desc, "EXT1_PWREN");
> > + if (ret)
> > + return;
> > +
> > + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
> > + dm_gpio_set_value(&desc, 1);
> > +
> > + /* Deassert SD3_nRST */
> > + ret = dm_gpio_lookup_name("gpio@22_12", &desc);
> > + if (ret)
> > + return;
> > +
> > + ret = dm_gpio_request(&desc, "SD3_nRST");
> > + if (ret)
> > + return;
> > +
> > + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
> > + dm_gpio_set_value(&desc, 1);
>
> Why do we need all this board code? This should be properly described
> in the devicetree.
I just cherry-picked the patches from imx v2024.04,
I agree your point that the board code should be dropped.
>
> How does Linux deal with it?
The linux changes still in downstream as below:
/*
* For this spi-nor on M.2 card, need first enable the VPCIe_3.3v.
* Note, VPCIe_3.3v need about 1.74ms to change from 0v to 3.3v.
* U-boot already enable VPCIe_3.3v, so in linux, can ignore this
* 1.7ms, if u-boot do not eanble VPCIe_3.3v first, then need to
* take care of the 1.74ms delay, better to build the flexspi driver
* as module in driver to avoid spi-nor probe fail.
*/
pinctrl-assert-gpios = <&pcal6524 13 GPIO_ACTIVE_HIGH>, /* enable
VPCIe_3v3 */
<&pcal6524 20 GPIO_ACTIVE_HIGH>, /* enable
SPI-NOR VCC 1.8v */
<&pcal6524 12 GPIO_ACTIVE_HIGH>; /* put SPI-NOR
RST pin to 1.8v */
To use device tree, need use reset-gpios property I think.
Regards,
Peng.
RE: [PATCH 06/21] imx9: soc: Change second Ethernet MAC fuse layout
> Subject: Re: [PATCH 06/21] imx9: soc: Change second Ethernet MAC
> fuse layout
>
> On Mon, Sep 16, 2024 at 11:30 PM Peng Fan (OSS)
> wrote:
>
> > +void build_info(void)
> > +{
> > + u32 fw_version, sha1, res, status;
> > + int ret;
> > +
> > + printf("\nBuildInfo:\n");
> > +
> > + ret = ele_get_fw_status(&status, &res);
> > + if (ret) {
> > + printf(" - ELE firmware status failed %d, 0x%x\n", ret,
> > res);
> > + } else if ((status & 0xff) == 1) {
> > + ret = ele_get_fw_version(&fw_version, &sha1, &res);
> > + if (ret) {
> > + printf(" - ELE firmware version failed %d,
> > 0x%x\n", ret,
> res);
> > + } else {
> > + printf(" - ELE firmware version %u.%u.%u-%x",
> > + (fw_version & (0x00ff)) >> 16,
> > + (fw_version & (0xfff0)) >> 4,
> > + (fw_version & (0x000f)), sha1);
> > + ((fw_version & (0x8000)) >> 31) == 1 ? puts("-
> dirty\n") : puts("\n");
> > + }
> > + } else {
> > + printf(" - ELE firmware not included\n");
> > + }
> > + puts("\n");
>
> This build_info() is unrelated to changing the second MAC address
> layout.
>
> It should be a separate patch.
Ah. This is a mistaken when I do git rebase to resolve errors.
I will fix.
Thanks,
Peng.
RE: [PATCH 21/21] imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
> Subject: Re: [PATCH 21/21] imx93_evk: Enable M.2 VPCIe_3V3 and > deassert SD3_nRST > > Hi Peng, > > On Mon, Sep 16, 2024 at 11:31 PM Peng Fan (OSS) > wrote: > > > > From: Ye Li > > > > VPCIe_3V3 is used to supply the power to M.2 card, we must enable > it > > before using the flash. > > Flash? Which flash are you referring to? There is a mt25qu512abb8e12 flash connected with flexspi interface. Regards, Peng.
RE: [PATCH 04/21] imx9: soc: Print UID in big endian format for EL2GO
> Subject: Re: [PATCH 04/21] imx9: soc: Print UID in big endian format > for EL2GO > > On Mon, Sep 16, 2024 at 11:30 PM Peng Fan (OSS) > wrote: > > > > From: Ye Li > > > > Print UID in big endian format and as one buffer of bytes, so > customer > > can directly use it for EL2GO. > > What is EL2GO? EdgeLock 2GO https://www.nxp.com/products/security-and-authentication/secure-service-2go-platform/edgelock-2go:EDGELOCK-2GO Thanks, Peng.
[PATCH 21/21] imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST
From: Ye Li
VPCIe_3V3 is used to supply the power to M.2 card, we must enable it
before using the flash.
The SD3_nRST is connected to reset pin of flash, must deassert
(pull up) it.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/imx93_evk.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/board/freescale/imx93_evk/imx93_evk.c
b/board/freescale/imx93_evk/imx93_evk.c
index 341831a7d30..08da1563f03 100644
--- a/board/freescale/imx93_evk/imx93_evk.c
+++ b/board/freescale/imx93_evk/imx93_evk.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -48,11 +49,43 @@ int board_phy_config(struct phy_device *phydev)
return 0;
}
+static void board_gpio_init(void)
+{
+ struct gpio_desc desc;
+ int ret;
+
+ /* Enable EXT1_PWREN for PCIE_3.3V */
+ ret = dm_gpio_lookup_name("gpio@22_13", &desc);
+ if (ret)
+ return;
+
+ ret = dm_gpio_request(&desc, "EXT1_PWREN");
+ if (ret)
+ return;
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ dm_gpio_set_value(&desc, 1);
+
+ /* Deassert SD3_nRST */
+ ret = dm_gpio_lookup_name("gpio@22_12", &desc);
+ if (ret)
+ return;
+
+ ret = dm_gpio_request(&desc, "SD3_nRST");
+ if (ret)
+ return;
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ dm_gpio_set_value(&desc, 1);
+}
+
int board_init(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC))
setup_fec();
+ board_gpio_init();
+
return 0;
}
--
2.35.3
[PATCH 20/21] imx93_evk: add back Low drive mode ddr timing file
From: Peng Fan
Add back low drive mode 1866mts ddr timing file, no need
CONFIG_IMX9_LOW_DRIVE_MODE anymore, using runtime selection.
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/Makefile |2 +-
board/freescale/imx93_evk/lpddr4x_timing_1866mts.c | 1995
board/freescale/imx93_evk/spl.c|9 +-
3 files changed, 2004 insertions(+), 2 deletions(-)
diff --git a/board/freescale/imx93_evk/Makefile
b/board/freescale/imx93_evk/Makefile
index 575f8e94604..ede8d20ff5c 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,5 +8,5 @@ obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
+obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o lpddr4x_timing_1866mts.o
endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
new file mode 100644
index 000..f4e910b2536
--- /dev/null
+++ b/board/freescale/imx93_evk/lpddr4x_timing_1866mts.c
@@ -0,0 +1,1995 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2024 NXP
+ *
+ * Code generated with DDR Tool v3.4.0_8.3-4e2b550a.
+ * DDR PHY FW2022.01
+ */
+
+#include
+#include
+
+/* Initialize DDRC registers */
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ {0x4e300110, 0x4411},
+ {0x4e30, 0x8000ff},
+ {0x4e38, 0x0},
+ {0x4e300080, 0x8512},
+ {0x4e300084, 0x0},
+ {0x4e300114, 0x1002},
+ {0x4e300260, 0x80},
+ {0x4e300f04, 0x80},
+ {0x4e300800, 0x43b30002},
+ {0x4e300804, 0x1f1f1f1f},
+ {0x4e301000, 0x0},
+ {0x4e301240, 0x0},
+ {0x4e301244, 0x0},
+ {0x4e301248, 0x0},
+ {0x4e30124c, 0x0},
+ {0x4e301250, 0x0},
+ {0x4e301254, 0x0},
+ {0x4e301258, 0x0},
+ {0x4e30125c, 0x0},
+};
+
+/* dram fsp cfg */
+static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = {
+ {
+ {
+ {0x4e300100, 0x12552100},
+ {0x4e300104, 0xF877000E},
+ {0x4e300108, 0x1816B4AA},
+ {0x4e30010C, 0x0051E1E6},
+ {0x4e300124, 0x0E3A},
+ {0x4e300160, 0x9101},
+ {0x4e30016C, 0x3090},
+ {0x4e300170, 0x8A0A0508},
+ {0x4e300250, 0x0014},
+ {0x4e300254, 0x00AA00AA},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ {0x4e300300, 0x11281109},
+ {0x4e300304, 0x00AA140A},
+ {0x4e300308, 0x063C071E},
+ },
+ {
+ {0x01, 0xB4},
+ {0x02, 0x1B},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x010A1000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x9492AA58},
+ {0x4e30010C, 0x00310113},
+ {0x4e300124, 0x071E},
+ {0x4e300160, 0x9100},
+ {0x4e30016C, 0x3020},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x000A},
+ {0x4e300254, 0x00510051},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11},
+ {0x16, 0x04},
+ },
+ 0,
+ },
+ {
+ {
+ {0x4e300100, 0x00061000},
+ {0x4e300104, 0xF855000A},
+ {0x4e300108, 0x6E62FA48},
+ {0x4e30010C, 0x0031010D},
+ {0x4e300124, 0x04C5},
+ {0x4e300160, 0x9100},
+ {0x4e30016C, 0x3000},
+ {0x4e300170, 0x89090408},
+ {0x4e300250, 0x0007},
+ {0x4e300254, 0x00340034},
+ {0x4e300258, 0x0008},
+ {0x4e30025C, 0x0400},
+ },
+ {
+ {0x01, 0x94},
+ {0x02, 0x9},
+ {0x03, 0x32},
+ {0x0b, 0x46},
+ {0x0c, 0x11},
+ {0x0e, 0x11
[PATCH 19/21] imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig
From: Peng Fan
Remove unused CONFIG_IMX9_LOW_DRIVE_MODE kconfig and
imx93_11x11_evk_ld_defconfig.
Remove the ld timing file.
The LD mode support will be added back with runtime detection later.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/Kconfig|5 -
board/freescale/imx93_evk/Makefile|4 -
board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 -
configs/imx93_11x11_evk_ld_defconfig | 126 ---
4 files changed, 1631 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index 63e75b6806e..4d32c28670d 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -5,11 +5,6 @@ config AHAB_BOOT
help
This option enables the support for AHAB secure boot.
-config IMX9_LOW_DRIVE_MODE
-bool "Configure to i.MX9 low drive mode"
-help
-This option enables the settings for iMX9 low drive mode.
-
config IMX9
bool
select BINMAN
diff --git a/board/freescale/imx93_evk/Makefile
b/board/freescale/imx93_evk/Makefile
index 17956d24bf7..575f8e94604 100644
--- a/board/freescale/imx93_evk/Makefile
+++ b/board/freescale/imx93_evk/Makefile
@@ -8,9 +8,5 @@ obj-y += imx93_evk.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
-ifdef CONFIG_IMX9_LOW_DRIVE_MODE
-obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing_ld.o
-else
obj-$(CONFIG_IMX93_EVK_LPDDR4X) += lpddr4x_timing.o
endif
-endif
diff --git a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
b/board/freescale/imx93_evk/lpddr4x_timing_ld.c
deleted file mode 100644
index f080322f112..000
--- a/board/freescale/imx93_evk/lpddr4x_timing_ld.c
+++ /dev/null
@@ -1,1496 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2022 NXP
- *
- * Generated code from IMX_DDR_tool
- *
- * Align with uboot version:
- * imx_v2019.04_5.4.x and above version
- */
-
-#include
-#include
-
-struct dram_cfg_param ddr_ddrc_cfg[] = {
- /** Initialize DDRC registers **/
- { 0x4e300110, 0x44140001 },
- { 0x4e301000, 0x0 },
- { 0x4e30, 0x8000ff },
- { 0x4e38, 0x0 },
- { 0x4e300080, 0x8512 },
- { 0x4e300084, 0x0 },
- { 0x4e300114, 0x2 },
- { 0x4e300260, 0x0 },
- { 0x4e30017c, 0x0 },
- { 0x4e300f04, 0x80 },
- { 0x4e300104, 0xaa77000e },
- { 0x4e300108, 0x1816b1aa },
- { 0x4e30010c, 0x5101e6 },
- { 0x4e300100, 0x12552100 },
- { 0x4e300160, 0x9002 },
- { 0x4e30016c, 0x3090 },
- { 0x4e300250, 0x14 },
- { 0x4e300254, 0xaa00aa },
- { 0x4e300258, 0x8 },
- { 0x4e30025c, 0x400 },
- { 0x4e300300, 0x11281109 },
- { 0x4e300304, 0xaa110a },
- { 0x4e300308, 0x620071e },
- { 0x4e300170, 0x8a0a0508 },
- { 0x4e300124, 0xe3c },
- { 0x4e300804, 0x1f1f1f1f },
- { 0x4e301240, 0x0 },
- { 0x4e301244, 0x0 },
- { 0x4e301248, 0x0 },
- { 0x4e30124c, 0x0 },
- { 0x4e301250, 0x0 },
- { 0x4e301254, 0x0 },
- { 0x4e301258, 0x0 },
- { 0x4e30125c, 0x0 },
-};
-
-/* PHY Initialize Configuration */
-struct dram_cfg_param ddr_ddrphy_cfg[] = {
- { 0x100a0, 0x4 },
- { 0x100a1, 0x5 },
- { 0x100a2, 0x6 },
- { 0x100a3, 0x7 },
- { 0x100a4, 0x0 },
- { 0x100a5, 0x1 },
- { 0x100a6, 0x2 },
- { 0x100a7, 0x3 },
- { 0x110a0, 0x3 },
- { 0x110a1, 0x2 },
- { 0x110a2, 0x0 },
- { 0x110a3, 0x1 },
- { 0x110a4, 0x7 },
- { 0x110a5, 0x6 },
- { 0x110a6, 0x4 },
- { 0x110a7, 0x5 },
- { 0x1005f, 0x5ff },
- { 0x1015f, 0x5ff },
- { 0x1105f, 0x5ff },
- { 0x1115f, 0x5ff },
- { 0x55, 0x1ff },
- { 0x1055, 0x1ff },
- { 0x2055, 0x1ff },
- { 0x200c5, 0xb },
- { 0x2002e, 0x2 },
- { 0x90204, 0x0 },
- { 0x20024, 0x1e3 },
- { 0x2003a, 0x2 },
- { 0x2007d, 0x212 },
- { 0x2007c, 0x61 },
- { 0x20056, 0x3 },
- { 0x1004d, 0xe00 },
- { 0x1014d, 0xe00 },
- { 0x1104d, 0xe00 },
- { 0x1114d, 0xe00 },
- { 0x10049, 0xe00 },
- { 0x10149, 0xe00 },
- { 0x11049, 0xe00 },
- { 0x11149, 0xe00 },
- { 0x43, 0x60 },
- { 0x1043, 0x60 },
- { 0x2043, 0x60 },
- { 0x20018, 0x1 },
- { 0x20075, 0x4 },
- { 0x20050, 0x0 },
- { 0x2009b, 0x2 },
- { 0x20008, 0x1d3 },
- { 0x20088, 0x9 },
- { 0x200b2, 0x10c },
- { 0x10043, 0x5a1 },
- { 0x10143, 0x5a1 },
- { 0x11043, 0x5a1 },
- { 0x11143, 0x5a1 },
- { 0x200fa, 0x2 },
- { 0x20019, 0x1 },
- { 0x200f0, 0x0 },
- { 0x200f1, 0x0 },
- { 0x200f2, 0x },
- { 0x200f3, 0x },
- { 0x200f4, 0x },
- { 0x200f5, 0x0 },
- { 0x200f6, 0x0 },
- { 0x200f7, 0xf000 },
- { 0x1004a, 0x500 },
- { 0x1104a, 0x500 },
- { 0x20025, 0x0 },
- { 0x2002d, 0x0 },
- { 0x
[PATCH 18/21] imx93_evk: spl: update pmic settings
From: Peng Fan
1. Use runtime voltage selection for LD/OD/ND mode.
2. According to latest PE/TE report, the voltages of VDD_SOC for
LD and ND mode need add 50mv margin, so LD voltage is 0.75v->0.8v,
ND voltage is 0.8v->0.85v.
3. Use TOFF_DEB to differentiate new trimmed pmic and old pmic
Signed-off-by: Peng Fan
---
board/freescale/imx93_evk/spl.c | 42 +++--
include/power/pca9450.h | 2 ++
2 files changed, 34 insertions(+), 10 deletions(-)
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index 2ad7489ada7..503286ce3af 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -62,6 +62,7 @@ int power_init_board(void)
{
struct udevice *dev;
int ret;
+ unsigned int val = 0, buck_val;
ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV) {
@@ -77,20 +78,41 @@ int power_init_board(void)
/* enable DVS control through PMIC_STBY_REQ */
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
- if (is_voltage_mode(VOLT_LOW_DRIVE))
- /* 0.75v for Low drive mode
-*/
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x0c);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x0c);
+ ret = pmic_reg_read(dev, PCA9450_PWR_CTRL);
+ if (ret < 0)
+ return ret;
+
+ val = ret;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ buck_val = 0x0c; /* 0.8v for Low drive mode */
+ printf("PMIC: Low Drive Voltage Mode\n");
+ } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) {
+ buck_val = 0x10; /* 0.85v for Nominal drive mode */
+ printf("PMIC: Nominal Voltage Mode\n");
+ } else {
+ buck_val = 0x14; /* 0.9v for Over drive mode */
+ printf("PMIC: Over Drive Voltage Mode\n");
+ }
+
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) {
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val);
} else {
- /* 0.9v for Over drive mode
-*/
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x18);
- pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x18);
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4);
+ pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4);
+ }
+
+ if (IS_ENABLED(CONFIG_IMX93_EVK_LPDDR4X)) {
+ /* Set VDDQ to 1.1V from buck2 */
+ pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x28);
}
/* set standby voltage to 0.65v */
- pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
+ if (val & PCA9450_REG_PWRCTRL_TOFF_DEB)
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0);
+ else
+ pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4);
/* I2C_LT_EN*/
pmic_reg_write(dev, 0xa, 0x3);
diff --git a/include/power/pca9450.h b/include/power/pca9450.h
index b8219d535ad..f896d829d37 100644
--- a/include/power/pca9450.h
+++ b/include/power/pca9450.h
@@ -54,6 +54,8 @@ enum {
PCA9450_REG_NUM,
};
+#define PCA9450_REG_PWRCTRL_TOFF_DEBBIT(5)
+
int power_pca9450_init(unsigned char bus, unsigned char addr);
enum {
--
2.35.3
[PATCH 16/21] imx9: trdc: cleanup code
From: Peng Fan
Replace magic number with meaningful macros.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 5 +
arch/arm/mach-imx/imx9/trdc.c | 156 ++
2 files changed, 101 insertions(+), 60 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index fb6de533d12..44f6a95f23b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -50,6 +50,11 @@
#define BCTRL_GPR_ENET_QOS_INTF_SEL_RGMII(0x1 << 1)
#define BCTRL_GPR_ENET_QOS_CLK_GEN_EN(0x1 << 0)
+#define TRDC_AON_BASE (0x4427UL)
+#define TRDC_WAKEUP_BASE (0x4246UL)
+#define TRDC_MEGA_BASE (0x4281UL)
+#define TRDC_NIC_BASE (0x4901UL)
+
#define MARKETING_GRADING_MASK GENMASK(5, 4)
#define SPEED_GRADING_MASK GENMASK(11, 6)
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index 8cdb28459a3..ae1a46d1331 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -4,12 +4,13 @@
*/
#include
+#include
+#include
#include
#include
#include
#include
#include
-#include
#include
#include
@@ -19,6 +20,25 @@
#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+enum {
+ /* Order following ELE API Spec, not change */
+ TRDC_A,
+ TRDC_W,
+ TRDC_M,
+ TRDC_N,
+};
+
+/* Just make it easier to know what the parameter is */
+#define MBC(X) (X)
+#define MRC(X) (X)
+#define GLOBAL_ID(X) (X)
+#define MEM(X) (X)
+#define DOM(X) (X)
+/*
+ *0|SPR|SPW|SPX,0|SUR|SUW|SWX, 0|NPR|NPW|NPX, 0|NUR|NUW|NUX
+ */
+#define PERM(X)(X)
+
struct mbc_mem_dom {
u32 mem_glbcfg[4];
u32 nse_blk_index;
@@ -364,68 +384,84 @@ void trdc_early_init(void)
{
int ret = 0, i;
- ret |= release_rdc(0);
- ret |= release_rdc(2);
- ret |= release_rdc(1);
- ret |= release_rdc(3);
+ ret |= release_rdc(TRDC_A);
+ ret |= release_rdc(TRDC_M);
+ ret |= release_rdc(TRDC_W);
+ ret |= release_rdc(TRDC_N);
- if (!ret) {
- /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX
only */
- trdc_mbc_set_control(0x4901, 3, 0, 0x7700);
+ if (ret) {
+ hang();
+ return;
+ }
+
+ /* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
+ trdc_mbc_set_control(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0), PERM(0x7700));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 3, 0, i, true, 0);
+ for (i = 0; i < 40; i++) {
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 3, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(1), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 0, 0, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(0), i,
+ true, GLOBAL_ID(0));
- for (i = 0; i < 40; i++)
- trdc_mbc_blk_config(0x4901, 3, 0, 1, i, true, 0);
+ trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(0), MEM(1), i,
+ true, GLOBAL_ID(0));
}
}
void trdc_init(void)
{
/* TRDC mega */
- if (trdc_mrc_enabled(0x4901)) {
+ if (trdc_mrc_enabled(TRDC_NIC_BASE)) {
/* DDR */
- trdc_mrc_set_control(0x4901, 0, 0, 0x);
+ trdc_mrc_set_control(TRDC_NIC_BASE, MRC(0), GLOBAL_ID(0),
PERM(0x));
/* ELE */
- trdc_mrc_region_config(0x4901, 0, 0, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(0),
0x8000,
+ 0x, false, GLOBAL_ID(0));
/* MTR */
- trdc_mrc_region_config(0x4901, 0, 1, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(1),
0x8000,
+ 0x, false, GLOBAL_ID(0));
/* M33 */
- trdc_mrc_region_config(0x4901, 0, 2, 0x8000,
0x, false, 0);
+ trdc_mrc_region_config(TRDC_NIC_BASE, MRC(0), DOM(2),
0x8000,
+ 0x,
[PATCH 17/21] imx9: trdc: introduce trdc_mbc_blk_num
From: Peng Fan
Add trdc_mbc_blk_num to get num blks in a MBC mem slot, then drop
the hardcoded value '40' for NIC OCRAM configuration.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/trdc.c | 21 -
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx9/trdc.c b/arch/arm/mach-imx/imx9/trdc.c
index ae1a46d1331..ef0f8b52a4d 100644
--- a/arch/arm/mach-imx/imx9/trdc.c
+++ b/arch/arm/mach-imx/imx9/trdc.c
@@ -19,6 +19,7 @@
#define MRC_MAX_NUM 2
#define MBC_NUM(HWCFG) (((HWCFG) >> 16) & 0xF)
#define MRC_NUM(HWCFG) (((HWCFG) >> 24) & 0x1F)
+#define MBC_BLK_NUM(GLBCFG)((GLBCFG) & 0x3FF)
enum {
/* Order following ELE API Spec, not change */
@@ -154,6 +155,22 @@ static ulong trdc_get_mrc_base(ulong trdc_reg, u32 mrc_x)
return trdc_reg + 0x1 + 0x2000 * mbc_num + 0x1000 * mrc_x;
}
+static u32 trdc_mbc_blk_num(ulong trdc_reg, u32 mbc_x, u32 mem_x)
+{
+ struct trdc_mbc *mbc_base = (struct trdc_mbc
*)trdc_get_mbc_base(trdc_reg, mbc_x);
+ struct mbc_mem_dom *mbc_dom;
+ u32 glbcfg;
+
+ if (mbc_base == 0)
+ return 0;
+
+ /* only first dom has the glbcfg */
+ mbc_dom = &mbc_base->mem_dom[0];
+ glbcfg = readl((uintptr_t)&mbc_dom->mem_glbcfg[mem_x]);
+
+ return MBC_BLK_NUM(glbcfg);
+}
+
int trdc_mbc_set_control(ulong trdc_reg, u32 mbc_x, u32 glbac_id, u32
glbac_val)
{
struct trdc_mbc *mbc_base = (struct trdc_mbc
*)trdc_get_mbc_base(trdc_reg, mbc_x);
@@ -383,6 +400,7 @@ int release_rdc(u8 xrdc)
void trdc_early_init(void)
{
int ret = 0, i;
+ u32 blks;
ret |= release_rdc(TRDC_A);
ret |= release_rdc(TRDC_M);
@@ -397,7 +415,8 @@ void trdc_early_init(void)
/* Set OCRAM to RWX for secure, when OEM_CLOSE, the image is RX only */
trdc_mbc_set_control(TRDC_NIC_BASE, MBC(3), GLOBAL_ID(0), PERM(0x7700));
- for (i = 0; i < 40; i++) {
+ blks = trdc_mbc_blk_num(TRDC_NIC_BASE, MBC(3), MEM(0));
+ for (i = 0; i < blks; i++) {
trdc_mbc_blk_config(TRDC_NIC_BASE, MBC(3), DOM(3), MEM(0), i,
true, GLOBAL_ID(0));
--
2.35.3
[PATCH 15/21] imx: generalize fixup_thermal_trips
From: Peng Fan
i.MX8M and i.MX9 have duplicated fixup_thermal_trips, so move it
to arch/arm/mach-imx/fdt.c to avoid duplicated code.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 1 +
arch/arm/mach-imx/fdt.c | 42 +++
arch/arm/mach-imx/imx8m/soc.c | 42 ---
arch/arm/mach-imx/imx9/soc.c | 42 ---
4 files changed, 43 insertions(+), 84 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index c146a223b71..31ace977d2b 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -280,4 +280,5 @@ enum boot_device get_boot_device(void);
int disable_cpu_nodes(void *blob, const char * const *nodes_path,
u32 num_disabled_cores, u32 max_cores);
+int fixup_thermal_trips(void *blob, const char *name);
#endif
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
index df6fbf51dba..ac782e3ee63 100644
--- a/arch/arm/mach-imx/fdt.c
+++ b/arch/arm/mach-imx/fdt.c
@@ -85,3 +85,45 @@ int disable_cpu_nodes(void *blob, const char * const
*nodes_path, u32 num_disabl
return 0;
}
+
+int fixup_thermal_trips(void *blob, const char *name)
+{
+ int minc, maxc;
+ int node, trip;
+
+ node = fdt_path_offset(blob, "/thermal-zones");
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, name);
+ if (node < 0)
+ return node;
+
+ node = fdt_subnode_offset(blob, node, "trips");
+ if (node < 0)
+ return node;
+
+ get_cpu_temp_grade(&minc, &maxc);
+
+ fdt_for_each_subnode(trip, blob, node) {
+ const char *type;
+ int temp, ret;
+
+ type = fdt_getprop(blob, trip, "type", NULL);
+ if (!type)
+ continue;
+
+ temp = 0;
+ if (!strcmp(type, "critical"))
+ temp = 1000 * (maxc - 5);
+ else if (!strcmp(type, "passive"))
+ temp = 1000 * (maxc - 10);
+ if (temp) {
+ ret = fdt_setprop_u32(blob, trip, "temperature", temp);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 68d5762c2ce..dd2d1796e3d 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1166,48 +1166,6 @@ static int cleanup_nodes_for_efi(void *blob)
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
-{
- int minc, maxc;
- int node, trip;
-
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
-
- get_cpu_temp_grade(&minc, &maxc);
-
- fdt_for_each_subnode(trip, blob, node) {
- const char *type;
- int temp, ret;
-
- type = fdt_getprop(blob, trip, "type", NULL);
- if (!type)
- continue;
-
- temp = 0;
- if (!strcmp(type, "critical"))
- temp = 1000 * maxc;
- else if (!strcmp(type, "passive"))
- temp = 1000 * (maxc - 10);
- if (temp) {
- ret = fdt_setprop_u32(blob, trip, "temperature", temp);
- if (ret)
- return ret;
- }
- }
-
- return 0;
-}
-
#define OPTEE_SHM_SIZE 0x0040
static int ft_add_optee_node(void *fdt, struct bd_info *bd)
{
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index d00162c6fdf..9ec8ac2599f 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -530,48 +530,6 @@ int print_cpuinfo(void)
return 0;
}
-static int fixup_thermal_trips(void *blob, const char *name)
-{
- int minc, maxc;
- int node, trip;
-
- node = fdt_path_offset(blob, "/thermal-zones");
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, name);
- if (node < 0)
- return node;
-
- node = fdt_subnode_offset(blob, node, "trips");
- if (node < 0)
- return node;
-
- get_cpu_temp_grade(&minc, &maxc);
-
- fdt_for_each_subnode(trip, blob, node)
[PATCH 14/21] imx93: Add Low performance parts 9302/9301 support
From: Ye Li
Add support for iMX93 low performance parts 9302 and 9301 which
restrict to low drive voltage only.
The parts run A55 max speed at 900Mhz and M33 at 133Mhz, have NPU
and A55 core1 (9301) disabled.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 2 ++
arch/arm/include/asm/mach-imx/sys_proto.h | 5 -
arch/arm/mach-imx/imx9/Kconfig| 1 +
arch/arm/mach-imx/imx9/soc.c | 6 +-
drivers/cpu/imx8_cpu.c| 4
5 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx/cpu.h
b/arch/arm/include/asm/arch-imx/cpu.h
index cbd2717f97c..b0468a1a136 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -68,6 +68,8 @@
#define MXC_CPU_IMX93210xC6 /* dummy ID */
#define MXC_CPU_IMX93120xC7 /* dummy ID */
#define MXC_CPU_IMX93110xC8 /* dummy ID */
+#define MXC_CPU_IMX93020xC9 /* dummy ID */
+#define MXC_CPU_IMX93010xCA /* dummy ID */
#define MXC_SOC_MX60x60
#define MXC_SOC_MX70x70
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index d93e095e191..c146a223b71 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -85,7 +85,8 @@ struct bd_info;
#define is_imx93() (is_cpu_type(MXC_CPU_IMX93) || is_cpu_type(MXC_CPU_IMX9331)
|| \
is_cpu_type(MXC_CPU_IMX9332) || is_cpu_type(MXC_CPU_IMX9351) || \
is_cpu_type(MXC_CPU_IMX9322) || is_cpu_type(MXC_CPU_IMX9321) || \
- is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311))
+ is_cpu_type(MXC_CPU_IMX9312) || is_cpu_type(MXC_CPU_IMX9311) || \
+ is_cpu_type(MXC_CPU_IMX9302) || is_cpu_type(MXC_CPU_IMX9301))
#define is_imx9351() (is_cpu_type(MXC_CPU_IMX9351))
#define is_imx9332() (is_cpu_type(MXC_CPU_IMX9332))
#define is_imx9331() (is_cpu_type(MXC_CPU_IMX9331))
@@ -93,6 +94,8 @@ struct bd_info;
#define is_imx9321() (is_cpu_type(MXC_CPU_IMX9321))
#define is_imx9312() (is_cpu_type(MXC_CPU_IMX9312))
#define is_imx9311() (is_cpu_type(MXC_CPU_IMX9311))
+#define is_imx9302() (is_cpu_type(MXC_CPU_IMX9302))
+#define is_imx9301() (is_cpu_type(MXC_CPU_IMX9301))
#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
index e892da80fe8..63e75b6806e 100644
--- a/arch/arm/mach-imx/imx9/Kconfig
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -30,6 +30,7 @@ choice
config TARGET_IMX93_11X11_EVK
bool "imx93_11x11_evk"
+ select OF_BOARD_FIXUP
select IMX93
imply OF_UPSTREAM
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 0f8ea55eb51..d00162c6fdf 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -183,6 +183,10 @@ static u32 get_cpu_variant_type(u32 type)
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
+ /* Low performance 93 part */
+ if (((val >> 6) & 0x3F) == 0xE && npu_disable)
+ return core1_disable ? MXC_CPU_IMX9301 : MXC_CPU_IMX9302;
+
if ((val2 & pack_9x9_fused) == pack_9x9_fused)
type = MXC_CPU_IMX9322;
@@ -696,7 +700,7 @@ int ft_system_setup(void *blob, struct bd_info *bd)
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
- if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311())
+ if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311() ||
is_imx9301())
disable_cpu_nodes(blob, nodes_path, 1, 2);
if (is_voltage_mode(VOLT_LOW_DRIVE))
diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c
index 60deca963a6..6c0a8c0cbe4 100644
--- a/drivers/cpu/imx8_cpu.c
+++ b/drivers/cpu/imx8_cpu.c
@@ -60,6 +60,10 @@ static const char *get_imx_type_str(u32 imxtype)
return "93(12)";/* iMX93 9x9 Dual core without NPU */
case MXC_CPU_IMX9311:
return "93(11)";/* iMX93 9x9 Single core without NPU */
+ case MXC_CPU_IMX9302:
+ return "93(02)";/* iMX93 900Mhz Low performance Dual core
without NPU */
+ case MXC_CPU_IMX9301:
+ return "93(01)";/* iMX93 900Mhz Low performance Single core
without NPU */
default:
return "??";
}
--
2.35.3
[PATCH 12/21] imx: generialize disable_cpu_nodes
From: Peng Fan
disable_cpu_nodes could be reused by i.MX9, so move disable_cpu_nodes
out from mach-imx/imx8m/soc.c to mach-imx/fdt.c and update
disable_cpu_nodes to make it easy to support different socs.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/sys_proto.h | 2 +
arch/arm/mach-imx/Makefile| 1 +
arch/arm/mach-imx/fdt.c | 87 +++
arch/arm/mach-imx/imx8m/soc.c | 99 ---
4 files changed, 103 insertions(+), 86 deletions(-)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h
b/arch/arm/include/asm/mach-imx/sys_proto.h
index 31ae179b211..d93e095e191 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -275,4 +275,6 @@ void enable_ca7_smp(void);
enum boot_device get_boot_device(void);
+int disable_cpu_nodes(void *blob, const char * const *nodes_path,
+ u32 num_disabled_cores, u32 max_cores);
#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5262dca4ffd..47e2cb8d943 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,6 +12,7 @@ endif
ifeq ($(SOC),$(filter $(SOC),imx8m))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+obj-y += fdt.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c
new file mode 100644
index 000..df6fbf51dba
--- /dev/null
+++ b/arch/arm/mach-imx/fdt.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2024 NXP
+ */
+
+#include
+#include
+#include
+#include
+
+static void disable_thermal_cpu_nodes(void *blob, u32 num_disabled_cores, u32
max_cores)
+{
+ static const char * const thermal_path[] = {
+ "/thermal-zones/cpu-thermal/cooling-maps/map0"
+ };
+
+ int nodeoff, cnt, i, ret, j;
+ u32 num_le32 = max_cores * 3;
+ u32 *cooling_dev = (u32 *)malloc(num_le32 * sizeof(__le32));
+
+ if (!cooling_dev) {
+ printf("failed to alloc cooling dev\n");
+ return;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(thermal_path); i++) {
+ nodeoff = fdt_path_offset(blob, thermal_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ cnt = fdtdec_get_int_array_count(blob, nodeoff,
"cooling-device",
+cooling_dev, num_le32);
+ if (cnt < 0)
+ continue;
+
+ if (cnt != num_le32)
+ printf("Warning: %s, cooling-device count %d\n",
thermal_path[i], cnt);
+
+ for (j = 0; j < cnt; j++)
+ cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]);
+
+ ret = fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev,
+ sizeof(__le32) * (num_le32 -
num_disabled_cores * 3));
+ if (ret < 0) {
+ printf("Warning: %s, cooling-device setprop failed
%d\n",
+ thermal_path[i], ret);
+ continue;
+ }
+
+ printf("Update node %s, cooling-device prop\n",
thermal_path[i]);
+ }
+
+ free(cooling_dev);
+}
+
+int disable_cpu_nodes(void *blob, const char * const *nodes_path, u32
num_disabled_cores,
+ u32 max_cores)
+{
+ u32 i = 0;
+ int rc;
+ int nodeoff;
+
+ if (max_cores == 0 || (num_disabled_cores > (max_cores - 1)))
+ return -EINVAL;
+
+ i = max_cores - num_disabled_cores;
+
+ for (; i < max_cores; i++) {
+ nodeoff = fdt_path_offset(blob, nodes_path[i]);
+ if (nodeoff < 0)
+ continue; /* Not found, skip it */
+
+ debug("Found %s node\n", nodes_path[i]);
+
+ rc = fdt_del_node(blob, nodeoff);
+ if (rc < 0) {
+ printf("Unable to delete node %s, err=%s\n",
+ nodes_path[i], fdt_strerror(rc));
+ } else {
+ printf("Delete node %s\n", nodes_path[i]);
+ }
+ }
+
+ disable_thermal_cpu_nodes(blob, num_disabled_cores, max_cores);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 9ed27b59303..68d5762c2ce 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1135,79 +1135,6 @@ int disable_dsp_nodes(void *blob)
return disable_fdt_nodes(blob, nodes_path_8mp,
ARRAY_SIZE(nodes_path_8mp));
}
-static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char
[PATCH 13/21] imx9: soc: Disable cpu1 for variants that only has one A55 core
From: Peng Fan
Disale CPU1 for i.MX93 variants that only has one A55 core and update
cooling maps.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/Makefile | 7 ++-
arch/arm/mach-imx/imx9/soc.c | 8
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 47e2cb8d943..f8903afc92e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,6 @@ endif
ifeq ($(SOC),$(filter $(SOC),imx8m))
ifneq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
-obj-y += fdt.o
endif
obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o
obj-$(CONFIG_FEC_MXC) += mac.o
@@ -22,6 +21,12 @@ obj-$(CONFIG_IMX_HAB) += hab.o
obj-y += cpu.o
endif
+ifeq ($(SOC),$(filter $(SOC),imx8m imx9))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += fdt.o
+endif
+endif
+
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += cpu.o speed.o
ifneq ($(CONFIG_MX51),y)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index a73e73adfe6..0f8ea55eb51 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -688,9 +688,17 @@ int board_fix_fdt(void *fdt)
int ft_system_setup(void *blob, struct bd_info *bd)
{
+ static const char * const nodes_path[] = {
+ "/cpus/cpu@0",
+ "/cpus/cpu@100",
+ };
+
if (fixup_thermal_trips(blob, "cpu-thermal"))
printf("Failed to update cpu-thermal trip(s)");
+ if (is_imx9351() || is_imx9331() || is_imx9321() || is_imx9311())
+ disable_cpu_nodes(blob, nodes_path, 1, 2);
+
if (is_voltage_mode(VOLT_LOW_DRIVE))
low_drive_freq_update(blob);
--
2.35.3
[PATCH 11/21] imx8m: soc: Drop disable_pmu_cpu_nodes
From: Peng Fan
i.MX8M use PPI for PMU interrupts, there is no reason to update
interrupt-affinity for PMU even interrupt-affinity was wrongly added
to device tree before.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 38 --
1 file changed, 38 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index be38ca52885..9ed27b59303 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1171,43 +1171,6 @@ static void disable_thermal_cpu_nodes(void *blob, u32
disabled_cores)
}
}
-static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores)
-{
- static const char * const pmu_path[] = {
- "/pmu"
- };
-
- int nodeoff, cnt, i, ret, j;
- u32 irq_affinity[4];
-
- for (i = 0; i < ARRAY_SIZE(pmu_path); i++) {
- nodeoff = fdt_path_offset(blob, pmu_path[i]);
- if (nodeoff < 0)
- continue; /* Not found, skip it */
-
- cnt = fdtdec_get_int_array_count(blob, nodeoff,
"interrupt-affinity",
-irq_affinity, 4);
- if (cnt < 0)
- continue;
-
- if (cnt != 4)
- printf("Warning: %s, interrupt-affinity count %d\n",
pmu_path[i], cnt);
-
- for (j = 0; j < cnt; j++)
- irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]);
-
- ret = fdt_setprop(blob, nodeoff, "interrupt-affinity",
&irq_affinity,
-sizeof(u32) * (4 - disabled_cores));
- if (ret < 0) {
- printf("Warning: %s, interrupt-affinity setprop failed
%d\n",
- pmu_path[i], ret);
- continue;
- }
-
- printf("Update node %s, interrupt-affinity prop\n",
pmu_path[i]);
- }
-}
-
static int disable_cpu_nodes(void *blob, u32 disabled_cores)
{
static const char * const nodes_path[] = {
@@ -1241,7 +1204,6 @@ static int disable_cpu_nodes(void *blob, u32
disabled_cores)
}
disable_thermal_cpu_nodes(blob, disabled_cores);
- disable_pmu_cpu_nodes(blob, disabled_cores);
return 0;
}
--
2.35.3
[PATCH 10/21] imx9: Add 233Mhz DDR PLL frequency
From: Ye Li
To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/clock.c | 1 +
drivers/ddr/imx/phy/ddrphy_utils.c | 4
2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 76d19f1cba3..12685f970de 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -41,6 +41,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(46600U, 1, 155, 8, 1, 3), /* 466Mhz */
FRAC_PLL_RATE(4U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(3U, 1, 150, 12, 0, 1),
+ FRAC_PLL_RATE(23300U, 1, 174, 18, 3, 4), /* 233Mhz */
};
/* return in khz */
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c
b/drivers/ddr/imx/phy/ddrphy_utils.c
index cf5bdad7abe..14278f5ad8f 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(266));
dram_disable_bypass();
break;
+ case 933:
+ dram_pll_init(MHZ(233));
+ dram_disable_bypass();
+ break;
case 667:
dram_pll_init(MHZ(167));
dram_disable_bypass();
--
2.35.3
[PATCH 09/21] imx9: soc: Mask the wdog reset in src by default on i.mx9
From: Jacky Bai
Normally, the wdog will be used for trigger external PMIC reset
through the WDOG_ANY pin. If the PMIC chip has debounce logic for
the reset signal, in some corner case the wdog can NOT trigger
external PMIC reset if the SoC has been reset internal before the
PMIC captures the WDOG_ANY pin reset, so need to keep the WDOG3-5
reset masked in the SRC to let the PMIC to do the reset safely.
Reviewed-by: Ye Li
Signed-off-by: Jacky Bai
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 8a577b98255..a73e73adfe6 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -232,15 +232,9 @@ static void disable_wdog(void __iomem *wdog_base)
void init_wdog(void)
{
- u32 src_val;
-
disable_wdog((void __iomem *)WDG3_BASE_ADDR);
disable_wdog((void __iomem *)WDG4_BASE_ADDR);
disable_wdog((void __iomem *)WDG5_BASE_ADDR);
-
- src_val = readl(0x54460018); /* reset mask */
- src_val &= ~0x1c;
- writel(src_val, 0x54460018);
}
static struct mm_region imx93_mem_map[] = {
--
2.35.3
[PATCH 07/21] imx9: soc: Add function to get target voltage mode
From: Ye Li
Replace the static CONFIG_IMX9_LOW_DRIVE_MODE with runtime target
voltage mode by checking the part's SPEED GRADE fuse.
SPL will configure to highest A55 speed which is indicated by the SPEED
fuse and select corresponding voltage mode.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/sys_proto.h | 11 +++
arch/arm/mach-imx/imx9/clock.c | 31 +++--
arch/arm/mach-imx/imx9/soc.c | 107 +
board/freescale/imx93_evk/spl.c| 2 +-
4 files changed, 143 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h
b/arch/arm/include/asm/arch-imx9/sys_proto.h
index 2f7a1292758..e4bf6a63424 100644
--- a/arch/arm/include/asm/arch-imx9/sys_proto.h
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -8,7 +8,18 @@
#include
+enum imx9_soc_voltage_mode {
+ VOLT_LOW_DRIVE = 0,
+ VOLT_NOMINAL_DRIVE,
+ VOLT_OVER_DRIVE,
+};
+
void soc_power_init(void);
bool m33_is_rom_kicked(void);
int m33_prepare(void);
+
+enum imx9_soc_voltage_mode soc_target_voltage_mode(void);
+
+#define is_voltage_mode(mode) (soc_target_voltage_mode() == (mode))
+
#endif
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 0abf4579a1e..1433e68874d 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -603,7 +603,7 @@ void init_clk_usdhc(u32 index)
{
u32 div;
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (is_voltage_mode(VOLT_LOW_DRIVE))
div = 3; /* 266.67 Mhz */
else
div = 2; /* 400 Mhz */
@@ -700,8 +700,7 @@ void set_arm_core_max_clk(void)
#endif
-#if IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE)
-struct imx_clk_setting imx_clk_settings[] = {
+struct imx_clk_setting imx_clk_ld_settings[] = {
/* Set A55 clk to 500M */
{ARM_A55_CLK_ROOT, SYS_PLL_PFD0, 2},
/* Set A55 periphal to 200M */
@@ -728,7 +727,7 @@ struct imx_clk_setting imx_clk_settings[] = {
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#else
+
struct imx_clk_setting imx_clk_settings[] = {
/*
* Set A55 clk to 500M. This clock root is normally used as intermediate
@@ -762,9 +761,18 @@ struct imx_clk_setting imx_clk_settings[] = {
/* NIC_APB to 133M */
{NIC_APB_CLK_ROOT, SYS_PLL_PFD1_DIV2, 3}
};
-#endif
-int clock_init(void)
+void bus_clock_init_low_drive(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx_clk_ld_settings); i++) {
+ ccm_clk_root_cfg(imx_clk_ld_settings[i].clk_root,
+imx_clk_ld_settings[i].src,
imx_clk_ld_settings[i].div);
+ }
+}
+
+void bus_clock_init(void)
{
int i;
@@ -772,9 +780,18 @@ int clock_init(void)
ccm_clk_root_cfg(imx_clk_settings[i].clk_root,
imx_clk_settings[i].src,
imx_clk_settings[i].div);
}
+}
- if (IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+int clock_init(void)
+{
+ int i;
+
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ bus_clock_init_low_drive();
set_arm_clk(MHZ(900));
+ } else {
+ bus_clock_init();
+ }
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 5b0fada8295..a55863bf456 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -607,11 +607,99 @@ int arch_misc_init(void)
return 0;
}
+struct low_drive_freq_entry {
+ const char *node_path;
+ u32 clk;
+ u32 new_rate;
+};
+
+static int low_drive_fdt_fix_clock(void *fdt, int node_off, u32 clk_index, u32
new_rate)
+{
+#define MAX_ASSIGNED_CLKS 8
+ int cnt, j;
+ u32 assignedclks[MAX_ASSIGNED_CLKS]; /* max 8 clocks*/
+
+ cnt = fdtdec_get_int_array_count(fdt, node_off, "assigned-clock-rates",
+assignedclks, MAX_ASSIGNED_CLKS);
+ if (cnt > 0) {
+ if (cnt <= clk_index)
+ return -ENOENT;
+
+ if (assignedclks[clk_index] <= new_rate)
+ return 0;
+
+ assignedclks[clk_index] = new_rate;
+ for (j = 0; j < cnt; j++)
+ assignedclks[j] = cpu_to_fdt32(assignedclks[j]);
+
+ return fdt_setprop(fdt, node_off, "assigned-clock-rates",
&assignedclks,
+ cnt * sizeof(u32));
+ }
+
+ return -ENOENT;
+}
+
+static int low_drive_freq_update(void *blob)
+{
+ int nodeoff, ret;
+ int i;
+
+ /* Update kernel dtb clocks for low drive mode */
+ struct low_drive_freq_entry table[] = {
+ {"/soc@0/bus@4280/mmc@4285", 0, 2
[PATCH 08/21] imx9: clock: Update clock init function and sequence
From: Ye Li
Since we use SPEED GRADE fuse to set A55 frequency, remove the
set_arm_core_low_drive_clk function which has hard coded frequency.
And adjust clock_init called sequence and split it to early and late
functions.
Set the authen register in early function, because CCF driver checks
NS bit.
Set bus and core clock in late function, because the fuse read and
SoC type/rev depend on ELE.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/clock.h | 3 ++-
arch/arm/mach-imx/imx9/clock.c | 22 ++
arch/arm/mach-imx/imx9/soc.c | 2 +-
board/freescale/imx93_evk/spl.c| 4 +++-
board/phytec/phycore_imx93/spl.c | 2 +-
5 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/arch/arm/include/asm/arch-imx9/clock.h
b/arch/arm/include/asm/arch-imx9/clock.h
index 1ce6ac4c3a8..76f12118592 100644
--- a/arch/arm/include/asm/arch-imx9/clock.h
+++ b/arch/arm/include/asm/arch-imx9/clock.h
@@ -211,7 +211,8 @@ struct imx_clk_setting {
u32 div;
};
-int clock_init(void);
+int clock_init_early(void);
+int clock_init_late(void);
u32 get_clk_src_rate(enum ccm_clk_src source);
u32 get_lpuart_clk(void);
void init_uart_clk(u32 index);
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 1433e68874d..76d19f1cba3 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -782,17 +782,10 @@ void bus_clock_init(void)
}
}
-int clock_init(void)
+int clock_init_early(void)
{
int i;
- if (is_voltage_mode(VOLT_LOW_DRIVE)) {
- bus_clock_init_low_drive();
- set_arm_clk(MHZ(900));
- } else {
- bus_clock_init();
- }
-
/* allow for non-secure access */
for (i = 0; i < OSCPLL_END; i++)
ccm_clk_src_tz_access(i, true, false, false);
@@ -809,6 +802,19 @@ int clock_init(void)
return 0;
}
+/* Set bus and A55 core clock per voltage mode */
+int clock_init_late(void)
+{
+ if (is_voltage_mode(VOLT_LOW_DRIVE)) {
+ bus_clock_init_low_drive();
+ set_arm_core_max_clk();
+ } else {
+ bus_clock_init();
+ }
+
+ return 0;
+}
+
int set_clk_eqos(enum enet_freq type)
{
u32 eqos_post_div;
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index a55863bf456..8a577b98255 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -733,7 +733,7 @@ int arch_cpu_init(void)
/* Disable wdog */
init_wdog();
- clock_init();
+ clock_init_early();
trdc_early_init();
diff --git a/board/freescale/imx93_evk/spl.c b/board/freescale/imx93_evk/spl.c
index e4999baa95f..2ad7489ada7 100644
--- a/board/freescale/imx93_evk/spl.c
+++ b/board/freescale/imx93_evk/spl.c
@@ -123,9 +123,11 @@ void board_init_f(ulong dummy)
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
+ clock_init_late();
+
power_init_board();
- if (!IS_ENABLED(CONFIG_IMX9_LOW_DRIVE_MODE))
+ if (!is_voltage_mode(VOLT_LOW_DRIVE))
set_arm_clk(get_cpu_speed_grade_hz());
/* Init power of mix */
diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c
index 5efa38a1442..17a8736c73f 100644
--- a/board/phytec/phycore_imx93/spl.c
+++ b/board/phytec/phycore_imx93/spl.c
@@ -130,7 +130,7 @@ void board_init_f(ulong dummy)
debug("LC: 0x%x\n", gd->arch.lifecycle);
}
- clock_init();
+ clock_init_late();
power_init_board();
--
2.35.3
[PATCH 06/21] imx9: soc: Change second Ethernet MAC fuse layout
From: Peng Fan
The second Ethernet MAC (eQOS) fuse layout is changed since i.MX93 A1
following other i.MX platforms, for example i.MX8MP.
Order for A0:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
Order since A1:
MAC1_ADDR[15:0]
MAC1_ADDR[31:16]
MAC1_ADDR[47:32]
MAC2_ADDR[15:0]
MAC2_ADDR[31:16]
MAC2_ADDR[47:32]
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 54 +++-
1 file changed, 48 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 42c6deedbf2..5b0fada8295 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -496,12 +496,21 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
if (ret)
goto err;
- mac[0] = val[1] >> 24;
- mac[1] = val[1] >> 16;
- mac[2] = val[0] >> 24;
- mac[3] = val[0] >> 16;
- mac[4] = val[0] >> 8;
- mac[5] = val[0];
+ if (is_imx93() && is_soc_rev(CHIP_REV_1_0)) {
+ mac[0] = val[1] >> 24;
+ mac[1] = val[1] >> 16;
+ mac[2] = val[0] >> 24;
+ mac[3] = val[0] >> 16;
+ mac[4] = val[0] >> 8;
+ mac[5] = val[0];
+ } else {
+ mac[0] = val[0] >> 24;
+ mac[1] = val[0] >> 16;
+ mac[2] = val[0] >> 8;
+ mac[3] = val[0];
+ mac[4] = val[1] >> 24;
+ mac[5] = val[1] >> 16;
+ }
}
debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n",
@@ -565,6 +574,39 @@ static int fixup_thermal_trips(void *blob, const char
*name)
return 0;
}
+void build_info(void)
+{
+ u32 fw_version, sha1, res, status;
+ int ret;
+
+ printf("\nBuildInfo:\n");
+
+ ret = ele_get_fw_status(&status, &res);
+ if (ret) {
+ printf(" - ELE firmware status failed %d, 0x%x\n", ret, res);
+ } else if ((status & 0xff) == 1) {
+ ret = ele_get_fw_version(&fw_version, &sha1, &res);
+ if (ret) {
+ printf(" - ELE firmware version failed %d, 0x%x\n",
ret, res);
+ } else {
+ printf(" - ELE firmware version %u.%u.%u-%x",
+ (fw_version & (0x00ff)) >> 16,
+ (fw_version & (0xfff0)) >> 4,
+ (fw_version & (0x000f)), sha1);
+ ((fw_version & (0x8000)) >> 31) == 1 ?
puts("-dirty\n") : puts("\n");
+ }
+ } else {
+ printf(" - ELE firmware not included\n");
+ }
+ puts("\n");
+}
+
+int arch_misc_init(void)
+{
+ build_info();
+ return 0;
+}
+
int ft_system_setup(void *blob, struct bd_info *bd)
{
if (fixup_thermal_trips(blob, "cpu-thermal"))
--
2.35.3
[PATCH 05/21] imx9: soc: Change FSB directly access to fuse API
From: Ye Li
To support OSCCA enabled part which has disabled FSB access from SOC,
change directly read from FSB to use fuse_read API.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 26 +-
1 file changed, 21 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 7df3c686350..42c6deedbf2 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -96,10 +96,14 @@ int mmc_get_env_dev(void)
*/
u32 get_cpu_speed_grade_hz(void)
{
+ int ret;
u32 speed, max_speed;
u32 val;
- fuse_read(2, 3, &val);
+ ret = fuse_read(2, 3, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
val = FIELD_GET(SPEED_GRADING_MASK, val) & 0xF;
speed = MHZ(2300) - val * MHZ(100);
@@ -122,9 +126,13 @@ u32 get_cpu_speed_grade_hz(void)
*/
u32 get_cpu_temp_grade(int *minc, int *maxc)
{
+ int ret;
u32 val;
- fuse_read(2, 3, &val);
+ ret = fuse_read(2, 3, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
val = FIELD_GET(MARKETING_GRADING_MASK, val);
if (minc && maxc) {
@@ -160,9 +168,17 @@ static void set_cpu_info(struct ele_get_info_data *info)
static u32 get_cpu_variant_type(u32 type)
{
- /* word 19 */
- u32 val = readl((ulong)FSB_BASE_ADDR + 0x8000 + (19 << 2));
- u32 val2 = readl((ulong)FSB_BASE_ADDR + 0x8000 + (20 << 2));
+ u32 val, val2;
+ int ret;
+
+ ret = fuse_read(2, 3, &val);
+ if (ret)
+ val = 0; /* If read fuse failed, return as blank fuse */
+
+ ret = fuse_read(2, 4, &val2);
+ if (ret)
+ val2 = 0; /* If read fuse failed, return as blank fuse */
+
bool npu_disable = !!(val & BIT(13));
bool core1_disable = !!(val & BIT(15));
u32 pack_9x9_fused = BIT(4) | BIT(17) | BIT(19) | BIT(24);
--
2.35.3
[PATCH 04/21] imx9: soc: Print UID in big endian format for EL2GO
From: Ye Li
Print UID in big endian format and as one buffer of bytes, so customer
can directly use it for EL2GO.
Before:
UID: 0xf6c8ae93 0x0f46b326 0x10d61eb3 0x0583c2d2
Become:
UID: 93aec8f626b3460fb31ed610d2c28305
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index f458fc0564e..7df3c686350 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -560,8 +560,9 @@ int ft_system_setup(void *blob, struct bd_info *bd)
#if defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
void get_board_serial(struct tag_serialnr *serialnr)
{
- printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
- gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
+ printf("UID: %08x%08x%08x%08x\n", __be32_to_cpu(gd->arch.uid[0]),
+ __be32_to_cpu(gd->arch.uid[1]), __be32_to_cpu(gd->arch.uid[2]),
+ __be32_to_cpu(gd->arch.uid[3]));
serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
--
2.35.3
[PATCH 03/21] imx9: soc: Serial No align with rom setting
From: Frank Li
ROM use UID[0] and UID[1] as serial number with big endian when usb serial
download.
After update this, uuu(>1.6) can use below command to filter out devices
when multi boards connected.
uuu -ms ...
[sudo] uuu -lsusb can list known devices with serial# informaiton.
Signed-off-by: Frank Li
Reviewed-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx9/soc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 25b9116f2a6..f458fc0564e 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -563,8 +563,8 @@ void get_board_serial(struct tag_serialnr *serialnr)
printf("UID: 0x%x 0x%x 0x%x 0x%x\n",
gd->arch.uid[0], gd->arch.uid[1], gd->arch.uid[2],
gd->arch.uid[3]);
- serialnr->low = gd->arch.uid[0];
- serialnr->high = gd->arch.uid[3];
+ serialnr->low = __be32_to_cpu(gd->arch.uid[1]);
+ serialnr->high = __be32_to_cpu(gd->arch.uid[0]);
}
#endif
--
2.35.3
[PATCH 02/21] imx9: soc: Configure TRDC for M33 TCM access
From: Ye Li
On OSCCA part, M33 TCM is used for ROM PATCH and protected by ELE ROM.
So after release TRDC, we need to configure TRDC for M33 TCM,
otherwise A55 can't access the TCM.
Reviewed-by: Peng Fan
Signed-off-by: Ye Li
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 14 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 9953c33b73b..fb6de533d12 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -25,6 +25,7 @@
#define ANATOP_BASE_ADDR0x4448UL
#define BLK_CTRL_WAKEUPMIX_BASE_ADDR 0x4242
+#define BLK_CTRL_NS_ANOMIX_BASE_ADDR 0x4421
#define BLK_CTRL_S_ANOMIX_BASE_ADDR 0x444f
#define SRC_IPS_BASE_ADDR (0x4446)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 9b6ba5609d2..25b9116f2a6 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -792,7 +792,7 @@ int m33_prepare(void)
(struct src_general_regs *)(ulong)SRC_GLOBAL_RBASE;
struct blk_ctrl_s_aonmix_regs *s_regs =
(struct blk_ctrl_s_aonmix_regs
*)BLK_CTRL_S_ANOMIX_BASE_ADDR;
- u32 val;
+ u32 val, i;
if (m33_is_rom_kicked())
return -EPERM;
@@ -817,6 +817,18 @@ int m33_prepare(void)
/* Set ELE LP handshake for M33 reset */
setbits_le32(&s_regs->lp_handshake[0], BIT(6));
+ /* OSCCA enabled, reconfigure TRDC for TCM access, otherwise ECC init
will raise error */
+ val = readl(BLK_CTRL_NS_ANOMIX_BASE_ADDR + 0x28);
+ if (val & BIT(0)) {
+ trdc_mbc_set_control(0x4427, 1, 0, 0x6600);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x4427, 1, 3, 0, i, true, 0);
+
+ for (i = 0; i < 32; i++)
+ trdc_mbc_blk_config(0x4427, 1, 3, 1, i, true, 0);
+ }
+
/* Clear M33 TCM for ECC */
memset((void *)(ulong)0x201e, 0, 0x4);
--
2.35.3
[PATCH 01/21] imx9: soc: wait ssar when power on power domain
From: Peng Fan
SSAR handshake done means power on finished, not ISO done. so correct
the waiting mask.
Fixes: 0256577a83b ("imx: imx9: Add MIX power init")
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx9/imx-regs.h | 1 +
arch/arm/mach-imx/imx9/soc.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h
b/arch/arm/include/asm/arch-imx9/imx-regs.h
index 76d241eab09..9953c33b73b 100644
--- a/arch/arm/include/asm/arch-imx9/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -38,6 +38,7 @@
#define SRC_MIX_SLICE_FUNC_STAT_PSW_STAT BIT(0)
#define SRC_MIX_SLICE_FUNC_STAT_RST_STAT BIT(2)
#define SRC_MIX_SLICE_FUNC_STAT_ISO_STAT BIT(4)
+#define SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT BIT(8)
#define SRC_MIX_SLICE_FUNC_STAT_MEM_STAT BIT(12)
#define IMG_CONTAINER_BASE (0x8000UL)
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
index 32208220b20..9b6ba5609d2 100644
--- a/arch/arm/mach-imx/imx9/soc.c
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -752,7 +752,7 @@ static int mix_power_init(enum mix_power_domain pd)
/* power on */
clrbits_le32(&mix_regs->slice_sw_ctrl, BIT(31));
val = readl(&mix_regs->func_stat);
- while (val & SRC_MIX_SLICE_FUNC_STAT_ISO_STAT)
+ while (val & SRC_MIX_SLICE_FUNC_STAT_SSAR_STAT)
val = readl(&mix_regs->func_stat);
return 0;
--
2.35.3
[PATCH 00/21] imx9: various update
Several updates to i.MX9 SOC and i.MX93 EVK, the related code has been in NXP downstream for some time and gone through several public releases. Some are directly cherry-picked(with R-b kept), some are modified from downtream. This patchset includes: power domain on fixes TRDC cleanup and update MAC address update i.MX9301/9302 included. runtime detection of voltage mode PMIC update generalize some code for i.MX8M and i.MX9 i.MX93 EVK update and misc. CI passed. Signed-off-by: Peng Fan --- Frank Li (1): imx9: soc: Serial No align with rom setting Jacky Bai (1): imx9: soc: Mask the wdog reset in src by default on i.mx9 Peng Fan (11): imx9: soc: wait ssar when power on power domain imx9: soc: Change second Ethernet MAC fuse layout imx8m: soc: Drop disable_pmu_cpu_nodes imx: generialize disable_cpu_nodes imx9: soc: Disable cpu1 for variants that only has one A55 core imx: generalize fixup_thermal_trips imx9: trdc: cleanup code imx9: trdc: introduce trdc_mbc_blk_num imx93_evk: spl: update pmic settings imx93_evk: Remove CONFIG_IMX9_LOW_DRIVE_MODE and ld defconfig imx93_evk: add back Low drive mode ddr timing file Ye Li (8): imx9: soc: Configure TRDC for M33 TCM access imx9: soc: Print UID in big endian format for EL2GO imx9: soc: Change FSB directly access to fuse API imx9: soc: Add function to get target voltage mode imx9: clock: Update clock init function and sequence imx9: Add 233Mhz DDR PLL frequency imx93: Add Low performance parts 9302/9301 support imx93_evk: Enable M.2 VPCIe_3V3 and deassert SD3_nRST arch/arm/include/asm/arch-imx/cpu.h|2 + arch/arm/include/asm/arch-imx9/clock.h |3 +- arch/arm/include/asm/arch-imx9/imx-regs.h |7 + arch/arm/include/asm/arch-imx9/sys_proto.h | 11 + arch/arm/include/asm/mach-imx/sys_proto.h |8 +- arch/arm/mach-imx/Makefile |6 + arch/arm/mach-imx/fdt.c| 129 ++ arch/arm/mach-imx/imx8m/soc.c | 179 +- arch/arm/mach-imx/imx9/Kconfig |6 +- arch/arm/mach-imx/imx9/clock.c | 40 +- arch/arm/mach-imx/imx9/soc.c | 246 ++- arch/arm/mach-imx/imx9/trdc.c | 175 +- board/freescale/imx93_evk/Makefile |6 +- board/freescale/imx93_evk/imx93_evk.c | 33 + board/freescale/imx93_evk/lpddr4x_timing_1866mts.c | 1995 board/freescale/imx93_evk/lpddr4x_timing_ld.c | 1496 --- board/freescale/imx93_evk/spl.c| 55 +- board/phytec/phycore_imx93/spl.c |2 +- configs/imx93_11x11_evk_ld_defconfig | 126 -- drivers/cpu/imx8_cpu.c |4 + drivers/ddr/imx/phy/ddrphy_utils.c |4 + include/power/pca9450.h|2 + 22 files changed, 2602 insertions(+), 1933 deletions(-) --- base-commit: 1630ff26cc960439b5949b80cfc604a2c8aa47dd change-id: 20240916-imx9-update-0ce38f6ccd3d Best regards, -- Peng Fan
RE: [PATCH] imx8mq-u-boot: Pass FIT offset to fix boot regression
> Subject: [PATCH] imx8mq-u-boot: Pass FIT offset to fix boot regression
>
> Since commit 37e50627efac ("ARM: dts: imx: Convert i.MX8M
> flash.bin image generation to binman") the imx8mq-evk fails to boot:
>
> U-Boot SPL 2024.10-rc4 (Sep 09 2024 - 16:08:22 -0300)
> PMIC: PFUZE100 ID=0x10
> SEC0: RNG instantiated
> Normal Boot
> Trying to boot from MMC2
>
> Fix it by passing the offset property for the FIT image, just like it is done
> on i.MX8MM.
>
> Fixes: 37e50627efac ("ARM: dts: imx: Convert i.MX8M flash.bin image
> generation to binman")
> Signed-off-by: Fabio Estevam
Reviewed-by: Peng Fan
RE: [PATCH v2] ARM: imx: Enable MMU and dcache very early on i.MX8M
> Subject: [PATCH v2] ARM: imx: Enable MMU and dcache very early on > i.MX8M > > Enable MMU and caches very early on in the boot process on i.MX8M > in U-Boot proper. This allows board_init_f to run with icache and > dcache enabled, which saves some 700 milliseconds of boot time on > i.MX8M Plus based device. > > The 'bootstage report' output is below: > > Before: > ``` > Timer summary in microseconds (8 records): >MarkElapsed Stage > 0 0 reset > 961,363961,363 board_init_f > 1,818,874857,511 board_init_r > 1,921,474102,600 eth_common_init > 2,013,702 92,228 eth_initialize > 2,015,238 1,536 main_loop > > Accumulated time: > 32,775 dm_r >289,165 dm_f > ``` > > After: > ``` > Timer summary in microseconds (8 records): >MarkElapsed Stage > 0 0 reset > 989,466989,466 board_init_f > 1,179,100189,634 board_init_r > 1,281,456102,356 eth_common_init > 1,373,857 92,401 eth_initialize > 1,375,396 1,539 main_loop > > Accumulated time: > 12,630 dm_f > 32,635 dm_r > ``` > > Signed-off-by: Marek Vasut > --- Reviewed-by: Peng Fan
RE: [PATCH v2 3/4] mx5: Remove CFG_MXC_USB_PORT
> Subject: [PATCH v2 3/4] mx5: Remove CFG_MXC_USB_PORT > > From: Fabio Estevam > > CFG_MXC_USB_PORT is not used anywhere, so remove this unused > symbol. > > Suggested-by: Tim Harvey > Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan
RE: [PATCH v2 2/4] usb: ehci-mx5: Add a default for CFG_MXC_USB_PORTSC
> Subject: [PATCH v2 2/4] usb: ehci-mx5: Add a default for > CFG_MXC_USB_PORTSC > > From: Fabio Estevam > > Just like drivers/usb/host/ehci-mx6.c, add a default for > drivers/usb/host/ehci-mx5.c. > > The motivation for doing this is to remove CFG_MXC_USB_PORTSC > from board config files. > > All the mx5 boards, with the exeption of mx51evk, define > CFG_MXC_USB_PORTSC as: > > #define CFG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) > > So move this definition as a default into ehci-mx5.c. > > Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan
RE: [PATCH v2 1/4] imx: Remove CFG_MXC_USB_FLAGS
> Subject: [PATCH v2 1/4] imx: Remove CFG_MXC_USB_FLAGS > > From: Fabio Estevam > > CFG_MXC_USB_FLAGS is only used for drivers/usb/host/ehci-mx5.c, so > it can be removed from all the imx6/imx7/imx8m board config files. > > mx51evk.h is the only place CFG_MXC_USB_FLAGS is not set to 0. > > Suggested-by: Tim Harvey > Signed-off-by: Fabio Estevam > Reviewed-by: Marek Vasut Reviewed-by: Peng Fan
RE: [PATCH v3] gpio: mxc_gpio: fix reading state of GPIO pins in output mode
> Subject: [PATCH v3] gpio: mxc_gpio: fix reading state of GPIO pins in
> output mode
You may give a look to this
https://lore.kernel.org/u-boot/57015c5f.3080...@denx.de/
Regards,
Peng.
>
> The PSR register works correctly for GPIO pins in input mode, but
> always returns 0 for GPIO pins in output mode unless the SION bit is
> set.
>
> The DR register should be used for GPIO pins in output mode to allow
> correct getting of previously set output value.
>
> Please note that the Linux gpio-mxc driver already uses the DR register
> for all GPIO pins in output mode:
>
>
> Signed-off-by: Tomas Paukrt
> ---
> drivers/gpio/mxc_gpio.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index
> cac6b32..190c70e 100644
> --- a/drivers/gpio/mxc_gpio.c
> +++ b/drivers/gpio/mxc_gpio.c
> @@ -133,7 +133,10 @@ int gpio_get_value(unsigned gpio)
>
> regs = (struct gpio_regs *)gpio_ports[port];
>
> - val = (readl(®s->gpio_psr) >> gpio) & 0x01;
> + if ((readl(®s->gpio_dir) >> offset) & 0x01)
> + val = (readl(®s->gpio_dr) >> gpio) & 0x01;
> + else
> + val = (readl(®s->gpio_psr) >> gpio) & 0x01;
>
> return val;
> }
> @@ -210,7 +213,10 @@ static void mxc_gpio_bank_set_value(struct
> gpio_regs *regs, int offset,
>
> static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset)
> {
> - return (readl(®s->gpio_psr) >> offset) & 0x01;
> + if ((readl(®s->gpio_dir) >> offset) & 0x01)
> + return (readl(®s->gpio_dr) >> offset) & 0x01;
> + else
> + return (readl(®s->gpio_psr) >> offset) & 0x01;
> }
>
> /* set GPIO pin 'gpio' as an input */
> --
> 2.7.4
>
RE: [PATCH] mx6: Expand bmode to support ecspi3 boot
> Subject: [PATCH] mx6: Expand bmode to support ecspi3 boot > > From: Fabio Estevam > > Currently, the bmode command only supports booting from ecspi1. > > Expand it to also support booting from ecspi3. > > Signed-off-by: Fabio Estevam Acked-by: Peng Fan
RE: [PATCH] imx: imx8: fix build when CONFIG_IMX_BOOTAUX is set
> Subject: [PATCH] imx: imx8: fix build when CONFIG_IMX_BOOTAUX is
> set
>
> From: Max Krummenacher
>
> Use correct function name.
>
> Fixes: e8cd1f60d964 ("imx: imx8: bootaux: Add i.MX8 M4 boot
> support")
> Signed-off-by: Max Krummenacher
> ---
>
> arch/arm/mach-imx/imx8/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-
> imx/imx8/cpu.c index accba502e492..834aca82bcfd 100644
> --- a/arch/arm/mach-imx/imx8/cpu.c
> +++ b/arch/arm/mach-imx/imx8/cpu.c
> @@ -258,14 +258,14 @@ int arch_auxiliary_core_up(u32 core_id,
> ulong boot_private_data)
> return -EIO;
> }
>
> - if (!power_domain_lookup_name("audio_sai0", &pd))
> {
> + if (!imx8_power_domain_lookup_name("audio_sai0",
> &pd)) {
I think need to find a proper fix to this. This API is legacy API.
Thanks
Peng
RE: [PATCH 5/5] imx8ulp_evk: enable binman support
> Subject: [PATCH 5/5] imx8ulp_evk: enable binman support
>
> Signed-off-by: Gary Bisson
> ---
> arch/arm/dts/imx8ulp-evk-u-boot.dtsi | 2 ++
> arch/arm/mach-imx/imx8ulp/Kconfig| 1 +
> configs/imx8ulp_evk_defconfig| 3 ++-
> 3 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
> b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
> index 608bde3a2a3..f67fe166d31 100644
> --- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
> @@ -3,6 +3,8 @@
> * Copyright 2021 NXP
> */
>
> +#include "imx8ulp-u-boot.dtsi"
> +
> / {
> mu@2702 {
> compatible = "fsl,imx8ulp-mu";
> diff --git a/arch/arm/mach-imx/imx8ulp/Kconfig b/arch/arm/mach-
> imx/imx8ulp/Kconfig
> index 49ea25250a3..6ce6039faf9 100644
> --- a/arch/arm/mach-imx/imx8ulp/Kconfig
> +++ b/arch/arm/mach-imx/imx8ulp/Kconfig
> @@ -23,6 +23,7 @@ choice
>
> config TARGET_IMX8ULP_EVK
> bool "imx8ulp_evk"
> +select BINMAN
Tab, no space.
Regards,
Peng.
RE: [PATCH 4/5] mach-imx: Add i.MX 8ULP binman support
> Subject: [PATCH 4/5] mach-imx: Add i.MX 8ULP binman support > > - Re-use i.MX 93 Makefile target as similar boot process > - Create imx8ulp-u-boot.dtsi for binman image architecture > - Create both SPL and U-Boot containers configuration > > Key differences between the 93 and 8ULP SPL container are: > - No LPDDR training library needed for 8ULP > - 8ULP requires a uPower binary (RISC-V core) for power management > - 8ULP also requires a M33 binary to work properly > > Signed-off-by: Gary Bisson Reviewed-by: Peng Fan
RE: [PATCH 3/5] spl: binman: Disable u_boot_any symbols for i.MX 8ULP boards
> Subject: [PATCH 3/5] spl: binman: Disable u_boot_any symbols for
> i.MX 8ULP boards
>
> This is extending commit da96f93cda9 ("spl: binman: Disable
> u_boot_any symbols for i.MX93 boards") to i.MX 8ULP boards.
>
> Signed-off-by: Gary Bisson
Reviewed-by: Peng Fan
RE: [PATCH 2/5] tools: imx8image: add upower image support
> Subject: [PATCH 2/5] tools: imx8image: add upower image support > > Part of the upower management was included in a previous commit [1]. > This patch only adds the bits required to properly parse a config file > that would include the binary as follows: > IMAGE PWR upower.bin > > [1] 6ec65c8558f (tools: image: support i.MX93) > > Signed-off-by: Gary Bisson Reviewed-by: Peng Fan
RE: [PATCH 1/5] tools: imx8image: fix soc variable for ULP
> Subject: [PATCH 1/5] tools: imx8image: fix soc variable for ULP > > Fixes: 6ec65c8558f (tools: image: support i.MX93) Put this just before your "Signed-off-by". > > Currently the ULP token sets the soc as IMX9, making it impossible to > differentiate the two families of processors. > However, since the 8ULP requires specific binaries like upower which > do not exist in 93, they need to be separated. > > Signed-off-by: Gary Bisson Besides the minor comment: Reviewed-by: Peng Fan Regards, Peng.
RE: [PATCH v2] mmc: fix signed vs unsigned compare in read check in _spl_load()
> Subject: [PATCH v2] mmc: fix signed vs unsigned compare in read
> check in _spl_load()
>
> Fix signed vs unsigned compare in read check in _spl_load()
>
> Issue: when info->read() returns a negative value because of an error,
>the comparison of 'read' (signed) with 'sizeof(*header)'
>(unsigned silently converts the negative value into a very
>large unsigned value and the check on the error condition
>always return false, i.e. the error is not detected
> Symptoms: if spl_load_image_fat() is unable to find the file 'uImage',
> the SPL phase of the boot process just hangs after displaying
> the following line:
> Trying to boot from MMC1
> Fix: cast 'sizeof(*header)' to int so the compare is now between
> signed types
> Reference:
>
> Signed-off-by: Franco Venturi
> ---
>
> (no changes since v1)
>
> include/spl_load.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/spl_load.h b/include/spl_load.h index
> 1c2b296c0a..83db381202 100644
> --- a/include/spl_load.h
> +++ b/include/spl_load.h
> @@ -22,7 +22,7 @@ static inline int _spl_load(struct spl_image_info
> *spl_image,
>
> read = info->read(info, offset, ALIGN(sizeof(*header),
> spl_get_bl_len(info)),
> header);
> - if (read < sizeof(*header))
> + if (read < (int)sizeof(*header))
> return -EIO;
>
> if (image_get_magic(header) == FDT_MAGIC) {
> --
Reviewed-by: Peng Fan
RE: [PATCH v1] mmc: fix signed vs unsigned compare in read check in _spl_load()
> Subject: [PATCH v1] mmc: fix signed vs unsigned compare in read
> check in _spl_load()
>
> Fix signed vs unsigned compare in read check in _spl_load()
>
> Issue: when info->read() returns a negative value because of an error,
>the comparison of 'read' (signed) with 'sizeof(*header)'
>(unsigned silently converts the negative value into a very
>large unsigned value and the check on the error condition
>always return false, i.e. the error is not detected
> Symptoms: if spl_load_image_fat() is unable to find the file 'uImage',
> the SPL phase of the boot process just hangs after displaying
> the following line:
> Trying to boot from MMC1
> Fix: first check if 'read' is negative then check its value against
> 'sizeof(*header)'
> Reference:
>
> Signed-off-by: Franco Venturi
> ---
>
> include/spl_load.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/spl_load.h b/include/spl_load.h index
> 1c2b296c0a..1e05599d29 100644
> --- a/include/spl_load.h
> +++ b/include/spl_load.h
> @@ -22,7 +22,7 @@ static inline int _spl_load(struct spl_image_info
> *spl_image,
>
> read = info->read(info, offset, ALIGN(sizeof(*header),
> spl_get_bl_len(info)),
> header);
> - if (read < sizeof(*header))
> + if (read < 0 || read < sizeof(*header))
"read < 0" will imply that "read < sizeof(*header)", so there
should no need to include this change.
Regards,
Peng.
> return -EIO;
>
> if (image_get_magic(header) == FDT_MAGIC) {
> --
> 2.45.2
RE: [PATCH v2] warp7: Convert to OF_UPSTREAM
> Subject: [PATCH v2] warp7: Convert to OF_UPSTREAM > > Instead of using the local imx7s-warp devicetree copies from U-Boot, > convert the imx7s-warp board to OF_UPSTREAM so that the upstream > kernel devicetree can be used instead. > > Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan
RE: [PATCH] imx93-u-boot: Describe the CPU clocks in the devicetree
> Subject: [PATCH] imx93-u-boot: Describe the CPU clocks in the > devicetree > > Currently, there is an error when the i.MX93 CPU frequency is > read: > > Could not read CPU frequency: -2 > CPU: NXP i.MX93(52) Rev1.1 A55 at 0 MHz > > Fix it by describing the A55 clock nodes in the devicetree, like done on > other i.MX SoCs. > > With this change, the CPU frequency error is gone and it can be > correctly > retrieved: > > CPU: NXP i.MX93(52) Rev1.1 A55 at 1700 MHz > CPU: Industrial temperature grade (-40C to 105C) at 35C > > As the upstream imx93.dtsi does not describe the CPU clocks, keep the > clock node in imx93-u-boot.dtsi for now. > > Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan
RE: [PATCH] ARM: dts: imx8mp-beacon-kit-u-boot: Drop EQoS clock work-around
> Subject: [PATCH] ARM: dts: imx8mp-beacon-kit-u-boot: Drop EQoS
> clock work-around
>
> Since commit ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock"),
> the clocks for the DWMAC driver can be configured, and removing
> them breaks operation.
>
> Fixes: ecb1c37a7b64 ("clk: imx8mp: Add EQoS MAC clock")
> Suggested-by: Tim Harvey
> Signed-off-by: Adam Ford
Reviewed-by: Peng Fan
RE: [PATCH] mx9: Correct repeatable build error
> Subject: [PATCH] mx9: Correct repeatable build error > > For some reason every second time imx93_11x11_evk is built it gives > an > error: > >make O=/tmp/x BINMAN_ALLOW_MISSING=1 > > It seems to sometimes skip generation of the .cfgout file and then > eventually Binman complains: > >ValueError: Error 1 running 'mkimage -d ./mkimage.spl.mkimage -n > spl/u-boot-spl.cfgout -T imx8image -e 0x2049A000 > ./mkimage-out.spl.mkimage': Fail open first container file > mx93a1-ahab-container.img > > Correct this by using if_changed instead of if_changed_dep > > The only reason this hasn't come up in CI is that buildman did not retry > failing builds of current source, but now it does. > > Note: The logic in this Makefile should be moved to Binman, e.g. these > warnings duplicate Binman functionality: > > WARNING 'bl31.bin' not found, resulting binary may be not-functional > WARNING 'tee.bin' not found, resulting binary may be not-functional > > Signed-off-by: Simon Glass Reviewed-by: Peng Fan
RE: [PATCH] arm: fsl: imx8mn_bsh_smm_s2: Migrate to OF_UPSTREAM
> Subject: [PATCH] arm: fsl: imx8mn_bsh_smm_s2: Migrate to OF_UPSTREAM > > Migrate imx8mn_bsh_smm_s2 and imx8mn_bsh_smm_s2pro boards to > OF_UPSTREAM. > > Signed-off-by: Patrick Barsanti > Tested-by: Michael Trimarchi LGTM, Reviewed-by: Peng Fan
RE: [PATCH] ARM: imx: mx5: Enable BMODE command on MX53 Menlo board
> Subject: [PATCH] ARM: imx: mx5: Enable BMODE command on MX53 Menlo > board > > The board can do primary/secondary boot switching, enable the bmode > command. > > Signed-off-by: Marek Vasut Reviewed-by: Peng Fan > --- > Cc: "NXP i.MX U-Boot Team" > Cc: Fabio Estevam > Cc: Stefano Babic > Cc: u-boot@lists.denx.de > --- > configs/m53menlo_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig > index b06a614dde0..d6b47240c10 100644 > --- a/configs/m53menlo_defconfig > +++ b/configs/m53menlo_defconfig > @@ -22,6 +22,7 @@ CONFIG_SPL=y > CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y > CONFIG_ENV_OFFSET_REDUND=0x18 > CONFIG_SYS_LOAD_ADDR=0x7080 > +CONFIG_CMD_BMODE=y > CONFIG_FIT=y > CONFIG_BOOTDELAY=-2 > CONFIG_OF_BOARD_SETUP=y > -- > 2.43.0
RE: [PATCH] ARM: dts: imx8mm: Enable CPLD_Dn pull down resistor on MX8Menlo
> Subject: [PATCH] ARM: dts: imx8mm: Enable CPLD_Dn pull down resistor on
> MX8Menlo
>
> Enable CPLD_Dn pull down resistor instead of pull up to avoid intefering with
> CPLD power off functionality.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: "NXP i.MX U-Boot Team"
> Cc: Fabio Estevam
> Cc: Francesco Dolcini
> Cc: Marcel Ziswiler
> Cc: Philippe Schenker
> Cc: Martyn Welch
> Cc: Stefano Babic
> Cc: u-boot@lists.denx.de
> ---
> arch/arm/dts/imx8mm-mx8menlo.dts | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mm-mx8menlo.dts b/arch/arm/dts/imx8mm-
> mx8menlo.dts
> index 0b123a84018..c226285c6ea 100644
> --- a/arch/arm/dts/imx8mm-mx8menlo.dts
> +++ b/arch/arm/dts/imx8mm-mx8menlo.dts
> @@ -290,6 +290,28 @@
> >;
> };
>
> +&pinctrl_gpio_hog1 {
Should these be in xx-u-boot.dtsi?
Regards,
Peng.
> + fsl,pins = <
> + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20
> 0x1c4 /* SODIMM 88 */
> + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1
> 0x1c4 /* CPLD_int */
> + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2
> 0x1c4 /* CPLD_reset */
> + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3
> 0x1c4 /* SODIMM 94 */
> + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4
> 0x1c4 /* SODIMM 96 */
> + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5
> 0x184 /* CPLD_D[7] */
> + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0
> 0x184 /* CPLD_D[6] */
> + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11
> 0x184 /* CPLD_D[5] */
> + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12
> 0x184 /* CPLD_D[4] */
> + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13
> 0x184 /* CPLD_D[3] */
> + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14
> 0x184 /* CPLD_D[2] */
> + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15
> 0x184 /* CPLD_D[1] */
> + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16
> 0x184 /* CPLD_D[0] */
> + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27
> 0x1c4 /* KBD_intK */
> + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22
> 0x1c4 /* DISP_reset */
> + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23
> 0x1c4 /* KBD_intI */
> + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24
> 0x1c4
> + >;
> +};
> +
> ®_usb_otg1_vbus {
> /delete-property/ enable-active-high;
> gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
> --
> 2.43.0
RE: [PATCH] ARM: dts: imx8mm: Update iMX8MM Menlo board configuration
> Subject: [PATCH] ARM: dts: imx8mm: Update iMX8MM Menlo board
> configuration
>
> Synchronize Toradex Verdin iMX8MM based MX8Menlo board configuration
> with Toradex Verdin iMX8MM and enable convenience commands like cat,
> hexdump, xxd.
>
> Signed-off-by: Marek Vasut
Reviewed-by: Peng Fan
> ---
> Cc: "NXP i.MX U-Boot Team"
> Cc: Fabio Estevam
> Cc: Francesco Dolcini
> Cc: Marcel Ziswiler
> Cc: Philippe Schenker
> Cc: Martyn Welch
> Cc: Stefano Babic
> Cc: u-boot@lists.denx.de
> ---
> configs/imx8mm-mx8menlo_defconfig | 28 ++--
> 1 file changed, 26 insertions(+), 2 deletions(-)
>
> diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-
> mx8menlo_defconfig
> index 1ed7f0a2259..2fbd25491f7 100644
> --- a/configs/imx8mm-mx8menlo_defconfig
> +++ b/configs/imx8mm-mx8menlo_defconfig
> @@ -22,15 +22,19 @@ CONFIG_SPL_STACK=0x92 CONFIG_SPL=y
> CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
> CONFIG_ENV_OFFSET_REDUND=0xDE00
> +CONFIG_IMX_BOOTAUX=y
> CONFIG_SYS_LOAD_ADDR=0x4048
> CONFIG_SYS_MEMTEST_START=0x4000
> CONFIG_SYS_MEMTEST_END=0x8000
> CONFIG_FIT=y
> CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> +CONFIG_FIT_VERBOSE=y
> CONFIG_SPL_LOAD_FIT=y
> CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_BOOTDELAY=1
> CONFIG_OF_SYSTEM_SETUP=y
> CONFIG_BOOTCOMMAND="mmc partconf 0 distro_bootpart && load
> ${devtype} ${devnum}:${distro_bootpart} ${loadaddr} boot/fitImage &&
> source ${loadaddr}:bootscr-boot.cmd ; reset"
> +CONFIG_USE_PREBOOT=y
> CONFIG_DEFAULT_FDT_FILE="imx8mm-mx8menlo.dtb"
> CONFIG_SYS_CBSIZE=2048
> CONFIG_SYS_PBSIZE=2081
> @@ -57,19 +61,26 @@ CONFIG_SYS_PROMPT="Verdin iMX8MM # "
> # CONFIG_BOOTM_NETBSD is not set
> CONFIG_CMD_ASKENV=y
> # CONFIG_CMD_EXPORTENV is not set
> -# CONFIG_CMD_CRC32 is not set
> +CONFIG_CRC32_VERIFY=y
> +CONFIG_CMD_MD5SUM=y
> +CONFIG_MD5SUM_VERIFY=y
> CONFIG_CMD_MEMTEST=y
> CONFIG_CMD_CLK=y
> CONFIG_CMD_FUSE=y
> CONFIG_CMD_GPIO=y
> CONFIG_CMD_I2C=y
> CONFIG_CMD_MMC=y
> +CONFIG_CMD_READ=y
> CONFIG_CMD_USB=y
> CONFIG_CMD_USB_SDP=y
> CONFIG_CMD_USB_MASS_STORAGE=y
> +CONFIG_CMD_CAT=y
> +CONFIG_CMD_XXD=y
> CONFIG_CMD_BOOTCOUNT=y
> CONFIG_CMD_CACHE=y
> +CONFIG_CMD_TIME=y
> CONFIG_CMD_UUID=y
> +CONFIG_CMD_PMIC=y
> CONFIG_CMD_REGULATOR=y
> CONFIG_CMD_BTRFS=y
> CONFIG_CMD_EXT4_WRITE=y
> @@ -84,8 +95,9 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> CONFIG_SYS_MMC_ENV_PART=1
> CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
> CONFIG_USE_ETHPRIME=y
> -CONFIG_ETHPRIME="FEC"
> +CONFIG_ETHPRIME="eth0"
> CONFIG_VERSION_VARIABLE=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> CONFIG_IP_DEFRAG=y
> CONFIG_TFTP_BLOCKSIZE=4096
> CONFIG_SPL_DM=y
> @@ -96,16 +108,26 @@ CONFIG_CLK_COMPOSITE_CCF=y
> CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y
> CONFIG_GPIO_HOG=y
> +CONFIG_SPL_GPIO_HOG=y
> CONFIG_MXC_GPIO=y
> CONFIG_DM_I2C=y
> CONFIG_MISC=y
> CONFIG_I2C_EEPROM=y
> CONFIG_SUPPORT_EMMC_BOOT=y
> +CONFIG_MMC_IO_VOLTAGE=y
> +CONFIG_SPL_MMC_IO_VOLTAGE=y
> +CONFIG_MMC_UHS_SUPPORT=y
> +CONFIG_SPL_MMC_UHS_SUPPORT=y
> +CONFIG_MMC_HS400_ES_SUPPORT=y
> +CONFIG_MMC_HS400_SUPPORT=y
> +CONFIG_SPL_MMC_HS400_SUPPORT=y
> CONFIG_FSL_USDHC=y
> CONFIG_PHYLIB=y
> CONFIG_PHY_ADDR_ENABLE=y
> CONFIG_PHY_MICREL=y
> CONFIG_PHY_MICREL_KSZ90X1=y
> +CONFIG_PHY_FIXED=y
> +CONFIG_DM_MDIO=y
> CONFIG_FEC_MXC=y
> CONFIG_MII=y
> CONFIG_SPL_PHY=y
> @@ -128,6 +150,7 @@ CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y
> CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y
> +CONFIG_IMX_TMU=y
> CONFIG_USB=y
> CONFIG_SPL_USB_HOST=y
> CONFIG_USB_EHCI_HCD=y
> @@ -143,3 +166,4 @@ CONFIG_SDP_LOADADDR=0x4040
> CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_SPL_USB_SDP_SUPPORT=y
> CONFIG_IMX_WATCHDOG=y
> +CONFIG_HEXDUMP=y
> --
> 2.43.0
RE: [PATCH 061/149] board: freescale: Remove and add needed includes
> Subject: [PATCH 061/149] board: freescale: Remove and add > needed includes > > Remove from this board vendor directory and when needed > add missing include files directly. > > Signed-off-by: Tom Rini Acked-by: Peng Fan > --- > Cc: Stefano Babic > Cc: Fabio Estevam > Cc: "NXP i.MX U-Boot Team" > Cc: Peng Fan > Cc: Giulio Benetti > Cc: Jesse Taube > Cc: Pramod Kumar > Cc: Alison Wang > Cc: Tang Yuantian > Cc: Mingkai Hu > Cc: Ashish Kumar > Cc: Priyanka Jain > Cc: Wasim Khan > Cc: Meenakshi Aggarwal > Cc: Angelo Dureghello > Cc: TsiChung Liew > Cc: Sinan Akman > Cc: Otavio Salvador > Cc: Jason Liu > Cc: Eric Nelson > Cc: Adrian Alonso > Cc: Qiang Zhao > Cc: Shengzhou Liu > --- > arch/arm/include/asm/arch-imx8m/ddr.h | 2 +- > arch/arm/include/asm/mach-imx/gpio.h | 2 ++ > board/freescale/common/cadmus.c | 3 ++- > board/freescale/common/cds_pci_ft.c | 1 - > board/freescale/common/cds_via.c | 1 - > board/freescale/common/cmd_esbc_validate.c| 2 +- > board/freescale/common/emc2305.c | 1 - > board/freescale/common/fman.c | 1 - > board/freescale/common/fsl_chain_of_trust.c | 2 +- > board/freescale/common/fsl_validate.c | 2 +- > board/freescale/common/i2c_common.c | 2 +- > board/freescale/common/i2c_mux.c | 3 ++- > board/freescale/common/ics307_clk.c | 2 +- > board/freescale/common/ls102xa_stream_id.c| 2 +- > board/freescale/common/mc34vr500.c| 1 - > board/freescale/common/mmc.c | 2 +- > board/freescale/common/ngpixis.c | 1 - > board/freescale/common/ns_access.c| 2 +- > board/freescale/common/p_corenet/law.c| 2 +- > board/freescale/common/p_corenet/tlb.c| 3 ++- > board/freescale/common/pfuze.c| 1 - > board/freescale/common/qixis.c| 2 +- > board/freescale/common/sdhc_boot.c| 1 - > board/freescale/common/sys_eeprom.c | 1 - > board/freescale/common/vid.c | 3 ++- > board/freescale/imx8mm_evk/imx8mm_evk.c | 1 - > board/freescale/imx8mm_evk/spl.c | 1 - > board/freescale/imx8mn_evk/imx8mn_evk.c | 1 - > board/freescale/imx8mn_evk/spl.c | 1 - > board/freescale/imx8mp_evk/spl.c | 1 - > board/freescale/imx8mq_evk/imx8mq_evk.c | 1 - > board/freescale/imx8mq_evk/lpddr4_timing.c| 1 - > board/freescale/imx8mq_evk/lpddr4_timing_b0.c | 1 - > board/freescale/imx8mq_evk/spl.c | 2 +- > board/freescale/imx8qm_mek/imx8qm_mek.c | 1 - > board/freescale/imx8qm_mek/spl.c | 1 - > board/freescale/imx8qxp_mek/imx8qxp_mek.c | 1 - > board/freescale/imx8qxp_mek/spl.c | 1 - > board/freescale/imx8ulp_evk/imx8ulp_evk.c | 1 - > board/freescale/imx8ulp_evk/spl.c | 1 - > board/freescale/imx93_evk/imx93_evk.c | 1 - > board/freescale/imx93_evk/spl.c | 1 - > board/freescale/imxrt1020-evk/imxrt1020-evk.c | 1 - > board/freescale/imxrt1050-evk/imxrt1050-evk.c | 1 - > board/freescale/imxrt1170-evk/imxrt1170-evk.c | 1 - > board/freescale/ls1012afrdm/eth.c | 1 - > board/freescale/ls1012afrdm/ls1012afrdm.c | 2 +- > board/freescale/ls1012aqds/eth.c | 2 +- > board/freescale/ls1012aqds/ls1012aqds.c | 2 +- > board/freescale/ls1012ardb/eth.c | 2 +- > board/freescale/ls1012ardb/ls1012ardb.c | 2 +- > board/freescale/ls1021aiot/ls1021aiot.c | 2 +- > board/freescale/ls1021aqds/ddr.c | 2 +- > board/freescale/ls1028a/ddr.c | 1 - > board/freescale/ls1028a/ls1028a.c | 2 +- > board/freescale/ls1043aqds/ddr.c | 1 - > board/freescale/ls1043aqds/eth.c | 2 +- > board/freescale/ls1043aqds/ls1043aqds.c | 2 +- > board/freescale/ls1043ardb/cpld.c | 2 +- > board/freescale/ls1043ardb/ddr.c | 1 - > board/freescale/ls1043ardb/eth.c | 2 +- > board/freescale/ls1046afrwy/ddr.c | 1 - > board/freescale/ls1046afrwy/eth.c | 2 +- > board/freescale/ls1046afrwy/ls1046afrwy.c | 2 +- > board/freescale/ls1046aqds/ddr.c | 1 - > board/freescale/ls1046aqds/eth.c | 2 +- > board/freescale/ls104
RE: [PATCH 23/33] arm: imx: Remove and add needed includes
> Subject: [PATCH 23/33] arm: imx: Remove and add needed > includes > > Remove from all mach-imx, CPU specific sub-directories and > include/asm/arch-mx* files and when needed add missing include files > directly. > > Signed-off-by: Tom Rini Acked-by: Peng Fan > --- > Cc: Stefano Babic > Cc: Fabio Estevam > Cc: "NXP i.MX U-Boot Team" > --- > arch/arm/cpu/arm1136/mx31/devices.c | 1 - > arch/arm/cpu/arm1136/mx31/generic.c | 1 - > arch/arm/cpu/arm1136/mx31/timer.c | 1 - > arch/arm/cpu/arm926ejs/mxs/clock.c | 1 - > arch/arm/cpu/arm926ejs/mxs/iomux.c | 1 - > arch/arm/cpu/arm926ejs/mxs/mxs.c| 1 - > arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 1 - > arch/arm/cpu/arm926ejs/mxs/spl_lradc_init.c | 1 - > arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 1 - > arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 1 - > arch/arm/cpu/arm926ejs/mxs/start.S | 1 - > arch/arm/cpu/arm926ejs/mxs/timer.c | 1 - > arch/arm/include/asm/arch-mx5/clock.h | 2 ++ > arch/arm/include/asm/arch-mx7/sys_proto.h | 2 ++ > arch/arm/mach-imx/cache.c | 2 +- > arch/arm/mach-imx/cmd_bmode.c | 1 - > arch/arm/mach-imx/cmd_dek.c | 3 ++- > arch/arm/mach-imx/cmd_hdmidet.c | 1 - > arch/arm/mach-imx/cmd_mfgprot.c | 2 +- > arch/arm/mach-imx/cmd_nandbcb.c | 1 - > arch/arm/mach-imx/cpu.c | 1 - > arch/arm/mach-imx/ddrmc-vf610-calibration.c | 1 - > arch/arm/mach-imx/ddrmc-vf610.c | 1 - > arch/arm/mach-imx/ele_ahab.c| 2 +- > arch/arm/mach-imx/hab.c | 1 - > arch/arm/mach-imx/i2c-mxv7.c| 2 +- > arch/arm/mach-imx/image-container.c | 2 +- > arch/arm/mach-imx/imx8/ahab.c | 1 - > arch/arm/mach-imx/imx8/clock.c | 1 - > arch/arm/mach-imx/imx8/cpu.c| 1 - > arch/arm/mach-imx/imx8/fdt.c| 1 - > arch/arm/mach-imx/imx8/iomux.c | 1 - > arch/arm/mach-imx/imx8/misc.c | 1 - > arch/arm/mach-imx/imx8/snvs_security_sc.c | 1 - > arch/arm/mach-imx/imx8m/clock_imx8mm.c | 1 - > arch/arm/mach-imx/imx8m/clock_imx8mq.c | 1 - > arch/arm/mach-imx/imx8m/clock_slice.c | 1 - > arch/arm/mach-imx/imx8m/psci.c | 1 - > arch/arm/mach-imx/imx8m/soc.c | 2 +- > arch/arm/mach-imx/imx8ulp/cgc.c | 1 - > arch/arm/mach-imx/imx8ulp/clock.c | 1 - > arch/arm/mach-imx/imx8ulp/iomux.c | 1 - > arch/arm/mach-imx/imx8ulp/pcc.c | 1 - > arch/arm/mach-imx/imx8ulp/rdc.c | 3 ++- > arch/arm/mach-imx/imx9/clock.c | 1 - > arch/arm/mach-imx/imx9/clock_root.c | 2 +- > arch/arm/mach-imx/imx9/imx_bootaux.c| 3 ++- > arch/arm/mach-imx/imx9/soc.c| 2 +- > arch/arm/mach-imx/imx9/trdc.c | 2 +- > arch/arm/mach-imx/imx_bootaux.c | 5 - > arch/arm/mach-imx/imxrt/soc.c | 1 - > arch/arm/mach-imx/iomux-v3.c| 1 - > arch/arm/mach-imx/mac.c | 1 - > arch/arm/mach-imx/misc.c| 1 - > arch/arm/mach-imx/mmc_env.c | 1 - > arch/arm/mach-imx/mmdc_size.c | 2 +- > arch/arm/mach-imx/mx5/clock.c | 1 - > arch/arm/mach-imx/mx5/mx53_dram.c | 2 +- > arch/arm/mach-imx/mx5/soc.c | 1 - > arch/arm/mach-imx/mx6/clock.c | 2 +- > arch/arm/mach-imx/mx6/ddr.c | 1 - > arch/arm/mach-imx/mx6/litesom.c | 2 +- > arch/arm/mach-imx/mx6/module_fuse.c | 1 - > arch/arm/mach-imx/mx6/mp.c | 1 - > arch/arm/mach-imx/mx6/opos6ul.c | 2 +- > arch/arm/mach-imx/mx6/soc.c | 1 - > arch/arm/mach-imx/mx7/clock.c | 3 ++- > arch/arm/mach-imx/mx7/clock_slice.c | 1 - > arch/arm/mach-imx/mx7/ddr.c | 1 - > arch/arm/mach-imx/mx7/psci-mx7.c| 1 - > arch/arm/mach-imx/mx7/soc.c | 1 - > arch/arm/mach-imx/mx7ulp/clock.c| 2 +- > arch/arm/mach-imx/mx7ulp/iomux.c| 1 - > arch/arm/mach-imx/mx7ulp/pcc.c | 1 - > arch/arm/mach-imx/mx7ulp/scg.c | 2 +- > arch/arm/mach-imx/mx7ulp/soc.c | 2 +- > arch/arm/mach-imx/priblob.c | 1 - > arch/arm/mach-imx/rdc-sema.c| 1 - > arch/arm/mach-imx/speed.c | 2 +- > arch/arm/mach-imx/spl.c | 2 +- > arch/arm/mach-imx/spl_imx_romapi.c | 1 - > arch/arm/mach-imx/sy
RE: [PATCH 32/33] arm: fsl-layerscape: Remove and add needed includes
> Subject: [PATCH 32/33] arm: fsl-layerscape: Remove and add > needed includes > > Remove from all fsl-layerscape related files and when needed > add missing include files directly. > > Signed-off-by: Tom Rini Acked-by: Peng Fan > --- > Cc: Peng Fan > --- > arch/arm/cpu/armv7/ls102xa/clock.c | 2 +- > arch/arm/cpu/armv7/ls102xa/cpu.c | 1 - > arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- > arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 1 - > arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c| 2 +- > arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c| 2 +- > arch/arm/cpu/armv7/ls102xa/soc.c | 2 +- > arch/arm/cpu/armv7/ls102xa/spl.c | 1 - > arch/arm/cpu/armv7/ls102xa/timer.c | 1 - > arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 2 +- > arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 2 +- > arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c | 3 ++- > arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c| 2 +- > arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c| 2 +- > arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/ls1028a_serdes.c | 3 ++- > arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 3 ++- > arch/arm/cpu/armv8/fsl-layerscape/ls1043a_serdes.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 3 ++- > arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 3 ++- > arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 3 ++- > arch/arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 3 ++- > arch/arm/cpu/armv8/fsl-layerscape/lx2160a_serdes.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/mp.c | 2 +- > arch/arm/cpu/armv8/fsl-layerscape/soc.c| 2 +- > arch/arm/cpu/armv8/fsl-layerscape/spl.c| 2 +- > arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 ++ > arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 + > arch/arm/include/asm/arch-ls102xa/fsl_serdes.h | 2 ++ > 35 files changed, 40 insertions(+), 32 deletions(-) > > diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c > b/arch/arm/cpu/armv7/ls102xa/clock.c > index 4e1fe281201f..e885a85ce65c 100644 > --- a/arch/arm/cpu/armv7/ls102xa/clock.c > +++ b/arch/arm/cpu/armv7/ls102xa/clock.c > @@ -3,7 +3,7 @@ > * Copyright 2014 Freescale Semiconductor, Inc. > */ > > -#include > +#include > #include > #include > #include > diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c > b/arch/arm/cpu/armv7/ls102xa/cpu.c > index c455969609f6..74a2dcbc116a 100644 > --- a/arch/arm/cpu/armv7/ls102xa/cpu.c > +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c > @@ -4,7 +4,6 @@ > * Copyright 2021 NXP > */ > > -#include > #include > #include > #include > diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c > b/arch/arm/cpu/armv7/ls102xa/fdt.c > index 1c3d24bcad94..34eea22eb923 100644 > --- a/arch/arm/cpu/armv7/ls102xa/fdt.c > +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c > @@ -3,7 +3,7 @@ > * Copyright 2014 Freescale Semiconductor, Inc. > */ > > -#include > +#include > #include > #include > #include > diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c > b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c > index e31a4fb6c31b..664eae532d5f 100644 > --- a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c > +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c > @@ -3,7 +3,6 @@ > * Copyright 2014 Freescale Semiconductor, Inc. > */ > > -#include > #include > > #include "fsl_epu.h" > diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c > b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c > index f74d819ea1ea..c1eadb34523f 100644 > --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c > +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c > @@ -3,7 +3,7 @@ > * Copyright 2014 Freescale Semiconductor, Inc. > */ > > -#include > +#include > #include > #include > #include > diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c > b/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c > index 8c030be8b36f..3032e266c5d4 100644 > --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_serdes.c > +++ b/arch/arm/cpu/armv7/ls102xa/ls10
[PATCH 2/2] imx: imx93-11x11-evk: convert to OF_UPSTREAM
From: Peng Fan
Convert to OF_UPSTREAM for i.MX93 11x11 EVK.
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile| 1 -
arch/arm/dts/imx93-11x11-evk-u-boot.dtsi | 118 +
arch/arm/dts/imx93-11x11-evk.dts | 322 ---
arch/arm/dts/imx93-u-boot.dtsi | 15 ++
arch/arm/mach-imx/imx9/Kconfig | 1 +
configs/imx93_11x11_evk_defconfig| 2 +-
configs/imx93_11x11_evk_ld_defconfig | 2 +-
7 files changed, 136 insertions(+), 325 deletions(-)
delete mode 100644 arch/arm/dts/imx93-11x11-evk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dad869726dc..5c32daaebfe 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1041,7 +1041,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mq-librem5-r4.dtb
dtb-$(CONFIG_ARCH_IMX9) += \
- imx93-11x11-evk.dtb \
imx93-var-som-symphony.dtb \
imx93-phyboard-segin.dtb
diff --git a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
index a99ba99bfb4..408e601bc90 100644
--- a/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx93-11x11-evk-u-boot.dtsi
@@ -26,6 +26,111 @@
bootph-pre-ram;
};
+&lpi2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <40>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-1 = <&pinctrl_lpi2c2>;
+ status = "okay";
+
+ pmic@25 {
+ compatible = "nxp,pca9451a";
+ reg = <0x25>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <65>;
+ regulator-max-microvolt = <2237500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <2187500>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <3125>;
+ };
+
+ buck4: BUCK4{
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <340>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5: BUCK5{
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <340>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <60>;
+ regulator-max-microvolt = <340>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <160>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+
