he tripled cache level is placed in x12, not x0.
Signed-off-by: Pierre-Clément Tosi
---
arch/arm/cpu/armv8/cache.S | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S
index aabb3dff61..5051597f6f 100644
--- a/arch/arm/cpu/arm
ARM). This has the added benefit (albeit arguably
negligible) of reducing the final code size.
Signed-off-by: Pierre-Clément Tosi
---
arch/arm/cpu/armv8/cache.S | 16 ++--
1 file changed, 6 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8
access.
Note that other env_locations might be concerned by this bug but that
this commit only intends to fix it for when ENV_IS_NOWHERE.
Fixes: 5557eec01cbf ("env: Fix invalid env handling in env_init()")
Signed-off-by: Pierre-Clément Tosi
---
env/env.c | 2 +-
1 file changed, 1 insertio
On Wed, Mar 16, 2022 at 01:23:43PM -0600, Simon Glass wrote:
> Hi Pierre-Clément,
>
> On Wed, 16 Mar 2022 at 09:40, Pierre-Clément Tosi wrote:
> >
> > Some headers included (possibly indirectly) from .dts files might have
> > U-Boot specific content relying on the __
Use the macro introduced by commit ef0f4e834c66 ("build_bug.h: add
wrapper for _Static_assert") by importing .
Signed-off-by: Pierre-Clément Tosi
Cc: Simon Glass
Cc: Steffen Jaeckel
---
lib/crypt/crypt-port.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a
GENMASK_INPUT_CHECK.
Signed-off-by: Pierre-Clément Tosi
Cc: Simon Glass
Cc: Tom Rini
---
include/linux/bitops.h | 27 ++---
include/linux/bits.h | 55 ++
2 files changed, 62 insertions(+), 20 deletions(-)
create mode 100644 include/linux/bits.h
Hi,
On Thu, Mar 31, 2022 at 10:09:48AM +, Andrew Scull wrote:
> Check the length of data written by the device is consistent with the
> size of the buffers to avoid out-of-bounds memory accesses in case
> values aren't consistent.
>
> Signed-off-by: Andrew Scull
> Cc: Sughosh Ganu
> ---
>
Hi Chris,
On Fri, Oct 27, 2023 at 01:23:51PM +1300, Chris Packham wrote:
> As discussed this series reverts the HAFDBS changes that caused an issue
> on AC5/AC5X. I think there are some improvements that can be made to the
> initial memory map for the AC5/AC5X but so far nothing I've found makes
Hi Marc,
On Fri, Oct 27, 2023 at 03:11:15PM +0100, Marc Zyngier wrote:
> Hi Pierre-Clément,
>
> On Fri, 27 Oct 2023 10:49:47 +0100,
> Pierre-Clément Tosi wrote:
> >
> > Hi Chris,
> >
> > On Fri, Oct 27, 2023 at 01:23:51PM +1300, Chris Packham wrote:
&g
Skip missing setup data (which is valid) rather than failing with an
error.
Cc: Bin Meng
Cc: Simon Glass
Reported-by: Andrew Walbran
Signed-off-by: Pierre-Clément Tosi
---
cmd/qfw.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/cmd/qfw.c b/cmd/qfw.c
index
Hi,
On Fri, Dec 02, 2022 at 08:38:37PM +0100, s...@geanix.com wrote:
>
> Quoting Pierre-Clément Tosi :
>
> > Add a check for calloc() failing to allocate the requested memory.
> >
> > Make decode_regions() return an error code.
> >
> > Cc: Bin Meng
&g
Hi,
On Tue, Mar 21, 2023 at 08:57:18AM +0100, Christian Gmeiner wrote:
> Am So., 4. Dez. 2022 um 22:22 Uhr schrieb Pierre-Clément Tosi
> :
> >
> > Hi,
> >
> > On Fri, Dec 02, 2022 at 08:38:37PM +0100, s...@geanix.com wrote:
> > >
> > > Quoting
Hi Fabio,
On Fri, Mar 15, 2024 at 08:56:17AM -0300, Fabio Estevam wrote:
> Hi Marc,
>
> On Sat, Mar 9, 2024 at 11:36 AM Fabio Estevam wrote:
>
> > Does the log below help?
> >
> > https://pastebin.com/raw/1i1VBA0a
> >
> > If not, please send me a debug patch and I will be glad to run it here.
exity")
Signed-off-by: Pierre-Clément Tosi
---
arch/arm/cpu/armv8/cache_v8.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 697334086f..57d06f0575 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/
Hi Fabio,
On Mon, Mar 18, 2024 at 10:31:25AM -0300, Fabio Estevam wrote:
> Please find the new logs here:
>
> https://pastebin.com/raw/qF3GbJry
I notice that the mem_map in these logs have overlapping ranges, which results
in unnecessary work when creating the PTs. For this reason, it would
Hi Marc,
On Tue, Mar 19, 2024 at 09:43:03AM +, Marc Zyngier wrote:
> This seems pretty reasonable, thanks for looking into this. However, I
> can't help but notice that this is done without any BBM, and no TLBI
> either.
>
> Are we guaranteed that the updated page tables are not live at the
Hi Fabio,
On Tue, Mar 19, 2024 at 09:13:12AM -0300, Fabio Estevam wrote:
> Hi Pierre,
>
> On Tue, Mar 19, 2024 at 8:39 AM Pierre-Clément Tosi wrote:
>
> > This means gd->arch.tlb_addr pointing to the live PTs during
> > setup_pgtables().
> >
> > In
17 matches
Mail list logo