Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Reviewed-by: Sean Anderson
Signed-off-by: Pratyush Yadav
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index fe249f77ba..de3c11c8e2 100644
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index
spi_nor_setup_op().
- Add support for Micron mt35xu512aba to run in Octal DTR mode.
Pratyush Yadav (26):
spi: spi-mem: allow specifying whether an op is DTR or not
spi: spi-mem: allow specifying a command's extension
spi: spi-mem: export spi_mem_default_supports_op()
spi: spi-mem: add spi_
On 23/06/21 05:32PM, Jagan Teki wrote:
> On Wed, May 5, 2021 at 3:11 PM Pratyush Yadav wrote:
> >
> > Hi,
> >
> > This series adds support for octal DTR flashes in the SPI NOR framework,
> > and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
op(nor, , SNOR_PROTO_8_8_8_DTR);
> > > +ret = spi_mem_exec_op(nor->spi, );
> > > +if (ret) {
> > > +dev_warn(nor->dev, "Software reset
> > > failed: %d\n", ret);
> > > +
* flash. Looking at a few flashes, most range somewhere
> below 100
> + * microseconds. So, wait for 200ms just to be sure.
> + */
> +udelay(SPI_NOR_SRST_SLEEP_LEN);
> +
> +out:
> +nor->cmd_ext_type = ext;
> +return ret;
> +}
>
>
> Thanks
> Jaime
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
Jagan,
On 26/05/21 10:35PM, Jagan Teki wrote:
> On Mon, May 10, 2021 at 6:50 PM Pratyush Yadav wrote:
> >
> > Jagan,
> >
> > On 05/05/21 03:11PM, Pratyush Yadav wrote:
> > > Hi,
> > >
> > > This series adds support for octal DTR flash
"not present" classes. if (!rst) is much cleaner than if
(PTR_ERR(rst) == -ENODATA).
I think the waters have been muddied because the "normal" reset APIs
require the caller to pass in the reset struct to fill, and the devm and
optional APIs allocate the struct themselves and return it. So the check
for whether a reset is valid changes based on which of the two APIs was
used to get the reset. Linux has been allocating a struct reset_control
and returning the pointer from the get go so they don't have this
problem. I think it is reasonable for U-Boot to update reset_valid() to
check for pointer validity to accomodate both API styles.
So here is my suggestion summarized: return NULL when PTR_ERR() ==
-ENODATA. In all other cases return the pointer as it is. Then in all
reset operations like reset_assert(), etc. check if the pointer passed
in is NULL. If it is, do nothing. If it is an error pointer, return
-EINVAL. Otherwise run the function like normal. reset_valid() should
also be updated check for IS_ERR_OR_NULL().
> >
> > But all of your patches are about a function that returns a pointer,
> > which is a different thing
>
> Sorry about this. I pointed to the wrong function creating more confusion.
> >
> >> I can add reset_valid() and add the conditional checks corresponding to
> >> the changes made for reset (like return -ENODATA instead of 0).
> >
> > I'm a bit lost at this point...will look at what you send.
>
> I hope I've explained the differences between clk and reset above.
> Please see and provide your feedback.
>
> Thanks
> Kishon
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 26/05/21 10:35PM, Jagan Teki wrote:
> On Mon, May 10, 2021 at 6:50 PM Pratyush Yadav wrote:
> >
> > Jagan,
> >
> > On 05/05/21 03:11PM, Pratyush Yadav wrote:
> > > Hi,
> > >
> > > This series adds support for octal DTR flashes in the SPI NO
ll versed enough with these CI/CD
tools to know if this was a good idea or not so I never sent a patch.
Acked-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
rth mentioning that lore.kernel.org is based on
public-inbox [0]. If the kernel folks are not willing to host an archive
for this list, we can look into hosting a public-inbox instance on
denx.de as well.
[0] https://public-inbox.org/
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
X Technology Inc.) */
> + { INFO("XT25F128B", 0x0b4018, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
Looks good to me.
> #endif
> { },
> };
> --
> 2.25.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
>
> By disabling CONFIG_SPI_FLASH_BAR, the tiny SPI NOR framework can be
> used.
>
> Signed-off-by: Stefan Roese
> Cc: Chris Packham
> Cc: Pratyush Yadav
> Cc: Tom Rini
Acked-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
Jagan,
On 05/05/21 03:11PM, Pratyush Yadav wrote:
> Hi,
>
> This series adds support for octal DTR flashes in the SPI NOR framework,
> and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
> flashes.
>
> The Cadence QSPI controller driver is also update
ue
> leak.
>
> Nevertheless this is intended. Add a comment to molify Coverity.
>
> Signed-off-by: Simon Glass
> Reported-by: Coverity (CID: 312951)
Acked-by: Pratyush Yadav
> ---
>
> drivers/core/regmap.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/
; }
> #endif
>
> +char *memdup(const void *src, size_t len)
> +{
> + char *p;
> +
> + p = malloc(len);
> + if (!p)
> + return NULL;
> +
> + memcpy(p, src, len);
> +
> + return p;
> +}
> +
> #ifndef __HAVE_ARCH_STRSTR
> /**
> * strstr - Find the first substring in a %NUL terminated string
[...]
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav
versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig| 8 ++
drivers/mtd/spi/spi-nor-core.c | 187 +
drivers/mtd/spi/spi-nor-ids.c | 3 +
include/linux/mtd/spi-nor.h
used.
Signed-off-by: Takahiro Kuwano
Signed-off-by: Pratyush Yadav
[p.ya...@ti.com: Refactor the function to be compatible with nor->erase,
make 4K opcode customizable, call spi_nor_setup_op() before executing
the op.]
---
drivers/mtd/spi/spi-nor-core.c | 61 ++
KiB sectors till the end.
Let the flash-specific erase functions erase less than the requested
length in case of the 4 or 128 KiB sectors and report the number of
bytes erased back to the calling function.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 16 +++-
1 f
ven if ROM hands it to us in Octal
DTR mode.
To accommodate cases where there is more than one flash on a board, and
only one of them needs a soft reset, failure to reset is not made fatal,
and we still try to read ID if possible.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig
assumes that we don't set any non-volatile bits anywhere,
and the flash doesn't have any non-volatile Octal DTR mode
configuration.
Since spi-nor-tiny doesn't (and likely shouldn't) have
spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does
nothing.
Signed-off-by: Pratyush Yadav
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
include/linux/mtd/spi
o abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-cor
mode read 2 bytes and discard the second. This shows
no side effects with the two flashes I tested: Micron mt35xu512aba and
Cypress s28hs512t.
Update Read FSR to mimic Read SR because they share the same
characteristics.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 60
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33 insertions
dummy cycles for a fast octal DTR read are set to 20. Since
there is no simple way of determining the dummy cycles needed for the
fast read command, flashes that use a different value should update it
in their flash-specific hooks.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c
d "inverse" extensions are supported.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 6ce63994ff..7704a62d62 100644
--- a/dri
-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b171a35eb5..6ce63994ff 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor
phases need to be either DTR or STR.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 178 +
include/linux/mtd/spi-nor.h| 50 ++---
3 files changed, 175 insertions(+), 54 deletions(-)
diff --git
: Rework hwcaps
selection for the spi-mem case, 2019-08-06)
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig| 9 ++
drivers/mtd/spi/spi-nor-core.c | 244 ++---
drivers/spi/spi-mem-nodm.c | 62 +
include/linux/mtd/spi-nor.h| 17 ++-
4
there is no data to write.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 33d8637749..7a58d410b4 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers
uct
spi_nor_fixups in nor->info. This is not possible in U-Boot because the
spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c.
Since spi-nor-tiny shouldn't have those fixup hooks populated, add a
separate function that lets flashes populate their fixup hooks.
Signed-off-by: Pratyush
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
ons to avoid forward declarations.
Inspired by the Linux kernel's setup() hook.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 84 +++
drivers/mtd/spi/spi-nor-tiny.c | 22
include/linux/mtd/spi-nor.h| 192 ++---
3 files changed,
324f78dfb442b82365548b657ec4e6974c677502.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index a6625535a7..db918fc06f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b
-by: Pratyush Yadav
---
configs/x530_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 890c94b5c1..0570dbe9ea 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -62,7 +62,6 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y
spi-mem take care of polling the SR.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 39 -
drivers/spi/cadence_qspi.h | 14 +-
drivers/spi/cadence_qspi_apb.c | 286 ++---
3 files changed, 313 insertions(+), 26 deletions(-)
diff --git
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 4
drivers
. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 26
(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 32
Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Reviewed-by: Sean Anderson
Signed-off-by: Pratyush Yadav
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index fe249f77ba..de3c11c8e2 100644
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index
avoid
tripping up controllers.
- Use op->data.nbytes as a measure of whether the data phase exists or
not. This fixes data buswidth not being updadted for SR and FSR reads
because they keep data buffer as NULL when calling spi_nor_setup_op().
- Add support for Micron mt35xu512aba to run in Oct
to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav
---
drivers/spi/mtk_snfi_spi.c | 3 +--
drivers/spi/spi-mem-nodm.c | 4 ++--
drivers/spi/spi-mem.c | 13 +++--
include/spi-mem.h | 6 +-
4 files ch
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 26/04/21 06:25PM, Jagan Teki wrote:
> On Mon, Apr 26, 2021 at 6:19 PM Pratyush Yadav wrote:
> >
> > On 26/04/21 06:04PM, Jagan Teki wrote:
> > > On Mon, Apr 26, 2021 at 12:30 PM Takahiro Kuwano
> > > wrote:
> > > >
> > > > Hi Jaga
drivers/mtd/spi/spi-nor-ids.o
> > >>1919 0 01919 77f
> > >> spl/drivers/mtd/spi/spi-nor-tiny.o
> > >>
> > >> arm-none-eabi-gcc (GCC) 8.2.0, Optimization level -O2.
> > >
> > > Does this series depend on any other patches or Octal DTR?
> >
> > No. This series is for Quad SPI parts and independent from any other
> > patches.
> > The #1, #2, and #3 patches in this series come from Pratyush's series [0]
> > that adds Octal DTR support. However, those three patches introduce generic
> > hooks and do not contain any specific changes for Octal DTR.
>
> nor->erase seems improper, please have a look at the issue here.
> https://source.denx.de/u-boot/custodians/u-boot-spi/-/jobs/260932
I get a 404 on this link. Can you elaborate on what is wrong with
nor->erase?
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 22/04/21 10:28PM, Dario Binacchi wrote:
> As reported by Coverity Scan for Das U-Boot, the 'less-than-zero'
> comparison of an unsigned value is never true.
>
> Signed-off-by: Dario Binacchi
> Reviewed-by: Pratyush Yadav
>
> ---
>
> Changes in v2:
> - B
On 22/04/21 06:37PM, Dario Binacchi wrote:
> As reported by Coverity Scan for Das U-Boot, the 'less-than-zero
> comparison of an unsigned value is never true.
Unbalanced quote.
>
> Signed-off-by: Dario Binacchi
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 21/04/21 11:39AM, Masami Hiramatsu wrote:
> Hello Pratyush,
>
> 2021年4月19日(月) 17:41 Pratyush Yadav :
> >
> > On 17/04/21 08:38AM, Masami Hiramatsu wrote:
> > > From: Jassi Brar
> > >
> > > Signed-off-by: Jassi Brar
> > > ---
>
| SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES | SECT_4K) },
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 06/04/21 01:32PM, Heinrich Schuchardt wrote:
> On 06.04.21 12:22, Pratyush Yadav wrote:
> > On 06/04/21 04:30PM, Simon Glass wrote:
> >> Update this code to use IS_ENABLED() instead.
> >>
> >> Signed-off-by: Simon Glass
> >> ---
> >>
> &
On 06/04/21 10:48AM, Takahiro Kuwano wrote:
> On 4/2/2021 4:31 AM, Pratyush Yadav wrote:
> > From: Takahiro Kuwano
> >
> > Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
> > bottom, depending on the device configuration, while U-Boot support
gt; - " at address 'sector'\n"
> - SF_TEST_HELP
> + " at address 'sector'"
> +#ifdef CONFIG_CMD_SF_TEST
> + "\nsf test offset len - run a very basic destructive test"
> +#endif
> +#endif /* CONFIG_SYS_LONGHELP */
> + ;
> +
> +U_BOOT_CMD(
> + sf, 5, 1, do_spi_flash,
> + "SPI flash sub-system", long_help
> );
> --
> 2.31.0.208.g409f899ff0-goog
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 05/04/21 09:12AM, Sean Anderson wrote:
>
> On 4/5/21 7:47 AM, Tom Rini wrote:
> > On Mon, Apr 05, 2021 at 01:55:06PM +0530, Pratyush Yadav wrote:
> > > On 02/04/21 06:21PM, Sean Anderson wrote:
> > > >
> > > > On 4/1/21 3:31 PM, Pratyush Yadav wr
On 02/04/21 06:21PM, Sean Anderson wrote:
>
> On 4/1/21 3:31 PM, Pratyush Yadav wrote:
> > Each phase is given a separate 'dtr' field so mixed protocols like
> > 4S-4D-4D can be supported.
> >
> > Signed-off-by: Pratyush Yadav
> > ---
> > drivers/spi
On 02/04/21 06:29PM, Sean Anderson wrote:
> On 4/1/21 3:31 PM, Pratyush Yadav wrote:
> > In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
> > the "command extension". There can be 3 types of extensions in xSPI:
> > repeat, invert, and hex. Whe
On 02/04/21 06:28PM, Sean Anderson wrote:
> On 4/1/21 3:31 PM, Pratyush Yadav wrote:
> > Hi,
> >
> > This series adds support for octal DTR flashes in the SPI NOR framework,
>
> As an overall question, is this the same as "DDR" mode?
Sort of...
DD
On 02/04/21 06:31PM, Sean Anderson wrote:
> On 4/1/21 3:31 PM, Pratyush Yadav wrote:
> > spi_mem_default_supports_op() rejects DTR ops by default to ensure that
> > the controller drivers that haven't been updated with DTR support
> > continue to reject them. It also makes
used.
Signed-off-by: Takahiro Kuwano
Signed-off-by: Pratyush Yadav
[p.ya...@ti.com: Refactor the function to be compatible with nor->erase,
make 4K opcode customizable, call spi_nor_setup_op() before executing
the op.]
---
Unfortunately there is a race between this and Takahiro's series
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
Signed-off-by: Pratyush Yadav
versions of the flash was incorrect.
Fixes for that are included in the fixup hooks.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig| 8 ++
drivers/mtd/spi/spi-nor-core.c | 187 +
drivers/mtd/spi/spi-nor-ids.c | 3 +
include/linux/mtd/spi-nor.h
ven if ROM hands it to us in Octal
DTR mode.
To accommodate cases where there is more than one flash on a board, and
only one of them needs a soft reset, failure to reset is not made fatal,
and we still try to read ID if possible.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig
assumes that we don't set any non-volatile bits anywhere,
and the flash doesn't have any non-volatile Octal DTR mode
configuration.
Since spi-nor-tiny doesn't (and likely shouldn't) have
spi_nor_soft_reset(), add a dummy spi_nor_remove() for it that does
nothing.
Signed-off-by: Pratyush Yadav
KiB sectors till the end.
Let the flash-specific erase functions erase less than the requested
length in case of the 4 or 128 KiB sectors and report the number of
bytes erased back to the calling function.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 16 +++-
1 f
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
include/linux/mtd/spi
o abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-cor
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33 insertions
mode read 2 bytes and discard the second. This shows
no side effects with the two flashes I tested: Micron mt35xu512aba and
Cypress s28hs512t.
Update Read FSR to mimic Read SR because they share the same
characteristics.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 60
dummy cycles for a fast octal DTR read are set to 20. Since
there is no simple way of determining the dummy cycles needed for the
fast read command, flashes that use a different value should update it
in their flash-specific hooks.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c
d "inverse" extensions are supported.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index fd5e345baf..86bf7e3efd 100644
--- a/dri
-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 673089ff5b..fd5e345baf 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor
phases need to be either DTR or STR.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 178 +
include/linux/mtd/spi-nor.h| 50 ++---
3 files changed, 175 insertions(+), 54 deletions(-)
diff --git
there is no data to write.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b2a25b0099..1816319ad0 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers
: Rework hwcaps
selection for the spi-mem case, 2019-08-06)
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/Kconfig| 9 ++
drivers/mtd/spi/spi-nor-core.c | 244 ++---
drivers/spi/spi-mem-nodm.c | 62 +
include/linux/mtd/spi-nor.h| 17 ++-
4
uct
spi_nor_fixups in nor->info. This is not possible in U-Boot because the
spi-nor-ids list is shared between spi-nor-core.c and spi-nor-tiny.c.
Since spi-nor-tiny shouldn't have those fixup hooks populated, add a
separate function that lets flashes populate their fixup hooks.
Signed-off-by: Pratyush
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
ons to avoid forward declarations.
Inspired by the Linux kernel's setup() hook.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 84 +++
drivers/mtd/spi/spi-nor-tiny.c | 22
include/linux/mtd/spi-nor.h| 192 ++---
3 files changed,
324f78dfb442b82365548b657ec4e6974c677502.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index e0efebc355..9b995bc6aa 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b
-by: Pratyush Yadav
---
configs/x530_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 890c94b5c1..0570dbe9ea 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -62,7 +62,6 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y
spi-mem take care of polling the SR.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 39 -
drivers/spi/cadence_qspi.h | 14 +-
drivers/spi/cadence_qspi_apb.c | 286 ++---
3 files changed, 313 insertions(+), 26 deletions(-)
diff --git
Once the start bit is toggled it takes a small amount of time before it
is internally synchronized. This means we can't start writing during
that part. So add a small delay to allow the bit to be synchronized.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 4
drivers
. It needs a read delay of 4 in
octal DTR mode. But since the calibration procedure is run before the
flash is switched in octal DTR mode, it yields a read delay of 2. A
value of 4 works for both octal DTR and legacy modes.
Signed-off-by: Pratyush Yadav
---
drivers/spi/cadence_qspi.c | 26
.
Add spi_mem_dtr_supports_op(). It provides a basic sanity check for DTR
ops and performs the buswidth requirement check. Move the logic for
checking buswidth in spi_mem_default_supports_op() to a separate
function so the logic is not repeated twice.
Signed-off-by: Pratyush Yadav
---
drivers
e data phase exists or
not. This fixes data buswidth not being updadted for SR and FSR reads
because they keep data buffer as NULL when calling spi_nor_setup_op().
- Add support for Micron mt35xu512aba to run in Octal DTR mode.
Pratyush Yadav (27):
spi: spi-mem: allow specifying whether an op i
Controllers can use this function to perform basic sanity checking on
the spi-mem op.
Signed-off-by: Pratyush Yadav
---
include/spi-mem.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 3e5b771045..dc53b517c1 100644
--- a/include/spi-mem.h
to be changed to be
op->cmd.nbytes because that is the actual indicator of opcode size.
Signed-off-by: Pratyush Yadav
---
drivers/spi/mtk_snfi_spi.c | 3 +--
drivers/spi/spi-mem-nodm.c | 4 ++--
drivers/spi/spi-mem.c | 13 +++--
include/spi-mem.h | 6 +-
4 files ch
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index
to ask nicely and get the URL.
>
> Regards,
> Simon
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 17/03/21 12:31PM, Michal Simek wrote:
> From: T Karthik Reddy
>
> Add spi memory operations to relocate manually when
> CONFIG_NEEDS_MANUAL_RELOC is enabled.
>
> Signed-off-by: T Karthik Reddy
> Acked-by: Ashok Reddy Soma
> Signed-off-by: Michal Simek
Rev
has native support for memory-like
operations". So you should do a NULL check before accessing it.
> reloc_done++;
> }
> #endif
> --
> 2.30.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
union / writing data from this union.
>
> Signed-off-by: Marek Behún
> Cc: Simon Glass
> Cc: Heiko Schocher
> Cc: Bin Meng
> Cc: Pratyush Yadav
> ---
> drivers/core/regmap.c | 59 +--
> 1 file changed, 57 insertions(
On 16/03/21 03:15PM, Marek Behun wrote:
> On Tue, 16 Mar 2021 19:28:46 +0530
> Pratyush Yadav wrote:
>
> > On 16/03/21 01:25PM, Marek Behún wrote:
> > > There is a serious bug in regmap_read() and regmap_write() functions
> > > where an uint pointer is cast to (
546,6 +555,8 @@ int regmap_raw_write(struct regmap *map, uint offset,
> const void *val,
>
> int regmap_write(struct regmap *map, uint offset, uint val)
> {
> + val = cpu_to_le32(val);
> +
> return regmap_raw_write(map, offset, , map->width);
> }
>
> --
> 2.26.2
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
t; with previous patch.
>
> Fixes: 12bfb2e05fc2 ("dm: spi: prevent setting a speed of 0 Hz")
> Signed-off-by: Michal Simek
Reviewed-by: Pratyush Yadav
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
O("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K) },
> { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
> { INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ |
> SPI_NOR_QUAD_READ) },
> --
> 2.20.1
>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
;
> /* Read back and check it. */
> ret = spansion_read_any_reg(nor, addr, 0, _cr[1]);
>
> [...]
> }
>
> return 0;
> }
>
> /* Check current Quad Enable bit value. */
> ret = read_cr(nor);
> if (ret < 0) {
> dev_dbg(nor->dev,
> "error while reading configuration register\n");
> return -EINVAL;
> }
>
> [...]
> }
>
> Or defining a new flag like 'SNOR_F_HAS_VOLATILE_QE'?
FWIW I think your current implementation is better than both these
alternatives.
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
On 08/03/21 05:47PM, Takahiro Kuwano wrote:
> On 2/24/2021 9:40 PM, Pratyush Yadav wrote:
> > On 19/02/21 10:56AM, tkuw584...@gmail.com wrote:
> >> From: Takahiro Kuwano
> >>
> >> This patch adds Flash specific fixups and hooks for Cypress
> >>
60789?attachment-id=19522
> https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503
>
> Tested on Xilinx Zynq-7000 FPGA board.
I think this series is in very good shape apart from a few minor issues.
Thanks f
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