, OMAP4460 Panda boards
and verified MAKEALL for all armv7 boards.
Lokesh Vutla (4):
ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
ARM: OMAP4+: Cleanup emif specific files
ARM: OMAP4+: Make control module register structure generic
ARM: OMAP5: Clean up iosettings code
R Sricharan
From: Lokesh Vutla lokeshvu...@ti.com
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards
Signed-off-by: R Sricharan r.sricha
From: Lokesh Vutla lokeshvu...@ti.com
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.
These change reduces code addition for future Socs.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off
From: Lokesh Vutla lokeshvu...@ti.com
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.
This avoids unnessecary code addition for future socs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
the omap4+ boards.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |5 +-
arch/arm/cpu/armv7/omap4/hw_data.c |4 +
arch/arm/cpu/armv7/omap4/hwinit.c | 36 -
arch/arm
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c | 79 +--
arch/arm/cpu/armv7/omap4/Makefile |1 -
arch/arm
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++--
arch/arm/include/asm/arch-omap5/omap.h |2 ++
arch/arm/include/asm/armv7.h |1 +
arch/arm/include
Change OPP settings as per the latest 0.4 version of
addendum for OMAP5430 ES2.0
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |4 +
arch/arm/cpu/armv7/omap4/hw_data.c | 140
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.
So adding the nessecary register changes for the same.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |4 +
arch/arm/cpu/armv7/omap5
From: Lokesh Vutla lokeshvu...@ti.com
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.
Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan
is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |6 ++
arch/arm/cpu/armv7/omap5/hwinit.c | 116
/152563
Lokesh Vutla (2):
ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
R Sricharan (3):
ARM: OMAP5: Add silicon id support for ES2.0 revision.
ARM: OMAP5: clock: Add the prcm register changes required
On Thursday 31 January 2013 09:59 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 01/31/2013 12:51 AM, R Sricharan wrote:
From: Lokesh Vutla lokeshvu...@ti.com
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM
On Thursday 31 January 2013 10:10 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 01/31/2013 12:52 AM, R Sricharan wrote:
The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new
silicon revision
Hi Tom,
On Thursday 31 January 2013 10:31 PM, Tom Rini wrote:
On Thu, Jan 31, 2013 at 11:22:02AM +0530, R Sricharan wrote:
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan r.sricha...@ti.com
[snip
Hi Tom,
On Thursday 31 January 2013 10:50 PM, Tom Rini wrote:
On Thu, Jan 31, 2013 at 11:32:30AM +0530, R Sricharan wrote:
From: Lokesh Vutla lokeshvu...@ti.com
After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP
Hi,
On Sunday 03 February 2013 07:47 PM, Albert ARIBAUD wrote:
Hi R Sicharan, Vincent,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricha...@ti.com
wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with
manager permissions for all 4GB address space. Because
Hi,
On Sunday 03 February 2013 07:49 PM, R Sricharan wrote:
Hi,
On Sunday 03 February 2013 07:47 PM, Albert ARIBAUD wrote:
Hi R Sicharan, Vincent,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricha...@ti.com
wrote: i meant
Currently for ARM based cpu's, mmu pagetable attributes are set
On Sunday 03 February 2013 08:55 PM, Albert ARIBAUD wrote:
Hi R,
On Sun, 3 Feb 2013 19:52:04 +0530, R Sricharan r.sricha...@ti.com
wrote:
Hi,
On Sunday 03 February 2013 07:49 PM, R Sricharan wrote:
Hi,
On Sunday 03 February 2013 07:47 PM, Albert ARIBAUD wrote:
Hi R Sicharan, Vincent
From: Lokesh Vutla lokeshvu...@ti.com
Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.
These change reduces code addition for future Socs.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off
, OMAP4460 Panda boards
and verified MAKEALL for all armv7 boards.
Lokesh Vutla (4):
ARM: OMAP4+: emif: Detect SDRAM from SDRAM config register
ARM: OMAP4+: Cleanup emif specific files
ARM: OMAP4+: Make control module register structure generic
ARM: OMAP5: Clean up iosettings code
R Sricharan
From: Lokesh Vutla lokeshvu...@ti.com
There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.
This avoids unnessecary code addition for future socs.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
From: Lokesh Vutla lokeshvu...@ti.com
Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards
Signed-off-by: R Sricharan r.sricha
The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
[V2] Addressed Tom Rini's tr...@ti.com comments
arch/arm/cpu/armv7/omap-common/clocks
the omap4+ boards.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |5 +-
arch/arm/cpu/armv7/omap4/hw_data.c |3 +
arch/arm/cpu/armv7/omap4/hwinit.c | 36 -
arch/arm
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++--
arch/arm/include/asm/arch-omap5/omap.h |2 ++
arch/arm/include/asm/armv7.h |1 +
arch/arm/include
/152834
Lokesh Vutla (2):
ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
R Sricharan (3):
ARM: OMAP5: Add silicon id support for ES2.0 revision.
ARM: OMAP5: clock: Add the prcm register changes required
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.
So adding the nessecary register changes for the same.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hw_data.c |5 +
arch/arm/cpu/armv7/omap5
is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c |6 ++
arch/arm/cpu/armv7/omap5/hwinit.c | 116
From: Lokesh Vutla lokeshvu...@ti.com
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.
Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla
Change OPP settings as per the latest 0.4 version of
addendum for OMAP5430 ES2.0
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/clocks-common.c |4 +
arch/arm/cpu/armv7/omap4/hw_data.c | 142
Hi Nishanth,
On Tuesday 05 February 2013 01:46 AM, Nishanth Menon wrote:
On 19:59-20130204, R Sricharan wrote:
Change OPP settings as per the latest 0.4 version of
addendum for OMAP5430 ES2.0
--please be clear that these are for OPP_NOM. FYI, latest documentation
is 0.5 rev which
On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:
On 19:59-20130204, R Sricharan wrote:
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++--
arch/arm
Hi,
On Tuesday 05 February 2013 08:49 PM, Nishanth Menon wrote:
On 18:02-20130205, R Sricharan wrote:
On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:
On 19:59-20130204, R Sricharan wrote:
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R
On Tuesday 05 February 2013 08:59 PM, Nishanth Menon wrote:
[..]
Answering all of your above questions here.
The above data is for OMAP4 and not OMAP5. This file was modified
here just to include dummy dividers. Because we were now using a
common dpll_params structure, there
/152834
Both the cleanup and ES2.0 support series against mainline is available
here
git://gitorious.org/u-boot-shared/u-boot.git omap5_es2
Lokesh Vutla (2):
ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs
ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup
R
Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: R Sricharan r.sricha...@ti.com
Cc: Tom Rini tr...@ti.com
Cc: Nishanth Menon n...@ti.com
---
[v2] Addressed Tom Rini's tr...@ti.com comments
[v3] Changed the patch to use CONTROL_ID_CODE first
and then arm
PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.
So adding the nessecary register changes for the same.
Signed-off-by: R Sricharan r.sricha...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
Cc: Tom Rini tr...@ti.com
---
[v2
From: Lokesh Vutla lokeshvu...@ti.com
Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.
Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla
is not enabled because smart i/os
of wkup domain work with default compensation code.
Signed-off-by: R Sricharan r.sricha...@ti.com
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Reviewed-by: Tom Rini tr...@ti.com
Cc: Tom Rini tr...@ti.com
---
[v2] Addressed Tom Rini's tr...@ti.com comments
[v3
later.
Signed-off-by: Lokesh Vutla lokeshvu...@ti.com
Signed-off-by: R Sricharan r.sricha...@ti.com
Cc: Tom Rini tr...@ti.com
Cc: Nishanth Menon n...@ti.com
---
[v2] Addressed Tom Rini's tr...@ti.com comments
[v3] Addressed some of Nishanth's comments here.
Essentially added missing OPP_HIGH
/omap5_evm.h
@@ -55,6 +55,7 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_BOOTZ
Reviewed-by: R Sricharan r.sricha...@ti.com
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/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -52,7 +52,7 @@
#define CONFIG_MISC_INIT_R
#define CONFIG_OF_LIBFDT 1
-
+#define CONFIG_CMD_BOOTZ
Reviewed-by: R Sricharan r.sricha...@ti.com
Regards,
Sricharan
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Hi Tom,
On Tuesday 19 February 2013 09:44 PM, Tom Rini wrote:
Hello,
The following changes since commit 9f024f62e4604274a23213dcee30016092e32e7b:
Merge branch 'fixes' of git://git.denx.de/u-boot-mips (2013-02-15 12:23:42
-0500)
are available in the git repository at:
On Thursday 21 February 2013 11:27 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 02/21/2013 12:52 PM, R Sricharan wrote:
Hi Tom,
On Tuesday 19 February 2013 09:44 PM, Tom Rini wrote:
Hello,
The following changes since commit
9f024f62e4604274a23213dcee30016092e32e7b
Hi Tom/Albert,
From: Rini, Tom
Sent: Friday, March 01, 2013 7:51 PM
To: Albert ARIBAUD
Cc: R, Sricharan; U-Boot; Stehle, Vincent
Subject: Re: [U-Boot] [PATCH 0/2] ARM: mmu: Set domain permissions to client
access - build warnings!
-BEGIN PGP SIGNED
by GENERATED_GBL_DATA_SIZE, though it is small.
SRAM size available for SPL code is a concern in OMAP4 platforms.
Do you prefer keeping CONFIG_SPL_STACK to NON_SECURE_SRAM_END ?.
Except for that
Acked-by: R Sricharan r.sricha...@ti.com
Thanks,
Sricharan
Hi,
-- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -138,6 +138,7 @@ struct watchdog {
#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x7)
#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
#define I2C_BASE3
Hi Roger,
If board config does not select CONFIG_USB_EHCI_OMAP (e.g.
omap4_sdp4430_config)
then the USB DPLL is stuck in running state and it prevents the system from
entering OFF mode (i.e. l3init domain is kept ON).
With this patch we unconditionally configure the USB DPLL so it
Hi Roger,
If board config does not select CONFIG_USB_EHCI_OMAP (e.g.
omap4_sdp4430_config)
then the USB DPLL is stuck in running state and it prevents the system from
entering OFF mode (i.e. l3init domain is kept ON).
With this patch we unconditionally configure the USB DPLL so it
Hi Aneesh,
On Thu, Jun 21, 2012 at 2:55 PM, Sricharan R r.sricha...@ti.com wrote:
Hi,
[snip..]
On 06/15/2012 07:48 AM, R, Sricharan wrote:
Hi,
On Fri, Jun 15, 2012 at 12:31 AM, Tom Rinitr...@ti.com wrote:
If we are built with D-CACHE enabled but have run 'dcache off
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
While, this looks like to be the safest option till
we fix both the cache issue and alignment issue in USB stack.
Acked-by: R Sricharan r.sricha...@ti.com
Thanks,
Sricharan
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Aneesh,
[snip..]
If we are built with D-CACHE enabled but have run 'dcache off' and
then
attempt to flush unaligned regions we spam the console with
problems
that aren't true (as the cache was off).
Today we do cache maintenance operations after the dcache is
turned off.
One
file for PANDA was missed out. Adding it here
to ensure TFTP works fine on OMAP4 panda boards.
Tested this on OMAP4430 ES2.2, OMAP4460 ES1.1 PANDA boards.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
board/ti/panda/panda_mux_data.h | 44 +++
1 file
Hi Tom,
[snip..]
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 7f05cb5..c697e0b 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -39,11 +39,6 @@
#define OMAP54XX_L4_WKUP_BASE
Hi Tom,
On Tue, Jul 31, 2012 at 8:43 PM, Tom Rini tr...@ti.com wrote:
On 07/31/2012 01:33 AM, R, Sricharan wrote:
Hi Tom,
[snip..]
diff --git a/arch/arm/include/asm/arch-omap5/omap.h
b/arch/arm/include/asm/arch-omap5/omap.h
index 7f05cb5..c697e0b 100644
--- a/arch/arm/include/asm/arch
Correct.
DRAM_ADDR_SPACE_END should be 0x for OMAP5.
Thanks,
Sricharan
On Tue, Jul 31, 2012 at 9:12 PM, Tom Rini tr...@ti.com wrote:
On 07/31/2012 08:27 AM, R, Sricharan wrote:
Hi Tom,
On Tue, Jul 31, 2012 at 8:43 PM, Tom Rini tr...@ti.com wrote:
On 07/31/2012 01:33 AM, R
Hi,
On Tue, Aug 7, 2012 at 2:59 PM, Jassi Brar jaswinder.si...@linaro.org wrote:
The commit
f3f98bb0 : ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls
removed the config option aimed towards moving that stuff into kernel, which
renders some code unreachable. Remove that
Hi Vincent,
On Monday 07 January 2013 08:14 PM, Vincent Stehlé wrote:
We introduce an OMAP5 specific version of arm_setup_identity_mapping(), which
makes the first page of the identity mapping invalid.
We want to unmap the region near address zero on HS OMAP devices, to avoid
speculative
Introduce a weak version of dram_bank_setup function
to allow a platform specific redefinition.
This is used in the subsequent patch to setup dram region
without 'XN' attribute in order to enable the region
under client permissions.
Signed-off-by: R Sricharan r.sricha...@ti.com
Cc: Vincent
of speculative prefetch aborts seen with CORTEX A15
otherwise.
Signed-off-by: R Sricharan r.sricha...@ti.com
Cc: Vincent Stehle v-ste...@ti.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/cache_v7.c |3 ++
arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35
Hi Stefan,
On Tuesday 08 January 2013 05:22 PM, Stefan Roese wrote:
On 01/08/2013 12:18 PM, R Sricharan wrote:
Introduce a weak version of dram_bank_setup function
to allow a platform specific redefinition.
This is used in the subsequent patch to setup dram region
without 'XN' attribute
Hi Vincent,
On Tuesday 08 January 2013 05:57 PM, Vincent Stehlé wrote:
On 01/08/2013 12:14 PM, R Sricharan wrote:
(..)
We had this problem of speculative aborts in the kernel uncompress code
as well, which maps all of 4GB address space. It was solved by setting
the non-DRAM region as non
/msg102709.html
R Sricharan (2):
ARM: mmu: Introduce weak dram_bank_setup function
ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c |3 ++
arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35
arch/arm/include/asm
of speculative prefetch aborts seen on OMAP5
secure devices.
Signed-off-by: R Sricharan r.sricha...@ti.com
Tested-by: Vincent Stehle v-ste...@ti.com
Cc: Vincent Stehle v-ste...@ti.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/cpu/armv7/cache_v7.c |3 ++
arch/arm/cpu/armv7/omap
Introduce a weak version of dram_bank_setup function
to allow a platform specific function.
This is used in the subsequent patch to setup dram region
without 'XN' attribute in order to enable the region
under client permissions.
Signed-off-by: R Sricharan r.sricha...@ti.com
Cc: Vincent Stehle v
Introduce a weak version of dram_bank_setup function
to allow a platform specific function.
This is used in the subsequent patch to setup dram region
without 'XN' attribute in order to enable the region
under client permissions.
Signed-off-by: R Sricharan r.sricha...@ti.com
Cc: Vincent Stehle v
Hi,
On Saturday 01 December 2012 04:31 AM, Simon Glass wrote:
From: Arun Mankuzhi aru...@samsung.com
In Cortex-A15 architecture, when we run cache invalidate
the cache clean operation executes automatically.
So if there are any dirty cache lines before disabling the L2 cache
these will be
Jon,
[snip]
--- a/include/configs/omap4_common.h
+++ b/include/configs/omap4_common.h
@@ -151,6 +151,7 @@
#define CONFIG_EXTRA_ENV_SETTINGS \
loadaddr=0x8200\0 \
console=ttyO2,115200n8\0 \
+ fdt_high=0x\0 \
Tested this on mainline and worked fine on
,
prcm-cm_l3instr_l3_3_clkctrl,
prcm-cm_l3instr_l3_instr_clkctrl,
Looks fine.
Acked-by: R Sricharan r.sricha...@ti.com
Thanks,
Sricharan
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Hi Tero,
On Wed, Apr 25, 2012 at 9:35 PM, Tero Kristo t-kri...@ti.com wrote:
If uart2 is enabled during boot, spurious wifi chip transmission will
hang the module and it is impossible to recover from this situation
without hard reset. This will prevent any l4_per domain idle
transitions.
Hi Tero,
[snip]
@@ -378,7 +378,6 @@ void enable_basic_clocks(void)
prcm-cm_l4per_gptimer2_clkctrl,
prcm-cm_wkup_wdtimer2_clkctrl,
prcm-cm_l4per_uart3_clkctrl,
- prcm-cm_l3init_fsusb_clkctrl,
Hi Tero,
Sorry my mailer thrashed my earlier email.
resending it again.
On Wed, Apr 25, 2012 at 9:35 PM, Tero Kristo t-kri...@ti.com wrote:
If this is done in the bootloader, the FS-USB will later be stuck into
intransition state, which will prevent the device from entering idle.
Tero,
[snip]
- {UART2_CTS, (PTU | IEN | M0)}, /*
uart2_cts */
- {UART2_RTS, (M0)}, /*
uart2_rts */
- {UART2_RX, (PTU | IEN | M0)}, /*
uart2_rx */
-
Signed-off-by: R Sricharan r.sricha...@ti.com
CC: Aneesh V ane...@ti.com
CC: Tom Rini tr...@ti.com
---
MAINTAINERS | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index e2441d8..71e6bb5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
Hi Tom,
[snip]
Option 1 (SPL only):
0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
You wanted to change the above comment to
0x40200800 - 0x4020DFFC as well ?
-0x4020BC00 - 0x4020FFFC: Area for the SPL stack.
+0x4020E000 - 0x4020FFFC: Area for the SPL stack.
Hi Peter,
board/ti/sdp4430/sdp4430_mux_data.h | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/ti/sdp4430/sdp4430_mux_data.h
b/board/ti/sdp4430/sdp4430_mux_data.h
index 0a20968..beb7c7a 100644
--- a/board/ti/sdp4430/sdp4430_mux_data.h
+++
flushes the dirty
line as well. So some times the dirty line from sequence 1
can corrupt the memory resulting in a crash.
Fixing this by moving the get_cr() and cp_delay() calls before
cleaning up the cache, thus avoiding the dirty entry.
Signed-off-by: R Sricharan r.sricha...@ti.com
This series has been tested on
OMAP4430 sdp
OMAP4 panda
OMAP5 evm
MAKEALL has been tested for all armv7 boards to ensure
no build breakage.
R Sricharan (4):
ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections.
ARM: OMAP5: dmm: Create a tiler trap section.
ARM: OMAP5: Align
of the above scenarios while calculating the
size of the actual ram.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/hwinit-common.c | 20 ++--
1 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
b
OMAP5 evm board has 2GB of memory. So correct the
macro to take in to account of the full dram size.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/include/asm/arch-omap5/omap.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5
to the power of 2.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index db509c9..389feda
reported to MPU.
Note that here the tiler trap section is overlapping
with the actual ddr physical space and we lose 16MB
out of the total 2GB.
Signed-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap5/sdram.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff
Hi peter,
@@ -216,7 +216,7 @@ const struct pad_conf_entry
core_padconf_array_non_essential[] = {
{FREF_CLK1_OUT, (M0)}, /*
fref_clk1_out */
{FREF_CLK2_OUT, (M0)}, /*
fref_clk2_out */
Hi Lokesh,
@@ -56,7 +56,7 @@
#define CONTROL_ID_CODE (CTRL_BASE + 0x204)
/* To be verified */
-#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F
+#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B94202F
ok, then the above comment /* To be verified */
can be removed as well
Hi Lokesh,
Adding precalculated timings for ddr3 with 1cs
adding required registers for ddr3
You want to mention the part name as well ?
nit in subject : and defining the additional registers required
for DDR3.
[snip..]
/* Dummy registers for OMAP44xx */
const
Hi Lokesh,
No need to Unlock DPLL initially.
DDR3 can work at normal OPP from initialozation
Why is it so ?
The commit log should make it clear why is it
nessecary to do the initialisations at higher frequency and
that becomes the reason for this patch.
Thanks,
Sricharan
Hi Tom,
In OMAP5432 EMIF controlller supports DDR3 device.
This patch adds support for ddr3 device intialization and configuration.
Initialization sequence is done as specified in JEDEC specs.
This also adds support for ddr3 leveling.
[snip]
@@ -975,8 +1070,12 @@ static void
- ? ? if (!in_sdram)
- ? ? ? ? ? ? lpddr2_init(base, regs);
+ ? ? if (!in_sdram) {
+ ? ? ? ? ? ? if (omap_revision() != OMAP5432_ES1_0)
+ ? ? ? ? ? ? ? ? ? ? lpddr2_init(base, regs);
+ ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? ddr3_init(base, regs);
+ ? ? }
In omap4+ land do we
Hi Tom,
ah, this is what is there on OMAP5.
3 for DDR3
4 for LPDDR2-S4,
5 for LPDDR2-S2
4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2
in same way.
Is the reset value set correctly on
Hi Tom,
ah, this is what is there on OMAP5.
3 for DDR3
4 for LPDDR2-S4,
5 for LPDDR2-S2
4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2
in same way.
Is the reset value set correctly on
To meet certain timing requirements on the lpddr2 cmd and data phy
interfaces ,lpddr iopads have to be configured as differential buffers
and a Vref has to be internally generated and provided to these buffers.
Correcting the above settings here.
Signed-off-by: R Sricharan r.sricha...@ti.com
R Sricharan (4):
ARM: OMAP4+: dmm: Take care of overlapping dmm and trap sections.
ARM: OMAP5: dmm: Create a tiler trap section.
ARM: OMAP5: Align memory used for testing to the power of 2
ARM: OMAP5: Correct the DRAM_ADDR_SPACE_END macro.
arch/arm/cpu/armv7/omap-common/emif
Hi Albert,
Are you planning to take up the below patch ?
Thanks,
Sricharan
On Thu, May 17, 2012 at 3:22 PM, R Sricharan r.sricha...@ti.com wrote:
The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c
int cleanup_before_linux(void)
{
...
...
dcache_disable
Hi,
arch/arm/cpu/armv7/omap-common/emif-common.c |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c
b/arch/arm/cpu/armv7/omap-common/emif-common.c
index db509c9..176520c 100644
---
Code currently tests for = 0xff. Micron manufacturer code is 0xff, so
Micron memory will not be detected!
Signed-off-by: Steve Sakoman st...@sakoman.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
-off-by: R Sricharan r.sricha...@ti.com
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 32 +-
arch/arm/cpu/armv7/omap4/sdram_elpida.c |3 --
arch/arm/cpu/armv7/omap5/sdram.c | 31 +
arch/arm/include/asm/emif.h
Hi Steve,
[snip]
---
arch/arm/cpu/armv7/omap4/sdram_elpida.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index b538960..0599aaa 100644
---
Hi Marek Vasut,
Ping..
+1
Thanks..
Thanks,
Sricharan
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.
There are a lot of warnings during boot because some dplls are no
more locked by default. This could also break other drivers which
were dependent upon the bootloaders for their configurations.
R Sricharan (4):
ARM: OMAP4/5: Move gpmc clocks to essential group.
ARM: OMAP4/5: Move USB clocks
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