the exception
for spl/Makefile otherwise it has no effect.
Signed-off-by: Ralph Siemsen ral...@netwinder.org
---
Note: feel free to adjust the commit message to remove the
gratuitous ascii art emphasis, etc.
Note2: kindly CC: me on any replies
---
.gitignore | 2 +-
1 file changed, 1 insertion(+), 1
Small correction:
> Notes:
> The array of pointers allocated in dfu_prepare_function() is larger
> than necessary. For some reason it is N+2 when N+1 would suffice.
> Not a memory leak, so did not address in this commit.
Please ignore that note... the N+2 element is indeed needed, it
incrementing counter, as in dfu_prepare_function().
Signed-off-by: Ralph Siemsen
---
Notes:
The array of pointers allocated in dfu_prepare_function() is larger
than necessary. For some reason it is N+2 when N+1 would suffice.
Not a memory leak, so did not address in this commit.
drivers/usb/gadget/f
Make it a little easier to find the documentation.
Signed-off-by: Ralph Siemsen
---
doc/driver-model/spi-howto.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst
index a538fdcb93..5540eb7d38 100644
--- a/doc
Signed-off-by: Ralph Siemsen
---
This compatible string also appears in: axs10x_mb.dtsi and hsdk.dts.
Maintainers of those boards have been copied, kindly review.
drivers/net/designware.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index
In combination with multiple partitions in NAND, this printf() ends up
being more noise than helpful. Change it to debug() instead.
Signed-off-by: Ralph Siemsen
---
drivers/dfu/dfu_nand.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu
incrementing counter, as in dfu_prepare_function().
Signed-off-by: Ralph Siemsen
---
Changes in v2:
Remove incorrect note.
Fix spelling error in commit message.
drivers/usb/gadget/f_dfu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/f_dfu.c b/drivers/usb/gadget/f_dfu.c
index 30ece524a
On Wed, Oct 02, 2019 at 02:37:20PM +0200, Marek Szyprowski wrote:
malloc_cache_aligned() might return zero, so fix potential NULL pointer
access if __GFP_ZERO flag is set.
Signed-off-by: Marek Szyprowski
Reviewed-by: Ralph Siemsen
This looks reasonable to me. The memset() will happily
Hi Stefan,
On Wed, Sep 09, 2020 at 10:49:29AM +0200, Stefan Roese wrote:
Hi Ralph,
Thanks for finding and fixing this:
I've sent a v2 with the suggested changes.
Have also noticed that mtest takes considerably longer when doing the
bitflip test. To the point where using it for
dress. Thus it fails to test
the last word of the requested range. Fixed by using (end - start + 1).
Fixes: 8e434cb705d463bc8cff935160e4fb4c77cb99ab ("cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v2:
- Minor refactor to reduce line l
Hi Stefan,
On Wed, Sep 09, 2020 at 03:34:35PM +0200, Stefan Roese wrote:
I agree that it's too time consuming (usually) for a manufacturing test.
Either you are okay with disabling CONFIG_SYS_ALT_MEMTEST on your board,
which will also disable this bitflip test. Or please continue adding a
new
t;cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v3:
- Add Kconfig option to disable bitflip test
- Refactor the fix into a helper function
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/Kconfig | 12
cmd/mem.c | 24 +
t;cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v4:
- Avoid #ifdef in the code
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/Kconfig | 12
cmd/mem.c | 18 ++
2 files changed, 26 insertions(+), 4 dele
t;cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen
--
Changes in v5:
- Correct logic for updating error count
Changes in v4:
- Avoid #ifdef in the code
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/Kconfig | 12
cmd/mem.c | 21 ++
Hi Stefan,
On Wed, Sep 09, 2020 at 03:53:08PM +0200, Stefan Roese wrote:
Hi Ralph,
On 09.09.20 15:49, Ralph Siemsen wrote:
Very good, I will send a separate patch that adds a Kconfig option.
As it turns out, doing a separate patch for this gets messy, and also
would introduce a dependency
Hi Stefan,
On Wed, Sep 09, 2020 at 05:13:49PM +0200, Stefan Roese wrote:
Usually the RB is only added, when not too many further changes are
made by the committer. There is no strict rule here AFAIK.
In that case I'll omit your RB on v3 as the change is somewhat larger,
and includes the
Hi Jasper,
On Wed, Sep 09, 2020 at 07:03:58PM +0200, Jasper van Santen wrote:
I am sorry to ask such a basic question, but i really can't find any
documentation on the commands possible in scripting.
Documentation of Hush and its commands i can't find.
The hush shell gives you the ability to
st to alternate mtest")
Signed-off-by: Ralph Siemsen
--
TODO/FIXME: maybe the ending address should be automatically aligned?
Change-Id: Ie641d04e731fc5bc6a3bbef914bf7fad136cdc94
---
cmd/mem.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/cmd/mem.c b/cmd/me
Hi Jasper,
On Thu, Sep 10, 2020 at 11:19:29AM +0200, Jasper van Santen wrote:
I had already seen the movie, the book would have been better ;)
I feel that way too... ;)
Fortunately I build U-Boot with buildroot, so i have the source code.
It is a big meager, but I ended up grepping the man
Hi,
The "sf probe" command is documented to take optional speed/mode args:
sf probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus
and chip select
This worked correctly in older u-boot versions, but as of 2019.07 the
speed/mode arguments appear to
On Tue, Sep 29, 2020 at 02:52:05PM -0400, Ralph Siemsen wrote:
Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert
system manager from struct to defines")
Just curious if you have had a chance to look over this patch?
http://patchwork.ozlabs.org/project/u
Hi Wolfgang et al.,
On Fri, Aug 07, 2020 at 05:49:13PM +0200, Wolfgang Grandegger wrote:
Am 07.08.20 um 17:05 schrieb Dinh Nguyen:
On 8/6/20 7:36 AM, Wolfgang Grandegger wrote:
Am 06.08.20 um 13:04 schrieb Marek Vasut:
On 8/6/20 12:53 PM, Wolfgang Grandegger wrote:
This reverts commit
On Wed, Aug 19, 2020 at 09:28:39PM +0200, Marek Vasut wrote:
Is the F2SDRAM port enabled in your case ?
Is there a way I can check this via software? Unfortunately I do not
have access to Quartus/Qsys files, nor the person who did the design.
Ralph
when operating at 100Mbit.
Fixes: db5741f7a85ec3ee79b64496172afaa7dc2cb225 ("arm: socfpga: Convert system
manager from struct to defines")
Signed-off-by: Ralph Siemsen
---
I reviewed the other #defines for gen5 and they seem correct.
I have NOT checked the defines for Arria 10 or
Dear maintainers,
Any thoughts on this? It seems that "sf probe" behaviour should either
get fixed, or we should remove the "hz" and "mode" arguments entirely,
since they don't work anymore.
Regards,
Ralph
On Thu, Oct 15, 2020 at 12:25:41PM -0400, Ralph Siem
On Thu, Apr 21, 2022 at 2:01 PM Tom Rini wrote:
> OK, but this doesn't do anything. Where are you select'ing the new
> symbol from?
It is in code for a new platform which I am going to slowly beat into
shape and try to get upstreamed.
If you prefer to see everything at once, I can do that,
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
Correct spelling and copy/paste errors in comments.
Fixes 1c4db59d9b ("regmap: Add support for regmap fields")
Signed-off-by: Ralph Siemsen
---
include/regmap.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/regmap.h b/include/regmap.h
index
On Thu, Jul 7, 2022 at 7:07 AM Thu Ra wrote:
>
> Error: cmd/libkiosk_crypto.c:5:10: fatal error: unistd.h: No such file or
> directory
This file (libkiosk_crypto.c) is not part of u-boot. In the build log,
we can see that it is copied into the u-boot tree:
cp ../common/src/libkiosk_crypto.c
Update the diagnostic message with revised location of document, which
changed in 3e9fddfc4f1 ("doc: Move devicetree control doc to rST")
Signed-off-by: Ralph Siemsen
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index c
On Tue, Aug 23, 2022 at 12:14:31AM -0400, Sean Anderson wrote:
Regarding the unused fields (scon, mirack, mistat): I am not really
sure what their purpose is. Maybe there is some value in having them.
I'll try to find out more information about them. If we do decide to
drop them, I would like
On Mon, Aug 22, 2022 at 11:42:54PM -0400, Sean Anderson wrote:
+static int spkgimage_check_image_types(uint8_t type)
+{
+ return type == IH_TYPE_RENESAS_SPKG ? 0 : 1;
This function is not necessary if you only support one type.
Without this function, mkimage kept telling me that my
Hi Martin,
On Wed, Aug 3, 2022 at 6:05 AM Martin Bonner wrote:
>
> I and my colleagues have a number of patches we would like to
> contribute back to the community, however for various reasons
> (principally operating inside corporate firewalls), it isn't possible
> to use `git send-email`, and
On Sat, Aug 13, 2022 at 01:30:19AM -0400, Sean Anderson wrote:
+
+ u16 gate, reset, ready, midle,
+ scon, mirack, mistat;
What are the scon/mirack/mistat fields for? You define them for a lot
of clocks, but I don't see them used in the driver.
These came from the Linux
Hello Heinrich,
FYI, I had some trouble trying to apply your changes (patch seems to
be mangled?).
Only one small question for you, see below.
On Wed, Aug 10, 2022 at 2:42 AM Heinrich Schuchardt wrote:
>
> diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst
> index
On Tue, Aug 9, 2022 at 1:15 PM Sean Anderson wrote:
>
> The traditional way to handle this is to specify a config file with -n.
> See e.g. mtk_image
Thanks Pali and Sean. I have converted this tool to work as part of
mkimage, with a config file for the extra parameters. Patch v2 to
follow.
/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
---
Changes in v2:
- rewrote the stand-alone
On Sat, Aug 13, 2022 at 10:47 AM Sean Anderson wrote:
> >
> > board/schneider/lces/spkgimage.cfg | 26 +++
> > boot/image.c | 1 +
> > include/image.h| 1 +
> > tools/Makefile | 1 +
> > tools/spkgimage.c
://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzn1
[2] https://github.com/renesas-rz/rzn1_u-boot/tree/rzn1-stable
Michel Pollet (1):
tools: Add tool to create Renesas SPKG images
Ralph Siemsen (8):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare
.
The support code contains platform specific hardware access (TMU_BASE),
and it is not needed for other Renesas devices such as RZ/N1. Therefore,
alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2 and RCAR-GEN3.
Signed-off-by: Ralph Siemsen
---
drivers/clk/renesas/Kconfig | 2 +-
drivers/clk
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Only basic setup, not using the ECC features.
Signed-off-by: Ralph Siemsen
---
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile| 2 +
drivers/ram/cadence/Kconfig | 24 ++
drivers/ram/cadence
Add support for Schneider Electronics LCES1 / LCES2 boards, which are
based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
TODO: remove the debug UART settings from
of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c | 20
as existing Renesas RCAR2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
- TODO: add support for div_table
drivers/clk/renesas/Kconfig| 6 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a06g032-clocks.c | 734
the regmap_update_bits for level1/level2 register updates
--> does not exist for regmap_ranges, consider adding?
Signed-off-by: Ralph Siemsen
---
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/renesas/Kconfig| 7 +
drivers/pinctrl/renesas/Makef
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes
Signed-off-by: Ralph Siemsen
---
This tool could possibly be incorporated into mkimage / imagetools.
However it is unclear how to handle the extra commandline parameters
(NAND ECC settings, etc). So for now it is stand-alone tool.
tools/Makefile | 2 +
tools/spkg_header.h | 49
Hi Simon,
On Sun, Aug 7, 2022 at 9:25 AM Simon Glass wrote:
>
> Link to patman's documentation from the doc/ directory so that it appears
> in the 'make htmldocs' output.
Presumably this will show up on readthedocs? Seems like a nice addition.
The rename of README to README.rst would break
Hi Pali,
On Tuesday 09 August 2022 15:03:48 Pali Rohár wrote:
>
> Hello! You can use for example config file, like it has kwbimage.c which
> is integrated into mkimage and has support for NAND ECC settings.
Thank you, I was unaware of this config file approach. From a quick
look at
On Tue, Aug 9, 2022 at 12:07 PM Pali Rohár wrote:
>
> This documentation is not probably up-to-date. List of all kwbimage
> config options can be visible in kwbimage_generate_config() function.
I will check the code as well.
> > 1) mkimage already has far too many options
>
> I know. But for
On Tue, Aug 16, 2022 at 12:17 PM Andre Przywara wrote:
>
> So what is the story here? This commit seems to suggest U-Boot doesn't support
> even ARMv5 without "T", has this changed? There are probably other code
> places which would need adjustment to run on ARMv4?
Note that gcc 6.0 and later
, 2022 at 9:45 PM Ralph Siemsen wrote:
> >
> > I wonder if you could just fill in the header directly. This is
> > for a userspace tool, and this struct will be created at most
> > once. It's OK to use 10 bytes :)
>
> I could fill the header directly, but I figured
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
drivers/pinctrl/Makefile | 1
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
.
The support code contains platform specific hardware access (TMU_BASE),
and it is not needed for other Renesas devices such as RZ/N1. Therefore,
alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2/3.
Signed-off-by: Ralph Siemsen
Reviewed-by: Sean Anderson
---
(no changes since v3)
Changes
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v4:
- add binman support
resolved
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
Ralph Siemsen (10):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare for non-RCAR clock drivers
clk: renesas: add R906G032 driver
pinctrl: renesas: add R906G032 driver
ram: cadence: add
structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v4:
- commit message now includes hash of Linux upon which this is based
as well as the additional patches (clock table cleanups)
- sync changes from review on linux patches, including
- move RB macro higher up an
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
(no changes since v3)
Changes in v3:
- assorted small cleanups
- support version 1.0 silicon (previously #if 0...)
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile
-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
Reviewed-by: Simon Glass
---
Changes in v4
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes
Collect the list of currerently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
doc/board/renesas/index.rst | 9 +++
doc/board/renesas/renesas.rst | 115 ++
2
of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c
On Fri, Feb 24, 2023 at 10:19:53AM -0500, Ralph Siemsen wrote:
Hi Bryan,
On Thu, Feb 23, 2023 at 2:54 PM Bryan Brattlof wrote:
Hi Ralph!
Love seeing more boards here, though I know of a few chips that use some
type of cadence controller. I'm just curious if it would it make sense
to name
-snarc/spkgimage.cfg \
-T spkgimage -a 0x2004 -e 0x2004 \
-d u-boot.bin u-boot.bin.spkg
The config file (spkgimage.cfg in this example) contains additional
parameters such as NAND ECC settings.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- provide definition
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- assorted small cleanups
- support version 1.0 silicon (previously #if 0...)
drivers/ram/Kconfig | 1 +
drivers/ram/Makefile| 2 +
drivers/ram
as existing Renesas RCAR2/3
clock drivers, using a temporary structure filled on-the-fly.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- convert data table to explicit reg/bit numbers
- drop the unused scon, mirack, mirstat fields
- added some kernel docs to structures
- use enum for type field
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
drivers/pinctrl/Makefile | 1
Add support for Schneider Electronics RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v3:
- rename board LCES
of ARCH_RZN1 symbol.
Signed-off-by: Ralph Siemsen
---
(no changes since v1)
arch/arm/Kconfig | 17 +
arch/arm/Makefile | 1 +
arch/arm/mach-rzn1/Kconfig| 18 ++
arch/arm/mach-rzn1/Makefile | 3 +++
arch/arm/mach-rzn1/cpu_info.c
v2023.04-rc2
- reviewer suggestions added to spkgimage.c
- many small cleanups, checkpatch, FIXMEs resolved
Changes in v2:
- rewrote the stand-alone spkg_utility to integrate into mkimage
Ralph Siemsen (9):
ARM: armv7: add non-SPL enable for Cortex SMPEN
clk: renesas: prepare for non-RCAR clock
Hi Sean,
I finally got around to posting v3 of this patch series. I wanted to
touch on a few issues you had mentioned in previous review.
On Fri, Aug 26, 2022 at 11:47 AM Ralph Siemsen wrote:
>
> On Tue, Aug 23, 2022 at 12:14:31AM -0400, Sean Anderson wrote:
> >>Regarding th
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk/renesas/r9a06g032-clocks.c.
For starters, can you please include the exact kernel version ,
ideally
On Wed, Feb 22, 2023 at 07:45:45PM +0100, Marek Vasut wrote:
On 2/22/23 19:32, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 06:47:44PM +0100, Marek Vasut wrote:
Are those fixes in mainline Linux ?
Yes, they are in mainline:
2dee50ab9e72 clk: renesas: r9a06g032: Fix UART clkgrp bitsel
This should fix a rendering oddity when viewing the docs online at
https://u-boot.readthedocs.io/en/latest/develop/package/binman.html
Signed-off-by: Ralph Siemsen
---
tools/binman/binman.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/binman/binman.rst b/tools
On Wed, Feb 22, 2023 at 06:07:45PM +0100, Marek Vasut wrote:
On 2/22/23 17:57, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen wrote:
Clock driver for the Renesas RZ/N1 SoC family. This is based
on the Linux kernel drivers/clk
On Wed, Feb 22, 2023 at 06:47:44PM +0100, Marek Vasut wrote:
On 2/22/23 18:21, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 06:07:45PM +0100, Marek Vasut wrote:
On 2/22/23 17:57, Ralph Siemsen wrote:
On Wed, Feb 22, 2023 at 05:06:14PM +0100, Marek Vasut wrote:
On 2/22/23 16:44, Ralph Siemsen
Hi Simon,
Thanks for your review!
On Wed, Feb 22, 2023 at 2:17 PM Simon Glass wrote:
>
> Can you please add some details to doc/ for this SoC and how it boots,
> the use of mkimage, etc.?
Sure, I will cobble something together. Any particular good examples
to look at for inspiration?
> Also
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Additional functionality (from newer kernel versions) will be added
later. Note that the Linux side is under active development.
Signed-off-by: Ralph Siemsen
---
The following changes
.
The support code contains platform specific hardware access (TMU_BASE),
and it is not needed for other Renesas devices such as RZ/N1. Therefore,
alter Makefile to build renesas-cpg-mssr.c only for RCAR-GEN2/3.
Signed-off-by: Ralph Siemsen
Reviewed-by: Sean Anderson
---
Changes in v3:
- added tags
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off
Hi Bryan,
On Thu, Feb 23, 2023 at 2:54 PM Bryan Brattlof wrote:
>
> Hi Ralph!
> Love seeing more boards here, though I know of a few chips that use some
> type of cadence controller. I'm just curious if it would it make sense
> to name this with some type of Renesas specific branding?
Indeed
On Thu, Feb 23, 2023 at 9:09 AM Miquel Raynal wrote:
>
> Hi Marek,
>
> marek.va...@mailbox.org wrote on Thu, 23 Feb 2023 14:56:41 +0100:
> >
> > Either way is fine by me, I just want to be sure the u-boot clock tables
> > are in sync with Linux as much as possible, and can be easily resynced in
Hi Marek,
On Fri, Feb 24, 2023 at 12:05 PM Marek Vasut wrote:
>
> Could you at least submit the clean up to Linux and then sync the result
> to U-Boot, and indicate the Linux clock table came from commit
> with extra patch on top ?
Yes will do. I am refreshing my linux-side patch as we speak.
On Mon, Apr 17, 2023 at 07:07:57PM +0200, Marek Vasut wrote:
R-Car , not RCAR .
Ack, will fix in next version (including in some commit msg)
+static int r9a06g032_clk_probe(struct udevice *dev)
+{
+ struct r9a06g032_priv *priv = dev_get_priv(dev);
+ int err;
+
+
On Mon, Apr 17, 2023 at 07:04:15PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the correspondi
On Mon, Apr 17, 2023 at 07:15:07PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
[...]
+++ b/arch/arm/Kconfig
@@ -1031,6 +1031,21 @@ config ARCH_RMOBILE
imply SYS_THUMB_BUILD
imply ARCH_MISC_INIT if DISPLAY_CPUINFO
+config ARCH_RZN1
+ bool "Renea
On Mon, Apr 17, 2023 at 07:18:46PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
diff --git a/board/schneider/rzn1-snarc/ddr_timing.c
b/board/schneider/rzn1-snarc/ddr_timing.c
new file mode 100644
index 00..8bc3fe7be4
--- /dev/null
+++ b/board/schneider/rzn1-snarc
On Mon, Apr 17, 2023 at 10:34:08PM +0200, Marek Vasut wrote:
On 4/17/23 22:29, Ralph Siemsen wrote:
Indeed it does, see below. I did however want to document how to call
mkimage manually, since it took me a while to work out the right
arguments (especially using -n for the config file
On Mon, Apr 17, 2023 at 07:12:31PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
This is taken from Linux kernel 5.17, and contains just bare minimum
functionality: CPU, UART and system timer.
Why Linux 5.17 and not e.g. 6.2 or 6.1 LTS ?
It was the current version
On Mon, Apr 17, 2023 at 07:23:46PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
+ spkgimage.o \
Maybe just call the file renesas_spkgimage.o so its clear which
SoC/vendor this file is associtated with.
Okay, will do.
+static struct spkg_file
Hi Marek,
On Mon, Apr 17, 2023 at 07:02:34PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
diff --git a/drivers/clk/renesas/Makefile
b/drivers/clk/renesas/Makefile
index 8f82a7aa3e..a0d8c10bdb 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
On Mon, Apr 17, 2023 at 07:28:05PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
RZ/N1
+- Schneider rzn1-snarc board
+
+Building
+
+
+NOTE: the following information is for the rzn1 board only.
Maybe this should be in a separate document , some rzn1 specific
On Mon, Apr 17, 2023 at 10:33:18PM +0200, Marek Vasut wrote:
On 4/17/23 20:22, Ralph Siemsen wrote:
Perhaps we could change Kconfig to select CPG also for gen2. I can
make this patch, but how to test that this does not introduce any new
problems? Might there be an autobuilder for R-Car
On Mon, Apr 17, 2023 at 07:32:30PM +0200, Marek Vasut wrote:
On 3/8/23 21:26, Ralph Siemsen wrote:
[...]
+#define FUNCCTRL 0x00
+#define FUNCCTRL_MASKSDLOFS (0x18 << 16)
+#define FUNCCTRL_DVDDQ_1_5V (1 << 8)
+#define FUNCCTRL_RESET_N (1 << 0
On Mon, Apr 17, 2023 at 10:30:26PM +0200, Marek Vasut wrote:
I mean, if you drop 'CLK' and 'CLK_RENESAS' from this list, do they
still get selected because 'CLK_R8A06G032' is in this list ? If yes,
then drop them from this list, else keep them.
If I drop the first two, I get some kconfig
On Mon, Apr 17, 2023 at 4:21 PM Marek Vasut wrote:
>
> On 4/17/23 20:26, Ralph Siemsen wrote:
> > On Mon, Apr 17, 2023 at 07:04:15PM +0200, Marek Vasut wrote:
> >> You could send this patch as a separate one.
> >
> > In fact I did that almost a year ago:
&
The -l-e-constant flag has been deprecated since 2012. [1]
Use the recommended replacement instead.
[1] https://sourceforge.net/p/srecord/code/ci/1.59.D009/
Signed-off-by: Ralph Siemsen
---
arch/arm/mach-rmobile/Makefile | 48 +-
1 file changed, 24 insertions
On Tue, Apr 18, 2023 at 3:36 PM Marek Vasut wrote:
> I'm afraid this needs some backward compatibility sreccat version check
> . Similar to GCC compiler flags presence check. To avoid breaking legacy
> users.
I'll revisit this after the rz/n1 work, which is more important.
Also I noticed that
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