[U-Boot] [PATCH v2 00/18] Add U-Boot support for MediaTek SoCs - MT7623n & MT7629
Hello, This is the new round to add U-Boot support for MediaTek SoCs - MT7623n & MT7629, and the most of the drivers are based on mainline Linux, such as clock, timer, mmc, pinctrl, watchdog, power domain and device tree. The following are the major differences between mainline Linux and U-Boot: - Modify the drivers to adapt the U-Boot DM framework. - Remove unneeded DT nodes as they don't have proper drivers in U-Boot yet. - Just add the basic functions (step-by-step) so that we can monitor the size. - Reuse UART driver ns16550.c but add a highspeed register for MediaTek chips. - Add a whole new MT7629 SNOR driver which is based on SPI framework. Our current progress: The MT7623n (BananaPi R2) which has already been supported in mainline Linux. - Boot from eMMC or SD card. - Boot flow: ROM -> MediaTek's preloder -> U-Boot ... - An open development board called BananaPi R2 [1]. The MT7629 is NOT supported yet in mainline Linux, but I will add it soon. - Boot from SNOR currently. - Boot flow: ROM -> (boot header parsing sequence) -> SPL -> U-Boot ... [1] http://wiki.banana-pi.org/Banana_Pi_BPI-R2 Current implementation was validated via the FIT image. Thanks, Ryder Changes since v2: - Squash defconfig parts into other patches. - Drop unneeded definitions in include/configs/*. - Add a MT7629 qspi driver in the series. Changes since v1: - Fix new blank line at EOF and indentation. - Revise commit message. - Add missing sgmiisys device nodes. - Add Tested-by tags from Matthias. - Drop MT7629 qspi driver in the series, and we will implement another one based on the spi-mem framework. Guochun Mao (1): spi: mtk_qspi: add qspi driver for MT7629 SoC Ryder Lee (15): tools: MediaTek: add MTK boot header generation to mkimage arm: dts: MediaTek: add device tree for MT7629 arm: dts: MediaTek: add device tree for MT7623 arm: MediaTek: add basic support for MT7629 boards clk: MediaTek: add clock driver for MT7629 SoC. clk: MediaTek: add clock driver for MT7623 SoC. timer: MediaTek: add timer driver for MediaTek SoCs watchdog: MediaTek: add watchdog driver for MediaTek SoCs pinctrl: MediaTek: add pinctrl driver for MT7629 SoC pinctrl: MediaTek: add pinctrl driver for MT7623 SoC power domain: MediaTek: add power domain driver for MT7629 SoC power domain: MediaTek: add power domain driver for MT7623 SoC serial: 16550: allow the driver to support MediaTek serial ram: MediaTek: add DDR3 driver for MT7629 SoC MAINTAINERS: add an entry for MediaTek Weijie Gao (2): arm: MediaTek: add basic support for MT7623 boards mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC MAINTAINERS | 18 + Makefile | 22 + arch/arm/Kconfig | 14 + arch/arm/Makefile |1 + arch/arm/dts/Makefile |4 + arch/arm/dts/mt7623.dtsi | 255 + arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 arch/arm/dts/mt7629-rfb.dts | 71 ++ arch/arm/dts/mt7629.dtsi | 244 + arch/arm/include/asm/arch-mediatek/gpio.h |9 + arch/arm/include/asm/arch-mediatek/misc.h | 17 + arch/arm/mach-mediatek/Kconfig| 32 + arch/arm/mach-mediatek/Makefile |7 + arch/arm/mach-mediatek/cpu.c | 34 + arch/arm/mach-mediatek/init.h | 11 + arch/arm/mach-mediatek/mt7623/Makefile|4 + arch/arm/mach-mediatek/mt7623/init.c | 54 + arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 + arch/arm/mach-mediatek/mt7623/preloader.h | 99 ++ arch/arm/mach-mediatek/mt7629/Makefile|4 + arch/arm/mach-mediatek/mt7629/init.c | 131 +++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 + arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7623/Kconfig | 13 + board/mediatek/mt7623/MAINTAINERS |7 + board/mediatek/mt7623/Makefile|3 + board/mediatek/mt7623/mt7623_rfb.c| 16 + board/mediatek/mt7629/Kconfig | 17 + board/mediatek/mt7629/MAINTAINERS |7 + board/mediatek/mt7629/Makefile|3 + board/mediatek/mt7629/mt7629_rfb.c| 16 + common/image.c|1 + configs/mt7623n_bpir2_defconfig | 53 + configs/mt7629_rfb_defconfig | 73 ++ drivers/clk/Makefile |1 + drivers/clk/mediatek/Makefile |7 + drivers/clk/mediatek/clk-mt7623.c | 870 drivers/clk/mediatek/clk-mt7629.c | 709 + drivers/clk/mediatek/clk-mtk.c| 492 + drivers/clk/mediatek/clk-mtk.h| 153 +++
[U-Boot] [PATCH v2 11/18] pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/pinctrl/mediatek/Kconfig |4 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.h |1 +
4 files changed, 1290 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index e0145b1..1bd9a92 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -4,6 +4,10 @@ config PINCTRL_MTK
depends on PINCTRL_GENERIC
bool
+config PINCTRL_MT7623
+ bool "MT7623 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index cbf0765..f6ef362 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
new file mode 100644
index 000..6fa3e2b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -0,0 +1,1284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_BOND_REG0 0xb10
+#define PIN_BOND_REG1 0xf20
+#define PIN_BOND_REG2 0xef0
+#define BOND_PCIE_CLR (0x77 << 3)
+#define BOND_I2S_CLR 0x3
+#define BOND_MSDC0E_CLR0x1
+
+#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 15, false)
+
+#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, true)
+
+static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
+ PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
+ PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
+ PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
+ PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
+ PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
+ PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
+ PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
+ PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
+ PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
+ PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
+ PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
+ PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
+ PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
+ PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
+ PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
+ PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
+ PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
+ PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
+ PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
+ PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
+ PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
+ PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
+ PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
+ PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
+ PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
+ PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
+ PINS_FIELD16(118, 121, 0xce0, 0
[U-Boot] [PATCH v2 15/18] ram: MediaTek: add DDR3 driver for MT7629 SoC
This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou Signed-off-by: Ryder Lee --- drivers/ram/Makefile | 1 + drivers/ram/mediatek/Makefile | 7 + drivers/ram/mediatek/ddr3-mt7629.c | 766 + 3 files changed, 774 insertions(+) create mode 100644 drivers/ram/mediatek/Makefile create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 4ad3604..65cba80 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/ram/mediatek/Makefile b/drivers/ram/mediatek/Makefile new file mode 100644 index 000..95507b5 --- /dev/null +++ b/drivers/ram/mediatek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 MediaTek Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_TARGET_MT7629) = ddr3-mt7629.o diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c new file mode 100644 index 000..b413f49 --- /dev/null +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DDR3 driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Wu Zou + *Ryder Lee + */ + +#include +#include +#include +#include +#include + +/* EMI */ +#define EMI_CONA 0x000 +#define EMI_CONF 0x028 +#define EMI_CONM 0x060 + +/* DDR PHY */ +#define DDRPHY_PLL10x +#define DDRPHY_PLL20x0004 +#define DDRPHY_PLL30x0008 +#define DDRPHY_PLL40x000c +#define DDRPHY_PLL50x0010 +#define DDRPHY_PLL70x0018 +#define DDRPHY_B0_DLL_ARPI00x0080 +#define DDRPHY_B0_DLL_ARPI10x0084 +#define DDRPHY_B0_DLL_ARPI20x0088 +#define DDRPHY_B0_DLL_ARPI30x008c +#define DDRPHY_B0_DLL_ARPI40x0090 +#define DDRPHY_B0_DLL_ARPI50x0094 +#define DDRPHY_B0_DQ2 0x00a0 +#define DDRPHY_B0_DQ3 0x00a4 +#define DDRPHY_B0_DQ4 0x00a8 +#define DDRPHY_B0_DQ5 0x00ac +#define DDRPHY_B0_DQ6 0x00b0 +#define DDRPHY_B0_DQ7 0x00b4 +#define DDRPHY_B0_DQ8 0x00b8 +#define DDRPHY_B1_DLL_ARPI00x0100 +#define DDRPHY_B1_DLL_ARPI10x0104 +#define DDRPHY_B1_DLL_ARPI20x0108 +#define DDRPHY_B1_DLL_ARPI30x010c +#define DDRPHY_B1_DLL_ARPI40x0110 +#define DDRPHY_B1_DLL_ARPI50x0114 +#define DDRPHY_B1_DQ2 0x0120 +#define DDRPHY_B1_DQ3 0x0124 +#define DDRPHY_B1_DQ4 0x0128 +#define DDRPHY_B1_DQ5 0x012c +#define DDRPHY_B1_DQ6 0x0130 +#define DDRPHY_B1_DQ7 0x0134 +#define DDRPHY_B1_DQ8 0x0138 +#define DDRPHY_CA_DLL_ARPI00x0180 +#define DDRPHY_CA_DLL_ARPI10x0184 +#define DDRPHY_CA_DLL_ARPI20x0188 +#define DDRPHY_CA_DLL_ARPI30x018c +#define DDRPHY_CA_DLL_ARPI40x0190 +#define DDRPHY_CA_DLL_ARPI50x0194 +#define DDRPHY_CA_CMD2 0x01a0 +#define DDRPHY_CA_CMD3 0x01a4 +#define DDRPHY_CA_CMD5 0x01ac +#define DDRPHY_CA_CMD6 0x01b0 +#define DDRPHY_CA_CMD7 0x01b4 +#define DDRPHY_CA_CMD8 0x01b8 +#define DDRPHY_MISC_VREF_CTRL 0x0264 +#define DDRPHY_MISC_IMP_CTRL0 0x0268 +#define DDRPHY_MISC_IMP_CTRL1 0x026c +#define DDRPHY_MISC_SHU_OPT0x0270 +#define DDRPHY_MISC_SPM_CTRL0 0x0274 +#define DDRPHY_MISC_SPM_CTRL1 0x0278 +#define DDRPHY_MISC_SPM_CTRL2 0x027c +#define DDRPHY_MISC_CG_CTRL0 0x0284 +#define DDRPHY_MISC_CG_CTRL1 0x0288 +#define DDRPHY_MISC_CG_CTRL2 0x028c +#define DDRPHY_MISC_CG_CTRL4 0x0294 +#define DDRPHY_MISC_CTRL0 0x029c +#define DDRPHY_MISC_CTRL1 0x02a0 +#define DDRPHY_MISC_CTRL3 0x02a8 +#define DDRPHY_MISC_RXDVS1 0x05e4 +#define DDRPHY_SHU1_B0_DQ4 0x0c10 +#define DDRPHY_SHU1_B0_DQ5 0x0c14 +#define DDRPHY_SHU1_B0_DQ6 0x0c18 +#define DDRPHY_SHU1_B0_DQ7 0x0c1c +#define DDRPHY_SHU1_B1_DQ4 0x0c90 +#define DDRPHY_SHU1_B1_DQ5 0x0c94 +#define DDRPHY_SHU1_B1_DQ6 0x0c98 +#define DDRPHY_SHU1_B1_DQ7 0x0c9c +#define DDRPHY_SHU1_CA_CMD20x0d08 +#define DDRPHY_SHU1_CA_CMD40x0d10 +#define DDRPHY_SHU1_CA_CMD50x0d14 +#define DDRPHY_SHU1_CA_CMD60x0d18
[U-Boot] [PATCH v2 02/18] arm: dts: MediaTek: add device tree for MT7629
This patch adds MT7629 device tree and the includes it needs.
Signed-off-by: Ryder Lee
---
arch/arm/dts/Makefile| 3 +
arch/arm/dts/mt7629-rfb.dts | 71 +
arch/arm/dts/mt7629.dtsi | 244 +++
include/dt-bindings/clock/mt7629-clk.h | 206 ++
include/dt-bindings/power/mt7629-power.h | 13 ++
5 files changed, 537 insertions(+)
create mode 100644 arch/arm/dts/mt7629-rfb.dts
create mode 100644 arch/arm/dts/mt7629.dtsi
create mode 100644 include/dt-bindings/clock/mt7629-clk.h
create mode 100644 include/dt-bindings/power/mt7629-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfe9335..1ab01e1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -555,6 +555,9 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7629-rfb.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
new file mode 100644
index 000..e3b8fb4
--- /dev/null
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7629.dtsi"
+
+/ {
+ model = "MediaTek MT7629 RFB";
+ compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
+
+ aliases {
+ spi0 =
+ };
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+};
+
+ {
+ qspi_pins: qspi_pins {
+ pins_bus {
+ groups = "nor_flash_io", "nor_flash_wp",
+"nor_flash_hold";
+ function = "nor_flash";
+ };
+ };
+
+ uart0_pins: uart0-default {
+ mux {
+ function = "uart";
+ groups = "uart0_txd_rxd";
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "spi-flash";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
new file mode 100644
index 000..f7966cb
--- /dev/null
+++ b/arch/arm/dts/mt7629.dtsi
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7629";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <125000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clock-frequency = <125000>;
+ };
+ };
+
+ clk20m: oscillator@0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2000>;
+ clock-output-names = "clk20m";
+ };
+
+ clk40m: oscillator@1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4000>;
+ clock-output-names = "clkxtal";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <2000>;
+
[U-Boot] [PATCH v2 04/18] arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. Signed-off-by: Ryder Lee Signed-off-by: Weijie Gao --- arch/arm/Kconfig | 14 +++ arch/arm/Makefile | 1 + arch/arm/include/asm/arch-mediatek/misc.h | 17 arch/arm/mach-mediatek/Kconfig| 24 + arch/arm/mach-mediatek/Makefile | 6 ++ arch/arm/mach-mediatek/cpu.c | 34 +++ arch/arm/mach-mediatek/init.h | 11 +++ arch/arm/mach-mediatek/mt7629/Makefile| 4 + arch/arm/mach-mediatek/mt7629/init.c | 131 ++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 ++ arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7629/Kconfig | 17 board/mediatek/mt7629/MAINTAINERS | 7 ++ board/mediatek/mt7629/Makefile| 3 + board/mediatek/mt7629/mt7629_rfb.c| 16 configs/mt7629_rfb_defconfig | 73 ++ include/configs/mt7629.h | 62 17 files changed, 513 insertions(+) create mode 100644 arch/arm/include/asm/arch-mediatek/misc.h create mode 100644 arch/arm/mach-mediatek/Kconfig create mode 100644 arch/arm/mach-mediatek/Makefile create mode 100644 arch/arm/mach-mediatek/cpu.c create mode 100644 arch/arm/mach-mediatek/init.h create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile create mode 100644 arch/arm/mach-mediatek/mt7629/init.c create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/spl.c create mode 100644 board/mediatek/mt7629/Kconfig create mode 100644 board/mediatek/mt7629/MAINTAINERS create mode 100644 board/mediatek/mt7629/Makefile create mode 100644 board/mediatek/mt7629/mt7629_rfb.c create mode 100644 configs/mt7629_rfb_defconfig create mode 100644 include/configs/mt7629.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ccf2a84..eac03f0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -668,6 +668,18 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MEDIATEK + bool "MediaTek SoCs" + select DM + select OF_CONTROL + select SPL_DM if SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL + select SPL_OF_CONTROL if SPL + select SUPPORT_SPL + help + Support for the MediaTek SoCs family. + config ARCH_MX8M bool "NXP i.MX8M platform" select ARM64 @@ -1423,6 +1435,8 @@ source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-mediatek/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 8f50560..ddb9618 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE)+= keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h new file mode 100644 index 000..2530e78 --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/misc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_MISC_H_ +#define __MEDIATEK_MISC_H_ + +#define VER_BASE 0x0800 +#define VER_SIZE 0x10 + +#define APHW_CODE 0x00 +#define APHW_SUBCODE 0x04 +#define APHW_VER 0x08 +#define APSW_VER 0x0c + +#endif /* __MEDIATEK_MISC_H_ */ diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 000..a932e70 --- /dev/null +++ b/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,24 @@ +if ARCH_MEDIATEK + +config SYS_SOC + default "mediatek" + +config SYS_VENDOR + default "mediatek" + +choice + prompt "MediaTek board select" + +config TARGET_MT7629 + bool "MediaTek MT7629 SoC" + select CPU_V7A + select SPL + select ARCH_MISC_INIT + help + Support MediaTek MT7629 SoC. + +endchoice + +source "board/mediatek/mt7629/Kconfig" + +endif diff --git a/arch/arm/mach-mediatek/Makefile b/a
[U-Boot] [PATCH v2 05/18] arm: MediaTek: add basic support for MT7623 boards
From: Weijie Gao
This adds a general board file based on MT7623 SoCs from MediaTek.
As this u-boot is loaded by preloader, there is no low level
initializtion codes.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
arch/arm/mach-mediatek/Kconfig| 8 +++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7623/Makefile| 4 ++
arch/arm/mach-mediatek/mt7623/init.c | 54 +++
arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++
arch/arm/mach-mediatek/mt7623/preloader.h | 99 +++
board/mediatek/mt7623/Kconfig | 13
board/mediatek/mt7623/MAINTAINERS | 7 ++
board/mediatek/mt7623/Makefile| 3 +
board/mediatek/mt7623/mt7623_rfb.c| 16 +
configs/mt7623n_bpir2_defconfig | 53 ++
include/configs/mt7623.h | 61 +
12 files changed, 341 insertions(+)
create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7623/init.c
create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S
create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h
create mode 100644 board/mediatek/mt7623/Kconfig
create mode 100644 board/mediatek/mt7623/MAINTAINERS
create mode 100644 board/mediatek/mt7623/Makefile
create mode 100644 board/mediatek/mt7623/mt7623_rfb.c
create mode 100644 configs/mt7623n_bpir2_defconfig
create mode 100644 include/configs/mt7623.h
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index a932e70..b39bc44 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -9,6 +9,13 @@ config SYS_VENDOR
choice
prompt "MediaTek board select"
+config TARGET_MT7623
+ bool "MediaTek MT7623 SoC"
+ select CPU_V7A
+ select ARCH_MISC_INIT
+ help
+ Support MediaTek MT7623 SoC.
+
config TARGET_MT7629
bool "MediaTek MT7629 SoC"
select CPU_V7A
@@ -19,6 +26,7 @@ config TARGET_MT7629
endchoice
+source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 852d330..b5d3a37 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,4 +3,5 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
+obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
diff --git a/arch/arm/mach-mediatek/mt7623/Makefile
b/arch/arm/mach-mediatek/mt7623/Makefile
new file mode 100644
index 000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7623/init.c
b/arch/arm/mach-mediatek/mt7623/init.c
new file mode 100644
index 000..0ee8c66
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/init.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "preloader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct boot_argument *preloader_param;
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ u32 i;
+
+ if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ ((size_t)preloader_param % sizeof(size_t) == 0) &&
+ preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
+ preloader_param->dram_rank_num <=
+ ARRAY_SIZE(preloader_param->dram_rank_size)) {
+ gd->ram_size = 0;
+
+ for (i = 0; i < preloader_param->dram_rank_num; i++)
+ gd->ram_size += preloader_param->dram_rank_size[i];
+ } else {
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ SZ_2G);
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ void __iomem *chipid;
+ u32 swver;
+
+ chipid = ioremap(VER_BASE, VER_SIZE);
+ swver = readl(chipid + APSW_VER);
+
+ printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1);
+
+ return 0;
+}
diff --git a/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
new file mode 100644
index 000..afb9476
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include
+
+.externpreloader_param
+
+ENTRY(save_boot_params)
+ ldr r6, =preloader_param
+ str r4, [r6]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(lowlevel_init)
[U-Boot] [PATCH v2 03/18] arm: dts: MediaTek: add device tree for MT7623
This adds device tree for MT7623 development board - Bananapi R2
Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/mt7623.dtsi | 255 +++
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207
include/dt-bindings/clock/mt7623-clk.h | 413 +++
include/dt-bindings/power/mt7623-power.h | 19 ++
5 files changed, 895 insertions(+)
create mode 100644 arch/arm/dts/mt7623.dtsi
create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
create mode 100644 include/dt-bindings/clock/mt7623-clk.h
create mode 100644 include/dt-bindings/power/mt7623-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1ab01e1..44ed968 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -556,6 +556,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
new file mode 100644
index 000..3be5b6a
--- /dev/null
+++ b/arch/arm/dts/mt7623.dtsi
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7623";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <1300>;
+ #clock-cells = <0>;
+ };
+
+ rtc32k: oscillator-1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
+ };
+
+ clk26m: oscillator-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ clock-output-names = "clk26m";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt7623-topckgen";
+
[U-Boot] [PATCH v2 10/18] pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee
---
arch/arm/include/asm/arch-mediatek/gpio.h | 9 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 11 +
drivers/pinctrl/mediatek/Makefile | 6 +
drivers/pinctrl/mediatek/pinctrl-mt7629.c | 488 +++
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +
8 files changed, 1250 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h
b/arch/arm/include/asm/arch-mediatek/gpio.h
new file mode 100644
index 000..4ea1020
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_GPIO_H
+#define __MEDIATEK_GPIO_H
+
+#endif /* __MEDIATEK_GPIO_H */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8da..7e6fad3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -301,6 +301,7 @@ config ASPEED_AST2500_PINCTRL
endif
source "drivers/pinctrl/meson/Kconfig"
+source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d..293bad3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-$(CONFIG_PINCTRL_MTK) += mediatek/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 000..e0145b1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MEDIATEK
+
+config PINCTRL_MTK
+ depends on PINCTRL_GENERIC
+ bool
+
+config PINCTRL_MT7629
+ bool "MT7629 SoC pinctrl driver"
+ select PINCTRL_MTK
+
+endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 000..cbf0765
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
new file mode 100644
index 000..1787937
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+
+#define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
+
+static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
+ PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
+ PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
+ PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
+ PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
+ PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
+ PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
+ PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
+ PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
+
[U-Boot] [PATCH v2 06/18] clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee
---
drivers/clk/Makefile | 1 +
drivers/clk/mediatek/Makefile | 6 +
drivers/clk/mediatek/clk-mt7629.c | 709 ++
drivers/clk/mediatek/clk-mtk.c| 492 ++
drivers/clk/mediatek/clk-mtk.h| 153
5 files changed, 1361 insertions(+)
create mode 100644 drivers/clk/mediatek/Makefile
create mode 100644 drivers/clk/mediatek/clk-mt7629.c
create mode 100644 drivers/clk/mediatek/clk-mtk.c
create mode 100644 drivers/clk/mediatek/clk-mtk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8bc9f52..3641991 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
new file mode 100644
index 000..297f99d
--- /dev/null
+++ b/drivers/clk/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
+
+# SoC Drivers
+obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk/mediatek/clk-mt7629.c
new file mode 100644
index 000..46e9fad
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7629_CLKSQ_STB_CON0 0x20
+#define MT7629_PLL_ISO_CON00x2c
+#define MT7629_PLL_FMAX(2500UL * MHZ)
+#define MT7629_CON0_RST_BARBIT(24)
+
+#define MCU_AXI_DIV0x640
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX0x7c0
+#define MCU_BUS_MSKGENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7629_CON0_RST_BAR,\
+ .fmax = MT7629_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 3125),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 3125),
+
[U-Boot] [PATCH v2 12/18] power domain: MediaTek: add power domain driver for MT7629 SoC
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee
---
drivers/power/domain/Kconfig| 7 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/mtk-power-domain.c | 326
3 files changed, 334 insertions(+)
create mode 100644 drivers/power/domain/mtk-power-domain.c
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 2c34488..e479fed 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -16,6 +16,13 @@ config BCM6328_POWER_DOMAIN
Enable support for manipulating BCM6345 power domains via MMIO
mapped registers.
+config MTK_POWER_DOMAIN
+ bool "Enable the MediaTek power domain driver"
+ depends on POWER_DOMAIN && ARCH_MEDIATEK
+ help
+ Enable support for manipulating MediaTek power domains via MMIO
+ mapped registers.
+
config MESON_GX_VPU_POWER_DOMAIN
bool "Enable Amlogic Meson GX VPU power domain driver"
depends on ARCH_MESON
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 6bdaa17..d6c7aa7 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
+obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
new file mode 100644
index 000..5ebeabd
--- /dev/null
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define SPM_ETHSYS_PWR_CON 0x2e0
+#define SPM_HIF0_PWR_CON 0x2e4
+#define SPM_HIF1_PWR_CON 0x2e8
+#define SPM_PWR_STATUS 0x60c
+#define SPM_PWR_STATUS_2ND 0x610
+
+#define PWR_RST_B_BIT BIT(0)
+#define PWR_ISO_BITBIT(1)
+#define PWR_ON_BIT BIT(2)
+#define PWR_ON_2ND_BIT BIT(3)
+#define PWR_CLK_DIS_BITBIT(4)
+
+#define PWR_STATUS_ETHSYS BIT(24)
+#define PWR_STATUS_HIF0BIT(25)
+#define PWR_STATUS_HIF1BIT(26)
+
+/* Infrasys configuration */
+#define INFRA_TOPDCM_CTRL 0x10
+#define INFRA_TOPAXI_PROT_EN 0x220
+#define INFRA_TOPAXI_PROT_STA1 0x228
+
+#define DCM_TOP_EN BIT(0)
+
+enum scp_domain_type {
+ SCPSYS_MT7629,
+};
+
+struct scp_domain;
+
+struct scp_domain_data {
+ struct scp_domain *scpd;
+ u32 sta_mask;
+ int ctl_offs;
+ u32 sram_pdn_bits;
+ u32 sram_pdn_ack_bits;
+ u32 bus_prot_mask;
+};
+
+struct scp_domain {
+ void __iomem *base;
+ void __iomem *infracfg;
+ enum scp_domain_type type;
+ struct scp_domain_data *data;
+};
+
+static struct scp_domain_data scp_domain_mt7629[] = {
+ [MT7629_POWER_DOMAIN_ETHSYS] = {
+ .sta_mask = PWR_STATUS_ETHSYS,
+ .ctl_offs = SPM_ETHSYS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = (BIT(3) | BIT(17)),
+ },
+ [MT7629_POWER_DOMAIN_HIF0] = {
+ .sta_mask = PWR_STATUS_HIF0,
+ .ctl_offs = SPM_HIF0_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(25, 24),
+ },
+ [MT7629_POWER_DOMAIN_HIF1] = {
+ .sta_mask = PWR_STATUS_HIF1,
+ .ctl_offs = SPM_HIF1_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(28, 26),
+ },
+};
+
+/**
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hang when some unit accesses the
+ * bus while in power down.
+ */
+static int mtk_infracfg_set_bus_protection(void __iomem *infracfg,
+ u32 mask)
+{
+ u32 val;
+
+ clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask);
+
+ return
[U-Boot] [PATCH v2 07/18] clk: MediaTek: add clock driver for MT7623 SoC.
This patch adds a driver for MT7623 clock blocks.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7623.c | 870 ++
2 files changed, 871 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7623.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 297f99d..0632dc8 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7623.c
b/drivers/clk/mediatek/clk-mt7623.c
new file mode 100644
index 000..ac4450e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7623 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7623_CLKSQ_STB_CON0 0x18
+#define MT7623_PLL_ISO_CON00x24
+#define MT7623_PLL_FMAX(2000UL * MHZ)
+#define MT7623_CON0_RST_BARBIT(27)
+
+#define MCU_AXI_DIV0x60
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7623_CON0_RST_BAR,\
+ .fmax = MT7623_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x8001, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf001, HAVE_RST_BAR,
+ 21, 0x210, 4, 0x214, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf301, HAVE_RST_BAR,
+ 7, 0x220, 4, 0x224, 14),
+ PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x0001, 0,
+ 21, 0x230, 4, 0x234, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x0001, 0,
+ 21, 0x240, 4, 0x244, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x0001, 0,
+ 21, 0x250, 4, 0x254, 0),
+ PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x0001, 0,
+ 31, 0x270, 4, 0x274, 0),
+ PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x0001, 0,
+ 31, 0x280, 4, 0x284, 0),
+ PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x0001, 0,
+ 31, 0x290, 4, 0x294, 0),
+ PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x0001, 0,
+ 31, 0x2a0, 4, 0x2a4, 0),
+ PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x0001, 0,
+ 31, 0x2b0, 4, 0x2b4, 0),
+ PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x0001, 0,
+ 31, 0x2c0, 4, 0x2c4, 0),
+ PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x0001, 0,
+ 21, 0x2d0, 4, 0x2d4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
+ FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
+ FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
+ FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
+ FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
+
[U-Boot] [PATCH v2 01/18] tools: MediaTek: add MTK boot header generation to mkimage
This patch adds support for MTK boot image generation.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
---
Makefile | 22 ++
common/image.c | 1 +
include/image.h | 1 +
scripts/Makefile.spl | 11 +
tools/Makefile | 1 +
tools/mtkimage.c | 749 +++
tools/mtkimage.h | 199 ++
7 files changed, 984 insertions(+)
create mode 100644 tools/mtkimage.c
create mode 100644 tools/mtkimage.h
diff --git a/Makefile b/Makefile
index aadd1ec..5ca7da6 100644
--- a/Makefile
+++ b/Makefile
@@ -852,6 +852,8 @@ ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin
endif
+ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
+
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
@@ -1357,6 +1359,26 @@ u-boot.elf: u-boot.bin
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+# MediaTek's ARM-based u-boot needs a header to contains its load address
+# which is parsed by the BootROM.
+# If the SPL build is enabled, the header will be added to the spl binary,
+# and the spl binary and the u-boot.img will be combined into one file.
+# Otherwise the header will be added to the u-boot.bin directly.
+
+ifeq ($(CONFIG_SPL),y)
+OBJCOPYFLAGS_u-boot-mtk.bin = -I binary -O binary \
+ --pad-to=$(CONFIG_SPL_PAD_TO)
+u-boot-mtk.bin: spl/u-boot-spl-mtk.bin u-boot.img FORCE
+ $(call if_changed,pad_cat)
+else
+MKIMAGEFLAGS_u-boot-mtk.bin = -T mtkimage \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+u-boot-mtk.bin: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+endif
+
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
diff --git a/common/image.c b/common/image.c
index 4f20128..3035cc8 100644
--- a/common/image.c
+++ b/common/image.c
@@ -165,6 +165,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT"
},
{ IH_TYPE_PMMC,"pmmc","TI Power Management
Micro-Controller Firmware",},
{ IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32
Image" },
+ { IH_TYPE_MTKIMAGE, "mtkimage", "MeidaTek BootROM loadable
Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 3bb7d29..3128981 100644
--- a/include/image.h
+++ b/include/image.h
@@ -277,6 +277,7 @@ enum {
IH_TYPE_PMMC,/* TI Power Management Micro-Controller
Firmware */
IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
IH_TYPE_SOCFPGAIMAGE_V1,/* Altera SOCFPGA A10 Preloader */
+ IH_TYPE_MTKIMAGE, /* MeidaTek BootROM loadable Image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7416abe..989461a 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -219,6 +219,8 @@ ALL-$(CONFIG_SPL_X86_16BIT_INIT) +=
$(obj)/u-boot-x86-16bit-spl.bin
ALL-$(CONFIG_ARCH_ZYNQ)+= $(obj)/boot.bin
ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_MEDIATEK)+= $(obj)/u-boot-spl-mtk.bin
+
all: $(ALL-y)
quiet_cmd_cat = CAT $@
@@ -349,6 +351,15 @@ cmd_sunxi_spl_image_builder =
$(objtree)/tools/sunxi-spl-image-builder \
$(obj)/sunxi-spl-with-ecc.bin: $(obj)/sunxi-spl.bin
$(call if_changed,sunxi_spl_image_builder)
+
+# MediaTek's specific SPL build
+MKIMAGEFLAGS_u-boot-spl-mtk.bin = -T mtkimage \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+$(obj)/u-boot-spl-mtk.bin: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
# Rule to link u-boot-spl
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot-spl ?= LD $@
diff --git a/tools/Makefile b/tools/Makefile
index 0c3341e..11732e3 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -115,6 +115,7 @@ dumpimage-mkimage-objs := aisimage.o \
$(LIBFDT_OBJS) \
gpimage.o \
gpimage-common.o \
+ mtkimage.o \
$(RSA_OBJS-y)
dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
diff --git a/tools/mtkimage.c b/tools/mtkimage.c
new file mode 100644
index 000..23ca378
--- /dev/null
+++ b/tools/mtkimage.c
@@ -0,0 +1,749 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generate MediaTek BootROM hea
[U-Boot] [PATCH v2 13/18] power domain: MediaTek: add power domain driver for MT7623 SoC
This adds power domain (scpsys) support for MT7623 SoC.
Signed-off-by: Ryder Lee
---
drivers/power/domain/mtk-power-domain.c | 80 +
1 file changed, 80 insertions(+)
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
index 5ebeabd..8b97a16 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -14,8 +14,18 @@
#include
#include
+#include
#include
+#define SPM_VDE_PWR_CON0x0210
+#define SPM_MFG_PWR_CON0x0214
+#define SPM_ISP_PWR_CON0x0238
+#define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON 0x0280
+#define SPM_BDP_PWR_CON0x029c
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
#define SPM_ETHSYS_PWR_CON 0x2e0
#define SPM_HIF0_PWR_CON 0x2e4
#define SPM_HIF1_PWR_CON 0x2e8
@@ -28,6 +38,15 @@
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BITBIT(4)
+#define PWR_STATUS_CONNBIT(1)
+#define PWR_STATUS_DISPBIT(3)
+#define PWR_STATUS_MFG BIT(4)
+#define PWR_STATUS_ISP BIT(5)
+#define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
#define PWR_STATUS_ETHSYS BIT(24)
#define PWR_STATUS_HIF0BIT(25)
#define PWR_STATUS_HIF1BIT(26)
@@ -40,6 +59,7 @@
#define DCM_TOP_EN BIT(0)
enum scp_domain_type {
+ SCPSYS_MT7623,
SCPSYS_MT7629,
};
@@ -61,6 +81,59 @@ struct scp_domain {
struct scp_domain_data *data;
};
+static struct scp_domain_data scp_domain_mt7623[] = {
+ [MT7623_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .bus_prot_mask = BIT(8) | BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_DISP] = {
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .bus_prot_mask = BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_MFG] = {
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_VDEC] = {
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_ISP] = {
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ },
+ [MT7623_POWER_DOMAIN_BDP] = {
+ .sta_mask = PWR_STATUS_BDP,
+ .ctl_offs = SPM_BDP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ },
+ [MT7623_POWER_DOMAIN_ETH] = {
+ .sta_mask = PWR_STATUS_ETH,
+ .ctl_offs = SPM_ETH_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_HIF] = {
+ .sta_mask = PWR_STATUS_HIF,
+ .ctl_offs = SPM_HIF_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_IFR_MSC] = {
+ .sta_mask = PWR_STATUS_IFR_MSC,
+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
+ },
+};
+
static struct scp_domain_data scp_domain_mt7629[] = {
[MT7629_POWER_DOMAIN_ETHSYS] = {
.sta_mask = PWR_STATUS_ETHSYS,
@@ -252,6 +325,9 @@ static int mtk_power_domain_hook(struct udevice *dev)
scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
switch (scpd->type) {
+ case SCPSYS_MT7623:
+ scpd->data = scp_domain_mt7623;
+ break;
case SCPSYS_MT7629:
scpd->data = scp_domain_mt7629;
break;
@@ -303,6 +379,10 @@ static int mtk_power_domain_probe(struct udevice *dev)
static const struct udevice_id mtk_power_domain_ids[] = {
{
+ .compatible = "mediatek,mt7623-scpsys",
+ .data = SCPSYS_MT7623,
+ },
+ {
.compatible = "mediatek,mt7629-scpsys",
.data = SCPSYS_MT7629,
},
--
1.9.1
___
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[U-Boot] [PATCH v2 08/18] timer: MediaTek: add timer driver for MediaTek SoCs
This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/timer/Kconfig | 7
drivers/timer/Makefile| 1 +
drivers/timer/mtk_timer.c | 85 +++
3 files changed, 93 insertions(+)
create mode 100644 drivers/timer/mtk_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index a7d600b..6013945 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -147,4 +147,11 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
+config MTK_TIMER
+ bool "MediaTek timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ MediaTek devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 7f19c49..c4fbab2 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
new file mode 100644
index 000..b5e76bd
--- /dev/null
+++ b/drivers/timer/mtk_timer.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek timer driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_GPT4_CTRL 0x40
+#define MTK_GPT4_CLK 0x44
+#define MTK_GPT4_CNT 0x48
+
+#define GPT4_ENABLEBIT(0)
+#define GPT4_CLEAR BIT(1)
+#define GPT4_FREERUN GENMASK(5, 4)
+#define GPT4_CLK_SYS 0x0
+#define GPT4_CLK_DIV1 0x0
+
+struct mtk_timer_priv {
+ void __iomem *base;
+};
+
+static int mtk_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ u32 val = readl(priv->base + MTK_GPT4_CNT);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int mtk_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk, parent;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 1, );
+ if (!ret) {
+ ret = clk_set_parent(, );
+ if (ret)
+ return ret;
+ }
+
+ uc_priv->clock_rate = clk_get_rate();
+ if (!uc_priv->clock_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct timer_ops mtk_timer_ops = {
+ .get_count = mtk_timer_get_count,
+};
+
+static const struct udevice_id mtk_timer_ids[] = {
+ { .compatible = "mediatek,timer" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_timer) = {
+ .name = "mtk_timer",
+ .id = UCLASS_TIMER,
+ .of_match = mtk_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct mtk_timer_priv),
+ .probe = mtk_timer_probe,
+ .ops = _timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
1.9.1
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Re: [U-Boot] [PATCH v1 04/19] arm: MediaTek: add basic support for MT7629 boards
On Thu, 2018-10-11 at 10:10 -0400, Tom Rini wrote: > On Tue, Oct 09, 2018 at 11:54:04AM +0800, Ryder Lee wrote: > > > This adds a general board file based on MT7629 SoCs from MediaTek. > > > > Apart from the generic parts (cpu) we add some low level init codes > > and initialize the early clocks. > > > > Signed-off-by: Ryder Lee > > Signed-off-by: Weijie Gao > [snip] > > diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h > > new file mode 100644 > > index 000..e640108 > > --- /dev/null > > +++ b/include/configs/mt7629.h > > @@ -0,0 +1,71 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Configuration for MediaTek MT7629 SoC > > + * > > + * Copyright (C) 2018 MediaTek Inc. > > + * Author: Ryder Lee > > + */ > > + > > +#ifndef __MT7629_H > > +#define __MT7629_H > > + > > +#include > > + > > +#include > > +#include > > We don't want these two includes here. > > > +#ifndef __ASSEMBLY__ > > +extern unsigned long get_spl_size(void); > > +#endif > > Nor should we have this here. > > > +/* Machine ID */ > > +#define CONFIG_MACH_TYPE 7629 > > Since this is for pre-DT kernels, lets drop this. > > > +#define NOR_MMAP_ADDR 0x3000 > > +#define CONFIG_SYS_SPI_U_BOOT_OFFS get_spl_size() > > +#define CONFIG_SYS_UBOOT_BASE (NOR_MMAP_ADDR + get_spl_size()) > > Use the value of NOR_MMAP_ADDR directly, and we use some constant > (rounded up as needed) for SYS_SPI_U_BOOT_OFFS not a function. > > And all of these comments apply to the other include/configs/ files in > the rest of the series too, thanks! > Okay. I've sent a new series to fix these. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 17/18] spi: mtk_qspi: add qspi driver for MT7629 SoC
From: Guochun Mao
This patch adds MT7629 qspi driver for accessing SPI NOR flash.
Cc: Jagan Teki
Signed-off-by: Guochun Mao
---
change since v2:
- Drop flash commands in the driver.
---
drivers/spi/Kconfig| 7 +
drivers/spi/Makefile | 1 +
drivers/spi/mtk_qspi.c | 359 +
3 files changed, 367 insertions(+)
create mode 100644 drivers/spi/mtk_qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 1df6876..f9cf4ba 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -124,6 +124,13 @@ config MT7621_SPI
the SPI NOR flash on platforms embedding this Ralink / MediaTek
SPI core, like MT7621/7628/7688.
+config MTK_QSPI
+ bool "Mediatek QSPI driver"
+ help
+ Enable the Mediatek QSPI driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Mediatek QSPI IP core.
+
config MVEBU_A3700_SPI
bool "Marvell Armada 3700 SPI driver"
select CLK_ARMADA_3720
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 7242ea7..e5a78f5 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
+obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o
obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/mtk_qspi.c b/drivers/spi/mtk_qspi.c
new file mode 100644
index 000..b510733
--- /dev/null
+++ b/drivers/spi/mtk_qspi.c
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek, Inc.
+ * Author : guochun@mediatek.com
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Register Offset */
+struct mtk_qspi_regs {
+ u32 cmd;
+ u32 cnt;
+ u32 rdsr;
+ u32 rdata;
+ u32 radr[3];
+ u32 wdata;
+ u32 prgdata[6];
+ u32 shreg[10];
+ u32 cfg[2];
+ u32 shreg10;
+ u32 mode_mon;
+ u32 status[4];
+ u32 flash_time;
+ u32 flash_cfg;
+ u32 reserved_0[3];
+ u32 sf_time;
+ u32 pp_dw_data;
+ u32 reserved_1;
+ u32 delsel_0[2];
+ u32 intrstus;
+ u32 intren;
+ u32 reserved_2;
+ u32 cfg3;
+ u32 reserved_3;
+ u32 chksum;
+ u32 aaicmd;
+ u32 wrprot;
+ u32 radr3;
+ u32 dual;
+ u32 delsel_1[3];
+};
+
+struct mtk_qspi_platdata {
+ fdt_addr_t reg_base;
+ fdt_addr_t mem_base;
+};
+
+struct mtk_qspi_priv {
+ struct mtk_qspi_regs *regs;
+ unsigned long *mem_base;
+ u8 op;
+ u8 tx[3]; /* only record max 3 bytes paras, when it's address. */
+ u32 txlen; /* dout buffer length - op code length */
+ u8 *rx;
+ u32 rxlen;
+};
+
+#define MTK_QSPI_CMD_POLLINGREG_US 50
+#define MTK_QSPI_WRBUF_SIZE256
+#define MTK_QSPI_COMMAND_ENABLE0x30
+
+/* NOR flash controller commands */
+#define MTK_QSPI_RD_TRIGGERBIT(0)
+#define MTK_QSPI_READSTATUSBIT(1)
+#define MTK_QSPI_PRG_CMD BIT(2)
+#define MTK_QSPI_WR_TRIGGERBIT(4)
+#define MTK_QSPI_WRITESTATUS BIT(5)
+#define MTK_QSPI_AUTOINC BIT(7)
+
+#define MTK_QSPI_MAX_RX_TX_SHIFT 0x6
+#define MTK_QSPI_MAX_SHIFT 0x8
+
+#define MTK_QSPI_WR_BUF_ENABLE 0x1
+#define MTK_QSPI_WR_BUF_DISABLE0x0
+
+static int mtk_qspi_execute_cmd(struct mtk_qspi_priv *priv, u8 cmd)
+{
+ u8 tmp;
+ u8 val = cmd & ~MTK_QSPI_AUTOINC;
+
+ writeb(cmd, >regs->cmd);
+
+ return readb_poll_timeout(>regs->cmd, tmp, !(val & tmp),
+ MTK_QSPI_CMD_POLLINGREG_US);
+}
+
+static int mtk_qspi_tx_rx(struct mtk_qspi_priv *priv)
+{
+ int len = 1 + priv->txlen + priv->rxlen;
+ int i, ret, idx;
+
+ if (len > MTK_QSPI_MAX_SHIFT)
+ return -ERR_INVAL;
+
+ writeb(len * 8, >regs->cnt);
+
+ /* start at PRGDATA5, go down to PRGDATA0 */
+ idx = MTK_QSPI_MAX_RX_TX_SHIFT - 1;
+
+ /* opcode */
+ writeb(priv->op, >regs->prgdata[idx]);
+ idx--;
+
+ /* program TX data */
+ for (i = 0; i < priv->txlen; i++, idx--)
+ writeb(priv->tx[i], >regs->prgdata[idx]);
+
+ /* clear out rest of TX registers */
+ while (idx >= 0) {
+ writeb(0, >regs->prgdata[idx]);
+ idx--;
+ }
+
+ ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_PRG_CMD);
+ if (ret)
+ return ret;
+
+ /* restart at first RX byte */
+ idx = priv->rxlen - 1;
+
+ /* read out RX data */
+ for (i = 0; i < priv->rxlen; i++, idx--)
+ priv->rx[i] = readb(>regs->shreg[idx]);
+
+ return 0;
+}
+
+static int mtk_qspi_read(struct mtk_qspi_priv *priv,
+
Re: [U-Boot] [PATCH v1 06/19] configs: MediaTek: add MT7629 reference board support
On Thu, 2018-10-11 at 10:10 -0400, Tom Rini wrote: > On Tue, Oct 09, 2018 at 11:54:06AM +0800, Ryder Lee wrote: > > > This patch adds defconfig for the MT7629 reference board. > > > > Signed-off-by: Ryder Lee > > --- > > configs/mt7629_rfb_defconfig | 72 > > > > 1 file changed, 72 insertions(+) > > create mode 100644 configs/mt7629_rfb_defconfig > > This should be squashed into the patch which also adds include/configs/ > for the platform and please make sure the MAINTAINERS entry also has > these files, thanks! > I've sent a new series to squash these configs and the files which have been listed in board/mediatek/mt*/MAINTAINERS. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 09/18] watchdog: MediaTek: add watchdog driver for MediaTek SoCs
This patch adds a common driver for the Mediatek SoC integrated
watchdog.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/watchdog/Kconfig | 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/mtk_wdt.c | 135 +
3 files changed, 144 insertions(+)
create mode 100644 drivers/watchdog/mtk_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d545b3e..57a12f5 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -103,6 +103,14 @@ config WDT_CDNS
Select this to enable Cadence watchdog timer, which can be found on
some
Xilinx Microzed Platform.
+config WDT_MTK
+ bool "MediaTek watchdog timer support"
+ depends on WDT && ARCH_MEDIATEK
+ help
+ Select this to enable watchdog timer for MediaTek SoCs.
+ The watchdog timer is stopped when initialized.
+ It performs full SoC reset.
+
config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 08406ca..04fa4a6 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o
+obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
new file mode 100644
index 000..0b50173
--- /dev/null
+++ b/drivers/watchdog/mtk_wdt.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Watchdog driver for MediaTek SoCs
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#define MTK_WDT_MODE 0x00
+#define MTK_WDT_LENGTH 0x04
+#define MTK_WDT_RESTART0x08
+#define MTK_WDT_STATUS 0x0c
+#define MTK_WDT_INTERVAL 0x10
+#define MTK_WDT_SWRST 0x14
+#define MTK_WDT_REQ_MODE 0x30
+#define MTK_WDT_DEBUG_CTL 0x40
+
+#define WDT_MODE_KEY (0x22 << 24)
+#define WDT_MODE_ENBIT(0)
+#define WDT_MODE_EXTPOLBIT(1)
+#define WDT_MODE_EXTEN BIT(2)
+#define WDT_MODE_IRQ_ENBIT(3)
+#define WDT_MODE_DUAL_EN BIT(6)
+
+#define WDT_LENGTH_KEY 0x8
+#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
+
+#define WDT_RESTART_KEY0x1971
+#define WDT_SWRST_KEY 0x1209
+
+struct mtk_wdt_priv {
+ void __iomem *base;
+};
+
+static int mtk_wdt_reset(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Reload watchdog duration */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ return 0;
+}
+
+static int mtk_wdt_stop(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
+
+ return 0;
+}
+
+static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Kick watchdog to prevent counter == 0 */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ /* Reset */
+ writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
+ hang();
+
+ return 0;
+}
+
+static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /*
+* One bit is the value of 512 ticks
+* The clock has 32 KHz
+*/
+ timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
+ writel(timeout, priv->base + MTK_WDT_LENGTH);
+
+ mtk_wdt_reset(dev);
+}
+
+static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ mtk_wdt_set_timeout(dev, timeout);
+
+ /* Enable watchdog reset signal */
+ setbits_le32(priv->base + MTK_WDT_MODE,
+WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
+
+ return 0;
+}
+
+static int mtk_wdt_probe(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ /* Clear status */
+ clrsetbits_le32(priv->base + MTK_WDT_MODE,
+ WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
+
+ return mtk_wdt_stop(dev);
+}
+
+static const struct wdt_ops mtk_wdt_ops = {
+ .start = mtk_wdt_start,
+ .reset = mtk_wdt_reset,
+ .stop = mtk_wdt_stop,
+ .expire_now = mtk_wdt_expire_now,
+};
[U-Boot] [PATCH v2 16/18] mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC
From: Weijie Gao This patch adds MT7623 host controller driver for accessing SD/MMC. Cc: Jaehoon Chung Signed-off-by: Weijie Gao Signed-off-by: Ryder Lee Tested-by: Matthias Brugger --- drivers/mmc/Kconfig |9 + drivers/mmc/Makefile |1 + drivers/mmc/mtk-sd.c | 1331 ++ 3 files changed, 1341 insertions(+) create mode 100644 drivers/mmc/mtk-sd.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0a0d4aa..ca13341 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -598,6 +598,15 @@ config FTSDC010_SDIO help This can enable ftsdc010 sdio function. +config MMC_MTK + bool "MediaTek SD/MMC Card Interface support" + default n + help + This selects the MediaTek(R) Secure digital and Multimedia card Interface. + If you have a machine with a integrated SD/MMC card reader, say Y or M here. + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 23c5b0d..801a26d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o +obj-$(CONFIG_MMC_MTK) += mtk-sd.o diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c new file mode 100644 index 000..5027764 --- /dev/null +++ b/drivers/mmc/mtk-sd.c @@ -0,0 +1,1331 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek SD/MMC Card Interface driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MSDC_CFG 0x0 +#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) +#define MSDC_CFG_CKMOD_EXT_M 0x03 +#define MSDC_CFG_CKMOD_EXT_S 20 +#define MSDC_CFG_CKDIV_EXT_M 0xfff +#define MSDC_CFG_CKDIV_EXT_S 8 +#define MSDC_CFG_HS400_CK_MODE BIT(18) +#define MSDC_CFG_CKMOD_M 0x03 +#define MSDC_CFG_CKMOD_S 16 +#define MSDC_CFG_CKDIV_M 0xff +#define MSDC_CFG_CKDIV_S 8 +#define MSDC_CFG_CKSTB BIT(7) +#define MSDC_CFG_PIO BIT(3) +#define MSDC_CFG_RST BIT(2) +#define MSDC_CFG_CKPDN BIT(1) +#define MSDC_CFG_MODEBIT(0) + +#define MSDC_IOCON 0x04 +#define MSDC_IOCON_W_DSPLBIT(8) +#define MSDC_IOCON_DSPL BIT(2) +#define MSDC_IOCON_RSPL BIT(1) + +#define MSDC_PS0x08 +#define MSDC_PS_DAT0 BIT(16) +#define MSDC_PS_CDEN BIT(0) + +#define MSDC_INT 0x0c +#define MSDC_INTEN 0x10 +#define MSDC_INT_ACMDRDY BIT(3) +#define MSDC_INT_ACMDTMO BIT(4) +#define MSDC_INT_ACMDCRCERR BIT(5) +#define MSDC_INT_CMDRDY BIT(8) +#define MSDC_INT_CMDTMO BIT(9) +#define MSDC_INT_RSPCRCERR BIT(10) +#define MSDC_INT_XFER_COMPL BIT(12) +#define MSDC_INT_DATTMO BIT(14) +#define MSDC_INT_DATCRCERR BIT(15) + +#define MSDC_FIFOCS0x14 +#define MSDC_FIFOCS_CLR BIT(31) +#define MSDC_FIFOCS_TXCNT_M 0xff +#define MSDC_FIFOCS_TXCNT_S 16 +#define MSDC_FIFOCS_RXCNT_M 0xff +#define MSDC_FIFOCS_RXCNT_S 0 + +#define MSDC_TXDATA0x18 +#define MSDC_RXDATA0x1c + +#define SDC_CFG0x30 +#define SDC_CFG_DTOC_M 0xff +#define SDC_CFG_DTOC_S 24 +#define SDC_CFG_SDIOIDE BIT(20) +#define SDC_CFG_SDIO BIT(19) +#define SDC_CFG_BUSWIDTH_M 0x03 +#define SDC_CFG_BUSWIDTH_S 16 + +#define SDC_CMD0x34 +#define SDC_CMD_BLK_LEN_M0xfff +#define SDC_CMD_BLK_LEN_S16 +#define SDC_CMD_STOP BIT(14) +#define SDC_CMD_WR BIT(13) +#define SDC_CMD_DTYPE_M 0x03 +#define SDC_CMD_DTYPE_S 11 +#define SDC_CMD_RSPTYP_M 0x07 +#define SDC_CMD_RSPTYP_S 7 +#define SDC_CMD_CMD_M0x3f +#define SDC_CMD_CMD_S0 + +#define SDC_ARG0x38 + +#define SDC_STS0x3c +#define SDC_STS_CMDBUSY BIT(1
[U-Boot] [PATCH v2 18/18] MAINTAINERS: add an entry for MediaTek
This patch adds an entry for MediaTek. Signed-off-by: Ryder Lee --- MAINTAINERS | 18 ++ 1 file changed, 18 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index ace7d9a..c8b7ecb 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,24 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM MEDIATEK +M: Ryder Lee +M: Weijie Gao +S: Maintained +F: arch/arm/mach-mediatek/ +F: arch/arm/include/asm/arch-mediatek/ +F: board/mediatek/ +F: drivers/clk/mediatek/ +F: drivers/mmc/mtk-sd.c +F: drivers/pinctrl/mediatek/ +F: drivers/power/domain/mtk-power-domain.c +F: drivers/ram/mediatek/ +F: drivers/spi/mtk_qspi.c +F: drivers/timer/mtk_timer.c +F: drivers/watchdog/mtk_wdt.c +F: tools/mtkimage.c +N: mediatek + ARM OWL M: Manivannan Sadhasivam S: Maintained -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 14/18] serial: 16550: allow the driver to support MediaTek serial
This patch adds an extra operation in ns16550.c to suuport MediaTek
SoCs as we have a highspeed register which influences the calcualtion
of the divisor.
Note that we don't support the baudrate greater than 115200 currently.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/serial/ns16550.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index f9041aa..f5410af 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -148,6 +148,13 @@ int ns16550_calc_divisor(NS16550_t port, int clock, int
baudrate)
static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
{
+#ifdef CONFIG_ARCH_MEDIATEK
+ /*
+* MediaTek UARTs has an extra highspeed register.
+* We need to clear it if baudrate <= 115200.
+*/
+ serial_out(0, _port->reg9);
+#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, _port->lcr);
serial_out(baud_divisor & 0xff, _port->dll);
serial_out((baud_divisor >> 8) & 0xff, _port->dlm);
@@ -261,6 +268,9 @@ static inline void _debug_uart_init(void)
serial_dout(_port->mcr, UART_MCRVAL);
serial_dout(_port->fcr, UART_FCR_DEFVAL);
+#ifdef CONFIG_ARCH_MEDIATEK
+ serial_dout(_port->reg9, 0);
+#endif
serial_dout(_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
serial_dout(_port->dll, baud_divisor & 0xff);
serial_dout(_port->dlm, (baud_divisor >> 8) & 0xff);
--
1.9.1
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Re: [U-Boot] [PATCH v2 10/18] pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
Hi Simon,
On Wed, 2018-10-24 at 21:29 -0600, Simon Glass wrote:
> Hi Ryder,
>
> On 12 October 2018 at 01:00, Ryder Lee wrote:
> > This patch adds pinctrl support for MT7629 SoC. The IO core found on
> > the SoC has the registers for pinctrl, pinconf and gpio mixed up in
> > the same register range. Hence the driver also implements the gpio
> > functionality through UCLASS_GPIO.
> >
> > This also creates a common file as there might be other chips that use
> > the same binding and driver, then being a little more abstract could
> > help in the long run.
> >
> > Signed-off-by: Ryder Lee
> > ---
> > arch/arm/include/asm/arch-mediatek/gpio.h | 9 +
> > drivers/pinctrl/Kconfig | 1 +
> > drivers/pinctrl/Makefile | 1 +
> > drivers/pinctrl/mediatek/Kconfig | 11 +
> > drivers/pinctrl/mediatek/Makefile | 6 +
> > drivers/pinctrl/mediatek/pinctrl-mt7629.c | 488 +++
> > drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552
> > ++
> > drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +
> > 8 files changed, 1250 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
> > create mode 100644 drivers/pinctrl/mediatek/Kconfig
> > create mode 100644 drivers/pinctrl/mediatek/Makefile
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
> > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
> >
>
> [..]
>
> > +int mtk_pinctrl_probe(struct udevice *dev, struct mtk_pinctrl_soc *soc)
> > +{
> > + struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
> > + int ret;
> > +
> > + priv->base = dev_read_addr_ptr(dev);
> > + if (priv->base == (void *)FDT_ADDR_T_NONE)
> > + return -EINVAL;
> > +
> > + priv->soc = soc;
> > +
> > + ret = mtk_gpiochip_register(dev);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
>
> How come this function is exported? It should be probed like any other driver.
It makes no difference. We could reuse it for other MTK chips in this
way.
In pinctrl-mt7623.c (patch 11/18):
static int mtk_pinctrl_mt7623_probe(struct udevice *dev)
{
//common probed function
mtk_pinctrl_probe(dev, _data);
//proprietary operations for the chip
mt7623_bonding_disable(dev);
}
The similar usage is meson_pinctrl_probe() in pinctrl-meson.c
Ryder
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Re: [U-Boot] [PATCH v2 05/18] arm: MediaTek: add basic support for MT7623 boards
On Wed, 2018-10-24 at 21:29 -0600, Simon Glass wrote: > Hi, > > On 12 October 2018 at 01:00, Ryder Lee wrote: > > From: Weijie Gao > > > > This adds a general board file based on MT7623 SoCs from MediaTek. > > > > As this u-boot is loaded by preloader, there is no low level > > initializtion codes. > > > > Signed-off-by: Weijie Gao > > Signed-off-by: Ryder Lee > > Tested-by: Matthias Brugger > > --- > > arch/arm/mach-mediatek/Kconfig| 8 +++ > > arch/arm/mach-mediatek/Makefile | 1 + > > arch/arm/mach-mediatek/mt7623/Makefile| 4 ++ > > arch/arm/mach-mediatek/mt7623/init.c | 54 +++ > > arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++ > > arch/arm/mach-mediatek/mt7623/preloader.h | 99 > > +++ > > board/mediatek/mt7623/Kconfig | 13 > > board/mediatek/mt7623/MAINTAINERS | 7 ++ > > board/mediatek/mt7623/Makefile| 3 + > > board/mediatek/mt7623/mt7623_rfb.c| 16 + > > configs/mt7623n_bpir2_defconfig | 53 ++ > > include/configs/mt7623.h | 61 + > > 12 files changed, 341 insertions(+) > > create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile > > create mode 100644 arch/arm/mach-mediatek/mt7623/init.c > > create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S > > create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h > > create mode 100644 board/mediatek/mt7623/Kconfig > > create mode 100644 board/mediatek/mt7623/MAINTAINERS > > create mode 100644 board/mediatek/mt7623/Makefile > > create mode 100644 board/mediatek/mt7623/mt7623_rfb.c > > create mode 100644 configs/mt7623n_bpir2_defconfig > > create mode 100644 include/configs/mt7623.h > > > > There is a new SPL handoff and bloblist feature that I hope will land > in the next release. Can you please look at using this instead of an > SoC-specififc mechanism? > > See u-boot-dm/spl-working Okay, I will take a look at this. Ryder ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 11/18] pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
On Wed, 2018-10-24 at 21:29 -0600, Simon Glass wrote: > Hi Ryder, > > On 12 October 2018 at 01:01, Ryder Lee wrote: > > This patch adds pinctrl support for MT7623 SoC. And most of the > > structures are used to hold the hardware configuration for each > > pin. > > > > Signed-off-by: Ryder Lee > > Tested-by: Matthias Brugger > > --- > > drivers/pinctrl/mediatek/Kconfig |4 + > > drivers/pinctrl/mediatek/Makefile |1 + > > drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 > > + > > drivers/pinctrl/mediatek/pinctrl-mtk-common.h |1 + > > 4 files changed, 1290 insertions(+) > > create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c > > [..] > > > +void mtk_rmw(struct udevice *dev, u32 reg, u32 mask, u32 set); > > What is this for? It has no comment and is an exported function. We > should not export things from drivers unless there is a good reason. This is a common 'read-modify-write' helper. I think we could export it in this shared header? > Regards, > Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 06/18] clk: MediaTek: add clock driver for MT7629 SoC.
On Wed, 2018-10-24 at 21:29 -0600, Simon Glass wrote:
> Hi Ryder,
>
> On 12 October 2018 at 01:00, Ryder Lee wrote:
> > This patch adds clock modules for MediaTek SoCs:
> > - Shared part: a common driver which contains the general operations
> > for plls, muxes, dividers and gates so that we can reuse it in future.
> >
> > - Specific SoC part: the group of structures used to hold the hardware
> > configuration for each SoC.
> >
> > We take MT7629 as an example to demonstrate how to implement driver if
> > any other MediaTek chips would like to use it.
> >
> > Signed-off-by: Ryder Lee
> > ---
> > drivers/clk/Makefile | 1 +
> > drivers/clk/mediatek/Makefile | 6 +
> > drivers/clk/mediatek/clk-mt7629.c | 709
> > ++
> > drivers/clk/mediatek/clk-mtk.c| 492 ++
> > drivers/clk/mediatek/clk-mtk.h| 153
> > 5 files changed, 1361 insertions(+)
> > create mode 100644 drivers/clk/mediatek/Makefile
> > create mode 100644 drivers/clk/mediatek/clk-mt7629.c
> > create mode 100644 drivers/clk/mediatek/clk-mtk.c
> > create mode 100644 drivers/clk/mediatek/clk-mtk.h
>
> Looks good except for a few things below.
>
> [..]
>
> > +const struct clk_ops mtk_clk_gate_ops = {
> > + .enable = mtk_clk_gate_enable,
> > + .disable = mtk_clk_gate_disable,
> > + .get_rate = mtk_clk_gate_get_rate,
> > +};
> > +
> > +int mtk_clk_init(struct udevice *dev, const struct mtk_clk_tree *tree)
> > +{
> > + struct mtk_clk_priv *priv = dev_get_priv(dev);
> > +
> > + priv->base = dev_read_addr_ptr(dev);
> > + if (!priv->base)
> > + return -ENOENT;
>
> Why do you export these two functions? Devices should be probed in the
> normal DM way.
Yes, they are probed in the normal way. These functions are used by
several clock blocks and MTK SoCs. so I put the common parts here to
keep the code as clean as possible.
ex:
static int mt7629_apmixedsys_probe(struct udevice *dev)
{
...
ret = mtk_clk_init(...);
/* reduce clock square disable time */
writel(...);
...
}
static int mt7629_topckgen_probe(struct udevice *dev)
{
return mtk_clk_init(...);
}
> > +
> > + priv->tree = tree;
> > +
> > + return 0;
> > +}
> > +
> > +int mtk_clk_gate_init(struct udevice *dev,
> > + const struct mtk_clk_tree *tree,
> > + const struct mtk_gate *gates)
> > +{
> > + struct mtk_cg_priv *priv = dev_get_priv(dev);
> > +
> > + priv->base = dev_read_addr_ptr(dev);
> > + if (!priv->base)
> > + return -ENOENT;
> > +
> > + priv->tree = tree;
> > + priv->gates = gates;
> > +
> > + return 0;
> > +}
>
> [...]
>
> Regards,
> Simon
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Re: [U-Boot] [PATCH v2 04/18] arm: MediaTek: add basic support for MT7629 boards
On Wed, 2018-10-24 at 21:29 -0600, Simon Glass wrote: > Hi Ryder, > > On 12 October 2018 at 01:00, Ryder Lee wrote: > > This adds a general board file based on MT7629 SoCs from MediaTek. > > > > Apart from the generic parts (cpu) we add some low level init codes > > and initialize the early clocks. > > > > Signed-off-by: Ryder Lee > > Signed-off-by: Weijie Gao > > --- > > arch/arm/Kconfig | 14 +++ > > arch/arm/Makefile | 1 + > > arch/arm/include/asm/arch-mediatek/misc.h | 17 > > arch/arm/mach-mediatek/Kconfig| 24 + > > arch/arm/mach-mediatek/Makefile | 6 ++ > > arch/arm/mach-mediatek/cpu.c | 34 +++ > > arch/arm/mach-mediatek/init.h | 11 +++ > > arch/arm/mach-mediatek/mt7629/Makefile| 4 + > > arch/arm/mach-mediatek/mt7629/init.c | 131 > > ++ > > arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 ++ > > arch/arm/mach-mediatek/spl.c | 43 + > > board/mediatek/mt7629/Kconfig | 17 > > board/mediatek/mt7629/MAINTAINERS | 7 ++ > > board/mediatek/mt7629/Makefile| 3 + > > board/mediatek/mt7629/mt7629_rfb.c| 16 > > configs/mt7629_rfb_defconfig | 73 ++ > > include/configs/mt7629.h | 62 > > 17 files changed, 513 insertions(+) > > create mode 100644 arch/arm/include/asm/arch-mediatek/misc.h > > create mode 100644 arch/arm/mach-mediatek/Kconfig > > create mode 100644 arch/arm/mach-mediatek/Makefile > > create mode 100644 arch/arm/mach-mediatek/cpu.c > > create mode 100644 arch/arm/mach-mediatek/init.h > > create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile > > create mode 100644 arch/arm/mach-mediatek/mt7629/init.c > > create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S > > create mode 100644 arch/arm/mach-mediatek/spl.c > > create mode 100644 board/mediatek/mt7629/Kconfig > > create mode 100644 board/mediatek/mt7629/MAINTAINERS > > create mode 100644 board/mediatek/mt7629/Makefile > > create mode 100644 board/mediatek/mt7629/mt7629_rfb.c > > create mode 100644 configs/mt7629_rfb_defconfig > > create mode 100644 include/configs/mt7629.h > > Looks good. A few nits below > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > index ccf2a84..eac03f0 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -668,6 +668,18 @@ config ARCH_MESON > > targeted at media players and tablet computers. We currently > > support the S905 (GXBaby) 64-bit SoC. > > > > +config ARCH_MEDIATEK > > + bool "MediaTek SoCs" > > + select DM > > + select OF_CONTROL > > + select SPL_DM if SPL > > + select SPL_LIBCOMMON_SUPPORT if SPL > > + select SPL_LIBGENERIC_SUPPORT if SPL > > + select SPL_OF_CONTROL if SPL > > + select SUPPORT_SPL > > + help > > + Support for the MediaTek SoCs family. > > Please add more info. What type of SoCs are these? What are the > capabilities? Link to web site? datasheets? wiki? Or maybe point to a > doc/README.mediatek? > > > + > > config ARCH_MX8M > > bool "NXP i.MX8M platform" > > select ARM64 > > @@ -1423,6 +1435,8 @@ source "arch/arm/mach-rmobile/Kconfig" > > > > source "arch/arm/mach-meson/Kconfig" > > > > +source "arch/arm/mach-mediatek/Kconfig" > > + > > source "arch/arm/mach-qemu/Kconfig" > > > > source "arch/arm/mach-rockchip/Kconfig" > > diff --git a/arch/arm/Makefile b/arch/arm/Makefile > > index 8f50560..ddb9618 100644 > > --- a/arch/arm/Makefile > > +++ b/arch/arm/Makefile > > @@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3 > > machine-$(CONFIG_ARCH_KEYSTONE)+= keystone > > # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD > > machine-$(CONFIG_KIRKWOOD) += kirkwood > > +machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek > > machine-$(CONFIG_ARCH_MESON) += meson > > machine-$(CONFIG_ARCH_MVEBU) += mvebu > > # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA > > diff --git a/arch/arm/include/asm/arch-mediatek/misc.h > > b/arch/arm/include/asm/arch-mediatek/misc.h >
Re: [U-Boot] [PATCH v2 01/18] tools: MediaTek: add MTK boot header generation to mkimage
On Wed, 2018-10-24 at 21:29 -0600, Simon Glass wrote: > Hi Ryder, > > On 12 October 2018 at 01:00, Ryder Lee wrote: > > This patch adds support for MTK boot image generation. > > > > Signed-off-by: Weijie Gao > > Signed-off-by: Ryder Lee > > --- > > Makefile | 22 ++ > > common/image.c | 1 + > > include/image.h | 1 + > > scripts/Makefile.spl | 11 + > > tools/Makefile | 1 + > > tools/mtkimage.c | 749 > > +++ > > tools/mtkimage.h | 199 ++ > > 7 files changed, 984 insertions(+) > > create mode 100644 tools/mtkimage.c > > create mode 100644 tools/mtkimage.h > > The mkimage stuff looks fine. > > But can you use binman for the pad/cat part of this? See for example > sunxi. - sunxi-u-boot.dtsi > > Also mtkimage.c is too close to mkimage.c - how about mtk_image.c ? > This looks great. I will switch to use binman in v3. Thanks Ryder ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 01/18] tools: MediaTek: add MTK boot header generation to mkimage
On Sat, 2018-11-03 at 00:08 -0600, Simon Glass wrote: > On 2 November 2018 at 09:15, Ryder Lee wrote: > > This patch adds support for MTK boot image generation. > > > > Signed-off-by: Weijie Gao > > Signed-off-by: Ryder Lee > > --- > > Makefile | 20 ++ > > common/image.c | 1 + > > include/image.h | 1 + > > scripts/Makefile.spl | 11 + > > tools/Makefile | 1 + > > tools/mtk_image.c| 749 > > +++ > > tools/mtk_image.h| 199 ++ > > 7 files changed, 982 insertions(+) > > create mode 100644 tools/mtk_image.c > > create mode 100644 tools/mtk_image.h > > It would help to use patman so that we get a changelog on each patch. > > Reviewed-by: Simon Glass I forgot to add changelog on each patch. Sorry for the inconvenience. Ryder ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 14/18] serial: 16550: allow the driver to support MediaTek serial
On Mon, 2018-11-05 at 10:20 +0800, Ryder Lee wrote:
> On Sat, 2018-11-03 at 00:09 -0600, Simon Glass wrote:
> > Hi Ryder,
> >
> > On 2 November 2018 at 09:15, Ryder Lee wrote:
> > > This patch adds an extra operation in ns16550.c to suuport MediaTek
> > > SoCs as we have a highspeed register which influences the calcualtion
> > > of the divisor.
> > >
> > > Note that we don't support the baudrate greater than 115200 currently.
> > >
> > > Signed-off-by: Ryder Lee
> > > Tested-by: Matthias Brugger
> > > Reviewed-by: Simon Glass
> > > ---
> > > drivers/serial/ns16550.c | 10 ++
> > > 1 file changed, 10 insertions(+)
> >
> > Actually it seems to me that we should have a compatible string for
> > this and deal with this at run-time?
> >
> > Is that easy to do here?
> >
>
> How about this:
>
> uart0: serial@11002000 {
> compatible = "ns16550a";
>
> mediatek,highspeed = <0>;
>
>
> Ryder
>
Sorry, I didn't get it right. I will add a compatible string in
ns16550_serial_ids[] for MTK chips.
Ryder
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 06/18] clk: MediaTek: add clock driver for MT7629 SoC.
On Sat, 2018-11-03 at 00:08 -0600, Simon Glass wrote: > Hi Ryder, > > On 2 November 2018 at 09:15, Ryder Lee wrote: > > This patch adds clock modules for MediaTek SoCs: > > - Shared part: a common driver which contains the general operations > > for plls, muxes, dividers and gates so that we can reuse it in future. > > > > - Specific SoC part: the group of structures used to hold the hardware > > configuration for each SoC. > > > > We take MT7629 as an example to demonstrate how to implement driver if > > any other MediaTek chips would like to use it. > > > > Signed-off-by: Ryder Lee > > --- > > drivers/clk/Makefile | 1 + > > drivers/clk/mediatek/Makefile | 6 + > > drivers/clk/mediatek/clk-mt7629.c | 709 > > ++ > > drivers/clk/mediatek/clk-mtk.c| 492 ++ > > drivers/clk/mediatek/clk-mtk.h| 153 > > 5 files changed, 1361 insertions(+) > > create mode 100644 drivers/clk/mediatek/Makefile > > create mode 100644 drivers/clk/mediatek/clk-mt7629.c > > create mode 100644 drivers/clk/mediatek/clk-mtk.c > > create mode 100644 drivers/clk/mediatek/clk-mtk.h > > Please add coments to the structs and functions in the header file. > Also put a _common prefix on the functions that are called from other > files. > > Otherwise: > > Reviewed-by: Simon Glass > > Regards, > Simon Got it. I will send a new series soon. Ryder ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 10/18] pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee
---
arch/arm/include/asm/arch-mediatek/gpio.h | 9 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 11 +
drivers/pinctrl/mediatek/Makefile | 6 +
drivers/pinctrl/mediatek/pinctrl-mt7629.c | 471 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +
8 files changed, 1233 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h
b/arch/arm/include/asm/arch-mediatek/gpio.h
new file mode 100644
index 000..4ea1020
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_GPIO_H
+#define __MEDIATEK_GPIO_H
+
+#endif /* __MEDIATEK_GPIO_H */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8da..7e6fad3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -301,6 +301,7 @@ config ASPEED_AST2500_PINCTRL
endif
source "drivers/pinctrl/meson/Kconfig"
+source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d..293bad3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-$(CONFIG_PINCTRL_MTK) += mediatek/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 000..e0145b1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MEDIATEK
+
+config PINCTRL_MTK
+ depends on PINCTRL_GENERIC
+ bool
+
+config PINCTRL_MT7629
+ bool "MT7629 SoC pinctrl driver"
+ select PINCTRL_MTK
+
+endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 000..cbf0765
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
new file mode 100644
index 000..bf51486
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+
+#define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
+
+static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
+ PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
+ PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
+ PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
+ PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
+ PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
+ PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
+ PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
+ PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
+ PIN_FIELD(70,
[U-Boot] [PATCH v3 09/18] watchdog: MediaTek: add watchdog driver for MediaTek SoCs
This patch adds a common driver for the Mediatek SoC integrated
watchdog.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
drivers/watchdog/Kconfig | 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/mtk_wdt.c | 135 +
3 files changed, 144 insertions(+)
create mode 100644 drivers/watchdog/mtk_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 02f4e1e..b919ef6 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -103,6 +103,14 @@ config WDT_CDNS
Select this to enable Cadence watchdog timer, which can be found on
some
Xilinx Microzed Platform.
+config WDT_MTK
+ bool "MediaTek watchdog timer support"
+ depends on WDT && ARCH_MEDIATEK
+ help
+ Select this to enable watchdog timer for MediaTek SoCs.
+ The watchdog timer is stopped when initialized.
+ It performs full SoC reset.
+
config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 08406ca..04fa4a6 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o
+obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
new file mode 100644
index 000..0b50173
--- /dev/null
+++ b/drivers/watchdog/mtk_wdt.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Watchdog driver for MediaTek SoCs
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#define MTK_WDT_MODE 0x00
+#define MTK_WDT_LENGTH 0x04
+#define MTK_WDT_RESTART0x08
+#define MTK_WDT_STATUS 0x0c
+#define MTK_WDT_INTERVAL 0x10
+#define MTK_WDT_SWRST 0x14
+#define MTK_WDT_REQ_MODE 0x30
+#define MTK_WDT_DEBUG_CTL 0x40
+
+#define WDT_MODE_KEY (0x22 << 24)
+#define WDT_MODE_ENBIT(0)
+#define WDT_MODE_EXTPOLBIT(1)
+#define WDT_MODE_EXTEN BIT(2)
+#define WDT_MODE_IRQ_ENBIT(3)
+#define WDT_MODE_DUAL_EN BIT(6)
+
+#define WDT_LENGTH_KEY 0x8
+#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
+
+#define WDT_RESTART_KEY0x1971
+#define WDT_SWRST_KEY 0x1209
+
+struct mtk_wdt_priv {
+ void __iomem *base;
+};
+
+static int mtk_wdt_reset(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Reload watchdog duration */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ return 0;
+}
+
+static int mtk_wdt_stop(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
+
+ return 0;
+}
+
+static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Kick watchdog to prevent counter == 0 */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ /* Reset */
+ writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
+ hang();
+
+ return 0;
+}
+
+static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /*
+* One bit is the value of 512 ticks
+* The clock has 32 KHz
+*/
+ timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
+ writel(timeout, priv->base + MTK_WDT_LENGTH);
+
+ mtk_wdt_reset(dev);
+}
+
+static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ mtk_wdt_set_timeout(dev, timeout);
+
+ /* Enable watchdog reset signal */
+ setbits_le32(priv->base + MTK_WDT_MODE,
+WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
+
+ return 0;
+}
+
+static int mtk_wdt_probe(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ /* Clear status */
+ clrsetbits_le32(priv->base + MTK_WDT_MODE,
+ WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
+
+ return mtk_wdt_stop(dev);
+}
+
+static const struct wdt_ops mtk_wdt_ops = {
+ .start = mtk_wdt_start,
+ .reset = mtk_wdt_reset,
+ .stop = mtk_wdt_stop,
+ .expire_no
[U-Boot] [PATCH v3 04/18] arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. Signed-off-by: Ryder Lee Signed-off-by: Weijie Gao --- arch/arm/Kconfig | 16 arch/arm/Makefile | 1 + arch/arm/include/asm/arch-mediatek/misc.h | 17 arch/arm/mach-mediatek/Kconfig| 26 ++ arch/arm/mach-mediatek/Makefile | 6 ++ arch/arm/mach-mediatek/cpu.c | 34 +++ arch/arm/mach-mediatek/init.h | 11 +++ arch/arm/mach-mediatek/mt7629/Makefile| 4 + arch/arm/mach-mediatek/mt7629/init.c | 128 ++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 ++ arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7629/Kconfig | 17 board/mediatek/mt7629/MAINTAINERS | 7 ++ board/mediatek/mt7629/Makefile| 3 + board/mediatek/mt7629/mt7629_rfb.c| 11 +++ configs/mt7629_rfb_defconfig | 73 +++ include/configs/mt7629.h | 60 17 files changed, 507 insertions(+) create mode 100644 arch/arm/include/asm/arch-mediatek/misc.h create mode 100644 arch/arm/mach-mediatek/Kconfig create mode 100644 arch/arm/mach-mediatek/Makefile create mode 100644 arch/arm/mach-mediatek/cpu.c create mode 100644 arch/arm/mach-mediatek/init.h create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile create mode 100644 arch/arm/mach-mediatek/mt7629/init.c create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/spl.c create mode 100644 board/mediatek/mt7629/Kconfig create mode 100644 board/mediatek/mt7629/MAINTAINERS create mode 100644 board/mediatek/mt7629/Makefile create mode 100644 board/mediatek/mt7629/mt7629_rfb.c create mode 100644 configs/mt7629_rfb_defconfig create mode 100644 include/configs/mt7629.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 326d5c0..5f3d29b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -658,6 +658,20 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MEDIATEK + bool "MediaTek SoCs" + select BINMAN + select DM + select OF_CONTROL + select SPL_DM if SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL + select SPL_OF_CONTROL if SPL + select SUPPORT_SPL + help + Support for the MediaTek SoCs family developed by MediaTek Inc. + Please refer to doc/README.mediatek for more information. + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -1442,6 +1456,8 @@ source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-mediatek/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b6c5e1..c38ef3c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE)+= keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h new file mode 100644 index 000..2530e78 --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/misc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_MISC_H_ +#define __MEDIATEK_MISC_H_ + +#define VER_BASE 0x0800 +#define VER_SIZE 0x10 + +#define APHW_CODE 0x00 +#define APHW_SUBCODE 0x04 +#define APHW_VER 0x08 +#define APSW_VER 0x0c + +#endif /* __MEDIATEK_MISC_H_ */ diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 000..d2ada97 --- /dev/null +++ b/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,26 @@ +if ARCH_MEDIATEK + +config SYS_SOC + default "mediatek" + +config SYS_VENDOR + default "mediatek" + +choice + prompt "MediaTek board select" + +config TARGET_MT7629 + bool "MediaTek MT7629 SoC" + select CPU_V7A + select SPL + select ARCH_MISC_INIT + help + The MediaTek MT7629 is a
[U-Boot] [PATCH v3 01/18] tools: MediaTek: add MTK boot header generation to mkimage
This patch adds support for MTK boot image generation.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
---
Makefile | 20 ++
common/image.c | 1 +
include/image.h | 1 +
scripts/Makefile.spl | 11 +
tools/Makefile | 1 +
tools/mtk_image.c| 749 +++
tools/mtk_image.h| 199 ++
7 files changed, 982 insertions(+)
create mode 100644 tools/mtk_image.c
create mode 100644 tools/mtk_image.h
diff --git a/Makefile b/Makefile
index 250eb6c..5a384c8 100644
--- a/Makefile
+++ b/Makefile
@@ -852,6 +852,8 @@ ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin
endif
+ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
+
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
@@ -1359,6 +1361,24 @@ u-boot.elf: u-boot.bin
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+# MediaTek's ARM-based u-boot needs a header to contains its load address
+# which is parsed by the BootROM.
+# If the SPL build is enabled, the header will be added to the spl binary,
+# and the spl binary and the u-boot.img will be combined into one file.
+# Otherwise the header will be added to the u-boot.bin directly.
+
+ifeq ($(CONFIG_SPL),y)
+u-boot-mtk.bin: u-boot.dtb u-boot.img spl/u-boot-spl-mtk.bin FORCE
+ $(call if_changed,binman)
+else
+MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+u-boot-mtk.bin: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+endif
+
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
diff --git a/common/image.c b/common/image.c
index 1c3a772..d3f9914 100644
--- a/common/image.c
+++ b/common/image.c
@@ -166,6 +166,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT"
},
{ IH_TYPE_PMMC,"pmmc","TI Power Management
Micro-Controller Firmware",},
{ IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32
Image" },
+ { IH_TYPE_MTKIMAGE, "mtk_image", "MeidaTek BootROM loadable
Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 031c355..8dd7247 100644
--- a/include/image.h
+++ b/include/image.h
@@ -278,6 +278,7 @@ enum {
IH_TYPE_PMMC,/* TI Power Management Micro-Controller
Firmware */
IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
IH_TYPE_SOCFPGAIMAGE_V1,/* Altera SOCFPGA A10 Preloader */
+ IH_TYPE_MTKIMAGE, /* MeidaTek BootROM loadable Image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7416abe..22bd8f7 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -219,6 +219,8 @@ ALL-$(CONFIG_SPL_X86_16BIT_INIT) +=
$(obj)/u-boot-x86-16bit-spl.bin
ALL-$(CONFIG_ARCH_ZYNQ)+= $(obj)/boot.bin
ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_MEDIATEK)+= $(obj)/u-boot-spl-mtk.bin
+
all: $(ALL-y)
quiet_cmd_cat = CAT $@
@@ -349,6 +351,15 @@ cmd_sunxi_spl_image_builder =
$(objtree)/tools/sunxi-spl-image-builder \
$(obj)/sunxi-spl-with-ecc.bin: $(obj)/sunxi-spl.bin
$(call if_changed,sunxi_spl_image_builder)
+
+# MediaTek's specific SPL build
+MKIMAGEFLAGS_u-boot-spl-mtk.bin = -T mtk_image \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+$(obj)/u-boot-spl-mtk.bin: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
# Rule to link u-boot-spl
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot-spl ?= LD $@
diff --git a/tools/Makefile b/tools/Makefile
index 3c0521f..c93d17a 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -116,6 +116,7 @@ dumpimage-mkimage-objs := aisimage.o \
$(LIBFDT_OBJS) \
gpimage.o \
gpimage-common.o \
+ mtk_image.o \
$(RSA_OBJS-y)
dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
new file mode 100644
index 000..900a293
--- /dev/null
+++ b/tools/mtk_image.c
@@ -0,0 +1,749 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generate MediaTek BootROM header for SPL/U-Boot images
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Wei
[U-Boot] [PATCH v3 02/18] arm: dts: MediaTek: add device tree for MT7629
This patch adds MT7629 device tree and the includes it needs.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
arch/arm/dts/Makefile| 3 +
arch/arm/dts/mt7629-rfb-u-boot.dtsi | 24 +++
arch/arm/dts/mt7629-rfb.dts | 70 +
arch/arm/dts/mt7629.dtsi | 244 +++
include/dt-bindings/clock/mt7629-clk.h | 206 ++
include/dt-bindings/power/mt7629-power.h | 13 ++
6 files changed, 560 insertions(+)
create mode 100644 arch/arm/dts/mt7629-rfb-u-boot.dtsi
create mode 100644 arch/arm/dts/mt7629-rfb.dts
create mode 100644 arch/arm/dts/mt7629.dtsi
create mode 100644 include/dt-bindings/clock/mt7629-clk.h
create mode 100644 include/dt-bindings/power/mt7629-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d36447d..2001e63 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -558,6 +558,9 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7629-rfb.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi
b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
new file mode 100644
index 000..1ef5568
--- /dev/null
+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+/ {
+ binman {
+ filename = "u-boot-mtk.bin";
+ pad-byte = <0xff>;
+
+#ifdef CONFIG_SPL
+ blob {
+ filename = "spl/u-boot-spl-mtk.bin";
+ size = ;
+ };
+
+ u-boot-img {
+ };
+#endif
+ };
+};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
new file mode 100644
index 000..a6d28a0
--- /dev/null
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7629.dtsi"
+
+/ {
+ model = "MediaTek MT7629 RFB";
+ compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
+
+ aliases {
+ spi0 =
+ };
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+};
+
+ {
+ qspi_pins: qspi-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0-default {
+ mux {
+ function = "uart";
+ groups = "uart0_txd_rxd";
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "spi-flash";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
new file mode 100644
index 000..f7966cb
--- /dev/null
+++ b/arch/arm/dts/mt7629.dtsi
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7629";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <125000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clock-frequency = <125000>;
+ };
+ };
+
+ clk20m: oscillator@0 {
+ compatible = "fixed-clo
[U-Boot] [PATCH v3 06/18] clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee
---
drivers/clk/Makefile | 1 +
drivers/clk/mediatek/Makefile | 6 +
drivers/clk/mediatek/clk-mt7629.c | 709 ++
drivers/clk/mediatek/clk-mtk.c| 492 ++
drivers/clk/mediatek/clk-mtk.h| 153
5 files changed, 1361 insertions(+)
create mode 100644 drivers/clk/mediatek/Makefile
create mode 100644 drivers/clk/mediatek/clk-mt7629.c
create mode 100644 drivers/clk/mediatek/clk-mtk.c
create mode 100644 drivers/clk/mediatek/clk-mtk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 821b586..c128538 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
new file mode 100644
index 000..297f99d
--- /dev/null
+++ b/drivers/clk/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
+
+# SoC Drivers
+obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk/mediatek/clk-mt7629.c
new file mode 100644
index 000..46e9fad
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7629_CLKSQ_STB_CON0 0x20
+#define MT7629_PLL_ISO_CON00x2c
+#define MT7629_PLL_FMAX(2500UL * MHZ)
+#define MT7629_CON0_RST_BARBIT(24)
+
+#define MCU_AXI_DIV0x640
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX0x7c0
+#define MCU_BUS_MSKGENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7629_CON0_RST_BAR,\
+ .fmax = MT7629_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 3125),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 3125),
+ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 12500),
+
[U-Boot] [PATCH v3 03/18] arm: dts: MediaTek: add device tree for MT7623
This adds device tree for MT7623 development board - Bananapi R2
Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/mt7623.dtsi | 255 +++
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207
include/dt-bindings/clock/mt7623-clk.h | 413 +++
include/dt-bindings/power/mt7623-power.h | 19 ++
5 files changed, 895 insertions(+)
create mode 100644 arch/arm/dts/mt7623.dtsi
create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
create mode 100644 include/dt-bindings/clock/mt7623-clk.h
create mode 100644 include/dt-bindings/power/mt7623-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2001e63..4b30ef9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -559,6 +559,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
new file mode 100644
index 000..3be5b6a
--- /dev/null
+++ b/arch/arm/dts/mt7623.dtsi
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7623";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <1300>;
+ #clock-cells = <0>;
+ };
+
+ rtc32k: oscillator-1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
+ };
+
+ clk26m: oscillator-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ clock-output-names = "clk26m";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ topckgen: clock-controller@1000 {
+ compatible
[U-Boot] [PATCH v3 05/18] arm: MediaTek: add basic support for MT7623 boards
From: Weijie Gao
This adds a general board file based on MT7623 SoCs from MediaTek.
As this u-boot is loaded by MTK proprietary preloader, there is no
low level initializtion codes.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
arch/arm/mach-mediatek/Kconfig| 13
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7623/Makefile| 4 ++
arch/arm/mach-mediatek/mt7623/init.c | 54 +++
arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++
arch/arm/mach-mediatek/mt7623/preloader.h | 99 +++
board/mediatek/mt7623/Kconfig | 13
board/mediatek/mt7623/MAINTAINERS | 7 ++
board/mediatek/mt7623/Makefile| 3 +
board/mediatek/mt7623/mt7623_rfb.c| 11 +++
configs/mt7623n_bpir2_defconfig | 54 +++
include/configs/mt7623.h | 59
12 files changed, 340 insertions(+)
create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7623/init.c
create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S
create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h
create mode 100644 board/mediatek/mt7623/Kconfig
create mode 100644 board/mediatek/mt7623/MAINTAINERS
create mode 100644 board/mediatek/mt7623/Makefile
create mode 100644 board/mediatek/mt7623/mt7623_rfb.c
create mode 100644 configs/mt7623n_bpir2_defconfig
create mode 100644 include/configs/mt7623.h
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index d2ada97..7a733e9 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -9,6 +9,18 @@ config SYS_VENDOR
choice
prompt "MediaTek board select"
+config TARGET_MT7623
+ bool "MediaTek MT7623 SoC"
+ select CPU_V7A
+ select ARCH_MISC_INIT
+ help
+ The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
+ including NEON and GPU, Mali-450 graphics, several DDR3 options,
+ crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
+ video interfaces supporting HDMI and MIPI, and video codec support.
+ Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
+ I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
+
config TARGET_MT7629
bool "MediaTek MT7629 SoC"
select CPU_V7A
@@ -21,6 +33,7 @@ config TARGET_MT7629
endchoice
+source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 852d330..b5d3a37 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,4 +3,5 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
+obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
diff --git a/arch/arm/mach-mediatek/mt7623/Makefile
b/arch/arm/mach-mediatek/mt7623/Makefile
new file mode 100644
index 000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7623/init.c
b/arch/arm/mach-mediatek/mt7623/init.c
new file mode 100644
index 000..0ee8c66
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/init.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "preloader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct boot_argument *preloader_param;
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ u32 i;
+
+ if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ ((size_t)preloader_param % sizeof(size_t) == 0) &&
+ preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
+ preloader_param->dram_rank_num <=
+ ARRAY_SIZE(preloader_param->dram_rank_size)) {
+ gd->ram_size = 0;
+
+ for (i = 0; i < preloader_param->dram_rank_num; i++)
+ gd->ram_size += preloader_param->dram_rank_size[i];
+ } else {
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ SZ_2G);
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ void __iomem *chipid;
+ u32 swver;
+
+ chipid = ioremap(VER_BASE, VER_SIZE);
+ swver = readl(chipid + APSW_VER);
+
+ printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1);
+
+ return 0;
+}
diff --git a/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
new file mod
[U-Boot] [PATCH v3 07/18] clk: MediaTek: add clock driver for MT7623 SoC.
This patch adds a driver for MT7623 clock blocks.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7623.c | 870 ++
2 files changed, 871 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7623.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 297f99d..0632dc8 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7623.c
b/drivers/clk/mediatek/clk-mt7623.c
new file mode 100644
index 000..ac4450e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7623 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7623_CLKSQ_STB_CON0 0x18
+#define MT7623_PLL_ISO_CON00x24
+#define MT7623_PLL_FMAX(2000UL * MHZ)
+#define MT7623_CON0_RST_BARBIT(27)
+
+#define MCU_AXI_DIV0x60
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7623_CON0_RST_BAR,\
+ .fmax = MT7623_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x8001, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf001, HAVE_RST_BAR,
+ 21, 0x210, 4, 0x214, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf301, HAVE_RST_BAR,
+ 7, 0x220, 4, 0x224, 14),
+ PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x0001, 0,
+ 21, 0x230, 4, 0x234, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x0001, 0,
+ 21, 0x240, 4, 0x244, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x0001, 0,
+ 21, 0x250, 4, 0x254, 0),
+ PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x0001, 0,
+ 31, 0x270, 4, 0x274, 0),
+ PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x0001, 0,
+ 31, 0x280, 4, 0x284, 0),
+ PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x0001, 0,
+ 31, 0x290, 4, 0x294, 0),
+ PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x0001, 0,
+ 31, 0x2a0, 4, 0x2a4, 0),
+ PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x0001, 0,
+ 31, 0x2b0, 4, 0x2b4, 0),
+ PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x0001, 0,
+ 31, 0x2c0, 4, 0x2c4, 0),
+ PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x0001, 0,
+ 21, 0x2d0, 4, 0x2d4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
+ FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
+ FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
+ FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
+ FIXED_CLK(CLK_TOP_32K_EXTERNAL
[U-Boot] [PATCH v3 00/18] Add U-Boot support for MediaTek SoCs - MT7623n & MT7629
Hello, This is the new round to add U-Boot support for MediaTek SoCs - MT7623n & MT7629, and the most of the drivers are based on mainline Linux, such as clock, timer, mmc, pinctrl, watchdog, power domain and device tree. Current implementation was validated via the FIT image. Thanks, Ryder Ryder Lee (16): tools: MediaTek: add MTK boot header generation to mkimage arm: dts: MediaTek: add device tree for MT7629 arm: dts: MediaTek: add device tree for MT7623 arm: MediaTek: add basic support for MT7629 boards clk: MediaTek: add clock driver for MT7629 SoC. clk: MediaTek: add clock driver for MT7623 SoC. timer: MediaTek: add timer driver for MediaTek SoCs watchdog: MediaTek: add watchdog driver for MediaTek SoCs pinctrl: MediaTek: add pinctrl driver for MT7629 SoC pinctrl: MediaTek: add pinctrl driver for MT7623 SoC power domain: MediaTek: add power domain driver for MT7629 SoC power domain: MediaTek: add power domain driver for MT7623 SoC serial: 16550: allow the driver to support MediaTek serial ram: MediaTek: add DDR3 driver for MT7629 SoC doc: README.mediatek: Add a simple README for MediaTek MAINTAINERS: add an entry for MediaTek Weijie Gao (2): arm: MediaTek: add basic support for MT7623 boards mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC MAINTAINERS | 20 + Makefile | 20 + arch/arm/Kconfig | 16 + arch/arm/Makefile |1 + arch/arm/dts/Makefile |4 + arch/arm/dts/mt7623.dtsi | 255 + arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 arch/arm/dts/mt7629-rfb-u-boot.dtsi | 24 + arch/arm/dts/mt7629-rfb.dts | 70 ++ arch/arm/dts/mt7629.dtsi | 244 + arch/arm/include/asm/arch-mediatek/gpio.h |9 + arch/arm/include/asm/arch-mediatek/misc.h | 17 + arch/arm/mach-mediatek/Kconfig| 39 + arch/arm/mach-mediatek/Makefile |7 + arch/arm/mach-mediatek/cpu.c | 34 + arch/arm/mach-mediatek/init.h | 11 + arch/arm/mach-mediatek/mt7623/Makefile|4 + arch/arm/mach-mediatek/mt7623/init.c | 54 + arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 + arch/arm/mach-mediatek/mt7623/preloader.h | 99 ++ arch/arm/mach-mediatek/mt7629/Makefile|4 + arch/arm/mach-mediatek/mt7629/init.c | 128 +++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 + arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7623/Kconfig | 13 + board/mediatek/mt7623/MAINTAINERS |7 + board/mediatek/mt7623/Makefile|3 + board/mediatek/mt7623/mt7623_rfb.c| 11 + board/mediatek/mt7629/Kconfig | 17 + board/mediatek/mt7629/MAINTAINERS |7 + board/mediatek/mt7629/Makefile|3 + board/mediatek/mt7629/mt7629_rfb.c| 11 + common/image.c|1 + configs/mt7623n_bpir2_defconfig | 54 + configs/mt7629_rfb_defconfig | 73 ++ doc/README.mediatek | 54 + drivers/clk/Makefile |1 + drivers/clk/mediatek/Makefile |7 + drivers/clk/mediatek/clk-mt7623.c | 870 +++ drivers/clk/mediatek/clk-mt7629.c | 709 + drivers/clk/mediatek/clk-mtk.c| 492 + drivers/clk/mediatek/clk-mtk.h| 153 +++ drivers/mmc/Kconfig | 11 + drivers/mmc/Makefile |1 + drivers/mmc/mtk-sd.c | 1394 + drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/mediatek/Kconfig | 15 + drivers/pinctrl/mediatek/Makefile |7 + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +++ drivers/pinctrl/mediatek/pinctrl-mt7629.c | 471 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552 ++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 183 drivers/power/domain/Kconfig |7 + drivers/power/domain/Makefile |1 + drivers/power/domain/mtk-power-domain.c | 406 +++ drivers/ram/Makefile |1 + drivers/ram/mediatek/Makefile |7 + drivers/ram/mediatek/ddr3-mt7629.c| 766 ++ drivers/serial/ns16550.c | 10 + drivers/timer/Kconfig |7 + drivers/timer/Makefile|1 + drivers/timer/mtk_timer.c | 85 ++ dri
[U-Boot] [PATCH v3 12/18] power domain: MediaTek: add power domain driver for MT7629 SoC
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
drivers/power/domain/Kconfig| 7 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/mtk-power-domain.c | 326
3 files changed, 334 insertions(+)
create mode 100644 drivers/power/domain/mtk-power-domain.c
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a08b428..93deaef 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -23,6 +23,13 @@ config IMX8_POWER_DOMAIN
Enable support for manipulating NXP i.MX8 on-SoC power domains via
IPC
requests to the SCU.
+config MTK_POWER_DOMAIN
+ bool "Enable the MediaTek power domain driver"
+ depends on POWER_DOMAIN && ARCH_MEDIATEK
+ help
+ Enable support for manipulating MediaTek power domains via MMIO
+ mapped registers.
+
config MESON_GX_VPU_POWER_DOMAIN
bool "Enable Amlogic Meson GX VPU power domain driver"
depends on ARCH_MESON
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index b08d18f..695aafe 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o
+obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
new file mode 100644
index 000..ed4a718
--- /dev/null
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define SPM_EN (0xb16 << 16 | 0x1)
+#define SPM_ETHSYS_PWR_CON 0x2e0
+#define SPM_HIF0_PWR_CON 0x2e4
+#define SPM_HIF1_PWR_CON 0x2e8
+#define SPM_PWR_STATUS 0x60c
+#define SPM_PWR_STATUS_2ND 0x610
+
+#define PWR_RST_B_BIT BIT(0)
+#define PWR_ISO_BITBIT(1)
+#define PWR_ON_BIT BIT(2)
+#define PWR_ON_2ND_BIT BIT(3)
+#define PWR_CLK_DIS_BITBIT(4)
+
+#define PWR_STATUS_ETHSYS BIT(24)
+#define PWR_STATUS_HIF0BIT(25)
+#define PWR_STATUS_HIF1BIT(26)
+
+/* Infrasys configuration */
+#define INFRA_TOPDCM_CTRL 0x10
+#define INFRA_TOPAXI_PROT_EN 0x220
+#define INFRA_TOPAXI_PROT_STA1 0x228
+
+#define DCM_TOP_EN BIT(0)
+
+enum scp_domain_type {
+ SCPSYS_MT7629,
+};
+
+struct scp_domain;
+
+struct scp_domain_data {
+ struct scp_domain *scpd;
+ u32 sta_mask;
+ int ctl_offs;
+ u32 sram_pdn_bits;
+ u32 sram_pdn_ack_bits;
+ u32 bus_prot_mask;
+};
+
+struct scp_domain {
+ void __iomem *base;
+ void __iomem *infracfg;
+ enum scp_domain_type type;
+ struct scp_domain_data *data;
+};
+
+static struct scp_domain_data scp_domain_mt7629[] = {
+ [MT7629_POWER_DOMAIN_ETHSYS] = {
+ .sta_mask = PWR_STATUS_ETHSYS,
+ .ctl_offs = SPM_ETHSYS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = (BIT(3) | BIT(17)),
+ },
+ [MT7629_POWER_DOMAIN_HIF0] = {
+ .sta_mask = PWR_STATUS_HIF0,
+ .ctl_offs = SPM_HIF0_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(25, 24),
+ },
+ [MT7629_POWER_DOMAIN_HIF1] = {
+ .sta_mask = PWR_STATUS_HIF1,
+ .ctl_offs = SPM_HIF1_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(28, 26),
+ },
+};
+
+/**
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hang when some unit accesses the
+ * bus while in power down.
+ */
+static int mtk_infracfg_set_bus_protection(void __iomem *infracfg,
+
[U-Boot] [PATCH v3 14/18] serial: 16550: allow the driver to support MediaTek serial
This patch adds an extra operation in ns16550.c to suuport MediaTek
SoCs as we have a highspeed register which influences the calcualtion
of the divisor.
Note that we don't support the baudrate greater than 115200 currently.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
drivers/serial/ns16550.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index f9041aa..f5410af 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -148,6 +148,13 @@ int ns16550_calc_divisor(NS16550_t port, int clock, int
baudrate)
static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
{
+#ifdef CONFIG_ARCH_MEDIATEK
+ /*
+* MediaTek UARTs has an extra highspeed register.
+* We need to clear it if baudrate <= 115200.
+*/
+ serial_out(0, _port->reg9);
+#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, _port->lcr);
serial_out(baud_divisor & 0xff, _port->dll);
serial_out((baud_divisor >> 8) & 0xff, _port->dlm);
@@ -261,6 +268,9 @@ static inline void _debug_uart_init(void)
serial_dout(_port->mcr, UART_MCRVAL);
serial_dout(_port->fcr, UART_FCR_DEFVAL);
+#ifdef CONFIG_ARCH_MEDIATEK
+ serial_dout(_port->reg9, 0);
+#endif
serial_dout(_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
serial_dout(_port->dll, baud_divisor & 0xff);
serial_dout(_port->dlm, (baud_divisor >> 8) & 0xff);
--
1.9.1
___
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U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 11/18] pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/pinctrl/mediatek/Kconfig |4 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.h |1 +
4 files changed, 1290 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index e0145b1..1bd9a92 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -4,6 +4,10 @@ config PINCTRL_MTK
depends on PINCTRL_GENERIC
bool
+config PINCTRL_MT7623
+ bool "MT7623 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index cbf0765..f6ef362 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
new file mode 100644
index 000..6fa3e2b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -0,0 +1,1284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_BOND_REG0 0xb10
+#define PIN_BOND_REG1 0xf20
+#define PIN_BOND_REG2 0xef0
+#define BOND_PCIE_CLR (0x77 << 3)
+#define BOND_I2S_CLR 0x3
+#define BOND_MSDC0E_CLR0x1
+
+#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 15, false)
+
+#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, true)
+
+static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
+ PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
+ PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
+ PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
+ PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
+ PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
+ PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
+ PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
+ PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
+ PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
+ PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
+ PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
+ PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
+ PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
+ PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
+ PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
+ PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
+ PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
+ PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
+ PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
+ PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
+ PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
+ PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
+ PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
+ PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
+ PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
+ PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
+ PINS_FIELD16(118, 121, 0xce0, 0
[U-Boot] [PATCH v3 08/18] timer: MediaTek: add timer driver for MediaTek SoCs
This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
drivers/timer/Kconfig | 7
drivers/timer/Makefile| 1 +
drivers/timer/mtk_timer.c | 85 +++
3 files changed, 93 insertions(+)
create mode 100644 drivers/timer/mtk_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index d012cf7..229c3a2 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -160,4 +160,11 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
+config MTK_TIMER
+ bool "MediaTek timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ MediaTek devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 7f19c49..c4fbab2 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
new file mode 100644
index 000..b5e76bd
--- /dev/null
+++ b/drivers/timer/mtk_timer.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek timer driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_GPT4_CTRL 0x40
+#define MTK_GPT4_CLK 0x44
+#define MTK_GPT4_CNT 0x48
+
+#define GPT4_ENABLEBIT(0)
+#define GPT4_CLEAR BIT(1)
+#define GPT4_FREERUN GENMASK(5, 4)
+#define GPT4_CLK_SYS 0x0
+#define GPT4_CLK_DIV1 0x0
+
+struct mtk_timer_priv {
+ void __iomem *base;
+};
+
+static int mtk_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ u32 val = readl(priv->base + MTK_GPT4_CNT);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int mtk_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk, parent;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 1, );
+ if (!ret) {
+ ret = clk_set_parent(, );
+ if (ret)
+ return ret;
+ }
+
+ uc_priv->clock_rate = clk_get_rate();
+ if (!uc_priv->clock_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct timer_ops mtk_timer_ops = {
+ .get_count = mtk_timer_get_count,
+};
+
+static const struct udevice_id mtk_timer_ids[] = {
+ { .compatible = "mediatek,timer" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_timer) = {
+ .name = "mtk_timer",
+ .id = UCLASS_TIMER,
+ .of_match = mtk_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct mtk_timer_priv),
+ .probe = mtk_timer_probe,
+ .ops = _timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
1.9.1
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[U-Boot] [PATCH v3 18/18] MAINTAINERS: add an entry for MediaTek
This patch adds an entry for MediaTek. Signed-off-by: Ryder Lee Reviewed-by: Simon Glass --- MAINTAINERS | 20 1 file changed, 20 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf8f73f..9940200 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,26 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM MEDIATEK +M: Ryder Lee +M: Weijie Gao +S: Maintained +F: arch/arm/mach-mediatek/ +F: arch/arm/include/asm/arch-mediatek/ +F: board/mediatek/ +F: doc/README.mediatek +F: drivers/clk/mediatek/ +F: drivers/mmc/mtk-sd.c +F: drivers/pinctrl/mediatek/ +F: drivers/power/domain/mtk-power-domain.c +F: drivers/ram/mediatek/ +F: drivers/spi/mtk_qspi.c +F: drivers/timer/mtk_timer.c +F: drivers/watchdog/mtk_wdt.c +F: tools/mtk_image.c +F: tools/mtk_image.h +N: mediatek + ARM OWL M: Manivannan Sadhasivam S: Maintained -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 13/18] power domain: MediaTek: add power domain driver for MT7623 SoC
This adds power domain (scpsys) support for MT7623 SoC.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
drivers/power/domain/mtk-power-domain.c | 80 +
1 file changed, 80 insertions(+)
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
index ed4a718..c67e880 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -14,9 +14,19 @@
#include
#include
+#include
#include
#define SPM_EN (0xb16 << 16 | 0x1)
+#define SPM_VDE_PWR_CON0x0210
+#define SPM_MFG_PWR_CON0x0214
+#define SPM_ISP_PWR_CON0x0238
+#define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON 0x0280
+#define SPM_BDP_PWR_CON0x029c
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
#define SPM_ETHSYS_PWR_CON 0x2e0
#define SPM_HIF0_PWR_CON 0x2e4
#define SPM_HIF1_PWR_CON 0x2e8
@@ -29,6 +39,15 @@
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BITBIT(4)
+#define PWR_STATUS_CONNBIT(1)
+#define PWR_STATUS_DISPBIT(3)
+#define PWR_STATUS_MFG BIT(4)
+#define PWR_STATUS_ISP BIT(5)
+#define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
#define PWR_STATUS_ETHSYS BIT(24)
#define PWR_STATUS_HIF0BIT(25)
#define PWR_STATUS_HIF1BIT(26)
@@ -41,6 +60,7 @@
#define DCM_TOP_EN BIT(0)
enum scp_domain_type {
+ SCPSYS_MT7623,
SCPSYS_MT7629,
};
@@ -62,6 +82,59 @@ struct scp_domain {
struct scp_domain_data *data;
};
+static struct scp_domain_data scp_domain_mt7623[] = {
+ [MT7623_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .bus_prot_mask = BIT(8) | BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_DISP] = {
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .bus_prot_mask = BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_MFG] = {
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_VDEC] = {
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_ISP] = {
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ },
+ [MT7623_POWER_DOMAIN_BDP] = {
+ .sta_mask = PWR_STATUS_BDP,
+ .ctl_offs = SPM_BDP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ },
+ [MT7623_POWER_DOMAIN_ETH] = {
+ .sta_mask = PWR_STATUS_ETH,
+ .ctl_offs = SPM_ETH_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_HIF] = {
+ .sta_mask = PWR_STATUS_HIF,
+ .ctl_offs = SPM_HIF_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_IFR_MSC] = {
+ .sta_mask = PWR_STATUS_IFR_MSC,
+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
+ },
+};
+
static struct scp_domain_data scp_domain_mt7629[] = {
[MT7629_POWER_DOMAIN_ETHSYS] = {
.sta_mask = PWR_STATUS_ETHSYS,
@@ -252,6 +325,9 @@ static int mtk_power_domain_hook(struct udevice *dev)
scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
switch (scpd->type) {
+ case SCPSYS_MT7623:
+ scpd->data = scp_domain_mt7623;
+ break;
case SCPSYS_MT7629:
scpd->data = scp_domain_mt7629;
break;
@@ -303,6 +379,10 @@ static int mtk_power_domain_probe(struct udevice *dev)
static const struct udevice_id mtk_power_domain_ids[] = {
{
+ .compatible = "mediatek,mt7623-scpsys",
+ .data = SCPSYS_MT7623,
+ },
+ {
.compatible = "mediatek,mt7629-scpsys",
.data = SCPSYS_MT7629,
},
--
1.9.1
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[U-Boot] [PATCH v3 16/18] mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC
From: Weijie Gao This patch adds MT7623 host controller driver for accessing SD/MMC. Cc: Jaehoon Chung Signed-off-by: Weijie Gao Signed-off-by: Ryder Lee Tested-by: Matthias Brugger Reviewed-by: Simon Glass --- drivers/mmc/Kconfig | 11 + drivers/mmc/Makefile |1 + drivers/mmc/mtk-sd.c | 1394 ++ 3 files changed, 1406 insertions(+) create mode 100644 drivers/mmc/mtk-sd.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 27246ee..ea60ed5 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -598,6 +598,17 @@ config FTSDC010_SDIO help This can enable ftsdc010 sdio function. +config MMC_MTK + bool "MediaTek SD/MMC Card Interface support" + depends on ARCH_MEDIATEK + depends on BLK && DM_MMC + depends on OF_CONTROL + help + This selects the MediaTek(R) Secure digital and Multimedia card Interface. + If you have a machine with a integrated SD/MMC card reader, say Y or M here. + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 23c5b0d..801a26d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o +obj-$(CONFIG_MMC_MTK) += mtk-sd.o diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c new file mode 100644 index 000..0741a52 --- /dev/null +++ b/drivers/mmc/mtk-sd.c @@ -0,0 +1,1394 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek SD/MMC Card Interface driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MSDC_CFG */ +#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) +#define MSDC_CFG_CKMOD_EXT_M 0x30 +#define MSDC_CFG_CKMOD_EXT_S 20 +#define MSDC_CFG_CKDIV_EXT_M 0xfff00 +#define MSDC_CFG_CKDIV_EXT_S 8 +#define MSDC_CFG_HS400_CK_MODE BIT(18) +#define MSDC_CFG_CKMOD_M 0x3 +#define MSDC_CFG_CKMOD_S 16 +#define MSDC_CFG_CKDIV_M 0xff00 +#define MSDC_CFG_CKDIV_S 8 +#define MSDC_CFG_CKSTB BIT(7) +#define MSDC_CFG_PIO BIT(3) +#define MSDC_CFG_RST BIT(2) +#define MSDC_CFG_CKPDN BIT(1) +#define MSDC_CFG_MODE BIT(0) + +/* MSDC_IOCON */ +#define MSDC_IOCON_W_DSPL BIT(8) +#define MSDC_IOCON_DSPLBIT(2) +#define MSDC_IOCON_RSPLBIT(1) + +/* MSDC_PS */ +#define MSDC_PS_DAT0 BIT(16) +#define MSDC_PS_CDDBCE_M 0xf000 +#define MSDC_PS_CDDBCE_S 12 +#define MSDC_PS_CDSTS BIT(1) +#define MSDC_PS_CDEN BIT(0) + +/* #define MSDC_INT(EN) */ +#define MSDC_INT_ACMDRDY BIT(3) +#define MSDC_INT_ACMDTMO BIT(4) +#define MSDC_INT_ACMDCRCERRBIT(5) +#define MSDC_INT_CMDRDYBIT(8) +#define MSDC_INT_CMDTMOBIT(9) +#define MSDC_INT_RSPCRCERR BIT(10) +#define MSDC_INT_XFER_COMPLBIT(12) +#define MSDC_INT_DATTMOBIT(14) +#define MSDC_INT_DATCRCERR BIT(15) + +/* MSDC_FIFOCS */ +#define MSDC_FIFOCS_CLRBIT(31) +#define MSDC_FIFOCS_TXCNT_M0xff +#define MSDC_FIFOCS_TXCNT_S16 +#define MSDC_FIFOCS_RXCNT_M0xff +#define MSDC_FIFOCS_RXCNT_S0 + +/* #define SDC_CFG */ +#define SDC_CFG_DTOC_M 0xff00 +#define SDC_CFG_DTOC_S 24 +#define SDC_CFG_SDIOIDEBIT(20) +#define SDC_CFG_SDIO BIT(19) +#define SDC_CFG_BUSWIDTH_M 0x3 +#define SDC_CFG_BUSWIDTH_S 16 + +/* SDC_CMD */ +#define SDC_CMD_BLK_LEN_M 0xfff +#define SDC_CMD_BLK_LEN_S 16 +#define SDC_CMD_STOP BIT(14) +#define SDC_CMD_WR BIT(13) +#define SDC_CMD_DTYPE_M0x1800 +#define SDC_CMD_DTYPE_S11 +#define SDC_CMD_RSPTYP_M 0x380 +#define SDC_CMD_RSPTYP_S 7 +#define SDC_CMD_CMD_M 0x3f +#define SDC_CMD_CMD_S 0 + +/* SDC_STS */ +#define SDC_STS_CMDBUSYBIT(1) +#define SDC_STS_SDCBUSYBIT(0) + +/* SDC_ADV_CFG0 */ +#define SDC_RX_ENHANCE_EN
[U-Boot] [PATCH v3 17/18] doc: README.mediatek: Add a simple README for MediaTek
Add a few notes on how to try out the MediaTek support so far. Signed-off-by: Ryder Lee --- doc/README.mediatek | 54 + 1 file changed, 54 insertions(+) create mode 100644 doc/README.mediatek diff --git a/doc/README.mediatek b/doc/README.mediatek new file mode 100644 index 000..7690342 --- /dev/null +++ b/doc/README.mediatek @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 MediaTek Inc. +# Ryder Lee + + +This document describes how to compile the U-Boot and how to change U-Boot +configuration about the MediaTek SoCs. + + +Build Procedure +=== + -Set the cross compiler: + + # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi- + + -Clean-up old residuals: + + # make mrproper + + -Configure the U-Boot: + + # make + # make + + - For the MT7623n bananapi R2 board use "mt7623n_bpir2_defconfig" + - For the MT7629 reference board use "mt7629_rfb_defconfig" + + +Boot sequence += + -Boorom -> MTK preloader -> U-Boot + + - MT7623n + + This version of U-Boot doesn't implement SPL. So, MTK preloader binary + is needed to boot up: + + https://github.com/BPI-SINOVOIP/BPI-R2-bsp/tree/master/mt-pack/mtk/bpi-r2/bin + + + -Boorom -> SPL -> U-Boot + + - MT7629 + + +Configuration update + + To update the U-Boot configuration, please refer to doc/README.kconfig + + +Documentation += + http://wiki.banana-pi.org/Banana_Pi_BPI-R2 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 15/18] ram: MediaTek: add DDR3 driver for MT7629 SoC
This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou Signed-off-by: Ryder Lee Reviewed-by: Simon Glass --- drivers/ram/Makefile | 1 + drivers/ram/mediatek/Makefile | 7 + drivers/ram/mediatek/ddr3-mt7629.c | 766 + 3 files changed, 774 insertions(+) create mode 100644 drivers/ram/mediatek/Makefile create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index cfba57f..92ea715 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/ram/mediatek/Makefile b/drivers/ram/mediatek/Makefile new file mode 100644 index 000..95507b5 --- /dev/null +++ b/drivers/ram/mediatek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 MediaTek Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_TARGET_MT7629) = ddr3-mt7629.o diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c new file mode 100644 index 000..b413f49 --- /dev/null +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DDR3 driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Wu Zou + *Ryder Lee + */ + +#include +#include +#include +#include +#include + +/* EMI */ +#define EMI_CONA 0x000 +#define EMI_CONF 0x028 +#define EMI_CONM 0x060 + +/* DDR PHY */ +#define DDRPHY_PLL10x +#define DDRPHY_PLL20x0004 +#define DDRPHY_PLL30x0008 +#define DDRPHY_PLL40x000c +#define DDRPHY_PLL50x0010 +#define DDRPHY_PLL70x0018 +#define DDRPHY_B0_DLL_ARPI00x0080 +#define DDRPHY_B0_DLL_ARPI10x0084 +#define DDRPHY_B0_DLL_ARPI20x0088 +#define DDRPHY_B0_DLL_ARPI30x008c +#define DDRPHY_B0_DLL_ARPI40x0090 +#define DDRPHY_B0_DLL_ARPI50x0094 +#define DDRPHY_B0_DQ2 0x00a0 +#define DDRPHY_B0_DQ3 0x00a4 +#define DDRPHY_B0_DQ4 0x00a8 +#define DDRPHY_B0_DQ5 0x00ac +#define DDRPHY_B0_DQ6 0x00b0 +#define DDRPHY_B0_DQ7 0x00b4 +#define DDRPHY_B0_DQ8 0x00b8 +#define DDRPHY_B1_DLL_ARPI00x0100 +#define DDRPHY_B1_DLL_ARPI10x0104 +#define DDRPHY_B1_DLL_ARPI20x0108 +#define DDRPHY_B1_DLL_ARPI30x010c +#define DDRPHY_B1_DLL_ARPI40x0110 +#define DDRPHY_B1_DLL_ARPI50x0114 +#define DDRPHY_B1_DQ2 0x0120 +#define DDRPHY_B1_DQ3 0x0124 +#define DDRPHY_B1_DQ4 0x0128 +#define DDRPHY_B1_DQ5 0x012c +#define DDRPHY_B1_DQ6 0x0130 +#define DDRPHY_B1_DQ7 0x0134 +#define DDRPHY_B1_DQ8 0x0138 +#define DDRPHY_CA_DLL_ARPI00x0180 +#define DDRPHY_CA_DLL_ARPI10x0184 +#define DDRPHY_CA_DLL_ARPI20x0188 +#define DDRPHY_CA_DLL_ARPI30x018c +#define DDRPHY_CA_DLL_ARPI40x0190 +#define DDRPHY_CA_DLL_ARPI50x0194 +#define DDRPHY_CA_CMD2 0x01a0 +#define DDRPHY_CA_CMD3 0x01a4 +#define DDRPHY_CA_CMD5 0x01ac +#define DDRPHY_CA_CMD6 0x01b0 +#define DDRPHY_CA_CMD7 0x01b4 +#define DDRPHY_CA_CMD8 0x01b8 +#define DDRPHY_MISC_VREF_CTRL 0x0264 +#define DDRPHY_MISC_IMP_CTRL0 0x0268 +#define DDRPHY_MISC_IMP_CTRL1 0x026c +#define DDRPHY_MISC_SHU_OPT0x0270 +#define DDRPHY_MISC_SPM_CTRL0 0x0274 +#define DDRPHY_MISC_SPM_CTRL1 0x0278 +#define DDRPHY_MISC_SPM_CTRL2 0x027c +#define DDRPHY_MISC_CG_CTRL0 0x0284 +#define DDRPHY_MISC_CG_CTRL1 0x0288 +#define DDRPHY_MISC_CG_CTRL2 0x028c +#define DDRPHY_MISC_CG_CTRL4 0x0294 +#define DDRPHY_MISC_CTRL0 0x029c +#define DDRPHY_MISC_CTRL1 0x02a0 +#define DDRPHY_MISC_CTRL3 0x02a8 +#define DDRPHY_MISC_RXDVS1 0x05e4 +#define DDRPHY_SHU1_B0_DQ4 0x0c10 +#define DDRPHY_SHU1_B0_DQ5 0x0c14 +#define DDRPHY_SHU1_B0_DQ6 0x0c18 +#define DDRPHY_SHU1_B0_DQ7 0x0c1c +#define DDRPHY_SHU1_B1_DQ4 0x0c90 +#define DDRPHY_SHU1_B1_DQ5 0x0c94 +#define DDRPHY_SHU1_B1_DQ6 0x0c98 +#define DDRPHY_SHU1_B1_DQ7 0x0c9c +#define DDRPHY_SHU1_CA_CMD20x0d08 +#define DDRPHY_SHU1_CA_CMD40x0d10 +#define DDRPHY_SHU1_CA_CMD50x0d14 +#define DDRPHY_SHU1_CA_CMD6
Re: [U-Boot] [PATCH v2 15/18] ram: MediaTek: add DDR3 driver for MT7629 SoC
On Wed, 2018-10-24 at 21:30 -0600, Simon Glass wrote:
> On 12 October 2018 at 01:01, Ryder Lee wrote:
> > This patch adds a DDR3 driver for MT7629 SoC.
> >
> > Signed-off-by: Wu Zou
> > Signed-off-by: Ryder Lee
> > ---
> > drivers/ram/Makefile | 1 +
> > drivers/ram/mediatek/Makefile | 7 +
> > drivers/ram/mediatek/ddr3-mt7629.c | 766
> > +
> > 3 files changed, 774 insertions(+)
> > create mode 100644 drivers/ram/mediatek/Makefile
> > create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c
>
> Reviewed-by: Simon Glass
>
> Thoughts below.
>
> [..]
>
> > +#define DDRPHY_PLL10x
> > +#define DDRPHY_PLL20x0004
>
> Why not use a C struct for these registers?
These are copy-n-paste from our SDK. I've considered converting these
into C struct but it will take me a while. Just let it be.
But, I could do that if you insist.
> [..]
>
> > + writel(0x400, priv->dramc_ao + DRAMC_MRS);
> > + writel(0x1d7000, priv->dramc_ao + DRAMC_MRS);
> > + writel(0x1, priv->dramc_ao + DRAMC_SPCMD);
> > + writel(0x0, priv->dramc_ao + DRAMC_SPCMD);
> > + udelay(100);
>
> Are these delays specified in a datasheet? Why did you chose 100?
> Perhaps add an enum for this value? Is there a way to check for when
> the hardware is ready, e.g. by reading a registers in a loop?
Rule of thumb. There is no registers to read here, but I can try to
reduce the delay time.
> [..]
>
> > +static int mtk_ddr3_probe(struct udevice *dev)
> > +{
> > + struct mtk_ddr3_priv *priv = dev_get_priv(dev);
> > +
> > + priv->emi = dev_read_addr_index(dev, 0);
> > + if (priv->emi == FDT_ADDR_T_NONE)
> > + return -EINVAL;
> > +
> > + priv->ddrphy = dev_read_addr_index(dev, 1);
> > + if (priv->ddrphy == FDT_ADDR_T_NONE)
> > + return -EINVAL;
> > +
> > + priv->dramc_ao = dev_read_addr_index(dev, 2);
> > + if (priv->dramc_ao == FDT_ADDR_T_NONE)
> > + return -EINVAL;
> > +
> > +#ifdef CONFIG_SPL_BUILD
> > + int ret;
> > +
> > + ret = clk_get_by_index(dev, 0, >phy);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_get_by_index(dev, 1, >phy_mux);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_get_by_index(dev, 2, >mem);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_get_by_index(dev, 3, >mem_mux);
> > + if (ret)
> > + return ret;
>
> Do you have phandles for these clocks? I only worry that it is a bit
> brittle to have them numbered.
Yes. I choose clk_get_by_index() here as I stripped the 'clock-names'
via CONFIG_OF_SPL_REMOVE_PROPS to reduce the size .
Also I don't understand why we cannot use clk_set_defaults() in
pre-relocate state?
Ryder
> > +
> > + ret = mtk_ddr3_init(dev);
> > + if (ret)
> > + return ret;
> > +#endif
> > + return 0;
> > +}
> > +
>
> Regards,
> Simon
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Re: [U-Boot] [PATCH v4 14/18] serial: 16550: allow the driver to support MediaTek serial
On Tue, 2018-11-13 at 11:53 -0800, Simon Glass wrote: > Hi Ryder, > > On 6 November 2018 at 01:47, Ryder Lee wrote: > > This patch adds an extra operation in ns16550.c to suuport MediaTek > > SoCs as we have a highspeed register which influences the calcualtion > > of the divisor. > > > > Note that we don't support the baudrate greater than 115200 currently. > > > > Signed-off-by: Ryder Lee > > Tested-by: Matthias Brugger > > Reviewed-by: Simon Glass > > --- > > Changes since v4: None > > > > @Simon > > We have tried the compatible string, but it made the ns16550 driver more > > complicated. > > To use the compatible string we have to add a new field in > > ns16550_platdata, and change > > the flow of ns16550_serial_probe(). > > > > Moreover, it's totally useless for debug uart. At present using a macro is > > the easiest way here. > > > > What do you think? > > --- > > drivers/serial/ns16550.c | 10 ++ > > 1 file changed, 10 insertions(+) > > Please see my reply to the other thread. We should not have > arch-specific code in generic drivers. > > Sorry for not replying earlier on that. > OK. BTW, can you (or Tom) please take the other patches through your tree? Ryder ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 16/18] mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC
From: Weijie Gao This patch adds MT7623 host controller driver for accessing SD/MMC. Cc: Jaehoon Chung Signed-off-by: Weijie Gao Signed-off-by: Ryder Lee Tested-by: Matthias Brugger Reviewed-by: Simon Glass --- Changes since v4: None --- drivers/mmc/Kconfig | 11 + drivers/mmc/Makefile |1 + drivers/mmc/mtk-sd.c | 1394 ++ 3 files changed, 1406 insertions(+) create mode 100644 drivers/mmc/mtk-sd.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 27246ee..ea60ed5 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -598,6 +598,17 @@ config FTSDC010_SDIO help This can enable ftsdc010 sdio function. +config MMC_MTK + bool "MediaTek SD/MMC Card Interface support" + depends on ARCH_MEDIATEK + depends on BLK && DM_MMC + depends on OF_CONTROL + help + This selects the MediaTek(R) Secure digital and Multimedia card Interface. + If you have a machine with a integrated SD/MMC card reader, say Y or M here. + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 23c5b0d..801a26d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o +obj-$(CONFIG_MMC_MTK) += mtk-sd.o diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c new file mode 100644 index 000..0741a52 --- /dev/null +++ b/drivers/mmc/mtk-sd.c @@ -0,0 +1,1394 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek SD/MMC Card Interface driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MSDC_CFG */ +#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) +#define MSDC_CFG_CKMOD_EXT_M 0x30 +#define MSDC_CFG_CKMOD_EXT_S 20 +#define MSDC_CFG_CKDIV_EXT_M 0xfff00 +#define MSDC_CFG_CKDIV_EXT_S 8 +#define MSDC_CFG_HS400_CK_MODE BIT(18) +#define MSDC_CFG_CKMOD_M 0x3 +#define MSDC_CFG_CKMOD_S 16 +#define MSDC_CFG_CKDIV_M 0xff00 +#define MSDC_CFG_CKDIV_S 8 +#define MSDC_CFG_CKSTB BIT(7) +#define MSDC_CFG_PIO BIT(3) +#define MSDC_CFG_RST BIT(2) +#define MSDC_CFG_CKPDN BIT(1) +#define MSDC_CFG_MODE BIT(0) + +/* MSDC_IOCON */ +#define MSDC_IOCON_W_DSPL BIT(8) +#define MSDC_IOCON_DSPLBIT(2) +#define MSDC_IOCON_RSPLBIT(1) + +/* MSDC_PS */ +#define MSDC_PS_DAT0 BIT(16) +#define MSDC_PS_CDDBCE_M 0xf000 +#define MSDC_PS_CDDBCE_S 12 +#define MSDC_PS_CDSTS BIT(1) +#define MSDC_PS_CDEN BIT(0) + +/* #define MSDC_INT(EN) */ +#define MSDC_INT_ACMDRDY BIT(3) +#define MSDC_INT_ACMDTMO BIT(4) +#define MSDC_INT_ACMDCRCERRBIT(5) +#define MSDC_INT_CMDRDYBIT(8) +#define MSDC_INT_CMDTMOBIT(9) +#define MSDC_INT_RSPCRCERR BIT(10) +#define MSDC_INT_XFER_COMPLBIT(12) +#define MSDC_INT_DATTMOBIT(14) +#define MSDC_INT_DATCRCERR BIT(15) + +/* MSDC_FIFOCS */ +#define MSDC_FIFOCS_CLRBIT(31) +#define MSDC_FIFOCS_TXCNT_M0xff +#define MSDC_FIFOCS_TXCNT_S16 +#define MSDC_FIFOCS_RXCNT_M0xff +#define MSDC_FIFOCS_RXCNT_S0 + +/* #define SDC_CFG */ +#define SDC_CFG_DTOC_M 0xff00 +#define SDC_CFG_DTOC_S 24 +#define SDC_CFG_SDIOIDEBIT(20) +#define SDC_CFG_SDIO BIT(19) +#define SDC_CFG_BUSWIDTH_M 0x3 +#define SDC_CFG_BUSWIDTH_S 16 + +/* SDC_CMD */ +#define SDC_CMD_BLK_LEN_M 0xfff +#define SDC_CMD_BLK_LEN_S 16 +#define SDC_CMD_STOP BIT(14) +#define SDC_CMD_WR BIT(13) +#define SDC_CMD_DTYPE_M0x1800 +#define SDC_CMD_DTYPE_S11 +#define SDC_CMD_RSPTYP_M 0x380 +#define SDC_CMD_RSPTYP_S 7 +#define SDC_CMD_CMD_M 0x3f +#define SDC_CMD_CMD_S 0 + +/* SDC_STS */ +#define SDC_STS_CMDBUSYBIT(1) +#define SDC_STS_SDCBUSYBIT(0) + +/* SDC_AD
[U-Boot] [PATCH v4 09/18] watchdog: MediaTek: add watchdog driver for MediaTek SoCs
This patch adds a common driver for the Mediatek SoC integrated
watchdog.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v4: None
---
drivers/watchdog/Kconfig | 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/mtk_wdt.c | 135 +
3 files changed, 144 insertions(+)
create mode 100644 drivers/watchdog/mtk_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 02f4e1e..b919ef6 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -103,6 +103,14 @@ config WDT_CDNS
Select this to enable Cadence watchdog timer, which can be found on
some
Xilinx Microzed Platform.
+config WDT_MTK
+ bool "MediaTek watchdog timer support"
+ depends on WDT && ARCH_MEDIATEK
+ help
+ Select this to enable watchdog timer for MediaTek SoCs.
+ The watchdog timer is stopped when initialized.
+ It performs full SoC reset.
+
config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 08406ca..04fa4a6 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o
+obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
new file mode 100644
index 000..0b50173
--- /dev/null
+++ b/drivers/watchdog/mtk_wdt.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Watchdog driver for MediaTek SoCs
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#define MTK_WDT_MODE 0x00
+#define MTK_WDT_LENGTH 0x04
+#define MTK_WDT_RESTART0x08
+#define MTK_WDT_STATUS 0x0c
+#define MTK_WDT_INTERVAL 0x10
+#define MTK_WDT_SWRST 0x14
+#define MTK_WDT_REQ_MODE 0x30
+#define MTK_WDT_DEBUG_CTL 0x40
+
+#define WDT_MODE_KEY (0x22 << 24)
+#define WDT_MODE_ENBIT(0)
+#define WDT_MODE_EXTPOLBIT(1)
+#define WDT_MODE_EXTEN BIT(2)
+#define WDT_MODE_IRQ_ENBIT(3)
+#define WDT_MODE_DUAL_EN BIT(6)
+
+#define WDT_LENGTH_KEY 0x8
+#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
+
+#define WDT_RESTART_KEY0x1971
+#define WDT_SWRST_KEY 0x1209
+
+struct mtk_wdt_priv {
+ void __iomem *base;
+};
+
+static int mtk_wdt_reset(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Reload watchdog duration */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ return 0;
+}
+
+static int mtk_wdt_stop(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
+
+ return 0;
+}
+
+static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Kick watchdog to prevent counter == 0 */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ /* Reset */
+ writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
+ hang();
+
+ return 0;
+}
+
+static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /*
+* One bit is the value of 512 ticks
+* The clock has 32 KHz
+*/
+ timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
+ writel(timeout, priv->base + MTK_WDT_LENGTH);
+
+ mtk_wdt_reset(dev);
+}
+
+static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ mtk_wdt_set_timeout(dev, timeout);
+
+ /* Enable watchdog reset signal */
+ setbits_le32(priv->base + MTK_WDT_MODE,
+WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
+
+ return 0;
+}
+
+static int mtk_wdt_probe(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ /* Clear status */
+ clrsetbits_le32(priv->base + MTK_WDT_MODE,
+ WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
+
+ return mtk_wdt_stop(dev);
+}
+
+static const struct wdt_ops mtk_wdt_ops = {
+ .start = mtk_wdt_start,
+ .reset = mtk_wdt_reset,
+ .stop = mtk_wdt_s
[U-Boot] [PATCH v4 12/18] power domain: MediaTek: add power domain driver for MT7629 SoC
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v4: None
---
drivers/power/domain/Kconfig| 7 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/mtk-power-domain.c | 326
3 files changed, 334 insertions(+)
create mode 100644 drivers/power/domain/mtk-power-domain.c
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a08b428..93deaef 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -23,6 +23,13 @@ config IMX8_POWER_DOMAIN
Enable support for manipulating NXP i.MX8 on-SoC power domains via
IPC
requests to the SCU.
+config MTK_POWER_DOMAIN
+ bool "Enable the MediaTek power domain driver"
+ depends on POWER_DOMAIN && ARCH_MEDIATEK
+ help
+ Enable support for manipulating MediaTek power domains via MMIO
+ mapped registers.
+
config MESON_GX_VPU_POWER_DOMAIN
bool "Enable Amlogic Meson GX VPU power domain driver"
depends on ARCH_MESON
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index b08d18f..695aafe 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o
+obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
new file mode 100644
index 000..ed4a718
--- /dev/null
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define SPM_EN (0xb16 << 16 | 0x1)
+#define SPM_ETHSYS_PWR_CON 0x2e0
+#define SPM_HIF0_PWR_CON 0x2e4
+#define SPM_HIF1_PWR_CON 0x2e8
+#define SPM_PWR_STATUS 0x60c
+#define SPM_PWR_STATUS_2ND 0x610
+
+#define PWR_RST_B_BIT BIT(0)
+#define PWR_ISO_BITBIT(1)
+#define PWR_ON_BIT BIT(2)
+#define PWR_ON_2ND_BIT BIT(3)
+#define PWR_CLK_DIS_BITBIT(4)
+
+#define PWR_STATUS_ETHSYS BIT(24)
+#define PWR_STATUS_HIF0BIT(25)
+#define PWR_STATUS_HIF1BIT(26)
+
+/* Infrasys configuration */
+#define INFRA_TOPDCM_CTRL 0x10
+#define INFRA_TOPAXI_PROT_EN 0x220
+#define INFRA_TOPAXI_PROT_STA1 0x228
+
+#define DCM_TOP_EN BIT(0)
+
+enum scp_domain_type {
+ SCPSYS_MT7629,
+};
+
+struct scp_domain;
+
+struct scp_domain_data {
+ struct scp_domain *scpd;
+ u32 sta_mask;
+ int ctl_offs;
+ u32 sram_pdn_bits;
+ u32 sram_pdn_ack_bits;
+ u32 bus_prot_mask;
+};
+
+struct scp_domain {
+ void __iomem *base;
+ void __iomem *infracfg;
+ enum scp_domain_type type;
+ struct scp_domain_data *data;
+};
+
+static struct scp_domain_data scp_domain_mt7629[] = {
+ [MT7629_POWER_DOMAIN_ETHSYS] = {
+ .sta_mask = PWR_STATUS_ETHSYS,
+ .ctl_offs = SPM_ETHSYS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = (BIT(3) | BIT(17)),
+ },
+ [MT7629_POWER_DOMAIN_HIF0] = {
+ .sta_mask = PWR_STATUS_HIF0,
+ .ctl_offs = SPM_HIF0_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(25, 24),
+ },
+ [MT7629_POWER_DOMAIN_HIF1] = {
+ .sta_mask = PWR_STATUS_HIF1,
+ .ctl_offs = SPM_HIF1_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(28, 26),
+ },
+};
+
+/**
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hang when some unit accesses the
+ * bus while in power down.
+ */
+static int mtk_infracfg_set_bus
[U-Boot] [PATCH v4 08/18] timer: MediaTek: add timer driver for MediaTek SoCs
This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v4: None
---
drivers/timer/Kconfig | 7
drivers/timer/Makefile| 1 +
drivers/timer/mtk_timer.c | 85 +++
3 files changed, 93 insertions(+)
create mode 100644 drivers/timer/mtk_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index d012cf7..229c3a2 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -160,4 +160,11 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
+config MTK_TIMER
+ bool "MediaTek timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ MediaTek devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 7f19c49..c4fbab2 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
new file mode 100644
index 000..b5e76bd
--- /dev/null
+++ b/drivers/timer/mtk_timer.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek timer driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_GPT4_CTRL 0x40
+#define MTK_GPT4_CLK 0x44
+#define MTK_GPT4_CNT 0x48
+
+#define GPT4_ENABLEBIT(0)
+#define GPT4_CLEAR BIT(1)
+#define GPT4_FREERUN GENMASK(5, 4)
+#define GPT4_CLK_SYS 0x0
+#define GPT4_CLK_DIV1 0x0
+
+struct mtk_timer_priv {
+ void __iomem *base;
+};
+
+static int mtk_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ u32 val = readl(priv->base + MTK_GPT4_CNT);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int mtk_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk, parent;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 1, );
+ if (!ret) {
+ ret = clk_set_parent(, );
+ if (ret)
+ return ret;
+ }
+
+ uc_priv->clock_rate = clk_get_rate();
+ if (!uc_priv->clock_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct timer_ops mtk_timer_ops = {
+ .get_count = mtk_timer_get_count,
+};
+
+static const struct udevice_id mtk_timer_ids[] = {
+ { .compatible = "mediatek,timer" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_timer) = {
+ .name = "mtk_timer",
+ .id = UCLASS_TIMER,
+ .of_match = mtk_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct mtk_timer_priv),
+ .probe = mtk_timer_probe,
+ .ops = _timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
1.9.1
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[U-Boot] [PATCH v4 07/18] clk: MediaTek: add clock driver for MT7623 SoC.
This patch adds a driver for MT7623 clock blocks.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v4: None
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7623.c | 870 ++
2 files changed, 871 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7623.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 297f99d..0632dc8 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7623.c
b/drivers/clk/mediatek/clk-mt7623.c
new file mode 100644
index 000..c6b09d8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7623 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7623_CLKSQ_STB_CON0 0x18
+#define MT7623_PLL_ISO_CON00x24
+#define MT7623_PLL_FMAX(2000UL * MHZ)
+#define MT7623_CON0_RST_BARBIT(27)
+
+#define MCU_AXI_DIV0x60
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7623_CON0_RST_BAR,\
+ .fmax = MT7623_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x8001, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf001, HAVE_RST_BAR,
+ 21, 0x210, 4, 0x214, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf301, HAVE_RST_BAR,
+ 7, 0x220, 4, 0x224, 14),
+ PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x0001, 0,
+ 21, 0x230, 4, 0x234, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x0001, 0,
+ 21, 0x240, 4, 0x244, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x0001, 0,
+ 21, 0x250, 4, 0x254, 0),
+ PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x0001, 0,
+ 31, 0x270, 4, 0x274, 0),
+ PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x0001, 0,
+ 31, 0x280, 4, 0x284, 0),
+ PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x0001, 0,
+ 31, 0x290, 4, 0x294, 0),
+ PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x0001, 0,
+ 31, 0x2a0, 4, 0x2a4, 0),
+ PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x0001, 0,
+ 31, 0x2b0, 4, 0x2b4, 0),
+ PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x0001, 0,
+ 31, 0x2c0, 4, 0x2c4, 0),
+ PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x0001, 0,
+ 21, 0x2d0, 4, 0x2d4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
+ FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
+ FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
+ FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
+
[U-Boot] [PATCH v4 04/18] arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. Signed-off-by: Ryder Lee Signed-off-by: Weijie Gao Reviewed-by: Simon Glass --- Changes since v4: -Add gd->bd->bi_boot_params for legacy method - ATAGs. --- arch/arm/Kconfig | 16 arch/arm/Makefile | 1 + arch/arm/include/asm/arch-mediatek/misc.h | 17 arch/arm/mach-mediatek/Kconfig| 26 ++ arch/arm/mach-mediatek/Makefile | 6 ++ arch/arm/mach-mediatek/cpu.c | 34 +++ arch/arm/mach-mediatek/init.h | 11 +++ arch/arm/mach-mediatek/mt7629/Makefile| 4 + arch/arm/mach-mediatek/mt7629/init.c | 128 ++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 ++ arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7629/Kconfig | 17 board/mediatek/mt7629/MAINTAINERS | 7 ++ board/mediatek/mt7629/Makefile| 3 + board/mediatek/mt7629/mt7629_rfb.c| 16 configs/mt7629_rfb_defconfig | 73 +++ include/configs/mt7629.h | 57 17 files changed, 509 insertions(+) create mode 100644 arch/arm/include/asm/arch-mediatek/misc.h create mode 100644 arch/arm/mach-mediatek/Kconfig create mode 100644 arch/arm/mach-mediatek/Makefile create mode 100644 arch/arm/mach-mediatek/cpu.c create mode 100644 arch/arm/mach-mediatek/init.h create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile create mode 100644 arch/arm/mach-mediatek/mt7629/init.c create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/spl.c create mode 100644 board/mediatek/mt7629/Kconfig create mode 100644 board/mediatek/mt7629/MAINTAINERS create mode 100644 board/mediatek/mt7629/Makefile create mode 100644 board/mediatek/mt7629/mt7629_rfb.c create mode 100644 configs/mt7629_rfb_defconfig create mode 100644 include/configs/mt7629.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1f3fa15..96cd41c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -658,6 +658,20 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MEDIATEK + bool "MediaTek SoCs" + select BINMAN + select DM + select OF_CONTROL + select SPL_DM if SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL + select SPL_OF_CONTROL if SPL + select SUPPORT_SPL + help + Support for the MediaTek SoCs family developed by MediaTek Inc. + Please refer to doc/README.mediatek for more information. + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -1442,6 +1456,8 @@ source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-mediatek/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b6c5e1..c38ef3c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE)+= keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h new file mode 100644 index 000..2530e78 --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/misc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_MISC_H_ +#define __MEDIATEK_MISC_H_ + +#define VER_BASE 0x0800 +#define VER_SIZE 0x10 + +#define APHW_CODE 0x00 +#define APHW_SUBCODE 0x04 +#define APHW_VER 0x08 +#define APSW_VER 0x0c + +#endif /* __MEDIATEK_MISC_H_ */ diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 000..d2ada97 --- /dev/null +++ b/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,26 @@ +if ARCH_MEDIATEK + +config SYS_SOC + default "mediatek" + +config SYS_VENDOR + default "mediatek" + +choice + prompt "MediaTek board select" + +config TARGET_MT7629 + bool "MediaTek MT7629 SoC" + sel
[U-Boot] [PATCH v4 15/18] ram: MediaTek: add DDR3 driver for MT7629 SoC
This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou Signed-off-by: Ryder Lee Reviewed-by: Simon Glass --- Changes since v4: None --- drivers/ram/Makefile | 1 + drivers/ram/mediatek/Makefile | 7 + drivers/ram/mediatek/ddr3-mt7629.c | 766 + 3 files changed, 774 insertions(+) create mode 100644 drivers/ram/mediatek/Makefile create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index cfba57f..92ea715 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/ram/mediatek/Makefile b/drivers/ram/mediatek/Makefile new file mode 100644 index 000..95507b5 --- /dev/null +++ b/drivers/ram/mediatek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 MediaTek Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_TARGET_MT7629) = ddr3-mt7629.o diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c new file mode 100644 index 000..b413f49 --- /dev/null +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DDR3 driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Wu Zou + *Ryder Lee + */ + +#include +#include +#include +#include +#include + +/* EMI */ +#define EMI_CONA 0x000 +#define EMI_CONF 0x028 +#define EMI_CONM 0x060 + +/* DDR PHY */ +#define DDRPHY_PLL10x +#define DDRPHY_PLL20x0004 +#define DDRPHY_PLL30x0008 +#define DDRPHY_PLL40x000c +#define DDRPHY_PLL50x0010 +#define DDRPHY_PLL70x0018 +#define DDRPHY_B0_DLL_ARPI00x0080 +#define DDRPHY_B0_DLL_ARPI10x0084 +#define DDRPHY_B0_DLL_ARPI20x0088 +#define DDRPHY_B0_DLL_ARPI30x008c +#define DDRPHY_B0_DLL_ARPI40x0090 +#define DDRPHY_B0_DLL_ARPI50x0094 +#define DDRPHY_B0_DQ2 0x00a0 +#define DDRPHY_B0_DQ3 0x00a4 +#define DDRPHY_B0_DQ4 0x00a8 +#define DDRPHY_B0_DQ5 0x00ac +#define DDRPHY_B0_DQ6 0x00b0 +#define DDRPHY_B0_DQ7 0x00b4 +#define DDRPHY_B0_DQ8 0x00b8 +#define DDRPHY_B1_DLL_ARPI00x0100 +#define DDRPHY_B1_DLL_ARPI10x0104 +#define DDRPHY_B1_DLL_ARPI20x0108 +#define DDRPHY_B1_DLL_ARPI30x010c +#define DDRPHY_B1_DLL_ARPI40x0110 +#define DDRPHY_B1_DLL_ARPI50x0114 +#define DDRPHY_B1_DQ2 0x0120 +#define DDRPHY_B1_DQ3 0x0124 +#define DDRPHY_B1_DQ4 0x0128 +#define DDRPHY_B1_DQ5 0x012c +#define DDRPHY_B1_DQ6 0x0130 +#define DDRPHY_B1_DQ7 0x0134 +#define DDRPHY_B1_DQ8 0x0138 +#define DDRPHY_CA_DLL_ARPI00x0180 +#define DDRPHY_CA_DLL_ARPI10x0184 +#define DDRPHY_CA_DLL_ARPI20x0188 +#define DDRPHY_CA_DLL_ARPI30x018c +#define DDRPHY_CA_DLL_ARPI40x0190 +#define DDRPHY_CA_DLL_ARPI50x0194 +#define DDRPHY_CA_CMD2 0x01a0 +#define DDRPHY_CA_CMD3 0x01a4 +#define DDRPHY_CA_CMD5 0x01ac +#define DDRPHY_CA_CMD6 0x01b0 +#define DDRPHY_CA_CMD7 0x01b4 +#define DDRPHY_CA_CMD8 0x01b8 +#define DDRPHY_MISC_VREF_CTRL 0x0264 +#define DDRPHY_MISC_IMP_CTRL0 0x0268 +#define DDRPHY_MISC_IMP_CTRL1 0x026c +#define DDRPHY_MISC_SHU_OPT0x0270 +#define DDRPHY_MISC_SPM_CTRL0 0x0274 +#define DDRPHY_MISC_SPM_CTRL1 0x0278 +#define DDRPHY_MISC_SPM_CTRL2 0x027c +#define DDRPHY_MISC_CG_CTRL0 0x0284 +#define DDRPHY_MISC_CG_CTRL1 0x0288 +#define DDRPHY_MISC_CG_CTRL2 0x028c +#define DDRPHY_MISC_CG_CTRL4 0x0294 +#define DDRPHY_MISC_CTRL0 0x029c +#define DDRPHY_MISC_CTRL1 0x02a0 +#define DDRPHY_MISC_CTRL3 0x02a8 +#define DDRPHY_MISC_RXDVS1 0x05e4 +#define DDRPHY_SHU1_B0_DQ4 0x0c10 +#define DDRPHY_SHU1_B0_DQ5 0x0c14 +#define DDRPHY_SHU1_B0_DQ6 0x0c18 +#define DDRPHY_SHU1_B0_DQ7 0x0c1c +#define DDRPHY_SHU1_B1_DQ4 0x0c90 +#define DDRPHY_SHU1_B1_DQ5 0x0c94 +#define DDRPHY_SHU1_B1_DQ6 0x0c98 +#define DDRPHY_SHU1_B1_DQ7 0x0c9c +#define DDRPHY_SHU1_CA_CMD20x0d08 +#define DDRPHY_SHU1_CA_CMD40x0d10 +#define DDRPHY_SHU1_CA_CMD50x0d14
[U-Boot] [PATCH v4 03/18] arm: dts: MediaTek: add device tree for MT7623
This adds device tree for MT7623 development board - Bananapi R2
Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v4: None
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/mt7623.dtsi | 255 +++
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207
include/dt-bindings/clock/mt7623-clk.h | 413 +++
include/dt-bindings/power/mt7623-power.h | 19 ++
5 files changed, 895 insertions(+)
create mode 100644 arch/arm/dts/mt7623.dtsi
create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
create mode 100644 include/dt-bindings/clock/mt7623-clk.h
create mode 100644 include/dt-bindings/power/mt7623-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2001e63..4b30ef9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -559,6 +559,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
new file mode 100644
index 000..3be5b6a
--- /dev/null
+++ b/arch/arm/dts/mt7623.dtsi
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7623";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <1300>;
+ #clock-cells = <0>;
+ };
+
+ rtc32k: oscillator-1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
+ };
+
+ clk26m: oscillator-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ clock-output-names = "clk26m";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ topckgen: clock-controller@1000 {
+ c
[U-Boot] [PATCH v4 14/18] serial: 16550: allow the driver to support MediaTek serial
This patch adds an extra operation in ns16550.c to suuport MediaTek
SoCs as we have a highspeed register which influences the calcualtion
of the divisor.
Note that we don't support the baudrate greater than 115200 currently.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v4: None
@Simon
We have tried the compatible string, but it made the ns16550 driver more
complicated.
To use the compatible string we have to add a new field in ns16550_platdata,
and change
the flow of ns16550_serial_probe().
Moreover, it's totally useless for debug uart. At present using a macro is the
easiest way here.
What do you think?
---
drivers/serial/ns16550.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index f9041aa..f5410af 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -148,6 +148,13 @@ int ns16550_calc_divisor(NS16550_t port, int clock, int
baudrate)
static void NS16550_setbrg(NS16550_t com_port, int baud_divisor)
{
+#ifdef CONFIG_ARCH_MEDIATEK
+ /*
+* MediaTek UARTs has an extra highspeed register.
+* We need to clear it if baudrate <= 115200.
+*/
+ serial_out(0, _port->reg9);
+#endif
serial_out(UART_LCR_BKSE | UART_LCRVAL, _port->lcr);
serial_out(baud_divisor & 0xff, _port->dll);
serial_out((baud_divisor >> 8) & 0xff, _port->dlm);
@@ -261,6 +268,9 @@ static inline void _debug_uart_init(void)
serial_dout(_port->mcr, UART_MCRVAL);
serial_dout(_port->fcr, UART_FCR_DEFVAL);
+#ifdef CONFIG_ARCH_MEDIATEK
+ serial_dout(_port->reg9, 0);
+#endif
serial_dout(_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
serial_dout(_port->dll, baud_divisor & 0xff);
serial_dout(_port->dlm, (baud_divisor >> 8) & 0xff);
--
1.9.1
___
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[U-Boot] [PATCH v4 13/18] power domain: MediaTek: add power domain driver for MT7623 SoC
This adds power domain (scpsys) support for MT7623 SoC.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v4: None
---
drivers/power/domain/mtk-power-domain.c | 80 +
1 file changed, 80 insertions(+)
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
index ed4a718..c67e880 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -14,9 +14,19 @@
#include
#include
+#include
#include
#define SPM_EN (0xb16 << 16 | 0x1)
+#define SPM_VDE_PWR_CON0x0210
+#define SPM_MFG_PWR_CON0x0214
+#define SPM_ISP_PWR_CON0x0238
+#define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON 0x0280
+#define SPM_BDP_PWR_CON0x029c
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
#define SPM_ETHSYS_PWR_CON 0x2e0
#define SPM_HIF0_PWR_CON 0x2e4
#define SPM_HIF1_PWR_CON 0x2e8
@@ -29,6 +39,15 @@
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BITBIT(4)
+#define PWR_STATUS_CONNBIT(1)
+#define PWR_STATUS_DISPBIT(3)
+#define PWR_STATUS_MFG BIT(4)
+#define PWR_STATUS_ISP BIT(5)
+#define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
#define PWR_STATUS_ETHSYS BIT(24)
#define PWR_STATUS_HIF0BIT(25)
#define PWR_STATUS_HIF1BIT(26)
@@ -41,6 +60,7 @@
#define DCM_TOP_EN BIT(0)
enum scp_domain_type {
+ SCPSYS_MT7623,
SCPSYS_MT7629,
};
@@ -62,6 +82,59 @@ struct scp_domain {
struct scp_domain_data *data;
};
+static struct scp_domain_data scp_domain_mt7623[] = {
+ [MT7623_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .bus_prot_mask = BIT(8) | BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_DISP] = {
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .bus_prot_mask = BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_MFG] = {
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_VDEC] = {
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_ISP] = {
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ },
+ [MT7623_POWER_DOMAIN_BDP] = {
+ .sta_mask = PWR_STATUS_BDP,
+ .ctl_offs = SPM_BDP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ },
+ [MT7623_POWER_DOMAIN_ETH] = {
+ .sta_mask = PWR_STATUS_ETH,
+ .ctl_offs = SPM_ETH_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_HIF] = {
+ .sta_mask = PWR_STATUS_HIF,
+ .ctl_offs = SPM_HIF_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_IFR_MSC] = {
+ .sta_mask = PWR_STATUS_IFR_MSC,
+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
+ },
+};
+
static struct scp_domain_data scp_domain_mt7629[] = {
[MT7629_POWER_DOMAIN_ETHSYS] = {
.sta_mask = PWR_STATUS_ETHSYS,
@@ -252,6 +325,9 @@ static int mtk_power_domain_hook(struct udevice *dev)
scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
switch (scpd->type) {
+ case SCPSYS_MT7623:
+ scpd->data = scp_domain_mt7623;
+ break;
case SCPSYS_MT7629:
scpd->data = scp_domain_mt7629;
break;
@@ -303,6 +379,10 @@ static int mtk_power_domain_probe(struct udevice *dev)
static const struct udevice_id mtk_power_domain_ids[] = {
{
+ .compatible = "mediatek,mt7623-scpsys",
+ .data = SCPSYS_MT7623,
+ },
+ {
.compatible = "mediatek,mt7629-scpsys",
.data = SCPSYS_MT7629,
},
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.de
[U-Boot] [PATCH v4 06/18] clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v4: None
-Add a __common_ infix on the shared funcitons to make them clear.
(i.e., mtk_clk_init() -> mtk_common_clk_init())
---
drivers/clk/Makefile | 1 +
drivers/clk/mediatek/Makefile | 6 +
drivers/clk/mediatek/clk-mt7629.c | 709 ++
drivers/clk/mediatek/clk-mtk.c| 493 ++
drivers/clk/mediatek/clk-mtk.h| 194 +++
5 files changed, 1403 insertions(+)
create mode 100644 drivers/clk/mediatek/Makefile
create mode 100644 drivers/clk/mediatek/clk-mt7629.c
create mode 100644 drivers/clk/mediatek/clk-mtk.c
create mode 100644 drivers/clk/mediatek/clk-mtk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 821b586..c128538 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
new file mode 100644
index 000..297f99d
--- /dev/null
+++ b/drivers/clk/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
+
+# SoC Drivers
+obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk/mediatek/clk-mt7629.c
new file mode 100644
index 000..2601b6c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7629_CLKSQ_STB_CON0 0x20
+#define MT7629_PLL_ISO_CON00x2c
+#define MT7629_PLL_FMAX(2500UL * MHZ)
+#define MT7629_CON0_RST_BARBIT(24)
+
+#define MCU_AXI_DIV0x640
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX0x7c0
+#define MCU_BUS_MSKGENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7629_CON0_RST_BAR,\
+ .fmax = MT7629_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] =
[U-Boot] [PATCH v4 00/18] Add U-Boot support for MediaTek SoCs - MT7623n & MT7629
Hello, This is the new round to add U-Boot support for MediaTek SoCs - MT7623n & MT7629, and the most of the drivers are based on mainline Linux, such as clock, timer, mmc, pinctrl, watchdog, power domain and device tree. Thanks, Ryder Ryder Lee (16): tools: MediaTek: add MTK boot header generation to mkimage arm: dts: MediaTek: add device tree for MT7629 arm: dts: MediaTek: add device tree for MT7623 arm: MediaTek: add basic support for MT7629 boards clk: MediaTek: add clock driver for MT7629 SoC. clk: MediaTek: add clock driver for MT7623 SoC. timer: MediaTek: add timer driver for MediaTek SoCs watchdog: MediaTek: add watchdog driver for MediaTek SoCs pinctrl: MediaTek: add pinctrl driver for MT7629 SoC pinctrl: MediaTek: add pinctrl driver for MT7623 SoC power domain: MediaTek: add power domain driver for MT7629 SoC power domain: MediaTek: add power domain driver for MT7623 SoC serial: 16550: allow the driver to support MediaTek serial ram: MediaTek: add DDR3 driver for MT7629 SoC doc: README.mediatek: Add a simple README for MediaTek MAINTAINERS: add an entry for MediaTek Weijie Gao (2): arm: MediaTek: add basic support for MT7623 boards mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC MAINTAINERS | 20 + Makefile | 20 + arch/arm/Kconfig | 16 + arch/arm/Makefile |1 + arch/arm/dts/Makefile |4 + arch/arm/dts/mt7623.dtsi | 255 + arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 arch/arm/dts/mt7629-rfb-u-boot.dtsi | 24 + arch/arm/dts/mt7629-rfb.dts | 70 ++ arch/arm/dts/mt7629.dtsi | 244 + arch/arm/include/asm/arch-mediatek/gpio.h |9 + arch/arm/include/asm/arch-mediatek/misc.h | 17 + arch/arm/mach-mediatek/Kconfig| 39 + arch/arm/mach-mediatek/Makefile |7 + arch/arm/mach-mediatek/cpu.c | 34 + arch/arm/mach-mediatek/init.h | 11 + arch/arm/mach-mediatek/mt7623/Makefile|4 + arch/arm/mach-mediatek/mt7623/init.c | 54 + arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 + arch/arm/mach-mediatek/mt7623/preloader.h | 99 ++ arch/arm/mach-mediatek/mt7629/Makefile|4 + arch/arm/mach-mediatek/mt7629/init.c | 128 +++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 + arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7623/Kconfig | 13 + board/mediatek/mt7623/MAINTAINERS |7 + board/mediatek/mt7623/Makefile|3 + board/mediatek/mt7623/mt7623_rfb.c| 16 + board/mediatek/mt7629/Kconfig | 17 + board/mediatek/mt7629/MAINTAINERS |7 + board/mediatek/mt7629/Makefile|3 + board/mediatek/mt7629/mt7629_rfb.c| 16 + common/image.c|1 + configs/mt7623n_bpir2_defconfig | 54 + configs/mt7629_rfb_defconfig | 73 ++ doc/README.mediatek | 221 drivers/clk/Makefile |1 + drivers/clk/mediatek/Makefile |7 + drivers/clk/mediatek/clk-mt7623.c | 870 +++ drivers/clk/mediatek/clk-mt7629.c | 709 + drivers/clk/mediatek/clk-mtk.c| 493 + drivers/clk/mediatek/clk-mtk.h| 194 drivers/mmc/Kconfig | 11 + drivers/mmc/Makefile |1 + drivers/mmc/mtk-sd.c | 1394 + drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/mediatek/Kconfig | 15 + drivers/pinctrl/mediatek/Makefile |7 + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +++ drivers/pinctrl/mediatek/pinctrl-mt7629.c | 471 + drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 553 ++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 184 drivers/power/domain/Kconfig |7 + drivers/power/domain/Makefile |1 + drivers/power/domain/mtk-power-domain.c | 406 +++ drivers/ram/Makefile |1 + drivers/ram/mediatek/Makefile |7 + drivers/ram/mediatek/ddr3-mt7629.c| 766 ++ drivers/serial/ns16550.c | 10 + drivers/timer/Kconfig |7 + drivers/timer/Makefile|1 + drivers/timer/mtk_timer.c | 85 ++ drivers/watchdog/Kconfig |
[U-Boot] [PATCH v4 05/18] arm: MediaTek: add basic support for MT7623 boards
From: Weijie Gao
This adds a general board file based on MT7623 SoCs from MediaTek.
As this u-boot is loaded by MTK proprietary preloader, there is no
low level initializtion codes.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
Changes since v4:
-Add gd->bd->bi_boot_params for legacy method - ATAGs.
---
arch/arm/mach-mediatek/Kconfig| 13
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7623/Makefile| 4 ++
arch/arm/mach-mediatek/mt7623/init.c | 54 +++
arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++
arch/arm/mach-mediatek/mt7623/preloader.h | 99 +++
board/mediatek/mt7623/Kconfig | 13
board/mediatek/mt7623/MAINTAINERS | 7 ++
board/mediatek/mt7623/Makefile| 3 +
board/mediatek/mt7623/mt7623_rfb.c| 16 +
configs/mt7623n_bpir2_defconfig | 54 +++
include/configs/mt7623.h | 56 +++
12 files changed, 342 insertions(+)
create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7623/init.c
create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S
create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h
create mode 100644 board/mediatek/mt7623/Kconfig
create mode 100644 board/mediatek/mt7623/MAINTAINERS
create mode 100644 board/mediatek/mt7623/Makefile
create mode 100644 board/mediatek/mt7623/mt7623_rfb.c
create mode 100644 configs/mt7623n_bpir2_defconfig
create mode 100644 include/configs/mt7623.h
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index d2ada97..7a733e9 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -9,6 +9,18 @@ config SYS_VENDOR
choice
prompt "MediaTek board select"
+config TARGET_MT7623
+ bool "MediaTek MT7623 SoC"
+ select CPU_V7A
+ select ARCH_MISC_INIT
+ help
+ The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
+ including NEON and GPU, Mali-450 graphics, several DDR3 options,
+ crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
+ video interfaces supporting HDMI and MIPI, and video codec support.
+ Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
+ I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
+
config TARGET_MT7629
bool "MediaTek MT7629 SoC"
select CPU_V7A
@@ -21,6 +33,7 @@ config TARGET_MT7629
endchoice
+source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 852d330..b5d3a37 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,4 +3,5 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
+obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
diff --git a/arch/arm/mach-mediatek/mt7623/Makefile
b/arch/arm/mach-mediatek/mt7623/Makefile
new file mode 100644
index 000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7623/init.c
b/arch/arm/mach-mediatek/mt7623/init.c
new file mode 100644
index 000..0ee8c66
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/init.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "preloader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct boot_argument *preloader_param;
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ u32 i;
+
+ if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ ((size_t)preloader_param % sizeof(size_t) == 0) &&
+ preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
+ preloader_param->dram_rank_num <=
+ ARRAY_SIZE(preloader_param->dram_rank_size)) {
+ gd->ram_size = 0;
+
+ for (i = 0; i < preloader_param->dram_rank_num; i++)
+ gd->ram_size += preloader_param->dram_rank_size[i];
+ } else {
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ SZ_2G);
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ void __iomem *chipid;
+ u32 swver;
+
+ chipid = ioremap(VER_BASE, VER_SIZE);
+ swver = readl(chipid + APSW_VER);
+
+ printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1);
+
+ return 0;
+}
diff --git a/arch/arm/mach-mediatek/mt7623/
[U-Boot] [PATCH v4 18/18] MAINTAINERS: add an entry for MediaTek
This patch adds an entry for MediaTek. Signed-off-by: Ryder Lee Reviewed-by: Simon Glass --- Changes since v4: None --- MAINTAINERS | 20 1 file changed, 20 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf8f73f..9940200 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -157,6 +157,26 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM MEDIATEK +M: Ryder Lee +M: Weijie Gao +S: Maintained +F: arch/arm/mach-mediatek/ +F: arch/arm/include/asm/arch-mediatek/ +F: board/mediatek/ +F: doc/README.mediatek +F: drivers/clk/mediatek/ +F: drivers/mmc/mtk-sd.c +F: drivers/pinctrl/mediatek/ +F: drivers/power/domain/mtk-power-domain.c +F: drivers/ram/mediatek/ +F: drivers/spi/mtk_qspi.c +F: drivers/timer/mtk_timer.c +F: drivers/watchdog/mtk_wdt.c +F: tools/mtk_image.c +F: tools/mtk_image.h +N: mediatek + ARM OWL M: Manivannan Sadhasivam S: Maintained -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 01/18] tools: MediaTek: add MTK boot header generation to mkimage
This patch adds support for MTK boot image generation.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v4: None
---
Makefile | 20 ++
common/image.c | 1 +
include/image.h | 1 +
scripts/Makefile.spl | 11 +
tools/Makefile | 1 +
tools/mtk_image.c| 749 +++
tools/mtk_image.h| 199 ++
7 files changed, 982 insertions(+)
create mode 100644 tools/mtk_image.c
create mode 100644 tools/mtk_image.h
diff --git a/Makefile b/Makefile
index 250eb6c..5a384c8 100644
--- a/Makefile
+++ b/Makefile
@@ -852,6 +852,8 @@ ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin
endif
+ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
+
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
@@ -1359,6 +1361,24 @@ u-boot.elf: u-boot.bin
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+# MediaTek's ARM-based u-boot needs a header to contains its load address
+# which is parsed by the BootROM.
+# If the SPL build is enabled, the header will be added to the spl binary,
+# and the spl binary and the u-boot.img will be combined into one file.
+# Otherwise the header will be added to the u-boot.bin directly.
+
+ifeq ($(CONFIG_SPL),y)
+u-boot-mtk.bin: u-boot.dtb u-boot.img spl/u-boot-spl-mtk.bin FORCE
+ $(call if_changed,binman)
+else
+MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+u-boot-mtk.bin: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+endif
+
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
diff --git a/common/image.c b/common/image.c
index 1c3a772..d3f9914 100644
--- a/common/image.c
+++ b/common/image.c
@@ -166,6 +166,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT"
},
{ IH_TYPE_PMMC,"pmmc","TI Power Management
Micro-Controller Firmware",},
{ IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32
Image" },
+ { IH_TYPE_MTKIMAGE, "mtk_image", "MeidaTek BootROM loadable
Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 031c355..8dd7247 100644
--- a/include/image.h
+++ b/include/image.h
@@ -278,6 +278,7 @@ enum {
IH_TYPE_PMMC,/* TI Power Management Micro-Controller
Firmware */
IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
IH_TYPE_SOCFPGAIMAGE_V1,/* Altera SOCFPGA A10 Preloader */
+ IH_TYPE_MTKIMAGE, /* MeidaTek BootROM loadable Image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7416abe..22bd8f7 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -219,6 +219,8 @@ ALL-$(CONFIG_SPL_X86_16BIT_INIT) +=
$(obj)/u-boot-x86-16bit-spl.bin
ALL-$(CONFIG_ARCH_ZYNQ)+= $(obj)/boot.bin
ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_MEDIATEK)+= $(obj)/u-boot-spl-mtk.bin
+
all: $(ALL-y)
quiet_cmd_cat = CAT $@
@@ -349,6 +351,15 @@ cmd_sunxi_spl_image_builder =
$(objtree)/tools/sunxi-spl-image-builder \
$(obj)/sunxi-spl-with-ecc.bin: $(obj)/sunxi-spl.bin
$(call if_changed,sunxi_spl_image_builder)
+
+# MediaTek's specific SPL build
+MKIMAGEFLAGS_u-boot-spl-mtk.bin = -T mtk_image \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+$(obj)/u-boot-spl-mtk.bin: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
# Rule to link u-boot-spl
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot-spl ?= LD $@
diff --git a/tools/Makefile b/tools/Makefile
index 3c0521f..c93d17a 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -116,6 +116,7 @@ dumpimage-mkimage-objs := aisimage.o \
$(LIBFDT_OBJS) \
gpimage.o \
gpimage-common.o \
+ mtk_image.o \
$(RSA_OBJS-y)
dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
new file mode 100644
index 000..2706d2d
--- /dev/null
+++ b/tools/mtk_image.c
@@ -0,0 +1,749 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generate MediaTek BootROM header for SPL/U-Boot images
[U-Boot] [PATCH v4 02/18] arm: dts: MediaTek: add device tree for MT7629
This patch adds MT7629 device tree and the includes it needs.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v4: None
---
arch/arm/dts/Makefile| 3 +
arch/arm/dts/mt7629-rfb-u-boot.dtsi | 24 +++
arch/arm/dts/mt7629-rfb.dts | 70 +
arch/arm/dts/mt7629.dtsi | 244 +++
include/dt-bindings/clock/mt7629-clk.h | 206 ++
include/dt-bindings/power/mt7629-power.h | 13 ++
6 files changed, 560 insertions(+)
create mode 100644 arch/arm/dts/mt7629-rfb-u-boot.dtsi
create mode 100644 arch/arm/dts/mt7629-rfb.dts
create mode 100644 arch/arm/dts/mt7629.dtsi
create mode 100644 include/dt-bindings/clock/mt7629-clk.h
create mode 100644 include/dt-bindings/power/mt7629-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d36447d..2001e63 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -558,6 +558,9 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7629-rfb.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi
b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
new file mode 100644
index 000..1ef5568
--- /dev/null
+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+/ {
+ binman {
+ filename = "u-boot-mtk.bin";
+ pad-byte = <0xff>;
+
+#ifdef CONFIG_SPL
+ blob {
+ filename = "spl/u-boot-spl-mtk.bin";
+ size = ;
+ };
+
+ u-boot-img {
+ };
+#endif
+ };
+};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
new file mode 100644
index 000..a6d28a0
--- /dev/null
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7629.dtsi"
+
+/ {
+ model = "MediaTek MT7629 RFB";
+ compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
+
+ aliases {
+ spi0 =
+ };
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+};
+
+ {
+ qspi_pins: qspi-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0-default {
+ mux {
+ function = "uart";
+ groups = "uart0_txd_rxd";
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "spi-flash";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
new file mode 100644
index 000..f7966cb
--- /dev/null
+++ b/arch/arm/dts/mt7629.dtsi
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7629";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <125000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clock-frequency = <125000>;
+ };
+ };
+
+ clk20m: oscillator@0 {
+ compatible
[U-Boot] [PATCH v4 10/18] pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v4:
-mtk_pinctrl_probe() is a common function called by all probe functions,
so rename it to mtk_pinctrl_common_probe().
---
arch/arm/include/asm/arch-mediatek/gpio.h | 9 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 11 +
drivers/pinctrl/mediatek/Makefile | 6 +
drivers/pinctrl/mediatek/pinctrl-mt7629.c | 471 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 553 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +
8 files changed, 1234 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h
b/arch/arm/include/asm/arch-mediatek/gpio.h
new file mode 100644
index 000..4ea1020
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_GPIO_H
+#define __MEDIATEK_GPIO_H
+
+#endif /* __MEDIATEK_GPIO_H */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8da..7e6fad3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -301,6 +301,7 @@ config ASPEED_AST2500_PINCTRL
endif
source "drivers/pinctrl/meson/Kconfig"
+source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d..293bad3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-$(CONFIG_PINCTRL_MTK) += mediatek/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 000..e0145b1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MEDIATEK
+
+config PINCTRL_MTK
+ depends on PINCTRL_GENERIC
+ bool
+
+config PINCTRL_MT7629
+ bool "MT7629 SoC pinctrl driver"
+ select PINCTRL_MTK
+
+endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 000..cbf0765
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
new file mode 100644
index 000..9558c3b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -0,0 +1,471 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+
+#define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
+
+static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
+ PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
+ PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
+ PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
+ PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
+ PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1
[U-Boot] [PATCH v4 17/18] doc: README.mediatek: Add a simple README for MediaTek
Add a few notes on how to try out the MediaTek support so far. Signed-off-by: Ryder Lee --- Changes since v4: -Add instructions on how to prepare SD card and write to SNOR flash. -Fix typo. --- doc/README.mediatek | 221 1 file changed, 221 insertions(+) create mode 100644 doc/README.mediatek diff --git a/doc/README.mediatek b/doc/README.mediatek new file mode 100644 index 000..5b8e3e9 --- /dev/null +++ b/doc/README.mediatek @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 MediaTek Inc. +# Ryder Lee + + +This document describes how to compile the U-Boot and how to change U-Boot +configuration about the MediaTek SoCs. + + +Build Procedure +=== + -Set the cross compiler: + + # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi- + + -Clean-up old residuals: + + # make mrproper + + -Configure the U-Boot: + + # make + # make + + - For the MT7623n bananapi R2 board use "mt7623n_bpir2_defconfig" + - For the MT7629 reference board use "mt7629_rfb_defconfig" + + +Boot sequence += + -Bootrom -> MTK preloader -> U-Boot + + - MT7623n + + This version of U-Boot doesn't implement SPL. So, MTK preloader binary + is needed to boot up: + + https://github.com/BPI-SINOVOIP/BPI-R2-bsp/tree/master/mt-pack/mtk/bpi-r2/bin + + + -Bootrom -> SPL -> U-Boot + + - MT7629 + + +Configuration update + + To update the U-Boot configuration, please refer to doc/README.kconfig + + +MediaTek image header += +Currently there are two image headers used for MediaTek chips: + + - BootROM image header. This header is used by the first stage bootloader. It records + the desired compatible boot device, integrity information and its load address. + + The on-chip BootROM will firstly verify integrity and compatibility of the bootloader. + + If verification passed, the BootROM will then load the bootloader into on-chip SRAM, + and pass control to it. + + Note that this header is actually a combination of three independent headers: + Device header, BRLYT header and GFH header. + + Used by U-Boot SPL of MT7629 and preloader of MT7623. + + + - MediaTek legacy image header. This header was originally used by the legacy image. It + basically records the load address, image size and image name. + + After all low level initializations passed, the preloader will locate the LK image and + load it into DRAM, and pass control to it. + + Now this header is used by U-Boot of MT7623. + + +To generate these two headers with mkimage: + + # mkimage -T mtk_image -a -n -d + + - mtk_image means using MediaTek's header generation method. + + + - load_addr is the load address of this image. + For first stage bootloader like U-Boot SPL or preloader, it usually points to the + on-chip SRAM. + + For second stage bootloader like U-Boot, it usually points to the DRAM. + + + - option_string contains options to generate the header. + + The option string is using the follow format: + key1=value1;key2=value2;... + + The following key names are valid: + lk: If lk=1, LK image header is used. Otherwise BootROM image header is used. + + lkname: The name of the LK image header. The maximum length is 32. + The default value is "U-Boot". + + media: Desired boot device. The valid values are: + nand : Parallel NAND + snand: Serial NAND + nor : Serial NOR + emmc : eMMC + sdmmc: SD + + nandinfo: Desired NAND device type, a combination of page size, oob size and +optional device capacity. Valid types are: + 2k+64: for Serial NAND, 2KiB page size + 64B oob size + 2k+120 : for Serial NAND, 2KiB page size + 120B oob size + 2k+128 : for Serial NAND, 2KiB page size + 128B oob size + 4k+256 : for Serial NAND, 4KiB page size + 256B oob size + 1g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 1Gbit size + 2g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 2Gbit size + 4g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 4Gbit size + 2g:2k+128: for Parallel NAND, 2KiB page size + 128B oob size, total 2Gbit size + 4g:2k+128: for Parallel NAND, 2KiB page size + 128B oob size, total 4Gbit size + + +MT7629 partitions on Serial NOR +=== + + Start End
[U-Boot] [PATCH v4 11/18] pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v4:
-Add a comment to the exported function - mtk_rmw()
---
drivers/pinctrl/mediatek/Kconfig |4 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.h |2 +
4 files changed, 1291 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index e0145b1..1bd9a92 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -4,6 +4,10 @@ config PINCTRL_MTK
depends on PINCTRL_GENERIC
bool
+config PINCTRL_MT7623
+ bool "MT7623 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index cbf0765..f6ef362 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
new file mode 100644
index 000..fd37dfa
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -0,0 +1,1284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_BOND_REG0 0xb10
+#define PIN_BOND_REG1 0xf20
+#define PIN_BOND_REG2 0xef0
+#define BOND_PCIE_CLR (0x77 << 3)
+#define BOND_I2S_CLR 0x3
+#define BOND_MSDC0E_CLR0x1
+
+#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 15, false)
+
+#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, true)
+
+static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
+ PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
+ PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
+ PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
+ PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
+ PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
+ PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
+ PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
+ PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
+ PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
+ PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
+ PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
+ PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
+ PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
+ PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
+ PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
+ PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
+ PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
+ PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
+ PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
+ PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
+ PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
+ PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
+ PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
+ PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
+ PIN_FIELD16(116, 116, 0xcd0,
[U-Boot] [PATCH v5 06/18] clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v5: None
Changes since v4
-Add a __common_ infix on the shared funcitons to make them clear.
(i.e., mtk_clk_init() -> mtk_common_clk_init())
---
drivers/clk/Makefile | 1 +
drivers/clk/mediatek/Makefile | 6 +
drivers/clk/mediatek/clk-mt7629.c | 709 ++
drivers/clk/mediatek/clk-mtk.c| 493 ++
drivers/clk/mediatek/clk-mtk.h| 194 +++
5 files changed, 1403 insertions(+)
create mode 100644 drivers/clk/mediatek/Makefile
create mode 100644 drivers/clk/mediatek/clk-mt7629.c
create mode 100644 drivers/clk/mediatek/clk-mtk.c
create mode 100644 drivers/clk/mediatek/clk-mtk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 821b586..c128538 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-y += imx/
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
new file mode 100644
index 000..297f99d
--- /dev/null
+++ b/drivers/clk/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
+
+# SoC Drivers
+obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk/mediatek/clk-mt7629.c
new file mode 100644
index 000..2601b6c
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -0,0 +1,709 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7629_CLKSQ_STB_CON0 0x20
+#define MT7629_PLL_ISO_CON00x2c
+#define MT7629_PLL_FMAX(2500UL * MHZ)
+#define MT7629_CON0_RST_BARBIT(24)
+
+#define MCU_AXI_DIV0x640
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX0x7c0
+#define MCU_BUS_MSKGENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7629_CON0_RST_BAR,\
+ .fmax = MT7629_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed
[U-Boot] [PATCH v5 03/18] arm: dts: MediaTek: add device tree for MT7623
This adds device tree for MT7623 development board - Bananapi R2
Detailed hardware information for BPI-R2 which could be found on
http://wiki.banana-pi.org/Banana_Pi_BPI-R2.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v5: Use new compatible 'mediatek,hsuart' for MTK UART
Changes since v4: None
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/mt7623.dtsi | 255 +++
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207
include/dt-bindings/clock/mt7623-clk.h | 413 +++
include/dt-bindings/power/mt7623-power.h | 19 ++
5 files changed, 895 insertions(+)
create mode 100644 arch/arm/dts/mt7623.dtsi
create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
create mode 100644 include/dt-bindings/clock/mt7623-clk.h
create mode 100644 include/dt-bindings/power/mt7623-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2001e63..4b30ef9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -559,6 +559,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
new file mode 100644
index 000..f50f4ef
--- /dev/null
+++ b/arch/arm/dts/mt7623.dtsi
@@ -0,0 +1,255 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7623";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <1300>;
+ #clock-cells = <0>;
+ };
+
+ rtc32k: oscillator-1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
+ };
+
+ clk26m: oscillator-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ clock-output-names = "clk26m";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
[U-Boot] [PATCH v5 01/18] tools: MediaTek: add MTK boot header generation to mkimage
This patch adds support for MTK boot image generation.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v5: Fix typo
Changes since v4: None
---
Makefile | 20 ++
common/image.c | 1 +
include/image.h | 1 +
scripts/Makefile.spl | 11 +
tools/Makefile | 1 +
tools/mtk_image.c| 749 +++
tools/mtk_image.h| 199 ++
7 files changed, 982 insertions(+)
create mode 100644 tools/mtk_image.c
create mode 100644 tools/mtk_image.h
diff --git a/Makefile b/Makefile
index 552687d..a5d0c1b 100644
--- a/Makefile
+++ b/Makefile
@@ -852,6 +852,8 @@ ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin
endif
+ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
+
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
@@ -1359,6 +1361,24 @@ u-boot.elf: u-boot.bin
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+# MediaTek's ARM-based u-boot needs a header to contains its load address
+# which is parsed by the BootROM.
+# If the SPL build is enabled, the header will be added to the spl binary,
+# and the spl binary and the u-boot.img will be combined into one file.
+# Otherwise the header will be added to the u-boot.bin directly.
+
+ifeq ($(CONFIG_SPL),y)
+u-boot-mtk.bin: u-boot.dtb u-boot.img spl/u-boot-spl-mtk.bin FORCE
+ $(call if_changed,binman)
+else
+MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+u-boot-mtk.bin: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+endif
+
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
diff --git a/common/image.c b/common/image.c
index 1c3a772..0659133 100644
--- a/common/image.c
+++ b/common/image.c
@@ -166,6 +166,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT"
},
{ IH_TYPE_PMMC,"pmmc","TI Power Management
Micro-Controller Firmware",},
{ IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32
Image" },
+ { IH_TYPE_MTKIMAGE, "mtk_image", "MediaTek BootROM loadable
Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 031c355..f67502e 100644
--- a/include/image.h
+++ b/include/image.h
@@ -278,6 +278,7 @@ enum {
IH_TYPE_PMMC,/* TI Power Management Micro-Controller
Firmware */
IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
IH_TYPE_SOCFPGAIMAGE_V1,/* Altera SOCFPGA A10 Preloader */
+ IH_TYPE_MTKIMAGE, /* MediaTek BootROM loadable Image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7416abe..22bd8f7 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -219,6 +219,8 @@ ALL-$(CONFIG_SPL_X86_16BIT_INIT) +=
$(obj)/u-boot-x86-16bit-spl.bin
ALL-$(CONFIG_ARCH_ZYNQ)+= $(obj)/boot.bin
ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_MEDIATEK)+= $(obj)/u-boot-spl-mtk.bin
+
all: $(ALL-y)
quiet_cmd_cat = CAT $@
@@ -349,6 +351,15 @@ cmd_sunxi_spl_image_builder =
$(objtree)/tools/sunxi-spl-image-builder \
$(obj)/sunxi-spl-with-ecc.bin: $(obj)/sunxi-spl.bin
$(call if_changed,sunxi_spl_image_builder)
+
+# MediaTek's specific SPL build
+MKIMAGEFLAGS_u-boot-spl-mtk.bin = -T mtk_image \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+$(obj)/u-boot-spl-mtk.bin: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
# Rule to link u-boot-spl
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot-spl ?= LD $@
diff --git a/tools/Makefile b/tools/Makefile
index 3c0521f..c93d17a 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -116,6 +116,7 @@ dumpimage-mkimage-objs := aisimage.o \
$(LIBFDT_OBJS) \
gpimage.o \
gpimage-common.o \
+ mtk_image.o \
$(RSA_OBJS-y)
dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
diff --git a/tools/mtk_image.c b/tools/mtk_image.c
new file mode 100644
index 000..2706d2d
--- /dev/null
+++ b/tools/mtk_image.c
@@ -0,0 +1,749 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generate MediaTek BootROM hea
[U-Boot] [PATCH v5 02/18] arm: dts: MediaTek: add device tree for MT7629
This patch adds MT7629 device tree and the includes it needs.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v5: Use new compatible 'mediatek,hsuart' for MTK UART
Changes since v4: None
---
arch/arm/dts/Makefile| 3 +
arch/arm/dts/mt7629-rfb-u-boot.dtsi | 24 +++
arch/arm/dts/mt7629-rfb.dts | 70 +
arch/arm/dts/mt7629.dtsi | 244 +++
include/dt-bindings/clock/mt7629-clk.h | 206 ++
include/dt-bindings/power/mt7629-power.h | 13 ++
6 files changed, 560 insertions(+)
create mode 100644 arch/arm/dts/mt7629-rfb-u-boot.dtsi
create mode 100644 arch/arm/dts/mt7629-rfb.dts
create mode 100644 arch/arm/dts/mt7629.dtsi
create mode 100644 include/dt-bindings/clock/mt7629-clk.h
create mode 100644 include/dt-bindings/power/mt7629-power.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d36447d..2001e63 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -558,6 +558,9 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7629-rfb.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi
b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
new file mode 100644
index 000..1ef5568
--- /dev/null
+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+/ {
+ binman {
+ filename = "u-boot-mtk.bin";
+ pad-byte = <0xff>;
+
+#ifdef CONFIG_SPL
+ blob {
+ filename = "spl/u-boot-spl-mtk.bin";
+ size = ;
+ };
+
+ u-boot-img {
+ };
+#endif
+ };
+};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
new file mode 100644
index 000..a6d28a0
--- /dev/null
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -0,0 +1,70 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+#include "mt7629.dtsi"
+
+/ {
+ model = "MediaTek MT7629 RFB";
+ compatible = "mediatek,mt7629-rfb", "mediatek,mt7629";
+
+ aliases {
+ spi0 =
+ };
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+};
+
+ {
+ qspi_pins: qspi-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0-default {
+ mux {
+ function = "uart";
+ groups = "uart0_txd_rxd";
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+
+ spi-flash@0{
+ compatible = "spi-flash";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
new file mode 100644
index 000..e6052bb
--- /dev/null
+++ b/arch/arm/dts/mt7629.dtsi
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7629";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clock-frequency = <125000>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clock-frequency = <125000>;
+
[U-Boot] [PATCH v5 05/18] arm: MediaTek: add basic support for MT7623 boards
From: Weijie Gao
This adds a general board file based on MT7623 SoCs from MediaTek.
As this u-boot is loaded by MTK proprietary preloader, there is no
low level initializtion codes.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
Changes since v5: None
Changes since v4:
-Add gd->bd->bi_boot_params for legacy method - ATAGs.
---
arch/arm/mach-mediatek/Kconfig| 13
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7623/Makefile| 4 ++
arch/arm/mach-mediatek/mt7623/init.c | 54 +++
arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++
arch/arm/mach-mediatek/mt7623/preloader.h | 99 +++
board/mediatek/mt7623/Kconfig | 13
board/mediatek/mt7623/MAINTAINERS | 7 ++
board/mediatek/mt7623/Makefile| 3 +
board/mediatek/mt7623/mt7623_rfb.c| 16 +
configs/mt7623n_bpir2_defconfig | 54 +++
include/configs/mt7623.h | 56 +++
12 files changed, 342 insertions(+)
create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7623/init.c
create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S
create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h
create mode 100644 board/mediatek/mt7623/Kconfig
create mode 100644 board/mediatek/mt7623/MAINTAINERS
create mode 100644 board/mediatek/mt7623/Makefile
create mode 100644 board/mediatek/mt7623/mt7623_rfb.c
create mode 100644 configs/mt7623n_bpir2_defconfig
create mode 100644 include/configs/mt7623.h
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index d2ada97..7a733e9 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -9,6 +9,18 @@ config SYS_VENDOR
choice
prompt "MediaTek board select"
+config TARGET_MT7623
+ bool "MediaTek MT7623 SoC"
+ select CPU_V7A
+ select ARCH_MISC_INIT
+ help
+ The MediaTek MT7623 is a ARM-based SoC with a quad-core Cortex-A7
+ including NEON and GPU, Mali-450 graphics, several DDR3 options,
+ crypto engine, built-in Wi-Fi / Bluetooth combo chip, JPEG decoder,
+ video interfaces supporting HDMI and MIPI, and video codec support.
+ Peripherals include Gigabit Ethernet, switch, USB3.0 and OTG, PCIe,
+ I2S, PCM, S/PDIF, UART, SPI, I2C, IR TX/RX, and PWM.
+
config TARGET_MT7629
bool "MediaTek MT7629 SoC"
select CPU_V7A
@@ -21,6 +33,7 @@ config TARGET_MT7629
endchoice
+source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 852d330..b5d3a37 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,4 +3,5 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
+obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
diff --git a/arch/arm/mach-mediatek/mt7623/Makefile
b/arch/arm/mach-mediatek/mt7623/Makefile
new file mode 100644
index 000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7623/init.c
b/arch/arm/mach-mediatek/mt7623/init.c
new file mode 100644
index 000..0ee8c66
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/init.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "preloader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct boot_argument *preloader_param;
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ u32 i;
+
+ if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ ((size_t)preloader_param % sizeof(size_t) == 0) &&
+ preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
+ preloader_param->dram_rank_num <=
+ ARRAY_SIZE(preloader_param->dram_rank_size)) {
+ gd->ram_size = 0;
+
+ for (i = 0; i < preloader_param->dram_rank_num; i++)
+ gd->ram_size += preloader_param->dram_rank_size[i];
+ } else {
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ SZ_2G);
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ void __iomem *chipid;
+ u32 swver;
+
+ chipid = ioremap(VER_BASE, VER_SIZE);
+ swver = readl(chipid + APSW_VER);
+
+ printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1);
+
+ return 0;
+}
diff --git a/a
[U-Boot] [PATCH v5 16/18] mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC
From: Weijie Gao This patch adds MT7623 host controller driver for accessing SD/MMC. Cc: Jaehoon Chung Signed-off-by: Weijie Gao Signed-off-by: Ryder Lee Tested-by: Matthias Brugger Reviewed-by: Simon Glass --- Changes since v5: None Changes since v4: None --- drivers/mmc/Kconfig | 11 + drivers/mmc/Makefile |1 + drivers/mmc/mtk-sd.c | 1394 ++ 3 files changed, 1406 insertions(+) create mode 100644 drivers/mmc/mtk-sd.c diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 27246ee..ea60ed5 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -598,6 +598,17 @@ config FTSDC010_SDIO help This can enable ftsdc010 sdio function. +config MMC_MTK + bool "MediaTek SD/MMC Card Interface support" + depends on ARCH_MEDIATEK + depends on BLK && DM_MMC + depends on OF_CONTROL + help + This selects the MediaTek(R) Secure digital and Multimedia card Interface. + If you have a machine with a integrated SD/MMC card reader, say Y or M here. + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. + endif config TEGRA124_MMC_DISABLE_EXT_LOOPBACK diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 23c5b0d..801a26d 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += tmio-common.o uniphier-sd.o obj-$(CONFIG_RENESAS_SDHI) += tmio-common.o renesas-sdhi.o obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o +obj-$(CONFIG_MMC_MTK) += mtk-sd.o diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c new file mode 100644 index 000..0741a52 --- /dev/null +++ b/drivers/mmc/mtk-sd.c @@ -0,0 +1,1394 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek SD/MMC Card Interface driver + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Weijie Gao + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* MSDC_CFG */ +#define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) +#define MSDC_CFG_CKMOD_EXT_M 0x30 +#define MSDC_CFG_CKMOD_EXT_S 20 +#define MSDC_CFG_CKDIV_EXT_M 0xfff00 +#define MSDC_CFG_CKDIV_EXT_S 8 +#define MSDC_CFG_HS400_CK_MODE BIT(18) +#define MSDC_CFG_CKMOD_M 0x3 +#define MSDC_CFG_CKMOD_S 16 +#define MSDC_CFG_CKDIV_M 0xff00 +#define MSDC_CFG_CKDIV_S 8 +#define MSDC_CFG_CKSTB BIT(7) +#define MSDC_CFG_PIO BIT(3) +#define MSDC_CFG_RST BIT(2) +#define MSDC_CFG_CKPDN BIT(1) +#define MSDC_CFG_MODE BIT(0) + +/* MSDC_IOCON */ +#define MSDC_IOCON_W_DSPL BIT(8) +#define MSDC_IOCON_DSPLBIT(2) +#define MSDC_IOCON_RSPLBIT(1) + +/* MSDC_PS */ +#define MSDC_PS_DAT0 BIT(16) +#define MSDC_PS_CDDBCE_M 0xf000 +#define MSDC_PS_CDDBCE_S 12 +#define MSDC_PS_CDSTS BIT(1) +#define MSDC_PS_CDEN BIT(0) + +/* #define MSDC_INT(EN) */ +#define MSDC_INT_ACMDRDY BIT(3) +#define MSDC_INT_ACMDTMO BIT(4) +#define MSDC_INT_ACMDCRCERRBIT(5) +#define MSDC_INT_CMDRDYBIT(8) +#define MSDC_INT_CMDTMOBIT(9) +#define MSDC_INT_RSPCRCERR BIT(10) +#define MSDC_INT_XFER_COMPLBIT(12) +#define MSDC_INT_DATTMOBIT(14) +#define MSDC_INT_DATCRCERR BIT(15) + +/* MSDC_FIFOCS */ +#define MSDC_FIFOCS_CLRBIT(31) +#define MSDC_FIFOCS_TXCNT_M0xff +#define MSDC_FIFOCS_TXCNT_S16 +#define MSDC_FIFOCS_RXCNT_M0xff +#define MSDC_FIFOCS_RXCNT_S0 + +/* #define SDC_CFG */ +#define SDC_CFG_DTOC_M 0xff00 +#define SDC_CFG_DTOC_S 24 +#define SDC_CFG_SDIOIDEBIT(20) +#define SDC_CFG_SDIO BIT(19) +#define SDC_CFG_BUSWIDTH_M 0x3 +#define SDC_CFG_BUSWIDTH_S 16 + +/* SDC_CMD */ +#define SDC_CMD_BLK_LEN_M 0xfff +#define SDC_CMD_BLK_LEN_S 16 +#define SDC_CMD_STOP BIT(14) +#define SDC_CMD_WR BIT(13) +#define SDC_CMD_DTYPE_M0x1800 +#define SDC_CMD_DTYPE_S11 +#define SDC_CMD_RSPTYP_M 0x380 +#define SDC_CMD_RSPTYP_S 7 +#define SDC_CMD_CMD_M 0x3f +#define SDC_CMD_CMD_S 0 + +/* SDC_STS */ +#define SDC_STS_CMDBUSYBIT(1) +#define SDC_STS_SDCBUSYBIT(0)
[U-Boot] [PATCH v5 13/18] power domain: MediaTek: add power domain driver for MT7623 SoC
This adds power domain (scpsys) support for MT7623 SoC.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v5: None
Changes since v4: None
---
drivers/power/domain/mtk-power-domain.c | 80 +
1 file changed, 80 insertions(+)
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
index ed4a718..c67e880 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -14,9 +14,19 @@
#include
#include
+#include
#include
#define SPM_EN (0xb16 << 16 | 0x1)
+#define SPM_VDE_PWR_CON0x0210
+#define SPM_MFG_PWR_CON0x0214
+#define SPM_ISP_PWR_CON0x0238
+#define SPM_DIS_PWR_CON0x023c
+#define SPM_CONN_PWR_CON 0x0280
+#define SPM_BDP_PWR_CON0x029c
+#define SPM_ETH_PWR_CON0x02a0
+#define SPM_HIF_PWR_CON0x02a4
+#define SPM_IFR_MSC_PWR_CON0x02a8
#define SPM_ETHSYS_PWR_CON 0x2e0
#define SPM_HIF0_PWR_CON 0x2e4
#define SPM_HIF1_PWR_CON 0x2e8
@@ -29,6 +39,15 @@
#define PWR_ON_2ND_BIT BIT(3)
#define PWR_CLK_DIS_BITBIT(4)
+#define PWR_STATUS_CONNBIT(1)
+#define PWR_STATUS_DISPBIT(3)
+#define PWR_STATUS_MFG BIT(4)
+#define PWR_STATUS_ISP BIT(5)
+#define PWR_STATUS_VDECBIT(7)
+#define PWR_STATUS_BDP BIT(14)
+#define PWR_STATUS_ETH BIT(15)
+#define PWR_STATUS_HIF BIT(16)
+#define PWR_STATUS_IFR_MSC BIT(17)
#define PWR_STATUS_ETHSYS BIT(24)
#define PWR_STATUS_HIF0BIT(25)
#define PWR_STATUS_HIF1BIT(26)
@@ -41,6 +60,7 @@
#define DCM_TOP_EN BIT(0)
enum scp_domain_type {
+ SCPSYS_MT7623,
SCPSYS_MT7629,
};
@@ -62,6 +82,59 @@ struct scp_domain {
struct scp_domain_data *data;
};
+static struct scp_domain_data scp_domain_mt7623[] = {
+ [MT7623_POWER_DOMAIN_CONN] = {
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = SPM_CONN_PWR_CON,
+ .bus_prot_mask = BIT(8) | BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_DISP] = {
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = SPM_DIS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .bus_prot_mask = BIT(2),
+ },
+ [MT7623_POWER_DOMAIN_MFG] = {
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = SPM_MFG_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_VDEC] = {
+ .sta_mask = PWR_STATUS_VDEC,
+ .ctl_offs = SPM_VDE_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT7623_POWER_DOMAIN_ISP] = {
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = SPM_ISP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ },
+ [MT7623_POWER_DOMAIN_BDP] = {
+ .sta_mask = PWR_STATUS_BDP,
+ .ctl_offs = SPM_BDP_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ },
+ [MT7623_POWER_DOMAIN_ETH] = {
+ .sta_mask = PWR_STATUS_ETH,
+ .ctl_offs = SPM_ETH_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_HIF] = {
+ .sta_mask = PWR_STATUS_HIF,
+ .ctl_offs = SPM_HIF_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ },
+ [MT7623_POWER_DOMAIN_IFR_MSC] = {
+ .sta_mask = PWR_STATUS_IFR_MSC,
+ .ctl_offs = SPM_IFR_MSC_PWR_CON,
+ },
+};
+
static struct scp_domain_data scp_domain_mt7629[] = {
[MT7629_POWER_DOMAIN_ETHSYS] = {
.sta_mask = PWR_STATUS_ETHSYS,
@@ -252,6 +325,9 @@ static int mtk_power_domain_hook(struct udevice *dev)
scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
switch (scpd->type) {
+ case SCPSYS_MT7623:
+ scpd->data = scp_domain_mt7623;
+ break;
case SCPSYS_MT7629:
scpd->data = scp_domain_mt7629;
break;
@@ -303,6 +379,10 @@ static int mtk_power_domain_probe(struct udevice *dev)
static const struct udevice_id mtk_power_domain_ids[] = {
{
+ .compatible = "mediatek,mt7623-scpsys",
+ .data = SCPSYS_MT7623,
+ },
+ {
.compatible = "mediatek,mt7629-scpsys",
.data = SCPSYS_MT7629,
},
--
1.9.1
___
U-Boot m
[U-Boot] [PATCH v5 10/18] pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v5:
- remove unused pin macros
Changes since v4:
-mtk_pinctrl_probe() is a common function called by all probe functions,
so rename it to mtk_pinctrl_common_probe().
---
arch/arm/include/asm/arch-mediatek/gpio.h | 9 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 11 +
drivers/pinctrl/mediatek/Makefile | 6 +
drivers/pinctrl/mediatek/pinctrl-mt7629.c | 409 +++
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 553 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +
8 files changed, 1172 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h
b/arch/arm/include/asm/arch-mediatek/gpio.h
new file mode 100644
index 000..4ea1020
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_GPIO_H
+#define __MEDIATEK_GPIO_H
+
+#endif /* __MEDIATEK_GPIO_H */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8da..7e6fad3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -301,6 +301,7 @@ config ASPEED_AST2500_PINCTRL
endif
source "drivers/pinctrl/meson/Kconfig"
+source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d..293bad3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-$(CONFIG_PINCTRL_MTK) += mediatek/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 000..e0145b1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MEDIATEK
+
+config PINCTRL_MTK
+ depends on PINCTRL_GENERIC
+ bool
+
+config PINCTRL_MT7629
+ bool "MT7629 SoC pinctrl driver"
+ select PINCTRL_MTK
+
+endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 000..cbf0765
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
new file mode 100644
index 000..aa6d1c2
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+
+#define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
+
+static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
+ PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
+ PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
+ PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
+ PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
+ PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
+
[U-Boot] [PATCH v5 14/18] serial: MediaTek: add high-speed uart driver for MediaTek SoCs
Many SoCs from MediaTek have a high-speed uart. This UART is compatible
with the ns16550 in legacy mode. It has extra registers for high-speed
mode which can reach a maximum baudrate at 921600.
However this UART will no longer be compatible if it's in high-speed mode.
Some BootROM of MediaTek's SoCs will change the UART into high-speed mode
and the U-Boot must use this driver to initialize the UART.
Signed-off-by: Weijie Gao
Tested-by: Ryder Lee
---
Changes since v5: Add a specific driver for MTK UART
Changes since v4: None
---
drivers/serial/Kconfig | 20
drivers/serial/Makefile | 1 +
drivers/serial/serial_mtk.c | 268
3 files changed, 289 insertions(+)
create mode 100644 drivers/serial/serial_mtk.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 597db4b..7ab38b7 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -368,6 +368,16 @@ config DEBUG_UART_OMAP
You will need to provide parameters to make this work. The driver
will be available until the real driver model serial is running.
+config DEBUG_UART_MTK
+ bool "MediaTek High-speed UART"
+ depends on MTK_SERIAL
+ help
+ Select this to enable a debug UART using the MediaTek High-speed
+ UART driver.
+ You will need to provide parameters to make this work. The
+ driver will be available until the real driver model serial is
+ running.
+
endchoice
config DEBUG_UART_BASE
@@ -692,6 +702,16 @@ config ZYNQ_SERIAL
This driver supports the Cadence UART. It is found e.g. in Xilinx
Zynq/ZynqMP.
+config MTK_SERIAL
+ bool "MediaTek High-speed UART support"
+ depends on DM_SERIAL
+ help
+ Select this to enable UART support for MediaTek High-speed UART
+ devices. This driver uses driver model and requires a device
+ tree binding to operate.
+ The High-speed UART is compatible with the ns16550a UART and have
+ its own high-speed registers.
+
config MPC8XX_CONS
bool "Console driver for MPC8XX"
depends on MPC8xx
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 03dc29e..2f8d065 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
+obj-$(CONFIG_MTK_SERIAL) += serial_mtk.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_mtk.c b/drivers/serial/serial_mtk.c
new file mode 100644
index 000..bce1be8
--- /dev/null
+++ b/drivers/serial/serial_mtk.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek High-speed UART driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Weijie Gao
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct mtk_serial_regs {
+ u32 rbr;
+ u32 ier;
+ u32 fcr;
+ u32 lcr;
+ u32 mcr;
+ u32 lsr;
+ u32 msr;
+ u32 spr;
+ u32 mdr1;
+ u32 highspeed;
+ u32 sample_count;
+ u32 sample_point;
+ u32 fracdiv_l;
+ u32 fracdiv_m;
+ u32 escape_en;
+ u32 guard;
+ u32 rx_sel;
+};
+
+#define thr rbr
+#define iir fcr
+#define dll rbr
+#define dlm ier
+
+#define UART_LCR_WLS_8 0x03/* 8 bit character length */
+#define UART_LCR_DLAB 0x80/* Divisor latch access bit */
+
+#define UART_LSR_DR0x01/* Data ready */
+#define UART_LSR_THRE 0x20/* Xmit holding register empty */
+
+/* the data is correct if the real baud is within 3%. */
+#define BAUD_ALLOW_MAX(baud) ((baud) + (baud) * 3 / 100)
+#define BAUD_ALLOW_MIX(baud) ((baud) - (baud) * 3 / 100)
+
+struct mtk_serial_priv {
+ struct mtk_serial_regs __iomem *regs;
+ u32 clock;
+};
+
+static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud)
+{
+ bool support_clk12m_baud115200;
+ u32 quot, samplecount, realbaud;
+
+ if ((baud <= 115200) && (priv->clock == 1200))
+ support_clk12m_baud115200 = true;
+ else
+ support_clk12m_baud115200 = false;
+
+ if (baud <= 115200) {
+ writel(0, >regs->highspeed);
+ quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud);
+
+ if (support_clk12m_baud115200) {
+ writel(3, >regs->highspeed);
+ quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud);
+ if (quot == 0)
+ quot = 1;
+
+ samplecount = DIV_ROUND_CLOSEST(priv->clock,
+
[U-Boot] [PATCH v5 00/18] Add U-Boot support for MediaTek SoCs - MT7623n & MT7629
Hello, This is the new round to add U-Boot support for MediaTek SoCs - MT7623n & MT7629, and the most of the drivers are based on mainline Linux, such as clock, timer, mmc, pinctrl, UART, watchdog, power domain and device tree. Ryder Ryder Lee (16): tools: MediaTek: add MTK boot header generation to mkimage arm: dts: MediaTek: add device tree for MT7629 arm: dts: MediaTek: add device tree for MT7623 arm: MediaTek: add basic support for MT7629 boards clk: MediaTek: add clock driver for MT7629 SoC. clk: MediaTek: add clock driver for MT7623 SoC. timer: MediaTek: add timer driver for MediaTek SoCs watchdog: MediaTek: add watchdog driver for MediaTek SoCs pinctrl: MediaTek: add pinctrl driver for MT7629 SoC pinctrl: MediaTek: add pinctrl driver for MT7623 SoC power domain: MediaTek: add power domain driver for MT7629 SoC power domain: MediaTek: add power domain driver for MT7623 SoC serial: MediaTek: add high-speed uart driver for MediaTek SoCs ram: MediaTek: add DDR3 driver for MT7629 SoC doc: README.mediatek: Add a simple README for MediaTek MAINTAINERS: add an entry for MediaTek Weijie Gao (2): arm: MediaTek: add basic support for MT7623 boards mmc: mtk-sd: add SD/MMC host controller driver for MT7623 SoC MAINTAINERS | 20 + Makefile | 20 + arch/arm/Kconfig | 16 + arch/arm/Makefile |1 + arch/arm/dts/Makefile |4 + arch/arm/dts/mt7623.dtsi | 255 + arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 arch/arm/dts/mt7629-rfb-u-boot.dtsi | 24 + arch/arm/dts/mt7629-rfb.dts | 70 ++ arch/arm/dts/mt7629.dtsi | 244 + arch/arm/include/asm/arch-mediatek/gpio.h |9 + arch/arm/include/asm/arch-mediatek/misc.h | 17 + arch/arm/mach-mediatek/Kconfig| 39 + arch/arm/mach-mediatek/Makefile |7 + arch/arm/mach-mediatek/cpu.c | 34 + arch/arm/mach-mediatek/init.h | 11 + arch/arm/mach-mediatek/mt7623/Makefile|4 + arch/arm/mach-mediatek/mt7623/init.c | 54 + arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 + arch/arm/mach-mediatek/mt7623/preloader.h | 99 ++ arch/arm/mach-mediatek/mt7629/Makefile|4 + arch/arm/mach-mediatek/mt7629/init.c | 128 +++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 + arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7623/Kconfig | 13 + board/mediatek/mt7623/MAINTAINERS |7 + board/mediatek/mt7623/Makefile|3 + board/mediatek/mt7623/mt7623_rfb.c| 16 + board/mediatek/mt7629/Kconfig | 17 + board/mediatek/mt7629/MAINTAINERS |7 + board/mediatek/mt7629/Makefile|3 + board/mediatek/mt7629/mt7629_rfb.c| 16 + common/image.c|1 + configs/mt7623n_bpir2_defconfig | 54 + configs/mt7629_rfb_defconfig | 73 ++ doc/README.mediatek | 221 drivers/clk/Makefile |1 + drivers/clk/mediatek/Makefile |7 + drivers/clk/mediatek/clk-mt7623.c | 870 +++ drivers/clk/mediatek/clk-mt7629.c | 709 + drivers/clk/mediatek/clk-mtk.c| 493 + drivers/clk/mediatek/clk-mtk.h| 194 drivers/mmc/Kconfig | 11 + drivers/mmc/Makefile |1 + drivers/mmc/mtk-sd.c | 1394 + drivers/pinctrl/Kconfig |1 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/mediatek/Kconfig | 15 + drivers/pinctrl/mediatek/Makefile |7 + drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +++ drivers/pinctrl/mediatek/pinctrl-mt7629.c | 409 drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 553 ++ drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 184 drivers/power/domain/Kconfig |7 + drivers/power/domain/Makefile |1 + drivers/power/domain/mtk-power-domain.c | 406 +++ drivers/ram/Makefile |1 + drivers/ram/mediatek/Makefile |7 + drivers/ram/mediatek/ddr3-mt7629.c| 766 ++ drivers/serial/Kconfig| 20 + drivers/serial/Makefile |1 + drivers/serial/serial_mtk.c | 268 + drivers/timer/Kconfig |7 + drivers/timer/Makefile|
[U-Boot] [PATCH v5 08/18] timer: MediaTek: add timer driver for MediaTek SoCs
This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v5: None
Changes since v4: None
---
drivers/timer/Kconfig | 7
drivers/timer/Makefile| 1 +
drivers/timer/mtk_timer.c | 85 +++
3 files changed, 93 insertions(+)
create mode 100644 drivers/timer/mtk_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index d012cf7..229c3a2 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -160,4 +160,11 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
+config MTK_TIMER
+ bool "MediaTek timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ MediaTek devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 7f19c49..c4fbab2 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
new file mode 100644
index 000..b5e76bd
--- /dev/null
+++ b/drivers/timer/mtk_timer.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek timer driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_GPT4_CTRL 0x40
+#define MTK_GPT4_CLK 0x44
+#define MTK_GPT4_CNT 0x48
+
+#define GPT4_ENABLEBIT(0)
+#define GPT4_CLEAR BIT(1)
+#define GPT4_FREERUN GENMASK(5, 4)
+#define GPT4_CLK_SYS 0x0
+#define GPT4_CLK_DIV1 0x0
+
+struct mtk_timer_priv {
+ void __iomem *base;
+};
+
+static int mtk_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ u32 val = readl(priv->base + MTK_GPT4_CNT);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int mtk_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk, parent;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 1, );
+ if (!ret) {
+ ret = clk_set_parent(, );
+ if (ret)
+ return ret;
+ }
+
+ uc_priv->clock_rate = clk_get_rate();
+ if (!uc_priv->clock_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct timer_ops mtk_timer_ops = {
+ .get_count = mtk_timer_get_count,
+};
+
+static const struct udevice_id mtk_timer_ids[] = {
+ { .compatible = "mediatek,timer" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_timer) = {
+ .name = "mtk_timer",
+ .id = UCLASS_TIMER,
+ .of_match = mtk_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct mtk_timer_priv),
+ .probe = mtk_timer_probe,
+ .ops = _timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
1.9.1
___
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[U-Boot] [PATCH v5 04/18] arm: MediaTek: add basic support for MT7629 boards
This adds a general board file based on MT7629 SoCs from MediaTek. Apart from the generic parts (cpu) we add some low level init codes and initialize the early clocks. Signed-off-by: Ryder Lee Signed-off-by: Weijie Gao Reviewed-by: Simon Glass --- Changes since v5: None Changes since v4: -Add gd->bd->bi_boot_params for legacy method - ATAGs. --- arch/arm/Kconfig | 16 arch/arm/Makefile | 1 + arch/arm/include/asm/arch-mediatek/misc.h | 17 arch/arm/mach-mediatek/Kconfig| 26 ++ arch/arm/mach-mediatek/Makefile | 6 ++ arch/arm/mach-mediatek/cpu.c | 34 +++ arch/arm/mach-mediatek/init.h | 11 +++ arch/arm/mach-mediatek/mt7629/Makefile| 4 + arch/arm/mach-mediatek/mt7629/init.c | 128 ++ arch/arm/mach-mediatek/mt7629/lowlevel_init.S | 50 ++ arch/arm/mach-mediatek/spl.c | 43 + board/mediatek/mt7629/Kconfig | 17 board/mediatek/mt7629/MAINTAINERS | 7 ++ board/mediatek/mt7629/Makefile| 3 + board/mediatek/mt7629/mt7629_rfb.c| 16 configs/mt7629_rfb_defconfig | 73 +++ include/configs/mt7629.h | 57 17 files changed, 509 insertions(+) create mode 100644 arch/arm/include/asm/arch-mediatek/misc.h create mode 100644 arch/arm/mach-mediatek/Kconfig create mode 100644 arch/arm/mach-mediatek/Makefile create mode 100644 arch/arm/mach-mediatek/cpu.c create mode 100644 arch/arm/mach-mediatek/init.h create mode 100644 arch/arm/mach-mediatek/mt7629/Makefile create mode 100644 arch/arm/mach-mediatek/mt7629/init.c create mode 100644 arch/arm/mach-mediatek/mt7629/lowlevel_init.S create mode 100644 arch/arm/mach-mediatek/spl.c create mode 100644 board/mediatek/mt7629/Kconfig create mode 100644 board/mediatek/mt7629/MAINTAINERS create mode 100644 board/mediatek/mt7629/Makefile create mode 100644 board/mediatek/mt7629/mt7629_rfb.c create mode 100644 configs/mt7629_rfb_defconfig create mode 100644 include/configs/mt7629.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1f3fa15..96cd41c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -658,6 +658,20 @@ config ARCH_MESON targeted at media players and tablet computers. We currently support the S905 (GXBaby) 64-bit SoC. +config ARCH_MEDIATEK + bool "MediaTek SoCs" + select BINMAN + select DM + select OF_CONTROL + select SPL_DM if SPL + select SPL_LIBCOMMON_SUPPORT if SPL + select SPL_LIBGENERIC_SUPPORT if SPL + select SPL_OF_CONTROL if SPL + select SUPPORT_SPL + help + Support for the MediaTek SoCs family developed by MediaTek Inc. + Please refer to doc/README.mediatek for more information. + config ARCH_LPC32XX bool "NXP LPC32xx platform" select CPU_ARM926EJS @@ -1442,6 +1456,8 @@ source "arch/arm/mach-rmobile/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-mediatek/Kconfig" + source "arch/arm/mach-qemu/Kconfig" source "arch/arm/mach-rockchip/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4b6c5e1..c38ef3c 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -62,6 +62,7 @@ machine-$(CONFIG_ARCH_K3) += k3 machine-$(CONFIG_ARCH_KEYSTONE)+= keystone # TODO: rename CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD machine-$(CONFIG_KIRKWOOD) += kirkwood +machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek machine-$(CONFIG_ARCH_MESON) += meson machine-$(CONFIG_ARCH_MVEBU) += mvebu # TODO: rename CONFIG_TEGRA -> CONFIG_ARCH_TEGRA diff --git a/arch/arm/include/asm/arch-mediatek/misc.h b/arch/arm/include/asm/arch-mediatek/misc.h new file mode 100644 index 000..2530e78 --- /dev/null +++ b/arch/arm/include/asm/arch-mediatek/misc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef __MEDIATEK_MISC_H_ +#define __MEDIATEK_MISC_H_ + +#define VER_BASE 0x0800 +#define VER_SIZE 0x10 + +#define APHW_CODE 0x00 +#define APHW_SUBCODE 0x04 +#define APHW_VER 0x08 +#define APSW_VER 0x0c + +#endif /* __MEDIATEK_MISC_H_ */ diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig new file mode 100644 index 000..d2ada97 --- /dev/null +++ b/arch/arm/mach-mediatek/Kconfig @@ -0,0 +1,26 @@ +if ARCH_MEDIATEK + +config SYS_SOC + default "mediatek" + +config SYS_VENDOR + default "mediatek" + +choice + prompt "MediaTek board select" + +config TARGET_MT7629 + bool "MediaTek MT7629 So
[U-Boot] [PATCH v5 17/18] doc: README.mediatek: Add a simple README for MediaTek
Add a few notes on how to try out the MediaTek support so far. Signed-off-by: Ryder Lee Tested-by: Frank Wunderlich --- Changes since v5: -Fix Whitespace-Error. Changes since v4: -Add instructions on how to prepare SD card and write to SNOR flash. -Fix typo. --- doc/README.mediatek | 221 1 file changed, 221 insertions(+) create mode 100644 doc/README.mediatek diff --git a/doc/README.mediatek b/doc/README.mediatek new file mode 100644 index 000..246579d --- /dev/null +++ b/doc/README.mediatek @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 MediaTek Inc. +# Ryder Lee + + +This document describes how to compile the U-Boot and how to change U-Boot +configuration about the MediaTek SoCs. + + +Build Procedure +=== + -Set the cross compiler: + + # export CROSS_COMPILE=/path/to/toolchain/arm-linux-gnueabi- + + -Clean-up old residuals: + + # make mrproper + + -Configure the U-Boot: + + # make + # make + + - For the MT7623n bananapi R2 board use "mt7623n_bpir2_defconfig" + - For the MT7629 reference board use "mt7629_rfb_defconfig" + + +Boot sequence += + -Bootrom -> MTK preloader -> U-Boot + + - MT7623n + + This version of U-Boot doesn't implement SPL. So, MTK preloader binary + is needed to boot up: + + https://github.com/BPI-SINOVOIP/BPI-R2-bsp/tree/master/mt-pack/mtk/bpi-r2/bin + + + -Bootrom -> SPL -> U-Boot + + - MT7629 + + +Configuration update + + To update the U-Boot configuration, please refer to doc/README.kconfig + + +MediaTek image header += +Currently there are two image headers used for MediaTek chips: + + - BootROM image header. This header is used by the first stage bootloader. It records + the desired compatible boot device, integrity information and its load address. + + The on-chip BootROM will firstly verify integrity and compatibility of the bootloader. + + If verification passed, the BootROM will then load the bootloader into on-chip SRAM, + and pass control to it. + + Note that this header is actually a combination of three independent headers: + Device header, BRLYT header and GFH header. + + Used by U-Boot SPL of MT7629 and preloader of MT7623. + + + - MediaTek legacy image header. This header was originally used by the legacy image. It + basically records the load address, image size and image name. + + After all low level initializations passed, the preloader will locate the LK image and + load it into DRAM, and pass control to it. + + Now this header is used by U-Boot of MT7623. + + +To generate these two headers with mkimage: + + # mkimage -T mtk_image -a -n -d + + - mtk_image means using MediaTek's header generation method. + + + - load_addr is the load address of this image. + For first stage bootloader like U-Boot SPL or preloader, it usually points to the + on-chip SRAM. + + For second stage bootloader like U-Boot, it usually points to the DRAM. + + + - option_string contains options to generate the header. + + The option string is using the follow format: + key1=value1;key2=value2;... + + The following key names are valid: + lk: If lk=1, LK image header is used. Otherwise BootROM image header is used. + + lkname: The name of the LK image header. The maximum length is 32. + The default value is "U-Boot". + + media: Desired boot device. The valid values are: + nand : Parallel NAND + snand: Serial NAND + nor : Serial NOR + emmc : eMMC + sdmmc: SD + + nandinfo: Desired NAND device type, a combination of page size, oob size and +optional device capacity. Valid types are: + 2k+64: for Serial NAND, 2KiB page size + 64B oob size + 2k+120 : for Serial NAND, 2KiB page size + 120B oob size + 2k+128 : for Serial NAND, 2KiB page size + 128B oob size + 4k+256 : for Serial NAND, 4KiB page size + 256B oob size + 1g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 1Gbit size + 2g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 2Gbit size + 4g:2k+64 : for Parallel NAND, 2KiB page size + 64B oob size, total 4Gbit size + 2g:2k+128: for Parallel NAND, 2KiB page size + 128B oob size, total 2Gbit size + 4g:2k+128: for Parallel NAND, 2KiB page size + 128B oob size, total 4Gbit
[U-Boot] [PATCH v5 07/18] clk: MediaTek: add clock driver for MT7623 SoC.
This patch adds a driver for MT7623 clock blocks.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v5: None
Changes since v4: None
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7623.c | 870 ++
2 files changed, 871 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7623.c
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 297f99d..0632dc8 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7623.c
b/drivers/clk/mediatek/clk-mt7623.c
new file mode 100644
index 000..c6b09d8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7623 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7623_CLKSQ_STB_CON0 0x18
+#define MT7623_PLL_ISO_CON00x24
+#define MT7623_PLL_FMAX(2000UL * MHZ)
+#define MT7623_CON0_RST_BARBIT(27)
+
+#define MCU_AXI_DIV0x60
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7623_CON0_RST_BAR,\
+ .fmax = MT7623_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x8001, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf001, HAVE_RST_BAR,
+ 21, 0x210, 4, 0x214, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf301, HAVE_RST_BAR,
+ 7, 0x220, 4, 0x224, 14),
+ PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x0001, 0,
+ 21, 0x230, 4, 0x234, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x0001, 0,
+ 21, 0x240, 4, 0x244, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x0001, 0,
+ 21, 0x250, 4, 0x254, 0),
+ PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x0001, 0,
+ 31, 0x270, 4, 0x274, 0),
+ PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x0001, 0,
+ 31, 0x280, 4, 0x284, 0),
+ PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x0001, 0,
+ 31, 0x290, 4, 0x294, 0),
+ PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x0001, 0,
+ 31, 0x2a0, 4, 0x2a4, 0),
+ PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x0001, 0,
+ 31, 0x2b0, 4, 0x2b4, 0),
+ PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x0001, 0,
+ 31, 0x2c0, 4, 0x2c4, 0),
+ PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x0001, 0,
+ 21, 0x2d0, 4, 0x2d4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
+ FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
+ FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
+ FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
+ FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
+ FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
+ FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL
[U-Boot] [PATCH v5 15/18] ram: MediaTek: add DDR3 driver for MT7629 SoC
This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou Signed-off-by: Ryder Lee Reviewed-by: Simon Glass --- Changes since v5: None Changes since v4: None --- drivers/ram/Makefile | 1 + drivers/ram/mediatek/Makefile | 7 + drivers/ram/mediatek/ddr3-mt7629.c | 766 + 3 files changed, 774 insertions(+) create mode 100644 drivers/ram/mediatek/Makefile create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index cfba57f..92ea715 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/ram/mediatek/Makefile b/drivers/ram/mediatek/Makefile new file mode 100644 index 000..95507b5 --- /dev/null +++ b/drivers/ram/mediatek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 MediaTek Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_TARGET_MT7629) = ddr3-mt7629.o diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c new file mode 100644 index 000..b413f49 --- /dev/null +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DDR3 driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Wu Zou + *Ryder Lee + */ + +#include +#include +#include +#include +#include + +/* EMI */ +#define EMI_CONA 0x000 +#define EMI_CONF 0x028 +#define EMI_CONM 0x060 + +/* DDR PHY */ +#define DDRPHY_PLL10x +#define DDRPHY_PLL20x0004 +#define DDRPHY_PLL30x0008 +#define DDRPHY_PLL40x000c +#define DDRPHY_PLL50x0010 +#define DDRPHY_PLL70x0018 +#define DDRPHY_B0_DLL_ARPI00x0080 +#define DDRPHY_B0_DLL_ARPI10x0084 +#define DDRPHY_B0_DLL_ARPI20x0088 +#define DDRPHY_B0_DLL_ARPI30x008c +#define DDRPHY_B0_DLL_ARPI40x0090 +#define DDRPHY_B0_DLL_ARPI50x0094 +#define DDRPHY_B0_DQ2 0x00a0 +#define DDRPHY_B0_DQ3 0x00a4 +#define DDRPHY_B0_DQ4 0x00a8 +#define DDRPHY_B0_DQ5 0x00ac +#define DDRPHY_B0_DQ6 0x00b0 +#define DDRPHY_B0_DQ7 0x00b4 +#define DDRPHY_B0_DQ8 0x00b8 +#define DDRPHY_B1_DLL_ARPI00x0100 +#define DDRPHY_B1_DLL_ARPI10x0104 +#define DDRPHY_B1_DLL_ARPI20x0108 +#define DDRPHY_B1_DLL_ARPI30x010c +#define DDRPHY_B1_DLL_ARPI40x0110 +#define DDRPHY_B1_DLL_ARPI50x0114 +#define DDRPHY_B1_DQ2 0x0120 +#define DDRPHY_B1_DQ3 0x0124 +#define DDRPHY_B1_DQ4 0x0128 +#define DDRPHY_B1_DQ5 0x012c +#define DDRPHY_B1_DQ6 0x0130 +#define DDRPHY_B1_DQ7 0x0134 +#define DDRPHY_B1_DQ8 0x0138 +#define DDRPHY_CA_DLL_ARPI00x0180 +#define DDRPHY_CA_DLL_ARPI10x0184 +#define DDRPHY_CA_DLL_ARPI20x0188 +#define DDRPHY_CA_DLL_ARPI30x018c +#define DDRPHY_CA_DLL_ARPI40x0190 +#define DDRPHY_CA_DLL_ARPI50x0194 +#define DDRPHY_CA_CMD2 0x01a0 +#define DDRPHY_CA_CMD3 0x01a4 +#define DDRPHY_CA_CMD5 0x01ac +#define DDRPHY_CA_CMD6 0x01b0 +#define DDRPHY_CA_CMD7 0x01b4 +#define DDRPHY_CA_CMD8 0x01b8 +#define DDRPHY_MISC_VREF_CTRL 0x0264 +#define DDRPHY_MISC_IMP_CTRL0 0x0268 +#define DDRPHY_MISC_IMP_CTRL1 0x026c +#define DDRPHY_MISC_SHU_OPT0x0270 +#define DDRPHY_MISC_SPM_CTRL0 0x0274 +#define DDRPHY_MISC_SPM_CTRL1 0x0278 +#define DDRPHY_MISC_SPM_CTRL2 0x027c +#define DDRPHY_MISC_CG_CTRL0 0x0284 +#define DDRPHY_MISC_CG_CTRL1 0x0288 +#define DDRPHY_MISC_CG_CTRL2 0x028c +#define DDRPHY_MISC_CG_CTRL4 0x0294 +#define DDRPHY_MISC_CTRL0 0x029c +#define DDRPHY_MISC_CTRL1 0x02a0 +#define DDRPHY_MISC_CTRL3 0x02a8 +#define DDRPHY_MISC_RXDVS1 0x05e4 +#define DDRPHY_SHU1_B0_DQ4 0x0c10 +#define DDRPHY_SHU1_B0_DQ5 0x0c14 +#define DDRPHY_SHU1_B0_DQ6 0x0c18 +#define DDRPHY_SHU1_B0_DQ7 0x0c1c +#define DDRPHY_SHU1_B1_DQ4 0x0c90 +#define DDRPHY_SHU1_B1_DQ5 0x0c94 +#define DDRPHY_SHU1_B1_DQ6 0x0c98 +#define DDRPHY_SHU1_B1_DQ7 0x0c9c +#define DDRPHY_SHU1_CA_CMD20x0d08 +#define DDRPHY_SHU1_CA_CMD40x0d10 +#define
[U-Boot] [PATCH v5 09/18] watchdog: MediaTek: add watchdog driver for MediaTek SoCs
This patch adds a common driver for the Mediatek SoC integrated
watchdog.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v5: None
Changes since v4: None
---
drivers/watchdog/Kconfig | 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/mtk_wdt.c | 135 +
3 files changed, 144 insertions(+)
create mode 100644 drivers/watchdog/mtk_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 02f4e1e..b919ef6 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -103,6 +103,14 @@ config WDT_CDNS
Select this to enable Cadence watchdog timer, which can be found on
some
Xilinx Microzed Platform.
+config WDT_MTK
+ bool "MediaTek watchdog timer support"
+ depends on WDT && ARCH_MEDIATEK
+ help
+ Select this to enable watchdog timer for MediaTek SoCs.
+ The watchdog timer is stopped when initialized.
+ It performs full SoC reset.
+
config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 08406ca..04fa4a6 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o
+obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
new file mode 100644
index 000..0b50173
--- /dev/null
+++ b/drivers/watchdog/mtk_wdt.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Watchdog driver for MediaTek SoCs
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#define MTK_WDT_MODE 0x00
+#define MTK_WDT_LENGTH 0x04
+#define MTK_WDT_RESTART0x08
+#define MTK_WDT_STATUS 0x0c
+#define MTK_WDT_INTERVAL 0x10
+#define MTK_WDT_SWRST 0x14
+#define MTK_WDT_REQ_MODE 0x30
+#define MTK_WDT_DEBUG_CTL 0x40
+
+#define WDT_MODE_KEY (0x22 << 24)
+#define WDT_MODE_ENBIT(0)
+#define WDT_MODE_EXTPOLBIT(1)
+#define WDT_MODE_EXTEN BIT(2)
+#define WDT_MODE_IRQ_ENBIT(3)
+#define WDT_MODE_DUAL_EN BIT(6)
+
+#define WDT_LENGTH_KEY 0x8
+#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
+
+#define WDT_RESTART_KEY0x1971
+#define WDT_SWRST_KEY 0x1209
+
+struct mtk_wdt_priv {
+ void __iomem *base;
+};
+
+static int mtk_wdt_reset(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Reload watchdog duration */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ return 0;
+}
+
+static int mtk_wdt_stop(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
+
+ return 0;
+}
+
+static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Kick watchdog to prevent counter == 0 */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ /* Reset */
+ writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
+ hang();
+
+ return 0;
+}
+
+static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /*
+* One bit is the value of 512 ticks
+* The clock has 32 KHz
+*/
+ timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
+ writel(timeout, priv->base + MTK_WDT_LENGTH);
+
+ mtk_wdt_reset(dev);
+}
+
+static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ mtk_wdt_set_timeout(dev, timeout);
+
+ /* Enable watchdog reset signal */
+ setbits_le32(priv->base + MTK_WDT_MODE,
+WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
+
+ return 0;
+}
+
+static int mtk_wdt_probe(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ /* Clear status */
+ clrsetbits_le32(priv->base + MTK_WDT_MODE,
+ WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
+
+ return mtk_wdt_stop(dev);
+}
+
+static const struct wdt_ops mtk_wdt_ops = {
+ .start = mtk_wdt_start,
+ .reset = mtk_wdt_rese
[U-Boot] [PATCH v5 11/18] pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
Reviewed-by: Simon Glass
---
Changes since v5: None
Changes since v4:
-Add a comment to the exported function - mtk_rmw()
---
drivers/pinctrl/mediatek/Kconfig |4 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.h |2 +
4 files changed, 1291 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index e0145b1..1bd9a92 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -4,6 +4,10 @@ config PINCTRL_MTK
depends on PINCTRL_GENERIC
bool
+config PINCTRL_MT7623
+ bool "MT7623 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index cbf0765..f6ef362 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
new file mode 100644
index 000..fd37dfa
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -0,0 +1,1284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_BOND_REG0 0xb10
+#define PIN_BOND_REG1 0xf20
+#define PIN_BOND_REG2 0xef0
+#define BOND_PCIE_CLR (0x77 << 3)
+#define BOND_I2S_CLR 0x3
+#define BOND_MSDC0E_CLR0x1
+
+#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 15, false)
+
+#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, true)
+
+static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
+ PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
+ PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
+ PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
+ PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
+ PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
+ PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
+ PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
+ PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
+ PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
+ PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
+ PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
+ PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
+ PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
+ PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
+ PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
+ PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
+ PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
+ PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
+ PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
+ PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
+ PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
+ PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
+ PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
+ PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
+ PIN
[U-Boot] [PATCH v5 18/18] MAINTAINERS: add an entry for MediaTek
This patch adds an entry for MediaTek. Signed-off-by: Ryder Lee Reviewed-by: Simon Glass --- Changes since v5: None Changes since v4: None --- MAINTAINERS | 20 1 file changed, 20 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index abdb6dc..214629e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -158,6 +158,26 @@ T: git git://git.denx.de/u-boot-pxa.git F: arch/arm/cpu/pxa/ F: arch/arm/include/asm/arch-pxa/ +ARM MEDIATEK +M: Ryder Lee +M: Weijie Gao +S: Maintained +F: arch/arm/mach-mediatek/ +F: arch/arm/include/asm/arch-mediatek/ +F: board/mediatek/ +F: doc/README.mediatek +F: drivers/clk/mediatek/ +F: drivers/mmc/mtk-sd.c +F: drivers/pinctrl/mediatek/ +F: drivers/power/domain/mtk-power-domain.c +F: drivers/ram/mediatek/ +F: drivers/spi/mtk_qspi.c +F: drivers/timer/mtk_timer.c +F: drivers/watchdog/mtk_wdt.c +F: tools/mtk_image.c +F: tools/mtk_image.h +N: mediatek + ARM OWL M: Manivannan Sadhasivam S: Maintained -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 12/18] power domain: MediaTek: add power domain driver for MT7629 SoC
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee
Reviewed-by: Simon Glass
---
Changes since v5: None
Changes since v4: None
---
drivers/power/domain/Kconfig| 7 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/mtk-power-domain.c | 326
3 files changed, 334 insertions(+)
create mode 100644 drivers/power/domain/mtk-power-domain.c
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a08b428..93deaef 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -23,6 +23,13 @@ config IMX8_POWER_DOMAIN
Enable support for manipulating NXP i.MX8 on-SoC power domains via
IPC
requests to the SCU.
+config MTK_POWER_DOMAIN
+ bool "Enable the MediaTek power domain driver"
+ depends on POWER_DOMAIN && ARCH_MEDIATEK
+ help
+ Enable support for manipulating MediaTek power domains via MMIO
+ mapped registers.
+
config MESON_GX_VPU_POWER_DOMAIN
bool "Enable Amlogic Meson GX VPU power domain driver"
depends on ARCH_MESON
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index b08d18f..695aafe 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain.o
+obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
new file mode 100644
index 000..ed4a718
--- /dev/null
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define SPM_EN (0xb16 << 16 | 0x1)
+#define SPM_ETHSYS_PWR_CON 0x2e0
+#define SPM_HIF0_PWR_CON 0x2e4
+#define SPM_HIF1_PWR_CON 0x2e8
+#define SPM_PWR_STATUS 0x60c
+#define SPM_PWR_STATUS_2ND 0x610
+
+#define PWR_RST_B_BIT BIT(0)
+#define PWR_ISO_BITBIT(1)
+#define PWR_ON_BIT BIT(2)
+#define PWR_ON_2ND_BIT BIT(3)
+#define PWR_CLK_DIS_BITBIT(4)
+
+#define PWR_STATUS_ETHSYS BIT(24)
+#define PWR_STATUS_HIF0BIT(25)
+#define PWR_STATUS_HIF1BIT(26)
+
+/* Infrasys configuration */
+#define INFRA_TOPDCM_CTRL 0x10
+#define INFRA_TOPAXI_PROT_EN 0x220
+#define INFRA_TOPAXI_PROT_STA1 0x228
+
+#define DCM_TOP_EN BIT(0)
+
+enum scp_domain_type {
+ SCPSYS_MT7629,
+};
+
+struct scp_domain;
+
+struct scp_domain_data {
+ struct scp_domain *scpd;
+ u32 sta_mask;
+ int ctl_offs;
+ u32 sram_pdn_bits;
+ u32 sram_pdn_ack_bits;
+ u32 bus_prot_mask;
+};
+
+struct scp_domain {
+ void __iomem *base;
+ void __iomem *infracfg;
+ enum scp_domain_type type;
+ struct scp_domain_data *data;
+};
+
+static struct scp_domain_data scp_domain_mt7629[] = {
+ [MT7629_POWER_DOMAIN_ETHSYS] = {
+ .sta_mask = PWR_STATUS_ETHSYS,
+ .ctl_offs = SPM_ETHSYS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = (BIT(3) | BIT(17)),
+ },
+ [MT7629_POWER_DOMAIN_HIF0] = {
+ .sta_mask = PWR_STATUS_HIF0,
+ .ctl_offs = SPM_HIF0_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(25, 24),
+ },
+ [MT7629_POWER_DOMAIN_HIF1] = {
+ .sta_mask = PWR_STATUS_HIF1,
+ .ctl_offs = SPM_HIF1_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(28, 26),
+ },
+};
+
+/**
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hang when some unit accesses the
+ * bus while in power down.
+ */
+static int mtk_infracfg_set_bus
Re: [U-Boot] mt7623 bootup example
On Sun, 2018-11-04 at 11:38 +0100, Frank Wunderlich wrote: > Just to be clear...i tested v2 patches on rc1 > (https://github.com/frank-w/u-boot/tree/bpi-r2_v2) they working well. > > v3 have additional depencies (swig,python-dev same on rc1) and bootargs > seems not to be passed to kernel (rc1=bpi-r2_v3_old and rc3 = bpi-r2_v3) That's because I remove 'gd->bd->bi_boot_params' in v3, but it seems you use legacy method (ATAGs) to pass parameters. I will add it back. > > Gesendet: Samstag, 03. November 2018 um 09:46 Uhr > > Von: "Frank Wunderlich" > > An: s...@chromium.org, "Ryder Lee" > > Cc: u-boot@lists.denx.de > > Betreff: [U-Boot] mt7623 bootup example > > > > Hi Simon, hi Ryder, > > > > i tried Patches so far, they are working well > > > > https://patchwork.ozlabs.org/patch/992398/ > > > > here my github-repo with steps to build: > > > > https://github.com/frank-w/u-boot > > > > there is a build.sh, which compiles uboot the common way with some > > additions like bootmenu and full environment to load a kernel on BPI-R2 > > > > here are instructions how to prepare SD-Card for boot-up: > > > > https://www.fw-web.de/dokuwiki/doku.php?id=en:bpi-r2:storage#extended_boot-headers > > > > as you see you need 3 Headers on SD-Card (SDMMC_BOOT, BRLYT, Preloader) and > > the uboot.bin for SD-Card. on emmc imho preloader in boot0-block and uboot > > on main-Partition is enough for uboot to boot > > > > Source: > > https://www.fw-web.de/dokuwiki/doku.php?id=en:bpi-r2:uboot#update_uboot > > > > btw. @ryder.lee you have a small typo in the readme: > > Boorom => Bootrom (2 times) Thanks for catching that. > > maybe you can add Infos above from my wiki. Btw. how far is the > > ethernet-driver? then i can replace my 2014-uboot ;) > > OK. Thanks Ryder ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 14/18] serial: 16550: allow the driver to support MediaTek serial
On Sat, 2018-11-03 at 00:09 -0600, Simon Glass wrote:
> Hi Ryder,
>
> On 2 November 2018 at 09:15, Ryder Lee wrote:
> > This patch adds an extra operation in ns16550.c to suuport MediaTek
> > SoCs as we have a highspeed register which influences the calcualtion
> > of the divisor.
> >
> > Note that we don't support the baudrate greater than 115200 currently.
> >
> > Signed-off-by: Ryder Lee
> > Tested-by: Matthias Brugger
> > Reviewed-by: Simon Glass
> > ---
> > drivers/serial/ns16550.c | 10 ++
> > 1 file changed, 10 insertions(+)
>
> Actually it seems to me that we should have a compatible string for
> this and deal with this at run-time?
>
> Is that easy to do here?
>
How about this:
uart0: serial@11002000 {
compatible = "ns16550a";
mediatek,highspeed = <0>;
Ryder
___
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[U-Boot] [PATCH v1 14/19] power domain: MediaTek: add power domain driver for MT7629 SoC
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic voltage frequency scaling (DVFS), interrupt
filter and lowlevel sleep control. The System Power Manager (SPM)
inside the SCPSYS is for the MTCMOS power domain control.
For now this driver only adds power domain support.
Signed-off-by: Ryder Lee
---
drivers/power/domain/Kconfig| 7 +
drivers/power/domain/Makefile | 1 +
drivers/power/domain/mtk-power-domain.c | 326
3 files changed, 334 insertions(+)
create mode 100644 drivers/power/domain/mtk-power-domain.c
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 2c34488..e479fed 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -16,6 +16,13 @@ config BCM6328_POWER_DOMAIN
Enable support for manipulating BCM6345 power domains via MMIO
mapped registers.
+config MTK_POWER_DOMAIN
+ bool "Enable the MediaTek power domain driver"
+ depends on POWER_DOMAIN && ARCH_MEDIATEK
+ help
+ Enable support for manipulating MediaTek power domains via MMIO
+ mapped registers.
+
config MESON_GX_VPU_POWER_DOMAIN
bool "Enable Amlogic Meson GX VPU power domain driver"
depends on ARCH_MESON
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 6bdaa17..d6c7aa7 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -4,6 +4,7 @@
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
+obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
diff --git a/drivers/power/domain/mtk-power-domain.c
b/drivers/power/domain/mtk-power-domain.c
new file mode 100644
index 000..5ebeabd
--- /dev/null
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -0,0 +1,326 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define SPM_ETHSYS_PWR_CON 0x2e0
+#define SPM_HIF0_PWR_CON 0x2e4
+#define SPM_HIF1_PWR_CON 0x2e8
+#define SPM_PWR_STATUS 0x60c
+#define SPM_PWR_STATUS_2ND 0x610
+
+#define PWR_RST_B_BIT BIT(0)
+#define PWR_ISO_BITBIT(1)
+#define PWR_ON_BIT BIT(2)
+#define PWR_ON_2ND_BIT BIT(3)
+#define PWR_CLK_DIS_BITBIT(4)
+
+#define PWR_STATUS_ETHSYS BIT(24)
+#define PWR_STATUS_HIF0BIT(25)
+#define PWR_STATUS_HIF1BIT(26)
+
+/* Infrasys configuration */
+#define INFRA_TOPDCM_CTRL 0x10
+#define INFRA_TOPAXI_PROT_EN 0x220
+#define INFRA_TOPAXI_PROT_STA1 0x228
+
+#define DCM_TOP_EN BIT(0)
+
+enum scp_domain_type {
+ SCPSYS_MT7629,
+};
+
+struct scp_domain;
+
+struct scp_domain_data {
+ struct scp_domain *scpd;
+ u32 sta_mask;
+ int ctl_offs;
+ u32 sram_pdn_bits;
+ u32 sram_pdn_ack_bits;
+ u32 bus_prot_mask;
+};
+
+struct scp_domain {
+ void __iomem *base;
+ void __iomem *infracfg;
+ enum scp_domain_type type;
+ struct scp_domain_data *data;
+};
+
+static struct scp_domain_data scp_domain_mt7629[] = {
+ [MT7629_POWER_DOMAIN_ETHSYS] = {
+ .sta_mask = PWR_STATUS_ETHSYS,
+ .ctl_offs = SPM_ETHSYS_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = (BIT(3) | BIT(17)),
+ },
+ [MT7629_POWER_DOMAIN_HIF0] = {
+ .sta_mask = PWR_STATUS_HIF0,
+ .ctl_offs = SPM_HIF0_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(25, 24),
+ },
+ [MT7629_POWER_DOMAIN_HIF1] = {
+ .sta_mask = PWR_STATUS_HIF1,
+ .ctl_offs = SPM_HIF1_PWR_CON,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bus_prot_mask = GENMASK(28, 26),
+ },
+};
+
+/**
+ * This function enables the bus protection bits for disabled power
+ * domains so that the system does not hang when some unit accesses the
+ * bus while in power down.
+ */
+static int mtk_infracfg_set_bus_protection(void __iomem *infracfg,
+ u32 mask)
+{
+ u32 val;
+
+ clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask);
+
+ return
[U-Boot] [PATCH v1 01/19] tools: MediaTek: add MTK boot header generation to mkimage
This patch adds support for MTK boot image generation.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
---
Makefile | 20 ++
common/image.c | 1 +
include/image.h | 1 +
scripts/Makefile.spl | 11 +
tools/Makefile | 1 +
tools/mtkimage.c | 749 +++
tools/mtkimage.h | 199 ++
7 files changed, 982 insertions(+)
create mode 100644 tools/mtkimage.c
create mode 100644 tools/mtkimage.h
diff --git a/Makefile b/Makefile
index 7b5e06a..80f3c74 100644
--- a/Makefile
+++ b/Makefile
@@ -852,6 +852,8 @@ ALL-y += u-boot-tegra.bin u-boot-nodtb-tegra.bin
ALL-$(CONFIG_OF_SEPARATE) += u-boot-dtb-tegra.bin
endif
+ALL-$(CONFIG_ARCH_MEDIATEK) += u-boot-mtk.bin
+
# Add optional build target if defined in board/cpu/soc headers
ifneq ($(CONFIG_BUILD_TARGET),)
ALL-y += $(CONFIG_BUILD_TARGET:"%"=%)
@@ -1354,6 +1356,24 @@ u-boot.elf: u-boot.bin
$(Q)$(OBJCOPY) -I binary $(PLATFORM_ELFFLAGS) $< u-boot-elf.o
$(call if_changed,u-boot-elf)
+# MediaTek's ARM-based u-boot needs a header to contains its load address
+# which is parsed by the BootROM.
+# If the SPL build is enabled, the header will be added to the spl binary,
+# and the spl binary and the u-boot.img will be combined into one file.
+# Otherwise the header will be added to the u-boot.bin directly.
+
+ifeq ($(CONFIG_SPL),y)
+u-boot-mtk.bin: spl/u-boot-spl-mtk.bin u-boot.img FORCE
+ $(call if_changed,cat)
+else
+MKIMAGEFLAGS_u-boot-mtk.bin = -T mtkimage \
+ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+u-boot-mtk.bin: u-boot.bin FORCE
+ $(call if_changed,mkimage)
+endif
+
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot
diff --git a/common/image.c b/common/image.c
index 4f20128..3035cc8 100644
--- a/common/image.c
+++ b/common/image.c
@@ -165,6 +165,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_FIRMWARE_IVT, "firmware_ivt", "Firmware with HABv4 IVT"
},
{ IH_TYPE_PMMC,"pmmc","TI Power Management
Micro-Controller Firmware",},
{ IH_TYPE_STM32IMAGE, "stm32image", "STMicroelectronics STM32
Image" },
+ { IH_TYPE_MTKIMAGE, "mtkimage", "MeidaTek BootROM loadable
Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 3bb7d29..3128981 100644
--- a/include/image.h
+++ b/include/image.h
@@ -277,6 +277,7 @@ enum {
IH_TYPE_PMMC,/* TI Power Management Micro-Controller
Firmware */
IH_TYPE_STM32IMAGE, /* STMicroelectronics STM32 Image */
IH_TYPE_SOCFPGAIMAGE_V1,/* Altera SOCFPGA A10 Preloader */
+ IH_TYPE_MTKIMAGE, /* MeidaTek BootROM loadable Image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index e494d18..b87d0dc 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -212,6 +212,8 @@ ALL-$(CONFIG_SPL_X86_16BIT_INIT) +=
$(obj)/u-boot-x86-16bit-spl.bin
ALL-$(CONFIG_ARCH_ZYNQ)+= $(obj)/boot.bin
ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin
+ALL-$(CONFIG_ARCH_MEDIATEK)+= $(obj)/u-boot-spl-mtk.bin
+
all: $(ALL-y)
quiet_cmd_cat = CAT $@
@@ -342,6 +344,15 @@ cmd_sunxi_spl_image_builder =
$(objtree)/tools/sunxi-spl-image-builder \
$(obj)/sunxi-spl-with-ecc.bin: $(obj)/sunxi-spl.bin
$(call if_changed,sunxi_spl_image_builder)
+
+# MediaTek's specific SPL build
+MKIMAGEFLAGS_u-boot-spl-mtk.bin = -T mtkimage \
+ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) \
+ -n "$(patsubst "%",%,$(CONFIG_MTK_BROM_HEADER_INFO))"
+
+$(obj)/u-boot-spl-mtk.bin: $(obj)/u-boot-spl.bin FORCE
+ $(call if_changed,mkimage)
+
# Rule to link u-boot-spl
# May be overridden by arch/$(ARCH)/config.mk
quiet_cmd_u-boot-spl ?= LD $@
diff --git a/tools/Makefile b/tools/Makefile
index 0c3341e..11732e3 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -115,6 +115,7 @@ dumpimage-mkimage-objs := aisimage.o \
$(LIBFDT_OBJS) \
gpimage.o \
gpimage-common.o \
+ mtkimage.o \
$(RSA_OBJS-y)
dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
diff --git a/tools/mtkimage.c b/tools/mtkimage.c
new file mode 100644
index 000..23ca378
--- /dev/null
+++ b/tools/mtkimage.c
@@ -0,0 +1,749 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Generate MediaTek BootROM header for SPL/U-Boot images
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Weijie Gao
+
[U-Boot] [PATCH v1 05/19] arm: MediaTek: add basic support for MT7623 boards
From: Weijie Gao
This adds a general board file based on MT7623 SoCs from MediaTek.
As this u-boot is loaded by preloader, there is no low level
initializtion codes.
Signed-off-by: Weijie Gao
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
arch/arm/mach-mediatek/Kconfig| 8 +++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7623/Makefile| 4 ++
arch/arm/mach-mediatek/mt7623/init.c | 53 ++
arch/arm/mach-mediatek/mt7623/lowlevel_init.S | 22 ++
arch/arm/mach-mediatek/mt7623/preloader.h | 99 +++
board/mediatek/mt7623/Kconfig | 13
board/mediatek/mt7623/MAINTAINERS | 7 ++
board/mediatek/mt7623/Makefile| 3 +
board/mediatek/mt7623/mt7623_rfb.c| 16 +
include/configs/mt7623.h | 67 ++
11 files changed, 293 insertions(+)
create mode 100644 arch/arm/mach-mediatek/mt7623/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7623/init.c
create mode 100644 arch/arm/mach-mediatek/mt7623/lowlevel_init.S
create mode 100644 arch/arm/mach-mediatek/mt7623/preloader.h
create mode 100644 board/mediatek/mt7623/Kconfig
create mode 100644 board/mediatek/mt7623/MAINTAINERS
create mode 100644 board/mediatek/mt7623/Makefile
create mode 100644 board/mediatek/mt7623/mt7623_rfb.c
create mode 100644 include/configs/mt7623.h
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index a932e70..b39bc44 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -9,6 +9,13 @@ config SYS_VENDOR
choice
prompt "MediaTek board select"
+config TARGET_MT7623
+ bool "MediaTek MT7623 SoC"
+ select CPU_V7A
+ select ARCH_MISC_INIT
+ help
+ Support MediaTek MT7623 SoC.
+
config TARGET_MT7629
bool "MediaTek MT7629 SoC"
select CPU_V7A
@@ -19,6 +26,7 @@ config TARGET_MT7629
endchoice
+source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
endif
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index 852d330..b5d3a37 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,4 +3,5 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD)+= spl.o
+obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
diff --git a/arch/arm/mach-mediatek/mt7623/Makefile
b/arch/arm/mach-mediatek/mt7623/Makefile
new file mode 100644
index 000..007eb4a
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
+obj-y += lowlevel_init.o
diff --git a/arch/arm/mach-mediatek/mt7623/init.c
b/arch/arm/mach-mediatek/mt7623/init.c
new file mode 100644
index 000..bec0570
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/init.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include
+#include
+#include
+#include
+#include "preloader.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct boot_argument *preloader_param;
+
+int mtk_soc_early_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ u32 i;
+
+ if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) &&
+ ((size_t)preloader_param % sizeof(size_t) == 0) &&
+ preloader_param->magic == BOOT_ARGUMENT_MAGIC &&
+ preloader_param->dram_rank_num <=
+ ARRAY_SIZE(preloader_param->dram_rank_size)) {
+ gd->ram_size = 0;
+
+ for (i = 0; i < preloader_param->dram_rank_num; i++)
+ gd->ram_size += preloader_param->dram_rank_size[i];
+ } else {
+ gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+ SZ_2G);
+ }
+
+ return 0;
+}
+
+int print_cpuinfo(void)
+{
+ void __iomem *chipid;
+ u32 swver;
+
+ chipid = ioremap(VER_BASE, VER_SIZE);
+ swver = readl(chipid + APSW_VER);
+
+ printf("CPU: MediaTek MT7623 E%d\n", (swver & 0xf) + 1);
+
+ return 0;
+}
diff --git a/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
new file mode 100644
index 000..afb9476
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7623/lowlevel_init.S
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#include
+
+.externpreloader_param
+
+ENTRY(save_boot_params)
+ ldr r6, =preloader_param
+ str r4, [r6]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
+
+ENTRY(lowlevel_init)
+ /* enable SMP bit */
+ mrc p15, 0, r0, c1, c0, 1
+ orr r0, r0, #0x40
+ mcr p15, 0, r
[U-Boot] [PATCH v1 11/19] watchdog: MediaTek: add watchdog driver for MediaTek SoCs
This patch adds a common driver for the Mediatek SoC integrated
watchdog.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/watchdog/Kconfig | 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/mtk_wdt.c | 135 +
3 files changed, 144 insertions(+)
create mode 100644 drivers/watchdog/mtk_wdt.c
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index d545b3e..57a12f5 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -103,6 +103,14 @@ config WDT_CDNS
Select this to enable Cadence watchdog timer, which can be found on
some
Xilinx Microzed Platform.
+config WDT_MTK
+ bool "MediaTek watchdog timer support"
+ depends on WDT && ARCH_MEDIATEK
+ help
+ Select this to enable watchdog timer for MediaTek SoCs.
+ The watchdog timer is stopped when initialized.
+ It performs full SoC reset.
+
config XILINX_TB_WATCHDOG
bool "Xilinx Axi watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 08406ca..04fa4a6 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
obj-$(CONFIG_MPC8xx_WATCHDOG) += mpc8xx_wdt.o
+obj-$(CONFIG_WDT_MTK) += mtk_wdt.o
diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c
new file mode 100644
index 000..0b50173
--- /dev/null
+++ b/drivers/watchdog/mtk_wdt.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Watchdog driver for MediaTek SoCs
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+
+#define MTK_WDT_MODE 0x00
+#define MTK_WDT_LENGTH 0x04
+#define MTK_WDT_RESTART0x08
+#define MTK_WDT_STATUS 0x0c
+#define MTK_WDT_INTERVAL 0x10
+#define MTK_WDT_SWRST 0x14
+#define MTK_WDT_REQ_MODE 0x30
+#define MTK_WDT_DEBUG_CTL 0x40
+
+#define WDT_MODE_KEY (0x22 << 24)
+#define WDT_MODE_ENBIT(0)
+#define WDT_MODE_EXTPOLBIT(1)
+#define WDT_MODE_EXTEN BIT(2)
+#define WDT_MODE_IRQ_ENBIT(3)
+#define WDT_MODE_DUAL_EN BIT(6)
+
+#define WDT_LENGTH_KEY 0x8
+#define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
+
+#define WDT_RESTART_KEY0x1971
+#define WDT_SWRST_KEY 0x1209
+
+struct mtk_wdt_priv {
+ void __iomem *base;
+};
+
+static int mtk_wdt_reset(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Reload watchdog duration */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ return 0;
+}
+
+static int mtk_wdt_stop(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
+
+ return 0;
+}
+
+static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /* Kick watchdog to prevent counter == 0 */
+ writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
+
+ /* Reset */
+ writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
+ hang();
+
+ return 0;
+}
+
+static void mtk_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ /*
+* One bit is the value of 512 ticks
+* The clock has 32 KHz
+*/
+ timeout = WDT_LENGTH_TIMEOUT(timeout << 6) | WDT_LENGTH_KEY;
+ writel(timeout, priv->base + MTK_WDT_LENGTH);
+
+ mtk_wdt_reset(dev);
+}
+
+static int mtk_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ mtk_wdt_set_timeout(dev, timeout);
+
+ /* Enable watchdog reset signal */
+ setbits_le32(priv->base + MTK_WDT_MODE,
+WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
+
+ return 0;
+}
+
+static int mtk_wdt_probe(struct udevice *dev)
+{
+ struct mtk_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ /* Clear status */
+ clrsetbits_le32(priv->base + MTK_WDT_MODE,
+ WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
+
+ return mtk_wdt_stop(dev);
+}
+
+static const struct wdt_ops mtk_wdt_ops = {
+ .start = mtk_wdt_start,
+ .reset = mtk_wdt_reset,
+ .stop = mtk_wdt_stop,
+ .expire_now = mtk_wdt_expire_now,
+};
[U-Boot] [PATCH v1 12/19] pinctrl: MediaTek: add pinctrl driver for MT7629 SoC
This patch adds pinctrl support for MT7629 SoC. The IO core found on
the SoC has the registers for pinctrl, pinconf and gpio mixed up in
the same register range. Hence the driver also implements the gpio
functionality through UCLASS_GPIO.
This also creates a common file as there might be other chips that use
the same binding and driver, then being a little more abstract could
help in the long run.
Signed-off-by: Ryder Lee
---
arch/arm/include/asm/arch-mediatek/gpio.h | 9 +
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mediatek/Kconfig | 11 +
drivers/pinctrl/mediatek/Makefile | 6 +
drivers/pinctrl/mediatek/pinctrl-mt7629.c | 488 +++
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 552 ++
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 182 +
8 files changed, 1250 insertions(+)
create mode 100644 arch/arm/include/asm/arch-mediatek/gpio.h
create mode 100644 drivers/pinctrl/mediatek/Kconfig
create mode 100644 drivers/pinctrl/mediatek/Makefile
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7629.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-common.h
diff --git a/arch/arm/include/asm/arch-mediatek/gpio.h
b/arch/arm/include/asm/arch-mediatek/gpio.h
new file mode 100644
index 000..4ea1020
--- /dev/null
+++ b/arch/arm/include/asm/arch-mediatek/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ */
+
+#ifndef __MEDIATEK_GPIO_H
+#define __MEDIATEK_GPIO_H
+
+#endif /* __MEDIATEK_GPIO_H */
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8da..7e6fad3 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -301,6 +301,7 @@ config ASPEED_AST2500_PINCTRL
endif
source "drivers/pinctrl/meson/Kconfig"
+source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d..293bad3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-$(CONFIG_PINCTRL_MTK) += mediatek/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 000..e0145b1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MEDIATEK
+
+config PINCTRL_MTK
+ depends on PINCTRL_GENERIC
+ bool
+
+config PINCTRL_MT7629
+ bool "MT7629 SoC pinctrl driver"
+ select PINCTRL_MTK
+
+endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 000..cbf0765
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
+
+# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
new file mode 100644
index 000..1787937
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -0,0 +1,488 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+
+#define MT7629_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
+
+static const struct mtk_pin_field_calc mt7629_pin_mode_range[] = {
+ PIN_FIELD(0, 78, 0x300, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_dir_range[] = {
+ PIN_FIELD(0, 78, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_di_range[] = {
+ PIN_FIELD(0, 78, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_do_range[] = {
+ PIN_FIELD(0, 78, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7629_pin_ies_range[] = {
+ PIN_FIELD(0, 10, 0x1000, 0x10, 0, 1),
+ PIN_FIELD(11, 18, 0x2000, 0x10, 0, 1),
+ PIN_FIELD(19, 32, 0x3000, 0x10, 0, 1),
+ PIN_FIELD(33, 48, 0x4000, 0x10, 0, 1),
+ PIN_FIELD(49, 50, 0x5000, 0x10, 0, 1),
+ PIN_FIELD(51, 69, 0x6000, 0x10, 0, 1),
+
[U-Boot] [PATCH v1 13/19] pinctrl: MediaTek: add pinctrl driver for MT7623 SoC
This patch adds pinctrl support for MT7623 SoC. And most of the
structures are used to hold the hardware configuration for each
pin.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/pinctrl/mediatek/Kconfig |4 +
drivers/pinctrl/mediatek/Makefile |1 +
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 1284 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.h |1 +
4 files changed, 1290 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index e0145b1..1bd9a92 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -4,6 +4,10 @@ config PINCTRL_MTK
depends on PINCTRL_GENERIC
bool
+config PINCTRL_MT7623
+ bool "MT7623 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index cbf0765..f6ef362 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,4 +3,5 @@
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
new file mode 100644
index 000..6fa3e2b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -0,0 +1,1284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_BOND_REG0 0xb10
+#define PIN_BOND_REG1 0xf20
+#define PIN_BOND_REG2 0xef0
+#define BOND_PCIE_CLR (0x77 << 3)
+#define BOND_I2S_CLR 0x3
+#define BOND_MSDC0E_CLR0x1
+
+#define PIN_FIELD15(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 15, false)
+
+#define PIN_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+#define PINS_FIELD16(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, true)
+
+static const struct mtk_pin_field_calc mt7623_pin_mode_range[] = {
+ PIN_FIELD15(0, 278, 0x760, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_dir_range[] = {
+ PIN_FIELD16(0, 175, 0x0, 0x10, 0, 1),
+ PIN_FIELD16(176, 278, 0xc0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_di_range[] = {
+ PIN_FIELD16(0, 278, 0x630, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_do_range[] = {
+ PIN_FIELD16(0, 278, 0x500, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7623_pin_ies_range[] = {
+ PINS_FIELD16(0, 6, 0xb20, 0x10, 0, 1),
+ PINS_FIELD16(7, 9, 0xb20, 0x10, 1, 1),
+ PINS_FIELD16(10, 13, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(14, 15, 0xb30, 0x10, 13, 1),
+ PINS_FIELD16(16, 17, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(18, 29, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(30, 32, 0xb40, 0x10, 7, 1),
+ PINS_FIELD16(33, 37, 0xb40, 0x10, 13, 1),
+ PIN_FIELD16(38, 38, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(39, 42, 0xb40, 0x10, 13, 1),
+ PINS_FIELD16(43, 45, 0xb20, 0x10, 10, 1),
+ PINS_FIELD16(47, 48, 0xb20, 0x10, 11, 1),
+ PIN_FIELD16(49, 49, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(50, 52, 0xb20, 0x10, 13, 1),
+ PINS_FIELD16(53, 56, 0xb20, 0x10, 14, 1),
+ PINS_FIELD16(57, 58, 0xb20, 0x10, 15, 1),
+ PIN_FIELD16(59, 59, 0xb30, 0x10, 10, 1),
+ PINS_FIELD16(60, 62, 0xb30, 0x10, 0, 1),
+ PINS_FIELD16(63, 65, 0xb30, 0x10, 1, 1),
+ PINS_FIELD16(66, 71, 0xb30, 0x10, 2, 1),
+ PINS_FIELD16(72, 74, 0xb20, 0x10, 12, 1),
+ PINS_FIELD16(75, 76, 0xb30, 0x10, 3, 1),
+ PINS_FIELD16(77, 78, 0xb30, 0x10, 4, 1),
+ PINS_FIELD16(79, 82, 0xb30, 0x10, 5, 1),
+ PINS_FIELD16(83, 84, 0xb30, 0x10, 2, 1),
+ PIN_FIELD16(85, 85, 0xda0, 0x10, 4, 1),
+ PIN_FIELD16(86, 86, 0xd90, 0x10, 4, 1),
+ PINS_FIELD16(87, 90, 0xdb0, 0x10, 4, 1),
+ PINS_FIELD16(101, 104, 0xb30, 0x10, 6, 1),
+ PIN_FIELD16(105, 105, 0xd40, 0x10, 4, 1),
+ PIN_FIELD16(106, 106, 0xd30, 0x10, 4, 1),
+ PINS_FIELD16(107, 110, 0xd50, 0x10, 4, 1),
+ PINS_FIELD16(111, 115, 0xce0, 0x10, 4, 1),
+ PIN_FIELD16(116, 116, 0xcd0, 0x10, 4, 1),
+ PIN_FIELD16(117, 117, 0xcc0, 0x10, 4, 1),
+ PINS_FIELD16(118, 121, 0xce0, 0
[U-Boot] [PATCH v1 08/19] clk: MediaTek: add clock driver for MT7629 SoC.
This patch adds clock modules for MediaTek SoCs:
- Shared part: a common driver which contains the general operations
for plls, muxes, dividers and gates so that we can reuse it in future.
- Specific SoC part: the group of structures used to hold the hardware
configuration for each SoC.
We take MT7629 as an example to demonstrate how to implement driver if
any other MediaTek chips would like to use it.
Signed-off-by: Ryder Lee
---
drivers/clk/Makefile | 1 +
drivers/clk/mediatek/Makefile | 6 +
drivers/clk/mediatek/clk-mt7629.c | 706 ++
drivers/clk/mediatek/clk-mtk.c| 494 ++
drivers/clk/mediatek/clk-mtk.h| 151
5 files changed, 1358 insertions(+)
create mode 100644 drivers/clk/mediatek/Makefile
create mode 100644 drivers/clk/mediatek/clk-mt7629.c
create mode 100644 drivers/clk/mediatek/clk-mtk.c
create mode 100644 drivers/clk/mediatek/clk-mtk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8bc9f52..3641991 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
obj-y += tegra/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
obj-$(CONFIG_ARCH_MESON) += clk_meson.o
+obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_ARCH_SOCFPGA) += altera/
obj-$(CONFIG_CLK_AT91) += at91/
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
new file mode 100644
index 000..297f99d
--- /dev/null
+++ b/drivers/clk/mediatek/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0
+# Core
+obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
+
+# SoC Drivers
+obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
diff --git a/drivers/clk/mediatek/clk-mt7629.c
b/drivers/clk/mediatek/clk-mt7629.c
new file mode 100644
index 000..d4d963e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -0,0 +1,706 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7629 SoC
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT7629_CLKSQ_STB_CON0 0x20
+#define MT7629_PLL_ISO_CON00x2c
+#define MT7629_PLL_FMAX(2500UL * MHZ)
+#define MT7629_CON0_RST_BARBIT(24)
+
+#define MCU_AXI_DIV0x640
+#define AXI_DIV_MSKGENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX0x7c0
+#define MCU_BUS_MSKGENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT7629_CON0_RST_BAR,\
+ .fmax = MT7629_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 3125),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 3125),
+ FIXED_CLK(CLK_T
[U-Boot] [PATCH v1 10/19] timer: MediaTek: add timer driver for MediaTek SoCs
This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.
Signed-off-by: Ryder Lee
Tested-by: Matthias Brugger
---
drivers/timer/Kconfig | 7
drivers/timer/Makefile| 1 +
drivers/timer/mtk_timer.c | 85 +++
3 files changed, 93 insertions(+)
create mode 100644 drivers/timer/mtk_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index a7d600b..6013945 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -147,4 +147,11 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
+config MTK_TIMER
+ bool "MediaTek timer support"
+ depends on TIMER
+ help
+ Select this to enable support for the timer found on
+ MediaTek devices.
+
endmenu
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 7f19c49..c4fbab2 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_STI_TIMER)+= sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
+obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
diff --git a/drivers/timer/mtk_timer.c b/drivers/timer/mtk_timer.c
new file mode 100644
index 000..b5e76bd
--- /dev/null
+++ b/drivers/timer/mtk_timer.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek timer driver
+ *
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define MTK_GPT4_CTRL 0x40
+#define MTK_GPT4_CLK 0x44
+#define MTK_GPT4_CNT 0x48
+
+#define GPT4_ENABLEBIT(0)
+#define GPT4_CLEAR BIT(1)
+#define GPT4_FREERUN GENMASK(5, 4)
+#define GPT4_CLK_SYS 0x0
+#define GPT4_CLK_DIV1 0x0
+
+struct mtk_timer_priv {
+ void __iomem *base;
+};
+
+static int mtk_timer_get_count(struct udevice *dev, u64 *count)
+{
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ u32 val = readl(priv->base + MTK_GPT4_CNT);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int mtk_timer_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct mtk_timer_priv *priv = dev_get_priv(dev);
+ struct clk clk, parent;
+ int ret;
+
+ priv->base = dev_read_addr_ptr(dev);
+ if (!priv->base)
+ return -ENOENT;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret)
+ return ret;
+
+ ret = clk_get_by_index(dev, 1, );
+ if (!ret) {
+ ret = clk_set_parent(, );
+ if (ret)
+ return ret;
+ }
+
+ uc_priv->clock_rate = clk_get_rate();
+ if (!uc_priv->clock_rate)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct timer_ops mtk_timer_ops = {
+ .get_count = mtk_timer_get_count,
+};
+
+static const struct udevice_id mtk_timer_ids[] = {
+ { .compatible = "mediatek,timer" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_timer) = {
+ .name = "mtk_timer",
+ .id = UCLASS_TIMER,
+ .of_match = mtk_timer_ids,
+ .priv_auto_alloc_size = sizeof(struct mtk_timer_priv),
+ .probe = mtk_timer_probe,
+ .ops = _timer_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
1.9.1
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[U-Boot] [PATCH v1 17/19] ram: MediaTek: add DDR3 driver for MT7629 SoC
This patch adds a DDR3 driver for MT7629 SoC. Signed-off-by: Wu Zou Signed-off-by: Ryder Lee --- drivers/ram/Makefile | 1 + drivers/ram/mediatek/Makefile | 7 + drivers/ram/mediatek/ddr3-mt7629.c | 766 + 3 files changed, 774 insertions(+) create mode 100644 drivers/ram/mediatek/Makefile create mode 100644 drivers/ram/mediatek/ddr3-mt7629.c diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 4ad3604..65cba80 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -12,3 +12,4 @@ obj-$(CONFIG_STM32_SDRAM) += stm32_sdram.o obj-$(CONFIG_ARCH_BMIPS) += bmips_ram.o obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ +obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ diff --git a/drivers/ram/mediatek/Makefile b/drivers/ram/mediatek/Makefile new file mode 100644 index 000..95507b5 --- /dev/null +++ b/drivers/ram/mediatek/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2018 MediaTek Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-$(CONFIG_TARGET_MT7629) = ddr3-mt7629.o diff --git a/drivers/ram/mediatek/ddr3-mt7629.c b/drivers/ram/mediatek/ddr3-mt7629.c new file mode 100644 index 000..b413f49 --- /dev/null +++ b/drivers/ram/mediatek/ddr3-mt7629.c @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek DDR3 driver for MT7629 SoC + * + * Copyright (C) 2018 MediaTek Inc. + * Author: Wu Zou + *Ryder Lee + */ + +#include +#include +#include +#include +#include + +/* EMI */ +#define EMI_CONA 0x000 +#define EMI_CONF 0x028 +#define EMI_CONM 0x060 + +/* DDR PHY */ +#define DDRPHY_PLL10x +#define DDRPHY_PLL20x0004 +#define DDRPHY_PLL30x0008 +#define DDRPHY_PLL40x000c +#define DDRPHY_PLL50x0010 +#define DDRPHY_PLL70x0018 +#define DDRPHY_B0_DLL_ARPI00x0080 +#define DDRPHY_B0_DLL_ARPI10x0084 +#define DDRPHY_B0_DLL_ARPI20x0088 +#define DDRPHY_B0_DLL_ARPI30x008c +#define DDRPHY_B0_DLL_ARPI40x0090 +#define DDRPHY_B0_DLL_ARPI50x0094 +#define DDRPHY_B0_DQ2 0x00a0 +#define DDRPHY_B0_DQ3 0x00a4 +#define DDRPHY_B0_DQ4 0x00a8 +#define DDRPHY_B0_DQ5 0x00ac +#define DDRPHY_B0_DQ6 0x00b0 +#define DDRPHY_B0_DQ7 0x00b4 +#define DDRPHY_B0_DQ8 0x00b8 +#define DDRPHY_B1_DLL_ARPI00x0100 +#define DDRPHY_B1_DLL_ARPI10x0104 +#define DDRPHY_B1_DLL_ARPI20x0108 +#define DDRPHY_B1_DLL_ARPI30x010c +#define DDRPHY_B1_DLL_ARPI40x0110 +#define DDRPHY_B1_DLL_ARPI50x0114 +#define DDRPHY_B1_DQ2 0x0120 +#define DDRPHY_B1_DQ3 0x0124 +#define DDRPHY_B1_DQ4 0x0128 +#define DDRPHY_B1_DQ5 0x012c +#define DDRPHY_B1_DQ6 0x0130 +#define DDRPHY_B1_DQ7 0x0134 +#define DDRPHY_B1_DQ8 0x0138 +#define DDRPHY_CA_DLL_ARPI00x0180 +#define DDRPHY_CA_DLL_ARPI10x0184 +#define DDRPHY_CA_DLL_ARPI20x0188 +#define DDRPHY_CA_DLL_ARPI30x018c +#define DDRPHY_CA_DLL_ARPI40x0190 +#define DDRPHY_CA_DLL_ARPI50x0194 +#define DDRPHY_CA_CMD2 0x01a0 +#define DDRPHY_CA_CMD3 0x01a4 +#define DDRPHY_CA_CMD5 0x01ac +#define DDRPHY_CA_CMD6 0x01b0 +#define DDRPHY_CA_CMD7 0x01b4 +#define DDRPHY_CA_CMD8 0x01b8 +#define DDRPHY_MISC_VREF_CTRL 0x0264 +#define DDRPHY_MISC_IMP_CTRL0 0x0268 +#define DDRPHY_MISC_IMP_CTRL1 0x026c +#define DDRPHY_MISC_SHU_OPT0x0270 +#define DDRPHY_MISC_SPM_CTRL0 0x0274 +#define DDRPHY_MISC_SPM_CTRL1 0x0278 +#define DDRPHY_MISC_SPM_CTRL2 0x027c +#define DDRPHY_MISC_CG_CTRL0 0x0284 +#define DDRPHY_MISC_CG_CTRL1 0x0288 +#define DDRPHY_MISC_CG_CTRL2 0x028c +#define DDRPHY_MISC_CG_CTRL4 0x0294 +#define DDRPHY_MISC_CTRL0 0x029c +#define DDRPHY_MISC_CTRL1 0x02a0 +#define DDRPHY_MISC_CTRL3 0x02a8 +#define DDRPHY_MISC_RXDVS1 0x05e4 +#define DDRPHY_SHU1_B0_DQ4 0x0c10 +#define DDRPHY_SHU1_B0_DQ5 0x0c14 +#define DDRPHY_SHU1_B0_DQ6 0x0c18 +#define DDRPHY_SHU1_B0_DQ7 0x0c1c +#define DDRPHY_SHU1_B1_DQ4 0x0c90 +#define DDRPHY_SHU1_B1_DQ5 0x0c94 +#define DDRPHY_SHU1_B1_DQ6 0x0c98 +#define DDRPHY_SHU1_B1_DQ7 0x0c9c +#define DDRPHY_SHU1_CA_CMD20x0d08 +#define DDRPHY_SHU1_CA_CMD40x0d10 +#define DDRPHY_SHU1_CA_CMD50x0d14 +#define DDRPHY_SHU1_CA_CMD60x0d18
