Hi Heiko and Simon,
Thought I'd follow-up to keep this discussion going. The main thing I
would like to decide first (as it lets me start relying on it in boot
scripts) would be the UBI access syntax:
=> ls ubi 0:rootfs /boot
=> ls ubi 0:2 /boot
Do those look good? Should I be trying to
and its associated header file existed only to support
PSCI code, so also delete them altogether.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 57
arch/arm/include/asm/arch-sunxi/cpucfg.h | 67
2 files changed, 23 insertions
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.
Signed-off-by: Sam Edwards
Tested-by: Maksim Kiselev
Tested-by: Kevin Amadiva
---
arch/arm/cpu/armv7/sunxi/psci.c | 47 -
arch/arm/mach
SUNXI_CPUX_BASE to SUNXI_CPUCFG_BASE, to mirror expected changes in
Andre's v2 of the R528 series (we decided against using a new name for this
block).
- Removed sunxi_cpucfg_reg struct, and stopped using the PRCM struct in psci.c.
Happy Saturday all,
Sam
Sam Edwards (4):
sunxi: psci: clean aw
es instead.
There are no functional changes here.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
---
arch/arm/cpu/armv7/sunxi/psci.c | 103 +---
1 file changed, 43 insertions(+), 60 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/ps
same logic.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
---
arch/arm/cpu/armv7/sunxi/psci.c | 66 +++--
1 file changed, 47 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 69fa3f3c2
On 9/27/23 10:32, Andre Przywara wrote:
On Wed, 16 Aug 2023 10:34:20 -0700
Sam Edwards wrote:
Hi Sam,
Hi Andre,
Mmh, I didn't find a better solution than keeping this in.
I'll keep it if your R528 v2 doesn't find some other way to address it.
+#endif
+#if defined(SUNXI_CPUX_BASE
On 9/27/23 10:34, Andre Przywara wrote:
In the majority of cases, there are no changes to the text section
introduced by this patch. In the R40 case, there's a small change where
the compiler adds a NULL check onto the result of the `(void *)cpucfg +
SUN8I_R40_PWR_CLAMP(cpu)` computation, which
On 9/27/23 10:31, Andre Przywara wrote:
On Wed, 16 Aug 2023 10:34:19 -0700
Sam Edwards wrote:
Hi Sam,
Hi Andre,
@@ -103,10 +116,13 @@ static void __secure clamp_set(u32 *clamp)
static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)
{
- /* secondary
same logic.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
---
arch/arm/cpu/armv7/sunxi/psci.c | 66 +++--
1 file changed, 47 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 69fa3f3c2
l into sunxi_cpu_set_power().
- Removed unnecessary H6 special-case, since H6 is actually ARM64.
- Renamed SUNXI_CPUX_BASE to SUNXI_CPUCFG_BASE, to mirror expected changes in
Andre's v2 of the R528 series (we decided against using a new name for this
block).
- Removed sunxi_cpucfg_reg struct, and stoppe
and its associated header file existed only to support
PSCI code, so also delete them altogether.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 57
arch/arm/include/asm/arch-sunxi/cpucfg.h | 67
2 files changed, 23 insertions
es instead.
There are no functional changes here.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
---
arch/arm/cpu/armv7/sunxi/psci.c | 103 +---
1 file changed, 43 insertions(+), 60 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/ps
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.
Signed-off-by: Sam Edwards
Tested-by: Maksim Kiselev
Tested-by: Kevin Amadiva
---
arch/arm/cpu/armv7/Kconfig | 3 ++-
arch/arm/cpu/armv7/sunxi/psci.c | 47
Reviewed-by: Sam Edwards
Cheers,
Sam
lain
"Bad device specification" and does not suggest using ubifsmount.
Signed-off-by: Sam Edwards
---
disk/part.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/disk/part.c b/disk/part.c
index 72241b7b23..a4b6d265da 100644
--- a/disk/
the parent for the BLK devices that represent the static volumes.
Signed-off-by: Sam Edwards
---
cmd/ubi.c| 11 ++
drivers/mtd/ubi/Makefile | 1 +
drivers/mtd/ubi/ubi-uclass.c | 74
include/dm/uclass-id.h | 1 +
include/ubi_uboot.h
---
disk/part.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/disk/part.c b/disk/part.c
index a4b6d265da..7c995f583c 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -14,6 +14,9 @@
#include
#include
#include
+#include
+#include
ndex/volume numbers with `dectoul` instead of `hextoul`, to match
Linux's behavior of treating these numbers as decimal.
- Do not treat a valid decimal number as a volume name, even if the volume ID
doesn't exist, to match Linux's behavior of always treating decimal numbers
as volume IDs.
Cheer
This makes static UBI volumes readable as block devices, however
no mechanism for selecting these volume devices yet exists.
Signed-off-by: Sam Edwards
---
drivers/mtd/ubi/ubi-uclass.c | 111 +++
1 file changed, 111 insertions(+)
diff --git a/drivers/mtd/ubi/ubi
ot 3 of a Turing Pi 2
cluster board.
[1]: https://lore.kernel.org/all/20230428223500.23337-1-jim2101...@gmail.com/
Signed-off-by: Sam Edwards
---
drivers/pci/pcie_brcmstb.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pc
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.
Signed-off-by: Sam Edwards
Tested-by: Maksim Kiselev
---
arch/arm/cpu/armv7/sunxi/psci.c | 48 -
arch/arm/mach-sunxi/Kconfig | 2
and its associated header file existed only to support
PSCI code, so also delete them altogether.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 57
arch/arm/include/asm/arch-sunxi/cpucfg.h | 67
2 files changed, 23 insertions
es instead.
There are no functional changes here.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 102 +---
1 file changed, 42 insertions(+), 60 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index e1d3638b5c..7804e09
same logic.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 66 +++--
1 file changed, 47 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 7804e0933b..e2845f21ab 100644
--- a/arch
This is a hack for reviewer QoL. It is not being submitted for mainline
inclusion.
---
arch/arm/cpu/armv7/sunxi/psci.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index b4ce4f6def..27bac291d5 100644
---
uct in psci.c.
Cheers,
Sam
Sam Edwards (5):
sunxi: psci: clean away preprocessor macros
sunxi: psci: refactor register access to separate functions
sunxi: psci: stop modeling register layout with C structs
sunxi: psci: implement PSCI on R528
HACK: sunxi: psci: be compatible with v1 of
On 8/18/23 07:57, Andre Przywara wrote:
On Wed, 16 Aug 2023 10:34:17 -0700
Sam Edwards wrote:
Hi Sam,
Likewise Andre,
-static void __secure sunxi_set_entry_address(void *entry)
+static void __secure sunxi_cpu_set_entry(int __always_unused cpu, void *entry)
So what is the reasoning behind
what's changing. If it's easy enough, I'd like to adjust
my patch so that the optimizer does produce the same output. (Keep in
mind I'm on Clang, though. If Clang already gives the same output for
both, I'll just report back to use that when comparing.)
Signed-off-by: Sam Edwards
Reviewed
On 8/18/23 07:27, Andre Przywara wrote:
Hi Andre,
So instead of trying to derive some pattern from where there is none, I'd
rather do: config SUNXI_CPU_HOTPLUG_ADDRESS
hex
default 0x01c000bc if MACH_SUN8I_R40
But the hotplug flag register is at 0x01c000b8 for R40?
On 8/18/23 10:40, Sam Edwards wrote:
On 8/18/23 07:11, Andre Przywara wrote:
Hi Andre,
The resulting object file is different (8 byte larger,
even), so it's hard to prove
I'm no stranger to reading object code. Since the output should be
identical in principle, I'll spend a little bit
On 8/25/23 00:20, Chen-Yu Tsai wrote:
Hi Chen-Yu,
IIRC the GIC manual says that the secure bit is set or cleared to select
which bank of registers is accessed.
Which secure bit are we talking about here? Do we mean the *configured*
secure bit (SCR.NS, what the code is attempting to clear)
On 8/14/23 08:16, Andre Przywara wrote:
Hi Sam,
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.
Unfortunately this patch breaks the build on older 32-bit SoCs, as
SUNXI_CPUX_BASE is not defined there. That's a typical
On 8/15/23 15:59, Andre Przywara wrote:
Hi Sam,
Hi Andre,
So that's a bit more nasty indeed. I don't even know if R_CPUCFG really
makes sense here, as the _R_ term typically refers to the management
processor, which the D1/R528 don't have. Or at least the always-on power
domain, but then
On 8/26/23 04:22, Marc Zyngier wrote:
Hi Marc!
The GIC definitely has the NS bit routed to it. Otherwise, the secure
configuration would just be an utter joke. Just try it.
Thank you for your response. I'd like to revisit my prior point about
the distinction between the NS bit and AxPROT[1]
this initialization being about configuring a FIFO has
pretty much been debunked for years now.
This cleanup also adds a TODO comment about runtime discovery
of the SYSCON base, per discussion with Andre.
Signed-off-by: Sam Edwards
Cc: Andre Przywara
---
drivers/usb/musb-new/sunxi.c | 31
Hello again,
The only change from v2 is that `syscon_base` is now a param of
`sunxi_musb_claim_sram`, and the TODO comment has been removed.
Cheers,
Sam
Sam Edwards (2):
usb: musb-new: sunxi: only perform SRAM initialization when necessary
usb: musb-new: sunxi: clarify the purpose of SRAM
Only the older (ca. A10, A20) sunxis need this poke for the MUSB to
function. Mimic the Linux kernel and add a `has_sram` flag to the config
structure that is only set for the specific compatibles that require
this initialization.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
Tested
Hey there Heiko,
On 6/12/23 06:35, Heiko Schocher wrote:
I have not the deep knowledge of this specific i2c driver, but may
also an option is to set
int (*deblock)(struct udevice *bus);
in
static const struct dm_i2c_ops mvtwsi_i2c_ops = {
for this driver and do there the stuff needed to
Hey Andre,
On 6/11/23 18:20, Andre Przywara wrote:
Thanks for the update and the list! Can you confirm where you
still needed code changes compared to say my github branch plus the
changes we already discussed? Trying some guesses below, please confirm
or deny:
Pretyyy much everything
Hi again Andre,
On 12/5/22 17:45, Andre Przywara wrote:
+static struct ccu_clk_gate d1_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
+ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
+ [CLK_BUS_MMC2] = GATE(0x84c, BIT(2)),
+ [CLK_BUS_UART0]
Hey again Andre,
On 5/26/23 20:15, Sam Edwards wrote:
My "no success" is Linux stalling indefinitely at:
[ 0.123090] smp: Bringing up secondary CPUs ...
OK, correction: my "no success" was Linux being unable to access the
GIC, so boot was getting stuck. This was be
Hey Andre,
On 5/26/23 16:07, Andre Przywara wrote:
So with "no success" you are referring to the patch below? Which is the
Linux patch ported to U-Boot? And does that mean that the Linux patch
works, but the U-Boot version doesn't?
Yes, the diff below is what I've been trying to use. It's not
Hi folks,
On 5/26/23 13:27, Maksim Kiselev wrote:
There is a Linux patch that allows to bring up the second core.
https://github.com/szemzoa/awboot/blob/6ea4ae4ad7a558ad952fefee1942e260aea1a69f/linux/second_core_support_in_platsmp.patch#L10
I think this could be useful for adding PSCI support
This patch adds the necessary code to make nonsec booting and PSCI
secondary core management functional on the R528/T113.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 47 -
arch/arm/mach-sunxi/Kconfig | 2 ++
include/configs/sunxi
is to be
incorporated into the existing R528 series.
Cheers,
Sam
Sam Edwards (4):
SQUASH ME
sunxi: psci: clean away preprocessor macros
sunxi: psci: refactor register access to separate functions
sunxi: psci: implement PSCI on R528
arch/arm/cpu/armv7/sunxi/psci.c | 185
same logic.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 66 +++--
1 file changed, 47 insertions(+), 19 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index e6b73ebf2b..d9a9d73881 100644
--- a/arch
This patch contains only register defs for cpu_sunxi_ncat2.h, and should
be combined (as appropriate) into:
sunxi: introduce NCAT2 generation model
---
arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
es instead.
There are no functional changes here.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/sunxi/psci.c | 94 ++---
1 file changed, 41 insertions(+), 53 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index f866025c37..e6b73eb
The `musb_register` function returns some ERR_PTR(...) on failure,
not NULL, so update the check here appropriately.
Signed-off-by: Sam Edwards
---
drivers/usb/musb-new/sunxi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb
I believe that some sunxis (ncat2?) lack a SRAMC block,
as accessing this region results in a data abort. Checking
that it's non-null before accessing it allows this to be
set to NULL for SoCs where it's not present.
Signed-off-by: Sam Edwards
---
drivers/usb/musb-new/sunxi.c | 16
Since many sunxi boards do not implement a `board_usb_init`, it's
better if we just make the sunxi USB driver compatible with the
DM gadget model, as many other musb-new variants already are.
This change has been verified working on a T113s.
Signed-off-by: Sam Edwards
---
drivers/usb/musb-new
SUNXI_SRAMC_BASE 0
Kconfig:
+ select PHY_SUN4I_USB
...as appropriate? Those are the only changes necessary to get this USB gadget
driver working over there. :)
Many thanks,
Sam
Sam Edwards (3):
usb: musb-new: sunxi: do not attempt to access NULL SRAMC
usb: musb-new: sunxi: fix error
On 5/22/23 02:10, Heinrich Schuchardt wrote:
Hi Heinrich,
.dynamic should be aligned. Structure Elf64_Dyn requires at least 8 byte
alignment.
As best as I can tell, linkers (certainly lld[1], apparently also GNU ld
judging by its default linker scripts) themselves set the proper word
Hi Ilias,
On 5/22/23 01:00, Ilias Apalodimas wrote:
The reason we end up with both hash and gnu.hash is because the hash
style is set to 'both'. Should we perhaps use (and strip) only one of
them?
If we do keep one, it should probably be .hash -- see commit b02bfc4dfc.
I admit I'm
Hi Tom,
On 5/22/23 09:30, Tom Rini wrote:
I think objcopy is a bit of a stretch at this
point and it's not clear from the above if you're also making use of the
assembler.
I agree, since getting llvm-objcopy to play nice with this currently
requires that I make a handful of small hack edits
Hi Ilias,
On 5/22/23 00:52, Ilias Apalodimas wrote:
I can help clean up the arm architecture even further. I was toying
with the idea of having page-aligned sections and eventually map
u-boot with proper permissions per section. Right now (at least for
the majority of arm platforms) we are
Hi Marek,
Please add missing commit message and send V2.
Ah, apologies! I had (mistakenly) believed that the summary line would
be a sufficient commit message for something so trivial.
Instead I did a little research into how this got here and wrote a quick
explanation of why it's unused.
This is a remnant from when the USB controller driver managed
the reset signal itself. A patch from the very end of 2018 changed
this driver to delegate reset (and clock) management to the proper
control unit driver, but left this unused define behind.
Signed-off-by: Sam Edwards
Reviewed
Since many sunxi boards do not implement a `board_usb_init`, it's
better if we just make the sunxi USB driver compatible with the
DM gadget model, as many other musb-new variants already are.
This change has been verified working on a T113s.
Signed-off-by: Sam Edwards
---
drivers/usb/musb-new
of this patch.
Cheers,
Sam
Sam Edwards (2):
usb: musb-new: sunxi: remove unwanted printfs
usb: musb-new: sunxi: make compatible with UDC/DM gadget model
drivers/usb/musb-new/sunxi.c | 52 +---
1 file changed, 31 insertions(+), 21 deletions(-)
--
2.39.2
Per Marek's feedback, unconditional printfs in the probe function of this
USB controller driver should be removed.
This patch also slightly tidies up the return path, in preparation for
DM support.
Signed-off-by: Sam Edwards
Cc: Marek Vasut
---
drivers/usb/musb-new/sunxi.c | 8 ++--
1
but patch 2 is not, go ahead and
commit only patch 1 (unless the U-Boot project specifically avoids doing this).
Thanks for your time,
Sam
Sam Edwards (2):
usb: musb-new: sunxi: only perform SRAM initialization when necessary
usb: musb-new: sunxi: clarify the purpose of SRAM initialization
d
Signed-off-by: Sam Edwards
---
drivers/usb/musb-new/sunxi.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index 2b954601a0..85d815ad75 100644
--- a/drivers/usb/musb-new/sunxi.c
+++ b/drivers/usb/musb-new/sunxi.c
@@ -81,8 +81,6
, per discussion with Andre.
Signed-off-by: Sam Edwards
Cc: Andre Przywara
---
drivers/usb/musb-new/sunxi.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/musb-new/sunxi.c b/drivers/usb/musb-new/sunxi.c
index c05c0d5561..2b954601a0
Only the older (ca. A10, A20) sunxis need this poke for the MUSB to
function. Mimic the Linux kernel and add a `has_sram` flag to the config
structure that is only set for the specific compatibles that require
this initialization.
Signed-off-by: Sam Edwards
---
drivers/usb/musb-new/sunxi.c | 7
Hey Andre,
On 6/7/23 04:45, Andre Przywara wrote:
"syscon" really just means "a bunch of gates where AW didn't know where
else to put them".
The good ol' "kitchen sink" register block, eh? Its lack of clear,
definite purpose is even reflected in the name, because when you think
about it,
On 6/6/23 00:39, Icenowy Zheng wrote:
Well it depends on whether all SoCs differienate between SPI NOR and
SPI NAND.
Allwinner chips that (have datasheets saying they) support boot from
SPI-NAND seem quite few and far between, but I've learned that the
answer is "not all": the V3s, at
Howdy Andre,
On 6/5/23 05:04, Andre Przywara wrote:
Ah, that's a good find, but I think it goes a bit deeper:
Just to be clear, "SRAMC" stands for "SRAM controller", not "SRAM memory
block C" (which other SoCs have, but indeed not the D1/T113s). However
we (sort of) have an "SRAM controller",
The `musb_register` function returns some ERR_PTR(...) on failure,
not NULL, so update the check here appropriately.
Signed-off-by: Sam Edwards
Reviewed-by: Marek Vasut
---
drivers/usb/musb-new/sunxi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/musb-new
and CONFIG_MACH_SUN8I_R528
symbols. Also use CONFIG_SUNXI_GEN_NCAT2 symbol for the Kconfig
dependency.
Signed-off-by: Maxim Kiselev
Hi Maksim!
It took me a while on my end to get around to this one, but (with
Icenowy's SPL from SPI-NAND patchset):
Tested-by: Sam Edwards
Many thanks,
Sam
Hey hey Icenowy,
On 10/13/22 21:05, Icenowy Zheng wrote:
This patchset tries to extend SPI-based boot code in sunxi SPL to
support SPI NAND, following the same principle with current SPI NOR code
(mimicking the behavior of sunxi BROM).
Thank you for your work on this patchset; it works great
Hi, Peng Fan! Thank you for your review. :)
On 5/22/23 19:44, Peng Fan wrote:
This looks correct to me. BTW: do you met any issues during test?
I do not think I understand the question.
Are you asking, "Did you send this patch because the current MMC driver
was having problems on a real
: Clang's and other gaslike assemblers lack this
implicit alignment. Whether or not this is considered a bug in
those assemblers, it is better to ask directly for what we want.
[1]: https://sourceware.org/bugzilla/show_bug.cgi?id=12931
Signed-off-by: Sam Edwards
---
arch/arm/include/asm/linkage.h
supported in
llvm-objcopy
- llvm-objcopy also doesn't appear to speak S-Record; the u-boot.srec
target has to be deleted manually
- llvm-objcopy gets upset at some of the EFI code, since the EFI linker
scripts preserve dynamic sections that llvm-objcopy doesn't want to
strip off
Cheers,
The start-of-image marker symbol is `__image_copy_start`; by
searching for `_image_copy_start` instead, this check can
accidentally match `_image_copy_start_ofs`.
Signed-off-by: Sam Edwards
Reviewed-by: Tom Rini
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
what we don't need.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/u-boot.lds | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 8cdf08a730..bd4650bd86 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u
marking meant the markers could
end up with an unintended section inserted within that region.
Signed-off-by: Sam Edwards
Cc: Albert ARIBAUD
---
arch/arm/cpu/armv8/spl_data.c| 4 +-
arch/arm/cpu/armv8/u-boot-spl.lds| 26 +++
arch/arm/cpu/armv8/u-boot.lds
On 5/20/23 22:26, Heinrich Schuchardt wrote:
Hello Sam,
Hi Heinrich! Good to hear from you.
I guess the documentation and the CI testing would also have to be adjusted.
Ah, yeah, those are going to be big things for me to look at when this
series starts to mature out of the RFC phase. CI
LLD tends to put these at the very beginning of the file, only
for the .text 0x0 directive to end up going backward and
overlapping them, creating an error.
Since they don't appear to be used at runtime, just discard them.
Signed-off-by: Sam Edwards
---
arch/arm/lib/elf_arm_efi.lds | 3 +++
1
These symbols need to survive the IR-level dead function elimination
pass, since nothing at the IR level is referencing them (calls to these
are inserted later, at codegen time).
Signed-off-by: Sam Edwards
---
arch/arm/lib/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm
These are sometimes used by LLVM's code-generator, when it can guarantee
that the memory buffer being passed is aligned on a (4- or 8-byte)
boundary. They can safely be aliases to the unaligned versions.
Signed-off-by: Sam Edwards
---
arch/arm/lib/eabi_compat.c | 12
1 file
These are often a consequence of --pie, but they aren't actually
used in the runtime relocation code. It is better to discard them
than to aggregate them, because they tend to be of different types,
and this upsets some linkers (e.g. LLD).
Signed-off-by: Sam Edwards
---
arch/arm/cpu/u-boot.lds
This is not proper: A .text section is SHT_PROGBITS,
while the .dynamic section is SHT_DYNAMIC. Attempting to
combine them like this creates a section type mismatch.
It does seem that GNU ld does not complain, but LLVM's lld
considers this an error.
Signed-off-by: Sam Edwards
Cc: Heinrich
This is sometimes used by LLVM's code generator.
Signed-off-by: Sam Edwards
---
arch/arm/lib/eabi_compat.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/lib/eabi_compat.c b/arch/arm/lib/eabi_compat.c
index f7029918d4..059ca07265 100644
--- a/arch/arm/lib/eabi_compat.c
+++ b
On 12/5/22 17:45, Andre Przywara wrote:
From: Samuel Holland
Since the D1 CCU binding is defined, we can add support for its
gates/resets, following the pattern of the existing drivers.
Signed-off-by: Samuel Holland
Reviewed-by: Andre Przywara
Acked-by: Sean Anderson
Hi Andre,
So far so
Only the older (ca. A10, A20) sunxis need this poke for the MUSB to
function. Mimic the Linux kernel and add a `has_sram` flag to the config
structure that is only set for the specific compatibles that require
this initialization.
Signed-off-by: Sam Edwards
Reviewed-by: Andre Przywara
Tested
ther invite somebody to "DO" it. :)
Thank you once again for your continued efforts,
Sam
Sam Edwards (2):
usb: musb-new: sunxi: only perform SRAM initialization when necessary
usb: musb-new: sunxi: clarify the purpose of SRAM initialization
drivers/usb/musb-new/sunxi.c | 43 +
Hi Andre,
On 12/5/22 17:45, Andre Przywara wrote:
Please let me know if you have any opinions!
I believe I promised you last month I'd let you know once I had a build
I'm happy with, and I'm pleased to say that I think I've reached that
point. I'm running quite rapidly out of sharp edges to
Hi Andre,
I've applied most of this feedback (most of which comes as a relief; I
dislike inventing names for mystery bits) in preparation to send a v2,
but had two questions:
On 6/9/23 04:13, Andre Przywara wrote:
The new comments and function name are not from any official source,
but are
this initialization being about configuring a FIFO has
pretty much been debunked for years now.
This cleanup also adds a TODO comment about runtime discovery
of the SYSCON base, per discussion with Andre.
Signed-off-by: Sam Edwards
Cc: Andre Przywara
---
drivers/usb/musb-new/sunxi.c | 38
Hi I²C maintainers,
My target has the following devices sharing one bus:
- 24C02 EEPROM
- Realtek 8370 Ethernet switch
- Allwinner T113-s3 (running U-Boot, interfacing via MVTWSI)
The RTL8370 is configured in "EEPROM autoload" mode, so on reset
it will load the full contents of the EEPROM.
The functions `psci_get_context_id` and `psci_get_target_pc`
are written in C, so the C compiler may clobber registers r0-r3.
Do not use these registers to save data across calls.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7/psci.S | 6 +++---
1 file changed, 3 insertions(+), 3 deletions
The nonsec code overrides/handles these:
- Setting PMR to 0xFF happens earlier, in _nonsec_init, so this is
redundant.
- The NS bit is not yet set: it gets set later in _secure_monitor.
Trying to clear it here is pointless and misleading.
Signed-off-by: Sam Edwards
---
arch/arm/cpu/armv7
Hi again Andre,
On 12/5/22 17:45, Andre Przywara wrote:
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index b6ffbff883c..3763ec3d2e4 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -177,7 +177,7 @@ static int gpio_init(void)
#error
controllers
Signed-off-by: Maxim Kiselev
Tested-by: Sam Edwards
Cheers,
Sam
SPI flash that connects to the SPI0 controller.
This controller is the same for R329/D1/R528/T113s SoCs and
should be supported by the sun50i-r329-spi driver.
So let's add its DT nodes.
Signed-off-by: Maxim Kiselev
Reviewed-by: Sam Edwards
Cheers,
Sam
Hi Andre,
Series looks good so far! I'm trying to move my testing build over to it
now; I will report back when I've been running on it for a little bit.
On 7/21/23 07:45, Andre Przywara wrote:
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 7ac50c4ae8c..2db4a2d73ca 100644
---
Hi folks,
On 7/7/23 09:52, Yifan Zhao wrote:
diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h
index 4af7c91560..433a3c6c1e 100644
--- a/fs/erofs/internal.h
+++ b/fs/erofs/internal.h
+/* make sure that any user of the erofs headers has at least 64bit off_t type
*/
+extern int
is found to be held low, in an attempt to force the bus back to
an idle state. This patch only resets the controller in case something
else had previously upset it, and (in principle) results in no
externally-observable change in behavior.
Signed-off-by: Sam Edwards
---
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