El Tue, Sep 05, 2023 at 11:02:44AM -0400, Sean Anderson deia:
> On 9/4/23 08:59, Xavier Drudis Ferran wrote:
> > El Sun, Sep 03, 2023 at 08:17:26AM +, Jonas Karlman deia:
> >
> >> > Fundamentally, we can't really deal with unaligned images without a
> >&
El Mon, Sep 04, 2023 at 11:25:06AM +0200, Fabrice Gasnier deia:
>
> IMHO, the OHCI should have failed too in this example, instead of
> silently ignoring the error. Hopefully it has probed.
>
> The clk_get_bulk() code does a similar job compared to ohci current
> code. It counts all clock
El Sun, Sep 03, 2023 at 08:17:26AM +, Jonas Karlman deia:
> > Fundamentally, we can't really deal with unaligned images without a
> > bounce-buffer. The method used by SPL_LOAD_FIT_IMAGE_BUFFER_SIZE will
> > continue working, since we call into the FIT routines to load the image.
Yes
> > I
Is the change of behaviour intended when a clock or reset is not found ?
(see below)
El Wed, Aug 30, 2023 at 10:01:49AM +0200, Fabrice Gasnier deia:
> Make usage of clock and reset bulk API in order to simplify the code
>
> Signed-off-by: Fabrice Gasnier
> ---
>
>
El Mon, Sep 04, 2023 at 02:20:21PM +0200, Fabrice Gasnier deia:
> Make usage of clock and reset bulk API in order to simplify the code
>
> Reviewed-by: Marek Vasut
Reviewed-by: Xavier Drudis Ferran
Sorry. I don't know why I used the wrong address before.
> Signed-off-by: Fab
El Wed, Sep 06, 2023 at 02:25:11PM +0200, Heinrich Schuchardt deia:
> spl_blk_load_image() should not return an uninitialized value if
> blk_get_devnum_by_uclass_id() fails.
>
> Fixes: 8ce6a2e17577 ("spl: blk: Support loading images from fs")
> Reported-by: Xavier Drudis
El Wed, Oct 11, 2023 at 09:56:20PM -0400, Sean Anderson deia:
> This add some basic functions to create images, and a test for said
> functions. This is not intended to be a test of the image parsing
> functions, but rather a framework for creating minimal images for testing
> load methods. That
uchardt
Reviewed-by: Xavier Drudis Ferran
> ---
> doc/arch/arm64.ffa.rst | 20 ++--
> doc/board/AndesTech/ae350.rst | 2 +-
> doc/board/actions/cubieboard7.rst | 4 ++--
> doc/board/actions/index.rst| 2 +-
> doc/boa
El Mon, Nov 06, 2023 at 08:54:03AM -0500, Sean Anderson deia:
> On 11/6/23 07:35, Xavier Drudis Ferran wrote:
> > Thanks for your work. I'm still reading... but...
> >
> >
> > El Sun, Nov 05, 2023 at 09:25:46PM -0500, Sean Anderson deia:
> > > diff -
El Mon, Oct 23, 2023 at 10:21:52AM +0200, Heinrich Schuchardt deia:
>
> We will need separate patches for LGPL-2.0+ and LGPL-2.1+, too.
>
That'd be for LGPL-2.1+
The only case of LGPL-2.0+ in code is included in the patch you sent.
Well, there's another appearance of LGPL-2.0+ in
El Sun, Oct 22, 2023 at 07:47:07PM +0200, Heinrich Schuchardt deia:
> diff --git a/drivers/sound/tegra_ahub.c b/drivers/sound/tegra_ahub.c
> index 495a29c513..28f392504d 100644
> --- a/drivers/sound/tegra_ahub.c
> +++ b/drivers/sound/tegra_ahub.c
> @@ -1,4 +1,4 @@
> -// SPDX-License-Identifier:
Thanks for your work. I'm still reading... but...
El Sun, Nov 05, 2023 at 09:25:46PM -0500, Sean Anderson deia:
> diff --git a/include/spl.h b/include/spl.h
> index 951e136b9ea..ecfc50e0095 100644
> --- a/include/spl.h
> +++ b/include/spl.h
> @@ -297,10 +297,10 @@ struct spl_load_info {
>
d clk_release_all()")
> Signed-off-by: Eugen Hristev
Reviewed-by: Xavier Drudis Ferran
> ---
> drivers/clk/clk-uclass.c | 7 ---
> include/clk.h| 4 ++--
> 2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/clk-uclass.
El Wed, Nov 08, 2023 at 10:59:13AM -0500, Sean Anderson deia:
>
> OK, what about
>
> @offset: Offset to read from in bytes. This must be a multiple of
> @load->bl_len.
>
> --Sean
Great. Thank you.
of the parameters are for SOCs not even in U-Boot yet. To save a
little space it avoids most data for SOCs not configured in the build.
It even mentions CONFIG_ROCKCHIP_RK3066 and CONFIG_ROCKCHIP_RK3366
despite those constants not being in Kconfig yet.
Signed-off-by: Xavier Drudis Ferran
---
configs
_SPL_RESERVE_IRAM
put it at 0x4000 but in my tests this wasn't enough.
Signed-off-by: Xavier Drudis Ferran
---
configs/rock-pi-4-rk3399_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/rock-pi-4-rk3399_defconfig
b/configs/rock-pi-4-rk3399_defconfig
index 8861f13878..510028b095 100644
boot from
MMC1" message.
Signed-off-by: Xavier Drudis Ferran
---
drivers/clk/rockchip/clk_rk3399.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3399.c
b/drivers/clk/rockchip/clk_rk3399.c
index 7d31a9f22a..fc3a5d4e9b 100644
--- a/drive
be welcome,
but I'm not sure whether they need the new driver. For now I only
configured it for Rock Pi 4.
Thanks beforehand for any feedback. Specially if I should run any tests.
--
Xavier Drudis Ferran
/c41cb4c454570127ad3238f6b901fbf3aa773c
Link: [2]
https://github.com/radxa/kernel/blob/release-4.4-rockpi4/drivers/mtd/spi-nor/spi-nor.c
Link: [3]
https://github.com/radxa/kernel/commit/8216f17965de7bc7ced7092aab0e2bfe16838a4
Link: [4] https://www.xtxtech.com/download/?AId=157
Signed-off-by: Xavier Drudis Ferran
ufacturer spi_nor_xmc;
+extern const struct spi_nor_manufacturer spi_nor_xtx;
extern const struct attribute_group *spi_nor_sysfs_groups[];
diff --git a/drivers/mtd/spi-nor/xtx.c b/drivers/mtd/spi-nor/xtx.c
new file mode 100644
index 0..3db8bfd93
--- /dev/null
+++ b/drivers/m
This Flash part does not use octal mode. But soft reset seems to
be required to boot from SPI NOR Flash in Rock Pi 4B.
Cc: Jagan Teki
Cc: Vignesh R
Signed-off-by: Xavier Drudis Ferran
---
drivers/mtd/spi/spi-nor-core.c | 54 ++
include/linux/mtd/spi-nor.h
: Jagan Teki
Signed-off-by: Xavier Drudis Ferran
---
drivers/spi/spi-mem.c | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 9c1ede1b61..4dc90addb3 100644
--- a/drivers/spi/spi-mem.c
read, sf erase, sf
write, sf read and then boot linux and flashrom can write to
it. Sometimes flashrom seems to fail to write when at U-Boot stage
there was no sf read or write, not sure why.
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Signed-off-by: Xavier Drudis Ferran
Thanks for your work.
El Tue, Jul 05, 2022 at 03:04:15PM +0200, Johan Jonker deia:
> From: Johan Jonker
>
> The Rockchip SoCs with a NAND as boot device need
> a special Rockchip IDB block device to transfer the data
> from the rockusb gadget to the NAND driver.
>
Sorry for the fast
ted-by: YouMin Chen
> Signed-off-by: Lee Jones
My board doesn't suffer with the issue resolved by this series,
however I did apply it and nothing regressed.
Tested-by: Xavier Drudis Ferran
> ---
> drivers/ram/rockchip/sdram_rk3399.c | 36 +
> 1 file changed
issue resolved by this series,
however I did apply it and nothing regressed.
Tested-by: Xavier Drudis Ferran
> ---
> drivers/ram/rockchip/sdram_rk3399.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/ram/rockchip/sdram_rk3399.c
> b/drivers/ra
e reported accurately.
>
Not obvious to me what "mhz" means (mHz? MHz? Hz?)
and so not obvious to me by how many orders of magnitude
it was wrong but in any case now the message is correct and clear.
Tested-by: Xavier Drudis Ferran
> Signed-off-by: Lee Jones
> ---
> drivers/ram
This patch is option 3. Looked like the simplest and most performant.
But it might not be what's wanted, so comments wellcome.
Link: [1] https://lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Cc: M
which
> the SPL booted.
>
Yes, I also saw that. I changed and tested it at some time, but since there
were other changes, I hesitate to send a Tested by for your patch. FWIW:
Reviewed-by: Xavier Drudis Ferran
> Fixes: 822556a93459 ("arm: dts: sync the Rockhip 3399 SoCs fr
El Wed, Jun 22, 2022 at 10:47:31AM +0200, Xavier Drudis Ferran deia:
> The Radxa Rock Pi 4 board is sold from revision 1.4 with a soldered
> 4Mb SPI NOR Flash. This series allows to use it from U-Boot and boot
> from it.
>
Hello.
Is there any interest in this ?
This weekend I did
El Fri, Jun 10, 2022 at 11:59:23AM +0200, LABBE Corentin deia:
> --- a/drivers/core/lists.c
> +++ b/drivers/core/lists.c
> @@ -20,6 +20,10 @@
> #include
> #include
>
> +static int _errorcount;
> +int errorlist[1024];
> +int errorcount;
> +
> struct driver *lists_driver_lookup_name(const
El Fri, Jun 10, 2022 at 04:42:55PM +0200, Stefan Herbrechtsmeier deia:
> Hi Michal,
>
> what is the default entry address for the aft / bl31.bin?
>
> I have a bl31.bin with an entry address of 0x1000 and this is inside the
> BSS.
>
Me too, load address at 0x1000, but for me in SPL text, not
El Fri, Jun 03, 2022 at 03:17:05PM +0200, Jerome Forissier deia:
> First, I noticed that spl_load_fit_image() may write memory outside the range
> given in the image node. For example on RockPi 4B I have the following FIT
> (irrelevant parts omitted):
>
> / {
> images {
>
El Tue, Jun 14, 2022 at 11:16:42AM -0700, Jerome Forissier deia:
> Oops, that should rather be:
>
> +#if (CONFIG_SPL_LOAD_FIT_IMAGE_BUFFER_SIZE == 0)
>
I tested with this change, not that my opinion counts much, but
anyway:
Reviewed-by: Xavier Drudis Ferran
Tested-by: Xavier D
Hello.
Thank you for your work, simplifying and generalizing code,
and sorry that I hadn't seen this series before.
I'm new to U-Boot so I'm sorry if I waste your time with silly
questions, but I can't seem to understand some details.
1- Does some info->read implementation ever want its
El Fri, Jun 10, 2022 at 11:32:59PM -0700, RisingEdgeIndustries deia:
> Hello,
>
> I'm trying to update some of the u-boot environment variables when I build
> my linux Image using petalinux for the zynq 7000 (zedboard).
>
Hello, not an expert, but I hope I can help and that people correct me i
Sorry for the noise.
El Fri, Jun 03, 2022 at 04:58:38PM +0200, Xavier Drudis Ferran deia:
>
> In my Rock Pi 4B this does not happen. It happily writes the 17 blocks.
> Or it's just that I'm not noticing the problem ? Does it hang or give you
> an error, or do you just find it ou
I just checked this still works in next. No v2 needed (until feedback,
because I've heard about nodes providing two devices and maybe you
prefer that, so far I'd still see it too complex).
El Fri, Jul 01, 2022 at 08:59:59PM +0200, Xavier Drudis Ferran deia:
>
> arch/arm/dts/rk3399.dt
The Radxa Rock Pi 4 board is sold from revision 1.4 with a soldered
4Mb SPI NOR Flash. This series allows to use it from U-Boot and boot
from it.
This series applies to u-boot/master.
Changes since v2:
- rebased on master
- droped 5th path, and enabled CONFIG_SPL_DM_SEQ_ALIAS instead
-off-by: Xavier Drudis Ferran
Cc: Jagan Teki
Cc: Vignesh R
---
drivers/mtd/spi/spi-nor-ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 4fe8b0d92c..b09df00bab 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers
The Radxa Rock Pi 4 board is sold from revision 1.4 with a soldered
4Mb SPI NOR Flash. This series allows to use it from U-Boot and boot
from it.
This series applies to u-boot/master.
Changes since v2:
- rebased on master
- droped 5th path, and enabled CONFIG_SPL_DM_SEQ_ALIAS instead
.
Changed since v2:
- no changes
Changed since v1:
- no changes
Signed-off-by: Xavier Drudis Ferran
Cc: Jagan Teki
---
drivers/spi/spi-mem.c | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi
: Philipp Tomsich
Cc: Kever Yang
Signed-off-by: Xavier Drudis Ferran
---
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 18 ++
configs/rock-pi-4-rk3399_defconfig| 22 ++
2 files changed, 40 insertions(+)
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
odes until SNOR_PROTO_1_1_1 works and then remember the reset_proto.
This tries to be useful for other boards, but I still don't know any
other that needs it and what would work there.
Signed-off-by: Xavier Drudis Ferran
Cc: Jagan Teki
Cc: Vignesh R
---
drivers/mtd/spi/spi-nor-c
ossible loading media for U-Boot proper.
>
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
>
Tested on a Rock-Pi-4B and didn't see any regression.
Tested-by: Xavier Drudis Ferran
> - RFC because only tested on Puma Haikou RK3399
>
> common/spl/spl.c | 12
> no need to do this in the rk3399-specific code, so let's remove it.
>
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
>
Tested on a Rock-Pi-4B and didn't see any regression.
Tested-by: Xavier Drudis Ferran
> - This patch depends on
> https://lore.ke
with the small correction:
Tested-by: Xavier Drudis Ferran
> Fixes: 07586ee4322a ("rockchip: rk3399: Support common spl_board_init")
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
>
> v2:
> - use IS_ENABLED checks,
>
> arch/arm/mach-rockc
haven't seen any regression. So, with this small correction:
Tested-by: Xavier Drudis Ferran
> v2:
> - use IS_ENABLED checks,
>
> arch/arm/mach-rockchip/rk3399/rk3399.c | 45 ++
> 1 file changed, 24 insertions(+), 21 deletions(-)
>
> diff --git a/arc
nd boot_devices
> node paths.
>
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
Tested on a Rock-Pi-4B and didn't see any regression.
Tested-by: Xavier Drudis Ferran
Reviewed-by: Xavier Drudis Ferran
> arch/arm/mach-rockchip/rk3399/rk3399.c | 2 +-
> 1 file
t been consistent, and I'd do it like in this patch,
but I don't feel strongly about any option nor pretend to stop any
discussion.
Tested on a Rock-Pi-4B and didn't see any regression.
Tested-by: Xavier Drudis Ferran
> ---
> arch/arm/mach-rockchip/rk3399/rk3399.c | 4 ++--
> 1 file cha
ipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Link: [1] https://www.rockchip.fr/Rockchip%20RK3399%20TRM%20V1.4%20Part1.pdf
Link: [2] https://patchwork.ozlabs.org/project/uboot/list/?series=305766
Signed-off-by: Xavier Drudis Ferran
---
drivers/clk/rockchip/clk_rk3399.c
El Mon, Jul 18, 2022 at 01:00:03PM +0200, Michal Suchánek deia:
> mmc@fe31: 3
> mmc@fe32: 1 (SD)
> mmc@fe33: 0 (eMMC)
>
> This is not consistent with any of the above.
>
I agree, but this is mmc, and this thread was about spi.
El Fri, Jul 15, 2022 at 05:09:49PM +0200, Quentin Schulz deia:
> From: Quentin Schulz
>
> The check to perform is on CONFIG_SPL_GPIO and not SPL_GPIO.
> Because this was never compiled in, it missed an include of cru.h that
> was not detected before. Let's include it too.
>
> Also switch to
El Mon, Jul 25, 2022 at 12:54:04PM +0200, Quentin Schulz deia:
> You'd need a new binman entry I assume for calling mkenvimage.
>
> It's not a super safe assumption that CONFIG_ENV_OFFSET will be used for
> declaring where the environment is stored. E.g., CONFIG_ENV_OFFSET for Puma
> declares
Note: I removed a few recipients from Cc: with a quite random criteria,
just to avoid error messages from the list software that there were
too many addresses in Cc:. I hope those will get it from the list anyway
and sorry if this is a problem.
> I'm sure I'm just missing out on something
};
#endif
u-boot-spl {
};
};
#ifdef CONFIG_ARM64
#ifdef CONFIG_USE_SPL_FIT_GENERATOR
blob {
filename = "u-boot.itb";
#else
collection {
content = <&/binman/itb>;
#endif
El Mon, Jul 25, 2022 at 07:29:53PM +0200, Xavier Drudis Ferran deia:
>
> I copy here the rockchip-u-boot.dtsi file and then 2 patches on top of yours.
>
Sorry I copied a dirty version that din't work. The patches were correct, the
dtsi wasn't.
> #else
>
Thank you for your time looking at the patch.
El Tue, Jul 26, 2022 at 12:43:06PM +0530, Pratyush Yadav deia:
>
> Please don't put the changelog in the commit message. Put it below the 3
> dashed lines below.
>
Sorry. Will try to remember it next time. Not sure there's a next version of
this
El Tue, Jul 26, 2022 at 02:39:09PM +0530, Pratyush Yadav deia:
>
> Yes, this is indeed a chicken and egg problem of sorts. The octal mode
> soft reset I added is a hack that gets _some_ flashes working but not
> all. I see 3 possible ways to solve this:
>
But it was a hack that solved a
};
#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
simple-bin-spi {
filename = "u-boot-rockchip-spi.bin";
pad-byte = <0xff>;
mkimage {
args = "-n", CONFIG_SYS_SOC, "-T", "rkspi";
#ifd
El Tue, Jul 26, 2022 at 09:15:10PM +0200, Jerome Forissier deia:
>
> > I'm sending a patch below that adds a couple of configuration properties to
> > binman so that split-elf can fill the properties. How many segments are
> > in bl31.elf or optee is not something that we have in CONFIGs, I
El Tue, Jul 26, 2022 at 09:08:25PM +0200, Xavier Drudis Ferran deia:
> want u-boot.itb it runs binman -a of-list="rk3399-rock-pi-4b.dts
> rockchip-itb-u-boot.dts"
Sorry. I mistook the parameter. That would only generate two config entries and
2 fdts in the .itb image.
W
El Sat, Jul 23, 2022 at 02:07:30PM +0200, Johan Jonker deia:
>
> > + mkimage {
> > + args = "-n", CONFIG_SYS_SOC, "-T", "rksd";
>
> > +#ifndef CONFIG_TPL
> > + u-boot-spl {
> > + };
> > };
> > +#else
> > +
El Fri, Jul 22, 2022 at 01:34:58PM +0200, Quentin Schulz deia:
> From: Quentin Schulz
>
> This migrates the generation of u-boot-rockchip.bin from Makefile to binman
> completely. There is therefore no idbloader.img anymore as it is created on
> the fly by binman.
>
Thanks a lot.
I've tested
The Radxa Rock Pi 4 board is sold from revision 1.4 with a soldered
4Mb SPI NOR Flash. This series allows to use it from U-Boot and boot
from it.
This series applies to u-boot/next.
Changes since v1:
- Changed bus number to 1 in SPL to match U-Boot proper (before it
was bus 0 in SPL and
previously
used). This leverages the fixed supports_op() to take into account
controller and device.
Signed-off-by: Xavier Drudis Ferran
Cc: Jagan Teki
Cc: Vignesh R
---
drivers/mtd/spi/spi-nor-core.c | 98 ++
include/linux/mtd/spi-nor.h| 5 +
.
Changes from v1:
none (just retested with current next)
Signed-off-by: Xavier Drudis Ferran
Cc: Jagan Teki
---
drivers/spi/spi-mem.c | 34 ++
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index
and SPL (at patch 5/5)
Signed-off-by: Xavier Drudis Ferran
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
---
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 18 ++
configs/rock-pi-4-rk3399_defconfig| 22 ++
2 files changed, 40 insertions(+)
diff
Oops. Sorry to mess up the Reply-To.
I meant to send 1/5 .. 5/5 as replies to 0/5 but I sent them out of
mail thread.
Drudis Ferran
Cc: Jagan Teki
Cc: Vignesh R
---
drivers/mtd/spi/spi-nor-ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 67278c40e3..b8df694202 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi
to bus 1.
Changes since v1:
- new patch in v2.
Signed-off-by: Xavier Drudis Ferran
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
---
arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi
b/arch/arm
Hello, and thanks for you work
El Fri, Jul 15, 2022 at 05:14:25PM +0200, Quentin Schulz deia:
> From: Quentin Schulz
>
> This makes sure regulators that need to be turned on or off at boot are
> turned on or off in the SPL.
>
> This may be required for the SPL to do some operations, such as
El Mon, Jul 18, 2022 at 10:34:54AM +0200, Xavier Drudis Ferran deia:
>
> Can we remove the #if ?
Not sure if I was clear.
I meant remove the #if and #endif and leave an inconditional #include.
El Mon, Jul 18, 2022 at 10:33:18AM +0200, Quentin Schulz deia:
> Hi Xavier,
>
> On 7/15/22 18:30, Xavier Drudis Ferran wrote:
> > Spi0 is not needed in SPL and SPL could be a little smaller without it,
> > but then the SF_DEFAULT_BOOT would have to be 0 to refer to spi1, and
El Mon, Aug 01, 2022 at 01:13:27PM -0600, Simon Glass deia:
> >
> > Am I completely lost or does what I want to do make some kind of sense?
>
> Well I still feel that we should handle this properly in binman.
>
I respect your feelings but would you care explaining the goal of binman?
I first
El Sat, Aug 27, 2022 at 11:20:17AM +0800, Kever Yang deia:
> The idea for dtsi now is to sync the kernel and U-Boot dts, and Linux
> distribution will
> use the dts from U-Boot. If we change the dts property in -u-boot.dts, it
> will also pass
> to kernel, which make kernel function not available.
El Sun, Aug 07, 2022 at 04:44:04PM +0200, Michal Suchánek deia:
> Hello,
>
> when compiled with clock debug rk3399 cannot be booted because memory
> setup code triggers clock assertion:
>
> U-Boot TPL 2022.07-00038-g61e11a8e9f-dirty (Aug 07 2022 - 16:13:17)
> TPL PLL at ff76: fbdiv=50,
El Sun, Aug 07, 2022 at 04:33:26PM -0600, Simon Glass deia:
> This is an attempt to answer the comments provided by Xavier [1].
>
Thank you. Sorry if I point out silly things too. No agony intended.
>
> +Note that binman can itself can create a FIT. This helps to move mkimage
one "can" too
El Tue, Aug 02, 2022 at 06:41:40AM -0600, Simon Glass deia:
>
> It seems we need a lot more guidance here. I can help write more into
> the packaging docs, perhaps:
>
> https://u-boot.readthedocs.io/en/latest/develop/package/binman.html#motivation
>
> Can you please suggest a few questions to
El Mon, Aug 08, 2022 at 11:22:49PM +0530, Jagan Teki deia:
>
> If I remember correctly when I work with YouMin on LPDDR4 the initial
> code to start to check with was 50MHz (It was not working at that time
> with 48MHz). Not sure what to make other changes to fix that to try on
> 48MHz.
>
Not
El Thu, Dec 08, 2022 at 08:56:57AM +1300, Simon Glass deia:
> + @tee-SEQ {
> + fit,operation = "split-elf";
> + description = "TEE";
> + type = "tee";
> +
[2]
https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/#2954536
[3]
https://patchwork.ozlabs.org/project/uboot/patch/Y44+ayJfUlI08ptM@localhost/#3016099
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Cc: M
El Thu, Dec 08, 2022 at 09:12:08PM +0100, Marek Vasut deia:
> On 12/8/22 17:53, Xavier Drudis Ferran wrote:
>
> [...]
>
> > +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> > @@ -7,7 +7,7 @@
> >*/
> > #include
> > -#include
>
Cc: Sean Anderson
Cc: Marek Vasut
Signed-off-by: Xavier Drudis Ferran
---
Changes:
v4: move v3 to one patch in the series and add a second patch
to add operations to enable disable the usb2phy 480Mhz clock.
Also, honour clock-output-names for what is worth.
v3: implement opt
s
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Cc: Marek Vasut
Signed-off-by: Xavier Drudis Ferran
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/p
/patch/Y5IWpjYLB4aXMy9o@localhost/#3018135
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Cc: Marek Vasut
Signed-off-by: Xavier Drudis Ferran
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 79 ++-
1 file changed, 77
El Mon, Dec 05, 2022 at 08:08:40PM +0100, Marek Vasut deia:
> On 12/5/22 19:54, Xavier Drudis Ferran wrote:
> > 5- Trying to replicate linux and have usb2phy somehow provide a clk,
> > or have a separate clock device for usb2phy in addition to the phy
> > devi
//lkml.kernel.org/lkml/1731551.Q6cHK6n5ZM@phil/T/
[2]
https://patchwork.ozlabs.org/project/uboot/patch/20220701185959.GC1700@begut/#2954536
Cc: Simon Glass
Cc: Philipp Tomsich
Cc: Kever Yang
Cc: Lukasz Majewski
Cc: Sean Anderson
Cc: Marek Vasut
Signed-off-by: Xavier Drudis Ferran
-
El Sun, Dec 11, 2022 at 06:20:41AM +0100, Marek Vasut deia:
> On 12/9/22 16:47, Xavier Drudis Ferran wrote:
> > This clock has no users but appears in a phandle list used by
> > ehci-generic.c to bulk enable it. The phandle list comes from linux,
> > where it is needed for s
El Tue, Jan 24, 2023 at 09:07:58AM +0100, Patrice CHOTARD deia:
> Hi Marek
>
> On 1/23/23 23:32, Marek Vasut wrote:
> > In case CONFIG_DM_RESET=n, reset_get_bulk() returns -ENOTSUPP.
> > Do not fail in that case either. This is a valid use case, e.g.
> > in case the reset driver is a no-op and
be correctly in patchwork, should I resend ?
I guess I messed up subject lines ?
I think there are other rk3399 boards that have similar .dtsi files,
but I haven't investigated thoroughly. Do they all have broken EHCI ?
If someone has a rk3399 board with working EHCI maybe they should test
your patch and try usb start ; usb stop and usb start ; usb reset ?
[1] https://lists.denx.de/pipermail/u-boot/2023-February/510672.html
Thanks,
--
Xavier Drudis Ferran
El Wed, Mar 08, 2023 at 01:59:54PM +0200, Eugen Hristev deia:
> On 3/8/23 13:30, Xavier Drudis Ferran wrote:
> > El Fri, Mar 03, 2023 at 09:31:33AM +0200, Eugen Hristev deia:
> > > @@ -105,6 +130,17 @@ static int rockchip_usb2phy_power_off(struct phy
> > > *phy)
>
output
clock is correctly enabled or disabled when everything seems to work
fine already without enabling it, but it needs to be enabled simply
because of a dts coming from linux where it seems to have effects on
suspend/resume.
Thanks,
--
Xavier Drudis Ferran
El Fri, Mar 03, 2023 at 10:42:20AM +0100, Christoph Fritz deia:
> > Changes:
> >
> > v5: fixes a bug that Christoph Fritz discovered, consisting in the
> > wrong eror code returned when enabling or disabling the clock
> > because property_enable() returns an error code in
I'm sorry but I haven't been able to reproduce your issue.
El Fri, Mar 03, 2023 at 11:26:46AM +0100, Xavier Drudis Ferran deia:
> El Fri, Mar 03, 2023 at 10:42:20AM +0100, Christoph Fritz deia:
>
> Unfortunately I don't think I have any usb-ethernet dongle here to test...
>
[...
c: Sean Anderson
Cc: Marek Vasut
Cc: Christoph Fritz
Signed-off-by: Xavier Drudis Ferran
---
Changes:
v5: fixes a bug that Christoph Fritz discovered, consisting in the
wrong eror code returned when enabling or disabling the clock
because property_enable() returns an erro
Majewski
Cc: Sean Anderson
Cc: Marek Vasut
Cc: Christoph Fritz
Signed-off-by: Xavier Drudis Ferran
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/ro
: Lukasz Majewski
Cc: Sean Anderson
Cc: Marek Vasut
Signed-off-by: Xavier Drudis Ferran
---
v5: ignores the return value from property_enable() which is not
an error code in U-Boot (unlike in linux). This avoid a false
failure of rockchip_usb2phy_clk_disable() that interfered
Ok. New test.
This uses yesterday morning's next branch.
commit 5b589e139620214f
Merge: cc5a940923 32d2461e04
Merge branch 'next_net/phy_connect_dev'
USB2 does not work for rk3399 in next (fixes are in master, thanks),
but USB3 is enough.
I compiled for rock-pi-4-rk3399_defconfig
flashed
El Mon, Jun 12, 2023 at 10:17:38PM +0100, Simon Glass deia:
>
> I'm not sure what is going on here. Which version are you testing? Do
> you have these two commits?
>
> 8c29b73278d6 bootstd: usb: Avoid initing USB twice
> 9fea3a799dde usb: Tidy up the usb_start flag
>
> Regards,
> Simon
Yes, I
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