差出人: Simon Glass
送信日時: 2023年10月26日 03:23
宛先: Niek Nooijens / OC-IAB PBD-C DEVEL 1-1
CC: u-boot@lists.denx.de
件名: Re: quick question about TPM
Hi Niek,
On Tue, 24 Oct 2023 at 19:26, niek.nooij...@omron.com
wrote:
>
> Hi Simon
>
> Driver model is enabled, so it's
Simon Glass
送信日�r: 2023年10月25日 03:03
宛先: Niek Nooijens / OC-IAB PBD-C DEVEL 1-1
CC: u-boot@lists.denx.de
件名: Re: quick question about TPM
Hi Niek,
On Tue, 24 Oct 2023 at 04:51, niek.nooij...@omron.com
wrote:
>
> Hi
>
> Just a quick question. I'm developing a platform using the
Hi
Just a quick question. I'm developing a platform using the
socfpga_cyclone5_defconfig
everything is working, linux boots, but we decided to add a TPM to it's SPI bus.
For some reason the TPM support menu in the menuconfig is disabled and I can't
seem to find out why, or which file disables
Hi there
After the NV-memory read/write code I'm here again for another patch.
This time I implemented code to allow an NV-index to be locked behind a PCR
value.
This can be used together with the new measured-boot code allowing you to store
encryption keys inside the TPM and locking them
Hi dan
This might be because I used the checkpatch.pl script.
Here's one without it.
Niek
=START PATCH ===
From de056f510156a2fa1b4b439e1fa1f44516aa8add Mon Sep 17 00:00:00 2001
From: Niek Nooijens
Date: Tue, 20 Feb 2024 13:42:57 +0900
Subject:
Hi There
I added some new commands to the TPM2 command to allow read/writes to
nv_memory. I also implemented the nv_define and nv_undefine commands so spaces
can be created/deleted.
Still need to test with PCR policies, but at least for now we can store values
in the TPM.
Here's the patch:
*/
-
- tpm_u16(count),
+ /*end auth handle */
+ tpm_u16(count),/*size of buffer - 2 bytes*/
+ /*data (buffer)*/
+ /*offset -> the octet offset into the NV Area*/
};
size_t response_len = COMMAND_BUFFER_SIZE;
u8 response[COMMAND_BU
23年11月29日 22:17
宛先: Niek Nooijens / OC-IAB PBD-C DEVEL 1-1
CC: u-boot@lists.denx.de
件名: Re: TPM SPI issue
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Hi Niek,
On Wed, Nov 29, 2023 at 9:51 AM niek.nooij...@omron.com
Hi there
I have the same issue as here:
https://community.infineon.com/t5/OPTIGA-TPM/I-MX8-TPM-SLB9670-SPI-Com-Error/td-p/472533
apparently the CS is released in between responses. Can you help me solve this?
Thnx!
Niek
<https://docs.u-boot.org/en/latest/develop/sending_patches.html>
Thanks
/Ilias
On Wed, 21 Feb 2024 at 02:12, niek.nooij...@omron.com
wrote:
>
> Hi dan
>
> This might be because I used the checkpatch.pl script.
> Here's one without it.
>
> Niek
>
> ===
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