On Fri, 2011-06-03 at 02:46 -0500, Kumar Gala wrote:
On May 26, 2011, at 6:25 PM, York Sun wrote:
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c |8
Kumar,
These two patches replace previous 3/7, 6/7, 7/7
[PATCH 3/7] powerpc/mpc8xxx: Enable calculation for fixed DDR chips
[PATCH 6/7] powerpc/mpc8xxx: Adding fallback to raw timing on supported boards
[PATCH 7/7] powerpc/mpc8xxx: change raw timing function call parameters
York
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch
We used to have fixed parameters for soldered DDR chips. This patch introduces
CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR
chip datasheet, implemneted in board-specific files or header files.
Signed-off-by: York Sun york...@freescale.com
---
README
On Tue, 2011-06-07 at 08:35 -0500, Kumar Gala wrote:
+- CONFIG_SYS_DDR_RAW_TIMING
+ Get DDR timing information from other than SPD. Common with
+ soldered DDR chips onboard without SPD. DDR raw timing
+ parameters are extracted from datasheet and hard-coded
If DDR initialziation uses a speed table and the speed is not matched, print
a warning message instead of silently ignoring.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c |6 ++
board/freescale/mpc8572ds/ddr.c |8
board/freescale
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has data
width and primary sdram width. The latter one has different meaning for DDR3.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/options.c | 35 ---
1 files
Allow overriding RCW for all RDIMM, not only quad-rank ones.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index
Add this option to allow boards to override the default read-to-write
turnaround time for better performance.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |3 +++
arch/powerpc/include/asm/fsl_ddr_sdram.h |3 +++
2 files changed, 6 insertions
Enable buffer write for better performance. This platform uses a NOR flash chip
which supports write buffer programming. CFI driver can query the buffer size
and use it to program the flash for best performance.
Signed-off-by: York Sun york...@freescale.com
---
include/configs/corenet_ds.h
Move mac command to board/freescale/common/sys_eeprom.c.
Change the help message to be more helpful. Print argument format.
Fix MAX_NUM_PORTS to comply with v1 NXID format.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/sys_eeprom.c | 29 -
common
On Tue, 2011-04-05 at 16:52 -0500, Kim Phillips wrote:
On Tue, 5 Apr 2011 11:49:49 +0200
Andre Schwarz andre.schw...@matrix-vision.de wrote:
Cc'ing York Sun, who knows a little more about this stuff than I do.
I have made some mods to spd_sdram.c for various reason:
1.
use SPD
On Wed, 2011-04-06 at 10:42 +0200, Andre Schwarz wrote:
York,
I have made some mods to spd_sdram.c for various reason:
1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data
is written during in-circuit/boundary-scan testing.
On Wed, 2011-04-06 at 10:18 +0200, Andre Schwarz wrote:
Kim, York,
I have made some mods to spd_sdram.c for various reason:
1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data
is written during in-circuit/boundary-scan
On Thu, 2011-04-07 at 22:42 +0200, Schwarz,Andre wrote:
York,
Schwarz,Andre andre.schw...@matrix-vision.de hat am 6. April 2011
um 20:42 geschrieben:
York,
ok - will give it a try tomorrow.
hmm - having a look at the Makefile it looks like I need
On Fri, 2011-04-08 at 09:41 +0200, Andre Schwarz wrote:
I am sorry I totally ignored the subject with mpc83xx. I was thinking of
mpc85xx.
ok - no new code for 83xx then.
You are right the old code is in spd_sdram.c and it is still in use for
mpc83xx. Unless to adjust the code, there is no
On Fri, 2011-04-08 at 18:29 +0200, Andre Schwarz wrote:
York,
On Fri, 2011-04-08 at 09:41 +0200, Andre Schwarz wrote:
I am sorry I totally ignored the subject with mpc83xx. I was thinking of
mpc85xx.
ok - no new code for 83xx then.
You are right the old code is in spd_sdram.c and it is
) /* Write Recovery
Autopre */
Looks good to me.
Acked-by: York Sun york...@freescale.com
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Reword The DIMM max tCKmin is to The combined tCKmin is. It means the max
tCKmin across all DIMMs on the same controller.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git
On Mon, 2011-05-02 at 20:19 -0700, Tabi Timur-B04825 wrote:
On Mon, May 2, 2011 at 8:51 PM, York Sun york...@freescale.com wrote:
- printf(The DIMM max tCKmin is %d ps,
+ printf(The combined minimum tCKmin is %d ps,
doesn't support
Felix,
On Thu, 2011-05-05 at 16:17 +0300, Felix Radensky wrote:
Hi,
I'm working on a custom board based on P1011.
There are 2 board flavours, with either 128MB or 256MB of soldered
DDR2 SDRAM. Having u-boot image per board works fine, but I'd like
to have a single image and use
On Thu, 2011-05-05 at 10:04 -0500, Timur Tabi wrote:
Kumar Gala wrote:
That still needs some work, IMHO. I think you might need the word
which before doesn't. However, even with that, it's not clear
what's wrong. Where does the bad value of mclk_ps come from?
It happens
Reword The DIMM max tCKmin is ... to The DDR clock is faster than the slowest
DIMM(s) can support. Fixed interger type in printf as well.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|6 +++---
1 files changed, 3 insertions(+), 3
P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/p1010rdb/ddr.c |6 +++---
board/freescale
On Fri, 2011-09-16 at 14:15 -0500, Timur Tabi wrote:
York Sun wrote:
+Interactive DDR debugging
+===
+
+For DDR parameter tuning up and debugging, the interactive DDR debugging
can
+be activated by saving an environment variable ddr_interactive. The value
speed setting. If rank is unknown, it
has to panic.
Removed ODT overriding for P2020DS as it is not necessary.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c | 222 -
board/freescale/mpc8349emds/ddr.c | 80
From: Xie Xiaobo r63...@freescale.com
1.The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
to 4-bit and enable SPI signals.
2.Add eSPI controller and SPI-FLASH definition.
Signed-off-by: Xie Xiaobo
From: Tang Yuantian b29...@freescale.com
If CONFIG_LBA48 is not defined, the element lba48 of
struct sata_dev_desc is not avaible, and can't be used.
Signed-off-by: Tang Yuantian b29...@freescale.com
---
drivers/block/fsl_sata.c | 15 ++-
1 files changed, 10 insertions(+), 5
From: Xie Xiaobo r63...@freescale.com
MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum,
so that the SDHC write protected pin polarity does not
follow the SD card standard in MPC8536 Rev 1.0 silicon.
The MPC8536DS board invert the SDHC_WP pin as a workaround.
However, This silicon erratum has
From: Xie Xiaobo r63...@freescale.com
MPC8536DS offer booting from SDcard or SPI flash.
This patch defined that u-boot can save the environment variables
on SDcard or SPI flash when booting from the related device.
The Env parameter region and linux kernel region have overlap
in SPI-Flash, So
Wolfgang,
On Fri, 2011-10-14 at 23:32 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1313076710-12662-1-git-send-email-york...@freescale.com you
wrote:
Change the help message to be more helpful. Print argument format.
Fix MAX_NUM_PORTS to comply with v1 NXID format. Accept
Wolfgang,
On Thu, 2011-07-28 at 15:35 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1309457195-8475-1-git-send-email-york...@freescale.com you wrote:
Move mac command to board/freescale/common/sys_eeprom.c.
Change the help message to be more helpful. Print argument format.
Fix
(int board_type)
dram_size = fixed_sdram ();
#endif
- puts (DDR: );
+ debug (DDR: );
return dram_size;
}
Acked-by: York Sun york...@freescale.com
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http
On Mon, 2011-07-25 at 10:14 +0200, Wolfgang Denk wrote:
lc_common_dimm_params.c was too verbose and corrupted the boot
message display like this:
...
DRAM: Detected UDIMM M2U25664DS88C3G-6K
DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
...
Turn printf() into
On Thu, 2011-07-28 at 20:45 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1311875176.29459.14.camel@oslab-l1 you wrote:
- printf(Detected RDIMM %s\n,
+ debug(Detected RDIMM %s\n,
dimm_params[i
Kyle,
On Mon, 2011-03-14 at 16:35 -0500, Moffett, Kyle D wrote:
On Mar 14, 2011, at 16:22, York Sun wrote:
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
+ * Now divide by 5^12 and track the 32-bit remainder, then divide
+ * by 2*(2^12) using shifts (and updating the remainder
Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 19 ++-
arch/powerpc/include/asm/fsl_ddr_sdram.h |4
2 files changed, 14
Reduce the calculation error to 1ps.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/util.c | 26 +++---
1 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
b/arch/powerpc/cpu/mpc8xxx/ddr
The two slots on the same controller have different addresses.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch/powerpc/cpu/mpc8xxx
DDR2 has different ODT table and values. Adding table according to Samsung
application note.
Fix additive latency calculation to avoid interger underflow.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|3 +-
arch/powerpc/cpu/mpc8xxx/ddr
...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
Makefile |1 +
arch/powerpc/cpu/mpc83xx/Makefile| 20 +-
arch/powerpc/cpu/mpc83xx/ecc.c | 18 --
arch/powerpc/cpu/mpc83xx/law.c | 61
arch/powerpc/cpu
Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c.
The unified driver can initialize data using DDR controller. No need to
use DMA if just to initialze for ECC.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Kim Phillips kim.phill...@freescale.com
---
board
Change the help message to be more helpful. Print argument format.
Fix MAX_NUM_PORTS to comply with v1 NXID format.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/sys_eeprom.c |2 +-
common/cmd_mac.c| 29 +
2 files
On Wed, 2011-08-10 at 20:27 -0500, Tabi Timur-B04825 wrote:
York Sun wrote:
Change the help message to be more helpful. Print argument format.
Fix MAX_NUM_PORTS to comply with v1 NXID format.
Signed-off-by: York Sunyork...@freescale.com
Could you also fix the commands so that they take
Change the help message to be more helpful. Print argument format.
Fix MAX_NUM_PORTS to comply with v1 NXID format. Use decimal for port count.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/sys_eeprom.c |4 ++--
common/cmd_mac.c| 29
On Thu, 2011-08-11 at 09:55 -0500, Tabi Timur-B04825 wrote:
York Sun wrote:
- e.mac_count = simple_strtoul(argv[2], NULL, 16);
+ e.mac_count = simple_strtoul(argv[2], NULL, 10);
You forgot the MAC address index. There's another use of strtoul in the
code that needs
Change the help message to be more helpful. Print argument format.
Fix MAX_NUM_PORTS to comply with v1 NXID format. Accept hexadecimal and
decimal for port count and index.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/common/sys_eeprom.c |8
common/cmd_mac.c
Extend CAS write Latency (CWL) table to comply with DDR3 spec
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 18 --
1 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
b/arch
for
future use.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c | 103 +++---
1 files changed, 84 insertions(+), 19 deletions(-)
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index e3b3855..10ff4e7
DDR RCW varies at different speeds. It is common for all platform. Move it
out from corenet_ds.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/options.c | 15 +++
board/freescale/corenet_ds/ddr.c | 14 --
2 files changed, 15
Wolfgang,
On Thu, 2011-08-25 at 00:36 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1312923045-2612-5-git-send-email-york...@freescale.com you wrote:
Unified DDR driver is maintained for better performance, robustness and bug
fixes. Upgrading to use unified DDR driver for MPC83xx
On Thu, 2011-08-25 at 23:20 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1314305821.29220.21.camel@oslab-l1 you wrote:
WARNING: do not add new typedefs
#408: FILE: arch/powerpc/include/asm/immap_83xx.h:289:
+typedef struct ccsr_ddr {
Please fix.
I can fix
Wolfgang,
On Thu, 2011-08-25 at 23:30 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1314307500.29220.24.camel@oslab-l1 you wrote:
Fixing all existing reference to ccs_ddr is a lot of work, comparing
with defining it for 83xx. There are many other typedefs in the very
same
Wolfgang,
On Fri, 2011-08-26 at 00:31 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1314308192.29220.29.camel@oslab-l1 you wrote:
I am introducing it to this file as it is already being used somewhere
else. If you are trying to enforce this new policy, please start with
brand
On Fri, 2011-08-26 at 20:12 +0200, Wolfgang Denk wrote:
Dear York Sun,
In message 1314378058.20734.25.camel@oslab-l1 you wrote:
I am going to follow the style and not to add new typedefs. For the
existing typedef, I will keep using them. In this case, it is an
existing typedef, just
Check second DIMM slot in case the first one is empty.
Honor DQS enable option for SDRAM mode register.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 19 ++-
arch/powerpc/include/asm/fsl_ddr_sdram.h |4
2 files changed, 14
Reduce the calculation error to 1ps.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/util.c | 26 +++---
1 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
b/arch/powerpc/cpu/mpc8xxx/ddr
The two slots on the same controller have different addresses.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch/powerpc/cpu/mpc8xxx
DDR2 has different ODT table and values. Adding table according to Samsung
application note.
Fix additive latency calculation to avoid interger underflow.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|3 +-
arch/powerpc/cpu/mpc8xxx/ddr
...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
Makefile |1 +
arch/powerpc/cpu/mpc83xx/Makefile| 20 +-
arch/powerpc/cpu/mpc83xx/ecc.c | 18 --
arch/powerpc/cpu/mpc83xx/law.c | 61
arch/powerpc/cpu
Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c.
The unified driver can initialize data using DDR controller. No need to
use DMA if just to initialze for ECC.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Kim Phillips kim.phill...@freescale.com
---
board
Robert,
On Tue, 2011-09-06 at 13:34 -0400, Robert Sciuk wrote:
Has anyone had any experience with a P4080 target which has more than 1
sodimm slot on each controller? I'm having some difficulties accessing
memory on the higher order dimms, but the SPD data are correctly
enumerated by the FSL
Remove symbolic link generated by compiling. Fix makefile for out-of-tree
compiling error.
Signed-off-by: York Sun york...@freescale.com
---
Makefile |1 +
arch/powerpc/cpu/mpc83xx/Makefile |9 +++--
2 files changed, 4 insertions(+), 6 deletions(-)
diff
Looking good so far, what's the question? You can always override the
register values and try it since you got the interactive debug up.
York
On Fri, 2011-11-11 at 14:54 -0800, McClintock Matthew-B29882 wrote:
Adding York who might be able to help more...
-M
On Fri, Nov 11, 2011 at 4:18
Fix the bits for ngpixis to reset to alternative bank. Originally the mask
was 0xE0, which left it possible to reset to bank 3 if DIP switch is set to
boot from bank 1. Changing to 0xF0 gurantees to reset to bank 2.
Signed-off-by: York Sun york...@freescale.com
---
include/configs/P1022DS.h
Most of time U-boot doesn't get an exact clock number. For example, clock
900MHz may be detected as 899.99MHz. 800MHz could be 799.99MHz. Update the
table to align the desired clocks in the middle.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/p4080ds_ddr.c | 16
Beside displaying RDIMM or UDIMM, this patch adds display of the model numbers
embedded in SPD.
Signed-off-by: York Sun york...@freescale.com
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c| 11 +++
1 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu
When DDR data rate is higher than 1200MT/s or controller interleaving is
enabled, additional cycle for write-to-read turnaround is needed to satisfy
dynamic ODT timing.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |3 +++
arch/powerpc/cpu/mpc8xxx
[Patch v2 1/2] Adding more SPD registers
[Patch v2 2/2] powerpc/8xxx: Adding interactive DDR debugging
This is v2 patch to add interactive DDR debugging after cleaning up according
to feedback. Please review.
York
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Adding byte 32 and 33. Byte 33 is useful for displaying device type.
Signed-off-by: York Sun york...@freescale.com
---
include/ddr_spd.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/include/ddr_spd.h b/include/ddr_spd.h
index 710e528..d632a1e 100644
--- a/include
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 28
1
This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based
on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c |8
1 files changed, 4 insertions(+), 4 deletions
On Wed, 2011-03-02 at 13:31 -0600, Timur Tabi wrote:
York Sun wrote:
+ switch (wrrec_mclk) { /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
+ case 9:
+ wrrec_mclk = 10;
+ break;
+ case 11:
+ wrrec_mclk = 12;
+ break;
+ case 13
This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based
on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c |8
1 files changed, 4 insertions(+), 4 deletions
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 28
1
On Wed, 2011-03-02 at 13:46 -0600, Timur Tabi wrote:
York Sun wrote:
if (wrrec_mclk 1)
wrrec_mclk++;
Only 9, 11, 13, 15 need to round up.
What are all the possible values for wrrec_mclk?
There is no limitation on register timing_cfg_1[wrrec_mclk]. It can be
any value
This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based
on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c |8
1 files changed, 4 insertions(+), 4 deletions
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++--
1 files
The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 20 ++--
1 files
This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based
on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
Signed-off-by: York Sun york...@freescale.com
---
board/freescale/corenet_ds/ddr.c |8
1 files changed, 4 insertions(+), 4 deletions
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
The current FreeScale MPC-8xxx DDR SPD interpreter is using full 64-bit
integer divide operations to convert between nanoseconds and DDR clock
cycles given arbitrary DDR clock frequencies.
Since all of the inputs to this are 32-bit
On Thu, 2011-03-10 at 16:54 -0600, Peter Tyser wrote:
From: John Schmoller jschmol...@xes-inc.com
The JEDEC DDR3 specification states that the above parameters should
be set to a minimum of 4 clocks. The SPD defines the values in
nanoseconds, and depending on the clock frequency the value
On Mon, 2011-03-14 at 12:38 -0400, Kyle Moffett wrote:
The numeric constants in the switch statements are replaced by #defines
added to the common ddr_spd.h header. This dramatically improves the
readability of the switch statments.
In addition, a few of the longer lines were cleaned up,
(-)
Acked-by: York Sun york...@freescale.com
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Kyle,
On Mon, 2011-03-14 at 14:04 -0500, Moffett, Kyle D wrote:
On 64-bit this change is basically a no-op, because do_div() is implemented
as a literal 64-bit divide operation and the instruction scheduling works out
almost the same.
On 32-bit PowerPC a fully accurate 64/64 divide
On Wed, 2011-02-23 at 11:35 -0500, Kyle Moffett wrote:
+ * Now divide by 5^12 and track the 32-bit remainder, then divide
+ * by 2*(2^12) using shifts (and updating the remainder).
+ */
+ clks_rem = do_div(clks, UL_5pow12);
+ clks_rem = 13;
Shouldn't this be clks_rem =
Cc: Kumar Gala kumar.g...@freescale.com
Cc: Wolfgang Denk w...@denx.de
Cc: Kim Phillips kim.phill...@freescale.com
---
Acked-by: York Sun york...@freescale.com
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Tom,
The following changes since commit e222b1f36fedb0363dbc21e0add7dc3848bae553:
powerpc/mpc85xx:Increase binary size for P, B T series boards. (2014-01-21
14:06:30 -0800)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to fetch changes up to
On 01/21/2014 09:34 AM, York Sun wrote:
On 01/21/2014 09:29 AM, Scott Wood wrote:
On Tue, 2014-01-21 at 10:14 +0100, Wolfgang Denk wrote:
Dear York,
In message f1d691e4-180a-4a2d-be07-812547d46...@freescale.com you wrote:
On second thought, I also think we should avoid solutions where
On 01/25/2014 07:46 AM, Timur Tabi wrote:
On Fri, Jan 24, 2014 at 7:45 AM, Wolfgang Denk w...@denx.de wrote:
For the test
part, it is probably much easier to add a customized memory test (or
fix just the existing memory test such that it can be built for a 64
bit mode) and use this, then
On 01/24/2014 06:19 AM, Alexander Graf wrote:
Hrm, let me try that.
Looks you got plenty feedback from Scott. I am going to mark this set as change
requested so they will drop off from my to-do list. Please submit a v2 when
they are ready (all three patches together) with change log.
York
On 11/01/2013 12:47 AM, Zhang Haijun wrote:
:-)
Thanks.
δΊ 2013/11/1 15:45, Pantelis Antoniou ει:
Hi Zhang,
I'll take a look at it over the weekend.
Regards
-- Pantelis
Where are we on this patch?
York
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On 01/20/2014 10:15 PM, Shengzhou Liu wrote:
--- a/boards.cfg
+++ b/boards.cfg
@@ -973,11 +973,16 @@ Active powerpc mpc85xx-
freescale t4qds
Active powerpc mpc85xx- freescale t1040qds
T1040QDS
On 01/27/2014 10:44 PM, Priyanka Jain wrote:
This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both
-T1040RDB
-T1042RDB_PI
T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
-2 RGMIIS on DTSEC4, DTSEC5
-1 SGMII on
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
From: Rainer Boschung rainer.bosch...@keymile.com
-uses common deblocking algorithm from ../common/common.c
I don't see any algorithm in the common.c file.
-supports deblocking of of I2C-bus1 by means of QRIO GPIO
- SCL1 = GPIO_A16
-
On 01/30/2014 01:17 AM, Boschung, Rainer wrote:
On 01/30/2014 08:32 AM, Valentin Longchamp wrote:
On 01/30/2014 03:30 AM, York Sun wrote:
On 01/27/2014 02:49 AM, Valentin Longchamp wrote:
From: Rainer Boschung rainer.bosch...@keymile.com
-uses common deblocking algorithm from ../common
On 01/31/2014 04:46 AM, Valentin Longchamp wrote:
From: Rainer Boschung rainer.bosch...@keymile.com
This patch adds support for using some GPIOs that are connected to the
I2C bus to force the bus lines state and perform some bus deblocking
sequences.
The KM common deblocking algorithm
On 01/31/2014 03:16 AM, Alexander Graf wrote:
For KVM we have a special PV machine type called ppce500. This machine
is inspired by the MPC8544DS board, but implements a lot less features
than that one.
It also provides more PCI slots and is supposed to be enumerated by
device tree only.
On 01/31/2014 03:16 AM, Alexander Graf wrote:
With the qemu-ppce500 machine type we can run the same board with
either an e500v2 or an e500mc core plugged in.
This means that the IVOR setup can't be based on compile time decisions,
so instead we have to do a runtime check which CPU
Tom,
The following changes since commit 07e2822d158940a0e8ba45b6ab0344ffa1011a07:
board: nios2: Check if flash is configured before calling
early_flash_cmd_reset() (2014-01-29 16:44:18 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-mpc85xx.git master
for you to
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