On 04/25/2014 04:38 PM, Ebony Zhu wrote:
According to AN3638, CRC of NXID v1 is at the end of the
256-byte I2C memory. The wrong CRC32 offset prevents Uboot
from reading system information from EEPROM. No NXID v0 is
being used on Freescale boards.
Signed-off-by: Ebony Zhu
On 05/06/2014 07:50 PM, Chunhe Lan wrote:
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Chunhe Lan
On 05/06/2014 07:56 PM, Chunhe Lan wrote:
T4160RDB shares the same platform as T4240RDB. T4160 is
a low power version of T4240, with the eight e6500 cores,
two DDR3 controllers, and same peripheral bus interfaces.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
Applied to
On 05/07/2014 02:13 AM, Shaveta Leekha wrote:
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.
Signed-off-by: Shaveta Leekha shav...@freescale.com
Signed-off-by: Sandeep Singh
On 05/08/2014 04:35 AM, Nikhil Badola wrote:
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
Signed-off-by: Ramneek Mehresh
On 05/13/2014 03:06 AM, Ramneek Mehresh wrote:
Define number of USB controllers used on P1020RDB-PD platform.
This platform has P1020 SoC which has two USB controllers, but
only first one is used on the platform
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applied to
On 05/13/2014 11:15 PM, Aneesh Bansal wrote:
In case of secure boot from NAND, CSPR and FTIM settings are
same as non-secure NAND boot. CSPR0 is configured as NAND and
CSPR1 is configured as NOR.
Signed-off-by: Aneesh Bansal aneesh.ban...@freescale.com
---
Applied to
On 05/15/2014 04:13 AM, Prabhakar Kushwaha wrote:
In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub.
The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to
On 05/14/2014 05:33 PM, Kim Phillips wrote:
AFAICT, c=ffe does nothing and was a typo from the original commit
d17123696c6180ac8b74fbd318bf14652623e982 powerpc/p4080: Add support
for the P4080DS board and just kept on getting duplicated
in subsequently added board config files.
On 05/14/2014 11:30 PM, Liu Gang wrote:
The new 768KB u-boot image size requires changes for
SRIO/PCIE boot. These addresses need to be updated to
appropriate locations.
The updated addresses are used to configure the SRIO/PCIE
inbound windows for the boot, and they must be aligned
with
, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun york...@freescale.com
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/include/asm/config_mpc85xx.h | 18 ++
drivers/ddr/fsl/ctrl_regs.c |9 +
3
, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v2: Remove warning if workaround is not enabled.
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc/include/asm/config_mpc85xx.h | 18
Will update.
York
Original Message
From: Albert ARIBAUD
Sent: Sun, 25/05/2014 06:01
To: Sun York-R58495
CC: u-boot@lists.denx.de
Subject: Re: [Patch v2 3/5] ARMv8/ls2100a_emu: Add LS2100A emulator board
support
Hi York,
On Wed, 19 Mar 2014 14:02:23 -0700, York Sun york
On 02/04/2014 06:28 PM, Masahiro Yamada wrote:
Useful rules in scripts/Makefile.lib allows us to easily
generate a device tree blob and wrap it in assembly code.
We do not need to parse a linker script to get output format and arch.
This commit deletes ./u-boot.dtb since it is a copy of
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log:
v3: No change. The blank line mentioned in review is in the other patch.
image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
Change log:
v3: Add error detection and update device tree
LS2100A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Signed-off-by: York Sun york
on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu
On 05/29/2014 06:19 AM, Rob Herring wrote:
On Wed, May 28, 2014 at 6:46 PM, York Sun york...@freescale.com wrote:
snip
+static void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+ u8 memory_type)
+{
+ u64 value;
+
+ value = section
LS2100A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Signed-off-by: York Sun york
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log
v4: no change
v3: no change
arch/arm/include/asm/io.h |8
1
Make MMU functions reusable. Platform code can setup its own MMU tables.
Also fix a typo of TCR_EL3_IPS_BITS in cache_v8.c.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log:
v4: new patch, splitted from v3 2/4
Revise set_pgtable_section
on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu
image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
Change log
v4: no change
v3: Add error detection and update device
On 05/29/2014 10:37 AM, Rob Herring wrote:
On Thu, May 29, 2014 at 10:19 AM, York Sun york...@freescale.com wrote:
On 05/29/2014 06:19 AM, Rob Herring wrote:
On Wed, May 28, 2014 at 6:46 PM, York Sun york...@freescale.com wrote:
snip
+static void set_pgtable_section(u64 *page_table, u64
On 06/02/2014 04:34 AM, Mark Rutland wrote:
On Thu, May 29, 2014 at 09:49:05PM +0100, York Sun wrote:
Make MMU functions reusable. Platform code can setup its own MMU tables.
What exactly does platform code need to setup its own tables for?
The general ARMv8 MMU table is not detail enough
On Jun 3, 2014, at 8:52 PM, Stefan Roese wrote:
Hi Jeroen,
(added York to cc as he introduced CONFIG_SYS_GENERIC_GLOBAL_DATA with patch
2a1680e3 [common/board_f: Initialized global data for generic board])
On 03.06.2014 22:52, Jeroen Hofstee wrote:
Hello Wolfgang / Stefan.
On za,
On 06/02/2014 11:01 AM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 05:06:13PM +0100, York Sun wrote:
On 06/02/2014 04:34 AM, Mark Rutland wrote:
On Thu, May 29, 2014 at 09:49:05PM +0100, York Sun wrote:
Make MMU functions reusable. Platform code can setup its own MMU tables.
What exactly
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log
v5: no change
v4: no change
v3: no change
arch/arm/include/asm/io.h |
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log
v5: Drop the addition of inline function set_pgtable_section() from v4
It is only used twice and causes confusion.
v4
image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
Change log
v5: Fix a typo in commit message supoort
Fix
on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu
LS2100A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Signed-off-by: York Sun york
On 06/05/2014 03:09 AM, Mark Rutland wrote:
On Wed, Jun 04, 2014 at 05:27:30PM +0100, York Sun wrote:
On 06/02/2014 11:01 AM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 05:06:13PM +0100, York Sun wrote:
On 06/02/2014 04:34 AM, Mark Rutland wrote:
On Thu, May 29, 2014 at 09:49:05PM +0100
On 06/05/2014 10:41 AM, Mark Rutland wrote:
On Thu, Jun 05, 2014 at 04:07:17PM +0100, York Sun wrote:
On 06/05/2014 03:09 AM, Mark Rutland wrote:
On Wed, Jun 04, 2014 at 05:27:30PM +0100, York Sun wrote:
On 06/02/2014 11:01 AM, Mark Rutland wrote:
On Mon, Jun 02, 2014 at 05:06:13PM +0100
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log
v6: Modified from v4. Add dsb sy before setting MMU registers and add isb
after.
v5: Drop the addition of inline function
on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log
v6: no change
v5: no change
v4: no change
v3: no change
LS2100A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Signed-off-by: York Sun york
image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
Change log
v6: no change
v5: Fix a typo in commit message supoort
The offset of module information is at 128, different from DDR3.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/interactive.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c
index cfe1e1f
, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v3: Fix the error of closing curly bracket caused by v2.
v2: Remove warning if workaround is not enabled.
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +++
arch/powerpc
the workaround for erratum A-007186
Shengzhou Liu (3):
board/t208x: update t2080qds/t2080rdb for errata A-007186
board/t2080qds: some update for ddr
powerpc/t2080: add serdes2 protocol 0x27
York Sun (2):
powerpc/mpc85xx: Add workaround for DDR erratum A004508
driver/ddr
On 06/06/2014 05:33 AM, Mark Rutland wrote:
[...]
What you need to do to replace the active set of tables (assuming that
the new mapping has the instruction stream mapped in an identical way)
is:
- Write the tables.
- DSB to make them visible to the MMU.
- Write to the appropriate
On 06/06/2014 06:34 AM, Rob Herring wrote:
On Thu, Jun 5, 2014 at 1:34 PM, York Sun york...@freescale.com wrote:
On 06/05/2014 10:41 AM, Mark Rutland wrote:
On Thu, Jun 05, 2014 at 04:07:17PM +0100, York Sun wrote:
On 06/05/2014 03:09 AM, Mark Rutland wrote:
[...]
No objection here
On 06/06/2014 10:32 AM, Mark Rutland wrote:
On Fri, Jun 06, 2014 at 03:54:49PM +0100, York Sun wrote:
On 06/06/2014 05:33 AM, Mark Rutland wrote:
[...]
What you need to do to replace the active set of tables (assuming that
the new mapping has the instruction stream mapped in an identical way
On 06/06/2014 10:32 AM, Mark Rutland wrote:
How is TCR_EL2.SH0 (or TCR_EL1.SH*) configured?
You'll only need to flush the cache if they're configured non shareable.
It is configured as non shareable.
Is there any reason not to configure them as inner shareable? That way
the MMU will look
On 06/06/2014 01:17 PM, York Sun wrote:
On 06/06/2014 10:32 AM, Mark Rutland wrote:
How is TCR_EL2.SH0 (or TCR_EL1.SH*) configured?
You'll only need to flush the cache if they're configured non shareable.
It is configured as non shareable.
Is there any reason not to configure them as inner
On 06/06/2014 03:14 PM, Wolfgang Denk wrote:
Dear Lijun Pan,
In message 1402085638-12144-1-git-send-email-lijun@freescale.com you
wrote:
Since P1023RDS is no longer supported/manufactured by Freescale,
we clean up P1023RDS related code.
Since P1023RDB is still supported by Freescale,
On 06/10/2014 02:15 AM, Mark Rutland wrote:
Hi,
Apologies for the delay in replying.
On Fri, Jun 06, 2014 at 11:14:23PM +0100, York Sun wrote:
On 06/06/2014 01:17 PM, York Sun wrote:
On 06/06/2014 10:32 AM, Mark Rutland wrote:
How is TCR_EL2.SH0 (or TCR_EL1.SH*) configured?
You'll only
On 06/11/2014 07:05 AM, feng...@phytium.com.cn wrote:
Dear York,
My mailing list disabled a few days. Maybe I missed something important.
/*
* Performs a clean invalidation of the entire data cache at all levels
*/
void flush_dcache_all(void)
{
__asm_flush_dcache_all();
+
On 05/15/2014 04:24 AM, Shengzhou Liu wrote:
As errata A-007186, we need to use the alternate serdes
protocol instead of those impacted protocols.
- add support for serdes protocols: 0x1b, 0x50, 0x5e,
0x64, 0x6a, 0xd2, 0x67, 0x70.
- update t2080_rcw.cfg to adapt to new rcw_66_15 for
On 05/15/2014 07:52 PM, shh@gmail.com wrote:
From: Shaohui Xie shaohui@freescale.com
A-007186: SerDes PLL is calibrated at reset. It is possible for jitter to
increase and cause the PLL to unlock when the temperature delta from the
time the PLL is calibrated exceeds +56C/-66C when
On 05/19/2014 10:34 PM, Chunhe Lan wrote:
A-007186: SerDes PLL is calibrated at reset. It is possible
for jitter to increase and cause the PLL to unlock when the
temperature delta from the time the PLL is calibrated exceeds
+56C/-66C when using X VDD of 1.35 V (or +70C/-80C when using
XnVDD
On 05/19/2014 09:08 PM, Shengzhou Liu wrote:
- add support for 2nd DIMM slot.
- make it work with DIMM which is less than 2GB.
Verified with two 2GB UDIMM MT9JSF25672AZ-2G1K1 in two DIMM slots.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
Applied to u-boot-mpc85xx. Sorry
On 05/20/2014 07:25 PM, Hou Zhiqiang wrote:
Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
Applied to u-boot-mpc85xx. Sorry for the late notice.
York
___
U-Boot mailing list
On 05/22/2014 02:24 AM, Shengzhou Liu wrote:
Add a new serdes2 protocol 0x27.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
Applied to u-boot-mpc85xx. Sorry for the late notice.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if tdm is defined in hwconfig.
Also disable POST tests and add LIODN for TDM
Signed-off-by: Sandeep Singh sand...@freescale.com
Cc: York Sun
On 05/28/2014 01:48 AM, Shaveta Leekha wrote:
SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.
This workaround overwrite the SerDes registers with new values,
to
On 05/30/2014 11:38 AM, Poonam Aggrwal wrote:
Crossbars and IDT were not getting configured for Serdes2 protocol
0x9d for B4420.
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Shaveta Leekha shav...@freescale.com
---
Applied to u-boot-mpc85xx. Sorry for the late
On 05/20/2014 07:25 PM, Hou Zhiqiang wrote:
Replace 80 mircoseconds delay with polling flag ESPI_EV_TXE.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
---
Applied to u-boot-mpc85xx. Sorry for the late notice.
York
___
U-Boot mailing list
On 06/10/2014 02:15 AM, Mark Rutland wrote:
Hi,
Apologies for the delay in replying.
On Fri, Jun 06, 2014 at 11:14:23PM +0100, York Sun wrote:
On 06/06/2014 01:17 PM, York Sun wrote:
On 06/06/2014 10:32 AM, Mark Rutland wrote:
How is TCR_EL2.SH0 (or TCR_EL1.SH*) configured?
You'll only
the datasheet
to design a correct solution, but at least let's change it to access
only the existing registers.
Signed-off-by: Vasili Galka vvv...@gmail.com
Cc: York Sun york...@freescale.com
---
board/freescale/t4qds/t4240qds.c |2 +-
1 files changed, 1 insertions(+), 1 deletions
On 06/17/2014 08:41 AM, Scott Wood wrote:
On Tue, 2014-06-17 at 17:36 +0900, Masahiro Yamada wrote:
Hello Scott,
On Mon, 16 Jun 2014 16:46:13 -0500
Scott Wood scottw...@freescale.com wrote:
FWIW, all p1023rds support can probably be removed. Very few boards
were ever sold, and support was
Previously the driver was only tested on Power SoCs. Minor fix is needed
for ARM SoCs.
Signed-off-by: York Sun york...@freescale.com
---
arch/arm/include/asm/arch-fsl-lsch3/config.h |4
drivers/ddr/fsl/fsl_ddr_gen4.c |9 +
2 files changed, 13 insertions
On 06/18/2014 07:09 AM, feng...@phytium.com.cn wrote:
hi York,
On 06/10/2014 02:15 AM, Mark Rutland wrote:
Hi,
Apologies for the delay in replying.
On Fri, Jun 06, 2014 at 11:14:23PM +0100, York Sun wrote:
On 06/06/2014 01:17 PM, York Sun wrote:
On 06/06/2014 10:32 AM, Mark Rutland
On 06/18/2014 07:57 AM, Jon Loeliger wrote:
On Tue, Jun 17, 2014 at 5:07 PM, York Sun york...@freescale.com wrote:
Previously the driver was only tested on Power SoCs. Minor fix is needed
for ARM SoCs.
Signed-off-by: York Sun york...@freescale.com
Hi York!
--- a/drivers/ddr/fsl
, 2014 at 08:23:09PM +0100, York Sun wrote:
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance
on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log
v7: no change
v6: Modified from v4. Add dsb sy before setting MMU registers and add isb
after.
v5: Drop the addition
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
Change log
v7: no change
v6: no change
LS2100A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Management Complex (MC) is enabled
Signed-off-by: York Sun york
image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
Change log
v7: no change
v6: no change
v5: Fix a typo in commit
On 06/18/2014 07:57 AM, Jon Loeliger wrote:
On Tue, Jun 17, 2014 at 5:07 PM, York Sun york...@freescale.com wrote:
Previously the driver was only tested on Power SoCs. Minor fix is needed
for ARM SoCs.
Signed-off-by: York Sun york...@freescale.com
Hi York!
--- a/drivers/ddr/fsl
.
For example, do a 'git grep wmb' in the U-Boot repo.
Also ponder arch/arm/include/asm/io.h too.
HTH,
jdl
On Thu, Jun 19, 2014 at 12:47 PM, York Sun york...@freescale.com wrote:
On 06/18/2014 07:57 AM, Jon Loeliger wrote:
On Tue, Jun 17, 2014 at 5:07 PM, York Sun york...@freescale.com wrote
On 6/18/14 12:05 PM, York Sun york...@freescale.com wrote:
LS2100A is an ARMv8 implementation. This adds board support for emulator
and simulator:
Two DDR controllers
UART2 is used as the console
IFC timing is tightened for speedy booting
Support DDR3 and DDR4 as separated targets
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log
v8: no change
v7: no change
v6: Modified from v4. Add dsb sy before setting MMU registers and add isb
after.
v5: Drop
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log
v8: no change
v7: no change
v6: no change
v5: no change
v4: no change
image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
v8: no change
v7: no change
v6: no change
v5: Fix a typo
on GICv3 arch)
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Arnab Basu arnab.b...@freescale.com
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
---
v8: Rename ls2100a to ls2085a according to latest SoC name
on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu
On 06/20/2014 01:33 PM, Jeroen Hofstee wrote:
Hi York,
On 20-06-14 20:46, York Sun wrote:
From: J. German Rivera german.riv...@freescale.com
Adding support to load and start the Layerscape Management Complex (MC)
firmware. First, the MC GCR register is set to 0 to reset all cores. MC
To: Jeroen Hofstee; Rivera Jose-B46482
Cc: albert.u.b...@aribaud.net; Kanetkar Shruti-B44454; u-boot@lists.denx.de
Subject: Re: [U-Boot] [Patch v8 4/5] armv8/fsl-lsch3: Add support to load and
start MC Firmware
On 06/20/2014 01:33 PM, Jeroen Hofstee wrote:
Hi York,
On 20-06-14 20:46, York
Make MMU function reusable. Platform code can setup its own MMU tables.
Signed-off-by: York Sun york...@freescale.com
CC: David Feng feng...@phytium.com.cn
---
Change log
v9: no change
v8: no change
v7: no change
v6: Modified from v4. Add dsb sy before setting MMU registers and add isb
after
on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Varun Sethi varun.se...@freescale.com
Signed-off-by: Arnab Basu
on GICv3 arch)
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Arnab Basu arnab.b...@freescale.com
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: Bhupesh Sharma bhupesh.sha...@freescale.com
---
Change log
v9: no change
v8: Rename ls2100a to ls2085a
From: J. German Rivera german.riv...@freescale.com
This is needed for accessing peripherals with 64-bit MMIO registers,
from ARMv8 processors.
Signed-off-by: J. German Rivera german.riv...@freescale.com
---
Change log
v9: no change
v8: no change
v7: no change
v6: no change
v5: no change
image uses FIT format.
Signed-off-by: J. German Rivera german.riv...@freescale.com
Signed-off-by: York Sun york...@freescale.com
Signed-off-by: Lijun Pan lijun@freescale.com
Signed-off-by: Shruti Kanetkar shr...@freescale.com
---
v9: drop checking for uname == NULL in mc.c
v8: no change
v7
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v2: use mb() and isb() instead of #ifdef
arch/arm/include/asm/arch-fsl-lsch3/config.h |4
arch/arm/include/asm/io.h
some user errors.
Signed-off-by: York Sun york...@freescale.com
---
board/exmeritus/hww1u1a/hww1u1a.c | 12 +---
board/freescale/b4860qds/b4860qds.c | 12 +---
board/freescale/bsc9132qds/bsc9132qds.c | 12 +---
board/freescale/c29xpcie
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.
Signed-off-by: York Sun york...@freescale.com
---
drivers/ddr/fsl/ctrl_regs.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr
On 11/14/2013 03:32 AM, Shengzhou Liu wrote:
The T2080QDS is a high-performance computing evaluation, development and
test platform supporting the T2080 QorIQ Power Architecture processor.
T2080QDS feature overview
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up
Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v4: Rebase to latest master
v3: no change
v2: Replace macro CONFIG_SYS_FSL_DDR_ARM_GEN3 with CONFIG_SYS_FSL_DDRC_ARM_GEN3
Updated
. It was a misunderstanding in commit c360ceac.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v4: rebase to latest master
v3: no change
v2: no change since v1
drivers/ddr/fsl/ctrl_regs.c | 20
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/drivers
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v4: rebase to latset master
v3: no change
v2: no change since v1
drivers/ddr/fsl/main.c |6 +++---
1
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v4: Rebase to latest master
v3: Split again, as review feedback requested
v2: Merge to Driver/DDR: Moving Freescale DDR driver
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.
Signed-off-by: York Sun york...@freescale.com
---
Change log
v4: rebase to latest master
v3: no change
v2: Move to driver
On 11/07/2013 06:46 PM, shh@gmail.com wrote:
From: Shaohui Xie shaohui@freescale.com
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Applied to u-boot-mpc85xx/master. Thanks.
York
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On 11/14/2013 03:00 AM, shh@gmail.com wrote:
From: Shaohui Xie shaohui@freescale.com
fixed-link is used in kernel for PHY-less MAC, so introduce this
structure that U-boot can use it to fixup dtb dynamically.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
Applied to
On 10/16/2013 07:47 PM, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
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