Hi Kevin,
Akshay Saraswat aksha...@samsung.com writes:
[...]
I don't think it hurts to have a generic function with ARM errata
workaround implementation. Whoever wish to use it can call it in their
boot path. And it's not even getting executed right now for any SoC
other than Exynos542x, so
Hi Nishanth,
On 17:13-20150224, Nishanth Menon wrote:
On 13:27-20150220, Akshay Saraswat wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache
On 13:27-20150220, Akshay Saraswat wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second
in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Akshay Saraswat aksha...@samsung.com
the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v3:
- No change.
Changes since v2:
- No change.
Changes since v1
instructions.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v3:
- No change.
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
arch
that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v3:
- No change
of few macros for better understanding in patch 2.
- Added MPIDR bit assignment info comment in power_down_core in patch 2.
- Changed to SPDX header in sec_boot.S in patch 5.
- Fixed compilation error for snow build in patch 11.
Akshay Saraswat (9):
Exynos542x: Config: Add
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v3:
- No change.
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
- Removed unnecessary
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v3:
- Included armv7.h in lowlevel_init.c.
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed
a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes
the logic that uses that bit retains the previous
value.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v3:
- Added errata number in comment
to switching.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v3:
- Rebased.
Changes since v2:
- Replaced #ifndef
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
- Removed unnecessary CONFIGS.
include/configs/exynos5420
that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- No change
.
- Fixed compilation error for snow build in patch 11.
Akshay Saraswat (10):
Exynos542x: Config: Add various configs
Exynos542x: CPU: Power down all secondary cores
Exynos542x: Add workaround for ARM errata 798870
Exynos542x: Add workaround for ARM errata 799270
Exynos542x: Add workaround
the logic that uses that bit retains the previous
value.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
- Changed to SPDX header in sec_boot.S.
arch/arm/cpu/armv7/exynos
a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes
instructions.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed
in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Akshay Saraswat aksha...@samsung.com
1. Renaming set_l2cache to configure_l2actlr in order to avoid
misleading comprehensions. Apparently this name suggests
that L2 cache is being set or initialized which is incorrect
as per the code in this function.
2. Cleaning missed mrc for L2 control register.
Signed-off-by: Akshay
to switching.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- Replaced #ifndef with if(proid_is_soc()) check.
Changes since v1
the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v2:
- No change.
Changes since v1:
- Added Reviewed-by Tested
secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- No change.
Changes since v1:
- Removed unnecessary macros.
- Changed names of few macros for better understanding
Hello,
On Wed, 18 Feb 2015 15:16:27 +0530
Akshay Saraswat aksha...@samsung.com wrote:
This patch adds workaround for ARM errata 798870 which says
If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request
Hi,
Hi Akshay,
On 02/03/2015 05:27 PM, Akshay Saraswat wrote:
Cleaning up soc_get_periph_rate to make the logic easy to
comprehend.
Could you give more detailed description?
We did just a cleanup here by removing I2C sepecific calculations
because we can now have a generic div and pre-div
specific exceptions.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v5:
- Elaborated Commit message and fixed a nit.
Changes since v4:
- New patch.
arch/arm/cpu/armv7/exynos/clock.c | 74 ++-
1 file changed, 35 insertions
because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes since v5:
- No Change.
Changes since v4:
- Added Reviewed-by.
Changes since v3:
- Merged patches
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 3. It also reads prediv and does division only for
SDMMC0 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v5
to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v5:
- No Change.
Changes since v4:
- No Change.
Changes
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes since v5:
- No Change.
Changes since v4:
- Added Reviewed-by.
Changes since v3:
- Added a case for SPLL in exynos542x_get_periph_rate.
- Changed EXYNOS542x - EXYNOS542X
: Added checks for negative values in soc_get_periph_rate.
Changes since v1:
- Added 2 new patches.
Akshay Saraswat (7):
Exynos5: Fix compiler warnings due to clock_get_periph_rate
Exynos542x: Move exynos5420_get_pll_clk up and rename
Exynos542x: Add and enable get_periph_rate support
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay
that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- Removed
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v1:
- Added Reviewed-by Tested-by.
- Removed unnecessary CONFIGS.
include/configs/exynos5420-common.h | 16
1 file changed
a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes
the logic that uses that bit retains the previous
value.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v1:
- Added Reviewed-by Tested
.
- Added MPIDR bit assignment info comment in power_down_core in patch 2.
- Changed to SPDX header in sec_boot.S in patch 5.
- Fixed compilation error for snow build in patch 11.
Akshay Saraswat (10):
Exynos542x: Config: Add various configs
Exynos542x: CPU: Power down
:
- Added 2 new patches.
Akshay Saraswat (7):
Exynos5: Fix compiler warnings due to clock_get_periph_rate
Exynos542x: Move exynos5420_get_pll_clk up and rename
Exynos542x: Add and enable get_periph_rate support
Exynos5: Fix exynos5_get_periph_rate calculations
Exynos5: Use
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes since v4:
- Added Reviewed-by.
Changes since v3:
- Added a case for SPLL in exynos542x_get_periph_rate.
- Changed EXYNOS542x - EXYNOS542X.
Changes since v2:
- Fixed enum
to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v4:
- No Change.
Changes since v3:
- Added Reviewed
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay
in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Akshay Saraswat aksha...@samsung.com
1. Renaming set_l2cache to configure_l2actlr in order to avoid
misleading comprehensions. Apparently this name suggests
that L2 cache is being set or initialized which is incorrect
as per the code in this function.
2. Cleaning missed mrc for L2 control register.
Signed-off-by: Akshay
to switching.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos
-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v1:
- Added Reviewed-by Tested-by.
- Changed to SPDX header in sec_boot.S.
arch/arm/cpu/armv7/exynos/Makefile| 2 +
arch/arm/cpu
instructions.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
arch/arm/include/asm/arch-exynos
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed
the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v1:
- Added Reviewed-by Tested-by.
arch/arm/cpu/armv7/exynos
because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes since v4:
- Added Reviewed-by.
Changes since v3:
- Merged patches 5 and 6 of version 3 to fix build errors
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 3. It also reads prediv and does division only for
SDMMC0 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Cleaning up soc_get_periph_rate to make the logic easy to
comprehend.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v4:
- New patch.
arch/arm/cpu/armv7/exynos/clock.c | 76 +--
1 file changed, 33 insertions(+), 43 deletions
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v4
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 3. It also reads prediv and does division only for
SDMMC0 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v3:
- Added a case for SPLL in exynos542x_get_periph_rate.
- Changed EXYNOS542x - EXYNOS542X.
Changes since v2:
- Fixed enum and exynos542x_get_periph_rate switch.
- Added checks for negative values
to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Reviewed-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
Changes since v3:
- Added Reviewed-by Tested-by.
Changes since v2
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay
.
- Patch-3: Added checks for negative values in soc_get_periph_rate.
- Patch-4: Added checks for negative values in soc_get_periph_rate.
Changes since v1:
- Added 2 new patches.
Akshay Saraswat (6):
Exynos5: Fix compiler warnings due to clock_get_periph_rate
Exynos542x
We have assumed and kept mask bits for divider and pre-divider
as 0xf and 0xff, respectively. But these mask bits change from
one peripheral to another, and hence, need to be specified in
accordance with the peripherals.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v3
because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v3:
- Merged patches 5 and 6 of version 3 to fix build errors.
Changes since v2:
- No change.
Changes since v1:
- Separated
2015 at 21:46, Joonyoung Shim jy0922.s...@samsung.com
wrote:
Hi Simon,
On 01/28/2015 01:09 PM, Simon Glass wrote:
Hi,
On 15 January 2015 at 23:09, Joonyoung Shim jy0922.s...@samsung.com
wrote:
Hi,
On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
We planned to fetch peripheral rate through
Hi Kevin,
Akshay Saraswat aksha...@samsung.com writes:
This patch series introduces changes for booting secondary CPUs
on Exynos5420 and Exynos5800.
Thanks for this series. I think this should help get the odroid-xu3
behave better with the mainline linux kernel (assuming I can get
for negative values in soc_get_periph_rate.
- Patch-4: Added checks for negative values in soc_get_periph_rate.
Changes since v1:
- Added 2 new patches.
Akshay Saraswat (6):
Exynos5: Fix compiler warnings due to clock_get_periph_rate
Exynos542x: Move exynos5420_get_pll_clk up
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 3. It also reads prediv and does division only for
SDMMC0 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- Changed exynos5420 - exynos542x in line 33.
Changes since v1:
- New patch.
arch/arm/cpu/armv7/exynos/clock.c | 82
-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- Fixed enum and exynos542x_get_periph_rate switch.
- Added checks for negative values in exynos542x_get_periph_rate.
Changes since v1:
- Changes suuport - support in commit message.
- Removed position
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- No change.
Changes since v1:
- Separated exynos5_get_periph_rate fixes
Removing dead code of peripheral and SoC specific function
implementations which was used for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay
-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- Changes suuport - support in commit message.
- Removed position change of exynos5420_get_pll_clk.
- Removed #ifdef.
arch/arm/cpu/armv7/exynos/clock.c | 151 +++--
arch/arm
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- Separated exynos5_get_periph_rate fixes into another patch.
arch/arm/cpu/armv7/exynos
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 3. It also reads prediv and does division only for
SDMMC0 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
to
exynos542x_get_pll_clk because it is being used for both Exynos
5420 and 5800.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v1:
- New patch.
arch/arm/cpu/armv7/exynos/clock.c | 82 +++
1 file changed, 41 insertions(+), 41 deletions
useless due to
introduction of clock_get_periph_rate.
Changes since v1:
- Added 2 new patches.
Akshay Saraswat (6):
Exynos5: Fix compiler warnings due to clock_get_periph_rate
Exynos542x: Move exynos5420_get_pll_clk up and rename
Exynos542x: Add and enable get_periph_rate support
-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/Makefile| 2 +
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 90 +++
arch/arm/cpu/armv7/exynos/sec_boot.S | 145 ++
3 files changed, 219 insertions(+), 18 deletions
that they may come out
of WFE and jump to power_down_core function.
Step-6: And ultimately because of power_down_core all
secondary cores shut-down.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos
a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
1 file changed, 22
1. Renaming set_l2cache to configure_l2actlr in order to avoid
misleading comprehensions. Apparently this name suggests
that L2 cache is being set or initialized which is incorrect
as per the code in this function.
2. Cleaning missed mrc for L2 control register.
Signed-off-by: Akshay
the logic that uses that bit retains the previous
value.
Signed-off-by: Kimoon Kim kimoon@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos
the execution
unit consider the branch target as an ARM instruction.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7/exynos
in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Akshay Saraswat aksha...@samsung.com
Removing dead code of peripheral and SoC specific function
implementations which was used for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes
-by: Akshay Saraswat aksha...@samsung.com
---
include/configs/exynos5-common.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h
index ad63f3c..831bfd3 100644
--- a/include/configs/exynos5-common.h
This patch series introduces changes for booting secondary CPUs
on Exynos5420 and Exynos5800.
Akshay Saraswat (10):
Exynos542x: Config: Add various configs
Exynos542x: CPU: Power down all secondary cores
Exynos542x: Add workaround for ARM errata 798870
Exynos542x: Add workaround for ARM
instructions.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 2 +-
arch/arm/include/asm/arch-exynos/system.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c
b/arch/arm/cpu/armv7
L2 Auxiliary Control Register provides configuration
and control options for the L2 memory system. Bit 3
of L2ACTLR stands for clean/evict push to external.
Setting bit 3 disables clean/evict which is what
this patch intends to do.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm
to switching.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/lowlevel_init.c | 53 +++
arch/arm/cpu/armv7/exynos/soc.c | 7
2 files changed, 46 insertions(+), 14 deletions
useless due to
introduction of clock_get_periph_rate.
Akshay Saraswat (4):
Exynos5: Fix compiler warnings due to clock_get_periph_rate
Exynos542x: Add and enable get_periph_rate support
Exynos5: Use clock_get_periph_rate generic API
Exynos5: Remove dead code for fetching clocks
arch
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/clock.c | 60 +++
1 file changed, 48 insertions(+), 12
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay
-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/clock.c | 211 +++--
arch/arm/include/asm/arch-exynos/clk.h | 8 ++
2 files changed, 183 insertions(+), 36 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7
Removing dead code of peripheral and SoC specific function
implementations which was used for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm
for Exynos5420.
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
arch/arm/cpu/armv7/exynos/clock.c | 574 -
arch/arm/include/asm/arch-exynos/clk.h | 8 +
2 files changed, 279 insertions(+), 303 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b
Hi Przemyslaw,
Hello Akshay,
On 01/09/2015 10:21 AM, Akshay Saraswat wrote:
Hi Przemyslaw,
This commit allows for test i2c drivers with new i2c api
on Exynos5xxx based boards.
The S3C24X0 I2C driver supports driver model I2C api,
but i2c peripherials drivers on exynos5 boards doesn't.
So
patch
or config to encounter this?
Best Regards,
Jaehoon Chung
Regards,
Simon
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Regards,
Akshay Saraswat
___
U
1 - 100 of 410 matches
Mail list logo
