[PATCH] riscv: ae350: Increase malloc size for binman spl flow

2021-05-17 Thread Andes
From: Rick Chen It will need larger heap size for u-boot-spl to load u-boot.itb which be generated from binman than USE_SPL_FIT_GENERATOR. Signed-off-by: Rick Chen --- configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv64_spl_defconfig

[PATCH] MAINTAINERS: Add a co-maintainer for RISC-V

2021-01-24 Thread Andes
From: Rick Chen Add Leo as co-maintainer for RISC-V. Signed-off-by: Rick Chen --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index a7a62df..ee89d50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -947,6 +947,7 @@ F: arch/powerpc/cpu/mpc86xx/

[PATCH] riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg

2020-07-17 Thread Andes
From: Rick Chen Use fdtdec_get_addr_size_auto_noparent to read the "reg" property instead of fdtdec_get_addr. This will increase the compatibility of dtb parsing. Signed-off-by: Rick Chen --- board/AndesTech/ax25-ae350/ax25-ae350.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[U-Boot] [PATCH v2 07/10] riscv: Fix clear bss loop in the start-up code

2019-11-13 Thread Andes
From: Rick Chen For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen Cc: KC Lin Cc:

[U-Boot] [PATCH v2 09/10] riscv: dts: Add #address-cells and #size-cells in nor node

2019-11-13 Thread Andes
From: Rick Chen Those are required for cfi-flash driver to get correct address information. Also modify size description correctly. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/dts/ae350_32.dts | 4 +++- arch/riscv/dts/ae350_64.dts | 4 +++- 2 files changed, 6

[U-Boot] [PATCH v2 10/10] doc: update AX25-AE350 RISC-V documentation

2019-11-13 Thread Andes
+--- +Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be +cloned and build for AE350 as below: + +git clone https://github.com/riscv/opensbi.git +cd opensbi +make PLATFORM=andes/ae350 + +Copy OpenSBI FW_DYNAMIC image (build\platform\andes\ae350\firmware

[U-Boot] [PATCH v2 08/10] riscv: dts: Support four cores SMP

2019-11-13 Thread Andes
From: Rick Chen Add CPU2 and CPU3 information in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/dts/ae350_32.dts | 57 ++--- arch/riscv/dts/ae350_64.dts | 57

[U-Boot] [PATCH v2 06/10] spl: cache: Allow cache drivers in SPL

2019-11-13 Thread Andes
From: Rick Chen When ax25-ae350 try to enable v5l2 cache driver in SPL configuration, it need this option for cache support in SPL. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- common/spl/Kconfig | 7 +++ drivers/Makefile | 1 + 2 files changed, 8 insertions(+) diff --git

[U-Boot] [PATCH v2 03/10] riscv: ax25-ae350: Use generic memory size setup

2019-11-13 Thread Andes
From: Rick Chen To get memory size from device tree instead of get_ram_size(). This can avoid memory access fault in U-Boot proper after PMP configurations in OpenSBI. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++--- 1

[U-Boot] [PATCH v2 05/10] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

2019-11-13 Thread Andes
From: Rick Chen The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/cpu/ax25/cache.c | 60 ++--- 1 file changed, 46

[U-Boot] [PATCH v2 04/10] riscv: andes_plic: Fix some wrong configurations

2019-11-13 Thread Andes
From: Rick Chen Fix two wrong settings of andes plic driver as below: 1. Fix wrong pending register base definition. 2. Declaring the en variable in enable_ipi() as unsigned int instead of int can help to fix wrong plic enabling setting in RV64. Signed-off-by: Rick Chen Cc: KC Lin Cc

[U-Boot] [PATCH v2 02/10] riscv: ax25-ae350: add SPL configuration

2019-11-13 Thread Andes
From: Rick Chen This patch provides four configurations which can support U-Boot SPL to boot from RAM or FLASH and then boot FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices. With ae350_rv[32|64]_spl_defconfigs: U-Boot SPL will be loaded by

[U-Boot] [PATCH v2 00/10] RISC-V AX25-AE350 support SPL

2019-11-13 Thread Andes
From: Rick Chen This series add support for SPL to AX25-AE350. U-Boot SPL can boot from RAM or ROM and jump to OPenSbi(FW_DYNAMIC firmware) and U-Boot proper from RAM or MMC devices. Also fix some bugs of andes plic driver and improve cache configurations for SPL. Changes in v2: - Remove

[U-Boot] [PATCH v2 01/10] riscv: ax25: add SPL support

2019-11-13 Thread Andes
SPL_CPU_SUPPORT + imply SPL_OPENSBI + imply SPL_LOAD_FIT help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. -- 2.7.4 ___ U-Boot mailing

[U-Boot] [PATCH 7/8] riscv: Fix clear bss loop in the start-up code

2019-10-25 Thread Andes
From: Rick Chen For RV64, it will use sd instruction to clear t0 register, and the increament will be 8 bytes. So if the difference between__bss_strat and __bss_end was not 8 bytes aligned, the clear bss loop will overflow and acks like system hang. Signed-off-by: Rick Chen Cc: KC Lin Cc:

[U-Boot] [PATCH 8/8] riscv: dts: Support four cores SMP

2019-10-25 Thread Andes
From: Rick Chen Add CPU2 and CPU3 informations in cpus node to support four cores SMP booting. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/dts/ae350_32.dts | 51 ++--- arch/riscv/dts/ae350_64.dts | 51

[U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

2019-10-25 Thread Andes
From: Rick Chen The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- arch/riscv/cpu/ax25/cache.c | 60 ++--- 1 file changed, 46

[U-Boot] [PATCH 6/8] spl: cache: Allow cache drivers in SPL

2019-10-25 Thread Andes
From: Rick Chen When ax25-ae350 try to enable v5l2 cache driver in SPL configuration, it need this option for cache support in SPL. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- common/spl/Kconfig | 7 +++ drivers/Makefile | 1 + 2 files changed, 8 insertions(+) diff --git

[U-Boot] [PATCH 3/8] riscv: ax25-ae350: Use generic memory size setup

2019-10-25 Thread Andes
From: Rick Chen To get memory size from device tree instead of get_ram_size(). This can avoid memory access fault in U-Boot proper after PMP configurations in OpenSbi. Signed-off-by: Rick Chen Cc: KC Lin Cc: Alan Kao --- board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++--- 1

[U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations

2019-10-25 Thread Andes
From: Rick Chen It will work fine due to hart 0 always will be main hart coincidentally. When develop SPL flow, I try to force other harts to be main hart. And it will go wrong in sending IPI flow. So fix it. Having this fix, any hart can be main hart in U-Boot SPL theoretically, but it still

[U-Boot] [PATCH 2/8] riscv: ax25-ae350: add SPL configuration

2019-10-25 Thread Andes
From: Rick Chen This patch provides four configurations which can support U-Boot SPL to boot from RAM or FLASH and then boot FIT image including OpenSBI FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices. With ae350_rv[32|64]_spl_defconfigs: U-Boot SPL will be loaded by

[U-Boot] [PATCH 1/8] riscv: ax25: add SPL support

2019-10-25 Thread Andes
some specific features which are provided by Andes Technology AndeStar V5 families. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH 0/8] RISC-V AX25-AE350 support SPL

2019-10-25 Thread Andes
From: Rick Chen This series add support for SPL to AX25-AE350. U-Boot SPL can boots from RAM or ROM and jump to OPenSbi(FW_DYNAMIC firmware) and U-Boot proper from RAM or MMC devices. Also fix some bugs for andes plic driver and improve cache configurations for SPL. Following are the booting

[U-Boot] [PATCH v4 8/8] riscv: cache: use CCTL to flush d-cache

2019-08-28 Thread Andes
+ +/* D-cache operation */ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* -* Andes' AX25 does not have a coherence agent. U-Boot must use data -* cache flush and invalidate functions to keep data in the system -* coherent

[U-Boot] [PATCH v4 4/8] riscv: ae350: use the v5l2 driver to configure the cache

2019-08-28 Thread Andes
From: Rick Chen Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- board/AndesTech/ax25-ae350/ax25-ae350.c | 9 + 1 file changed, 9 insertions(+) diff --git

[U-Boot] [PATCH v4 7/8] riscv: dts: move out AE350 L2 node from cpus node

2019-08-28 Thread Andes
5l2cache"; + cache-level = <2>; + cache-size = <0x4>; + reg = <0xe050 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is */ +

[U-Boot] [PATCH v4 5/8] riscv: ax25: add imply v5l2 cache controller

2019-08-28 Thread Andes
From: Rick Chen Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e..49be775 100644

[U-Boot] [PATCH v4 6/8] riscv: cache: Flush L2 cache before jump to linux

2019-08-28 Thread Andes
From: Rick Chen Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng ---

[U-Boot] [PATCH v4 2/8] dm: cache: Add enable and disable ops for sandbox and test

2019-08-28 Thread Andes
From: Rick Chen Add cache enable and disable ops for test coverage. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- drivers/cache/sandbox_cache.c | 13 + test/dm/cache.c | 2 ++ 2 files changed, 15 insertions(+) diff --git

[U-Boot] [PATCH v4 3/8] dm: cache: add v5l2 cache controller driver

2019-08-28 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen Cc: KC Lin

[U-Boot] [PATCH v4 0/8] Support Andes RISC-V l2cache on AE350 platform

2019-08-28 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse and configure the cache settings (data & instruction prefetch, data & tag latency) from the device tree blob. Also implement L2 cache flush and disable before jump

[U-Boot] [PATCH v4 1/8] dm: cache: Add enable and disable ops for cache uclass

2019-08-28 Thread Andes
From: Rick Chen Add cache enable/disable ops to the DM cache uclass driver Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- drivers/cache/cache-uclass.c | 20 include/cache.h | 31 +++ 2 files changed, 51

[U-Boot] [PATCH] riscv: andes_plic: init plic by scanning each cpu node

2019-08-22 Thread Andes
From: Rick Chen Initialize plic driver by ofnode_for_each_subnode() instead of cpu_get_count(). This way can support to skip some harts which maybe mark as unavailable, but the cpu node exist indeed. Signed-off-by: Rick Chen Cc: KC Lin --- arch/riscv/lib/andes_plic.c | 36

[U-Boot] [PATCH 1/3] riscv: andes_plic: init plic by scanning each cpu node

2019-08-21 Thread Andes
From: Rick Chen Initialize plic driver by ofnode_for_each_subnode() instead of cpu_get_count(). This way can support to skip some harts which maybe mark as unavailable, but the cpu node exist indeed. Signed-off-by: Rick Chen Cc: KC Lin --- arch/riscv/lib/andes_plic.c | 36

[U-Boot] [PATCH v3 4/8] riscv: ae350: use the v5l2 driver to configure the cache

2019-08-21 Thread Andes
From: Rick Chen Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- board/AndesTech/ax25-ae350/ax25-ae350.c | 9 + 1 file changed, 9 insertions(+) diff --git

[U-Boot] [PATCH v3 8/8] riscv: cache: use CCTL to flush d-cache

2019-08-21 Thread Andes
+ +/* D-cache operation */ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* -* Andes' AX25 does not have a coherence agent. U-Boot must use data -* cache flush and invalidate functions to keep data in the system -* coherent

[U-Boot] [PATCH v3 6/8] riscv: cache: Flush L2 cache before jump to linux

2019-08-21 Thread Andes
From: Rick Chen Flush and disable L2 cache in dcache_disable() which will be called in cleanup_before_linux() before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: KC Lin --- arch/riscv/cpu/ax25/cache.c |

[U-Boot] [PATCH v3 7/8] riscv: dts: move out AE350 L2 node from cpus node

2019-08-21 Thread Andes
5l2cache"; + cache-level = <2>; + cache-size = <0x4>; + reg = <0xe050 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is */ +

[U-Boot] [PATCH v3 5/8] riscv: ax25: add imply v5l2 cache controller

2019-08-21 Thread Andes
From: Rick Chen Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen Cc: KC Lin Reviewed-by: Bin Meng --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e..49be775 100644

[U-Boot] [PATCH v3 2/8] dm: cache: Add enable and disable ops for sandbox and test

2019-08-21 Thread Andes
From: Rick Chen Add L2 cache enable and disable ops for test coverage. Signed-off-by: Rick Chen Cc: KC Lin --- drivers/cache/sandbox_cache.c | 13 + test/dm/cache.c | 2 ++ 2 files changed, 15 insertions(+) diff --git a/drivers/cache/sandbox_cache.c

[U-Boot] [PATCH v3 3/8] dm: cache: add v5l2 cache controller driver

2019-08-21 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen Cc: KC Lin

[U-Boot] [PATCH v3 1/8] dm: cache: Add enable and disable ops for cache uclass

2019-08-21 Thread Andes
From: Rick Chen The L2 cache will be enabled in init flow of dm cache driver when it detect L2 node in dtb. When U-Boot jumps to Linux Kernel, the disable ops will be called to flush and disable the L2 cache via the dm cache driver. Signed-off-by: Rick Chen Cc: KC Lin ---

[U-Boot] [PATCH v3 0/8] Support Andes RISC-V l2cache on AE350 platform

2019-08-21 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse and configure the cache settings (data & instruction prefetch, data & tag latency) from the device tree blob. Also implement L2 cache flush and disable before jump

[U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux

2019-07-09 Thread Andes
From: Rick Chen Flush and disable cache in cleanup_before_linux() which will be called before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: Greentime Hu Cc: KC Lin --- arch/riscv/cpu/ax25/cpu.c | 26

[U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache

2019-07-09 Thread Andes
operation */ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* -* Andes' AX25 does not have a coherence agent. U-Boot must use data -* cache flush and invalidate functions to keep data in the system -* coherent. -* The implementation

[U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller

2019-07-09 Thread Andes
From: Rick Chen Select the v5l2 UCLASS_CACHE driver for ax25. Signed-off-by: Rick Chen Cc: Greentime Hu Cc: KC Lin --- arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 6b4b92e..49be775 100644 ---

[U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node

2019-07-09 Thread Andes
5l2cache"; + cache-level = <2>; + cache-size = <0x4>; + reg = <0xe050 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + /* The value format is */ +

[U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache

2019-07-09 Thread Andes
From: Rick Chen Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen Cc: Greentime Hu Cc: KC Lin --- board/AndesTech/ax25-ae350/ax25-ae350.c | 9 + 1 file changed, 9 insertions(+) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c

[U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver

2019-07-09 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen Cc: Greentime Hu

[U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform

2019-07-09 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse and configure the cache settings (data & instruction prefetch, data & tag latency) from the device tree blob. Also implement L2 cache flush and disable before jump

[U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass

2019-07-09 Thread Andes
From: Rick Chen The L2 cache will be enabled in init flow of dm cache driver when it detect L2 node in dtb. When U-Boot jump to Linux Kernel, the disable ops will be called to flush and disable the L2 cache via the dm cache driver. Signed-off-by: Rick Chen Cc: KC Lin ---

[U-Boot] [PATCH] MAINTAINERS: Remove Macpaul and add Rick as nds32 maintainer

2019-07-09 Thread Andes
From: Rick Chen Macpaul have left Andestech for a while, and this mail address macp...@andestech.com can not received mail anymore. It might encounter account creation problem in this switching to gitlab about nds32 tree. So change the nds32 maintainer as Rick Chen Signed-off-by: Rick Chen

[U-Boot] [PATCH 6/6] riscv: ax25: use CCTL to flush d-cache

2019-05-28 Thread Andes
*/ +#define CCTL_L1D_WBINVAL_ALL 6 +#endif void flush_dcache_all(void) { - /* -* Andes' AX25 does not have a coherence agent. U-Boot must use data -* cache flush and invalidate functions to keep data in the system -* coherent. -* The implementation of the fence

[U-Boot] [PATCH 4/6] riscv: cache: Flush L2 cache before jump to linux

2019-05-28 Thread Andes
From: Rick Chen Flush and disable cache in cleanup_before_linux() which will be called before jump to linux. The sequence will be preferred as below: L1 flush -> L1 disable -> L2 flush -> L2 disable Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/cpu/ax25/cpu.c | 4 1 file

[U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node

2019-05-28 Thread Andes
ot;cache"; + cache-level = <2>; + cache-size = <0x4>; + reg = <0xe050 0x40000>; + andes,inst-prefetch = <3>; + andes,data-prefetch = <3>; + // The value format is +

[U-Boot] [PATCH 1/6] dm: cache: add v5l2 cache controller driver

2019-05-28 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen Cc: Greentime Hu

[U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller

2019-05-28 Thread Andes
From: Rick Chen Select the v5l2 UCLASS_CACHE driver for AE350. Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 5e682b6..dd299d9

[U-Boot] [PATCH 2/6] riscv: ae350: use the v5l2 driver to configure the cache

2019-05-28 Thread Andes
From: Rick Chen Find the UCLASS_CACHE driver to configure the cache controller's settings. Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/ax25-ae350.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c

[U-Boot] [PATCH 0/6] Support Andes RISC-V l2cache on AE350 platform

2019-05-28 Thread Andes
From: Rick Chen Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse and configure the cache settings (data & instruction prefetch, data & tag latency) from the device tree blob. Also implement L2 cache flush and disable before jump

[U-Boot] [PATCH v5 6/6] riscv: configs: add ae350_rv[32|64]_xip_defconfig to MAINTAINERS

2019-05-08 Thread Andes
From: Rick Chen This patch will fix Travis failure item as below: https://travis-ci.org/rickchen36/u-boot-riscv/jobs/529605196 Check for configs without MAINTAINERS entry Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/MAINTAINERS | 2 ++ 1 file changed, 2

[U-Boot] [PATCH v5 4/6] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ram

2019-05-08 Thread Andes
From: Rick Chen When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2

[U-Boot] [PATCH v5 5/6] riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash

2019-05-08 Thread Andes
From: Rick Chen When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD. Also remove unused code about prior_stage_fdt_address. And modify CONFIG_SYS_FDT_BASE as flash address. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer

[U-Boot] [PATCH v5 2/6] riscv: configs: Support AE350 SMP booting from flash flow

2019-05-08 Thread Andes
From: Rick Chen Add two defconfigs to support AE350 SMP booting from flash. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- configs/ae350_rv32_xip_defconfig | 37 + configs/ae350_rv64_xip_defconfig | 38

[U-Boot] [PATCH v5 3/6] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-05-08 Thread Andes
From: Rick Chen This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng

[U-Boot] [PATCH v5 0/6] AE350 support SMP boot from flash

2019-05-08 Thread Andes
From: Rick Chen In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by

[U-Boot] [PATCH v5 1/6] riscv: Introduce CONFIG_XIP to support booting from flash

2019-05-08 Thread Andes
From: Rick Chen When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen

[U-Boot] [PATCH v4 5/5] riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash

2019-04-29 Thread Andes
From: Rick Chen When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD. Also remove unused code about prior_stage_fdt_address. And modify CONFIG_SYS_FDT_BASE as flash address. Signed-off-by: Rick Chen Cc: Greentime Hu --- board/AndesTech/ax25-ae350/ax25-ae350.c | 4

[U-Boot] [PATCH v4 3/5] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-04-29 Thread Andes
From: Rick Chen This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/cpu/cpu.c |

[U-Boot] [PATCH v4 4/5] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ram

2019-04-29 Thread Andes
From: Rick Chen When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2

[U-Boot] [PATCH v4 2/5] riscv: configs: Support AE350 SMP booting from flash flow

2019-04-29 Thread Andes
From: Rick Chen Add two defconfigs to support AE350 SMP booting from flash. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- configs/ae350_rv32_xip_defconfig | 37 + configs/ae350_rv64_xip_defconfig | 38

[U-Boot] [PATCH v4 1/5] riscv: Introduce CONFIG_XIP to support booting from flash

2019-04-29 Thread Andes
From: Rick Chen When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen

[U-Boot] [PATCH v4 0/5] AE350 support SMP boot from flash

2019-04-29 Thread Andes
From: Rick Chen In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by

[U-Boot] [PATCH v3 4/4] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram

2019-04-29 Thread Andes
From: Rick Chen When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2

[U-Boot] [PATCH v3 1/4] riscv: Introduce CONFIG_XIP to support booting from flash

2019-04-29 Thread Andes
From: Rick Chen When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen

[U-Boot] [PATCH v3 3/4] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-04-29 Thread Andes
From: Rick Chen This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/cpu/cpu.c

[U-Boot] [PATCH v3 2/4] riscv: configs: Support AE350 SMP booting from flash flow

2019-04-29 Thread Andes
From: Rick Chen Add two defconfigs to support AE350 SMP booting from flash. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- configs/ae350_rv32_xip_defconfig | 37 + configs/ae350_rv64_xip_defconfig | 38

[U-Boot] [PATCH v3 0/4] AE350 support SMP boot from flash

2019-04-29 Thread Andes
From: Rick Chen In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by

[U-Boot] [PATCH v2 4/4] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram

2019-04-24 Thread Andes
From: Rick Chen When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead of CONFIG_OF_BOARD. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

[U-Boot] [PATCH v2 2/4] riscv: configs: Support AE350 SMP booting from flash flow

2019-04-24 Thread Andes
From: Rick Chen Add two defconfigs to support AE350 SMP booting from flash. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ae350_rv32_xip_defconfig | 36 configs/ae350_rv64_xip_defconfig | 37 + 2 files changed,

[U-Boot] [PATCH v2 3/4] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-04-24 Thread Andes
From: Rick Chen This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash. When AE350 was booting from falsh, prior_stage_fdt_address will be in flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu ---

[U-Boot] [PATCH v2 1/4] riscv: hart_lottery and available harts features can be selectable

2019-04-24 Thread Andes
From: Rick Chen In smp flow these two features only can be enabled when U-Boot booting from ram. It shall be disabled when U-Boot booting from flash. Add CONFIG_XIP to NOT select this two features. It's default value will say NO for booting from ram. AE350 will encounter the the write failure

[U-Boot] [PATCH v2 0/4] AE350 support SMP boot from flash

2019-04-24 Thread Andes
From: Rick Chen In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by

[U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable

2019-04-22 Thread Andes
From: Rick Chen This patch will fix prior_stage_fdt_address write failure problem, when AE350 was booting from flash. When AE350 was booting from falsh, prior_stage_fdt_address will be in flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu ---

[U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

2019-04-22 Thread Andes
From: Rick Chen When AE350 was booting from ram, use OF_PRIOR_STAGE instead of OF_PRIOR_STAGE. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ae350_rv32_defconfig | 2 +- configs/ae350_rv64_defconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

[U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow

2019-04-22 Thread Andes
From: Rick Chen Add two defconfig to support AE350 SMP boot from flash by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS. Signed-off-by: Rick Chen Cc: Greentime Hu --- configs/ae350_rv32_xip_defconfig | 37 + configs/ae350_rv64_xip_defconfig | 38

[U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

2019-04-22 Thread Andes
From: Rick Chen In smp flow this two features only can be enabled when U-Boot boot from ram. It shall be disabled when U-Boot boot from flash. Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select this two features. Their default value will say YES for booting from ram. AE350 will

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

2019-04-22 Thread Andes
From: Rick Chen In current RISC-V SMP flow, AE350 will encounter the the write failure problem since hart_lottery and available_harts_lock was not in ram address but in flash address when booing from flash. This patch can help to fix the failure problem when AE350 was booting from flash by

[U-Boot] [PATCH] riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure

2019-04-02 Thread Andes
From: Rick Chen It occurs since commit 27cb7300ffda ("Ensure device tree DTS is compiled"). More details can refer to 89c2b5c02049aea746b1edee0b4e1d8519dec2f4 ARM: fix arch/arm/dts/Makefile Signed-off-by: Rick Chen Cc: Greentime Hu --- arch/riscv/dts/Makefile | 2 ++ 1 file changed, 2

[U-Boot] [PATCH v4 6/6] riscv: ae350: enable SMP

2019-04-02 Thread Andes
From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 44cb302..5e682b6

[U-Boot] [PATCH v4 5/6] riscv: dts: ae350 support SMP

2019-04-02 Thread Andes
From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/dts/ae350_32.dts | 81 + arch/riscv/dts/ae350_64.dts | 81 + 2 files changed, 118

[U-Boot] [PATCH v4 2/6] riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-02 Thread Andes
5 files changed, 67 insertions(+) create mode 100644 arch/riscv/lib/andes_plmt.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 511768b..ae8ff7b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -118,6 +118,15 @@ config ANDES_PLIC The Andes PLIC block

[U-Boot] [PATCH v4 4/6] riscv: ax25: Andes specific cache shall only support in M-mode

2019-04-02 Thread Andes
ISCV_MMODE help Provide Andes Technology AndeStar V5 families specific cache support. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v4 3/6] riscv: ax25: Add platform-specific Kconfig options

2019-04-02 Thread Andes
+ imply ANDES_PLMT if RISCV_MMODE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index 5837b48..e13c7de

[U-Boot] [PATCH v4 0/6] AE350 SMP support RISC-V

2019-04-02 Thread Andes
a SYSCON driver for Andestech's PLMT riscv: ax25: Add platform-specific Kconfig options riscv: ax25: Andes specific cache shall only support in M-mode riscv: dts: ae350 support SMP riscv: ae350: enable SMP arch/riscv/Kconfig | 18 ++ arch/riscv/cpu/ax25/Kconfig

[U-Boot] [PATCH v4 1/6] riscv: Add a SYSCON driver for Andestech's PLIC

2019-04-02 Thread Andes
SYSCON + help + The Andes PLIC block holds memory-mapped claim and pending registers + associated with software interrupt. + config RISCV_RDTIME bool default y if RISCV_SMODE diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h

[U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

2019-04-01 Thread Andes
help Provide Andes Technology AndeStar V5 families specific cache support. -- 2.7.4 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot

[U-Boot] [PATCH v3 7/7] riscv: ae350: enable SMP

2019-04-01 Thread Andes
From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng --- board/AndesTech/ax25-ae350/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig index 44cb302..5e682b6 100644 ---

[U-Boot] [PATCH v3 6/7] riscv: dts: ae350 support SMP

2019-04-01 Thread Andes
From: Rick Chen Signed-off-by: Rick Chen Cc: Greentime Hu --- V3: - Fix some mis-alignments. - Recovery isa string of CPU1. arch/riscv/dts/ae350_32.dts | 81 + arch/riscv/dts/ae350_64.dts | 81 + 2

[U-Boot] [PATCH v3 4/7] riscv: ax25: Add platform-specific Kconfig options

2019-04-01 Thread Andes
if RISCV_MMODE + imply ANDES_PLMT if RISCV_MMODE help Run U-Boot on AndeStar V5 platforms and use some specific features which are provided by Andes Technology AndeStar V5 families. -- 2.7.4 ___ U-Boot mailing list U-Boot

[U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-01 Thread Andes
5 files changed, 67 insertions(+) create mode 100644 arch/riscv/lib/andes_plmt.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 511768b..ae8ff7b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -118,6 +118,15 @@ config ANDES_PLIC The Andes PLIC block holds memory

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