[PATCH] riscv: ae350: Increase malloc size for binman spl flow

2021-05-17 Thread Andes
From: Rick Chen 

It will need larger heap size for u-boot-spl to load u-boot.itb which
be generated from binman than USE_SPL_FIT_GENERATOR.

Signed-off-by: Rick Chen 
---
 configs/ae350_rv32_spl_defconfig | 1 +
 configs/ae350_rv32_spl_xip_defconfig | 1 +
 configs/ae350_rv64_spl_defconfig | 1 +
 configs/ae350_rv64_spl_xip_defconfig | 1 +
 4 files changed, 4 insertions(+)

diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 25b4ada..e8dc816 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
 CONFIG_SYS_TEXT_BASE=0x0120
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x10
 CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_TARGET_AX25_AE350=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig 
b/configs/ae350_rv32_spl_xip_defconfig
index c5d7ac3..418170c 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
 CONFIG_SYS_TEXT_BASE=0x0120
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x10
 CONFIG_SPL_TEXT_BASE=0x8000
 CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index 61637a9..d23b56c 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
 CONFIG_SYS_TEXT_BASE=0x0120
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x10
 CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_TARGET_AX25_AE350=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig 
b/configs/ae350_rv64_spl_xip_defconfig
index 6c63382..7826ae4 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -2,6 +2,7 @@ CONFIG_RISCV=y
 CONFIG_SYS_TEXT_BASE=0x0120
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x10
 CONFIG_SPL_TEXT_BASE=0x8000
 CONFIG_SPL=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
-- 
2.7.4



[PATCH] MAINTAINERS: Add a co-maintainer for RISC-V

2021-01-24 Thread Andes
From: Rick Chen 

Add Leo as co-maintainer for RISC-V.

Signed-off-by: Rick Chen 
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index a7a62df..ee89d50 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -947,6 +947,7 @@ F:  arch/powerpc/cpu/mpc86xx/
 
 RISC-V
 M: Rick Chen 
+M: Leo 
 S: Maintained
 T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
 F: arch/riscv/
-- 
2.7.4



[PATCH] riscv: ae350: Use fdtdec_get_addr_size_auto_noparent to parse smc reg

2020-07-17 Thread Andes
From: Rick Chen 

Use fdtdec_get_addr_size_auto_noparent to read the "reg" property
instead of fdtdec_get_addr. This will increase the compatibility
of dtb parsing.

Signed-off-by: Rick Chen 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index da5bc5b..231a0d5 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -71,7 +71,8 @@ int smc_init(void)
if (node < 0)
return -FDT_ERR_NOTFOUND;
 
-   addr = fdtdec_get_addr(blob, node, "reg");
+   addr = fdtdec_get_addr_size_auto_noparent(blob, node,
+   "reg", 0, NULL, false);
 
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
-- 
2.7.4



[U-Boot] [PATCH v2 07/10] riscv: Fix clear bss loop in the start-up code

2019-11-13 Thread Andes
From: Rick Chen 

For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/cpu/start.S| 4 ++--
 arch/riscv/cpu/u-boot-spl.lds | 2 +-
 arch/riscv/cpu/u-boot.lds | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 0a2ce6d..ee6d471 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -174,7 +174,7 @@ spl_clear_bss:
 spl_clear_bss_loop:
SREGzero, 0(t0)
addit0, t0, REGBYTES
-   bne t0, t1, spl_clear_bss_loop
+   blt t0, t1, spl_clear_bss_loop
 
 spl_stack_gd_setup:
jal spl_relocate_stack_gd
@@ -324,7 +324,7 @@ clear_bss:
 clbss_l:
SREGzero, 0(t0) /* clear loop... */
addit0, t0, REGBYTES
-   bne t0, t1, clbss_l
+   blt t0, t1, clbss_l
 
 relocate_secondary_harts:
 #ifdef CONFIG_SMP
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index 32255d5..955dd31 100644
--- a/arch/riscv/cpu/u-boot-spl.lds
+++ b/arch/riscv/cpu/u-boot-spl.lds
@@ -76,7 +76,7 @@ SECTIONS
.bss : {
__bss_start = .;
*(.bss*)
-   . = ALIGN(4);
+   . = ALIGN(8);
__bss_end = .;
} > .bss_mem
 }
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds
index 11bc4a7..838a844 100644
--- a/arch/riscv/cpu/u-boot.lds
+++ b/arch/riscv/cpu/u-boot.lds
@@ -82,7 +82,7 @@ SECTIONS
.bss : {
__bss_start = .;
*(.bss*)
-   . = ALIGN(4);
+   . = ALIGN(8);
__bss_end = .;
}
 }
-- 
2.7.4

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[U-Boot] [PATCH v2 09/10] riscv: dts: Add #address-cells and #size-cells in nor node

2019-11-13 Thread Andes
From: Rick Chen 

Those are required for cfi-flash driver to get correct address information.
Also modify size description correctly.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/dts/ae350_32.dts | 4 +++-
 arch/riscv/dts/ae350_64.dts | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index c6c2040..3f8525f 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -296,8 +296,10 @@
};
 
nor@0,0 {
+   #address-cells = <1>;
+   #size-cells = <1>;
compatible = "cfi-flash";
-   reg = <0x8800 0x1000>;
+   reg = <0x8800 0x400>;
bank-width = <2>;
device-width = <1>;
};
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index c57efe3..482c707 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -296,8 +296,10 @@
};
 
nor@0,0 {
+   #address-cells = <2>;
+   #size-cells = <2>;
compatible = "cfi-flash";
-   reg = <0x0 0x8800 0x0 0x1000>;
+   reg = <0x0 0x8800 0x0 0x400>;
bank-width = <2>;
device-width = <1>;
};
-- 
2.7.4

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[U-Boot] [PATCH v2 10/10] doc: update AX25-AE350 RISC-V documentation

2019-11-13 Thread Andes
From: Rick Chen 

Add descriptions about U-Boot SPL feature and how to build and run.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 doc/board/AndesTech/ax25-ae350.rst | 209 -
 1 file changed, 206 insertions(+), 3 deletions(-)

diff --git a/doc/board/AndesTech/ax25-ae350.rst 
b/doc/board/AndesTech/ax25-ae350.rst
index 7a01893..a7bd1a7 100644
--- a/doc/board/AndesTech/ax25-ae350.rst
+++ b/doc/board/AndesTech/ax25-ae350.rst
@@ -324,6 +324,209 @@ Boot bbl and riscv-linux via U-Boot on QEMU
/ #
 
 
-TODO
-
-Boot bbl and riscv-linux via U-Boot on AE350 board
+Running U-Boot SPL
+--
+The U-Boot SPL will boot in M mode and load the FIT image which include
+OpenSBI and U-Boot proper images. After loading progress, it will jump
+to OpenSBI first and then U-Boot proper which will run in S mode.
+
+
+How to build U-Boot SPL
+---
+Before building U-Boot SPL, OpenSBI must be build first. OpenSBI can be
+cloned and build for AE350 as below:
+
+git clone https://github.com/riscv/opensbi.git
+cd opensbi
+make PLATFORM=andes/ae350
+
+Copy OpenSBI FW_DYNAMIC image 
(build\platform\andes\ae350\firmware\fw_dynamic.bin)
+into U-Boot root directory
+
+
+How to build U-Boot SPL booting from RAM
+
+With ae350_rv[32|64]_spl_defconfigs:
+
+U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
+and then load FIT image from RAM device on AE350.
+
+
+How to build U-Boot SPL booting from ROM
+
+With ae350_rv[32|64]_spl_xip_defconfigs:
+
+U-Boot SPL can be burned into SPI flash and run in flash in machine mode
+and then load FIT image from SPI flash or MMC device on AE350.
+
+
+Messages of U-Boot SPL boots Kernel on AE350 board
+--
+
+.. code-block:: none
+
+U-Boot SPL 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800)
+Trying to boot from RAM
+
+OpenSBI v0.5-1-gdd8ef28 (Nov 14 2019 11:08:39)
+   _  _
+  / __ \  / |  _ \_   _|
+ | |  | |_ __   ___ _ __ | (___ | |_) || |
+ | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
+ | |__| | |_) |  __/ | | |) | |_) || |_
+  \/| .__/ \___|_| |_|_/|/_|
+| |
+|_|
+
+Platform Name  : Andes AE350
+Platform HART Features : RV64ACIMSUX
+Platform Max HARTs : 4
+Current Hart   : 0
+Firmware Base  : 0x0
+Firmware Size  : 84 KB
+Runtime SBI Version: 0.2
+
+PMP0: 0x-0x0001 (A)
+PMP1: 0x-0x0001 (A,R,W,X)
+
+
+U-Boot 2020.01-rc1-00292-g67a3313-dirty (Nov 14 2019 - 11:26:21 +0800)
+
+DRAM:  1 GiB
+Flash: 64 MiB
+MMC:   mmc@f0e0: 0
+Loading Environment from SPI Flash... SF: Detected mx25u1635e with page size 
256 Bytes, erase size 4 KiB, total 2 MiB
+OK
+In:serial@f030
+Out:   serial@f030
+Err:   serial@f030
+Net:   no alias for ethernet0
+
+Warning: mac@e010 (eth0) using random MAC address - a2:ae:93:7b:cc:8f
+eth0: mac@e010
+Hit any key to stop autoboot:  0
+6455 bytes read in 31 ms (203.1 KiB/s)
+20421684 bytes read in 8647 ms (2.3 MiB/s)
+## Booting kernel from Legacy Image at 0060 ...
+   Image Name:
+   Image Type:   RISC-V Linux Kernel Image (uncompressed)
+   Data Size:20421620 Bytes = 19.5 MiB
+   Load Address: 0020
+   Entry Point:  0020
+   Verifying Checksum ... OK
+## Flattened Device Tree blob at 2000
+   Booting using the fdt blob at 0x2000
+   Loading Kernel Image
+   Loading Device Tree to 1effb000, end 1efff936 ... OK
+
+Starting kernel ...
+
+OF: fdt: Ignoring memory range 0x0 - 0x20
+Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version 7.3.0 
(2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT Sat Apr 6 
23:41:49 CST 2019
+bootconsole [early0] enabled
+Initial ramdisk at: 0x(ptrval) (13665712 bytes)
+Zone ranges:
+  DMA32[mem 0x0020-0x3fff]
+  Normal   empty
+Movable zone start for each node
+Early memory node ranges
+  node   0: [mem 0x0020-0x3fff]
+Initmem setup node 0 [mem 0x0020-0x3fff]
+software IO TLB [mem 0x3b1f8000-0x3f1f8000] (64MB) mapped at [
(ptrval)-(ptrval)]
+elf_platform is rv64i2p0m2p0a2p0c2p0xv5-0p0
+compatible privileged spec version 1.10
+percpu: Embedded 16 pages/cpu @(ptrval) s28184 r8192 d29160 u65536
+Built 1 zonelists, mobility grouping on.  Total pages: 258055
+Kernel command line: console=ttyS0,38400n8 debug loglevel=7
+log_buf_len individual max cpu contribution: 4096 bytes
+log_buf_len total cpu_extra contributions: 12288 bytes
+log_buf_len min size: 16384 bytes
+log_buf_len: 32768 bytes
+early log buf free: 14608(89%)
+Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
+Inode-cache hash table entries: 65536 (order

[U-Boot] [PATCH v2 08/10] riscv: dts: Support four cores SMP

2019-11-13 Thread Andes
From: Rick Chen 

Add CPU2 and CPU3 information in cpus node
to support four cores SMP booting.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/dts/ae350_32.dts | 57 ++---
 arch/riscv/dts/ae350_64.dts | 57 ++---
 2 files changed, 108 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 97b7cee..c6c2040 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,6 +62,48 @@
compatible = "riscv,cpu-intc";
};
};
+   CPU2: cpu@2 {
+   device_type = "cpu";
+   reg = <2>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv32";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = <>;
+   CPU2_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "riscv,cpu-intc";
+   };
+   };
+   CPU3: cpu@3 {
+   device_type = "cpu";
+   reg = <3>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv32";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = <>;
+   CPU3_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "riscv,cpu-intc";
+   };
+   };
};
 
L2: l2-cache@e050 {
@@ -94,7 +136,10 @@
interrupt-controller;
reg = <0xe400 0x200>;
riscv,ndev=<71>;
-   interrupts-extended = <_intc 11 _intc 9 
_intc 11 _intc 9>;
+   interrupts-extended = <_intc 11 _intc 9
+   _intc 11 _intc 9
+   _intc 11 _intc 9
+   _intc 11 _intc 9>;
};
 
plic1: interrupt-controller@e640 {
@@ -104,12 +149,18 @@
interrupt-controller;
reg = <0xe640 0x40>;
riscv,ndev=<2>;
-   interrupts-extended = <_intc 3 _intc 3>;
+   interrupts-extended = <_intc 3
+   _intc 3
+   _intc 3
+   _intc 3>;
};
 
plmt0@e600 {
compatible = "riscv,plmt0";
-   interrupts-extended = <_intc 7 _intc 7>;
+   interrupts-extended = <_intc 7
+   _intc 7
+   _intc 7
+   _intc 7>;
reg = <0xe600 0x10>;
};
};
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index d8f00f8..c57efe3 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,6 +62,48 @@
compatible = "riscv,cpu-intc";
};
};
+   CPU2: cpu@2 {
+   device_type = "cpu";
+   reg = <2>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv64imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv39";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = 

[U-Boot] [PATCH v2 06/10] spl: cache: Allow cache drivers in SPL

2019-11-13 Thread Andes
From: Rick Chen 

When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 common/spl/Kconfig | 7 +++
 drivers/Makefile   | 1 +
 2 files changed, 8 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 8f0ba8e..9ed7a42 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -439,6 +439,13 @@ config SPL_FIT_IMAGE_TINY
  ensure this information is available to the next image
  invoked).
 
+config SPL_CACHE_SUPPORT
+   bool "Support CACHE drivers"
+   help
+ Enable CACHE drivers in SPL. These drivers can keep data so that
+ future requests for that data can be served faster. Enable this option
+ to build the drivers in drivers/cache as part of an SPL build.
+
 config SPL_CPU_SUPPORT
bool "Support CPU drivers"
help
diff --git a/drivers/Makefile b/drivers/Makefile
index 0befedd..8c29b1e 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -31,6 +31,7 @@ ifndef CONFIG_TPL_BUILD
 ifdef CONFIG_SPL_BUILD
 
 obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
+obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/
 obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
-- 
2.7.4

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[U-Boot] [PATCH v2 03/10] riscv: ax25-ae350: Use generic memory size setup

2019-11-13 Thread Andes
From: Rick Chen 

To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++---
 1 file changed, 2 insertions(+), 19 deletions(-)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index b0164a9..47e6929 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -30,29 +30,12 @@ int board_init(void)
 
 int dram_init(void)
 {
-   unsigned long sdram_base = PHYS_SDRAM_0;
-   unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
-   unsigned long actual_size;
-
-   actual_size = get_ram_size((void *)sdram_base, expected_size);
-   gd->ram_size = actual_size;
-
-   if (expected_size != actual_size) {
-   printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
-   actual_size >> 20, expected_size >> 20);
-   }
-
-   return 0;
+   return fdtdec_setup_mem_size_base();
 }
 
 int dram_init_banksize(void)
 {
-   gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
-   gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
-   gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
-   gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
-
-   return 0;
+   return fdtdec_setup_memory_banksize();
 }
 
 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-- 
2.7.4

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[U-Boot] [PATCH v2 05/10] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

2019-11-13 Thread Andes
From: Rick Chen 

The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/cpu/ax25/cache.c | 60 ++---
 1 file changed, 46 insertions(+), 14 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 41de30c..e0b5fdd 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -11,18 +11,46 @@
 #include 
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
 /* mcctlcommand */
 #define CCTL_REG_MCCTLCOMMAND_NUM  0x7cc
 
 /* D-cache operation */
 #define CCTL_L1D_WBINVAL_ALL   6
 #endif
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+static void _cache_enable(void)
+{
+   struct udevice *dev = NULL;
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_enable(dev);
+}
+
+static void _cache_disable(void)
+{
+   struct udevice *dev = NULL;
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_disable(dev);
+}
+#endif
 
 void flush_dcache_all(void)
 {
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
 #endif
+#endif
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -39,6 +67,7 @@ void icache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x1\n\t"
@@ -46,12 +75,14 @@ void icache_enable(void)
);
 #endif
 #endif
+#endif
 }
 
 void icache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
asm volatile (
"fence.i\n\t"
"csrr t1, mcache_ctl\n\t"
@@ -60,24 +91,23 @@ void icache_disable(void)
);
 #endif
 #endif
+#endif
 }
 
 void dcache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
-   struct udevice *dev = NULL;
-
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
-
-   uclass_find_first_device(UCLASS_CACHE, );
-
-   if (dev)
-   cache_enable(dev);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+   _cache_enable();
+#endif
 #endif
 #endif
 }
@@ -86,19 +116,17 @@ void dcache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
-   struct udevice *dev = NULL;
-
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
-
-   uclass_find_first_device(UCLASS_CACHE, );
-
-   if (dev)
-   cache_disable(dev);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+   _cache_disable();
+#endif
 #endif
 #endif
 }
@@ -108,6 +136,7 @@ int icache_status(void)
int ret = 0;
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi   %0, t1, 0x01\n\t"
@@ -116,6 +145,7 @@ int icache_status(void)
: "memory"
);
 #endif
+#endif
 
return ret;
 }
@@ -125,6 +155,7 @@ int dcache_status(void)
int ret = 0;
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if CONFIG_IS_ENABLED(RISCV_MMODE) || CONFIG_IS_ENABLED(SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi   %0, t1, 0x02\n\t"
@@ -133,6 +164,7 @@ int dcache_status(void)
: "memory"
);
 #endif
+#endif
 
return ret;
 }
-- 
2.7.4

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[U-Boot] [PATCH v2 04/10] riscv: andes_plic: Fix some wrong configurations

2019-11-13 Thread Andes
From: Rick Chen 

Fix two wrong settings of andes plic driver as below:

1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
   int can help to fix wrong plic enabling setting in RV64.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/lib/andes_plic.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 28568e4..42394b9 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -19,7 +19,7 @@
 #include 
 
 /* pending register */
-#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart) * 8)
+#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart) / 4) 
* 4)
 /* enable register */
 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
 /* claim register */
@@ -46,7 +46,7 @@ static int init_plic(void);
 
 static int enable_ipi(int hart)
 {
-   int en;
+   unsigned int en;
 
en = ENABLE_HART_IPI >> hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
@@ -94,10 +94,13 @@ static int init_plic(void)
 
 int riscv_send_ipi(int hart)
 {
+   unsigned int ipi;
+
PLIC_BASE_GET();
 
-   writel(SEND_IPI_TO_HART(hart),
-  (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
+   ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+   writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
+   gd->arch.boot_hart));
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v2 02/10] riscv: ax25-ae350: add SPL configuration

2019-11-13 Thread Andes
From: Rick Chen 

This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.

With ae350_rv[32|64]_spl_defconfigs:

U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
and then load FIT image from RAM device on AE350.

With ae350_rv[32|64]_spl_xip_defconfigs:

U-Boot SPL can be burned into SPI flash and run in flash in machine mode
and then load FIT image from SPI flash or MMC device on AE350.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 board/AndesTech/ax25-ae350/Kconfig  |  9 
 board/AndesTech/ax25-ae350/MAINTAINERS  |  4 
 board/AndesTech/ax25-ae350/ax25-ae350.c | 27 ++
 configs/ae350_rv32_spl_defconfig| 37 ++
 configs/ae350_rv32_spl_xip_defconfig| 39 
 configs/ae350_rv64_spl_defconfig| 38 +++
 configs/ae350_rv64_spl_xip_defconfig| 40 +
 include/configs/ax25-ae350.h| 17 ++
 8 files changed, 211 insertions(+)
 create mode 100644 configs/ae350_rv32_spl_defconfig
 create mode 100644 configs/ae350_rv32_spl_xip_defconfig
 create mode 100644 configs/ae350_rv64_spl_defconfig
 create mode 100644 configs/ae350_rv64_spl_xip_defconfig

diff --git a/board/AndesTech/ax25-ae350/Kconfig 
b/board/AndesTech/ax25-ae350/Kconfig
index 5e682b6..321dd0c 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -21,9 +21,18 @@ config ENV_SIZE
 config ENV_OFFSET
default 0x14 if ENV_IS_IN_SPI_FLASH
 
+config SPL_TEXT_BASE
+   default 0x80
+
+config SPL_OPENSBI_LOAD_ADDR
+   default 0x0100
+
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
+   select SUPPORT_SPL
imply SMP
+   imply SPL_RAM_SUPPORT
+   imply SPL_RAM_DEVICE
 
 endif
diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS 
b/board/AndesTech/ax25-ae350/MAINTAINERS
index feed5d1..eebee16 100644
--- a/board/AndesTech/ax25-ae350/MAINTAINERS
+++ b/board/AndesTech/ax25-ae350/MAINTAINERS
@@ -7,3 +7,7 @@ F:  configs/ae350_rv32_defconfig
 F: configs/ae350_rv64_defconfig
 F: configs/ae350_rv32_xip_defconfig
 F: configs/ae350_rv64_xip_defconfig
+F: configs/ae350_rv32_spl_defconfig
+F: configs/ae350_rv64_spl_defconfig
+F: configs/ae350_rv32_spl_xip_defconfig
+F: configs/ae350_rv64_spl_xip_defconfig
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index b43eebb..b0164a9 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -110,3 +111,29 @@ int board_early_init_f(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+   u8 i;
+   u32 boot_devices[] = {
+#ifdef CONFIG_SPL_RAM_SUPPORT
+   BOOT_DEVICE_RAM,
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+   BOOT_DEVICE_MMC1,
+#endif
+   };
+
+   for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+   spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   /* boot using first FIT config */
+   return 0;
+}
+#endif
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
new file mode 100644
index 000..53055b7
--- /dev/null
+++ b/configs/ae350_rv32_spl_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_SPL=y
+CONFIG_RISCV_SMODE=y
+CONFIG_SYS_TEXT_BASE=0x0120
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_PRIOR_STAGE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig 
b/configs/ae350_rv32_spl_xip_defconfig
new file mode 100644
index 000..fdbab43
--- /dev/null
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -0,0 +1,39 @@
+CONFIG_RISCV=y
+CONFIG_SPL=y
+CONFIG_RISCV_SMODE=y
+CONFIG_SPL_TEXT_BASE=0x8000
+CONFIG_SYS_TEXT_BASE=0x0120
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_XIP=y

[U-Boot] [PATCH v2 00/10] RISC-V AX25-AE350 support SPL

2019-11-13 Thread Andes
From: Rick Chen 

This series add support for SPL to AX25-AE350.

U-Boot SPL can boot from RAM or ROM and jump to
OPenSbi(FW_DYNAMIC firmware) and U-Boot proper from
RAM or MMC devices.

Also fix some bugs of andes plic driver and improve cache
configurations for SPL.

Changes in v2:
- Remove SYS_NS16550.
- Use CONFIG_IS_ENABLED(RISCV_MMODE).
- Add ALIGN(8) in ld for RV64.
- Add new [PATCH v2 09/10] riscv: dts: Add #address-cells and #size-cells in 
nor node.
- Add new [PATCH v2 10/10] doc: update AX25-AE350 RISC-V documentation.

Rick Chen (10):
  riscv: ax25: add SPL support
  riscv: ax25-ae350: add SPL configuration
  riscv: ax25-ae350: Use generic memory size setup
  riscv: andes_plic: Fix some wrong configurations
  riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
  spl: cache: Allow cache drivers in SPL
  riscv: Fix clear bss loop in the start-up code
  riscv: dts: Support four cores SMP
  riscv: dts: Add #address-cells and #size-cells in nor node
  doc: update AX25-AE350 RISC-V documentation

 arch/riscv/cpu/ax25/Kconfig |   4 +-
 arch/riscv/cpu/ax25/cache.c |  60 ++---
 arch/riscv/cpu/start.S  |   4 +-
 arch/riscv/cpu/u-boot-spl.lds   |   2 +-
 arch/riscv/cpu/u-boot.lds   |   2 +-
 arch/riscv/dts/ae350_32.dts |  61 +-
 arch/riscv/dts/ae350_64.dts |  61 +-
 arch/riscv/lib/andes_plic.c |  11 +-
 board/AndesTech/ax25-ae350/Kconfig  |   9 ++
 board/AndesTech/ax25-ae350/MAINTAINERS  |   4 +
 board/AndesTech/ax25-ae350/ax25-ae350.c |  48 +---
 common/spl/Kconfig  |   7 ++
 configs/ae350_rv32_spl_defconfig|  37 ++
 configs/ae350_rv32_spl_xip_defconfig|  39 ++
 configs/ae350_rv64_spl_defconfig|  38 ++
 configs/ae350_rv64_spl_xip_defconfig|  40 ++
 doc/board/AndesTech/ax25-ae350.rst  | 209 +++-
 drivers/Makefile|   1 +
 include/configs/ax25-ae350.h|  17 +++
 19 files changed, 601 insertions(+), 53 deletions(-)
 create mode 100644 configs/ae350_rv32_spl_defconfig
 create mode 100644 configs/ae350_rv32_spl_xip_defconfig
 create mode 100644 configs/ae350_rv64_spl_defconfig
 create mode 100644 configs/ae350_rv64_spl_xip_defconfig

-- 
2.7.4

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[U-Boot] [PATCH v2 01/10] riscv: ax25: add SPL support

2019-11-13 Thread Andes
From: Rick Chen 

The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.

Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/cpu/ax25/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index d411a79..8d8d71d 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,7 +6,9 @@ config RISCV_NDS
imply RISCV_TIMER
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
-   imply V5L2_CACHE
+   imply SPL_CPU_SUPPORT
+   imply SPL_OPENSBI
+   imply SPL_LOAD_FIT
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
-- 
2.7.4

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[U-Boot] [PATCH 7/8] riscv: Fix clear bss loop in the start-up code

2019-10-25 Thread Andes
From: Rick Chen 

For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/cpu/start.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 0a2ce6d..ee6d471 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -174,7 +174,7 @@ spl_clear_bss:
 spl_clear_bss_loop:
SREGzero, 0(t0)
addit0, t0, REGBYTES
-   bne t0, t1, spl_clear_bss_loop
+   blt t0, t1, spl_clear_bss_loop
 
 spl_stack_gd_setup:
jal spl_relocate_stack_gd
@@ -324,7 +324,7 @@ clear_bss:
 clbss_l:
SREGzero, 0(t0) /* clear loop... */
addit0, t0, REGBYTES
-   bne t0, t1, clbss_l
+   blt t0, t1, clbss_l
 
 relocate_secondary_harts:
 #ifdef CONFIG_SMP
-- 
2.7.4

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[U-Boot] [PATCH 8/8] riscv: dts: Support four cores SMP

2019-10-25 Thread Andes
From: Rick Chen 

Add CPU2 and CPU3 informations in cpus node
to support four cores SMP booting.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/dts/ae350_32.dts | 51 ++---
 arch/riscv/dts/ae350_64.dts | 51 ++---
 2 files changed, 96 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 97b7cee..c794a7f 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,6 +62,48 @@
compatible = "riscv,cpu-intc";
};
};
+   CPU2: cpu@2 {
+   device_type = "cpu";
+   reg = <2>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv32";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = <>;
+   CPU2_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "riscv,cpu-intc";
+   };
+   };
+   CPU3: cpu@3 {
+   device_type = "cpu";
+   reg = <3>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv32";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = <>;
+   CPU3_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "riscv,cpu-intc";
+   };
+   };
};
 
L2: l2-cache@e050 {
@@ -94,7 +136,8 @@
interrupt-controller;
reg = <0xe400 0x200>;
riscv,ndev=<71>;
-   interrupts-extended = <_intc 11 _intc 9 
_intc 11 _intc 9>;
+   interrupts-extended = <_intc 11 _intc 9 
_intc 11 _intc 9
+   
_intc 11 _intc 9 _intc 11 
_intc 9>;
};
 
plic1: interrupt-controller@e640 {
@@ -104,12 +147,14 @@
interrupt-controller;
reg = <0xe640 0x40>;
riscv,ndev=<2>;
-   interrupts-extended = <_intc 3 _intc 3>;
+   interrupts-extended = <_intc 3 _intc 3
+   
_intc 3 _intc 3>;
};
 
plmt0@e600 {
compatible = "riscv,plmt0";
-   interrupts-extended = <_intc 7 _intc 7>;
+   interrupts-extended = <_intc 7 _intc 7
+   
_intc 7 _intc 7>;
reg = <0xe600 0x10>;
};
};
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index d8f00f8..b3d6d15 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,6 +62,48 @@
compatible = "riscv,cpu-intc";
};
};
+   CPU2: cpu@2 {
+   device_type = "cpu";
+   reg = <2>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv64imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv39";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   

[U-Boot] [PATCH 5/8] riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL

2019-10-25 Thread Andes
From: Rick Chen 

The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/cpu/ax25/cache.c | 60 ++---
 1 file changed, 46 insertions(+), 14 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 41de30c..9437e81 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -11,18 +11,46 @@
 #include 
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
 /* mcctlcommand */
 #define CCTL_REG_MCCTLCOMMAND_NUM  0x7cc
 
 /* D-cache operation */
 #define CCTL_L1D_WBINVAL_ALL   6
 #endif
+#endif
+
+#ifdef CONFIG_V5L2_CACHE
+static void _cache_enable(void)
+{
+   struct udevice *dev = NULL;
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_enable(dev);
+}
+
+static void _cache_disable(void)
+{
+   struct udevice *dev = NULL;
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_disable(dev);
+}
+#endif
 
 void flush_dcache_all(void)
 {
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
 #endif
+#endif
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -39,6 +67,7 @@ void icache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x1\n\t"
@@ -46,12 +75,14 @@ void icache_enable(void)
);
 #endif
 #endif
+#endif
 }
 
 void icache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
asm volatile (
"fence.i\n\t"
"csrr t1, mcache_ctl\n\t"
@@ -60,24 +91,23 @@ void icache_disable(void)
);
 #endif
 #endif
+#endif
 }
 
 void dcache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
-   struct udevice *dev = NULL;
-
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
-
-   uclass_find_first_device(UCLASS_CACHE, );
-
-   if (dev)
-   cache_enable(dev);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+   _cache_enable();
+#endif
 #endif
 #endif
 }
@@ -86,19 +116,17 @@ void dcache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
-   struct udevice *dev = NULL;
-
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
-
-   uclass_find_first_device(UCLASS_CACHE, );
-
-   if (dev)
-   cache_disable(dev);
+#endif
+#ifdef CONFIG_V5L2_CACHE
+   _cache_disable();
+#endif
 #endif
 #endif
 }
@@ -108,6 +136,7 @@ int icache_status(void)
int ret = 0;
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi   %0, t1, 0x01\n\t"
@@ -116,6 +145,7 @@ int icache_status(void)
: "memory"
);
 #endif
+#endif
 
return ret;
 }
@@ -125,6 +155,7 @@ int dcache_status(void)
int ret = 0;
 
 #ifdef CONFIG_RISCV_NDS_CACHE
+#if defined(CONFIG_RISCV_MMODE) || defined(CONFIG_SPL_RISCV_MMODE)
asm volatile (
"csrr t1, mcache_ctl\n\t"
"andi   %0, t1, 0x02\n\t"
@@ -133,6 +164,7 @@ int dcache_status(void)
: "memory"
);
 #endif
+#endif
 
return ret;
 }
-- 
2.7.4

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[U-Boot] [PATCH 6/8] spl: cache: Allow cache drivers in SPL

2019-10-25 Thread Andes
From: Rick Chen 

When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 common/spl/Kconfig | 7 +++
 drivers/Makefile   | 1 +
 2 files changed, 8 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 86d7edf..4c4023a 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -456,6 +456,13 @@ config SPL_CRYPTO_SUPPORT
  this option to build the drivers in drivers/crypto as part of an
  SPL build.
 
+config SPL_CACHE_SUPPORT
+   bool "Support CACHE drivers"
+   help
+ Enable CACHE drivers in SPL. These drivers can store data so that
+ future requests for that data can be served faster. Enable this option
+ to build the drivers in drivers/cache as part of an SPL build.
+
 config SPL_HASH_SUPPORT
bool "Support hashing drivers"
select SHA1
diff --git a/drivers/Makefile b/drivers/Makefile
index a4bb5e4..5d300df 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -33,6 +33,7 @@ ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_BOOTCOUNT_LIMIT) += bootcount/
 obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
 obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
+obj-$(CONFIG_SPL_CACHE_SUPPORT) += cache/
 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/
 obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
-- 
2.7.4

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[U-Boot] [PATCH 3/8] riscv: ax25-ae350: Use generic memory size setup

2019-10-25 Thread Andes
From: Rick Chen 

To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSbi.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 21 ++---
 1 file changed, 2 insertions(+), 19 deletions(-)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index b0164a9..47e6929 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -30,29 +30,12 @@ int board_init(void)
 
 int dram_init(void)
 {
-   unsigned long sdram_base = PHYS_SDRAM_0;
-   unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
-   unsigned long actual_size;
-
-   actual_size = get_ram_size((void *)sdram_base, expected_size);
-   gd->ram_size = actual_size;
-
-   if (expected_size != actual_size) {
-   printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
-   actual_size >> 20, expected_size >> 20);
-   }
-
-   return 0;
+   return fdtdec_setup_mem_size_base();
 }
 
 int dram_init_banksize(void)
 {
-   gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
-   gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
-   gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
-   gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
-
-   return 0;
+   return fdtdec_setup_memory_banksize();
 }
 
 #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
-- 
2.7.4

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[U-Boot] [PATCH 4/8] riscv: andes_plic: Fix some wrong configurations

2019-10-25 Thread Andes
From: Rick Chen 

It will work fine due to hart 0 always will be main
hart coincidentally. When develop SPL flow, I try to
force other harts to be main hart. And it will go
wrong in sending IPI flow. So fix it.

Having this fix, any hart can be main hart in U-Boot SPL
theoretically, but it still fail somewhere. After dig in
and found there is an assumption that hart 0 shall be
main hart in OpenSbi.

After some work-arounds, it can pass the verifications
that any hart can be main hart and boots U-Boot SPL ->
OpenSbi -> U-Boot proper -> Linux Kernel successfully.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/lib/andes_plic.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 28568e4..42394b9 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -19,7 +19,7 @@
 #include 
 
 /* pending register */
-#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart) * 8)
+#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart) / 4) 
* 4)
 /* enable register */
 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
 /* claim register */
@@ -46,7 +46,7 @@ static int init_plic(void);
 
 static int enable_ipi(int hart)
 {
-   int en;
+   unsigned int en;
 
en = ENABLE_HART_IPI >> hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
@@ -94,10 +94,13 @@ static int init_plic(void)
 
 int riscv_send_ipi(int hart)
 {
+   unsigned int ipi;
+
PLIC_BASE_GET();
 
-   writel(SEND_IPI_TO_HART(hart),
-  (void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart));
+   ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+   writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
+   gd->arch.boot_hart));
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH 2/8] riscv: ax25-ae350: add SPL configuration

2019-10-25 Thread Andes
From: Rick Chen 

This patch provides four configurations
which can support U-Boot SPL to boot from
RAM or FLASH and then boot FIT image
including OpenSBI FW_DYNAMIC firmware
and U-Boot proper images from RAM or
MMC boot devices.

With ae350_rv[32|64]_spl_defconfigs:

U-Boot SPL will be loaded by gdb or FSBL
and runs in RAM in machine mode and then
load FIT image from RAM device on AE350.

With ae350_rv[32|64]_spl_xip_defconfigs:

U-Boot SPL can be burned into SPI flash
and run in flash in machine mode and then
load FIT image from SPI flash or MMC device
on AE350.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 board/AndesTech/ax25-ae350/Kconfig  | 10 +
 board/AndesTech/ax25-ae350/MAINTAINERS  |  4 
 board/AndesTech/ax25-ae350/ax25-ae350.c | 27 ++
 configs/ae350_rv32_spl_defconfig| 37 ++
 configs/ae350_rv32_spl_xip_defconfig| 39 
 configs/ae350_rv64_spl_defconfig| 38 +++
 configs/ae350_rv64_spl_xip_defconfig| 40 +
 include/configs/ax25-ae350.h| 17 ++
 8 files changed, 212 insertions(+)
 create mode 100644 configs/ae350_rv32_spl_defconfig
 create mode 100644 configs/ae350_rv32_spl_xip_defconfig
 create mode 100644 configs/ae350_rv64_spl_defconfig
 create mode 100644 configs/ae350_rv64_spl_xip_defconfig

diff --git a/board/AndesTech/ax25-ae350/Kconfig 
b/board/AndesTech/ax25-ae350/Kconfig
index 5e682b6..2e1e2bb 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -21,9 +21,19 @@ config ENV_SIZE
 config ENV_OFFSET
default 0x14 if ENV_IS_IN_SPI_FLASH
 
+config SPL_TEXT_BASE
+   default 0x
+
+config SPL_OPENSBI_LOAD_ADDR
+   default 0x0100
+
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
+   select SUPPORT_SPL
+   imply SYS_NS16550
imply SMP
+   imply SPL_RAM_SUPPORT
+   imply SPL_RAM_DEVICE
 
 endif
diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS 
b/board/AndesTech/ax25-ae350/MAINTAINERS
index feed5d1..eebee16 100644
--- a/board/AndesTech/ax25-ae350/MAINTAINERS
+++ b/board/AndesTech/ax25-ae350/MAINTAINERS
@@ -7,3 +7,7 @@ F:  configs/ae350_rv32_defconfig
 F: configs/ae350_rv64_defconfig
 F: configs/ae350_rv32_xip_defconfig
 F: configs/ae350_rv64_xip_defconfig
+F: configs/ae350_rv32_spl_defconfig
+F: configs/ae350_rv64_spl_defconfig
+F: configs/ae350_rv32_spl_xip_defconfig
+F: configs/ae350_rv64_spl_xip_defconfig
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index b43eebb..b0164a9 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -110,3 +111,29 @@ int board_early_init_f(void)
return 0;
 }
 #endif
+
+#ifdef CONFIG_SPL
+void board_boot_order(u32 *spl_boot_list)
+{
+   u8 i;
+   u32 boot_devices[] = {
+#ifdef CONFIG_SPL_RAM_SUPPORT
+   BOOT_DEVICE_RAM,
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+   BOOT_DEVICE_MMC1,
+#endif
+   };
+
+   for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
+   spl_boot_list[i] = boot_devices[i];
+}
+#endif
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+   /* boot using first FIT config */
+   return 0;
+}
+#endif
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
new file mode 100644
index 000..53055b7
--- /dev/null
+++ b/configs/ae350_rv32_spl_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_SPL=y
+CONFIG_RISCV_SMODE=y
+CONFIG_SYS_TEXT_BASE=0x0120
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_PRIOR_STAGE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig 
b/configs/ae350_rv32_spl_xip_defconfig
new file mode 100644
index 000..fdbab43
--- /dev/null
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -0,0 +1,39 @@
+CONFIG_RISCV=y
+CONFIG_SPL=y
+CONFIG_RISCV_SMODE=y
+CONFIG_SPL_TEXT_BASE=0x8000
+CONFIG_SYS_TEXT_BASE=0x0120
+CONFIG_NR_DRAM_BANKS=2

[U-Boot] [PATCH 1/8] riscv: ax25: add SPL support

2019-10-25 Thread Andes
From: Rick Chen 

The U-Boot SPL will boot in M mode and load the
FIT image which include OpenSbi and U-Boot proper
images. After loading progress, it will jump to
OpenSbi first and then U-Boot proper which will
run in S mode.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Cc: Alan Kao 
---
 arch/riscv/cpu/ax25/Kconfig | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index d411a79..8d8d71d 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,7 +6,9 @@ config RISCV_NDS
imply RISCV_TIMER
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
-   imply V5L2_CACHE
+   imply SPL_CPU_SUPPORT
+   imply SPL_OPENSBI
+   imply SPL_LOAD_FIT
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
-- 
2.7.4

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[U-Boot] [PATCH 0/8] RISC-V AX25-AE350 support SPL

2019-10-25 Thread Andes
From: Rick Chen 

This series add support for SPL to AX25-AE350.

U-Boot SPL can boots from RAM or ROM and jump to
OPenSbi(FW_DYNAMIC firmware) and U-Boot proper from
RAM or MMC devices.

Also fix some bugs for andes plic driver and improve cache
configurations for SPL.

Following are the booting messages on AE350 four cores SMP platform:

U-Boot 2019.10-00602-g693b70f (Oct 23 2019 - 16:32:19 +0800)

DRAM:  1 GiB

U-Boot SPL 2019.10-00601-g04f8f09-dirty (Oct 24 2019 - 10:46:49 +0800)
Trying to boot from RAM

OpenSBI v0.4-32-g98ee15c (Sep 17 2019 10:41:30)
   _  _
  / __ \  / |  _ \_   _|
 | |  | |_ __   ___ _ __ | (___ | |_) || |
 | |  | | '_ \ / _ \ '_ \ \___ \|  _ < | |
 | |__| | |_) |  __/ | | |) | |_) || |_
  \/| .__/ \___|_| |_|_/|/_|
| |
|_|

Platform Name  : Andes AE350
Platform HART Features : RV64ACIMSUX
Platform Max HARTs : 4
Current Hart   : 0
Firmware Base  : 0x0
Firmware Size  : 80 KB
Runtime SBI Version: 0.1

PMP0: 0x-0x0001 (A)
PMP1: 0x-0x0001 (A,R,W,X)


U-Boot 2019.10-00601-g04f8f09-dirty (Oct 24 2019 - 10:46:49 +0800)

DRAM:  1 GiB
Flash: 64 MiB
MMC:   mmc@f0e0: 0
Loading Environment from SPI Flash... SF: Detected mx25u1635e with page size 
256 Bytes, erase size 4 KiB, total 2 MiB
OK
In:serial@f030
Out:   serial@f030
Err:   serial@f030
Net:   no alias for ethernet0

Warning: mac@e010 (eth0) using random MAC address - 06:2b:40:2d:38:d1
eth0: mac@e010
Hit any key to stop autoboot:  0
6455 bytes read in 30 ms (210 KiB/s)
20421684 bytes read in 8614 ms (2.3 MiB/s)
## Booting kernel from Legacy Image at 0060 ...
   Image Name:
   Image Type:   RISC-V Linux Kernel Image (uncompressed)
   Data Size:20421620 Bytes = 19.5 MiB
   Load Address: 0020
   Entry Point:  0020
   Verifying Checksum ... OK
## Flattened Device Tree blob at 2000
   Booting using the fdt blob at 0x2000
   Loading Kernel Image
   Loading Device Tree to 1effb000, end 1efff936 ... OK

Starting kernel ...

OF: fdt: Ignoring memory range 0x0 - 0x20
Linux version 4.17.0-00253-g49136e10bcb2 (sqa@atcsqa07) (gcc version 7.3.0 
(2019-04-06_nds64le-linux-glibc-v5_experimental)) #1 SMP PREEMPT Sat Apr 6 
23:41:49 CST 2019
bootconsole [early0] enabled
Initial ramdisk at: 0x(ptrval) (13665712 bytes)
Zone ranges:
  DMA32[mem 0x0020-0x3fff]
  Normal   empty
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x0020-0x3fff]
Initmem setup node 0 [mem 0x0020-0x3fff]
software IO TLB [mem 0x3b1f8000-0x3f1f8000] (64MB) mapped at [(ptrval)- 
   (ptrval)]
elf_platform is rv64i2p0m2p0a2p0c2p0xv5-0p0
compatible privileged spec version 1.10
percpu: Embedded 16 pages/cpu @(ptrval) s28184 r8192 d29160 u65536
Built 1 zonelists, mobility grouping on.  Total pages: 258055
Kernel command line: console=ttyS0,38400n8 debug loglevel=7
log_buf_len individual max cpu contribution: 4096 bytes
log_buf_len total cpu_extra contributions: 12288 bytes
log_buf_len min size: 16384 bytes
log_buf_len: 32768 bytes
early log buf free: 14608(89%)
Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
Inode-cache hash table entries: 65536 (order: 7, 524288 bytes)
Sorting __ex_table...
Memory: 944428K/1046528K available (3979K kernel code, 246K rwdata, 1490K 
rodata, 13523K init, 688K bss, 102100K reserved, 0K cma-reserved)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
Preemptible hierarchical RCU implementation.
Tasks RCU enabled.
NR_IRQS: 72, nr_irqs: 72, preallocated irqs: 0
riscv,cpu_intc,0: 64 local interrupts mapped
riscv,cpu_intc,1: 64 local interrupts mapped
riscv,cpu_intc,2: 64 local interrupts mapped
riscv,cpu_intc,3: 64 local interrupts mapped
riscv,plic0,e400: mapped 71 interrupts to 8/8 handlers
clocksource: riscv_clocksource: mask: 0x max_cycles: 
0x1bacf917bf, max_idle_ns: 881590412290 ns
sched_clock: 64 bits at 60MHz, resolution 16ns, wraps every 4398046511098ns
Console: colour dummy device 40x30
Calibrating delay loop (skipped), value calculated using timer frequency.. 
120.00 BogoMIPS (lpj=60)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 2048 (order: 2, 16384 bytes)
Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes)
Hierarchical SRCU implementation.
smp: Bringing up secondary CPUs ...
CPU0: online
CPU2: online
CPU3: online
smp: Brought up 1 node, 4 CPUs
...
...
...

Rick Chen (8):
  riscv: ax25: add SPL support
  riscv: ax25-ae350: add SPL configuration
  riscv: ax25-ae350: Use generic memory size setup
  riscv: andes_plic: Fix some wrong configurations
  riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
  spl: cache: Allow cache drivers in SPL
  riscv: Fix clear bss loop in the start

[U-Boot] [PATCH v4 8/8] riscv: cache: use CCTL to flush d-cache

2019-08-28 Thread Andes
From: Rick Chen 

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/ax25/cache.c | 22 +-
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 8f5455e..41de30c 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -8,17 +8,21 @@
 #include 
 #include 
 #include 
+#include 
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM  0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL   6
+#endif
 
 void flush_dcache_all(void)
 {
-   /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-* The implementation of the fence instruction in the AX25 flushes the
-* data cache and is used for this purpose.
-*/
-   asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -84,8 +88,8 @@ void dcache_disable(void)
 #ifdef CONFIG_RISCV_NDS_CACHE
struct udevice *dev = NULL;
 
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
-   "fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
-- 
2.7.4

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[U-Boot] [PATCH v4 4/8] riscv: ae350: use the v5l2 driver to configure the cache

2019-08-28 Thread Andes
From: Rick Chen 

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7..b43eebb 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,10 +94,18 @@ int smc_init(void)
return 0;
 }
 
+static void v5l2_init(void)
+{
+   struct udevice *dev;
+
+   uclass_get_device(UCLASS_CACHE, 0, );
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
smc_init();
+   v5l2_init();
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v4 7/8] riscv: dts: move out AE350 L2 node from cpus node

2019-08-28 Thread Andes
From: Rick Chen 

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 arch/riscv/dts/ae350_32.dts | 17 +++--
 arch/riscv/dts/ae350_64.dts | 17 +++--
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..97b7cee 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "v5l2cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0xe050 0x40000>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   /* The value format is  */
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..d8f00f8 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "v5l2cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x4>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   /* The value format is  */
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
-- 
2.7.4

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[U-Boot] [PATCH v4 5/8] riscv: ax25: add imply v5l2 cache controller

2019-08-28 Thread Andes
From: Rick Chen 

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..49be775 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,6 +4,7 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
+   imply V5L2_CACHE
imply ANDES_PLIC if RISCV_MMODE
imply ANDES_PLMT if RISCV_MMODE
help
-- 
2.7.4

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[U-Boot] [PATCH v4 6/8] riscv: cache: Flush L2 cache before jump to linux

2019-08-28 Thread Andes
From: Rick Chen 

Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/ax25/cache.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index cd95058..8f5455e 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,6 +5,9 @@
  */
 
 #include 
+#include 
+#include 
+#include 
 
 void flush_dcache_all(void)
 {
@@ -59,11 +62,18 @@ void dcache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+   struct udevice *dev = NULL;
+
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_enable(dev);
 #endif
 #endif
 }
@@ -72,12 +82,19 @@ void dcache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+   struct udevice *dev = NULL;
+
asm volatile (
"fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_disable(dev);
 #endif
 #endif
 }
-- 
2.7.4

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[U-Boot] [PATCH v4 2/8] dm: cache: Add enable and disable ops for sandbox and test

2019-08-28 Thread Andes
From: Rick Chen 

Add cache enable and disable ops for test coverage.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 drivers/cache/sandbox_cache.c | 13 +
 test/dm/cache.c   |  2 ++
 2 files changed, 15 insertions(+)

diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
index 14cc6b0..9050c4c 100644
--- a/drivers/cache/sandbox_cache.c
+++ b/drivers/cache/sandbox_cache.c
@@ -17,8 +17,21 @@ static int sandbox_get_info(struct udevice *dev, struct 
cache_info *info)
return 0;
 }
 
+static int sandbox_enable(struct udevice *dev)
+{
+   return 0;
+}
+
+static int snadbox_disable(struct udevice *dev)
+{
+   return 0;
+}
+
+
 static const struct cache_ops sandbox_cache_ops = {
.get_info   = sandbox_get_info,
+   .enable = sandbox_enable,
+   .disable= snadbox_disable,
 };
 
 static const struct udevice_id sandbox_cache_ids[] = {
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d4144aa..2e244b1 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -14,6 +14,8 @@ static int dm_test_reset(struct unit_test_state *uts)
 
ut_assertok(uclass_get_device(UCLASS_CACHE, 0, _cache));
ut_assertok(cache_get_info(dev, ));
+   ut_assertok(cache_enable(dev));
+   ut_assertok(cache_disable(dev));
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v4 3/8] dm: cache: add v5l2 cache controller driver

2019-08-28 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 drivers/cache/Kconfig  |   9 +++
 drivers/cache/Makefile |   1 +
 drivers/cache/cache-v5l2.c | 186 +
 3 files changed, 196 insertions(+)
 create mode 100644 drivers/cache/cache-v5l2.c

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..629039e 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@ config L2X0_CACHE
  ARMv7(32-bit) devices. The driver configures the cache settings
  found in the device tree.
 
+config V5L2_CACHE
+   bool "Andes V5L2 cache driver"
+   select CACHE
+   depends on RISCV_NDS_CACHE
+   help
+     Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 000..d367171
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct l2cache {
+   volatile u64configure;
+   volatile u64control;
+   volatile u64hpm0;
+   volatile u64hpm1;
+   volatile u64hpm2;
+   volatile u64hpm3;
+   volatile u64error_status;
+   volatile u64ecc_error;
+   volatile u64cctl_command0;
+   volatile u64cctl_access_line0;
+   volatile u64cctl_command1;
+   volatile u64cctl_access_line1;
+   volatile u64cctl_command2;
+   volatile u64cctl_access_line2;
+   volatile u64cctl_command3;
+   volatile u64cctl_access_line4;
+   volatile u64cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE  0x1
+/* prefetch */
+#define IPREPETCH_OFF  3
+#define DPREPETCH_OFF  5
+#define IPREPETCH_MSK  (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK  (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF   8
+#define TRAMICTL_OFF   10
+#define TRAMOCTL_MSK   (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK   BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF   11
+#define DRAMICTL_OFF   13
+#define DRAMOCTL_MSK   (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK   BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart)   ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart)  (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart)  (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart)  (2 << ((hart) * 4))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+   struct l2cache  *regs;
+   u32 iprefetch;
+   u32 dprefetch;
+   u32 tram_ctl[2];
+   u32 dram_ctl[2];
+};
+
+static int v5l2_enable(struct udevice *dev)
+{
+   struct v5l2_plat *plat = dev_get_platdata(dev);
+   volatile struct l2cache *regs = plat->regs;
+
+   if (regs)
+   setbits_le32(>control, L2_ENABLE);
+
+   return 0;
+}
+
+static int v5l2_disable(struct udevice *dev)
+{
+   struct v5l2_plat *plat = dev_get_platdata(dev);
+   volatile struct l2cache *regs = plat->regs;
+   u8 hart = gd->arch.boot_hart;
+   void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+   if ((regs) && (readl(>control) & L2_ENABLE)) {
+   writel(L2_WBINVAL_ALL, cctlcmd);
+
+   while ((readl(>cctl_status) & CCTL_STATUS_MSK(hart))) {
+   if ((readl(>cctl_status) & 
CCTL_STATUS_ILLEGAL(hart))) {
+   printf("L2 flush illegal! hanging...");
+   hang();
+   }
+   }
+   clrbits_le32(>control, L2_ENABLE);
+   }
+
+   return 0;
+}
+
+static int v5l2_ofdata_to_platdata(struct udevice *dev)
+{
+   struct v5l2_plat *plat = dev_get_platdata(dev);
+   struct l2cache *regs;
+
+   regs = (struct l2cache *)dev_r

[U-Boot] [PATCH v4 0/8] Support Andes RISC-V l2cache on AE350 platform

2019-08-28 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.

Also implement L2 cache flush and disable before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Changes in v4:
- Remove definitions of v5l2cache.h to cache-v5l2.c

Changes in v3:
- Add the enable/disable in sandbox_cache.c.
- Parse dtb data in v5l2_ofdata_to_platdata() and configure HW in v5l2_probe().
- Move cache_disable() into dcache_disable() of cache.c

Changes in v2:
- Add new patch [1/7] to support dm cache uclass enable and disable ops.
- Use ofdata_to_platdata() to parse and save register base instead of global 
data.
- Rename compatible string of "cache" as "v5l2cache".
- make v512_init() return void.
- Use dm cache uclass api to disable L2 cache.

Rick Chen (8):
  dm: cache: Add enable and disable ops for cache uclass
  dm: cache: Add enable and disable ops for sandbox and test
  dm: cache: add v5l2 cache controller driver
  riscv: ae350: use the v5l2 driver to configure the cache
  riscv: ax25: add imply v5l2 cache controller
  riscv: cache: Flush L2 cache before jump to linux
  riscv: dts: move out AE350 L2 node from cpus node
  riscv: cache: use CCTL to flush d-cache

 arch/riscv/cpu/ax25/Kconfig |   1 +
 arch/riscv/cpu/ax25/cache.c |  39 +--
 arch/riscv/dts/ae350_32.dts |  17 +--
 arch/riscv/dts/ae350_64.dts |  17 +--
 board/AndesTech/ax25-ae350/ax25-ae350.c |   9 ++
 drivers/cache/Kconfig   |   9 ++
 drivers/cache/Makefile  |   1 +
 drivers/cache/cache-uclass.c|  20 
 drivers/cache/cache-v5l2.c  | 186 
 drivers/cache/sandbox_cache.c   |  13 +++
 include/cache.h |  31 ++
 test/dm/cache.c |   2 +
 12 files changed, 324 insertions(+), 21 deletions(-)
 create mode 100644 drivers/cache/cache-v5l2.c

-- 
2.7.4

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[U-Boot] [PATCH v4 1/8] dm: cache: Add enable and disable ops for cache uclass

2019-08-28 Thread Andes
From: Rick Chen 

Add cache enable/disable ops to the DM cache uclass driver

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 drivers/cache/cache-uclass.c | 20 
 include/cache.h  | 31 +++
 2 files changed, 51 insertions(+)

diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 97ce024..3b20a10 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info 
*info)
return ops->get_info(dev, info);
 }
 
+int cache_enable(struct udevice *dev)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->enable)
+   return -ENOSYS;
+
+   return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->disable)
+   return -ENOSYS;
+
+   return ops->disable(dev);
+}
+
 UCLASS_DRIVER(cache) = {
.id = UCLASS_CACHE,
.name   = "cache",
diff --git a/include/cache.h b/include/cache.h
index c6334ca..32f59fd 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -22,6 +22,22 @@ struct cache_ops {
 * @return 0 if OK, -ve on error
 */
int (*get_info)(struct udevice *dev, struct cache_info *info);
+
+   /**
+* enable() - Enable cache
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @return 0 if OK, -ve on error
+*/
+   int (*enable)(struct udevice *dev);
+
+   /**
+* disable() - Flush and disable cache
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @return 0 if OK, -ve on error
+*/
+   int (*disable)(struct udevice *dev);
 };
 
 #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
@@ -35,4 +51,19 @@ struct cache_ops {
  */
 int cache_get_info(struct udevice *dev, struct cache_info *info);
 
+/**
+ * cache_enable() - Enable cache
+ *
+ * @dev:   Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_enable(struct udevice *dev);
+
+/**
+ * cache_disable() - Flush and disable cache
+ *
+ * @dev:   Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_disable(struct udevice *dev);
 #endif
-- 
2.7.4

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[U-Boot] [PATCH] riscv: andes_plic: init plic by scanning each cpu node

2019-08-22 Thread Andes
From: Rick Chen 

Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().

This way can support to skip some harts which maybe mark as
unavailable, but the cpu node exist indeed.

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 arch/riscv/lib/andes_plic.c | 36 +---
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 2ffe49a..28568e4 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -44,15 +44,12 @@ static int init_plic(void);
}   \
} while (0)
 
-static int enable_ipi(int harts)
+static int enable_ipi(int hart)
 {
-   int i;
-   int en = ENABLE_HART_IPI;
+   int en;
 
-   for (i = 0; i < harts; i++) {
-   en = en >> i;
-   writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
-   }
+   en = ENABLE_HART_IPI >> hart;
+   writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
 
return 0;
 }
@@ -60,18 +57,35 @@ static int enable_ipi(int harts)
 static int init_plic(void)
 {
struct udevice *dev;
+   ofnode node;
int ret;
+   u32 reg;
 
ret = uclass_find_first_device(UCLASS_CPU, );
if (ret)
return ret;
 
if (ret == 0 && dev) {
-   ret = cpu_get_count(dev);
-   if (ret < 0)
-   return ret;
+   ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+   const char *device_type;
+
+   device_type = ofnode_read_string(node, "device_type");
+   if (!device_type)
+   continue;
+
+   if (strcmp(device_type, "cpu"))
+   continue;
+
+   /* skip if hart is marked as not available */
+   if (!ofnode_is_available(node))
+   continue;
+
+   /* read hart ID of CPU */
+   ret = ofnode_read_u32(node, "reg", );
+   if (ret == 0)
+   enable_ipi(reg);
+   }
 
-   enable_ipi(ret);
return 0;
}
 
-- 
2.7.4

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[U-Boot] [PATCH 1/3] riscv: andes_plic: init plic by scanning each cpu node

2019-08-21 Thread Andes
From: Rick Chen 

Initialize plic driver by ofnode_for_each_subnode() instead
of cpu_get_count().

This way can support to skip some harts which maybe mark as
unavailable, but the cpu node exist indeed.

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 arch/riscv/lib/andes_plic.c | 36 +---
 1 file changed, 25 insertions(+), 11 deletions(-)

diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
index 2ffe49a..28568e4 100644
--- a/arch/riscv/lib/andes_plic.c
+++ b/arch/riscv/lib/andes_plic.c
@@ -44,15 +44,12 @@ static int init_plic(void);
}   \
} while (0)
 
-static int enable_ipi(int harts)
+static int enable_ipi(int hart)
 {
-   int i;
-   int en = ENABLE_HART_IPI;
+   int en;
 
-   for (i = 0; i < harts; i++) {
-   en = en >> i;
-   writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
-   }
+   en = ENABLE_HART_IPI >> hart;
+   writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart));
 
return 0;
 }
@@ -60,18 +57,35 @@ static int enable_ipi(int harts)
 static int init_plic(void)
 {
struct udevice *dev;
+   ofnode node;
int ret;
+   u32 reg;
 
ret = uclass_find_first_device(UCLASS_CPU, );
if (ret)
return ret;
 
if (ret == 0 && dev) {
-   ret = cpu_get_count(dev);
-   if (ret < 0)
-   return ret;
+   ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+   const char *device_type;
+
+   device_type = ofnode_read_string(node, "device_type");
+   if (!device_type)
+   continue;
+
+   if (strcmp(device_type, "cpu"))
+   continue;
+
+   /* skip if hart is marked as not available */
+   if (!ofnode_is_available(node))
+   continue;
+
+   /* read hart ID of CPU */
+   ret = ofnode_read_u32(node, "reg", );
+   if (ret == 0)
+   enable_ipi(reg);
+   }
 
-   enable_ipi(ret);
return 0;
}
 
-- 
2.7.4

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[U-Boot] [PATCH v3 4/8] riscv: ae350: use the v5l2 driver to configure the cache

2019-08-21 Thread Andes
From: Rick Chen 

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7..b43eebb 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,10 +94,18 @@ int smc_init(void)
return 0;
 }
 
+static void v5l2_init(void)
+{
+   struct udevice *dev;
+
+   uclass_get_device(UCLASS_CACHE, 0, );
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
smc_init();
+   v5l2_init();
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v3 8/8] riscv: cache: use CCTL to flush d-cache

2019-08-21 Thread Andes
From: Rick Chen 

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/ax25/cache.c | 22 +-
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 8f5455e..41de30c 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -8,17 +8,21 @@
 #include 
 #include 
 #include 
+#include 
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM  0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL   6
+#endif
 
 void flush_dcache_all(void)
 {
-   /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-* The implementation of the fence instruction in the AX25 flushes the
-* data cache and is used for this purpose.
-*/
-   asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -84,8 +88,8 @@ void dcache_disable(void)
 #ifdef CONFIG_RISCV_NDS_CACHE
struct udevice *dev = NULL;
 
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
-   "fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
-- 
2.7.4

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[U-Boot] [PATCH v3 6/8] riscv: cache: Flush L2 cache before jump to linux

2019-08-21 Thread Andes
From: Rick Chen 

Flush and disable L2 cache in dcache_disable()
which will be called in cleanup_before_linux()
before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 arch/riscv/cpu/ax25/cache.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index cd95058..8f5455e 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,6 +5,9 @@
  */
 
 #include 
+#include 
+#include 
+#include 
 
 void flush_dcache_all(void)
 {
@@ -59,11 +62,18 @@ void dcache_enable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+   struct udevice *dev = NULL;
+
asm volatile (
"csrr t1, mcache_ctl\n\t"
"ori t0, t1, 0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_enable(dev);
 #endif
 #endif
 }
@@ -72,12 +82,19 @@ void dcache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+   struct udevice *dev = NULL;
+
asm volatile (
"fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
);
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_disable(dev);
 #endif
 #endif
 }
-- 
2.7.4

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[U-Boot] [PATCH v3 7/8] riscv: dts: move out AE350 L2 node from cpus node

2019-08-21 Thread Andes
From: Rick Chen 

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 arch/riscv/dts/ae350_32.dts | 17 +++--
 arch/riscv/dts/ae350_64.dts | 17 +++--
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..97b7cee 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "v5l2cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0xe050 0x40000>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   /* The value format is  */
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..d8f00f8 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "v5l2cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x4>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   /* The value format is  */
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
-- 
2.7.4

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[U-Boot] [PATCH v3 5/8] riscv: ax25: add imply v5l2 cache controller

2019-08-21 Thread Andes
From: Rick Chen 

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen 
Cc: KC Lin 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..49be775 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,6 +4,7 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
+   imply V5L2_CACHE
imply ANDES_PLIC if RISCV_MMODE
imply ANDES_PLMT if RISCV_MMODE
help
-- 
2.7.4

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[U-Boot] [PATCH v3 2/8] dm: cache: Add enable and disable ops for sandbox and test

2019-08-21 Thread Andes
From: Rick Chen 

Add L2 cache enable and disable ops for test coverage.

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 drivers/cache/sandbox_cache.c | 13 +
 test/dm/cache.c   |  2 ++
 2 files changed, 15 insertions(+)

diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c
index 14cc6b0..9050c4c 100644
--- a/drivers/cache/sandbox_cache.c
+++ b/drivers/cache/sandbox_cache.c
@@ -17,8 +17,21 @@ static int sandbox_get_info(struct udevice *dev, struct 
cache_info *info)
return 0;
 }
 
+static int sandbox_enable(struct udevice *dev)
+{
+   return 0;
+}
+
+static int snadbox_disable(struct udevice *dev)
+{
+   return 0;
+}
+
+
 static const struct cache_ops sandbox_cache_ops = {
.get_info   = sandbox_get_info,
+   .enable = sandbox_enable,
+   .disable= snadbox_disable,
 };
 
 static const struct udevice_id sandbox_cache_ids[] = {
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d4144aa..2e244b1 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -14,6 +14,8 @@ static int dm_test_reset(struct unit_test_state *uts)
 
ut_assertok(uclass_get_device(UCLASS_CACHE, 0, _cache));
ut_assertok(cache_get_info(dev, ));
+   ut_assertok(cache_enable(dev));
+   ut_assertok(cache_disable(dev));
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v3 3/8] dm: cache: add v5l2 cache controller driver

2019-08-21 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 arch/riscv/include/asm/v5l2cache.h |  58 
 drivers/cache/Kconfig  |   9 +++
 drivers/cache/Makefile |   1 +
 drivers/cache/cache-v5l2.c | 139 +
 4 files changed, 207 insertions(+)
 create mode 100644 arch/riscv/include/asm/v5l2cache.h
 create mode 100644 drivers/cache/cache-v5l2.c

diff --git a/arch/riscv/include/asm/v5l2cache.h 
b/arch/riscv/include/asm/v5l2cache.h
new file mode 100644
index 000..28e40f8
--- /dev/null
+++ b/arch/riscv/include/asm/v5l2cache.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ */
+
+#ifndef _ASM_V5_L2CACHE_H
+#define _ASM_V5_L2CACHE_H
+
+struct l2cache {
+   volatile u64configure;
+   volatile u64control;
+   volatile u64hpm0;
+   volatile u64hpm1;
+   volatile u64hpm2;
+   volatile u64hpm3;
+   volatile u64error_status;
+   volatile u64ecc_error;
+   volatile u64cctl_command0;
+   volatile u64cctl_access_line0;
+   volatile u64cctl_command1;
+   volatile u64cctl_access_line1;
+   volatile u64cctl_command2;
+   volatile u64cctl_access_line2;
+   volatile u64cctl_command3;
+   volatile u64cctl_access_line4;
+   volatile u64cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE  0x1
+/* prefetch */
+#define IPREPETCH_OFF  3
+#define DPREPETCH_OFF  5
+#define IPREPETCH_MSK  (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK  (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF   8
+#define TRAMICTL_OFF   10
+#define TRAMOCTL_MSK   (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK   BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF   11
+#define DRAMICTL_OFF   13
+#define DRAMOCTL_MSK   (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK   BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart)   ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart)  (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart)  (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart)  (2 << ((hart) * 4))
+
+#endif /* _ASM_V5_L2CACHE_H */
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..629039e 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@ config L2X0_CACHE
  ARMv7(32-bit) devices. The driver configures the cache settings
  found in the device tree.
 
+config V5L2_CACHE
+   bool "Andes V5L2 cache driver"
+   select CACHE
+   depends on RISCV_NDS_CACHE
+   help
+ Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 000..a2420e2
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+   struct l2cache  *regs;
+   u32 iprefetch;
+   u32 dprefetch;
+   u32 tram_ctl[2];
+   u32 dram_ctl[2];
+};
+
+static int v5l2_enable(struct udevice *dev)
+{
+   struct v5l2_plat *plat = dev_get_platdata(dev);
+   volatile struct l2cache *regs = plat->regs;
+
+   if (regs)
+   setbits_le32(>control, L2_ENABLE);
+
+   return 0;
+}
+
+static int v5l2_disable(struct udevice *dev)
+{
+   struct v5l2_plat *plat = dev_get_platdata(dev);
+   volatile struct l2cache *regs = plat->regs;
+   u8 hart = gd->arch.boot_hart;
+   void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+   if ((regs) && (readl(>control) & L2_ENABLE)) {
+   writel(L2_WBINVAL_ALL, cctlcmd);
+
+   while

[U-Boot] [PATCH v3 1/8] dm: cache: Add enable and disable ops for cache uclass

2019-08-21 Thread Andes
From: Rick Chen 

The L2 cache will be enabled in init flow of dm cache
driver when it detect L2 node in dtb.

When U-Boot jumps to Linux Kernel, the disable ops will
be called to flush and disable the L2 cache via the dm
cache driver.

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 drivers/cache/cache-uclass.c | 20 
 include/cache.h  | 31 +++
 2 files changed, 51 insertions(+)

diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 97ce024..3b20a10 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info 
*info)
return ops->get_info(dev, info);
 }
 
+int cache_enable(struct udevice *dev)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->enable)
+   return -ENOSYS;
+
+   return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->disable)
+   return -ENOSYS;
+
+   return ops->disable(dev);
+}
+
 UCLASS_DRIVER(cache) = {
.id = UCLASS_CACHE,
.name   = "cache",
diff --git a/include/cache.h b/include/cache.h
index c6334ca..32f59fd 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -22,6 +22,22 @@ struct cache_ops {
 * @return 0 if OK, -ve on error
 */
int (*get_info)(struct udevice *dev, struct cache_info *info);
+
+   /**
+* enable() - Enable cache
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @return 0 if OK, -ve on error
+*/
+   int (*enable)(struct udevice *dev);
+
+   /**
+* disable() - Flush and disable cache
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @return 0 if OK, -ve on error
+*/
+   int (*disable)(struct udevice *dev);
 };
 
 #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
@@ -35,4 +51,19 @@ struct cache_ops {
  */
 int cache_get_info(struct udevice *dev, struct cache_info *info);
 
+/**
+ * cache_enable() - Enable cache
+ *
+ * @dev:   Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_enable(struct udevice *dev);
+
+/**
+ * cache_disable() - Flush and disable cache
+ *
+ * @dev:   Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_disable(struct udevice *dev);
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v3 0/8] Support Andes RISC-V l2cache on AE350 platform

2019-08-21 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.

Also implement L2 cache flush and disable before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Changes in v3:
- Add the enable/disable in sandbox_cache.c.
- Parse dtb data in v5l2_ofdata_to_platdata() and configure HW in v5l2_probe().
- Move cache_disable() into dcache_disable() of cache.c

Changes in v2:
- Add new patch [1/7] to support dm cache uclass enable and disable ops.
- Use ofdata_to_platdata() to parse and save register base instead of global 
data.
- Rename compatible string of "cache" as "v5l2cache".
- make v512_init() return void.
- Use dm cache uclass api to disable L2 cache.

Rick Chen (8):
  dm: cache: Add enable and disable ops for cache uclass
  dm: cache: Add enable and disable ops for sandbox and test
  dm: cache: add v5l2 cache controller driver
  riscv: ae350: use the v5l2 driver to configure the cache
  riscv: ax25: add imply v5l2 cache controller
  riscv: cache: Flush L2 cache before jump to linux
  riscv: dts: move out AE350 L2 node from cpus node
  riscv: cache: use CCTL to flush d-cache

 arch/riscv/cpu/ax25/Kconfig |   1 +
 arch/riscv/cpu/ax25/cache.c |  39 ++---
 arch/riscv/dts/ae350_32.dts |  17 ++--
 arch/riscv/dts/ae350_64.dts |  17 ++--
 arch/riscv/include/asm/v5l2cache.h  |  58 +
 board/AndesTech/ax25-ae350/ax25-ae350.c |   9 +++
 drivers/cache/Kconfig   |   9 +++
 drivers/cache/Makefile  |   1 +
 drivers/cache/cache-uclass.c|  20 +
 drivers/cache/cache-v5l2.c  | 139 
 drivers/cache/sandbox_cache.c   |  13 +++
 include/cache.h |  31 +++
 test/dm/cache.c |   2 +
 13 files changed, 335 insertions(+), 21 deletions(-)
 create mode 100644 arch/riscv/include/asm/v5l2cache.h
 create mode 100644 drivers/cache/cache-v5l2.c

-- 
2.7.4

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[U-Boot] [PATCH v2 5/7] riscv: cache: Flush L2 cache before jump to linux

2019-07-09 Thread Andes
From: Rick Chen 

Flush and disable cache in cleanup_before_linux()
which will be called before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Cc: KC Lin 
---
 arch/riscv/cpu/ax25/cpu.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index 76689b2..31a714e 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -7,6 +7,29 @@
 /* CPU specific code */
 #include 
 #include 
+#include 
+#include 
+#include 
+
+void enable_v5l2(void)
+{
+   struct udevice *dev = NULL;
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_enable(dev);
+}
+
+void disable_v5l2(void)
+{
+   struct udevice *dev = NULL;
+
+   uclass_find_first_device(UCLASS_CACHE, );
+
+   if (dev)
+   cache_disable(dev);
+}
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -22,6 +45,9 @@ int cleanup_before_linux(void)
cache_flush();
icache_disable();
dcache_disable();
+#ifdef CONFIG_RISCV_NDS_CACHE
+   disable_v5l2();
+#endif
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v2 7/7] riscv: ax25: use CCTL to flush d-cache

2019-07-09 Thread Andes
From: Rick Chen 

Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Cc: KC Lin 
---
 arch/riscv/cpu/ax25/cache.c | 22 +-
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index cd95058..93f8d28 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,17 +5,21 @@
  */
 
 #include 
+#include 
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM  0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL   6
+#endif
 
 void flush_dcache_all(void)
 {
-   /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-* The implementation of the fence instruction in the AX25 flushes the
-* data cache and is used for this purpose.
-*/
-   asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -72,8 +76,8 @@ void dcache_disable(void)
 {
 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 #ifdef CONFIG_RISCV_NDS_CACHE
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
-   "fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
-- 
2.7.4

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[U-Boot] [PATCH v2 4/7] riscv: ax25: add imply v5l2 cache controller

2019-07-09 Thread Andes
From: Rick Chen 

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Cc: KC Lin 
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 6b4b92e..49be775 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,6 +4,7 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
+   imply V5L2_CACHE
imply ANDES_PLIC if RISCV_MMODE
imply ANDES_PLMT if RISCV_MMODE
help
-- 
2.7.4

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[U-Boot] [PATCH v2 6/7] riscv: dts: move out AE350 L2 node from cpus node

2019-07-09 Thread Andes
From: Rick Chen 

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Cc: KC Lin 
---
 arch/riscv/dts/ae350_32.dts | 17 +++--
 arch/riscv/dts/ae350_64.dts | 17 +++--
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..97b7cee 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "v5l2cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0xe050 0x40000>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   /* The value format is  */
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..d8f00f8 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "v5l2cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x4>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   /* The value format is  */
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
-- 
2.7.4

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[U-Boot] [PATCH v2 3/7] riscv: ae350: use the v5l2 driver to configure the cache

2019-07-09 Thread Andes
From: Rick Chen 

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Cc: KC Lin 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7..448ab0c 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,10 +94,18 @@ int smc_init(void)
return 0;
 }
 
+void v5l2_init(void)
+{
+   struct udevice *dev;
+
+   uclass_get_device(UCLASS_CACHE, 0, );
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
smc_init();
+   v5l2_init();
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH v2 2/7] dm: cache: add v5l2 cache controller driver

2019-07-09 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Cc: KC Lin 
---
 arch/riscv/include/asm/v5l2cache.h |  58 ++
 drivers/cache/Kconfig  |   9 +++
 drivers/cache/Makefile |   1 +
 drivers/cache/cache-v5l2.c | 121 +
 4 files changed, 189 insertions(+)
 create mode 100644 arch/riscv/include/asm/v5l2cache.h
 create mode 100644 drivers/cache/cache-v5l2.c

diff --git a/arch/riscv/include/asm/v5l2cache.h 
b/arch/riscv/include/asm/v5l2cache.h
new file mode 100644
index 000..28e40f8
--- /dev/null
+++ b/arch/riscv/include/asm/v5l2cache.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ */
+
+#ifndef _ASM_V5_L2CACHE_H
+#define _ASM_V5_L2CACHE_H
+
+struct l2cache {
+   volatile u64configure;
+   volatile u64control;
+   volatile u64hpm0;
+   volatile u64hpm1;
+   volatile u64hpm2;
+   volatile u64hpm3;
+   volatile u64error_status;
+   volatile u64ecc_error;
+   volatile u64cctl_command0;
+   volatile u64cctl_access_line0;
+   volatile u64cctl_command1;
+   volatile u64cctl_access_line1;
+   volatile u64cctl_command2;
+   volatile u64cctl_access_line2;
+   volatile u64cctl_command3;
+   volatile u64cctl_access_line4;
+   volatile u64cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE  0x1
+/* prefetch */
+#define IPREPETCH_OFF  3
+#define DPREPETCH_OFF  5
+#define IPREPETCH_MSK  (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK  (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF   8
+#define TRAMICTL_OFF   10
+#define TRAMOCTL_MSK   (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK   BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF   11
+#define DRAMICTL_OFF   13
+#define DRAMOCTL_MSK   (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK   BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart)   ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart)  (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart)  (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart)  (2 << ((hart) * 4))
+
+#endif /* _ASM_V5_L2CACHE_H */
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..629039e 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@ config L2X0_CACHE
  ARMv7(32-bit) devices. The driver configures the cache settings
  found in the device tree.
 
+config V5L2_CACHE
+   bool "Andes V5L2 cache driver"
+   select CACHE
+   depends on RISCV_NDS_CACHE
+   help
+ Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 000..dd1e72f
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct v5l2_plat {
+   struct l2cache *regs;
+};
+
+int v5l2_enable(struct udevice *dev)
+{
+   struct v5l2_plat *plat = dev_get_platdata(dev);
+   volatile struct l2cache *regs = plat->regs;
+
+   if (regs)
+   setbits_le32(>control, L2_ENABLE);
+
+   return 0;
+}
+
+int v5l2_disable(struct udevice *dev)
+{
+   struct v5l2_plat *plat = dev_get_platdata(dev);
+   volatile struct l2cache *regs = plat->regs;
+   u8 hart = gd->arch.boot_hart;
+   void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
+
+   if ((regs) && (readl(>control) & L2_ENABLE)) {
+   writel(L2_WBINVAL_ALL, cctlcmd);
+
+   while ((readl(>cctl_status) & CCTL_STATUS_MSK(hart))) {
+   if ((readl(>cctl_status) &am

[U-Boot] [PATCH v2 0/7] Support Andes RISC-V l2cache on AE350 platform

2019-07-09 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.

Also implement L2 cache flush and disable before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Changes in v2:
- Add new patch [1/7] to support dm cache uclass enable and disable ops.
- Use ofdata_to_platdata() to parse and save register base instead of global 
data.
- Rename compatible string of "cache" as "v5l2cache".
- make v512_init() return void.
- Use dm cache uclass api to disable L2 cache.

Rick Chen (7):
  dm: cache: Add enable and disable ops for cache uclass
  dm: cache: add v5l2 cache controller driver
  riscv: ae350: use the v5l2 driver to configure the cache
  riscv: ax25: add imply v5l2 cache controller
  riscv: cache: Flush L2 cache before jump to linux
  riscv: dts: move out AE350 L2 node from cpus node
  riscv: ax25: use CCTL to flush d-cache

 arch/riscv/cpu/ax25/Kconfig |   1 +
 arch/riscv/cpu/ax25/cache.c |  22 +++---
 arch/riscv/cpu/ax25/cpu.c   |  26 +++
 arch/riscv/dts/ae350_32.dts |  17 +++--
 arch/riscv/dts/ae350_64.dts |  17 +++--
 arch/riscv/include/asm/v5l2cache.h  |  58 +++
 board/AndesTech/ax25-ae350/ax25-ae350.c |   9 +++
 drivers/cache/Kconfig   |   9 +++
 drivers/cache/Makefile  |   1 +
 drivers/cache/cache-uclass.c|  20 ++
 drivers/cache/cache-v5l2.c  | 121 
 include/cache.h |  31 
 test/dm/cache.c |   2 +
 13 files changed, 313 insertions(+), 21 deletions(-)
 create mode 100644 arch/riscv/include/asm/v5l2cache.h
 create mode 100644 drivers/cache/cache-v5l2.c

-- 
2.7.4

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[U-Boot] [PATCH v2 1/7] dm: cache: Add enable and disable ops for cache uclass

2019-07-09 Thread Andes
From: Rick Chen 

The L2 cache will be enabled in init flow of dm cache
driver when it detect L2 node in dtb.

When U-Boot jump to Linux Kernel, the disable ops will
be called to flush and disable the L2 cache via the dm
cache driver.

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 drivers/cache/cache-uclass.c | 20 
 include/cache.h  | 31 +++
 test/dm/cache.c  |  2 ++
 3 files changed, 53 insertions(+)

diff --git a/drivers/cache/cache-uclass.c b/drivers/cache/cache-uclass.c
index 97ce024..3b20a10 100644
--- a/drivers/cache/cache-uclass.c
+++ b/drivers/cache/cache-uclass.c
@@ -17,6 +17,26 @@ int cache_get_info(struct udevice *dev, struct cache_info 
*info)
return ops->get_info(dev, info);
 }
 
+int cache_enable(struct udevice *dev)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->enable)
+   return -ENOSYS;
+
+   return ops->enable(dev);
+}
+
+int cache_disable(struct udevice *dev)
+{
+   struct cache_ops *ops = cache_get_ops(dev);
+
+   if (!ops->disable)
+   return -ENOSYS;
+
+   return ops->disable(dev);
+}
+
 UCLASS_DRIVER(cache) = {
.id = UCLASS_CACHE,
.name   = "cache",
diff --git a/include/cache.h b/include/cache.h
index c6334ca..32f59fd 100644
--- a/include/cache.h
+++ b/include/cache.h
@@ -22,6 +22,22 @@ struct cache_ops {
 * @return 0 if OK, -ve on error
 */
int (*get_info)(struct udevice *dev, struct cache_info *info);
+
+   /**
+* enable() - Enable cache
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @return 0 if OK, -ve on error
+*/
+   int (*enable)(struct udevice *dev);
+
+   /**
+* disable() - Flush and disable cache
+*
+* @dev:Device to check (UCLASS_CACHE)
+* @return 0 if OK, -ve on error
+*/
+   int (*disable)(struct udevice *dev);
 };
 
 #define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
@@ -35,4 +51,19 @@ struct cache_ops {
  */
 int cache_get_info(struct udevice *dev, struct cache_info *info);
 
+/**
+ * cache_enable() - Enable cache
+ *
+ * @dev:   Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_enable(struct udevice *dev);
+
+/**
+ * cache_disable() - Flush and disable cache
+ *
+ * @dev:   Device to check (UCLASS_CACHE)
+ * @return 0 if OK, -ve on error
+ */
+int cache_disable(struct udevice *dev);
 #endif
diff --git a/test/dm/cache.c b/test/dm/cache.c
index d4144aa..2e244b1 100644
--- a/test/dm/cache.c
+++ b/test/dm/cache.c
@@ -14,6 +14,8 @@ static int dm_test_reset(struct unit_test_state *uts)
 
ut_assertok(uclass_get_device(UCLASS_CACHE, 0, _cache));
ut_assertok(cache_get_info(dev, ));
+   ut_assertok(cache_enable(dev));
+   ut_assertok(cache_disable(dev));
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH] MAINTAINERS: Remove Macpaul and add Rick as nds32 maintainer

2019-07-09 Thread Andes
From: Rick Chen 

Macpaul have left Andestech for a while, and this mail address
macp...@andestech.com can not received mail anymore.

It might encounter account creation problem in this switching
to gitlab about nds32 tree.

So change the nds32 maintainer as Rick Chen 

Signed-off-by: Rick Chen 
Cc: KC Lin 
---
 MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index bea3122..b23abd5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -604,7 +604,7 @@ T:  git 
https://gitlab.denx.de/u-boot/custodians/u-boot-nand-flash.git
 F: drivers/mtd/nand/raw/
 
 NDS32
-M: Macpaul Lin 
+M: Rick Chen 
 S: Maintained
 T: git https://gitlab.denx.de/u-boot/custodians/u-boot-nds32.git
 F: arch/nds32/
-- 
2.7.4

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[U-Boot] [PATCH 6/6] riscv: ax25: use CCTL to flush d-cache

2019-05-28 Thread Andes
From: Rick Chen 

Use CCTL command to do d-cache write back and invalidate
instead of fence.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/ax25/cache.c | 22 +-
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c
index 228fc55..d30071e 100644
--- a/arch/riscv/cpu/ax25/cache.c
+++ b/arch/riscv/cpu/ax25/cache.c
@@ -5,17 +5,21 @@
  */
 
 #include 
+#include 
+
+#ifdef CONFIG_RISCV_NDS_CACHE
+/* mcctlcommand */
+#define CCTL_REG_MCCTLCOMMAND_NUM  0x7cc
+
+/* D-cache operation */
+#define CCTL_L1D_WBINVAL_ALL   6
+#endif
 
 void flush_dcache_all(void)
 {
-   /*
-* Andes' AX25 does not have a coherence agent. U-Boot must use data
-* cache flush and invalidate functions to keep data in the system
-* coherent.
-* The implementation of the fence instruction in the AX25 flushes the
-* data cache and is used for this purpose.
-*/
-   asm volatile ("fence" ::: "memory");
+#ifdef CONFIG_RISCV_NDS_CACHE
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
+#endif
 }
 
 void flush_dcache_range(unsigned long start, unsigned long end)
@@ -72,8 +76,8 @@ void dcache_disable(void)
 {
 #ifndef CONFIG_SYS_DCACHE_OFF
 #ifdef CONFIG_RISCV_NDS_CACHE
+   csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
asm volatile (
-   "fence\n\t"
"csrr t1, mcache_ctl\n\t"
"andi t0, t1, ~0x2\n\t"
"csrw mcache_ctl, t0\n\t"
-- 
2.7.4

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[U-Boot] [PATCH 4/6] riscv: cache: Flush L2 cache before jump to linux

2019-05-28 Thread Andes
From: Rick Chen 

Flush and disable cache in cleanup_before_linux()
which will be called before jump to linux.

The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/ax25/cpu.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/riscv/cpu/ax25/cpu.c b/arch/riscv/cpu/ax25/cpu.c
index 76689b2..9e7579a 100644
--- a/arch/riscv/cpu/ax25/cpu.c
+++ b/arch/riscv/cpu/ax25/cpu.c
@@ -7,6 +7,7 @@
 /* CPU specific code */
 #include 
 #include 
+#include 
 
 /*
  * cleanup_before_linux() is called just before we call linux
@@ -22,6 +23,9 @@ int cleanup_before_linux(void)
cache_flush();
icache_disable();
dcache_disable();
+#ifdef CONFIG_RISCV_NDS_CACHE
+   v5l2_disable();
+#endif
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH 5/6] riscv: dts: move out AE350 L2 node from cpus node

2019-05-28 Thread Andes
From: Rick Chen 

When L2 node exists inside cpus node, uclass_get_device
can not parse L2 node successfully. So move it outside
from cpus node.

Also add tag-ram-ctl and data-ram-ctl attributes for
v5l2 cache controller driver. This can adjust timing
by requirement from dtb to improve performance.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/dts/ae350_32.dts | 17 +++--
 arch/riscv/dts/ae350_64.dts | 17 +++--
 2 files changed, 22 insertions(+), 12 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index cb6ee13..83abfcb 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0xe050 0x40000>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   // The value format is 
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 705491a..7009bdc 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -62,13 +62,18 @@
compatible = "riscv,cpu-intc";
};
};
+   };
 
-   L2: l2-cache@e050 {
-   compatible = "cache";
-   cache-level = <2>;
-   cache-size = <0x4>;
-   reg = <0x0 0xe050 0x0 0x4>;
-   };
+   L2: l2-cache@e050 {
+   compatible = "cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x40000>;
+   andes,inst-prefetch = <3>;
+   andes,data-prefetch = <3>;
+   // The value format is 
+   andes,tag-ram-ctl = <0 0>;
+   andes,data-ram-ctl = <0 0>;
};
 
memory@0 {
-- 
2.7.4

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[U-Boot] [PATCH 1/6] dm: cache: add v5l2 cache controller driver

2019-05-28 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.

In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/include/asm/global_data.h |   3 ++
 arch/riscv/include/asm/v5l2cache.h   |  61 +
 drivers/cache/Kconfig|   9 
 drivers/cache/Makefile   |   1 +
 drivers/cache/cache-v5l2.c   | 102 +++
 5 files changed, 176 insertions(+)
 create mode 100644 arch/riscv/include/asm/v5l2cache.h
 create mode 100644 drivers/cache/cache-v5l2.c

diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index b74bd7e..6e52d5d 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -24,6 +24,9 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLMT
void __iomem *plmt; /* plmt base address */
 #endif
+#ifdef CONFIG_V5L2_CACHE
+   void __iomem *v5l2; /* v5l2 base address */
+#endif
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/v5l2cache.h 
b/arch/riscv/include/asm/v5l2cache.h
new file mode 100644
index 000..8ed1c6c
--- /dev/null
+++ b/arch/riscv/include/asm/v5l2cache.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ */
+
+#ifndef _ASM_V5_L2CACHE_H
+#define _ASM_V5_L2CACHE_H
+
+struct l2cache {
+   volatile u64configure;
+   volatile u64control;
+   volatile u64hpm0;
+   volatile u64hpm1;
+   volatile u64hpm2;
+   volatile u64hpm3;
+   volatile u64error_status;
+   volatile u64ecc_error;
+   volatile u64cctl_command0;
+   volatile u64cctl_access_line0;
+   volatile u64cctl_command1;
+   volatile u64cctl_access_line1;
+   volatile u64cctl_command2;
+   volatile u64cctl_access_line2;
+   volatile u64cctl_command3;
+   volatile u64cctl_access_line4;
+   volatile u64cctl_status;
+};
+
+/* Control Register */
+#define L2_ENABLE  0x1
+/* prefetch */
+#define IPREPETCH_OFF  3
+#define DPREPETCH_OFF  5
+#define IPREPETCH_MSK  (3 << IPREPETCH_OFF)
+#define DPREPETCH_MSK  (3 << DPREPETCH_OFF)
+/* tag ram */
+#define TRAMOCTL_OFF   8
+#define TRAMICTL_OFF   10
+#define TRAMOCTL_MSK   (3 << TRAMOCTL_OFF)
+#define TRAMICTL_MSK   BIT(TRAMICTL_OFF)
+/* data ram */
+#define DRAMOCTL_OFF   11
+#define DRAMICTL_OFF   13
+#define DRAMOCTL_MSK   (3 << DRAMOCTL_OFF)
+#define DRAMICTL_MSK   BIT(DRAMICTL_OFF)
+
+/* CCTL Command Register */
+#define CCTL_CMD_REG(base, hart)   ((ulong)(base) + 0x40 + (hart) * 0x10)
+#define L2_WBINVAL_ALL 0x12
+
+/* CCTL Status Register */
+#define CCTL_STATUS_MSK(hart)  (0xf << ((hart) * 4))
+#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
+#define CCTL_STATUS_PROCESS(hart)  (1 << ((hart) * 4))
+#define CCTL_STATUS_ILLEGAL(hart)  (2 << ((hart) * 4))
+
+void v5l2_enable(void);
+void v5l2_disable(void);
+
+#endif /* _ASM_V5_L2CACHE_H */
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 24def7a..665689a 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -22,4 +22,13 @@ config L2X0_CACHE
  ARMv7(32-bit) devices. The driver configures the cache settings
  found in the device tree.
 
+config V5L2_CACHE
+   tristate "Andes V5L2 cache driver"
+   select CACHE
+   depends on RISCV_NDS_CACHE
+   help
+ Support Andes V5L2 cache controller in AE350 platform.
+ It will configure tag and data ram timing control from the
+ device tree and enable L2 cache.
+
 endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 9deb961..4a6458c 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
 obj-$(CONFIG_CACHE) += cache-uclass.o
 obj-$(CONFIG_SANDBOX) += sandbox_cache.o
 obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
+obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
diff --git a/drivers/cache/cache-v5l2.c b/drivers/cache/cache-v5l2.c
new file mode 100644
index 000..7022feb
--- /dev/null
+++ b/drivers/cache/cache-v5l2.c
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void v5l2_enable(void)
+{
+   struct l2cache *regs = gd->arch.v5l2;
+
+   if (regs)
+   setbits_le32(>control, L2_ENABLE);
+}
+
+void v5l2_disable(void)
+{
+   volatile struct l2cache *regs = gd->arch.v5l2;
+   u8 hart = gd->arch.b

[U-Boot] [PATCH 3/6] riscv: ae350: add imply v5l2 cache controller

2019-05-28 Thread Andes
From: Rick Chen 

Select the v5l2 UCLASS_CACHE driver for AE350.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 board/AndesTech/ax25-ae350/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/AndesTech/ax25-ae350/Kconfig 
b/board/AndesTech/ax25-ae350/Kconfig
index 5e682b6..dd299d9 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -25,5 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
imply SMP
+   imply V5L2_CACHE
 
 endif
-- 
2.7.4

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[U-Boot] [PATCH 2/6] riscv: ae350: use the v5l2 driver to configure the cache

2019-05-28 Thread Andes
From: Rick Chen 

Find the UCLASS_CACHE driver to configure the cache controller's
settings.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index 3d65ce7..686ec4a 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -93,10 +94,24 @@ int smc_init(void)
return 0;
 }
 
+int v5l2_init(void)
+{
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_get_device(UCLASS_CACHE, 0, );
+
+   if (ret)
+   return ret;
+
+   return 0;
+}
+
 #ifdef CONFIG_BOARD_EARLY_INIT_F
 int board_early_init_f(void)
 {
smc_init();
+   v5l2_init();
 
return 0;
 }
-- 
2.7.4

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[U-Boot] [PATCH 0/6] Support Andes RISC-V l2cache on AE350 platform

2019-05-28 Thread Andes
From: Rick Chen 

Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse and configure the
cache settings (data & instruction prefetch, data & tag latency)
from the device tree blob.

Also implement L2 cache flush and disable before jump to linux.
The sequence will be preferred as below:
L1 flush -> L1 disable -> L2 flush -> L2 disable

Rick Chen (6):
  dm: cache: add v5l2 cache controller driver
  riscv: ae350: use the v5l2 driver to configure the cache
  riscv: ae350: add imply v5l2 cache controller
  riscv: cache: Flush L2 cache before jump to linux
  riscv: dts: move out AE350 L2 node from cpus node
  riscv: ax25: use CCTL to flush d-cache

 arch/riscv/cpu/ax25/cache.c |  22 ---
 arch/riscv/cpu/ax25/cpu.c   |   4 ++
 arch/riscv/dts/ae350_32.dts |  17 --
 arch/riscv/dts/ae350_64.dts |  17 --
 arch/riscv/include/asm/global_data.h|   3 +
 arch/riscv/include/asm/v5l2cache.h  |  61 +++
 board/AndesTech/ax25-ae350/Kconfig  |   1 +
 board/AndesTech/ax25-ae350/ax25-ae350.c |  15 +
 drivers/cache/Kconfig   |   9 +++
 drivers/cache/Makefile  |   1 +
 drivers/cache/cache-v5l2.c  | 102 
 11 files changed, 231 insertions(+), 21 deletions(-)
 create mode 100644 arch/riscv/include/asm/v5l2cache.h
 create mode 100644 drivers/cache/cache-v5l2.c

-- 
2.7.4

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[U-Boot] [PATCH v5 6/6] riscv: configs: add ae350_rv[32|64]_xip_defconfig to MAINTAINERS

2019-05-08 Thread Andes
From: Rick Chen 

This patch will fix Travis failure item as below:
https://travis-ci.org/rickchen36/u-boot-riscv/jobs/529605196

Check for configs without MAINTAINERS entry

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 board/AndesTech/ax25-ae350/MAINTAINERS | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/AndesTech/ax25-ae350/MAINTAINERS 
b/board/AndesTech/ax25-ae350/MAINTAINERS
index b0a99e4..feed5d1 100644
--- a/board/AndesTech/ax25-ae350/MAINTAINERS
+++ b/board/AndesTech/ax25-ae350/MAINTAINERS
@@ -5,3 +5,5 @@ F:  board/AndesTech/ax25-ae350/
 F: include/configs/ax25-ae350.h
 F: configs/ae350_rv32_defconfig
 F: configs/ae350_rv64_defconfig
+F: configs/ae350_rv32_xip_defconfig
+F: configs/ae350_rv64_xip_defconfig
-- 
2.7.4

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[U-Boot] [PATCH v5 4/6] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ram

2019-05-08 Thread Andes
From: Rick Chen 

When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 configs/ae350_rv32_defconfig | 2 +-
 configs/ae350_rv64_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index f029455..71d2716 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 98635a2..9bf1737 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.7.4

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[U-Boot] [PATCH v5 5/6] riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash

2019-05-08 Thread Andes
From: Rick Chen 

When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of
CONFIG_OF_BOARD.

Also remove unused code about prior_stage_fdt_address.
And modify CONFIG_SYS_FDT_BASE as flash address.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 4 
 configs/ae350_rv32_xip_defconfig| 2 +-
 configs/ae350_rv64_xip_defconfig| 2 +-
 include/configs/ax25-ae350.h| 2 +-
 4 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d343453..3d65ce7 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -67,10 +67,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, 
flash_info_t *info)
 
 void *board_fdt_blob_setup(void)
 {
-   void **ptr = (void *)_stage_fdt_address;
-   if (fdt_magic(*ptr) == FDT_MAGIC)
-   return (void *)*ptr;
-
return (void *)CONFIG_SYS_FDT_BASE;
 }
 
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 76534f2..07f1ecc 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index f7f2925..28afd81 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -16,7 +16,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index 395f3a4..a4037f3 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -40,7 +40,7 @@
 #define CONFIG_SYS_MALLOC_LEN   (512 << 10)
 
 /* DT blob (fdt) address */
-#define CONFIG_SYS_FDT_BASE0x000f
+#define CONFIG_SYS_FDT_BASE0x800f
 
 /*
  * Physical Memory Map
-- 
2.7.4

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[U-Boot] [PATCH v5 2/6] riscv: configs: Support AE350 SMP booting from flash flow

2019-05-08 Thread Andes
From: Rick Chen 

Add two defconfigs to support AE350 SMP booting from flash.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 configs/ae350_rv32_xip_defconfig | 37 +
 configs/ae350_rv64_xip_defconfig | 38 ++
 2 files changed, 75 insertions(+)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
new file mode 100644
index 000..76534f2
--- /dev/null
+++ b/configs/ae350_rv32_xip_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
new file mode 100644
index 000..f7f2925
--- /dev/null
+++ b/configs/ae350_rv64_xip_defconfig
@@ -0,0 +1,38 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
-- 
2.7.4

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[U-Boot] [PATCH v5 3/6] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-05-08 Thread Andes
From: Rick Chen 

This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.

When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 arch/riscv/cpu/cpu.c   | 2 ++
 arch/riscv/cpu/start.S | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 0cfd7d6..e9a8b43 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -15,7 +15,9 @@
  * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
+#ifdef CONFIG_OF_PRIOR_STAGE
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
 #ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 3402d09..60ac8c6 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,8 +111,10 @@ call_board_init_f_0:
bneztp, secondary_hart_loop
 #endif
 
+#ifdef CONFIG_OF_PRIOR_STAGE
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
+#endif
 
jal board_init_f_init_reserve
 
-- 
2.7.4

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[U-Boot] [PATCH v5 0/6] AE350 support SMP boot from flash

2019-05-08 Thread Andes
From: Rick Chen 

In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disabling this two features.

Changes in v5:
- New patch
[PATCH v5 6/6] riscv: configs: add ae350_rv[32|64]_xip_defconfig to 
MAINTAINERS
It will fix Travis failure item :
https://travis-ci.org/rickchen36/u-boot-riscv/jobs/529605196

Changes in v4:
- Use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD in ae350_rv32_xip_defconfig 
and ae350_rv64_xip_defconfig.
- Remove prior_stage_fdt_address in board_fdt_blob_setup.
- Modify CONFIG_SYS_FDT_BASE as flash address.

Changes in v3:
- Modify CONFIG_XIP descriptions
- Use #ifdef CONFIG_OF_PRIOR_STAGE to replace #  if 
CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
- Recovery some blank lines
- Add CONFIG_SF_DEFAULT_MODE=0x0 in ae350_rv32_xip_defconfig and 
ae350_rv64_xip_defconfig
- #ifdef CONFIG_OF_PRIOR_STAGE shall also surround SREG s1, 0(t0)
- Modify CONFIG_SYS_FDT_BASE from 0x000f as 0x800f in ax25-ae350.h


Changes in v2:
- Fix some typos
- Also surround the declaration of prior_stage_fdt_address in 
arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE
- Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS

Rick Chen (6):
  riscv: Introduce CONFIG_XIP to support booting from flash
  riscv: configs: Support AE350 SMP booting from flash flow
  riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE
is enabled
  riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from
ram
  riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from
flash
  riscv: configs: add ae350_rv[32|64]_xip_defconfig to MAINTAINERS

 arch/riscv/Kconfig  |  7 ++
 arch/riscv/cpu/cpu.c|  4 
 arch/riscv/cpu/start.S  |  8 +++
 arch/riscv/include/asm/global_data.h|  2 ++
 arch/riscv/lib/asm-offsets.c|  2 ++
 arch/riscv/lib/smp.c|  2 ++
 board/AndesTech/ax25-ae350/MAINTAINERS  |  2 ++
 board/AndesTech/ax25-ae350/ax25-ae350.c |  4 
 configs/ae350_rv32_defconfig|  2 +-
 configs/ae350_rv32_xip_defconfig| 37 
 configs/ae350_rv64_defconfig|  2 +-
 configs/ae350_rv64_xip_defconfig| 38 +
 include/configs/ax25-ae350.h|  2 +-
 13 files changed, 105 insertions(+), 7 deletions(-)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

-- 
2.7.4

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[U-Boot] [PATCH v5 1/6] riscv: Introduce CONFIG_XIP to support booting from flash

2019-05-08 Thread Andes
From: Rick Chen 

When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Lukas Auer 
Reviewed-by: Bin Meng 
---
 arch/riscv/Kconfig   | 7 +++
 arch/riscv/cpu/cpu.c | 2 ++
 arch/riscv/cpu/start.S   | 6 ++
 arch/riscv/include/asm/global_data.h | 2 ++
 arch/riscv/lib/asm-offsets.c | 2 ++
 arch/riscv/lib/smp.c | 2 ++
 6 files changed, 21 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..362f3cd 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,13 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
 
+config XIP
+   bool "XIP mode"
+   help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a NOR flash memory without copying the code to ram.
+ Say yes here if U-Boot boots from flash directly.
+
 config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..0cfd7d6 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,6 +16,7 @@
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 
 /*
@@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
  * finished initialization of global data.
  */
 u32 available_harts_lock = 1;
+#endif
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..3402d09 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv  sp, a0
 #endif
 
+#ifndef CONFIG_XIP
/*
 * Pick hart to initialize global data and run U-Boot. The other harts
 * wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
li  s2, 1
amoswap.w s2, t1, 0(t0)
bnezs2, wait_for_gd_init
+#else
+   bneztp, secondary_hart_loop
+#endif
 
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
 
+#ifndef CONFIG_XIP
la  t0, available_harts_lock
fence   rw, w
amoswap.w zero, zero, 0(t0)
@@ -141,6 +146,7 @@ wait_for_gd_init:
 * secondary_hart_loop.
 */
bnezs2, secondary_hart_loop
+#endif
 
/* Enable cache */
jal icache_enable
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index dffcd45..b74bd7e 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
+#ifndef CONFIG_XIP
ulong available_harts;
+#endif
 };
 
 #include 
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..4fa4fd3 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
 int main(void)
 {
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
 
return 0;
 }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..cc66f15 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
continue;
}
 
+#ifndef CONFIG_XIP
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
+#endif
 
gd->arch.ipi[reg].addr = ipi->addr;
gd->arch.ipi[reg].arg0 = ipi->arg0;
-- 
2.7.4

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[U-Boot] [PATCH v4 5/5] riscv: configs: AE350 will use CONFIG_OF_SEPARATE when boots from flash

2019-04-29 Thread Andes
From: Rick Chen 

When AE350 boots from flash, use CONFIG_OF_SEPARATE instead of
CONFIG_OF_BOARD.

Also remove unused code about prior_stage_fdt_address.
And modify CONFIG_SYS_FDT_BASE as flash address.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 board/AndesTech/ax25-ae350/ax25-ae350.c | 4 
 configs/ae350_rv32_xip_defconfig| 2 +-
 configs/ae350_rv64_xip_defconfig| 2 +-
 include/configs/ax25-ae350.h| 2 +-
 4 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d343453..3d65ce7 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -67,10 +67,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, 
flash_info_t *info)
 
 void *board_fdt_blob_setup(void)
 {
-   void **ptr = (void *)_stage_fdt_address;
-   if (fdt_magic(*ptr) == FDT_MAGIC)
-   return (void *)*ptr;
-
return (void *)CONFIG_SYS_FDT_BASE;
 }
 
diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
index 76534f2..07f1ecc 100644
--- a/configs/ae350_rv32_xip_defconfig
+++ b/configs/ae350_rv32_xip_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
index f7f2925..28afd81 100644
--- a/configs/ae350_rv64_xip_defconfig
+++ b/configs/ae350_rv64_xip_defconfig
@@ -16,7 +16,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_SEPARATE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index 395f3a4..a4037f3 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -40,7 +40,7 @@
 #define CONFIG_SYS_MALLOC_LEN   (512 << 10)
 
 /* DT blob (fdt) address */
-#define CONFIG_SYS_FDT_BASE0x000f
+#define CONFIG_SYS_FDT_BASE0x800f
 
 /*
  * Physical Memory Map
-- 
2.7.4

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[U-Boot] [PATCH v4 3/5] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-04-29 Thread Andes
From: Rick Chen 

This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.

When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/cpu.c   | 2 ++
 arch/riscv/cpu/start.S | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 0cfd7d6..e9a8b43 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -15,7 +15,9 @@
  * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
+#ifdef CONFIG_OF_PRIOR_STAGE
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
 #ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 3402d09..60ac8c6 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,8 +111,10 @@ call_board_init_f_0:
bneztp, secondary_hart_loop
 #endif
 
+#ifdef CONFIG_OF_PRIOR_STAGE
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
+#endif
 
jal board_init_f_init_reserve
 
-- 
2.7.4

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[U-Boot] [PATCH v4 4/5] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from ram

2019-04-29 Thread Andes
From: Rick Chen 

When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 configs/ae350_rv32_defconfig | 2 +-
 configs/ae350_rv64_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index f029455..71d2716 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 98635a2..9bf1737 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.7.4

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[U-Boot] [PATCH v4 2/5] riscv: configs: Support AE350 SMP booting from flash flow

2019-04-29 Thread Andes
From: Rick Chen 

Add two defconfigs to support AE350 SMP booting from flash.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 configs/ae350_rv32_xip_defconfig | 37 +
 configs/ae350_rv64_xip_defconfig | 38 ++
 2 files changed, 75 insertions(+)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
new file mode 100644
index 000..76534f2
--- /dev/null
+++ b/configs/ae350_rv32_xip_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
new file mode 100644
index 000..f7f2925
--- /dev/null
+++ b/configs/ae350_rv64_xip_defconfig
@@ -0,0 +1,38 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
-- 
2.7.4

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[U-Boot] [PATCH v4 1/5] riscv: Introduce CONFIG_XIP to support booting from flash

2019-04-29 Thread Andes
From: Rick Chen 

When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Lukas Auer 
---
 arch/riscv/Kconfig   | 7 +++
 arch/riscv/cpu/cpu.c | 2 ++
 arch/riscv/cpu/start.S   | 6 ++
 arch/riscv/include/asm/global_data.h | 2 ++
 arch/riscv/lib/asm-offsets.c | 2 ++
 arch/riscv/lib/smp.c | 2 ++
 6 files changed, 21 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..362f3cd 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,13 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
 
+config XIP
+   bool "XIP mode"
+   help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a NOR flash memory without copying the code to ram.
+ Say yes here if U-Boot boots from flash directly.
+
 config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..0cfd7d6 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,6 +16,7 @@
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 
 /*
@@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
  * finished initialization of global data.
  */
 u32 available_harts_lock = 1;
+#endif
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..3402d09 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv  sp, a0
 #endif
 
+#ifndef CONFIG_XIP
/*
 * Pick hart to initialize global data and run U-Boot. The other harts
 * wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
li  s2, 1
amoswap.w s2, t1, 0(t0)
bnezs2, wait_for_gd_init
+#else
+   bneztp, secondary_hart_loop
+#endif
 
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
 
+#ifndef CONFIG_XIP
la  t0, available_harts_lock
fence   rw, w
amoswap.w zero, zero, 0(t0)
@@ -141,6 +146,7 @@ wait_for_gd_init:
 * secondary_hart_loop.
 */
bnezs2, secondary_hart_loop
+#endif
 
/* Enable cache */
jal icache_enable
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index dffcd45..b74bd7e 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
+#ifndef CONFIG_XIP
ulong available_harts;
+#endif
 };
 
 #include 
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..4fa4fd3 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
 int main(void)
 {
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
 
return 0;
 }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..cc66f15 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
continue;
}
 
+#ifndef CONFIG_XIP
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
+#endif
 
gd->arch.ipi[reg].addr = ipi->addr;
gd->arch.ipi[reg].arg0 = ipi->arg0;
-- 
2.7.4

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[U-Boot] [PATCH v4 0/5] AE350 support SMP boot from flash

2019-04-29 Thread Andes
From: Rick Chen 

In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disabling this two features.

Changes in v4:
- Use CONFIG_OF_SEPARATE instead of CONFIG_OF_BOARD in ae350_rv32_xip_defconfig 
and ae350_rv64_xip_defconfig.
- Remove prior_stage_fdt_address in board_fdt_blob_setup.
- Modify CONFIG_SYS_FDT_BASE as flash address.

Changes in v3:
- Modify CONFIG_XIP descriptions
- Use #ifdef CONFIG_OF_PRIOR_STAGE to replace #  if 
CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
- Recovery some blank lines
- Add CONFIG_SF_DEFAULT_MODE=0x0 in ae350_rv32_xip_defconfig and 
ae350_rv64_xip_defconfig
- #ifdef CONFIG_OF_PRIOR_STAGE shall also surround SREG s1, 0(t0)
- Modify CONFIG_SYS_FDT_BASE from 0x000f as 0x800f in ax25-ae350.h


Changes in v2:
- Fix some typos
- Also surround the declaration of prior_stage_fdt_address in 
arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE
- Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS

Rick Chen (5):
  riscv: Introduce CONFIG_XIP to support booting from flash
  riscv: configs: Support AE350 SMP booting from flash flow
  riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE
is enabled
  riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when boots from
ram
  riscv: configs: ae350 will use CONFIG_OF_SEPARATE when boots from
flash

 arch/riscv/Kconfig  |  7 ++
 arch/riscv/cpu/cpu.c|  4 
 arch/riscv/cpu/start.S  |  8 +++
 arch/riscv/include/asm/global_data.h|  2 ++
 arch/riscv/lib/asm-offsets.c|  2 ++
 arch/riscv/lib/smp.c|  2 ++
 board/AndesTech/ax25-ae350/ax25-ae350.c |  4 
 configs/ae350_rv32_defconfig|  2 +-
 configs/ae350_rv32_xip_defconfig| 37 
 configs/ae350_rv64_defconfig|  2 +-
 configs/ae350_rv64_xip_defconfig| 38 +
 include/configs/ax25-ae350.h|  2 +-
 12 files changed, 103 insertions(+), 7 deletions(-)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

-- 
2.7.4

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[U-Boot] [PATCH v3 4/4] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram

2019-04-29 Thread Andes
From: Rick Chen 

When AE350 boots from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 configs/ae350_rv32_defconfig | 2 +-
 configs/ae350_rv64_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index f029455..71d2716 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index 98635a2..9bf1737 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.7.4

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[U-Boot] [PATCH v3 1/4] riscv: Introduce CONFIG_XIP to support booting from flash

2019-04-29 Thread Andes
From: Rick Chen 

When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/Kconfig   | 7 +++
 arch/riscv/cpu/cpu.c | 2 ++
 arch/riscv/cpu/start.S   | 6 ++
 arch/riscv/include/asm/global_data.h | 2 ++
 arch/riscv/lib/asm-offsets.c | 2 ++
 arch/riscv/lib/smp.c | 2 ++
 6 files changed, 21 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..362f3cd 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,13 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
 
+config XIP
+   bool "XIP mode"
+   help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a NOR flash memory without copying the code to ram.
+ Say yes here if U-Boot boots from flash directly.
+
 config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..0cfd7d6 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,6 +16,7 @@
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 
 /*
@@ -23,6 +24,7 @@ u32 hart_lottery __attribute__((section(".data"))) = 0;
  * finished initialization of global data.
  */
 u32 available_harts_lock = 1;
+#endif
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..3402d09 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv  sp, a0
 #endif
 
+#ifndef CONFIG_XIP
/*
 * Pick hart to initialize global data and run U-Boot. The other harts
 * wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
li  s2, 1
amoswap.w s2, t1, 0(t0)
bnezs2, wait_for_gd_init
+#else
+   bneztp, secondary_hart_loop
+#endif
 
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
 
+#ifndef CONFIG_XIP
la  t0, available_harts_lock
fence   rw, w
amoswap.w zero, zero, 0(t0)
@@ -141,6 +146,7 @@ wait_for_gd_init:
 * secondary_hart_loop.
 */
bnezs2, secondary_hart_loop
+#endif
 
/* Enable cache */
jal icache_enable
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index dffcd45..b74bd7e 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
+#ifndef CONFIG_XIP
ulong available_harts;
+#endif
 };
 
 #include 
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..4fa4fd3 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
 int main(void)
 {
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
 
return 0;
 }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..cc66f15 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
continue;
}
 
+#ifndef CONFIG_XIP
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
+#endif
 
gd->arch.ipi[reg].addr = ipi->addr;
gd->arch.ipi[reg].arg0 = ipi->arg0;
-- 
2.7.4

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[U-Boot] [PATCH v3 3/4] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-04-29 Thread Andes
From: Rick Chen 

This patch will fix prior_stage_fdt_address write failure problem, when
AE350 boots from flash.

When AE350 boots from flash, prior_stage_fdt_address will be flash
address, we shall avoid it to be written.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/cpu.c| 2 ++
 arch/riscv/cpu/start.S  | 2 ++
 board/AndesTech/ax25-ae350/ax25-ae350.c | 4 
 include/configs/ax25-ae350.h| 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 0cfd7d6..e9a8b43 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -15,7 +15,9 @@
  * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
+#ifdef CONFIG_OF_PRIOR_STAGE
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
 #ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 3402d09..60ac8c6 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,8 +111,10 @@ call_board_init_f_0:
bneztp, secondary_hart_loop
 #endif
 
+#ifdef CONFIG_OF_PRIOR_STAGE
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
+#endif
 
jal board_init_f_init_reserve
 
diff --git a/board/AndesTech/ax25-ae350/ax25-ae350.c 
b/board/AndesTech/ax25-ae350/ax25-ae350.c
index d343453..3d65ce7 100644
--- a/board/AndesTech/ax25-ae350/ax25-ae350.c
+++ b/board/AndesTech/ax25-ae350/ax25-ae350.c
@@ -67,10 +67,6 @@ ulong board_flash_get_legacy(ulong base, int banknum, 
flash_info_t *info)
 
 void *board_fdt_blob_setup(void)
 {
-   void **ptr = (void *)_stage_fdt_address;
-   if (fdt_magic(*ptr) == FDT_MAGIC)
-   return (void *)*ptr;
-
return (void *)CONFIG_SYS_FDT_BASE;
 }
 
diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h
index 395f3a4..a4037f3 100644
--- a/include/configs/ax25-ae350.h
+++ b/include/configs/ax25-ae350.h
@@ -40,7 +40,7 @@
 #define CONFIG_SYS_MALLOC_LEN   (512 << 10)
 
 /* DT blob (fdt) address */
-#define CONFIG_SYS_FDT_BASE0x000f
+#define CONFIG_SYS_FDT_BASE0x800f
 
 /*
  * Physical Memory Map
-- 
2.7.4

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[U-Boot] [PATCH v3 2/4] riscv: configs: Support AE350 SMP booting from flash flow

2019-04-29 Thread Andes
From: Rick Chen 

Add two defconfigs to support AE350 SMP booting from flash.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 configs/ae350_rv32_xip_defconfig | 37 +
 configs/ae350_rv64_xip_defconfig | 38 ++
 2 files changed, 75 insertions(+)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
new file mode 100644
index 000..76534f2
--- /dev/null
+++ b/configs/ae350_rv32_xip_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
new file mode 100644
index 000..f7f2925
--- /dev/null
+++ b/configs/ae350_rv64_xip_defconfig
@@ -0,0 +1,38 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
-- 
2.7.4

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[U-Boot] [PATCH v3 0/4] AE350 support SMP boot from flash

2019-04-29 Thread Andes
From: Rick Chen 

In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disabling this two features.

Changes in v3:
- Modify CONFIG_XIP descriptions
- Use #ifdef CONFIG_OF_PRIOR_STAGE to replace #  if 
CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
- Recovery some blank lines
- Add CONFIG_SF_DEFAULT_MODE=0x0 in ae350_rv32_xip_defconfig and 
ae350_rv64_xip_defconfig
- #ifdef CONFIG_OF_PRIOR_STAGE shall also surround SREG s1, 0(t0)
- Modify CONFIG_SYS_FDT_BASE from 0x000f as 0x800f in ax25-ae350.h


Changes in v2:
- Fix some typos
- Also surround the declaration of prior_stage_fdt_address in 
arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE
- Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS

Rick Chen (4):
  riscv: Introduce CONFIG_XIP to support booting from flash
  riscv: configs: Support AE350 SMP booting from flash flow
  riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE
is enabled
  riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from
ram

 arch/riscv/Kconfig  |  7 ++
 arch/riscv/cpu/cpu.c|  4 
 arch/riscv/cpu/start.S  |  8 +++
 arch/riscv/include/asm/global_data.h|  2 ++
 arch/riscv/lib/asm-offsets.c|  2 ++
 arch/riscv/lib/smp.c|  2 ++
 board/AndesTech/ax25-ae350/ax25-ae350.c |  4 
 configs/ae350_rv32_defconfig|  2 +-
 configs/ae350_rv32_xip_defconfig| 37 
 configs/ae350_rv64_defconfig|  2 +-
 configs/ae350_rv64_xip_defconfig| 38 +
 include/configs/ax25-ae350.h|  2 +-
 12 files changed, 103 insertions(+), 7 deletions(-)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

-- 
2.7.4

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[U-Boot] [PATCH v2 4/4] riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from ram

2019-04-24 Thread Andes
From: Rick Chen 

When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead
of CONFIG_OF_BOARD.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 configs/ae350_rv32_defconfig | 2 +-
 configs/ae350_rv64_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index e13c7de..54b65f1 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index a41f918..0ff4de8 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.7.4

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[U-Boot] [PATCH v2 2/4] riscv: configs: Support AE350 SMP booting from flash flow

2019-04-24 Thread Andes
From: Rick Chen 

Add two defconfigs to support AE350 SMP booting from flash.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 configs/ae350_rv32_xip_defconfig | 36 
 configs/ae350_rv64_xip_defconfig | 37 +
 2 files changed, 73 insertions(+)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
new file mode 100644
index 000..7c46769
--- /dev/null
+++ b/configs/ae350_rv32_xip_defconfig
@@ -0,0 +1,36 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
new file mode 100644
index 000..67633d6
--- /dev/null
+++ b/configs/ae350_rv64_xip_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_XIP=y
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
-- 
2.7.4

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[U-Boot] [PATCH v2 3/4] riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-04-24 Thread Andes
From: Rick Chen 

This patch will fix prior_stage_fdt_address write failure problem, when
AE350 was booting from flash.

When AE350 was booting from falsh, prior_stage_fdt_address will be in
flash address, we shall avoid it to be written.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/cpu.c   | 2 ++
 arch/riscv/cpu/start.S | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 768c44c..a17d37f 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -15,7 +15,9 @@
  * The variables here must be stored in the data section since they are used
  * before the bss section is available.
  */
+#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#endif
 #ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
 /*
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 41d9a32..9ede1a7 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,7 +111,9 @@ call_board_init_f_0:
bneztp, secondary_hart_loop
 #endif
 
+#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
la  t0, prior_stage_fdt_address
+#endif
SREGs1, 0(t0)
 
jal board_init_f_init_reserve
-- 
2.7.4

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[U-Boot] [PATCH v2 1/4] riscv: hart_lottery and available harts features can be selectable

2019-04-24 Thread Andes
From: Rick Chen 

In smp flow these two features only can be enabled when U-Boot
booting from ram. It shall be disabled when U-Boot booting from
flash.

Add CONFIG_XIP to NOT select this two features. It's default value
will say NO for booting from ram.

AE350 will encounter the the write failure problem since
hart_lottery and available_harts_lock was not in ram address but
in flash address when booing from flash.

This patch can help to fix the write failure problem when AE350
booting from flash by disabling this two features.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/Kconfig   | 10 ++
 arch/riscv/cpu/cpu.c |  3 ++-
 arch/riscv/cpu/start.S   |  7 ++-
 arch/riscv/include/asm/global_data.h |  2 ++
 arch/riscv/lib/asm-offsets.c |  2 ++
 arch/riscv/lib/smp.c |  2 ++
 6 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..fb9a8c6 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,16 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
 
+config XIP
+   bool "XIP mode"
+   default n
+   help
+ XIP (eXecute In Place) is a method for executing code directly
+ from a serial NOR flash memory without copying the code to ram.
+ This must NOT support hart lottery and available harts features.
+ These two feature only can be enabled when U-Boot booting from
+ ram, but shall be disabled when booting from flash.
+
 config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..768c44c 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,13 +16,14 @@
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifndef CONFIG_XIP
 u32 hart_lottery __attribute__((section(".data"))) = 0;
-
 /*
  * The main hart running U-Boot has acquired available_harts_lock until it has
  * finished initialization of global data.
  */
 u32 available_harts_lock = 1;
+#endif
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..41d9a32 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv  sp, a0
 #endif
 
+#ifndef CONFIG_XIP
/*
 * Pick hart to initialize global data and run U-Boot. The other harts
 * wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
li  s2, 1
amoswap.w s2, t1, 0(t0)
bnezs2, wait_for_gd_init
+#else
+   bneztp, secondary_hart_loop
+#endif
 
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
 
+#ifndef CONFIG_XIP
la  t0, available_harts_lock
fence   rw, w
amoswap.w zero, zero, 0(t0)
@@ -141,7 +146,7 @@ wait_for_gd_init:
 * secondary_hart_loop.
 */
bnezs2, secondary_hart_loop
-
+#endif
/* Enable cache */
jal icache_enable
jal dcache_enable
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index dffcd45..b74bd7e 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
+#ifndef CONFIG_XIP
ulong available_harts;
+#endif
 };
 
 #include 
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..4fa4fd3 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
 int main(void)
 {
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifndef CONFIG_XIP
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
 
return 0;
 }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..cc66f15 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)
continue;
}
 
+#ifndef CONFIG_XIP
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;
+#endif
 
gd->arch.ipi[reg].addr = ipi->addr;
gd->arch.ipi[reg].arg0 = ipi->arg0;
-- 
2.7.4

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[U-Boot] [PATCH v2 0/4] AE350 support SMP boot from flash

2019-04-24 Thread Andes
From: Rick Chen 

In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disabling this two features.

Changes in v2:
- Fix some typos
- Also surround the declaration of prior_stage_fdt_address in 
arch/riscv/cpu/cpu.c with OF_PRIOR_STAGE
- Use CONFIP_XIP to replace CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS

Rick Chen (4):
  riscv: hart_lottery and available harts features can be selectable
  riscv: configs: Support AE350 SMP booting from flash flow
  riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE
is enabled
  riscv: configs: AE350 will use CONFIG_OF_PRIOR_STAGE when booting from
ram

 arch/riscv/Kconfig   | 10 ++
 arch/riscv/cpu/cpu.c |  5 -
 arch/riscv/cpu/start.S   |  9 -
 arch/riscv/include/asm/global_data.h |  2 ++
 arch/riscv/lib/asm-offsets.c |  2 ++
 arch/riscv/lib/smp.c |  2 ++
 configs/ae350_rv32_defconfig |  2 +-
 configs/ae350_rv32_xip_defconfig | 36 +++
 configs/ae350_rv64_defconfig |  2 +-
 configs/ae350_rv64_xip_defconfig | 37 
 10 files changed, 103 insertions(+), 4 deletions(-)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

-- 
2.7.4

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[U-Boot] [PATCH 3/4] riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is enable

2019-04-22 Thread Andes
From: Rick Chen 

This patch will fix prior_stage_fdt_address write failure problem, when
AE350 was booting from flash.

When AE350 was booting from falsh, prior_stage_fdt_address will be in
flash address, we shall avoid it to be written.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/cpu/start.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index d030d4a..0e672e0 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,7 +111,9 @@ call_board_init_f_0:
bneztp, secondary_hart_loop
 #endif
 
+#  if CONFIG_IS_ENABLED(OF_PRIOR_STAGE)
la  t0, prior_stage_fdt_address
+#endif
SREGs1, 0(t0)
 
jal board_init_f_init_reserve
-- 
2.7.4

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[U-Boot] [PATCH 4/4] riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

2019-04-22 Thread Andes
From: Rick Chen 

When AE350 was booting from ram, use OF_PRIOR_STAGE instead
of OF_PRIOR_STAGE.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 configs/ae350_rv32_defconfig | 2 +-
 configs/ae350_rv64_defconfig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index e13c7de..54b65f1 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -14,7 +14,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index a41f918..0ff4de8 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -15,7 +15,7 @@ CONFIG_CMD_SF_TEST=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_BOOTP_PREFER_SERVERIP=y
 CONFIG_CMD_CACHE=y
-CONFIG_OF_BOARD=y
+CONFIG_OF_PRIOR_STAGE=y
 CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.7.4

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[U-Boot] [PATCH 2/4] riscv: configs: Support AE350 SMP boot from flash flow

2019-04-22 Thread Andes
From: Rick Chen 

Add two defconfig to support AE350 SMP boot from flash
by disable CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 configs/ae350_rv32_xip_defconfig | 37 +
 configs/ae350_rv64_xip_defconfig | 38 ++
 2 files changed, 75 insertions(+)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig
new file mode 100644
index 000..1639367
--- /dev/null
+++ b/configs/ae350_rv32_xip_defconfig
@@ -0,0 +1,37 @@
+CONFIG_RISCV=y
+CONFIG_HART_LOTTERY=n
+CONFIG_AVAILABLE_HARTS=n
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
diff --git a/configs/ae350_rv64_xip_defconfig b/configs/ae350_rv64_xip_defconfig
new file mode 100644
index 000..d6a502c
--- /dev/null
+++ b/configs/ae350_rv64_xip_defconfig
@@ -0,0 +1,38 @@
+CONFIG_RISCV=y
+CONFIG_HART_LOTTERY=n
+CONFIG_AVAILABLE_HARTS=n
+CONFIG_SYS_TEXT_BASE=0x8000
+CONFIG_TARGET_AX25_AE350=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_FIT=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_CMD_IMLS=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SF_TEST=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_PREFER_SERVERIP=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_BOARD=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC=y
+CONFIG_FTSDC010=y
+CONFIG_FTSDC010_SDIO=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_FLASH_CFI_DRIVER=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_FTMAC100=y
+CONFIG_BAUDRATE=38400
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_ATCSPI200_SPI=y
-- 
2.7.4

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[U-Boot] [PATCH 1/4] riscv: hart_lottery and available harts feature can be seletable

2019-04-22 Thread Andes
From: Rick Chen 

In smp flow this two features only can be enabled when U-Boot
boot from ram. It shall be disabled when U-Boot boot from flash.

Add CONFIG_HART_LOTTERY and CONFIG_AVAILABLE_HARTS to select
this two features. Their default value will say YES for booting
from ram.

AE350 will encounter the the write failure problem since
hart_lottery and available_harts_lock was not in ram address
but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disable this two features.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/Kconfig   | 21 +
 arch/riscv/cpu/cpu.c |  4 
 arch/riscv/cpu/start.S   |  9 -
 arch/riscv/include/asm/global_data.h |  2 ++
 arch/riscv/lib/asm-offsets.c |  2 ++
 arch/riscv/lib/smp.c |  2 ++
 6 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ae8ff7b..4354396 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -162,6 +162,27 @@ config SBI_IPI
default y if RISCV_SMODE
depends on SMP
 
+config HART_LOTTERY
+   bool "Hart lottery support"
+   default y
+   depends on SMP
+   help
+ This will upport hart lottery, all harts have changce to become
+ main hart. But if you say N here, hart 0 will be the main hart.
+ It only can be enabled when U-Boot boot from ram, but shall be
+ disabled when boot from flash.
+
+config AVAILABLE_HARTS
+   bool "available harts support"
+   default y
+   depends on SMP
+   depends on HART_LOTTERY
+   help
+ This will help to record active harts and compare with dts' cpus.
+ So it will not send ipi to in-active harts.
+ It only can be enabled when U-Boot boot from ram, but shall be
+ disabled when boot from flash.
+
 config STACK_SIZE_SHIFT
int
default 13
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index c32de8a..0add783 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -16,13 +16,17 @@
  * before the bss section is available.
  */
 phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+#ifdef CONFIG_HART_LOTTERY
 u32 hart_lottery __attribute__((section(".data"))) = 0;
+#endif
 
+#ifdef CONFIG_AVAILABLE_HARTS
 /*
  * The main hart running U-Boot has acquired available_harts_lock until it has
  * finished initialization of global data.
  */
 u32 available_harts_lock = 1;
+#endif
 
 static inline bool supports_extension(char ext)
 {
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a4433fb..d030d4a 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -98,6 +98,7 @@ call_board_init_f_0:
mv  sp, a0
 #endif
 
+#ifdef CONFIG_HART_LOTTERY
/*
 * Pick hart to initialize global data and run U-Boot. The other harts
 * wait for initialization to complete.
@@ -106,6 +107,9 @@ call_board_init_f_0:
li  s2, 1
amoswap.w s2, t1, 0(t0)
bnezs2, wait_for_gd_init
+#else
+   bneztp, secondary_hart_loop
+#endif
 
la  t0, prior_stage_fdt_address
SREGs1, 0(t0)
@@ -115,6 +119,7 @@ call_board_init_f_0:
/* save the boot hart id to global_data */
SREGtp, GD_BOOT_HART(gp)
 
+#ifdef CONFIG_AVAILABLE_HARTS
la  t0, available_harts_lock
fence   rw, w
amoswap.w zero, zero, 0(t0)
@@ -135,13 +140,15 @@ wait_for_gd_init:
 
fence   rw, w
amoswap.w zero, zero, 0(t0)
+#endif
 
+#ifdef CONFIG_HART_LOTTERY
/*
 * Continue on hart lottery winner, others branch to
 * secondary_hart_loop.
 */
bnezs2, secondary_hart_loop
-
+#endif
/* Enable cache */
jal icache_enable
jal dcache_enable
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index dffcd45..e2e8b65 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -27,7 +27,9 @@ struct arch_global_data {
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
+#ifdef CONFIG_AVAILABLE_HARTS
ulong available_harts;
+#endif
 };
 
 #include 
diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c
index f998402..3ebda97 100644
--- a/arch/riscv/lib/asm-offsets.c
+++ b/arch/riscv/lib/asm-offsets.c
@@ -14,7 +14,9 @@
 int main(void)
 {
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
+#ifdef CONFIG_AVAILABLE_HARTS
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
+#endif
 
return 0;
 }
diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index caa292c..4de7ea2 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -63,9 +63,11 @@ static int send_ipi_many(struct ipi_data *ipi)

[U-Boot] [PATCH 0/4] AE350 support SMP boot from flash

2019-04-22 Thread Andes
From: Rick Chen 

In current RISC-V SMP flow, AE350 will encounter the the write
failure problem since hart_lottery and available_harts_lock was
not in ram address but in flash address when booing from flash.

This patch can help to fix the failure problem when AE350 was
booting from flash by disable this two features.

Rick Chen (4):
  riscv: hart_lottery and available harts feature can be seletable
  riscv: configs: Support AE350 SMP boot from flash flow
  riscv: prior_stage_fdt_address only be used when OF_PRIOR_STAGE is
enable
  riscv: configs: AE350 will use OF_PRIOR_STAGE when boot from ram

 arch/riscv/Kconfig   | 21 
 arch/riscv/cpu/cpu.c |  4 
 arch/riscv/cpu/start.S   | 11 ++-
 arch/riscv/include/asm/global_data.h |  2 ++
 arch/riscv/lib/asm-offsets.c |  2 ++
 arch/riscv/lib/smp.c |  2 ++
 configs/ae350_rv32_defconfig |  2 +-
 configs/ae350_rv32_xip_defconfig | 37 +++
 configs/ae350_rv64_defconfig |  2 +-
 configs/ae350_rv64_xip_defconfig | 38 
 10 files changed, 118 insertions(+), 3 deletions(-)
 create mode 100644 configs/ae350_rv32_xip_defconfig
 create mode 100644 configs/ae350_rv64_xip_defconfig

-- 
2.7.4

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[U-Boot] [PATCH] riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure

2019-04-02 Thread Andes
From: Rick Chen 

It occurs since commit 27cb7300ffda
("Ensure device tree DTS is compiled").

More details can refer to
89c2b5c02049aea746b1edee0b4e1d8519dec2f4
ARM: fix arch/arm/dts/Makefile

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
 arch/riscv/dts/Makefile | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index b400def..f9cd606 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
-- 
2.7.4

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[U-Boot] [PATCH v4 6/6] riscv: ae350: enable SMP

2019-04-02 Thread Andes
From: Rick Chen 

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 board/AndesTech/ax25-ae350/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/AndesTech/ax25-ae350/Kconfig 
b/board/AndesTech/ax25-ae350/Kconfig
index 44cb302..5e682b6 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -24,5 +24,6 @@ config ENV_OFFSET
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
+   imply SMP
 
 endif
-- 
2.7.4

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[U-Boot] [PATCH v4 5/6] riscv: dts: ae350 support SMP

2019-04-02 Thread Andes
From: Rick Chen 

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 arch/riscv/dts/ae350_32.dts | 81 +
 arch/riscv/dts/ae350_64.dts | 81 +
 2 files changed, 118 insertions(+), 44 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0679827..2ec01a5 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -26,16 +26,49 @@
status = "okay";
compatible = "riscv";
riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
mmu-type = "riscv,sv32";
clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
+   next-level-cache = <>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
+   CPU1: cpu@1 {
+   device_type = "cpu";
+   reg = <1>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv32";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = <>;
+   CPU1_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "riscv,cpu-intc";
+   };
+   };
+
+   L2: l2-cache@e050 {
+   compatible = "cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x4>;
+   };
};
 
memory@0 {
@@ -46,32 +79,32 @@
soc {
#address-cells = <1>;
#size-cells = <1>;
-   compatible = "andestech,riscv-ae350-soc";
+   compatible = "simple-bus";
ranges;
 
-   plic0: interrupt-controller@e400 {
-   compatible = "riscv,plic0";
-   #address-cells = <1>;
-   #interrupt-cells = <1>;
-   interrupt-controller;
-   reg = <0xe400 0x200>;
-   riscv,ndev=<71>;
-   interrupts-extended = <_intc 11 _intc 9>;
-   };
+   plic0: interrupt-controller@e400 {
+   compatible = "riscv,plic0";
+   #address-cells = <1>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   reg = <0xe400 0x200>;
+   riscv,ndev=<71>;
+   interrupts-extended = <_intc 11 _intc 9 
_intc 11 _intc 9>;
+   };
 
-   plic1: interrupt-controller@e640 {
-   compatible = "riscv,plic1";
-   #address-cells = <1>;
-   #interrupt-cells = <1>;
-   interrupt-controller;
-   reg = <0xe640 0x40>;
-   riscv,ndev=<1>;
-   interrupts-extended = <_intc 3>;
-   };
+   plic1: interrupt-controller@e640 {
+   compatible = "riscv,plic1";
+   #address-cells = <1>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   reg = <0xe640 0x40>;
+   riscv,ndev=<2>;
+   interrupts-extended = <_intc 3 _intc 3>;
+   };
 
-   plmt0@e600 {
-   compatible = "riscv,plmt0";
-   interrupts-extended = <_intc 7>;
+   plmt0@e600 {
+   compatible = "riscv,plmt0";
+   interrupts-extended = <_intc 7 _intc 7>;
reg = <0xe600 0x10>;
};
};
@@ -146,6 +179,10 @@
interrupt-parent = <>;
};
 
+   pmu {
+   compatible = "riscv,base-pmu";
+   };
+
virtio_mmio@fe007000 {

[U-Boot] [PATCH v4 2/6] riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-02 Thread Andes
From: Rick Chen 

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
---
Changes in v4:
- Rename nds_plmt as andes_plmt

 arch/riscv/Kconfig   |  9 ++
 arch/riscv/include/asm/global_data.h |  3 ++
 arch/riscv/include/asm/syscon.h  |  1 +
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/andes_plmt.c  | 53 
 5 files changed, 67 insertions(+)
 create mode 100644 arch/riscv/lib/andes_plmt.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 511768b..ae8ff7b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config ANDES_PLIC
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
+config ANDES_PLMT
+   bool
+   depends on RISCV_MMODE
+   select REGMAP
+   select SYSCON
+   help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
 config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index b867910..dffcd45 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,6 +21,9 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLIC
void __iomem *plic; /* plic base address */
 #endif
+#ifdef CONFIG_ANDES_PLMT
+   void __iomem *plmt; /* plmt base address */
+#endif
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index a086208..26a008c 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -13,6 +13,7 @@ enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller (PLIC) */
+   RISCV_SYSCON_PLMT,  /* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1bf554b..1c332db 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,6 +12,7 @@ obj-y += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
new file mode 100644
index 000..84f4607
--- /dev/null
+++ b/arch/riscv/lib/andes_plmt.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen 
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* mtime register */
+#define MTIME_REG(base)((ulong)(base))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLMT_BASE_GET(void)\
+   do {\
+   long *ret;  \
+   \
+   if (!gd->arch.plmt) {   \
+   ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
+   if (IS_ERR(ret))\
+   return PTR_ERR(ret);\
+   gd->arch.plmt = ret;\
+   }   \
+   } while (0)
+
+int riscv_get_time(u64 *time)
+{
+   PLMT_BASE_GET();
+
+   *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+
+   return 0;
+}
+
+static const struct udevice_id andes_plmt_ids[] = {
+   { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+   { }
+};
+
+U_BOOT_DRIVER(andes_plmt) = {
+   .name   = "andes_plmt",
+   .id = UCLASS_SYSCON,
+   .of_match   = andes_plmt_ids,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.7.4

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[U-Boot] [PATCH v4 4/6] riscv: ax25: Andes specific cache shall only support in M-mode

2019-04-02 Thread Andes
From: Rick Chen 

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 68bd4e9..6b4b92e 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
+   depends on RISCV_MMODE
help
  Provide Andes Technology AndeStar V5 families specific cache support.
 
-- 
2.7.4

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[U-Boot] [PATCH v4 3/6] riscv: ax25: Add platform-specific Kconfig options

2019-04-02 Thread Andes
From: Rick Chen 

Add ax25 RISC-V platform-specific Kconfig options,
to include CPU and timer drivers. Also disable
ATCPIT100 SoC timer and replace by PLMT.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
Reviewed-by: Lukas Auer 
---
Changes in v4:
- Squash disable ATCPIT100 timer as 
patch 3 riscv: ax25: Add platform-specific Kconfig options

 arch/riscv/cpu/ax25/Kconfig  | 6 ++
 configs/ae350_rv32_defconfig | 1 -
 configs/ae350_rv64_defconfig | 1 -
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index e9dbca2..68bd4e9 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,5 +1,11 @@
 config RISCV_NDS
bool
+   select ARCH_EARLY_INIT_R
+   imply CPU
+   imply CPU_RISCV
+   imply RISCV_TIMER
+   imply ANDES_PLIC if RISCV_MMODE
+   imply ANDES_PLMT if RISCV_MMODE
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig
index 5837b48..e13c7de 100644
--- a/configs/ae350_rv32_defconfig
+++ b/configs/ae350_rv32_defconfig
@@ -33,4 +33,3 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
diff --git a/configs/ae350_rv64_defconfig b/configs/ae350_rv64_defconfig
index b250d3f..a41f918 100644
--- a/configs/ae350_rv64_defconfig
+++ b/configs/ae350_rv64_defconfig
@@ -34,4 +34,3 @@ CONFIG_BAUDRATE=38400
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
 CONFIG_ATCSPI200_SPI=y
-CONFIG_ATCPIT100_TIMER=y
-- 
2.7.4

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[U-Boot] [PATCH v4 0/6] AE350 SMP support RISC-V

2019-04-02 Thread Andes
From: Rick Chen 

Changes in v4:
Patch 1
- Drop the empty comment line
- Check return value after cpu_get_count()
- Rename nds_plic as andes_plic
- Fix checkpatch error issues
Patch 2
- Rename nds_plmt as andes_plmt
Patch 3 riscv: ae350: disable ATCPIT100 timer
Patch 4 riscv: ax25: Add platform-specific Kconfig options
- Squash as patch 3 riscv: ax25: Add platform-specific Kconfig options

Changes in v3:
Patch 1
- Rename plic_init() as enable_ipi()
- Remove PLIC_BASE_GET() from enable_ipi()
Patch 2
- Add a space before (PLMT)
Patch 6
- Fix some mis-alignments
- Recovery isa string of CPU1

Changes in v2:
- Drop patch1 and replace by simple-bus driver
- Rename nds_plic as andes_plic
- Move initialize plic to PLIC_BASE_GET() and called automatically
- Rename nds_plmt as andes_plmt
- Recovery dts isa string

Rick Chen (6):
  riscv: Add a SYSCON driver for Andestech's PLIC
  riscv: Add a SYSCON driver for Andestech's PLMT
  riscv: ax25: Add platform-specific Kconfig options
  riscv: ax25: Andes specific cache shall only support in M-mode
  riscv: dts: ae350 support SMP
  riscv: ae350: enable SMP

 arch/riscv/Kconfig   |  18 ++
 arch/riscv/cpu/ax25/Kconfig  |   7 +++
 arch/riscv/dts/ae350_32.dts  |  81 ++---
 arch/riscv/dts/ae350_64.dts  |  81 ++---
 arch/riscv/include/asm/global_data.h |   6 ++
 arch/riscv/include/asm/syscon.h  |   4 +-
 arch/riscv/lib/Makefile  |   2 +
 arch/riscv/lib/andes_plic.c  | 113 +++
 arch/riscv/lib/andes_plmt.c  |  53 
 board/AndesTech/ax25-ae350/Kconfig   |   1 +
 configs/ae350_rv32_defconfig |   1 -
 configs/ae350_rv64_defconfig |   1 -
 12 files changed, 320 insertions(+), 48 deletions(-)
 create mode 100644 arch/riscv/lib/andes_plic.c
 create mode 100644 arch/riscv/lib/andes_plmt.c

-- 
2.7.4

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[U-Boot] [PATCH v4 1/6] riscv: Add a SYSCON driver for Andestech's PLIC

2019-04-02 Thread Andes
From: Rick Chen 

The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
---
Changes in V4:
- Drop the empty comment line
- Check return value after cpu_get_count()
- Rename nds_plic as andes_plic
- Fix checkpatch error issues

 arch/riscv/Kconfig   |   9 +++
 arch/riscv/include/asm/global_data.h |   3 +
 arch/riscv/include/asm/syscon.h  |   3 +-
 arch/riscv/lib/Makefile  |   1 +
 arch/riscv/lib/andes_plic.c  | 113 +++
 5 files changed, 127 insertions(+), 2 deletions(-)
 create mode 100644 arch/riscv/lib/andes_plic.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3a4470d..511768b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -109,6 +109,15 @@ config SIFIVE_CLINT
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
 
+config ANDES_PLIC
+   bool
+   depends on RISCV_MMODE
+   select REGMAP
+   select SYSCON
+   help
+ The Andes PLIC block holds memory-mapped claim and pending registers
+ associated with software interrupt.
+
 config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index 80e3165..b867910 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,6 +18,9 @@ struct arch_global_data {
 #ifdef CONFIG_SIFIVE_CLINT
void __iomem *clint;/* clint base address */
 #endif
+#ifdef CONFIG_ANDES_PLIC
+   void __iomem *plic; /* plic base address */
+#endif
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index d311ee6..a086208 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -8,12 +8,11 @@
 
 /*
  * System controllers in a RISC-V system
- *
- * So far only SiFive's Core Local Interruptor (CLINT) is defined.
  */
 enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
+   RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller (PLIC) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 35dbf64..1bf554b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c
new file mode 100644
index 000..2ffe49a
--- /dev/null
+++ b/arch/riscv/lib/andes_plic.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen 
+ *
+ * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC).
+ * The PLIC block holds memory-mapped claim and pending registers
+ * associated with software interrupt.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* pending register */
+#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + (hart) * 8)
+/* enable register */
+#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
+/* claim register */
+#define CLAIM_REG(base, hart)  ((ulong)(base) + 0x24 + (hart) * 0x1000)
+
+#define ENABLE_HART_IPI (0x80808080)
+#define SEND_IPI_TO_HART(hart)  (0x80 >> (hart))
+
+DECLARE_GLOBAL_DATA_PTR;
+static int init_plic(void);
+
+#define PLIC_BASE_GET(void)\
+   do {\
+   long *ret;  \
+   \
+   if (!gd->arch.plic) {   \
+   ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
+   if (IS_ERR(ret))\
+   return PTR_ERR(ret);\
+   gd->arch.plic = ret;\
+   init_plic();\
+   }   \
+   } while (0)
+
+static int enable_ipi(int harts)
+{
+   int i;
+   int en = ENABLE_HART_IPI;
+
+   for (i = 0; i < harts; i++) {
+   en = en >> i;
+   writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, i));
+ 

[U-Boot] [PATCH v3 5/7] riscv: ax25: Andes specific cache shall only support in M-mode

2019-04-01 Thread Andes
From: Rick Chen 

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/ax25/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 68bd4e9..6b4b92e 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
+   depends on RISCV_MMODE
help
  Provide Andes Technology AndeStar V5 families specific cache support.
 
-- 
2.7.4

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[U-Boot] [PATCH v3 7/7] riscv: ae350: enable SMP

2019-04-01 Thread Andes
From: Rick Chen 

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
---
 board/AndesTech/ax25-ae350/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/board/AndesTech/ax25-ae350/Kconfig 
b/board/AndesTech/ax25-ae350/Kconfig
index 44cb302..5e682b6 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -24,5 +24,6 @@ config ENV_OFFSET
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select RISCV_NDS
+   imply SMP
 
 endif
-- 
2.7.4

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[U-Boot] [PATCH v3 6/7] riscv: dts: ae350 support SMP

2019-04-01 Thread Andes
From: Rick Chen 

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
---
V3:
 - Fix some mis-alignments.
 - Recovery isa string of CPU1.

 arch/riscv/dts/ae350_32.dts | 81 +
 arch/riscv/dts/ae350_64.dts | 81 +
 2 files changed, 118 insertions(+), 44 deletions(-)

diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 0679827..2ec01a5 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -26,16 +26,49 @@
status = "okay";
compatible = "riscv";
riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
mmu-type = "riscv,sv32";
clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
d-cache-size = <0x8000>;
d-cache-line-size = <32>;
+   next-level-cache = <>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
+   CPU1: cpu@1 {
+   device_type = "cpu";
+   reg = <1>;
+   status = "okay";
+   compatible = "riscv";
+   riscv,isa = "rv32imafdc";
+   riscv,priv-major = <1>;
+   riscv,priv-minor = <10>;
+   mmu-type = "riscv,sv32";
+   clock-frequency = <6000>;
+   i-cache-size = <0x8000>;
+   i-cache-line-size = <32>;
+   d-cache-size = <0x8000>;
+   d-cache-line-size = <32>;
+   next-level-cache = <>;
+   CPU1_intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "riscv,cpu-intc";
+   };
+   };
+
+   L2: l2-cache@e050 {
+   compatible = "cache";
+   cache-level = <2>;
+   cache-size = <0x4>;
+   reg = <0x0 0xe050 0x0 0x4>;
+   };
};
 
memory@0 {
@@ -46,32 +79,32 @@
soc {
#address-cells = <1>;
#size-cells = <1>;
-   compatible = "andestech,riscv-ae350-soc";
+   compatible = "simple-bus";
ranges;
 
-   plic0: interrupt-controller@e400 {
-   compatible = "riscv,plic0";
-   #address-cells = <1>;
-   #interrupt-cells = <1>;
-   interrupt-controller;
-   reg = <0xe400 0x200>;
-   riscv,ndev=<71>;
-   interrupts-extended = <_intc 11 _intc 9>;
-   };
+   plic0: interrupt-controller@e400 {
+   compatible = "riscv,plic0";
+   #address-cells = <1>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   reg = <0xe400 0x200>;
+   riscv,ndev=<71>;
+   interrupts-extended = <_intc 11 _intc 9 
_intc 11 _intc 9>;
+   };
 
-   plic1: interrupt-controller@e640 {
-   compatible = "riscv,plic1";
-   #address-cells = <1>;
-   #interrupt-cells = <1>;
-   interrupt-controller;
-   reg = <0xe640 0x40>;
-   riscv,ndev=<1>;
-   interrupts-extended = <_intc 3>;
-   };
+   plic1: interrupt-controller@e640 {
+   compatible = "riscv,plic1";
+   #address-cells = <1>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   reg = <0xe640 0x40>;
+   riscv,ndev=<2>;
+   interrupts-extended = <_intc 3 _intc 3>;
+   };
 
-   plmt0@e600 {
-   compatible = "riscv,plmt0";
-   interrupts-extended = <_intc 7>;
+   plmt0@e600 {
+   compatible = "riscv,plmt0";
+   interrupts-extended = <_intc 7 _intc 7>;
reg = <0xe600 0x10>;
};
};
@@ -146,6 +179,10 @@
interrupt-parent = <>;
};
 
+   pmu {
+   compatible = "riscv,base-pmu";
+   };
+
virtio_mmio@fe007000 {

[U-Boot] [PATCH v3 4/7] riscv: ax25: Add platform-specific Kconfig options

2019-04-01 Thread Andes
From: Rick Chen 

Add ax25 RISC-V platform-specific Kconfig options, to include
CPU and timer drivers.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
---
 arch/riscv/cpu/ax25/Kconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index e9dbca2..68bd4e9 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -1,5 +1,11 @@
 config RISCV_NDS
bool
+   select ARCH_EARLY_INIT_R
+   imply CPU
+   imply CPU_RISCV
+   imply RISCV_TIMER
+   imply ANDES_PLIC if RISCV_MMODE
+   imply ANDES_PLMT if RISCV_MMODE
help
  Run U-Boot on AndeStar V5 platforms and use some specific features
  which are provided by Andes Technology AndeStar V5 families.
-- 
2.7.4

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[U-Boot] [PATCH v3 2/7] riscv: Add a SYSCON driver for Andestech's PLMT

2019-04-01 Thread Andes
From: Rick Chen 

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.

Signed-off-by: Rick Chen 
Cc: Greentime Hu 
Reviewed-by: Bin Meng 
---
V3:
 - Add a space before (PLMT).

 arch/riscv/Kconfig   |  9 ++
 arch/riscv/include/asm/global_data.h |  3 ++
 arch/riscv/include/asm/syscon.h  |  1 +
 arch/riscv/lib/Makefile  |  1 +
 arch/riscv/lib/andes_plmt.c  | 53 
 5 files changed, 67 insertions(+)
 create mode 100644 arch/riscv/lib/andes_plmt.c

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 511768b..ae8ff7b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -118,6 +118,15 @@ config ANDES_PLIC
  The Andes PLIC block holds memory-mapped claim and pending registers
  associated with software interrupt.
 
+config ANDES_PLMT
+   bool
+   depends on RISCV_MMODE
+   select REGMAP
+   select SYSCON
+   help
+ The Andes PLMT block holds memory-mapped mtime register
+ associated with timer tick.
+
 config RISCV_RDTIME
bool
default y if RISCV_SMODE
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index b867910..dffcd45 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,6 +21,9 @@ struct arch_global_data {
 #ifdef CONFIG_ANDES_PLIC
void __iomem *plic; /* plic base address */
 #endif
+#ifdef CONFIG_ANDES_PLMT
+   void __iomem *plmt; /* plmt base address */
+#endif
 #ifdef CONFIG_SMP
struct ipi_data ipi[CONFIG_NR_CPUS];
 #endif
diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
index c1b4b86..6e12574 100644
--- a/arch/riscv/include/asm/syscon.h
+++ b/arch/riscv/include/asm/syscon.h
@@ -14,6 +14,7 @@ enum {
RISCV_NONE,
RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
RISCV_SYSCON_PLIC,  /* Platform Level Interrupt Controller (PLIC) */
+   RISCV_SYSCON_PLMT,  /* Platform Level Machine Timer (PLMT) */
 };
 
 #endif /* _ASM_SYSCON_H */
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 1bf554b..1c332db 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -12,6 +12,7 @@ obj-y += cache.o
 obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
 obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
+obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
diff --git a/arch/riscv/lib/andes_plmt.c b/arch/riscv/lib/andes_plmt.c
new file mode 100644
index 000..12d7e0e
--- /dev/null
+++ b/arch/riscv/lib/andes_plmt.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019, Rick Chen 
+ *
+ * U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
+ * The PLMT block holds memory-mapped mtime register
+ * associated with timer tick.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* mtime register */
+#define MTIME_REG(base)((ulong)(base))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define PLMT_BASE_GET(void)\
+   do {\
+   long *ret;  \
+   \
+   if (!gd->arch.plmt) {   \
+   ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
+   if (IS_ERR(ret))\
+   return PTR_ERR(ret);\
+   gd->arch.plmt = ret;\
+   }   \
+   } while (0)
+
+int riscv_get_time(u64 *time)
+{
+   PLMT_BASE_GET();
+
+   *time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
+
+   return 0;
+}
+
+static const struct udevice_id nds_plmt_ids[] = {
+   { .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
+   { }
+};
+
+U_BOOT_DRIVER(nds_plmt) = {
+   .name   = "nds_plmt",
+   .id = UCLASS_SYSCON,
+   .of_match   = nds_plmt_ids,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.7.4

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