bitbanging the SPI using the
> generic soft-spi driver might be easier ;-/
AR9331 SPI controller has special shift register for reading received data,
so you have no need in reading every single receiving MISO bit with separate
gpio access, this can give a small speedup. Next, in openwrt tree there is
a dirty-hacky ath79-spi linux kernel patch for very impressive SPI flash
read speedup (2 MiB/s instead of 20 KiB/s, I have no precise bandwidth
results at the moment).
So for better performance it is reasonable to have separate ath79-spi driver.
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Best regards,
Antony Pavlov
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t;dcache enable".
I so sorry! My bad: your lowlevel_init actually does not contain any cache code.
common code from arch/mips/cpu/start.S calls mips_cache_reset just after
invoking lowlevel_init.
> On 12/19/2015 12:16 AM, Antony Pavlov wrote:
> > On Fri, 18 Dec 2015 23:24:22 +0800
>
On Fri, 18 Dec 2015 23:24:22 +0800
Wills Wang wrote:
> On 12/18/2015 08:54 PM, Antony Pavlov wrote:
> > On Fri, 18 Dec 2015 15:34:29 +0800
> > Wills Wang wrote:
> >
> >> This patch enable work for ar933x SOC, tested on ar9331
> >>
> >> Signed-of
g:
Applying: mips: add base support for atheros ar71xx based SOCs
.git/rebase-apply/patch:1180: new blank line at EOF.
+
.git/rebase-apply/patch:2069: new blank line at EOF.
+
warning: 2 lines add whitespace errors.
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Antony Pavlov
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On Fri, 31 Oct 2014 12:35:18 +0400
Antony Pavlov wrote:
>
> $ time busybox tftp -g -r antony/16M -l 16M tftpserver
^^
> antony/16M 100% |**| 16384k
> 0:00:00 ETA
>
>
han
> > just boot an OS ...
>
> It seems some bootloader or x86 PXE (I do not know where it is
> implemented) have TCP support. So, that may not be that uncommon
> after all, and there is maybe even some code to take from these
> implementations, because they are
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