While configuring SerDes, errors could be encountered, in these cases,
return instead of going ahead. This is will help in booting even if
configuration of SerDes fails.
Signed-off-by: Aswath Govindraju
---
board/ti/j721e/evm.c | 32 ++--
1 file changed, 22
Hi Rasmus,
On 19/05/22 16:58, Rasmus Villemoes wrote:
> On 19/05/2022 12.41, Aswath Govindraju wrote:
>> Hi Rasmus,
>>
>> On 19/05/22 14:40, Rasmus Villemoes wrote:
>>> Asking if the alias we found actually points at the device tree node
>>> we passed in (in
Hi Rasmus,
On 19/05/22 14:40, Rasmus Villemoes wrote:
> Asking if the alias we found actually points at the device tree node
> we passed in (in the guise of its offset from blob) can be done simply
> by asking if the fdt_path_offset() of the alias' path is identical to
> offset.
>
> In fact, the
The node name of the bus in the device tree has changed. Also, the length
argument to be passed should be the length of new value. Therefore, fix the
path to usb device tree node as well as the length argument passed.
Signed-off-by: Aswath Govindraju
---
arch/arm/mach-k3/am6_init.c | 4 ++--
1
Sync the configs required for enabling checks for size of image and stack
from generic r5 defconfig file.
Signed-off-by: Aswath Govindraju
---
configs/am65x_evm_r5_usbdfu_defconfig | 5 +
configs/am65x_evm_r5_usbmsc_defconfig | 5 +
2 files changed, 10 insertions(+)
diff --git
The following series of patches along with [1], fix usb boot modes
on AM654 IDK board.
[1] - https://patchwork.ozlabs.org/project/uboot/list/?series=300845
Aswath Govindraju (3):
arm: dts: k3-am654-r5-base-board: Fix the dt properties in usb0
instance
arm: mach-k3: am6_init: Fix the path
For dfu boot mode, the clocks property needs to be deleted and dr_mode
needs to be set to peripheral. Therefore, add the required fixes for the
same.
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/k3-am654-r5-base-board-u-boot.dtsi | 2 +-
arch/arm/dts/k3-am654-r5-base-board.dts | 1
nal checks added for these in the dwc3_glue_probe().
Fixes: 142d50fbce7c ("usb: dwc3: Add support for usb3-phy PHY configuration")
Signed-off-by: Aswath Govindraju
---
drivers/usb/dwc3/dwc3-generic.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff
│
├┤
│▲ │
││ │
│ STACK │
├┤0x8048
│ Memory for Load│
│ Buffer Allocation │
├┤0x8080
││
│U-Boot Image│
││
└┘
Signed-off-by: Aswath Govindraju
Add support for AM62 USB wrapper for DWC3 Controller in AM62 SoC.
Signed-off-by: Aswath Govindraju
---
Link to corresponding kernel dt-bindings and driver patches,
- https://patchwork.kernel.org/project/linux-usb/list/?series=629613
drivers/usb/dwc3/Kconfig | 7 +
drivers/usb/dwc3
t; Signed-off-by: Patrick Delaunay
Reviewed-by: Aswath Govindraju
Thanks,
Aswath
> ---
>
> doc/usage/mmc.rst | 36
> 1 file changed, 20 insertions(+), 16 deletions(-)
>
> diff --git a/doc/usage/mmc.rst b/doc/usage/mmc.rst
> index 02b5d7b1c
Initialization and power on operations of links have been moved under the
link device in the Sierra SerDes driver. Also, the UCLASS of
sierra_phy_provider has been changed to UCLASS_MISC.
Therefore, fix the probing of SerDes0 instance accordingly.
Signed-off-by: Aswath Govindraju
Reviewed
no longer the
phy device.
Fixes: 6f46c7441a9f ("phy: cadence: Sierra: Add a UCLASS_PHY device for links")
Signed-off-by: Aswath Govindraju
Reviewed-by: Georgi Vlaev
---
drivers/phy/cadence/phy-cadence-sierra.c | 59
1 file changed, 20 insertions(+), 39 dele
The following series of patches fix USB DFU in U-Boot for J721e.
Aswath Govindraju (2):
phy: cadence: Sierra: Move the link operations from serdes phy to link
device
board: ti: j721e: evm.c: Fix the probing of in Sierra SerDes0
board/ti/j721e/evm.c | 28
QSGMII PHY present on the j721e common processor board requires
to be initialized before the core boots up. Therefore, run the
corresponding command during boot to do the same.
Signed-off-by: Aswath Govindraju
---
configs/j721e_hs_evm_a72_defconfig | 2 +-
1 file changed, 1 insertion(+), 1
Add the command "boot_rprocs" that is required for booting remote
processors in U-Boot.
Fixes: 5980925e2a5a ("include: configs: j721e_evm: Add support to boot ethfw
core in j721e")
Reported-by: Jesse Villarreal
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72
, remove dorprocboot that is being set by default.
Fixes: 5980925e2a5a ("include: configs: j721e_evm: Add support to boot ethfw
core in j721e")
Reported-by: Suman Anna
Signed-off-by: Aswath Govindraju
---
include/configs/j721e_evm.h | 19 +--
1 file changed, 17 insert
such that the QSGMII PHY initialization is only applicable for
J721E EVM
- Rearranged the order of PHY initialization and boot_rpocs in the bootcmd
- Added reported-bys
- Split the fix into two patches.
Aswath Govindraju (3):
include: configs: j721e_evm.h: Fix the env variable corresponding to
QSGMII
Hi,
On 18/02/22 6:59 pm, Aswath Govindraju wrote:
> The following series of patches fix the bootcmd for J721e,
> - adds the command 'run boot_rpocs' for booting remote processors
> from U-Boot (As it was earlier)
> - removes setting of dorprocboot to 1. Since this should be
>
Sync up the bootcmd with GP configs, to initialize the QSGMII phy required
for ethfw.
Signed-off-by: Aswath Govindraju
---
configs/j721e_hs_evm_a72_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/j721e_hs_evm_a72_defconfig
b/configs
.
Therefore, fix the bootcmd to reflect the same.
Fixes: 5980925e2a5a ("include: configs: j721e_evm: Add support to boot ethfw
core in j721e")
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 1 -
2 files changed, 1 insertion(+), 2
with GP.
Aswath Govindraju (2):
configs: j721e_evm_a72_defconfig: Fix the bootcmd
configs: j721e_hs_evm_a72_defconfig: Sync up the bootcmd with GP
configs
configs/j721e_evm_a72_defconfig| 2 +-
configs/j721e_hs_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h| 1 -
3 files
Enable config for setting mmc speed mode from U-Boot command line.
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig| 1 +
configs/j721e_hs_evm_a72_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/j721e_evm_a72_defconfig b/configs
Hi All,
On 27/01/22 2:42 pm, Aswath Govindraju wrote:
> The following series of patches,
> - add support for MultiLink on Sierra SerDes
> - Also adds the required to configs, dt node changes
> to enable this on J721e common processor board.
>
> Notes:
> - Patches 1, 2, 3,
Add configs to enable booting ethfw core in j721e
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 19 ++-
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs
Add support for QSGMII multilink configuration.
Signed-off-by: Aswath Govindraju
---
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 5 +
arch/arm/dts/k3-j721e-common-proc-board.dts| 14 +++---
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 12 ++--
3
-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 58 +---
1 file changed, 42 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 95cdd39cb367..d95d4b432a98 100644
--- a/drivers
From: Swapnil Jakhade
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 378 ++-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git
From: Swapnil Jakhade
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 153 +--
1 file changed, 145 insertions
From: Swapnil Jakhade
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 218 ++-
1
From: Swapnil Jakhade
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 35
1 file changed, 35 insertions(+)
diff --git a/drivers
From: Swapnil Jakhade
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence
From: Swapnil Jakhade
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 38
1 file
From: Swapnil Jakhade
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 12 ++--
1 file changed, 6 insertions
From: Swapnil Jakhade
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers
From: Swapnil Jakhade
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence
From: Swapnil Jakhade
Add binding to specify Spread Spectrum Clocking mode used
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
include/dt-bindings/phy/phy-cadence.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/phy/phy-cadence.h
b/include
to the link nodes in U-Boot device tree file.
Signed-off-by: Aswath Govindraju
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 10
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 24 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common
Add support for probing, initializing and powering, SerDes0 instance.
Signed-off-by: Aswath Govindraju
---
board/ti/j721e/evm.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 077d83420c9c..ad85b9d50115
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
driver in kernel.
Signed-off-by: Aswath Govindraju
---
drivers/phy/ti/phy-j721e-wiz.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 116 +++
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence
From: Kishon Vijay Abraham I
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/cadence/phy
by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 25 ++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index ea
From: Kishon Vijay Abraham I
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 19 +++
1 file
-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadenc
From: Kishon Vijay Abraham I
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22
t;phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/dri
From: Sanket Parmar
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 27
and SIERRA_PHY_PMA_LANE_CDB_OFFSET in patches 18 and 21.
Aswath Govindraju (8):
phy: cadence: Sierra: Add a UCLASS_PHY device for links
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
phy: ti: phy-j721e-wiz.c: Fix the condition for setting P_ENABLE_FORCE
board: ti: j721e: evm.c
-asserting
in probe. Fix it here.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadenc
by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 25 ++--
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index ea
t;phy" (or "link"
for old device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/dri
Skip the phy configuration if the required configurations were done in an
earlier boot stage.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 55 +---
1 file changed, 40 insertions(+), 15 deletions(-)
diff --git a/drivers/phy/cadence/phy
Add configs to enable booting ethfw core in j721e
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
include/configs/j721e_evm.h | 19 ++-
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/configs/j721e_evm_a72_defconfig b/configs
Add support for QSGMII multilink configuration.
Signed-off-by: Aswath Govindraju
---
.../arm/dts/k3-j721e-common-proc-board-u-boot.dtsi | 5 +
arch/arm/dts/k3-j721e-common-proc-board.dts| 14 +++---
arch/arm/dts/k3-j721e-r5-common-proc-board.dts | 12 ++--
3
From: Swapnil Jakhade
Add register sequences for PCIe + QSGMII PHY multilink configuration.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 378 ++-
1 file changed, 377 insertions(+), 1 deletion(-)
diff --git
From: Swapnil Jakhade
Add support for multilink configuration of Sierra PHY. Currently,
maximum two links are supported.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 153 +--
1 file changed, 145 insertions
From: Swapnil Jakhade
Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 218 ++-
1
From: Swapnil Jakhade
PIPE phy status is used to communicate the completion of several PHY
functions. Check if PHY is ready for operation while configured for
PIPE mode during startup.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence
From: Swapnil Jakhade
Check if PMA cmn_ready is set indicating the startup process is complete.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 35
1 file changed, 35 insertions(+)
diff --git a/drivers
From: Swapnil Jakhade
Add PHY PCS common register configuration sequences for single link.
Update single link PCIe register sequence accordingly.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 38
1 file
From: Swapnil Jakhade
No functional change. Rename some regmap variables as mentioned in Sierra
register description documentation.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 12 ++--
1 file changed, 6 insertions
From: Swapnil Jakhade
Sierra driver currently supports single link configurations only. Prepare
driver to support multilink multiprotocol configurations along with
different SSC modes.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence
From: Swapnil Jakhade
Add support to get SSC type from DT.
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers
From: Swapnil Jakhade
Add binding to specify Spread Spectrum Clocking mode used
Signed-off-by: Swapnil Jakhade
Signed-off-by: Aswath Govindraju
---
include/dt-bindings/phy/phy-cadence.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/phy/phy-cadence.h
b/include
to the link nodes in U-Boot device tree file.
Signed-off-by: Aswath Govindraju
---
.../k3-j721e-common-proc-board-u-boot.dtsi| 10
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 24 +++
2 files changed, 34 insertions(+)
diff --git a/arch/arm/dts/k3-j721e-common
Add support for probing, initializing and powering, SerDes0 instance.
Signed-off-by: Aswath Govindraju
---
board/ti/j721e/evm.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c
index 077d83420c9c..ad85b9d50115
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.
Signed-off-by: Aswath
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes
instance.
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 116 +++
1 file changed, 75 insertions(+), 41 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the
driver in kernel.
Signed-off-by: Aswath Govindraju
---
drivers/phy/ti/phy-j721e-wiz.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index
From: Kishon Vijay Abraham I
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove().
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/cadence/phy
From: Kishon Vijay Abraham I
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 19 +++
1 file
From: Kishon Vijay Abraham I
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22
v5.17-rc1
- Patch 24, syncs with linux kernel dt, with the following patch
https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=608996
Aswath Govindraju (8):
phy: cadence: Sierra: Add a UCLASS_PHY device for links
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1
From: Sanket Parmar
Updated values of USB3 related Sierra PHY registers.
This change fixes USB3 device disconnect issue observed
while enternig U1/U2 state.
Signed-off-by: Sanket Parmar
Signed-off-by: Aswath Govindraju
---
drivers/phy/cadence/phy-cadence-sierra.c | 27
Hi All,
On 18/01/22 12:57 pm, Aswath Govindraju wrote:
> The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
> providing advanced system integration in automotive ADAS applications and
> industrial applications requiring AI at the network edge. This SoC extends
> t
From: David Huang
Enable A72 specific configs for J721S2
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Hari Nagalla
---
configs/j721s2_evm_a72_defconfig | 207 +++
1 file changed, 207 insertions
From: David Huang
Enable R5 SPL specific configs for J721S2.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Hari Nagalla
---
configs/j721s2_evm_r5_defconfig | 171
1 file changed, 171 insertions
Add initial support for device tree that runs on R5.
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/Makefile | 3 +-
.../dts/k3-j721s2-r5-common-proc-board.dts| 196 ++
2 files changed, 198 insertions(+), 1 deletion(-)
create mode 100644 arch
out in the common processor board.
Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/Makefile | 1 +
.../k3-j721s2-common-proc-board-u-boot.dtsi | 149 ++
arch/arm/dts/k3-j721s2-common-proc-board.dts |
Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28
Introduce basic support for the J721S2 SoC.
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Nishanth Menon
---
arch/arm/dts/k3-j721s2-main.dtsi
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.
Signed-off-by: Aswath Govindraju
---
arch/arm/dts/k3-j721s2-som-p0.dtsi | 173 +
1 file
do not need parentheses enclosing the values for this
macro as we do intend it to generate two separate values as has been
done for other similar platforms.
Signed-off-by: Aswath Govindraju
---
include/dt-bindings/pinctrl/k3.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt
There are 4 lanes in the single instance of J721S2 SERDES. Each SERDES
lane mux can select upto 4 different IPs. Define all the possible
functions.
Signed-off-by: Aswath Govindraju
---
include/dt-bindings/mux/ti-serdes.h | 22 ++
1 file changed, 22 insertions(+)
diff --git
From: David Huang
Add board support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
board/ti/j721s2/Kconfig | 63 +
board/ti/j721s2/MAINTAINERS | 16
board/ti/j721s2/Makefile| 8 ++
board/ti/j721s2/evm.c | 180
From: David Huang
Add support for J721S2 SoC identification.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/soc/soc_ti_k3.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index 9abed7d490a2..c8f7a5768775
From: David Huang
Add support for DDR subsystem in J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/ram/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index a79594d35198..709c916a2a11
From: David Huang
Add support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/power/domain/ti-power-domain.c | 5 +
include/k3-dev.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/power/domain/ti-power-domain.c
From: David Huang
Add support for J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/clk/ti/clk-k3.c | 5 +
include/k3-clk.h| 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
index e04c57eff252
From: David Huang
Add support for DMA in J721S2 SoC.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j721s2.c | 167 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
drivers
From: David Huang
Add basic support for J721S2 SoC definition
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Dave Gerlach
Signed-off-by: Nishanth Menon
Signed-off-by: Hari Nagalla
---
arch/arm/mach-k3/Kconfig | 15 +-
arch/arm/mach-k3
for a different EMIF port, by default set to 3
Add support for configuring all the above by using a MSMC device
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 158
1 file changed, 158 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b
The current driver only supports single instance of DRR subsystem. Add
support for probing multiple instances of DDR subsystem.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 138
1 file changed, 87 insertions(+), 51 deletions(-)
diff
in the MAINTAINERS baord folder
Changes since v1:
- Removed unused serial aliases
- Assigned serial2 alias for main uart8 instance
- Moved aliases to respective board files
Aswath Govindraju (10):
ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance
ram: k3-ddrss: Add support
Add a pointer to ddr instance int the lpddr4_privatedata_s structure for
supporting mutliple instances of DDR in the drivers.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/lpddr4_structs_if.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ram/k3-ddrss
From: Nishanth Menon
If there is an optional boot notification channel that an SoC uses
separate from the rx path, use the same.
Signed-off-by: Nishanth Menon
---
.../remoteproc/k3-system-controller.txt | 3 +++
drivers/remoteproc/k3_system_controller.c | 20 ++-
2
Hi all,
On 11/01/22 1:25 pm, Aswath Govindraju wrote:
> The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
> providing advanced system integration in automotive ADAS applications and
> industrial applications requiring AI at the network edge. This SoC extends
> t
From: David Huang
Enable A72 specific configs for J721S2
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Hari Nagalla
---
configs/j721s2_evm_a72_defconfig | 207 +++
1 file changed, 207 insertions
From: David Huang
Enable R5 SPL specific configs for J721S2.
Signed-off-by: David Huang
Signed-off-by: Aswath Govindraju
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Hari Nagalla
---
configs/j721s2_evm_r5_defconfig | 171
1 file changed, 171 insertions
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