Re: [PATCH 1/2] cache: sifive: clear out the error irqs on init

2023-09-08 Thread Ben Dooks 

On 08/09/2023 14:37, Ben Dooks wrote:

We are getting a number of cache errors on starting an OS,
so to try and avoid this, clear the errors when we first
probe the cache.

Signed-off-by: Ben Dooks 
[ben.do...@codethink.co.uk: changed from sifive.com address]


As a follow-up, this hasn't been checked to see if it fixes the
unmatched or other fuXXX cores. If someone could test it on
others and see if it removes the issues, then it would be more
than worth getting this merged.

--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

[PATCH 2/2] sifive: ccache: add clear LIM area

2023-09-08 Thread Ben Dooks 
Add option to clear the LIM area on startup, just in case this
is the cause of some of the data-errors on startup.

Signed-off-by: Ben Dooks 
[ben.do...@codethink.co.uk: changed from sifive.com address]
---
 drivers/cache/Kconfig   |  8 ++
 drivers/cache/cache-sifive-ccache.c | 40 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index abe7de9abf..9d5cbaedea 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -46,6 +46,14 @@ config SIFIVE_CCACHE
  This driver is for SiFive Composable L2/L3 cache. It enables cache
  ways of composable cache.
 
+config SIFIVE_CCACHE_LIMZERO
+   bool "Zero LIM (loosely integrated memory) on startup"
+   depends on SIFIVE_CCACHE
+   help
+ Select this option to clear the LIM (cache memory) block before
+ enabling the cache. This will increase the init time but may
+ help with some of the errors being seen on OS startup.
+
 config SIFIVE_PL2CACHE
bool "SiFive per-core L2 cache"
select CACHE
diff --git a/drivers/cache/cache-sifive-ccache.c 
b/drivers/cache/cache-sifive-ccache.c
index 178bdcc82d..a84b5c9d04 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -8,6 +8,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define SIFIVE_CCACHE_CONFIG   0x000
@@ -43,6 +44,43 @@ static int sifive_ccache_get_info(struct udevice *dev, 
struct cache_info *info)
return 0;
 }
 
+#ifdef CONFIG_SIFIVE_CCACHE_LIMZERO
+static int sifive_clear_lim(struct udevice *dev)
+{
+
+   fdt_addr_t base, size;
+   ofnode mem_node;
+   u32 handle = 0;
+   int ret;
+
+   ret = ofnode_read_u32(dev_ofnode(dev), "memory-region", );
+   if (ret) {
+   dev_err(dev, "no memory-region for lim\n");
+   return -EINVAL;
+   }
+
+   mem_node = ofnode_get_by_phandle(handle);
+   if (!ofnode_valid(mem_node)) {
+   dev_err(dev, "invalid memory region for lim\n");
+   return -EINVAL;
+   }
+
+   base = ofnode_get_addr_size_index(mem_node, 0, );
+
+   /* note, we assume this is called so early none of the ways of
+* the cache have been enabled, so just clear the entire cache
+* memory
+*/
+
+   dev_info(dev, "clearing l3lim %llx..%llx\n", base, base+size);
+   memset((void *)base, 0x0, size);
+
+   return 0;
+}
+#else
+static inline int sifive_clear_lim(struct udevice *dev) { return 0; }
+#endif
+
 static const struct cache_ops sifive_ccache_ops = {
.enable = sifive_ccache_enable,
.get_info = sifive_ccache_get_info,
@@ -63,6 +101,8 @@ static int sifive_ccache_probe(struct udevice *dev)
(void)readl(base + 0x148);
(void)readl(base + 0x168);
 
+   sifive_clear_lim(dev);
+
return 0;
 }
 
-- 
2.40.1

[PATCH 1/2] cache: sifive: clear out the error irqs on init

2023-09-08 Thread Ben Dooks 
We are getting a number of cache errors on starting an OS,
so to try and avoid this, clear the errors when we first
probe the cache.

Signed-off-by: Ben Dooks 
[ben.do...@codethink.co.uk: changed from sifive.com address]
---
 drivers/cache/cache-sifive-ccache.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/cache/cache-sifive-ccache.c 
b/drivers/cache/cache-sifive-ccache.c
index 540e7df138..178bdcc82d 100644
--- a/drivers/cache/cache-sifive-ccache.c
+++ b/drivers/cache/cache-sifive-ccache.c
@@ -51,11 +51,18 @@ static const struct cache_ops sifive_ccache_ops = {
 static int sifive_ccache_probe(struct udevice *dev)
 {
struct sifive_ccache *priv = dev_get_priv(dev);
+   void __iomem *base;
 
-   priv->base = dev_read_addr_ptr(dev);
+   priv->base = base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;
 
+   /* read and clear any current errors, possilbly from reset */
+   (void)readl(base + 0x108);
+   (void)readl(base + 0x128);
+   (void)readl(base + 0x148);
+   (void)readl(base + 0x168);
+
return 0;
 }
 
-- 
2.40.1

[[PATCH v2]] riscv: add backtrace support

2023-09-05 Thread Ben Dooks 
When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.

Signed-off-by: Ben Dooks 
---
v2:
  - back to codethink email as sifive account is now gone
  - add option to build SPL with frame pointer
(as suggested by Bo Gan 
---
 arch/riscv/Kconfig  | 20 
 arch/riscv/Makefile |  4 
 arch/riscv/cpu/start.S  |  1 +
 arch/riscv/lib/interrupts.c | 35 +++
 4 files changed, 60 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6771d8d919..a446166631 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -111,6 +111,26 @@ config ARCH_RV64I
 
 endchoice
 
+config FRAMEPOINTER
+   bool "Build with frame pointer for stack unwinding"
+   help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+
+config SPL_FRAMEPOINTER
+   bool "Build SPL with frame pointer for stack unwinding"
+   help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+
 choice
prompt "Code Model"
default CMODEL_MEDLOW
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4963b5109b..0cb60c7c7e 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -45,6 +45,10 @@ endif
 ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 -mcmodel=$(CMODEL)
 
+ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y)
+   ARCH_FLAGS += -fno-omit-frame-pointer
+endif
+
 PLATFORM_CPPFLAGS  += $(ARCH_FLAGS)
 CFLAGS_EFI += $(ARCH_FLAGS)
 
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 30cf674370..53de424378 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -419,6 +419,7 @@ call_board_init_r:
  */
mv  a0, s3  /* gd_t */
mv  a1, s4  /* dest_addr */
+   mv  s0, zero/* fp == NULL */
 
 /*
  * jump to it ...
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index e966afa7e3..db3d7e294b 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -53,6 +53,40 @@ static void show_regs(struct pt_regs *regs)
 #endif
 }
 
+#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER)
+static void show_backtrace(struct pt_regs *regs)
+{
+   uintptr_t *fp = (uintptr_t *)regs->s0;
+   unsigned count = 0;
+   ulong ra;
+
+   printf("backtrace:\n");
+
+   /* there are a few entry points where the s0 register is
+* set to gd, so to avoid changing those, just abort if
+* the value is the same */
+   while (fp != NULL && fp != (uintptr_t *)gd) {
+   ra = fp[-1];
+   printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT,
+  count, (ulong)fp, ra);
+
+   if (gd && gd->flags & GD_FLG_RELOC)
+   printf(" - RA: " REG_FMT " reloc adjusted\n",
+   ra - gd->reloc_off);
+   else
+   printf("\n");
+
+   fp = (uintptr_t *)fp[-2];
+   count++;
+   }
+}
+#else
+static void show_backtrace(struct pt_regs *regs)
+{
+   printf("No backtrace support enabled\n");
+}
+#endif
+
 /**
  * instr_len() - get instruction length
  *
@@ -119,6 +153,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, 
struct pt_regs *regs)
   epc - gd->reloc_off, regs->ra - gd->reloc_off);
 
show_regs(regs);
+   show_backtrace(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");
-- 
2.40.1

Re: [PATCH v2] dt-bindings: riscv: deprecate riscv,isa

2023-07-03 Thread Ben Dooks 
 specification.
+
+  zicsr:
+type: boolean
+description:
+  The standard Zicsr extension for control and status register
+  instructions, as ratified in the 20191213 version of the unprivileged
+  ISA specification.
+
+  zifencei:
+type: boolean
+description:
+  The standard Zifencei extension for instruction-fetch fence, as
+  ratified in the 20191213 version of the unprivileged ISA
+  specification.
+
+  zihintpause:
+type: boolean
+description: |
+  The standard Zihintpause extension for pause hints, as ratified in
+  commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
+
+  zihpm:
+type: boolean
+description:
+  The standard Zihpm extension for hardware performance counters, as
+  ratified in the 20191213 version of the unprivileged ISA
+  specification.
+
+  ztso:
+type: boolean
+description:
+  The standard Ztso extension for total store ordering, as ratified in
+  commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual.
+
+additionalProperties: true
+...


--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH 2/3] riscv: implement local_irq_{save,restore} macros

2023-06-23 Thread Ben Dooks 




On 2023-06-12 08:47, Leo Liang wrote:

Hi Ben,

On Fri, May 05, 2023 at 09:02:06AM +0100, Ben Dooks wrote:

Add implementations of the local_irq_{save,restore} macros so that
 can be used with riscv.

Signed-off-by: Ben Dooks 
---
 arch/riscv/include/asm/system.h | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/include/asm/system.h 
b/arch/riscv/include/asm/system.h

index 9d8e43e394..78093681e5 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -7,15 +7,22 @@
 #ifndef __ASM_RISCV_SYSTEM_H
 #define __ASM_RISCV_SYSTEM_H

+#include 
+
 struct event;

 /*
- * Interrupt configuring macros.
- *
- * TODO
- *
+ * Interupt configuration macros
  */

+#define local_irq_save(__flags) do { \


Can we have this "do" in a new line just like what kernel does?


+__flags = csr_read_clear(CSR_SSTATUS, SR_SIE) & SR_SIE;\
+  } while (0)
+
+#define local_irq_restore(__flags) do { \
+csr_set(CSR_SSTATUS, __flags & SR_SIE); \
+  } while(0)

^
a space missing

+
 /* Hook to set up the CPU (called from SPL too) */
 int riscv_cpu_setup(void *ctx, struct event *event);



If you don't mind, I could make these format modification on my side,
so you don't have to spin another patch set.

Best regards,
Leo


Yes that's fine, this got buried under a lot of other work.

Thank you.

--
Ben

Re: [PATCH] riscv: add backtrace support

2023-06-16 Thread Ben Dooks 

On 15/06/2023 20:01, Bo Gan wrote:

On 6/14/23 10:15 AM, Ben Dooks wrote:

On 14/06/2023 07:25, Bo Gan wrote:

On 5/25/23 4:05 AM, Ben Dooks wrote:

On 15/05/2023 14:03, Ben Dooks wrote:

When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.


Hi, has anyone had time to review this?



Hi Ben, this looks really useful. I'd like to use it in SPL,
but I'm unable to enable CONFIG_SPL_FRAMEPOINTER=y. It's likely
that you need to add a SPL_FRAMEPOINTER entry to Kconfig as well.


I will have a look at this, but testing may not be easy as the
setup we're using has limited SPL space.



I did a hack (duplicate `config FRAMEPOINTER` to `config SPL_FRAMEPOINTER`)

--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -63,6 +63,24 @@ config SPL_SYS_DCACHE_OFF
+config SPL_FRAMEPOINTER
+   bool "Build with frame pointer for stack unwinding"


I think this should have been "Build SPL with...


+   depends on SPL
+   help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+

This is sufficient for enabling CONFIG_SPL_FRAMEPOINTER=y. With this, I
tested SPL on JH7110 (VisionFive 2), and observed your patch's working:


Ok, thank you for testing.

If I put this into v2 of the patch, do you want crediting with
a co-author tag?


Unhandled exception: Load access fault
EPC: 0800335e RA: 080033e8 TVAL: 0040

SP:  080ff5b0 GP:  080dbda0 TP:  
T0:  080ffb20 T1:  0020 T2:  
S0:  080ffb20 S1:  080ff6d0 A0:  
A1:  080ff6d0 A2:  08020d83 A3:  080ffb20
A4:  0025 A5:  08040218 A6:  0020
A7:  0800 S2:  0013 S3:  0001
S4:  4000 S5:  0001 S6:  000a
S7:  080ffb88 S8:  0200 S9:  0801bc60
S10: 080fff38 S11:  T3:  0023
T4:  0006 T5:  0001869f T6:  080dd138
backtrace:
backtrace  0: FP: 080ffb20 RA: 08005888
backtrace  1: FP: 080ffb80 RA: 08007046
backtrace  2: FP: 080ffc50 RA: 080024ec
backtrace  3: FP: 080ffd00 RA: 080028e0
backtrace  4: FP: 080ffe00 RA: 08002cf6
backtrace  5: FP: 080fff30 RA: 08002144
backtrace  6: FP: 0810 RA: 08000178

Code: 6797 0002 b783 1ba7 050e 953e 6108 6422 (613c)

Looks like you just need a `config SPL_FRAMEPOINTER` entry in Kconfig.



--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH] riscv: add backtrace support

2023-06-14 Thread Ben Dooks 

On 14/06/2023 07:25, Bo Gan wrote:

On 5/25/23 4:05 AM, Ben Dooks wrote:

On 15/05/2023 14:03, Ben Dooks wrote:

When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.


Hi, has anyone had time to review this?



Hi Ben, this looks really useful. I'd like to use it in SPL,
but I'm unable to enable CONFIG_SPL_FRAMEPOINTER=y. It's likely
that you need to add a SPL_FRAMEPOINTER entry to Kconfig as well.


I will have a look at this, but testing may not be easy as the
setup we're using has limited SPL space.

--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH] ubifs: allow loading to above 4GiB

2023-06-06 Thread Ben Dooks 

On 05/06/2023 08:45, Heiko Schocher wrote:

Hello Ben,

On 10.05.23 15:41, Ben Dooks wrote:

The ubifsload command is truncating any address above 4GiB as it casts
this address to an u32, instead of using an unsigned long which most of
the other load commands do. Change this to an unsigned long to allow
loading into high memory for boards which use these areas.

Fixes the following error:

=> ubifsload 0x21 /boot/Image.lzma
Loading file '/boot/Image.lzma' to addr 0x...
Unhandled exception: Store/AMO access fault

Signed-off-by: Ben Dooks 
---
  cmd/ubifs.c   | 2 +-
  fs/ubifs/ubifs.c  | 4 ++--
  include/ubifs_uboot.h | 2 +-
  3 files changed, 4 insertions(+), 4 deletions(-)


just started azure build and it drops errors:

https://dev.azure.com/hs0298/hs/_build/results?buildId=105=results

for example
https://dev.azure.com/hs0298/hs/_build/results?buildId=103=results

2023-06-05T07:34:39.9304987Z + tools/buildman/buildman -o /tmp/vexpress_ca9x4 
-w -E -W -e --board
vexpress_ca9x4
2023-06-05T07:34:45.4735755Z Building current source for 1 boards (1 thread, 2 
jobs per thread)
2023-06-05T07:34:45.4735947Z
2023-06-05T07:34:45.4736063Z Starting build...
2023-06-05T07:34:45.4736188Z
2023-06-05T07:34:45.4736233Z
2023-06-05T07:35:02.4142452Z 000 /1   -1  (starting)
2023-06-05T07:35:02.4150636Z
2023-06-05T07:35:02.4150787Zarm:  +   vexpress_ca9x4
2023-06-05T07:35:02.4150964Z +In file included from include/linux/printk.h:4,
2023-06-05T07:35:02.4151140Z + from include/common.h:20,
2023-06-05T07:35:02.4152527Z + from cmd/ubifs.c:14:
2023-06-05T07:35:02.4152796Z +cmd/ubifs.c: In function 'do_ubifs_load':
2023-06-05T07:35:02.4153181Z +cmd/ubifs.c:136:15: error: format '%x' expects 
argument of type
'unsigned int', but argument 3 has type 'long unsigned int' [-Werror=format=]
2023-06-05T07:35:02.4153550Z +  136 | debug("Loading file '%s' to 
address 0x%08x (size
%d)\n", filename, addr, size);
2023-06-05T07:35:02.4153758Z +  |   
^
2023-06-05T07:35:02.4154045Z +include/log.h:155:21: note: in definition of 
macro 'pr_fmt'
2023-06-05T07:35:02.4154220Z +  155 | #define pr_fmt(fmt) fmt
2023-06-05T07:35:02.4154344Z +  | ^~~
2023-06-05T07:35:02.4154571Z +include/log.h:272:9: note: in expansion of macro 
'debug_cond'
2023-06-05T07:35:02.4155974Z +  272 | debug_cond(_DEBUG, fmt, ##args)
2023-06-05T07:35:02.4156144Z +  | ^~
2023-06-05T07:35:02.4156393Z +cmd/ubifs.c:136:9: note: in expansion of macro 
'debug'
2023-06-05T07:35:02.4156541Z +  | ^
2023-06-05T07:35:02.4156769Z +cmd/ubifs.c:136:50: note: format string is 
defined here
2023-06-05T07:35:02.4156947Z +  |   
~~~^
2023-06-05T07:35:02.4157068Z +  |   
   |
2023-06-05T07:35:02.4157202Z +  |   
   unsigned int
2023-06-05T07:35:02.4157341Z +  |   
%08lx
2023-06-05T07:35:02.4157475Z +cc1: all warnings being treated as errors
2023-06-05T07:35:02.4157660Z +make[2]: *** [scripts/Makefile.build:256: 
cmd/ubifs.o] Error 1
2023-06-05T07:35:02.4157845Z +make[1]: *** [Makefile:1853: cmd] Error 2
2023-06-05T07:35:02.4158061Z +make: *** [Makefile:177: sub-make] Error 2

Please fix it, thanks!


I've just sent v2 with the debug print sorted.

--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

[PATCHv2] ubifs: allow loading to above 4GiB

2023-06-06 Thread Ben Dooks 
The ubifsload command is truncating any address above 4GiB as it casts
this address to an u32, instead of using an unsigned long which most of
the other load commands do. Change this to an unsigned long to allow
loading into high memory for boards which use these areas.

Fixes the following error:

=> ubifsload 0x21 /boot/Image.lzma
Loading file '/boot/Image.lzma' to addr 0x...
Unhandled exception: Store/AMO access fault

Signed-off-by: Ben Dooks 
Signed-off-by: Ben Dooks 
---
v2:
  - fixed debug print
---
 cmd/ubifs.c   | 4 ++--
 fs/ubifs/ubifs.c  | 4 ++--
 include/ubifs_uboot.h | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/cmd/ubifs.c b/cmd/ubifs.c
index 6a01d0988a..2a035bc7ae 100644
--- a/cmd/ubifs.c
+++ b/cmd/ubifs.c
@@ -111,7 +111,7 @@ static int do_ubifs_load(struct cmd_tbl *cmdtp, int flag, 
int argc,
char *filename;
char *endp;
int ret;
-   u32 addr;
+   unsigned long addr;
u32 size = 0;
 
if (!ubifs_mounted) {
@@ -133,7 +133,7 @@ static int do_ubifs_load(struct cmd_tbl *cmdtp, int flag, 
int argc,
if (endp == argv[3])
return CMD_RET_USAGE;
}
-   debug("Loading file '%s' to address 0x%08x (size %d)\n", filename, 
addr, size);
+   debug("Loading file '%s' to address 0x%08lx (size %d)\n", filename, 
addr, size);
 
ret = ubifs_load(filename, addr, size);
if (ret) {
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index d3026e3101..609bdbf603 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -925,12 +925,12 @@ void ubifs_close(void)
 }
 
 /* Compat wrappers for common/cmd_ubifs.c */
-int ubifs_load(char *filename, u32 addr, u32 size)
+int ubifs_load(char *filename, unsigned long addr, u32 size)
 {
loff_t actread;
int err;
 
-   printf("Loading file '%s' to addr 0x%08x...\n", filename, addr);
+   printf("Loading file '%s' to addr 0x%08lx...\n", filename, addr);
 
err = ubifs_read(filename, (void *)(uintptr_t)addr, 0, size, );
if (err == 0) {
diff --git a/include/ubifs_uboot.h b/include/ubifs_uboot.h
index b025779d59..db8a29e9bb 100644
--- a/include/ubifs_uboot.h
+++ b/include/ubifs_uboot.h
@@ -21,7 +21,7 @@ int ubifs_init(void);
 int uboot_ubifs_mount(char *vol_name);
 void uboot_ubifs_umount(void);
 int ubifs_is_mounted(void);
-int ubifs_load(char *filename, u32 addr, u32 size);
+int ubifs_load(char *filename, unsigned long addr, u32 size);
 
 int ubifs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info);
 int ubifs_ls(const char *dir_name);
-- 
2.39.2

Re: [PATCH] riscv: add backtrace support

2023-05-25 Thread Ben Dooks 

On 15/05/2023 14:03, Ben Dooks wrote:

When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.


Hi, has anyone had time to review this?

As a note, my sifive.com address may go soon, so please
add ben.do...@codethink.co.uk to any followups.


Signed-off-by: Ben Dooks 
---
  arch/riscv/Kconfig  | 10 ++
  arch/riscv/Makefile |  4 
  arch/riscv/cpu/start.S  |  1 +
  arch/riscv/lib/interrupts.c | 35 +++
  4 files changed, 50 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f6ed05906a..3f2316cfb5 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -98,6 +98,16 @@ config ARCH_RV64I
  
  endchoice
  
+config FRAMEPOINTER

+   bool "Build with frame pointer for stack unwinding"
+   help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+
  choice
prompt "Code Model"
default CMODEL_MEDLOW
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4963b5109b..0cb60c7c7e 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -45,6 +45,10 @@ endif
  ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 -mcmodel=$(CMODEL)
  
+ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y)

+   ARCH_FLAGS += -fno-omit-frame-pointer
+endif
+
  PLATFORM_CPPFLAGS += $(ARCH_FLAGS)
  CFLAGS_EFI+= $(ARCH_FLAGS)
  
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S

index dad22bfea8..3d13722615 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -396,6 +396,7 @@ call_board_init_r:
   */
mv  a0, s3  /* gd_t */
mv  a1, s4  /* dest_addr */
+   mv  s0, zero/* fp == NULL */
  
  /*

   * jump to it ...
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index e966afa7e3..db3d7e294b 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -53,6 +53,40 @@ static void show_regs(struct pt_regs *regs)
  #endif
  }
  
+#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER)

+static void show_backtrace(struct pt_regs *regs)
+{
+   uintptr_t *fp = (uintptr_t *)regs->s0;
+   unsigned count = 0;
+   ulong ra;
+
+   printf("backtrace:\n");
+
+   /* there are a few entry points where the s0 register is
+* set to gd, so to avoid changing those, just abort if
+* the value is the same */
+   while (fp != NULL && fp != (uintptr_t *)gd) {
+   ra = fp[-1];
+   printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT,
+  count, (ulong)fp, ra);
+
+   if (gd && gd->flags & GD_FLG_RELOC)
+   printf(" - RA: " REG_FMT " reloc adjusted\n",
+   ra - gd->reloc_off);
+   else
+   printf("\n");
+
+   fp = (uintptr_t *)fp[-2];
+   count++;
+   }
+}
+#else
+static void show_backtrace(struct pt_regs *regs)
+{
+   printf("No backtrace support enabled\n");
+}
+#endif
+
  /**
   * instr_len() - get instruction length
   *
@@ -119,6 +153,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, 
struct pt_regs *regs)
   epc - gd->reloc_off, regs->ra - gd->reloc_off);
  
  	show_regs(regs);

+   show_backtrace(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");


--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: riscv: asm update for building ubifs

2023-05-25 Thread Ben Dooks 

On 05/05/2023 09:02, Ben Dooks wrote:

Fix misisng atomic and test_and_{set,clear}_bit macros to allow
the ubi/ubifs code to be built for riscv. These are fairly simple
but are not being used outside of ubifs on our builds.


Has anyone had a chance to review these for merging?

I may be losing the ben.do...@sifive.com address soon,
so please cc ben.do...@codethink.co.uk in further discussions


Ben Dooks (3):
   riscv: add generic link for 
   riscv: implement local_irq_{save,restore} macros
   riscv: define test_and_{set,clear}_bit in asm/bitops.h

  arch/riscv/include/asm/atomic.h | 14 ++
  arch/riscv/include/asm/bitops.h |  3 +++
  arch/riscv/include/asm/system.h | 15 +++
  3 files changed, 28 insertions(+), 4 deletions(-)
  create mode 100644 arch/riscv/include/asm/atomic.h



--
Ben Dooks   http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

[PATCH] riscv: add backtrace support

2023-05-15 Thread Ben Dooks 
When debugging, it is useful to have a backtrace to find
out what is in the call stack as the previous function (RA)
may not have been the culprit.

Since this adds size to the build, do not add it by default
and avoid putting it in the SPL build if not needed.

Signed-off-by: Ben Dooks 
---
 arch/riscv/Kconfig  | 10 ++
 arch/riscv/Makefile |  4 
 arch/riscv/cpu/start.S  |  1 +
 arch/riscv/lib/interrupts.c | 35 +++
 4 files changed, 50 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f6ed05906a..3f2316cfb5 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -98,6 +98,16 @@ config ARCH_RV64I
 
 endchoice
 
+config FRAMEPOINTER
+   bool "Build with frame pointer for stack unwinding"
+   help
+ Choose this option to use the frame pointer so the stack can be
+ unwound if needed. This is useful for tracing where faults came
+ from as the source may be several functions back
+
+ If you say Y here, then the code size will be increased due to
+ having to store the fp.
+
 choice
prompt "Code Model"
default CMODEL_MEDLOW
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 4963b5109b..0cb60c7c7e 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -45,6 +45,10 @@ endif
 ARCH_FLAGS = -march=$(RISCV_MARCH) -mabi=$(ABI) \
 -mcmodel=$(CMODEL)
 
+ifeq ($(CONFIG_$(SPL_)FRAMEPOINTER),y)
+   ARCH_FLAGS += -fno-omit-frame-pointer
+endif
+
 PLATFORM_CPPFLAGS  += $(ARCH_FLAGS)
 CFLAGS_EFI += $(ARCH_FLAGS)
 
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index dad22bfea8..3d13722615 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -396,6 +396,7 @@ call_board_init_r:
  */
mv  a0, s3  /* gd_t */
mv  a1, s4  /* dest_addr */
+   mv  s0, zero/* fp == NULL */
 
 /*
  * jump to it ...
diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index e966afa7e3..db3d7e294b 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -53,6 +53,40 @@ static void show_regs(struct pt_regs *regs)
 #endif
 }
 
+#if defined(CONFIG_FRAMEPOINTER) || defined(CONFIG_SPL_FRAMEPOINTER)
+static void show_backtrace(struct pt_regs *regs)
+{
+   uintptr_t *fp = (uintptr_t *)regs->s0;
+   unsigned count = 0;
+   ulong ra;
+
+   printf("backtrace:\n");
+
+   /* there are a few entry points where the s0 register is
+* set to gd, so to avoid changing those, just abort if
+* the value is the same */
+   while (fp != NULL && fp != (uintptr_t *)gd) {
+   ra = fp[-1];
+   printf("backtrace %2d: FP: " REG_FMT " RA: " REG_FMT,
+  count, (ulong)fp, ra);
+
+   if (gd && gd->flags & GD_FLG_RELOC)
+   printf(" - RA: " REG_FMT " reloc adjusted\n",
+   ra - gd->reloc_off);
+   else
+   printf("\n");
+
+   fp = (uintptr_t *)fp[-2];
+   count++;
+   }
+}
+#else
+static void show_backtrace(struct pt_regs *regs)
+{
+   printf("No backtrace support enabled\n");
+}
+#endif
+
 /**
  * instr_len() - get instruction length
  *
@@ -119,6 +153,7 @@ static void _exit_trap(ulong code, ulong epc, ulong tval, 
struct pt_regs *regs)
   epc - gd->reloc_off, regs->ra - gd->reloc_off);
 
show_regs(regs);
+   show_backtrace(regs);
show_code(epc);
show_efi_loaded_images(epc);
panic("\n");
-- 
2.39.2

[PATCH] ubifs: allow loading to above 4GiB

2023-05-10 Thread Ben Dooks 
The ubifsload command is truncating any address above 4GiB as it casts
this address to an u32, instead of using an unsigned long which most of
the other load commands do. Change this to an unsigned long to allow
loading into high memory for boards which use these areas.

Fixes the following error:

=> ubifsload 0x21 /boot/Image.lzma
Loading file '/boot/Image.lzma' to addr 0x...
Unhandled exception: Store/AMO access fault

Signed-off-by: Ben Dooks 
---
 cmd/ubifs.c   | 2 +-
 fs/ubifs/ubifs.c  | 4 ++--
 include/ubifs_uboot.h | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/cmd/ubifs.c b/cmd/ubifs.c
index 6a01d0988a..33fff6500e 100644
--- a/cmd/ubifs.c
+++ b/cmd/ubifs.c
@@ -111,7 +111,7 @@ static int do_ubifs_load(struct cmd_tbl *cmdtp, int flag, 
int argc,
char *filename;
char *endp;
int ret;
-   u32 addr;
+   unsigned long addr;
u32 size = 0;
 
if (!ubifs_mounted) {
diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c
index d3026e3101..609bdbf603 100644
--- a/fs/ubifs/ubifs.c
+++ b/fs/ubifs/ubifs.c
@@ -925,12 +925,12 @@ void ubifs_close(void)
 }
 
 /* Compat wrappers for common/cmd_ubifs.c */
-int ubifs_load(char *filename, u32 addr, u32 size)
+int ubifs_load(char *filename, unsigned long addr, u32 size)
 {
loff_t actread;
int err;
 
-   printf("Loading file '%s' to addr 0x%08x...\n", filename, addr);
+   printf("Loading file '%s' to addr 0x%08lx...\n", filename, addr);
 
err = ubifs_read(filename, (void *)(uintptr_t)addr, 0, size, );
if (err == 0) {
diff --git a/include/ubifs_uboot.h b/include/ubifs_uboot.h
index b025779d59..db8a29e9bb 100644
--- a/include/ubifs_uboot.h
+++ b/include/ubifs_uboot.h
@@ -21,7 +21,7 @@ int ubifs_init(void);
 int uboot_ubifs_mount(char *vol_name);
 void uboot_ubifs_umount(void);
 int ubifs_is_mounted(void);
-int ubifs_load(char *filename, u32 addr, u32 size);
+int ubifs_load(char *filename, unsigned long addr, u32 size);
 
 int ubifs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info);
 int ubifs_ls(const char *dir_name);
-- 
2.39.2

[PATCH] clk: sifive: only build sifive-prci.o for CONFIG_CLK_SIFIVE_PRCI

2023-05-09 Thread Ben Dooks 
If we're building non FU540/FU740 SoC drivers, then the sifive-prci.o
is not needed. Only build this when CONFIG_CLK_SIFIVE_PRCI is selected.

Signed-off-by: Ben Dooks 
---
 drivers/clk/sifive/Makefile | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index 51348b1ddc..84859d92ab 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,5 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0+
 
-obj-y += sifive-prci.o
-
-obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o
+obj-$(CONFIG_CLK_SIFIVE_PRCI) +=  sifive-prci.o fu540-prci.o fu740-prci.o
-- 
2.39.2

[PATCH 1/3] riscv: add generic link for

2023-05-05 Thread Ben Dooks 
Add a link from  to the generic one to allow
things like ubifs to be built. This can be extended with
riscv AMO ops at a later date.

Signed-off-by: Ben Dooks 
---
 arch/riscv/include/asm/atomic.h | 14 ++
 1 file changed, 14 insertions(+)
 create mode 100644 arch/riscv/include/asm/atomic.h

diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h
new file mode 100644
index 00..f541fb4daa
--- /dev/null
+++ b/arch/riscv/include/asm/atomic.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 SiFive, Inc.
+ */
+
+#ifndef __RISCV_ATOMIC_H
+#define __RISCV_ATOMIC_H
+
+/* use the generic asm/atomic.h until we define a better one */
+
+#include 
+#include 
+
+#endif
-- 
2.39.2

[PATCH 3/3] riscv: define test_and_{set,clear}_bit in asm/bitops.h

2023-05-05 Thread Ben Dooks 
These seem to be missing, and trying to build ubifs without them
is causing errors due to these being missing.

Signed-off-by: Ben Dooks 
---
 arch/riscv/include/asm/bitops.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h
index 536629bbec..35f1368b83 100644
--- a/arch/riscv/include/asm/bitops.h
+++ b/arch/riscv/include/asm/bitops.h
@@ -158,6 +158,9 @@ static inline unsigned long ffz(unsigned long word)
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
 
+#define test_and_set_bit   __test_and_set_bit
+#define test_and_clear_bit __test_and_clear_bit
+
 #define ext2_set_bit   test_and_set_bit
 #define ext2_clear_bit test_and_clear_bit
 #define ext2_test_bit  test_bit
-- 
2.39.2

[PATCH 2/3] riscv: implement local_irq_{save,restore} macros

2023-05-05 Thread Ben Dooks 
Add implementations of the local_irq_{save,restore} macros so that
 can be used with riscv.

Signed-off-by: Ben Dooks 
---
 arch/riscv/include/asm/system.h | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h
index 9d8e43e394..78093681e5 100644
--- a/arch/riscv/include/asm/system.h
+++ b/arch/riscv/include/asm/system.h
@@ -7,15 +7,22 @@
 #ifndef __ASM_RISCV_SYSTEM_H
 #define __ASM_RISCV_SYSTEM_H
 
+#include 
+
 struct event;
 
 /*
- * Interrupt configuring macros.
- *
- * TODO
- *
+ * Interupt configuration macros
  */
 
+#define local_irq_save(__flags) do { \
+__flags = csr_read_clear(CSR_SSTATUS, SR_SIE) & SR_SIE;\
+  } while (0)
+
+#define local_irq_restore(__flags) do { \
+csr_set(CSR_SSTATUS, __flags & SR_SIE); \
+  } while(0)
+
 /* Hook to set up the CPU (called from SPL too) */
 int riscv_cpu_setup(void *ctx, struct event *event);
 
-- 
2.39.2

riscv: asm update for building ubifs

2023-05-05 Thread Ben Dooks 
Fix misisng atomic and test_and_{set,clear}_bit macros to allow
the ubi/ubifs code to be built for riscv. These are fairly simple
but are not being used outside of ubifs on our builds.

Ben Dooks (3):
  riscv: add generic link for 
  riscv: implement local_irq_{save,restore} macros
  riscv: define test_and_{set,clear}_bit in asm/bitops.h

 arch/riscv/include/asm/atomic.h | 14 ++
 arch/riscv/include/asm/bitops.h |  3 +++
 arch/riscv/include/asm/system.h | 15 +++
 3 files changed, 28 insertions(+), 4 deletions(-)
 create mode 100644 arch/riscv/include/asm/atomic.h

-- 
2.39.2

Re: [PATCH] drivers: pci: pcie_dw_common: add upper-limit to iATU

2022-10-25 Thread Ben Dooks 

On 20/10/2022 17:13, Bin Meng wrote:

Hi Ben,

On Thu, Oct 20, 2022 at 11:51 PM Ben Dooks  wrote:


The 4.6 spec added an upper 32bits to the ATU limit, and since this
driver is already assuming the unrolled feature added in the 4.8
specification this really should be set.

This is causing a bug with testing against the QEMU model as it


I guess you are testing QEMU sifive_u machine with some mods to add a
DW PCIe controller, with U-Boot sifive_unmatched defconfig?

Could you please document the QEMU command line in the commit message?


Your guess is wrong, I'm not currently using the sifive_u. This is a
test projec to test some of the work we've been doing updating the
dw-pcie code for future work.

I'll try and sort out adding this to the sifive_u as an option but I
expect that won't be until next week.

I am wondering whether to add a flag to say use viewport 2 for
the config, as logging from the dw-pcie model is showing a lot of
updates to windows setting, then restoring the IO view and I am
guessing people aren't configuring minimal settings on the Synopsys
designs...


defaults the viewports to fully open and not setting this causes
the config viewport to become most of memory (obviously stopping
the emulated system working correctly)

Signed-off-by: Ben Dooks 
---
  drivers/pci/pcie_dw_common.c | 2 ++
  drivers/pci/pcie_dw_common.h | 1 +
  2 files changed, 3 insertions(+)

diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index e66fb1490a..9f8b016d11 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -73,6 +73,8 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int 
index,
  upper_32_bits(cpu_addr));
 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
  lower_32_bits(cpu_addr + size - 1));
+   dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
+upper_32_bits(cpu_addr + size - 1));
 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
  lower_32_bits(pci_addr));
 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
index 60bf966d5e..8ec6834fa1 100644
--- a/drivers/pci/pcie_dw_common.h
+++ b/drivers/pci/pcie_dw_common.h
@@ -32,6 +32,7 @@
  #define PCIE_ATU_UNR_LIMIT 0x10
  #define PCIE_ATU_UNR_LOWER_TARGET  0x14
  #define PCIE_ATU_UNR_UPPER_TARGET  0x18
+#define PCIE_ATU_UNR_UPPER_LIMIT   0x20

  #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
  #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
--


Regards,
Bin

[PATCH] drivers: pci: pcie_dw_common: add upper-limit to iATU

2022-10-20 Thread Ben Dooks 
The 4.6 spec added an upper 32bits to the ATU limit, and since this
driver is already assuming the unrolled feature added in the 4.8
specification this really should be set.

This is causing a bug with testing against the QEMU model as it
defaults the viewports to fully open and not setting this causes
the config viewport to become most of memory (obviously stopping
the emulated system working correctly)

Signed-off-by: Ben Dooks 
---
 drivers/pci/pcie_dw_common.c | 2 ++
 drivers/pci/pcie_dw_common.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index e66fb1490a..9f8b016d11 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -73,6 +73,8 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int 
index,
 upper_32_bits(cpu_addr));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
 lower_32_bits(cpu_addr + size - 1));
+   dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
+upper_32_bits(cpu_addr + size - 1));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
 lower_32_bits(pci_addr));
dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
index 60bf966d5e..8ec6834fa1 100644
--- a/drivers/pci/pcie_dw_common.h
+++ b/drivers/pci/pcie_dw_common.h
@@ -32,6 +32,7 @@
 #define PCIE_ATU_UNR_LIMIT 0x10
 #define PCIE_ATU_UNR_LOWER_TARGET  0x14
 #define PCIE_ATU_UNR_UPPER_TARGET  0x18
+#define PCIE_ATU_UNR_UPPER_LIMIT   0x20
 
 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
-- 
2.35.1

Re: [U-Boot] [PATCH v3 u-boot 1/3] usb: host: Add simple of glue driver for DWC3 USB Controllers integration

2018-04-12 Thread Ben Dooks 

On 12/04/18 09:05, Neil Armstrong wrote:

Hi Jean-Jacques,

On 11/04/2018 18:17, Jean-Jacques Hiblot wrote:



On 11/04/2018 17:08, Neil Armstrong wrote:

This is a port of the dwc3-of-simple driver from Linux to enable/deassert
clock and resets of a simple DWC3 Controller HW glue.

Signed-off-by: Neil Armstrong <narmstr...@baylibre.com>
---
   drivers/usb/host/Kconfig  |   7 +++
   drivers/usb/host/Makefile |   1 +
   drivers/usb/host/dwc3-of-simple.c | 109 
++
   3 files changed, 117 insertions(+)
   create mode 100644 drivers/usb/host/dwc3-of-simple.c

diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index a7249b7..6caa615 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -21,6 +21,13 @@ config USB_XHCI_DWC3

[...]


+
+static int dwc3_of_simple_clk_init(struct udevice *dev,
+   struct dwc3_of_simple *simple)
+{
+    int ret;
+
+    ret = clk_get_bulk(dev, >clks);
+    if (ret == -ENOTSUPP)


Must be ENOSYS instead of ENOTSUPP, otherwise probe fails on platform not using 
the clk framework


You are right, I naively used the same between reset and clock...



tested-by: Jean-Jacques hiblot <jjhib...@ti.com>


+    return 0;
+    if (ret)
+    return ret;
+
+#if CONFIG_IS_ENABLED(CLK)
+    ret = clk_enable_bulk(>clks);
+    if (ret) {
+    clk_release_bulk(>clks);
+    return ret;
+    }
+#endif
+
+    return 0;
+}


Is the above #if CONFIG_IS_ENABLED(CLK) avoidable?



[...]
Thanks,
Neil

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Re: [U-Boot] [RFC PATCH u-boot v2] ARM: arch-meson: build memory banks using reported memory from registers

2017-10-19 Thread Ben Dooks 

On 2017-10-19 14:22, Neil Armstrong wrote:
As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 
firmware

and a secondary BL32 firmware.
Since mid-2017, the reserved memory address of the BL31 firmware was 
moved

and grown for security reasons.

But mainline U-boot and Linux has the old address and size fixed.

These SoCs have a register interface to get the two firmware reserved
memory start and sizes.

This patch adds a dynamic reservation of the memory zones in the
device tree bootmem
reserved memory zone used by the kernel in early boot.
To be complete, the memory zones are also added to the EFI reserved 
zones.


[1] 
http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html


Changes since v1:
- switch to fdt rsv mem table and efi reserve memory
- replaced in_le32 by readl()

Signed-off-by: Neil Armstrong 
---
 arch/arm/include/asm/arch-meson/gxbb.h |  17 +
 arch/arm/mach-meson/board.c| 117 
++---

 board/amlogic/odroid-c2/odroid-c2.c|   7 ++
 board/amlogic/p212/p212.c  |   7 ++
 configs/odroid-c2_defconfig|   1 +
 configs/p212_defconfig |   1 +
 include/configs/meson-gxbb-common.h|   2 +-
 7 files changed, 143 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/arch-meson/gxbb.h
b/arch/arm/include/asm/arch-meson/gxbb.h
index 74d5290..117f796 100644
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -7,10 +7,27 @@
 #ifndef __GXBB_H__
 #define __GXBB_H__

+#define GXBB_FIRMWARE_MEM_SIZE 0x100
+
+#define GXBB_AOBUS_BASE0xc810
 #define GXBB_PERIPHS_BASE  0xc8834400
 #define GXBB_HIU_BASE  0xc883c000
 #define GXBB_ETH_BASE  0xc941

+/* Always-On Peripherals registers */
+#define GXBB_AO_ADDR(off)  (GXBB_AOBUS_BASE + ((off) << 2))
+
+#define GXBB_AO_SEC_GP_CFG0GXBB_AO_ADDR(0x90)
+#define GXBB_AO_SEC_GP_CFG3GXBB_AO_ADDR(0x93)
+#define GXBB_AO_SEC_GP_CFG4GXBB_AO_ADDR(0x94)
+#define GXBB_AO_SEC_GP_CFG5GXBB_AO_ADDR(0x95)
+
+#define GXBB_AO_MEM_SIZE_MASK  0x
+#define GXBB_AO_MEM_SIZE_SHIFT 16
+#define GXBB_AO_BL31_RSVMEM_SIZE_MASK  0x
+#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16
+#define GXBB_AO_BL32_RSVMEM_SIZE_MASK  0x
+
 /* Peripherals registers */
 #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))

diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
index e89c6aa..24733e1 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board.c
@@ -11,6 +11,9 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 

 DECLARE_GLOBAL_DATA_PTR;

@@ -34,16 +37,114 @@ int dram_init(void)
return 0;
 }

-int dram_init_banksize(void)
+phys_size_t get_effective_memsize(void)
 {
-   /* Reserve first 16 MiB of RAM for firmware */
-   gd->bd->bi_dram[0].start = 0x100;
-   gd->bd->bi_dram[0].size  = 0xf00;
-   /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
-   gd->bd->bi_dram[1].start = 0x1000;
-   gd->bd->bi_dram[1].size  = gd->ram_size - 0x1020;
-   return 0;
+   /* Size is reported in MiB, convert it in bytes */
+   return ((readl(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK)
+   >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M;
+}
+
+#ifdef CONFIG_MESON_GXBB
+/*
+ * Early Meson GXBB Firmware revision did not provide the reserved
+ * memory zones in the registers, keep fixed memory zone handling.
+ */
+
+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+   int ret;
+
+   /* Add first 16MiB reserved zone */
+   ret = fdt_add_mem_rsv(fdt, 0, GXBB_FIRMWARE_MEM_SIZE);
+   if (ret)
+   printf("Could not reserve zone @ 0x0\n");
+
+#if defined(CONFIG_EFI_LOADER)
+   efi_add_memory_map(0, ALIGN(GXBB_FIRMWARE_MEM_SIZE, EFI_PAGE_SIZE)
+   >> EFI_PAGE_SHIFT,
+  EFI_RESERVED_MEMORY_TYPE, false);
+#endif


Could you make a sub function that does most of this and then have
only one set of #if defined ?

Would anyone mind if efi_add_memory_map had a default 'null' 
implementation

if !CONFIG_EFI_LOADER ?


+
+   /* Add BL31 reserved zone */
+   ret = fdt_add_mem_rsv(fdt, 0x1000, 0x20);
+   if (ret)
+   printf("Could not reserve BL1 zone @ 0x1000\n");
+
+#if defined(CONFIG_EFI_LOADER)
+   efi_add_memory_map(0x1000,
+  ALIGN(0x20, EFI_PAGE_SIZE)
+   >> EFI_PAGE_SHIFT,
+  EFI_RESERVED_MEMORY_TYPE, false);
+#endif
+}
+#endif


Can we reduce the pre-processor load here, I'm not even sure
we're testing the entire file can be compiled.


+
+#ifdef CONFIG_MESON_GXL


you're mixing #ifdef and #if defined.


+void ft_cpu_setup(void *fdt, bd_t *bd)
+{
+   u64 bl31_size, bl31_start;
+   u64 bl32_size, bl32_start;
+   u32 reg;
+

Re: [U-Boot] [RFC PATCH u-boot] ARM: arch-meson: build memory banks using reported memory from registers

2017-10-19 Thread Ben Dooks 

On 2017-10-19 10:04, Neil Armstrong wrote:
As discussed at [1], the Amlogic Meson GX SoCs can embed a BL31 
firmware

and a secondary BL32 firmware.
Since mid-2017, the reserved memory address of the BL31 firmware was 
moved

and grown for security reasons.

But mainline U-boot and Linux has the old address and size fixed.

These SoCs have a register interface to get the two firmware reserved
memory start and sizes.

This patch adds a dynamic memory bank redistribution according to the
values in the firmware.

Note that the memory address ordering between BL31 and BL32 is not 
etablished,

so it must be determined dynamically.

[1] 
http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html


Signed-off-by: Neil Armstrong 
---
 arch/arm/include/asm/arch-meson/gxbb.h | 15 ++
 arch/arm/mach-meson/board.c| 99 
+++---

 include/configs/meson-gxbb-common.h|  2 +-
 3 files changed, 109 insertions(+), 7 deletions(-)

diff --git a/arch/arm/include/asm/arch-meson/gxbb.h
b/arch/arm/include/asm/arch-meson/gxbb.h
index 74d5290..57db37e 100644
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -7,10 +7,25 @@
 #ifndef __GXBB_H__
 #define __GXBB_H__

+#define GXBB_AOBUS_BASE0xc810
 #define GXBB_PERIPHS_BASE  0xc8834400
 #define GXBB_HIU_BASE  0xc883c000
 #define GXBB_ETH_BASE  0xc941

+/* Always-On Peripherals registers */
+#define GXBB_AO_ADDR(off)  (GXBB_AOBUS_BASE + ((off) << 2))
+
+#define GXBB_AO_SEC_GP_CFG0GXBB_AO_ADDR(0x90)
+#define GXBB_AO_SEC_GP_CFG3GXBB_AO_ADDR(0x93)
+#define GXBB_AO_SEC_GP_CFG4GXBB_AO_ADDR(0x94)
+#define GXBB_AO_SEC_GP_CFG5GXBB_AO_ADDR(0x95)
+
+#define GXBB_AO_MEM_SIZE_MASK  0x
+#define GXBB_AO_MEM_SIZE_SHIFT 16
+#define GXBB_AO_BL31_RSVMEM_SIZE_MASK  0x
+#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16
+#define GXBB_AO_BL32_RSVMEM_SIZE_MASK  0x
+
 /* Peripherals registers */
 #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))

diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c
index e89c6aa..bd330af 100644
--- a/arch/arm/mach-meson/board.c
+++ b/arch/arm/mach-meson/board.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 

 DECLARE_GLOBAL_DATA_PTR;

@@ -34,14 +36,99 @@ int dram_init(void)
return 0;
 }

+phys_size_t get_effective_memsize(void)
+{
+   /* Size is reported in MiB, convert it in bytes */
+   return ((in_le32(GXBB_AO_SEC_GP_CFG0) & GXBB_AO_MEM_SIZE_MASK)
+   >> GXBB_AO_MEM_SIZE_SHIFT) * SZ_1M;


Is in_le32 suitable here?


+}
+
 int dram_init_banksize(void)
 {
-   /* Reserve first 16 MiB of RAM for firmware */
-   gd->bd->bi_dram[0].start = 0x100;
-   gd->bd->bi_dram[0].size  = 0xf00;
-   /* Reserve 2 MiB for ARM Trusted Firmware (BL31) */
-   gd->bd->bi_dram[1].start = 0x1000;
-   gd->bd->bi_dram[1].size  = gd->ram_size - 0x1020;
+   u32 bl31_size, bl31_start;
+   u32 bl32_size, bl32_start;
+   /* Start after first 16MiB reserved zone */
+   unsigned int next = 0;
+   u32 last = 0x100;
+   u32 reg;
+
+   /*
+* Get ARM Trusted Firmware reserved memory zones in :
+* - AO_SEC_GP_CFG3: bl32 & bl31 size in KiB, can be 0
+* - AO_SEC_GP_CFG5: bl31 physical start address, can be NULL
+* - AO_SEC_GP_CFG4: bl32 physical start address, can be NULL
+*/


Can you use bootmem reserve to do this?



+
+   reg = in_le32(GXBB_AO_SEC_GP_CFG3);
+
+   bl31_size = ((reg & GXBB_AO_BL31_RSVMEM_SIZE_MASK)
+   >> GXBB_AO_BL31_RSVMEM_SIZE_SHIFT) * SZ_1K;
+   bl32_size = (reg & GXBB_AO_BL32_RSVMEM_SIZE_MASK) * SZ_1K;
+
+   bl31_start = in_le32(GXBB_AO_SEC_GP_CFG5);
+   bl32_start = in_le32(GXBB_AO_SEC_GP_CFG4);
+
+   if (bl31_size && bl31_start && bl32_size && bl32_start) {
+   /* Reserve memory for ARM Trusted Firmware (BL31 && BL32) */
+   gd->bd->bi_dram[next].start = last;
+   if (bl31_start > bl32_start)
+   gd->bd->bi_dram[next].size = bl32_start - last;
+   else
+   gd->bd->bi_dram[next].size = bl31_start - last;
+
+   last = gd->bd->bi_dram[next].start +
+   gd->bd->bi_dram[next].size;
+
+   if (bl31_start > bl32_start)
+   last += bl32_size;
+   else
+   last += bl31_size;
+   next++;
+
+   gd->bd->bi_dram[next].start = last;
+   if (bl31_start > bl32_start)
+   gd->bd->bi_dram[next].size = bl31_start - last;
+   else
+   gd->bd->bi_dram[next].size = bl32_start - last;
+
+   last = gd->bd->bi_dram[next].start +
+   gd->bd->bi_dram[next].size;
+
+

Re: [U-Boot] [PATCH 2/2] board: amlogic: Rename folder for Amlogic boards

2016-06-10 Thread Ben Dooks 
do you have git rename-detection enabled?

On 10 June 2016 at 01:36, Simon Glass <s...@chromium.org> wrote:

> On 9 June 2016 at 08:45, Carlo Caione <ca...@caione.org> wrote:
> > From: Carlo Caione <ca...@endlessm.com>
> >
> > s/hardkernel/amlogic/ to have a single place for all the amlogic-based
> > boards.
> >
> > Signed-off-by: Carlo Caione <ca...@endlessm.com>
> > ---
> >  arch/arm/mach-meson/Kconfig|  2 +-
> >  board/amlogic/odroid-c2/Kconfig| 12 ++
> >  board/amlogic/odroid-c2/MAINTAINERS|  6 +++
> >  board/amlogic/odroid-c2/Makefile   |  7 
> >  board/amlogic/odroid-c2/README | 60
> ++
> >  board/amlogic/odroid-c2/odroid-c2.c| 67
> ++
> >  board/hardkernel/odroid-c2/Kconfig | 12 --
> >  board/hardkernel/odroid-c2/MAINTAINERS |  6 ---
> >  board/hardkernel/odroid-c2/Makefile|  7 
> >  board/hardkernel/odroid-c2/README  | 60
> --
> >  board/hardkernel/odroid-c2/odroid-c2.c | 67
> --
> >  11 files changed, 153 insertions(+), 153 deletions(-)
> >  create mode 100644 board/amlogic/odroid-c2/Kconfig
> >  create mode 100644 board/amlogic/odroid-c2/MAINTAINERS
> >  create mode 100644 board/amlogic/odroid-c2/Makefile
> >  create mode 100644 board/amlogic/odroid-c2/README
> >  create mode 100644 board/amlogic/odroid-c2/odroid-c2.c
> >  delete mode 100644 board/hardkernel/odroid-c2/Kconfig
> >  delete mode 100644 board/hardkernel/odroid-c2/MAINTAINERS
> >  delete mode 100644 board/hardkernel/odroid-c2/Makefile
> >  delete mode 100644 board/hardkernel/odroid-c2/README
> >  delete mode 100644 board/hardkernel/odroid-c2/odroid-c2.c
>
> Reviewed-by: Simon Glass <s...@chromium.org>
>
> Although I'm surprised this did not come through as a rename in your patch.
>
> - Simon
>
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>



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Re: [U-Boot] [PATCH 1/2] SPI: Add S25FL064A and S25FL116K flash information

2014-12-18 Thread Ben Dooks 
On 18/12/14 12:14, Jagan Teki wrote:
 On 17 November 2014 at 20:21, Ben Dooks ben.do...@codethink.co.uk wrote:
 From: Adnan Ali adnan@codethink.co.uk

 Add S25FL064A and S25FL116K flash indentifiers.

 Signed-off-by: Adnan Ali adnan@codethink.co.uk
 ---
  drivers/mtd/spi/sf_params.c | 2 ++
  1 file changed, 2 insertions(+)

 diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
 index 61545ca..462e5c2 100644
 --- a/drivers/mtd/spi/sf_params.c
 +++ b/drivers/mtd/spi/sf_params.c
 @@ -51,6 +51,8 @@ const struct spi_flash_params spi_flash_params_table[] = {
 {S25FL016A,  0x010214, 0x0,   64 * 1024,32,   0,   
  0},
 {S25FL032A,  0x010215, 0x0,   64 * 1024,64,   0,   
  0},
 {S25FL064A,  0x010216, 0x0,   64 * 1024,   128,   0,   
  0},
 +   {S25FL064A,  0x010216, 0x0,   64 * 1024,   128,   0,   
  0},
 
 What is this, already there the same part - any new?

I must have missed this when re-basing off the previous u-boot.

 +   {S25FL116k,  0x014015, 0x0,   64 * 1024,   128,   0,   
  0},
 
 Is this tested! can you rebase master and send the same patches.

Yes, it was one of the devices we looked at and tested on a Marvell
88F6281 based system.

 {S25FL128P_256K, 0x012018, 0x0300,   256 * 1024,64, RD_FULL,   
 WR_QPP},
 {S25FL128P_64K,  0x012018, 0x0301,64 * 1024,   256, RD_FULL,   
 WR_QPP},
 {S25FL032P,  0x010215, 0x4d00,64 * 1024,64, RD_FULL,   
 WR_QPP},
 --
 2.1.1

 
 thanks!
 


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[U-Boot] [PATCH 2/2] SPI: Add S25FL164K flash identifier info

2014-11-17 Thread Ben Dooks 
Add the necessary flash entry for the Spansion S25FL164K
flash. Tested on Marvell 88F6218 based design.

Signed-off-by: Ben Dooks ben.do...@codethink.co.uk
---
 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 462e5c2..c1f243b 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -53,6 +53,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
{S25FL064A,  0x010216, 0x0,   64 * 1024,   128,   0,  
  0},
{S25FL064A,  0x010216, 0x0,   64 * 1024,   128,   0,  
  0},
{S25FL116k,  0x014015, 0x0,   64 * 1024,   128,   0,  
  0},
+   {S25FL164K,  0x014017, 0x0140,64 * 1024,   128,   0,  
  0},
{S25FL128P_256K, 0x012018, 0x0300,   256 * 1024,64, RD_FULL,  
 WR_QPP},
{S25FL128P_64K,  0x012018, 0x0301,64 * 1024,   256, RD_FULL,  
 WR_QPP},
{S25FL032P,  0x010215, 0x4d00,64 * 1024,64, RD_FULL,  
 WR_QPP},
-- 
2.1.1

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[U-Boot] SPI flash ID patches

2014-11-17 Thread Ben Dooks 
These are a pair of patches adding some SPI flashes that were evaluated
on a Marvell Kirkwood system.

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[U-Boot] [PATCH 1/2] SPI: Add S25FL064A and S25FL116K flash information

2014-11-17 Thread Ben Dooks 
From: Adnan Ali adnan@codethink.co.uk

Add S25FL064A and S25FL116K flash indentifiers.

Signed-off-by: Adnan Ali adnan@codethink.co.uk
---
 drivers/mtd/spi/sf_params.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 61545ca..462e5c2 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -51,6 +51,8 @@ const struct spi_flash_params spi_flash_params_table[] = {
{S25FL016A,  0x010214, 0x0,   64 * 1024,32,   0,  
  0},
{S25FL032A,  0x010215, 0x0,   64 * 1024,64,   0,  
  0},
{S25FL064A,  0x010216, 0x0,   64 * 1024,   128,   0,  
  0},
+   {S25FL064A,  0x010216, 0x0,   64 * 1024,   128,   0,  
  0},
+   {S25FL116k,  0x014015, 0x0,   64 * 1024,   128,   0,  
  0},
{S25FL128P_256K, 0x012018, 0x0300,   256 * 1024,64, RD_FULL,  
 WR_QPP},
{S25FL128P_64K,  0x012018, 0x0301,64 * 1024,   256, RD_FULL,  
 WR_QPP},
{S25FL032P,  0x010215, 0x4d00,64 * 1024,64, RD_FULL,  
 WR_QPP},
-- 
2.1.1

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