Re: [PATCH 65/81] spi: Remove and add needed includes

[Cédric Le Goater]

On 5/2/24 03:31, Tom Rini wrote:

Remove  from this driver directory and when needed
add missing include files directly.

Signed-off-by: Tom Rini 
---
Cc: Jagan Teki 
Cc: Tom Rini 
Cc: Anand Gore 
Cc: William Zhang 
Cc: Kursad Oney 
Cc: Joel Peshkin 
Cc: Philippe Reynes 
Cc: Alex Nemirovsky 
Cc: Michal Simek 
Cc: Stefan Roese 
Cc: Neil Armstrong 
Cc: Gregory CLEMENT 
Cc: Lars Povlsen 
Cc: Horatiu Vultur 
Cc: Ryder Lee 
Cc: Weijie Gao 
Cc: Chunfeng Yun 
Cc: GSS_MTK_Uboot_upstream 
Cc: Nobuhiro Iwamatsu 
Cc: Marek Vasut 
Cc: Simon Glass 
Cc: Chin-Ting Kuo 
Cc: "Cédric Le Goater" 
Cc: Aspeed BMC SW team 
Cc: Ryan Chen 
Cc: Chia-Wei Wang 
Cc: Joel Stanley 
Cc: Robert Marko 
Cc: Luka Kovacic 
Cc: Luka Perkov 
Cc: Masahisa Kojima 
Cc: Patrick Delaunay 
Cc: Patrice Chotard 
Cc: Thierry Reding 
Cc: Svyatoslav Ryhel 
Cc: Kunihiko Hayashi 
Cc: Dai Okamura 


For spi-aspeed-smc.c,


Reviewed-by: Cédric Le Goater 

Thanks,

C.

Re: [PATCH 1/4] configs: evb-ast2500: Remove MMC support from default settings

[Cédric Le Goater]

On 10/27/22 08:39, Joel Stanley wrote:

On Wed, 26 Oct 2022 at 13:11, Cédric Le Goater  wrote:


This saves ~50K in the resulting u-boot.bin file which is important to
fit in the U-Boot partition defined in the flash layout of upstream Linux.


The downside is we stop testing it builds for ast2500. I guess as long
as it's being built for the 2600 that's okay?


We can not have both MMC and FIT in the same build because of the size
of the U-Boot partition. FIT is required to boot.

C.






Signed-off-by: Cédric Le Goater 
---
  configs/evb-ast2500_defconfig | 5 ++---
  1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 500c85b8d500..ad0feeb71df5 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -23,7 +23,7 @@ CONFIG_SYS_PBSIZE=276
  CONFIG_CMD_EEPROM=y
  CONFIG_CMD_GPIO=y
  CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
+# CONFIG_CMD_MMC is not set
  CONFIG_CMD_DHCP=y
  CONFIG_BOOTP_BOOTFILESIZE=y
  CONFIG_CMD_MII=y
@@ -38,8 +38,7 @@ CONFIG_ASPEED_GPIO=y
  CONFIG_DM_I2C=y
  CONFIG_SYS_I2C_ASPEED=y
  CONFIG_I2C_EEPROM=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ASPEED=y
+# CONFIG_MMC is not set
  CONFIG_DM_SPI_FLASH=y
  CONFIG_SPI_FLASH_SFDP_SUPPORT=y
  CONFIG_SPI_FLASH_GIGADEVICE=y
--
2.37.3

[PATCH 4/4] configs: evb-ast2500: Set environment in SPI flash

[Cédric Le Goater]

We now have a SPI flash driver. Let's use it.

Signed-off-by: Cédric Le Goater 
---
 configs/evb-ast2500_defconfig | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 5364b6ac3703..65a7056ebdbf 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -5,7 +5,9 @@ CONFIG_SYS_TEXT_BASE=0x0
 CONFIG_SYS_MALLOC_LEN=0x200
 CONFIG_TARGET_EVB_AST2500=y
 CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x6
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
 CONFIG_PRE_CON_BUF_ADDR=0x1e72
@@ -31,6 +33,7 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_NCSI=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_REGMAP=y
-- 
2.37.3

[PATCH 2/4] configs: evb-ast2500: Adjust boot command

[Cédric Le Goater]

Loading a kernel image is enough.

Signed-off-by: Cédric Le Goater 
---
 configs/evb-ast2500_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index ad0feeb71df5..8646e6944803 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -13,7 +13,7 @@ CONFIG_SYS_LOAD_ADDR=0x8300
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
 CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="bootm 2008 2030"
+CONFIG_BOOTCOMMAND="bootm 2008"
 CONFIG_PRE_CONSOLE_BUFFER=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_HUSH_PARSER=y
-- 
2.37.3

[PATCH 3/4] configs: evb-ast2500: Add support for FIT format

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
---
 configs/evb-ast2500_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 8646e6944803..5364b6ac3703 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -10,6 +10,7 @@ CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
 CONFIG_PRE_CON_BUF_ADDR=0x1e72
 CONFIG_SYS_LOAD_ADDR=0x8300
+CONFIG_FIT=y
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttyS4,115200n8 root=/dev/ram rw"
 CONFIG_USE_BOOTCOMMAND=y
-- 
2.37.3

[PATCH 1/4] configs: evb-ast2500: Remove MMC support from default settings

[Cédric Le Goater]

This saves ~50K in the resulting u-boot.bin file which is important to
fit in the U-Boot partition defined in the flash layout of upstream Linux.

Signed-off-by: Cédric Le Goater 
---
 configs/evb-ast2500_defconfig | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 500c85b8d500..ad0feeb71df5 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -23,7 +23,7 @@ CONFIG_SYS_PBSIZE=276
 CONFIG_CMD_EEPROM=y
 CONFIG_CMD_GPIO=y
 CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
+# CONFIG_CMD_MMC is not set
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_MII=y
@@ -38,8 +38,7 @@ CONFIG_ASPEED_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_ASPEED=y
 CONFIG_I2C_EEPROM=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ASPEED=y
+# CONFIG_MMC is not set
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
-- 
2.37.3

[PATCH 0/4] configs: evb-ast2500: defconfig adjustments

[Cédric Le Goater]

Hello,

Here are small adjustments to the evb-ast2500 defconfig to match the
flash layout of openbmc/upstream Linux. With these, one can boot a
system from a flash image containing an upstream U-Boot, an upstream
kernel and an upstream buildroot using the default configs provided by
each component.

Thanks,

C.

Cédric Le Goater (4):
  configs: evb-ast2500: Remove MMC support from default settings
  configs: evb-ast2500: Adjust boot command
  configs: evb-ast2500: Add support for FIT format
  configs: evb-ast2500: Set environment in SPI flash

 configs/evb-ast2500_defconfig | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

-- 
2.37.3

Re: [PATCH v4 1/4] net: NC-SI setup and handling

[Cédric Le Goater]

On 8/8/22 14:16, Joel Stanley wrote:

From: Samuel Mendoza-Jonas 

Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.

Signed-off-by: Samuel Mendoza-Jonas 
Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 


---
v4: split out cmd addition into a separate patch
v3:
  - Fix compilation. There were no configs that enabled the NCSI phy code
so it had bitrotted
  - Use NCSI_PHY instead of CMD_NCSI so NCSI can work without the command
  - Add phy_interface_is_ncsi() helper, thanks Cédric for this suggestion
  - Only create NCSI phy device when driver is configured for it

  include/net.h  |  2 +-
  include/phy.h  |  2 ++
  drivers/net/phy/ncsi.c |  1 +
  drivers/net/phy/phy.c  |  9 -
  net/net.c  | 26 +-
  5 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/include/net.h b/include/net.h
index e3889a0bc85e..0681b8246323 100644
--- a/include/net.h
+++ b/include/net.h
@@ -558,7 +558,7 @@ extern int  net_restart_wrap;   /* Tried all 
network devices */
  
  enum proto_t {

BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
-   TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP
+   TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI
  };
  
  extern char	net_boot_file_name[1024];/* Boot File name */

diff --git a/include/phy.h b/include/phy.h
index b32959571069..1e0f8856f629 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -583,6 +583,8 @@ static inline bool phy_interface_is_sgmii(struct phy_device 
*phydev)
phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
  }
  
+bool phy_interface_is_ncsi(void);

+
  /* PHY UIDs for various PHYs that are referenced in external code */
  #define PHY_UID_CS43400x13e51002
  #define PHY_UID_CS42230x03e57003
diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c
index bf1e832be9f1..bb7ecebed382 100644
--- a/drivers/net/phy/ncsi.c
+++ b/drivers/net/phy/ncsi.c
@@ -9,6 +9,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 1121b99abff5..d04538838852 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1026,7 +1026,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int 
addr,
  #endif
  
  #ifdef CONFIG_PHY_NCSI

-   if (!phydev)
+   if (!phydev && interface == PHY_INTERFACE_MODE_NCSI)
phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false);
  #endif
  
@@ -1101,3 +1101,10 @@ int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
  
  	return phy_write(phydev, devad, regnum, (ret & ~mask) | set);

  }
+
+bool phy_interface_is_ncsi(void)
+{
+   struct eth_pdata *pdata = dev_get_plat(eth_get_dev());
+
+   return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI;
+}
diff --git a/net/net.c b/net/net.c
index 81905f631592..f0faf33d0d77 100644
--- a/net/net.c
+++ b/net/net.c
@@ -93,6 +93,7 @@
  #include 
  #include 
  #include 
+#include 
  #if defined(CONFIG_CMD_PCAP)
  #include 
  #endif
@@ -410,6 +411,16 @@ int net_loop(enum proto_t protocol)
net_try_count = 1;
debug_cond(DEBUG_INT_STATE, "--- net_loop Entry\n");
  
+#ifdef CONFIG_PHY_NCSI

+   if (phy_interface_is_ncsi() && protocol != NCSI && !ncsi_active()) {
+   printf("%s: configuring NCSI first\n", __func__);
+   if (net_loop(NCSI) < 0)
+   return ret;
+   eth_init_state_only();
+   goto restart;
+   }
+#endif
+
bootstage_mark_name(BOOTSTAGE_ID_ETH_START, "eth_start");
net_init();
if (eth_is_on_demand_init()) {
@@ -526,6 +537,11 @@ restart:
case WOL:
wol_start();
break;
+#endif
+#if defined(CONFIG_PHY_NCSI)
+   case NCSI:
+   ncsi_probe_packages();
+   break;
  #endif
default:
break;
@@ -637,7 +653,7 @@ restart:
env_set_hex("filesize", net_boot_file_size);
env_set_hex("fileaddr", image_load_addr);
}
-   if (protocol != NETCONS)
+   if (protocol != NETCONS && protocol != NCSI)
eth_halt();
else
eth_halt_state_only();
@@ -1321,6 +1337,11 @@ void net_process_received_packet(uchar *in_packet, int 
len)
case PROT_WOL:
wol_receive(ip, len);
break;
+#endif
+#ifdef CONFIG_PHY_NCSI
+   case PROT_NCSI:
+   ncsi_receive(et, ip, len);
+   break;
  #endif
}

Re: [PATCH v4 2/4] cmd: Add ncsi command

[Cédric Le Goater]

On 8/8/22 14:16, Joel Stanley wrote:

From: Samuel Mendoza-Jonas 

Adds an "ncsi" command to manually start NC-SI configuration.

Signed-off-by: Samuel Mendoza-Jonas 
Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 


---
v4: New patch, split from patch 1

  cmd/net.c   | 22 ++
  net/net.c   |  1 +
  cmd/Kconfig |  8 
  3 files changed, 31 insertions(+)

diff --git a/cmd/net.c b/cmd/net.c
index 3619c843d838..2863fe768118 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -16,6 +16,7 @@
  #include 
  #include 
  #include 
+#include 
  
  static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const []);
  
@@ -524,3 +525,24 @@ U_BOOT_CMD(

"list - list available devices\n"
  );
  #endif // CONFIG_DM_ETH
+
+#if defined(CONFIG_CMD_NCSI)
+static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const 
argv[])
+{
+   if (!phy_interface_is_ncsi() || !ncsi_active()) {
+   printf("Device not configured for NC-SI\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (net_loop(NCSI) < 0)
+   return CMD_RET_FAILURE;
+
+   return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+   ncsi,   1,  1,  do_ncsi,
+   "Configure attached NIC via NC-SI",
+   ""
+);
+#endif  /* CONFIG_CMD_NCSI */
diff --git a/net/net.c b/net/net.c
index f0faf33d0d77..a4e645ac4425 100644
--- a/net/net.c
+++ b/net/net.c
@@ -434,6 +434,7 @@ int net_loop(enum proto_t protocol)
} else {
eth_init_state_only();
}
+
  restart:
  #ifdef CONFIG_USB_KEYBOARD
net_busy_flag = 0;
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 3625ff2a50b3..3a5d1bba78a8 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1813,6 +1813,14 @@ config CMD_LINK_LOCAL
help
  Acquire a network IP address using the link-local protocol
  
+config CMD_NCSI

+   bool "ncsi"
+   depends on PHY_NCSI
+   help
+ Manually configure the attached NIC via NC-SI.
+ Normally this happens automatically before other network
+ operations.
+
  endif
  
  config CMD_ETHSW

Re: [PATCH v2] mtd: spi-nor-ids: add winbond w25q512nw family support

[Cédric Le Goater]

On 7/8/22 21:03, Jae Hyun Yoo wrote:

Add Winbond w25q512nwq/n and w25q512nwm support.

datasheet:
https://www.winbond.com/resource-files/W25Q512NW%20RevB%2007192021.pdf

Signed-off-by: Jae Hyun Yoo 


Reviewed-by: Cédric Le Goater 


---
Changes in v2:
* Changed name from w25q512nwiq and w25q512nwim to w25q512nwq and w25q512nwm
   respectively to make them sync with linux code.


Thanks,

C.



  drivers/mtd/spi/spi-nor-ids.c | 10 ++
  1 file changed, 10 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7050ddc39716..91a3f983a5fa 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -362,6 +362,16 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+   {
+   INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
+   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+   },
+   {
+   INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
+   SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+   SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+   },
{
INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver

[Cédric Le Goater]

On 7/8/22 07:42, Chin-Ting Kuo wrote:

Hi Joel,


-Original Message-
From: Joel Stanley 
Sent: Thursday, July 7, 2022 1:37 PM
Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver

Hi Chin-Ting,

On Tue, 24 May 2022 at 05:58, Chin-Ting Kuo
 wrote:


Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface
for AST2500 and AST2600 platform.


Have you considered including 2400 support in your patch set?



No. But in order to achieve sustainability and completeness, we will add 
AST2400 part in the next patch version.


Could you please provide the AST2400 support as a separate patch on top
of the AST2500/AST2600 ? It helps to understand the differences.

Thanks,

C.

Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver

[Cédric Le Goater]

Hello Chin-Ting,

On 7/3/22 10:47, Chin-Ting Kuo wrote:

Hi Cédric,

Thanks for the review.


-Original Message-
From: Cédric Le Goater 
Sent: Friday, July 1, 2022 5:28 PM
To: Chin-Ting Kuo ; ChiaWei Wang
; lu...@denx.de; sean...@gmail.com;
Ryan Chen ; BMC-SW
; ja...@amarulasolutions.com; vigne...@ti.com;
u-boot@lists.denx.de; p.ya...@ti.com
Subject: Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver

Hello Chin-Ting,

On 5/24/22 07:56, Chin-Ting Kuo wrote:

Add ASPEED BMC FMC/SPI memory controller driver with spi-mem interface
for AST2500 and AST2600 platform.

There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
 fetches initial device boot image from FMC chip select(CS) 0.

- SPI1: Play the role of a SPI Master controller. Or, there is a
  dedicated path for HOST(X86) to access its BIOS flash mounted
  under BMC. spi-aspeed.c implements the control sequence when
  SPI1 is a SPI master.

- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
  mounted under it are for pure storage purpose.

ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h

or

 13h is used to fetch boot image from SPI flash.
 - AST2500: Only 03h command can be used after power

on

or reset.
 - AST2600: If FMC04[6:4] is set, 13h command is used,
otherwise, 03h command.
 The address length is decided by FMC04[2:0].

- Command mode: SPI controller can send command and address
  automatically when CPU read/write the related

remapped

  or decoded address area. The command used by this

mode

  can be configured by FMC10/14/18[23:16]. Also, the
  address length is decided by FMC04[2:0]. This mode

will

  be implemented in the following patch series.

- User mode: It is a traditional and pure SPI operation, where
   SPI transmission is controlled by CPU. It is the main
   mode in this patch.

Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a
specific address region for each CS of a SPI controller. The decoded
address cannot overlap to each other. With normal mode and command
mode, the decoded address accessed by the CPU determines which CS is

active.

When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.

Signed-off-by: Chin-Ting Kuo 


I would split the patch furthermore to ease reading.


Okay, this will be update in the next version.


   1 - Add basic support

   with default decoding ranges set for all possible CS, even
   without a device.

   WE only have USER mode for now. So it's not important to
   correctly set the ranges since we won't use them before
   direct mapping is introduced. They should not overlap,
   that's all.

   2 - decoding range adjustments

   On that topic, we might want to take the simple DT approach
   with a "ranges" property defining the mapping windows of each
   CE. I think it is safer than trying to compute perfect ranges
   like on Linux.

   3 - clock settings

   That should simply be the property defined in the DT



---
v2: Remove defconfig files from this patch.

   drivers/spi/Kconfig  |   8 +
   drivers/spi/Makefile |   1 +
   drivers/spi/spi-aspeed.c | 822

+++

   3 files changed, 831 insertions(+)
   create mode 100644 drivers/spi/spi-aspeed.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index
a1e515cb2b..a616294910 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -387,6 +387,14 @@ config SANDBOX_SPI
};
  };

+config SPI_ASPEED
+   bool "ASPEED SPI controller driver"
+   depends on DM_SPI && SPI_MEM
+   default n
+   help
+ Enable ASPEED SPI controller driver for AST2500
+ and AST2600 SoCs.
+
   config SPI_SIFIVE
bool "SiFive SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index
06e81b465b..36a4bd5dce 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -9,6 +9,7 @@ obj-y += spi-uclass.o
   obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
   obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
   obj-$(CONFIG_SOFT_SPI) += soft_spi.o
+obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o
   obj-$(CONFIG_SPI_MEM) += spi-mem.o
   obj-$(CONFIG_TI_QSPI) += ti_qspi.o
   obj-$(CONFIG_FSL_QSPI) 

Re: [PATCH v3 3/3] config/aspeed: Enable NC-SI support

[Cédric Le Goater]

On 7/4/22 09:58, Joel Stanley wrote:

Aspeed BMCs are commonly used with NC-SI. A system indicates the driver
should configure the link over NC-SI using the device tree.

Add it to the defconfig so we get compile coverage of the driver, even
if the EVBs do not normally use it.

Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 

Thanks,

C.


---
  configs/evb-ast2500_defconfig | 2 ++
  configs/evb-ast2600_defconfig | 2 ++
  2 files changed, 4 insertions(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 9d2c4f81c5ad..866732117aa7 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_DHCP=y
  CONFIG_BOOTP_BOOTFILESIZE=y
  CONFIG_CMD_MII=y
  CONFIG_CMD_PING=y
+CONFIG_CMD_NCSI=y
  CONFIG_ENV_OVERWRITE=y
  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  CONFIG_NET_RANDOM_ETHADDR=y
@@ -38,6 +39,7 @@ CONFIG_SYS_I2C_ASPEED=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_ASPEED=y
  CONFIG_PHY_REALTEK=y
+CONFIG_PHY_NCSI=y
  CONFIG_DM_ETH=y
  CONFIG_FTGMAC100=y
  CONFIG_PHY=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 5c4d8426607c..8be22014bb4e 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -54,6 +54,7 @@ CONFIG_CMD_DHCP=y
  CONFIG_BOOTP_BOOTFILESIZE=y
  CONFIG_CMD_MII=y
  CONFIG_CMD_PING=y
+CONFIG_CMD_NCSI=y
  CONFIG_SPL_OF_CONTROL=y
  CONFIG_ENV_OVERWRITE=y
  CONFIG_SYS_RELOC_GD_ENV_ADDR=y
@@ -73,6 +74,7 @@ CONFIG_MISC=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_ASPEED=y
  CONFIG_PHY_REALTEK=y
+CONFIG_PHY_NCSI=y
  CONFIG_DM_ETH=y
  CONFIG_DM_MDIO=y
  CONFIG_FTGMAC100=y

Re: [PATCH v3 1/3] net: NC-SI setup and handling

[Cédric Le Goater]

On 7/4/22 09:58, Joel Stanley wrote:

From: Samuel Mendoza-Jonas 

Add the handling of NC-SI ethernet frames, and add a check at the start
of net_loop() to configure NC-SI before starting other network commands.
This also adds an "ncsi" command to manually start NC-SI configuration.

Signed-off-by: Samuel Mendoza-Jonas 
Signed-off-by: Joel Stanley 



Reviewed-by: Cédric Le Goater 

Thanks,

C.


---
v3:
  - Fix compilation. There were no configs that enabled the NCSI phy code
so it had bitrotted
  - Use NCSI_PHY instead of CMD_NCSI so NCSI can work without the command
  - Add phy_interface_is_ncsi() helper, thanks Cédric for this suggestion
  - Only create NCSI phy device when driver is configured for it

  include/net.h  |  2 +-
  include/phy.h  |  2 ++
  cmd/net.c  | 22 ++
  drivers/net/phy/ncsi.c |  1 +
  drivers/net/phy/phy.c  |  9 -
  net/net.c  | 27 ++-
  cmd/Kconfig|  8 
  7 files changed, 68 insertions(+), 3 deletions(-)

diff --git a/include/net.h b/include/net.h
index e3889a0bc85e..0681b8246323 100644
--- a/include/net.h
+++ b/include/net.h
@@ -558,7 +558,7 @@ extern int  net_restart_wrap;   /* Tried all 
network devices */
  
  enum proto_t {

BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
-   TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP
+   TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI
  };
  
  extern char	net_boot_file_name[1024];/* Boot File name */

diff --git a/include/phy.h b/include/phy.h
index b32959571069..1e0f8856f629 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -583,6 +583,8 @@ static inline bool phy_interface_is_sgmii(struct phy_device 
*phydev)
phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
  }
  
+bool phy_interface_is_ncsi(void);

+
  /* PHY UIDs for various PHYs that are referenced in external code */
  #define PHY_UID_CS43400x13e51002
  #define PHY_UID_CS42230x03e57003
diff --git a/cmd/net.c b/cmd/net.c
index 3619c843d838..2863fe768118 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -16,6 +16,7 @@
  #include 
  #include 
  #include 
+#include 
  
  static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const []);
  
@@ -524,3 +525,24 @@ U_BOOT_CMD(

"list - list available devices\n"
  );
  #endif // CONFIG_DM_ETH
+
+#if defined(CONFIG_CMD_NCSI)
+static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const 
argv[])
+{
+   if (!phy_interface_is_ncsi() || !ncsi_active()) {
+   printf("Device not configured for NC-SI\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (net_loop(NCSI) < 0)
+   return CMD_RET_FAILURE;
+
+   return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+   ncsi,   1,  1,  do_ncsi,
+   "Configure attached NIC via NC-SI",
+   ""
+);
+#endif  /* CONFIG_CMD_NCSI */
diff --git a/drivers/net/phy/ncsi.c b/drivers/net/phy/ncsi.c
index bf1e832be9f1..bb7ecebed382 100644
--- a/drivers/net/phy/ncsi.c
+++ b/drivers/net/phy/ncsi.c
@@ -9,6 +9,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 1121b99abff5..d04538838852 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1026,7 +1026,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int 
addr,
  #endif
  
  #ifdef CONFIG_PHY_NCSI

-   if (!phydev)
+   if (!phydev && interface == PHY_INTERFACE_MODE_NCSI)
phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false);
  #endif
  
@@ -1101,3 +1101,10 @@ int phy_modify(struct phy_device *phydev, int devad, int regnum, u16 mask,
  
  	return phy_write(phydev, devad, regnum, (ret & ~mask) | set);

  }
+
+bool phy_interface_is_ncsi(void)
+{
+   struct eth_pdata *pdata = dev_get_plat(eth_get_dev());
+
+   return pdata->phy_interface == PHY_INTERFACE_MODE_NCSI;
+}
diff --git a/net/net.c b/net/net.c
index 81905f631592..a4e645ac4425 100644
--- a/net/net.c
+++ b/net/net.c
@@ -93,6 +93,7 @@
  #include 
  #include 
  #include 
+#include 
  #if defined(CONFIG_CMD_PCAP)
  #include 
  #endif
@@ -410,6 +411,16 @@ int net_loop(enum proto_t protocol)
net_try_count = 1;
debug_cond(DEBUG_INT_STATE, "--- net_loop Entry\n");
  
+#ifdef CONFIG_PHY_NCSI

+   if (phy_interface_is_ncsi() && protocol != NCSI && !ncsi_active()) {
+   printf("%s: configuring NCSI first\n", __func__);
+   if (net_loop(NCSI) < 0)
+   return ret;
+   eth_init_state_only();
+   goto restart;
+   }
+#endif
+
bootstage_mark_name(BOOTSTAGE_ID_ETH_START, "eth_start");
net_init();
if (eth_is_on_demand_init()) {
@@ -423,6 +434,7 @@ 

Re: [PATCH v3 2/3] net/ftgmac100: Add NC-SI mode support

[Cédric Le Goater]

On 7/4/22 09:58, Joel Stanley wrote:

From: Samuel Mendoza-Jonas 

Update the ftgmac100 driver to support NC-SI instead of an mdio phy
where available. This is a common setup for Aspeed AST2x00 platforms.

NC-SI mode is determined from the device-tree if either phy-mode sets it
or the use-ncsi property exists. If set then normal mdio setup is
skipped in favour of the NC-SI phy.

Signed-off-by: Samuel Mendoza-Jonas 
Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 

Thanks,

C.



---
v3:
  - Simplify ncsi enable by re-using pdata->phy_interface parsing.
use-ncsi still overrides this value.
  - Fix up freeing in remove callback per Joe's review

  drivers/net/ftgmac100.c | 14 ++
  1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 78779d7d60b9..69370ea5cca2 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -188,7 +188,7 @@ static int ftgmac100_phy_adjust_link(struct ftgmac100_data 
*priv)
struct phy_device *phydev = priv->phydev;
u32 maccr;
  
-	if (!phydev->link) {

+   if (!phydev->link && priv->phy_mode != PHY_INTERFACE_MODE_NCSI) {
dev_err(phydev->dev, "No link\n");
return -EREMOTEIO;
}
@@ -228,7 +228,8 @@ static int ftgmac100_phy_init(struct udevice *dev)
if (!phydev)
return -ENODEV;
  
-	phydev->supported &= PHY_GBIT_FEATURES;

+   if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+   phydev->supported &= PHY_GBIT_FEATURES;
if (priv->max_speed) {
ret = phy_set_supported(phydev, priv->max_speed);
if (ret)
@@ -308,7 +309,8 @@ static void ftgmac100_stop(struct udevice *dev)
  
  	writel(0, &ftgmac100->maccr);
  
-	phy_shutdown(priv->phydev);

+   if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI)
+   phy_shutdown(priv->phydev);
  }
  
  static int ftgmac100_start(struct udevice *dev)

@@ -580,6 +582,9 @@ static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
  
+	if (dev_read_bool(dev, "use-ncsi"))

+   priv->phy_mode = PHY_INTERFACE_MODE_NCSI;
+
  #ifdef CONFIG_PHY_ADDR
priv->phy_addr = CONFIG_PHY_ADDR;
  #endif
@@ -592,7 +597,8 @@ static int ftgmac100_probe(struct udevice *dev)
 * If DM MDIO is enabled, the MDIO bus will be initialized later in
 * dm_eth_phy_connect
 */
-   if (!IS_ENABLED(CONFIG_DM_MDIO)) {
+   if (priv->phy_mode != PHY_INTERFACE_MODE_NCSI &&
+   !IS_ENABLED(CONFIG_DM_MDIO)) {
ret = ftgmac100_mdio_init(dev);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);

Re: [v4 04/12] configs: aspeed: Enable SPI flash features

[Cédric Le Goater]

[ Adding Joel ]

On 7/3/22 11:00, Chin-Ting Kuo wrote:

Hi Cédric,


-Original Message-
From: Cédric Le Goater 
Sent: Friday, July 1, 2022 7:51 PM
Subject: Re: [v4 04/12] configs: aspeed: Enable SPI flash features

On 7/1/22 11:28, Cédric Le Goater wrote:

On 5/24/22 07:56, Chin-Ting Kuo wrote:

- Enable ASPEED SPI controller driver.
- Enable SPI flash memory configurations.
- Enable configurations for SPI flash manufacturers
    supported on both ASPEED AST2500 and AST2600 AVL.

Signed-off-by: Chin-Ting Kuo 
---
   configs/evb-ast2500_defconfig | 13 +
   configs/evb-ast2600_defconfig | 13 +
   2 files changed, 26 insertions(+)

diff --git a/configs/evb-ast2500_defconfig
b/configs/evb-ast2500_defconfig index 2371cc2742..fd04fe5a60 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -35,6 +35,16 @@ CONFIG_DM_I2C=y
   CONFIG_SYS_I2C_ASPEED=y
   CONFIG_MMC_SDHCI=y
   CONFIG_MMC_SDHCI_ASPEED=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
   CONFIG_PHY_REALTEK=y
   CONFIG_DM_ETH=y
   CONFIG_FTGMAC100=y
@@ -44,6 +54,9 @@ CONFIG_RAM=y
   CONFIG_DM_RESET=y
   CONFIG_DM_SERIAL=y
   CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_ASPEED=y
   CONFIG_SYSRESET=y
   CONFIG_TIMER=y
   CONFIG_WDT=y


This is breaking boot on the AST2500 evb (QEMU) . I haven't found why
yet. You might want to take a look.


The resulting binary is too big for the flash layout we use on OpenBMC.


What’s the flash layout used by you? I tested this patch series on AST2500 EVB, 
and it was okay before.


This is the OpenBMC 32M flash layout  :

[1.389291] Creating 5 MTD partitions on "bmc":
[1.389710] 0x-0x0006 : "u-boot"
[1.391281] 0x0006-0x0008 : "u-boot-env"
[1.392391] 0x0008-0x004c : "kernel"
[1.393434] 0x004c-0x01c0 : "rofs"
[1.394467] 0x01c0-0x0200 : "rwfs"

When using mainline u-boot, these extra configs are needed to boot
the OpenBMC image :
 
 CONFIG_FIT=y

 CONFIG_BOOTCOMMAND="bootm 2008"

The SPI driver is adding quite a lot of .text so I removed MMC support to
keep uboot.bin below 384KB


Thanks,

C.

Re: [v4 04/12] configs: aspeed: Enable SPI flash features

[Cédric Le Goater]

On 7/1/22 11:28, Cédric Le Goater wrote:

On 5/24/22 07:56, Chin-Ting Kuo wrote:

- Enable ASPEED SPI controller driver.
- Enable SPI flash memory configurations.
- Enable configurations for SPI flash manufacturers
   supported on both ASPEED AST2500 and AST2600 AVL.

Signed-off-by: Chin-Ting Kuo 
---
  configs/evb-ast2500_defconfig | 13 +
  configs/evb-ast2600_defconfig | 13 +
  2 files changed, 26 insertions(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 2371cc2742..fd04fe5a60 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -35,6 +35,16 @@ CONFIG_DM_I2C=y
  CONFIG_SYS_I2C_ASPEED=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_ASPEED=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  CONFIG_PHY_REALTEK=y
  CONFIG_DM_ETH=y
  CONFIG_FTGMAC100=y
@@ -44,6 +54,9 @@ CONFIG_RAM=y
  CONFIG_DM_RESET=y
  CONFIG_DM_SERIAL=y
  CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_ASPEED=y
  CONFIG_SYSRESET=y
  CONFIG_TIMER=y
  CONFIG_WDT=y


This is breaking boot on the AST2500 evb (QEMU) . I haven't found why
yet. You might want to take a look.


The resulting binary is too big for the flash layout we use on OpenBMC.

C.

Re: [v4 12/12] spi: aspeed: Fix bug when SPI_NOR_4B_OPCODES flag is set

[Cédric Le Goater]

On 5/24/22 07:56, Chin-Ting Kuo wrote:

When SPI_NOR_4B_OPCODES flag is set for a specific flash
in spi_nor_ids[] table, EN4B command will not be issued and
4-byte dedicated commands will be used to access SPI flash.
Thus, instead of EN4B command, address length is more suitable
for deciding whether the controller should be set to 4-byte mode.

Signed-off-by: Chin-Ting Kuo 
---
  drivers/spi/spi-aspeed.c | 7 +++
  1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
index e5e348eb7b..687ddc370b 100644
--- a/drivers/spi/spi-aspeed.c
+++ b/drivers/spi/spi-aspeed.c
@@ -504,10 +504,6 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave 
*slave,
/* Restore controller setting. */
writel(flash->ce_ctrl_read, ctrl_reg);
  
-	/* Set controller to 4-byte mode when flash is in 4-byte mode. */

-   if (op->cmd.opcode == SPINOR_OP_EN4B)
-   priv->info->set_4byte(bus, cs);
-
return 0;
  }



This should be part of the patch adding the driver.

Thanks,

C.



@@ -561,6 +557,9 @@ static int aspeed_spi_dirmap_create(struct 
spi_mem_dirmap_desc *desc)
   plat->ctrl_base + REG_CE0_CTRL_REG + cs * 4);
priv->flashes[cs].ce_ctrl_read = reg_val;
  
+		if (op_tmpl.addr.nbytes == 4)

+   priv->info->set_4byte(bus, cs);
+
dev_dbg(dev, "read bus width: %d [0x%08x]\n",
op_tmpl.data.buswidth, priv->flashes[cs].ce_ctrl_read);
} else {

Re: [v4 11/12] mtd: spi-nor-ids: Add Winbond W25Q512JV ID

[Cédric Le Goater]

On 5/24/22 07:56, Chin-Ting Kuo wrote:

Add ID for Winbond W25Q512JV device which is supported
on AST2600 EVB by default.

Signed-off-by: Chin-Ting Kuo 


Reviewed-by: Cédric Le Goater 

Thanks,

C.


---
  drivers/mtd/spi/spi-nor-ids.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 7050ddc397..444affb5af 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -362,6 +362,11 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+   {
+   INFO("w25q512jv", 0xef4020, 0, 64 * 1024, 1024,
+SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+   },
{
INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |

Re: [v4 06/12] arm: dts: aspeed: Update SPI flash node settings

[Cédric Le Goater]

On 5/24/22 07:56, Chin-Ting Kuo wrote:

For both AST2500 and AST2600, there are three
SPI controllers, FMC(Firmware Memory Controller),
SPI1 and SPI2. The clock source is HCLK. Following
is the basic information for ASPEED SPI controller.

AST2500:
   - FMC:
   CS number: 3
   controller reg: 0x1e62 - 0x1e62
   decoded address: 0x2000 - 0x2fff

   - SPI1:
   CS number: 2
   controller reg: 0x1e63 - 0x1e630fff
   decoded address: 0x3000 - 0x37ff

   - SPI2:
   CS number: 2
   controller reg: 0x1e631000 - 0x1e631fff
   decoded address: 0x3800 - 0x3fff

AST2600:
   - FMC:
   CS number: 3
   controller reg: 0x1e62 - 0x1e62
   decoded address: 0x2000 - 0x2fff

   - SPI1:
   CS number: 2
   controller reg: 0x1e63 - 0x1e630fff
   decoded address: 0x3000 - 0x3fff

   - SPI2:
   CS number: 3
   controller reg: 0x1e631000 - 0x1e631fff
   decoded address: 0x5000 - 0x5fff

Signed-off-by: Chin-Ting Kuo 


I might be wrong for the comment I did on 'num-cs' in the patch adding
the driver. Joel, what's your opinion ? Hard coded in the driver or
a property in the DT ?

Thanks,

C.


---
  arch/arm/dts/ast2500-evb.dts | 33 +
  arch/arm/dts/ast2500.dtsi| 23 ---
  arch/arm/dts/ast2600-evb.dts |  8 
  arch/arm/dts/ast2600.dtsi| 34 +++---
  4 files changed, 68 insertions(+), 30 deletions(-)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 4796ed445f..c6b7675902 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -73,3 +73,36 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd2_default>;
  };
+
+&fmc {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_fwspics1_default>;
+
+   flash@0 {
+   status = "okay";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <2>;
+   spi-rx-bus-width = <2>;
+   };
+
+   flash@1 {
+   status = "okay";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <2>;
+   spi-rx-bus-width = <2>;
+   };
+};
+
+&spi1 {
+   status = "okay";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_spi1cs1_default>;
+
+   flash@0 {
+   status = "okay";
+   spi-max-frequency = <5000>;
+   spi-tx-bus-width = <2>;
+   spi-rx-bus-width = <2>;
+   };
+};
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index ee66ef6704..d78a53aeb7 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -57,23 +57,26 @@
ranges;
  
  		fmc: flash-controller@1e62 {

-   reg = < 0x1e62 0xc4
-   0x2000 0x1000 >;
+   reg = <0x1e62 0xc4>, <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-fmc";
+   clocks = <&scu ASPEED_CLK_AHB>;
+   num-cs = <3>;
status = "disabled";
-   interrupts = <19>;
+
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@2 {
reg = < 2 >;
compatible = "jedec,spi-nor";
@@ -82,17 +85,20 @@
};
  
  		spi1: flash-controller@1e63 {

-   reg = < 0x1e63 0xc4
-   0x3000 0x0800 >;
+   reg = <0x1e63 0xc4>, <0x3000 0x0800>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-spi";
+   clocks = <&scu ASPEED_CLK_AHB>;
+   num-cs = <2>;
status = "disabled";
+
flash@0 {
reg = < 0 >;
compatible = "jedec,spi-nor";
status = "disabled";
};
+
flash@1 {
reg = < 1 >;
compatible = "jedec,spi-nor";
@@ -101,17 +107,20 @@
};
  
  		spi2: flash-controller@1e631000 {

-

Re: [v4 07/12] spi-mem: Add dirmap API from Linux

[Cédric Le Goater]

On 5/24/22 07:56, Chin-Ting Kuo wrote:

This adds the dirmap API originally introduced in Linux commit aa167f3
("spi: spi-mem: Add a new API to support direct mapping"). This also
includes several follow-up patches and fixes.

Changes from Linux include:
* Added Kconfig option
* Changed struct device to struct udevice
* Changed struct spi_mem to struct spi_slave

This patch is obtained from the following patch
https://patchwork.ozlabs.org/project/uboot/patch/20210205043924.149504-3-sean...@gmail.com/



It has been sent long ago. Is there an issue with the backport from Linux ?
Is it the lack of drivers using it ?

Thanks,

C.



Signed-off-by: Chin-Ting Kuo 
Signed-off-by: Sean Anderson 
Acked-by: Pratyush Yadav 
---
v2: Remove "#if CONFIG_SPI_DIRMAP" compile wrapper.
v3: Fix a grammatical error in spi-mem.h.

  drivers/spi/Kconfig   |  10 ++
  drivers/spi/spi-mem.c | 268 ++
  include/spi-mem.h |  79 +
  3 files changed, 357 insertions(+)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a616294910..297253714a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -40,6 +40,16 @@ config SPI_MEM
  This extension is meant to simplify interaction with SPI memories
  by providing an high-level interface to send memory-like commands.
  
+config SPI_DIRMAP

+   bool "SPI direct mapping"
+   depends on SPI_MEM
+   help
+ Enable the SPI direct mapping API. Most modern SPI controllers can
+ directly map a SPI memory (or a portion of the SPI memory) in the CPU
+ address space. Most of the time this brings significant performance
+ improvements as it automates the whole process of sending SPI memory
+ operations every time a new region is accessed.
+
  if DM_SPI
  
  config ALTERA_SPI

diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 9c1ede1b61..8e8995fc53 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -21,6 +21,8 @@
  #include 
  #include 
  #include 
+#include 
+#include 
  #endif
  
  #ifndef __UBOOT__

@@ -491,6 +493,272 @@ int spi_mem_adjust_op_size(struct spi_slave *slave, 
struct spi_mem_op *op)
  }
  EXPORT_SYMBOL_GPL(spi_mem_adjust_op_size);
  
+static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,

+ u64 offs, size_t len, void *buf)
+{
+   struct spi_mem_op op = desc->info.op_tmpl;
+   int ret;
+
+   op.addr.val = desc->info.offset + offs;
+   op.data.buf.in = buf;
+   op.data.nbytes = len;
+   ret = spi_mem_adjust_op_size(desc->slave, &op);
+   if (ret)
+   return ret;
+
+   ret = spi_mem_exec_op(desc->slave, &op);
+   if (ret)
+   return ret;
+
+   return op.data.nbytes;
+}
+
+static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc,
+  u64 offs, size_t len, const void *buf)
+{
+   struct spi_mem_op op = desc->info.op_tmpl;
+   int ret;
+
+   op.addr.val = desc->info.offset + offs;
+   op.data.buf.out = buf;
+   op.data.nbytes = len;
+   ret = spi_mem_adjust_op_size(desc->slave, &op);
+   if (ret)
+   return ret;
+
+   ret = spi_mem_exec_op(desc->slave, &op);
+   if (ret)
+   return ret;
+
+   return op.data.nbytes;
+}
+
+/**
+ * spi_mem_dirmap_create() - Create a direct mapping descriptor
+ * @mem: SPI mem device this direct mapping should be created for
+ * @info: direct mapping information
+ *
+ * This function is creating a direct mapping descriptor which can then be used
+ * to access the memory using spi_mem_dirmap_read() or spi_mem_dirmap_write().
+ * If the SPI controller driver does not support direct mapping, this function
+ * falls back to an implementation using spi_mem_exec_op(), so that the caller
+ * doesn't have to bother implementing a fallback on his own.
+ *
+ * Return: a valid pointer in case of success, and ERR_PTR() otherwise.
+ */
+struct spi_mem_dirmap_desc *
+spi_mem_dirmap_create(struct spi_slave *slave,
+ const struct spi_mem_dirmap_info *info)
+{
+   struct udevice *bus = slave->dev->parent;
+   struct dm_spi_ops *ops = spi_get_ops(bus);
+   struct spi_mem_dirmap_desc *desc;
+   int ret = -EOPNOTSUPP;
+
+   /* Make sure the number of address cycles is between 1 and 8 bytes. */
+   if (!info->op_tmpl.addr.nbytes || info->op_tmpl.addr.nbytes > 8)
+   return ERR_PTR(-EINVAL);
+
+   /* data.dir should either be SPI_MEM_DATA_IN or SPI_MEM_DATA_OUT. */
+   if (info->op_tmpl.data.dir == SPI_MEM_NO_DATA)
+   return ERR_PTR(-EINVAL);
+
+   desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+   if (!desc)
+   return ERR_PTR(-ENOMEM);
+
+   desc->slave = slave;
+   desc->info = *info;
+   if (ops->mem_ops && ops->mem_ops->dirmap_create)
+   ret = ops->mem_ops->dirmap_create

Re: [v4 04/12] configs: aspeed: Enable SPI flash features

[Cédric Le Goater]

On 5/24/22 07:56, Chin-Ting Kuo wrote:

- Enable ASPEED SPI controller driver.
- Enable SPI flash memory configurations.
- Enable configurations for SPI flash manufacturers
   supported on both ASPEED AST2500 and AST2600 AVL.

Signed-off-by: Chin-Ting Kuo 
---
  configs/evb-ast2500_defconfig | 13 +
  configs/evb-ast2600_defconfig | 13 +
  2 files changed, 26 insertions(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 2371cc2742..fd04fe5a60 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -35,6 +35,16 @@ CONFIG_DM_I2C=y
  CONFIG_SYS_I2C_ASPEED=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_ASPEED=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  CONFIG_PHY_REALTEK=y
  CONFIG_DM_ETH=y
  CONFIG_FTGMAC100=y
@@ -44,6 +54,9 @@ CONFIG_RAM=y
  CONFIG_DM_RESET=y
  CONFIG_DM_SERIAL=y
  CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_ASPEED=y
  CONFIG_SYSRESET=y
  CONFIG_TIMER=y
  CONFIG_WDT=y


This is breaking boot on the AST2500 evb (QEMU) . I haven't found why
yet. You might want to take a look.

Thanks,

C.



diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f84b723bbb..ccf63ec6d0 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -65,6 +65,16 @@ CONFIG_DM_I2C=y
  CONFIG_MISC=y
  CONFIG_MMC_SDHCI=y
  CONFIG_MMC_SDHCI_ASPEED=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  CONFIG_PHY_REALTEK=y
  CONFIG_DM_ETH=y
  CONFIG_DM_MDIO=y
@@ -77,6 +87,9 @@ CONFIG_SPL_RAM=y
  CONFIG_DM_RESET=y
  CONFIG_DM_SERIAL=y
  CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SPI_ASPEED=y
  CONFIG_SYSRESET=y
  CONFIG_SPL_SYSRESET=y
  CONFIG_WDT=y

Re: [v4 03/12] spi: aspeed: Add ASPEED SPI controller driver

[Cédric Le Goater]

Hello Chin-Ting,

On 5/24/22 07:56, Chin-Ting Kuo wrote:

Add ASPEED BMC FMC/SPI memory controller driver with
spi-mem interface for AST2500 and AST2600 platform.

There are three SPI memory controllers embedded in an ASPEED SoC.
- FMC: Named as Firmware Memory Controller. After AC on, MCU ROM
fetches initial device boot image from FMC chip select(CS) 0.

- SPI1: Play the role of a SPI Master controller. Or, there is a
 dedicated path for HOST(X86) to access its BIOS flash mounted
 under BMC. spi-aspeed.c implements the control sequence when
 SPI1 is a SPI master.

- SPI2: It is a pure SPI flash controller. For most scenarios, flashes
 mounted under it are for pure storage purpose.

ASPEED SPI controller supports 1-1-1, 1-1-2 and 1-1-4 SPI flash mode.
Three types of command mode are supported, normal mode, command
read/write mode and user mode.
- Normal mode: Default mode. After power on, normal read command 03h or
13h is used to fetch boot image from SPI flash.
- AST2500: Only 03h command can be used after power on
   or reset.
- AST2600: If FMC04[6:4] is set, 13h command is used,
   otherwise, 03h command.
The address length is decided by FMC04[2:0].

- Command mode: SPI controller can send command and address
 automatically when CPU read/write the related remapped
 or decoded address area. The command used by this mode
 can be configured by FMC10/14/18[23:16]. Also, the
 address length is decided by FMC04[2:0]. This mode will
 be implemented in the following patch series.

- User mode: It is a traditional and pure SPI operation, where
  SPI transmission is controlled by CPU. It is the main
  mode in this patch.

Each SPI controller in ASPEED SoC has its own decoded address mapping.
Within each SPI controller decoded address, driver can assign a specific
address region for each CS of a SPI controller. The decoded address
cannot overlap to each other. With normal mode and command mode, the
decoded address accessed by the CPU determines which CS is active.
When user mode is adopted, the CS decoded address is a FIFO, CPU can
send/receive any SPI transmission by accessing the related decoded
address for the target CS.

Signed-off-by: Chin-Ting Kuo 


I would split the patch furthermore to ease reading.

 1 - Add basic support

 with default decoding ranges set for all possible CS, even
 without a device.

 WE only have USER mode for now. So it's not important to
 correctly set the ranges since we won't use them before
 direct mapping is introduced. They should not overlap,
 that's all.

 2 - decoding range adjustments
 
 On that topic, we might want to take the simple DT approach

 with a "ranges" property defining the mapping windows of each
 CE. I think it is safer than trying to compute perfect ranges
 like on Linux.
   
 3 - clock settings


 That should simply be the property defined in the DT



---
v2: Remove defconfig files from this patch.

  drivers/spi/Kconfig  |   8 +
  drivers/spi/Makefile |   1 +
  drivers/spi/spi-aspeed.c | 822 +++
  3 files changed, 831 insertions(+)
  create mode 100644 drivers/spi/spi-aspeed.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1e515cb2b..a616294910 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -387,6 +387,14 @@ config SANDBOX_SPI
};
  };
  
+config SPI_ASPEED

+   bool "ASPEED SPI controller driver"
+   depends on DM_SPI && SPI_MEM
+   default n
+   help
+ Enable ASPEED SPI controller driver for AST2500
+ and AST2600 SoCs.
+
  config SPI_SIFIVE
bool "SiFive SPI driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 06e81b465b..36a4bd5dce 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -9,6 +9,7 @@ obj-y += spi-uclass.o
  obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
  obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
  obj-$(CONFIG_SOFT_SPI) += soft_spi.o
+obj-$(CONFIG_SPI_ASPEED) += spi-aspeed.o
  obj-$(CONFIG_SPI_MEM) += spi-mem.o
  obj-$(CONFIG_TI_QSPI) += ti_qspi.o
  obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o
diff --git a/drivers/spi/spi-aspeed.c b/drivers/spi/spi-aspeed.c
new file mode 100644
index 00..9574aff793
--- /dev/null
+++ b/drivers/spi/spi-aspeed.c
@@ -0,0 +1,822 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ASPEED FMC/SPI Controller driver
+ *
+ * Copyright (c) 2022 ASPEED Corporation.
+ * Copyright (c) 2022 IBM Corporation.
+ *
+ * Author:
+ * Chin-Ting Kuo 
+ * Cedric Le Goater 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#i

Re: [PATCH RESEND 3/5] config/ast2600: Disable hash hardware accel

[Cédric Le Goater]

Hello Neal

On 6/27/22 10:55, Neal Liu wrote:

Reviewed-by: Chia-Wei Wang 

The QEMU emulation issue is under investigation by Steven.
The CRC32 and MD5 SW support will be added before we re-enabling HW
crypto drivers.

Chiawei


From: joel.s...@gmail.com  On Behalf Of Joel
Stanley
Sent: Monday, June 27, 2022 3:58 PM

The HACE driver lacks support for all the hash types, causing boot to
fail with the default FIT configuration which uses CRC32.

Additionally the Qemu model or the u-boot driver is unable to
correctly compute the SHA256 hash used in a FIT.

Disable HACE by default while the above issues are worked out to
enable boot testing in Qemu.


I don't think this is the right way to do it.

First, it's fine that drivers can only support some algos. There is no rules 
that it must support CRC32.



For CRC32, I understand that the driver should be able to fallback to
the SW implementation.  It is not the case today. With some debug in
aspeed_hace_finish() :

  U-Boot SPL 2022.07-rc5-dirty (Jun 27 2022 - 09:01:28 +0200)
  already initialized, Trying to boot from RAM
  ## Checking hash(es) for config conf-1 ... OK
  ## Checking hash(es) for Image firmware-1 ... crc32Unsupported hash algorithm 
'crc32' error!
  Unsupported hash algorithm for 'hash-1' hash node in 'firmware-1' image node

The above is not related to QEMU.

Thanks,

C.




Second, if Qemu test is failure, it should fix the Qemu HACE driver or disable 
it in Qemu, not in common defconfig in u-boot.
This will affect lots of people who use mainline for developments and 
productions.
Thanks,

-Neal



Signed-off-by: Joel Stanley 
---
  configs/evb-ast2600_defconfig | 3 ---
  1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig
b/configs/evb-ast2600_defconfig index f3a6cb222020..160bccff48e2
100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -59,9 +59,6 @@ CONFIG_REGMAP=y
  CONFIG_SPL_OF_TRANSLATE=y
  CONFIG_CLK=y
  CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y
  CONFIG_ASPEED_GPIO=y
  CONFIG_DM_I2C=y
  CONFIG_MISC=y
--
2.35.1

Re: [PATCH RESEND 5/5] CI: Add Aspeed AST2600

[Cédric Le Goater]

On 6/27/22 09:58, Joel Stanley wrote:

The AST2600 has a Qemu model that allows testing. Create a SPI NOR image
containing the combined SPL and u-boot FIT image.

Signed-off-by: Joel Stanley 




Reviewed-by: Cédric Le Goater 

Thanks,

C.


---
  .azure-pipelines.yml | 3 +++
  .gitlab-ci.yml   | 6 ++
  2 files changed, 9 insertions(+)

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index ad540ea63536..bdc515ebcdc1 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -261,6 +261,9 @@ stages:
  evb_ast2500:
TEST_PY_BD: "evb-ast2500"
TEST_PY_ID: "--id qemu"
+evb_ast2600:
+  TEST_PY_BD: "evb-ast2600"
+  TEST_PY_ID: "--id qemu"
  vexpress_ca9x4:
TEST_PY_BD: "vexpress_ca9x4"
TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index c6a608f7e2a7..f9cd41750791 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -272,6 +272,12 @@ evb-ast2500 test.py:
  TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
  
+evb-ast2600 test.py:

+  variables:
+TEST_PY_BD: "evb-ast2600"
+TEST_PY_ID: "--id qemu"
+  <<: *buildman_and_testpy_dfn
+
  sandbox_flattree test.py:
variables:
  TEST_PY_BD: "sandbox_flattree"

Re: [PATCH RESEND 4/5] ast2600: Configure u-boot-with-spl.bin target

[Cédric Le Goater]

On 6/27/22 09:58, Joel Stanley wrote:

For the u-boot-with-spl.bin target to be useful for the AST2600, set the
maximum SPL size which also sets the padding length.

The normal way of loading u-boot is as a FIT, so configure u-boot.img as
the SPL playload.

With this the following simple steps can be used to build and boot a
system:

   make u-boot-with-spl.bin
   truncate -s 64M u-boot-with-spl.bin
   qemu-system-arm -nographic -M ast2600-evb \
 -drive file=u-boot-with-spl.bin,if=mtd,format=raw

Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 

Thanks,

C.



---
  include/configs/evb_ast2600.h | 3 +++
  configs/evb-ast2600_defconfig | 2 ++
  2 files changed, 5 insertions(+)

diff --git a/include/configs/evb_ast2600.h b/include/configs/evb_ast2600.h
index 3c2155da46df..f5ac88447b52 100644
--- a/include/configs/evb_ast2600.h
+++ b/include/configs/evb_ast2600.h
@@ -10,6 +10,9 @@
  
  #define CONFIG_SYS_UBOOT_BASE		CONFIG_SYS_TEXT_BASE
  
+/* The maximum size the AST2600 bootrom can load is 64KB */

+#define CONFIG_SPL_MAX_SIZE65536
+
  /* Misc */
  #define STR_HELPER(s) #s
  #define STR(s)STR_HELPER(s)
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 160bccff48e2..5230515f7ab6 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -20,6 +20,8 @@ CONFIG_SPL_SIZE_LIMIT=0x1
  CONFIG_SPL=y
  # CONFIG_ARMV7_NONSEC is not set
  CONFIG_SYS_LOAD_ADDR=0x8300
+CONFIG_SPL_PAYLOAD="u-boot.img"
+CONFIG_BUILD_TARGET="u-boot-with-spl.bin"
  # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
  CONFIG_FIT=y
  CONFIG_SPL_FIT_SIGNATURE=y

Re: [PATCH RESEND 3/5] config/ast2600: Disable hash hardware accel

[Cédric Le Goater]

On 6/27/22 10:15, ChiaWei Wang wrote:

Reviewed-by: Chia-Wei Wang 

The QEMU emulation issue is under investigation by Steven.


Great ! I was going to open a gitlab issue under :

  https://gitlab.com/qemu-project/qemu/-/issues/

But we still have a couple of weeks before QEMU 7.1 soft freeze :

  https://wiki.qemu.org/Planning/7.1

We should open one if not solved before, as a reminder, with
some guidelines to reproduce. It


The CRC32 and MD5 SW support will be added before we re-enabling HW crypto 
drivers.


Thanks,

C.


Chiawei


From: joel.s...@gmail.com  On Behalf Of Joel Stanley
Sent: Monday, June 27, 2022 3:58 PM

The HACE driver lacks support for all the hash types, causing boot to fail with
the default FIT configuration which uses CRC32.

Additionally the Qemu model or the u-boot driver is unable to correctly
compute the SHA256 hash used in a FIT.

Disable HACE by default while the above issues are worked out to enable boot
testing in Qemu.

Signed-off-by: Joel Stanley 
---
  configs/evb-ast2600_defconfig | 3 ---
  1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f3a6cb222020..160bccff48e2 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -59,9 +59,6 @@ CONFIG_REGMAP=y
  CONFIG_SPL_OF_TRANSLATE=y
  CONFIG_CLK=y
  CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y
  CONFIG_ASPEED_GPIO=y
  CONFIG_DM_I2C=y
  CONFIG_MISC=y
--
2.35.1

Re: [PATCH RESEND 3/5] config/ast2600: Disable hash hardware accel

[Cédric Le Goater]

On 6/27/22 09:58, Joel Stanley wrote:

The HACE driver lacks support for all the hash types, causing boot to
fail with the default FIT configuration which uses CRC32.

Additionally the Qemu model or the u-boot driver is unable to correctly
compute the SHA256 hash used in a FIT.

Disable HACE by default while the above issues are worked out to enable
boot testing in Qemu.

Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 

Thanks,

C.



---
  configs/evb-ast2600_defconfig | 3 ---
  1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f3a6cb222020..160bccff48e2 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -59,9 +59,6 @@ CONFIG_REGMAP=y
  CONFIG_SPL_OF_TRANSLATE=y
  CONFIG_CLK=y
  CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y
  CONFIG_ASPEED_GPIO=y
  CONFIG_DM_I2C=y
  CONFIG_MISC=y

Re: [PATCH RESEND 2/5] config/ast2600: Make position independent

[Cédric Le Goater]

On 6/27/22 09:58, Joel Stanley wrote:

Allows loading one u-boot from another. Useful for testing on hardware.

Signed-off-by: Joel Stanley 
---


Reviewed-by: Cédric Le Goater 

Thanks,

C.



  configs/evb-ast2600_defconfig | 1 +
  1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 53ba36a28374..f3a6cb222020 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -1,5 +1,6 @@
  CONFIG_ARM=y
  CONFIG_SYS_DCACHE_OFF=y
+CONFIG_POSITION_INDEPENDENT=y
  CONFIG_SPL_SYS_THUMB_BUILD=y
  CONFIG_ARCH_ASPEED=y
  CONFIG_SYS_TEXT_BASE=0x8000

Re: [PATCH RESEND 1/5] config/ast2600: Enable CRC32

[Cédric Le Goater]

On 6/27/22 09:58, Joel Stanley wrote:

Useful for testing images with the default hash type.

Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 

Thanks,

C.


---
  configs/evb-ast2600_defconfig | 1 +
  1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f84b723bbba3..53ba36a28374 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -35,6 +35,7 @@ CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
  CONFIG_SPL_SYS_MALLOC_SIMPLE=y
  CONFIG_SPL_STACK_R=y
  CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x200
+CONFIG_SPL_CRC32=y
  CONFIG_SPL_FIT_IMAGE_TINY=y
  CONFIG_SPL_DM_RESET=y
  CONFIG_SPL_RAM_SUPPORT=y

Re: [PATCH 3/5] config/ast2600: Disable hash hardware accel

[Cédric Le Goater]

Hello Chiawei,

On 6/27/22 02:39, ChiaWei Wang wrote:

Reply again to leave record on mailing list.


From: joel.s...@gmail.com  On Behalf Of Joel Stanley
Sent: Friday, June 24, 2022 10:50 AM

The Qemu model or the u-boot driver is unable to correctly compute the
SHA256 hash used in a FIT. Disable it by default while that issue is worked out
to enable boot testing in Qemu.

Signed-off-by: Joel Stanley 
---
  configs/evb-ast2600_defconfig | 3 ---
  1 file changed, 3 deletions(-)

diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index f3a6cb222020..160bccff48e2 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -59,9 +59,6 @@ CONFIG_REGMAP=y
  CONFIG_SPL_OF_TRANSLATE=y
  CONFIG_CLK=y
  CONFIG_SPL_CLK=y
-CONFIG_DM_HASH=y
-CONFIG_HASH_ASPEED=y
-CONFIG_ASPEED_ACRY=y


Per our previous discussion, SPL code size still exists if all of AST2600 
features are upstream-ed.
Therefore, HW-assisted crypto drivers are needed.

In addition, the current drivers works fine on real EVB to verify Hash + RSA 
signature (including the SHA256 in question).
This issue described in commit message should be attributed to incomplete QEMU 
emulation.


When activating some debug in the hace driver :

  U-Boot SPL 2022.07-rc5-dirty (Jun 27 2022 - 09:01:28 +0200)
  already initialized, aspeed_2600_sdmc_write: SDMC is locked! (write to MCR04 
blocked)
  Trying to boot from RAM
  ## Checking hash(es) for config conf-1 ... OK
  ## Checking hash(es) for Image firmware-1 ... crc32Unsupported hash algorithm 
'crc32'
   error!
  Unsupported hash algorithm for 'hash-1' hash node in 'firmware-1' image node

It seems the problem comes from the unsupported 'crc32' algo.
See aspeed_hace_init().

Thanks,

C.




Therefore, fixing QEMU should be the right way to go instead of disabling these 
options for real HW.

Chiawei


  CONFIG_ASPEED_GPIO=y
  CONFIG_DM_I2C=y
  CONFIG_MISC=y
--
2.35.1

Re: [v4 00/12] Add ASPEED SPI controller driver

[Cédric Le Goater]

On 6/26/22 06:56, Chin-Ting Kuo wrote:

Hi All,

Are there any comments about this patch series?*


Sorry, I haven't had time to take a look at the driver. I will try this week.

Thanks,

C.




Thanks.

Best Wishes,
Chin-Ting


-Original Message-
From: Chin-Ting Kuo 
Sent: Tuesday, May 24, 2022 1:57 PM
To: ChiaWei Wang ; lu...@denx.de;
sean...@gmail.com; Ryan Chen ; BMC-SW
; ja...@amarulasolutions.com; vigne...@ti.com;
c...@kaod.org; u-boot@lists.denx.de; p.ya...@ti.com
Subject: [v4 00/12] Add ASPEED SPI controller driver

This patch series aims to porting ASPEED FMC/SPI memory controller driver
with spi-mem interface. spi-mem dirmap framework is also synchronized from
Linux. These patches have been verified on both
AST2600 and AST2500 EVBs.

Changes in v2:
   - Separate defconfig files from the SPI driver patch.
   - Use "if (CONFIG_IS_ENABLED(SPI_DIRMAP))" to wrap
 spi_dirmap related functions.
   - Add Winbond w25q512jv flash ID.

Changes in v3:
   - Get AHB bus clock frequency from the function parameter.
   - Fix a grammatical error in spi-mem.h.

Changes in v4:
   - Fix bug when SPI_NOR_4B_OPCODES flag is set.

Chin-Ting Kuo (12):
   clk: aspeed: Get HCLK frequency support
   pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support
   spi: aspeed: Add ASPEED SPI controller driver
   configs: aspeed: Enable SPI flash features
   MAINTAINERS: Add ASPEED SPI driver file
   arm: dts: aspeed: Update SPI flash node settings
   spi-mem: Add dirmap API from Linux
   mtd: spi-nor: Use spi-mem dirmap API
   spi: aspeed: SPI dirmap read support
   configs: aspeed: Enable CONFIG_SPI_DIRMAP
   mtd: spi-nor-ids: Add Winbond W25Q512JV ID
   spi: aspeed: Fix bug when SPI_NOR_4B_OPCODES flag is set

  MAINTAINERS  |   7 +
  arch/arm/dts/ast2500-evb.dts |  33 +
  arch/arm/dts/ast2500.dtsi|  23 +-
  arch/arm/dts/ast2600-evb.dts |   8 -
  arch/arm/dts/ast2600.dtsi|  34 +-
  configs/evb-ast2500_defconfig|  14 +
  configs/evb-ast2600_defconfig|  14 +
  drivers/clk/aspeed/clk_ast2500.c |  23 +
  drivers/mtd/spi/sf_probe.c   |  76 ++
  drivers/mtd/spi/spi-nor-core.c   |  55 +-
  drivers/mtd/spi/spi-nor-ids.c|   5 +
  drivers/pinctrl/aspeed/pinctrl_ast2500.c |   2 +
  drivers/spi/Kconfig  |  18 +
  drivers/spi/Makefile |   1 +
  drivers/spi/spi-aspeed.c | 914
+++
  drivers/spi/spi-mem.c| 268 +++
  include/linux/mtd/spi-nor.h  |  18 +
  include/spi-mem.h|  79 ++
  18 files changed, 1546 insertions(+), 46 deletions(-)  create mode 100644
drivers/spi/spi-aspeed.c

--
2.25.1

Re: [u-boot-test-hooks PATCH 2/2] travis-ci: Add Aspeed AST2600 Qemu configuration

[Cédric Le Goater]

On 6/24/22 04:34, Joel Stanley wrote:

Similar to the AST2500 this machine is emulated by Qemu. It boots from
a 64MB SPI NOR flash device by default.

Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 

Thanks,

C.


---
  bin/travis-ci/conf.evb-ast2600_qemu  | 13 +
  py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py |  4 
  2 files changed, 17 insertions(+)
  create mode 100644 bin/travis-ci/conf.evb-ast2600_qemu
  create mode 100644 py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py

diff --git a/bin/travis-ci/conf.evb-ast2600_qemu 
b/bin/travis-ci/conf.evb-ast2600_qemu
new file mode 100644
index ..386ff7d25774
--- /dev/null
+++ b/bin/travis-ci/conf.evb-ast2600_qemu
@@ -0,0 +1,13 @@
+# Copyright 2022 IBM Corp.
+# Joel Stanley 
+# SPDX-License-Identifier: GPL-2.0+
+
+console_impl=qemu
+qemu_machine="ast2600-evb"
+qemu_binary="qemu-system-arm"
+qemu_extra_args="-nographic -nic user,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
+qemu_kernel_args="-drive file=${U_BOOT_BUILD_DIR}/flash.img,format=raw,if=mtd"
+flash_u_boot_bin="u-boot-with-spl.bin"
+reset_impl=none
+flash_impl=qemu_gen_padded_image
+flash_size=64
diff --git a/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py 
b/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py
new file mode 100644
index ..396261efa3a3
--- /dev/null
+++ b/py/travis-ci/u_boot_boardenv_evb-ast2600_qemu.py
@@ -0,0 +1,4 @@
+import travis_tftp
+
+env__net_dhcp_server = True
+env__net_tftp_readable_file = travis_tftp.file2env('u-boot')

Re: [u-boot-test-hooks PATCH 1/2] ast2500: Simplify Qemu command line

[Cédric Le Goater]

On 6/24/22 04:34, Joel Stanley wrote:

The Aspeed machine in Qemu has appropriate defaults so we don't need to
specify these options.

Signed-off-by: Joel Stanley 


Reviewed-by: Cédric Le Goater 

Thanks,

C.


---
  bin/travis-ci/conf.evb-ast2500_qemu | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bin/travis-ci/conf.evb-ast2500_qemu 
b/bin/travis-ci/conf.evb-ast2500_qemu
index 7f0f3c56e006..2e9adc6af9b0 100644
--- a/bin/travis-ci/conf.evb-ast2500_qemu
+++ b/bin/travis-ci/conf.evb-ast2500_qemu
@@ -5,7 +5,7 @@
  console_impl=qemu
  qemu_machine="ast2500-evb"
  qemu_binary="qemu-system-arm"
-qemu_extra_args="-nographic -m 512M -serial mon:stdio -net nic,model=ftgmac100 -net 
user,id=net0,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
+qemu_extra_args="-nographic -nic user,tftp=${UBOOT_TRAVIS_BUILD_DIR}"
  qemu_kernel_args="-drive file=${U_BOOT_BUILD_DIR}/flash.img,format=raw,if=mtd"
  reset_impl=none
  flash_impl=qemu_gen_padded_image

Re: [PATCH v2 02/11] pinctrl: aspeed: FWSPICS1 and SPI1CS1 pin support

[Cédric Le Goater]

On 5/9/22 09:23, Chin-Ting Kuo wrote:

Add FWSPICS1 and SPI1CS1 in AST2500 pinctrl group.
On AST2500 EVB, FWSPICS1 can be supported by default.
An extra jumper, J45, should be configured before
enabling SPI1CS1.

Signed-off-by: Chin-Ting Kuo 


Reviewed-by: Cédric Le Goater 


Thanks,

C.



---
  drivers/pinctrl/aspeed/pinctrl_ast2500.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c 
b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
index 3c2e10b88e..93920a6389 100644
--- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
+++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
@@ -61,6 +61,8 @@ static const struct ast2500_group_config ast2500_groups[] = {
{ "MDIO2", 5, (1 << 2) },
{ "SD1", 5, (1 << 0) },
{ "SD2", 5, (1 << 1) },
+   { "FWSPICS1", 3, (1 << 24) },
+   { "SPI1CS1", 1, (1 << 15) },
  };
  
  static int ast2500_pinctrl_get_groups_count(struct udevice *dev)

Re: [PATCH] net: ftgmac100: use bus name in mdio error messages

[Cédric Le Goater]

On 5/18/22 00:16, Zev Weiss wrote:

Previously we'd been using a device name retrieved via
ftgmac100_data->phydev, but the mdio read/write functions may be
called before that member is initialized in ftgmac100_phy_init(),
leading to a NULL pointer dereference while printing the error message
issued if the mdio access fails.  We can instead use bus->name, which
is already available at that point.

Signed-off-by: Zev Weiss 
Fixes: 538e75d3fc54 ("net: ftgmac100: add MDIO bus and phylib support")

Reviewed-by: Cédric Le Goater 

Thanks,

C.



---
  drivers/net/ftgmac100.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 78779d7d60b9..74261d14e548 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -119,7 +119,7 @@ static int ftgmac100_mdio_read(struct mii_dev *bus, int 
phy_addr, int dev_addr,
 FTGMAC100_MDIO_TIMEOUT_USEC);
if (ret) {
pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
-  priv->phydev->dev->name, phy_addr, reg_addr);
+  bus->name, phy_addr, reg_addr);
return ret;
}
  
@@ -151,7 +151,7 @@ static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,

 FTGMAC100_MDIO_TIMEOUT_USEC);
if (ret) {
pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
-  priv->phydev->dev->name, phy_addr, reg_addr);
+  bus->name, phy_addr, reg_addr);
}
  
  	return ret;

Re: [PATCH v2 01/11] clk: aspeed: Get HCLK frequency support

[Cédric Le Goater]

On 5/9/22 09:23, Chin-Ting Kuo wrote:

User can get correct HCLK frequency during driver probe stage
by adding the following configuration in the device tree.
"clocks = <&scu ASPEED_CLK_AHB>".

Signed-off-by: Chin-Ting Kuo 
---
  drivers/clk/aspeed/clk_ast2500.c | 24 
  1 file changed, 24 insertions(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index a1b4496ca2..d2a58a8462 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -29,6 +29,12 @@
  
  #define D2PLL_DEFAULT_RATE	(250 * 1000 * 1000)
  
+/*

+ * AXI/AHB clock selection, taken from Aspeed SDK
+ */
+#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT9
+#define SCU_HWSTRAP_AXIAHB_DIV_MASK (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT)
+
  DECLARE_GLOBAL_DATA_PTR;
  
  /*

@@ -85,6 +91,21 @@ static ulong ast2500_get_clkin(struct ast2500_scu *scu)
? 25 * 1000 * 1000 : 24 * 1000 * 1000;
  }
  
+static u32 ast2500_get_hclk(struct ast2500_scu *scu)

+{
+   ulong clkin = ast2500_get_clkin(scu);


you could avoid reading clkin and pass it as a parameter like the
other routines do : ast2500_get_hpll_rate() and ast2500_get_mpll_rate()

It's minor.

Reviewed-by: Cédric Le Goater 

Thanks,

C.



+   u32 hpll_reg = readl(&scu->h_pll_param);
+   ulong axi_div = 2;
+   u32 rate;
+   ulong ahb_div = 1 + ((readl(&scu->hwstrap)
+ & SCU_HWSTRAP_AXIAHB_DIV_MASK)
+>> SCU_HWSTRAP_AXIAHB_DIV_SHIFT);
+
+   rate = ast2500_get_hpll_rate(clkin, hpll_reg);
+
+   return (rate / axi_div / ahb_div);
+}
+
  /**
   * Get current rate or uart clock
   *
@@ -146,6 +167,9 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
+   case ASPEED_CLK_AHB:
+   rate = ast2500_get_hclk(priv->scu);
+   break;
case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)

Re: [PATCH] crypto: Add driver for Aspeed HACE

[Cédric Le Goater]

On 5/18/21 9:09 AM, Joel Stanley wrote:
> The HACE supports MD5, SHA1 and SHA2 family hash functions. This driver
> uses it in a polling mode to perform hash calculations over buffers
> placed in DRAM.
> 
> It registers a driver to allow the hardware's clocking to be enabled
> using the clock framework.
> 
> Co-developed-by: Klaus Heinrich Kiwi 
> Signed-off-by: Klaus Heinrich Kiwi 
> Signed-off-by: Joel Stanley 
> ---
>  configs/evb-ast2600_defconfig |   1 +
>  drivers/crypto/Kconfig|  19 +++
>  drivers/crypto/Makefile   |   1 +
>  drivers/crypto/aspeed_hace.c  | 256 ++
>  4 files changed, 277 insertions(+)
>  create mode 100644 drivers/crypto/aspeed_hace.c
> 
> diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
> index 91518dbe3589..52ae8e423bfd 100644
> --- a/configs/evb-ast2600_defconfig
> +++ b/configs/evb-ast2600_defconfig
> @@ -45,6 +45,7 @@ CONFIG_REGMAP=y
>  CONFIG_SPL_OF_TRANSLATE=y
>  CONFIG_CLK=y
>  CONFIG_SPL_CLK=y
> +CONFIG_ASPEED_HACE=y
>  CONFIG_DM_I2C=y
>  CONFIG_MISC=y
>  CONFIG_SPL_MISC=y
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index 1ea116be7503..e92037d88906 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -2,4 +2,23 @@ menu "Hardware crypto devices"
>  
>  source drivers/crypto/fsl/Kconfig
>  
> +config ASPEED_HACE
> + bool "ASPEED Hash and Crypto Engine"
> + depends on ASPEED_AST2600
> + imply SHA_HW_ACCEL
> + imply SHA_PROG_HW_ACCEL
> + imply SHA512
> + imply SHA512_ALGO
> + imply CMD_HASH
> + help
> +  Select this option to enable a driver for using the SHA engine in
> +  the ASPEED BMC SoCs.
> +
> +  Enabling this allows the use of SHA operations in hardware without 
> requiring the
> +  SHA software implementations, saving code size.
> +
> +  Due to hardware limitations it cannot be used with a FIT placed in SPI
> +  FLASH. Data can only be hashed if it is in SDRAM, making this relevant
> +  for MMC and network boot only.
> +
>  endmenu
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index efbd1d3fca05..ac93b1295954 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -4,5 +4,6 @@
>  #http://www.samsung.com
>  
>  obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
> +obj-$(CONFIG_ASPEED_HACE)+= aspeed_hace.o
>  obj-y += rsa_mod_exp/
>  obj-y += fsl/
> diff --git a/drivers/crypto/aspeed_hace.c b/drivers/crypto/aspeed_hace.c
> new file mode 100644
> index ..941c1555fe5c
> --- /dev/null
> +++ b/drivers/crypto/aspeed_hace.c
> @@ -0,0 +1,256 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +//
> +// (C) Copyright ASPEED Technology Inc.
> +// Copyright 2021 IBM Corp.
> +
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define ASPEED_HACE_STS  0x1C
> +#define  HACE_RSA_ISRBIT(13)
> +#define  HACE_CRYPTO_ISR BIT(12)
> +#define  HACE_HASH_ISR   BIT(9)
> +#define  HACE_RSA_BUSY   BIT(2)
> +#define  HACE_CRYPTO_BUSYBIT(1)
> +#define  HACE_HASH_BUSY  BIT(0)
> +#define ASPEED_HACE_HASH_SRC 0x20
> +#define ASPEED_HACE_HASH_DIGEST_BUFF 0x24
> +#define ASPEED_HACE_HASH_KEY_BUFF0x28
> +#define ASPEED_HACE_HASH_DATA_LEN0x2C
> +#define  HACE_SG_LASTBIT(31)
> +#define ASPEED_HACE_HASH_CMD 0x30
> +#define  HACE_SHA_BE_EN  BIT(3)
> +#define  HACE_MD5_LE_EN  BIT(2)
> +#define  HACE_ALGO_MD5   0
> +#define  HACE_ALGO_SHA1  BIT(5)
> +#define  HACE_ALGO_SHA224BIT(6)
> +#define  HACE_ALGO_SHA256(BIT(4) | BIT(6))
> +#define  HACE_ALGO_SHA512(BIT(5) | BIT(6))
> +#define  HACE_ALGO_SHA384(BIT(5) | BIT(6) | BIT(10))
> +#define  HACE_SG_EN  BIT(18)
> +
> +#define ASPEED_MAX_SG32

It would nice to have a struct aspeed_hace describing the register layout. 
  
> +struct aspeed_sg {
> + u32 len;
> + u32 addr;
> +};
> +
> +struct aspeed_hash_ctx {
> + u32 method;
> + u32 digest_size;
> + u32 len;
> + u32 count;
> + struct aspeed_sg list[ASPEED_MAX_SG]; /* Must be 8 byte aligned */
> +};


Shouldn't we use  __aligned(8); ?


> +struct aspeed_hace {
> + struct clk clk;
> +};
> +
> +static phys_addr_t base;
> +
> +static int aspeed_hace_wait_completion(u32 reg, u32 flag, int timeout_us)
> +{
> + u32 val;
> +
> + return readl_poll_timeout(reg, val, (val & flag) == flag, timeout_us);
> +}
> +
> +static int digest_object(const void *src, unsigned int length, void *digest, 
> u32 method)
> +{
> + if (!((u32)src & BIT(31))) {
> + debug("HACE src out of bounds: can only copy fr

Re: [PATCH v2 3/3] cosmetic: aspeed: Modify for SPDX-License

[Cédric Le Goater]

On 8/31/20 8:03 AM, Ryan Chen wrote:
> Modify SPDX-License for furture patch warning
> 
> Signed-off-by: Ryan Chen 
> ---
>  arch/arm/dts/ast2500-u-boot.dtsi | 1 +
>  include/dt-bindings/clock/aspeed-clock.h | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi 
> b/arch/arm/dts/ast2500-u-boot.dtsi
> index 29b08f16ac..51a5244766 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -1,3 +1,4 @@
> +// SPDX-License-Identifier: GPL-2.0
>  #include 
>  #include 
>  
> diff --git a/include/dt-bindings/clock/aspeed-clock.h 
> b/include/dt-bindings/clock/aspeed-clock.h
> index e6599deeb9..a1aa8c07ce 100644
> --- a/include/dt-bindings/clock/aspeed-clock.h
> +++ b/include/dt-bindings/clock/aspeed-clock.h
> @@ -1,4 +1,4 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> +// SPDX-License-Identifier: GPL-2.0


But Linux has : 

/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */

Thanks,

C.

>  
>  #define ASPEED_CLK_GATE_ECLK 0
>  #define ASPEED_CLK_GATE_GCLK 1
> 

Re: [PATCH v2 2/3] clock:aspeed: Sync with Linux kernel clock header define

[Cédric Le Goater]

On 8/31/20 8:03 AM, Ryan Chen wrote:
> v2: modify title description aspeed:clock -> clock:aspeed
> 
> Use kernel include/dt-bindings/clock/aspeed-clock.h define
> for clock driver.
> 
> Signed-off-by: Ryan Chen 
> ---
>  arch/arm/dts/ast2500-u-boot.dtsi | 20 +++
>  drivers/clk/aspeed/clk_ast2500.c | 38 +++--
>  include/dt-bindings/clock/aspeed-clock.h | 68 ++--
>  3 files changed, 68 insertions(+), 58 deletions(-)
> 
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi 
> b/arch/arm/dts/ast2500-u-boot.dtsi
> index 3b119e4ace..29b08f16ac 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -25,7 +25,7 @@
>   reg = <0x1e6e 0x174
>   0x1e6e0200 0x1d4 >;
>   #reset-cells = <1>;
> - clocks = <&scu PLL_MPLL>;
> + clocks = <&scu ASPEED_CLK_MPLL>;
>   resets = <&rst AST_RESET_SDRAM>;
>   };
>  
> @@ -39,7 +39,7 @@
>   compatible = "aspeed,ast2500-sdhci";
>   reg = <0x1e740100>;
>   #reset-cells = <1>;
> - clocks = <&scu BCLK_SDCLK>;
> + clocks = <&scu ASPEED_CLK_SDIO>;
>   resets = <&rst AST_RESET_SDIO>;
>   };
>  
> @@ -47,7 +47,7 @@
>   compatible = "aspeed,ast2500-sdhci";
>   reg = <0x1e740200>;
>   #reset-cells = <1>;
> - clocks = <&scu BCLK_SDCLK>;
> + clocks = <&scu ASPEED_CLK_SDIO>;
>   resets = <&rst AST_RESET_SDIO>;
>   };
>   };
> @@ -56,23 +56,23 @@
>  };
>  
>  &uart1 {
> - clocks = <&scu PCLK_UART1>;
> + clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
>  };
>  
>  &uart2 {
> - clocks = <&scu PCLK_UART2>;
> + clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
>  };
>  
>  &uart3 {
> - clocks = <&scu PCLK_UART3>;
> + clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
>  };
>  
>  &uart4 {
> - clocks = <&scu PCLK_UART4>;
> + clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
>  };
>  
>  &uart5 {
> - clocks = <&scu PCLK_UART5>;
> + clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
>  };
>  
>  &timer {
> @@ -80,9 +80,9 @@
>  };
>  
>  &mac0 {
> - clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
> + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
>  };
>  
>  &mac1 {
> - clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
> + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
>  };
> diff --git a/drivers/clk/aspeed/clk_ast2500.c 
> b/drivers/clk/aspeed/clk_ast2500.c
> index 392fe76b27..aab7d14deb 100644
> --- a/drivers/clk/aspeed/clk_ast2500.c
> +++ b/drivers/clk/aspeed/clk_ast2500.c
> @@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>   ulong rate;
>  
>   switch (clk->id) {
> - case PLL_HPLL:
> - case ARMCLK:
> + case ASPEED_CLK_HPLL:
>   /*
>* This ignores dynamic/static slowdown of ARMCLK and may
>* be inaccurate.
> @@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>   rate = ast2500_get_hpll_rate(clkin,
>readl(&priv->scu->h_pll_param));
>   break;
> - case MCLK_DDR:
> + case ASPEED_CLK_MPLL:
>   rate = ast2500_get_mpll_rate(clkin,
>readl(&priv->scu->m_pll_param));
>   break;
> - case BCLK_PCLK:
> + case ASPEED_CLK_APB:
>   {
>   ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
> & SCU_PCLK_DIV_MASK)
> @@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>   rate = rate / apb_div;
>   }
>   break;
> - case BCLK_SDCLK:
> + case ASPEED_CLK_SDIO:
>   {
>   ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
> & SCU_SDCLK_DIV_MASK)
> @@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>   rate = rate / apb_div;
>   }
>   break;
> - case PCLK_UART1:
> + case ASPEED_CLK_GATE_UART1CLK:
>   rate = ast2500_get_uart_clk_rate(priv->scu, 1);
>   break;
> - case PCLK_UART2:
> + case ASPEED_CLK_GATE_UART2CLK:
>   rate = ast2500_get_uart_clk_rate(priv->scu, 2);
>   break;
> - case PCLK_UART3:
> + case ASPEED_CLK_GATE_UART3CLK:
>   rate = ast2500_get_uart_clk_rate(priv->scu, 3);
>   break;
> - case PCLK_UART4:
> + case ASPEED_CLK_GATE_UART4CLK:
>   rate = ast2500_ge

Re: [PATCH v2 1/3] cosmetic: aspeed: ast2500: Rename clock header

[Cédric Le Goater]

On 8/31/20 8:03 AM, Ryan Chen wrote:
> Rename the ast2500-scu.h to aspeed-clock.h.
> 
> Signed-off-by: Ryan Chen 

Reviewed-by: Cédric Le Goater 


> ---
>  arch/arm/dts/ast2500-u-boot.dtsi| 2 +-
>  arch/arm/mach-aspeed/ast2500/sdram_ast2500.c| 2 +-
>  drivers/clk/aspeed/clk_ast2500.c| 2 +-
>  include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} | 0
>  4 files changed, 3 insertions(+), 3 deletions(-)
>  rename include/dt-bindings/clock/{ast2500-scu.h => aspeed-clock.h} (100%)
> 
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi 
> b/arch/arm/dts/ast2500-u-boot.dtsi
> index 8ac4215745..3b119e4ace 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -1,4 +1,4 @@
> -#include 
> +#include 
>  #include 
>  
>  #include "ast2500.dtsi"
> diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c 
> b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> index a3adaa8a99..8536a70a19 100644
> --- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> +++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
> @@ -19,7 +19,7 @@
>  #include 
>  #include 
>  #include 
> -#include 
> +#include 
>  
>  /* These configuration parameters are taken from Aspeed SDK */
>  #define DDR4_MR46_MODE   0x0800
> diff --git a/drivers/clk/aspeed/clk_ast2500.c 
> b/drivers/clk/aspeed/clk_ast2500.c
> index d1940f1884..392fe76b27 100644
> --- a/drivers/clk/aspeed/clk_ast2500.c
> +++ b/drivers/clk/aspeed/clk_ast2500.c
> @@ -10,7 +10,7 @@
>  #include 
>  #include 
>  #include 
> -#include 
> +#include 
>  #include 
>  #include 
>  
> diff --git a/include/dt-bindings/clock/ast2500-scu.h 
> b/include/dt-bindings/clock/aspeed-clock.h
> similarity index 100%
> rename from include/dt-bindings/clock/ast2500-scu.h
> rename to include/dt-bindings/clock/aspeed-clock.h
> 

Re: [PATCH 0/3] Rename ASPEED SoC clock name

[Cédric Le Goater]

Hello Ryan, 

On 8/28/20 9:32 AM, Ryan Chen wrote:
> This patch series refactor the exiting ASPEED clock name define sync
> with Linux kernel. And also add SPDX-License

All the patchset seems correct but the patch numbering is a bit 
confusing. I have received : 

 [1/3] cosmetic: aspeed: ast2500: Rename clock header
 [1/1] Remove not used export function header.
 [2/3] aspeed:clock: Sync with Linux kernel clock header define
 [3/3] cosmetic: aspeed: Modify for SPDX-License

Could you please merge the first two together maybe and resend ? 

Thanks,

C. 

> Ryan Chen (3):
>   cosmetic: aspeed: ast2500: Rename clock header
>   aspeed:clock: Sync with Linux kernel clock header define
>   cosmetic: aspeed: Modify for SPDX-License
> 
>  arch/arm/dts/ast2500-u-boot.dtsi | 23 ++-
>  arch/arm/mach-aspeed/ast2500/sdram_ast2500.c |  2 +-
>  drivers/clk/aspeed/clk_ast2500.c | 40 +--
>  include/dt-bindings/clock/aspeed-clock.h | 42 
>  include/dt-bindings/clock/ast2500-scu.h  | 30 --
>  5 files changed, 74 insertions(+), 63 deletions(-)
>  create mode 100644 include/dt-bindings/clock/aspeed-clock.h
>  delete mode 100644 include/dt-bindings/clock/ast2500-scu.h
> 

Re: [PATCH] net: ftgmac100: Add support for board specific PHY interface address

[Cédric Le Goater]

On 8/18/20 2:08 AM, Thirupathaiah Annapureddy wrote:
> ftgmac100 driver is using hard-coded PHY interface address of zero.
> Each board can have different PHY interface address (phy_addr).
> This commit modifies the driver to make use of board specific address
> by leveraging CONFIG_PHY_ADDR.
> 
> Signed-off-by: Thirupathaiah Annapureddy 

Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  drivers/net/ftgmac100.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
> index 5676a5b3ba..00bda24f1f 100644
> --- a/drivers/net/ftgmac100.c
> +++ b/drivers/net/ftgmac100.c
> @@ -551,6 +551,10 @@ static int ftgmac100_probe(struct udevice *dev)
>   priv->max_speed = pdata->max_speed;
>   priv->phy_addr = 0;
>  
> +#ifdef CONFIG_PHY_ADDR
> + priv->phy_addr = CONFIG_PHY_ADDR;
> +#endif
> +
>   ret = clk_enable_bulk(&priv->clks);
>   if (ret)
>   goto out;
> 

Re: [PATCH 1/5] dm: core: Fix devfdt_get_addr_ptr return value

[Cédric Le Goater]

On 5/27/20 8:41 AM, Ovidiu Panait wrote:
> According to the description of devfdt_get_addr_ptr, this function
> should return NULL on failure, but currently it returns (void
> *)FDT_ADDR_T_NONE.
> 
> This is also a problem because there are two definitions for 
> dev_read_addr_ptr, depending on CONFIG_DM_DEV_READ_INLINE:
> 
> 1. one returning NULL on failure (drivers/core/read.c): void
> *dev_read_addr_ptr(const struct udevice *dev) { fdt_addr_t addr =
> dev_read_addr(dev);
> 
> return (addr == FDT_ADDR_T_NONE) ? NULL : map_sysmem(addr, 0); }
> 
> 2. another one, which is a wrapper over devfdt_get_addr_ptr,
> returning (void *)FDT_ADDR_T_NONE (include/dm/read.h)
> 
> static inline void *dev_read_addr_ptr(const struct udevice *dev) { 
> return devfdt_get_addr_ptr(dev); }
> 
> Currently, some drivers which make use of devfdt_get_addr_ptr check
> the return value for NULL: drivers/i2c/mvtwsi.c 
> drivers/i2c/designware_i2c.c drivers/usb/host/ehci-zynq.c
> 
> while others check the return value for (void *)FDT_ADDR_T_NONE: 
> drivers/pinctrl/mvebu/pinctrl-mvebu.c drivers/timer/ast_timer.c 
> drivers/watchdog/ast_wdt.c
> 
> Fix this by making devfdt_get_addr_ptr return NULL on failure, as 
> described in the function comments. Also, update the drivers
> currently checking (void *)FDT_ADDR_T_NONE to check for NULL.
> 
> Signed-off-by: Ovidiu Panait  ---

Reviewed-by: Cédric Le Goater 


> 
> drivers/clk/aspeed/clk_ast2500.c  | 4 ++-- drivers/core/fdtaddr.c
> | 5 - drivers/i2c/ast_i2c.c | 4 ++-- 
> drivers/pinctrl/mvebu/pinctrl-mvebu.c | 2 +- 
> drivers/timer/ast_timer.c | 4 ++-- 
> drivers/watchdog/ast_wdt.c| 4 ++-- 6 files changed, 13
> insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/clk/aspeed/clk_ast2500.c
> b/drivers/clk/aspeed/clk_ast2500.c index ccfeded30c..284f5f58d6
> 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++
> b/drivers/clk/aspeed/clk_ast2500.c @@ -498,8 +498,8 @@ static int
> ast2500_clk_ofdata_to_platdata(struct udevice *dev) struct
> ast2500_clk_priv *priv = dev_get_priv(dev);
> 
> priv->scu = devfdt_get_addr_ptr(dev); -   if (IS_ERR(priv->scu)) -
> return PTR_ERR(priv->scu); +  if (!priv->scu) +   return -EINVAL;
> 
> return 0; } diff --git a/drivers/core/fdtaddr.c
> b/drivers/core/fdtaddr.c index dfcb868f65..044d5871b0 100644 ---
> a/drivers/core/fdtaddr.c +++ b/drivers/core/fdtaddr.c @@ -14,6 +14,7
> @@ #include  #include  #include
>  +#include 
> 
> DECLARE_GLOBAL_DATA_PTR;
> 
> @@ -154,7 +155,9 @@ fdt_addr_t devfdt_get_addr(const struct udevice
> *dev)
> 
> void *devfdt_get_addr_ptr(const struct udevice *dev) { -  return (void
> *)(uintptr_t)devfdt_get_addr_index(dev, 0); + fdt_addr_t addr =
> devfdt_get_addr_index(dev, 0); + +return (addr == FDT_ADDR_T_NONE) ?
> NULL : map_sysmem(addr, 0); }
> 
> void *devfdt_remap_addr_index(const struct udevice *dev, int index) 
> diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c index
> 214362d04b..253e653666 100644 --- a/drivers/i2c/ast_i2c.c +++
> b/drivers/i2c/ast_i2c.c @@ -93,8 +93,8 @@ static int
> ast_i2c_ofdata_to_platdata(struct udevice *dev) int ret;
> 
> priv->regs = devfdt_get_addr_ptr(dev); -  if (IS_ERR(priv->regs)) -
> return PTR_ERR(priv->regs); + if (!priv->regs) +  return -EINVAL;
> 
> ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) { diff --git
> a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
> b/drivers/pinctrl/mvebu/pinctrl-mvebu.c index 2206e958ec..ac0377e796
> 100644 --- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c +++
> b/drivers/pinctrl/mvebu/pinctrl-mvebu.c @@ -194,7 +194,7 @@ int
> mvebu_pinctl_probe(struct udevice *dev) }
> 
> priv->base_reg = devfdt_get_addr_ptr(dev); -  if (priv->base_reg ==
> (void *)FDT_ADDR_T_NONE) { +  if (!priv->base_reg) { debug("%s: Failed
> to get base address\n", __func__); return -EINVAL; } diff --git
> a/drivers/timer/ast_timer.c b/drivers/timer/ast_timer.c index
> 3838601f54..9f28cbfcf9 100644 --- a/drivers/timer/ast_timer.c +++
> b/drivers/timer/ast_timer.c @@ -65,8 +65,8 @@ static int
> ast_timer_ofdata_to_platdata(struct udevice *dev) struct
> ast_timer_priv *priv = dev_get_priv(dev);
> 
> priv->regs = devfdt_get_addr_ptr(dev); -  if (IS_ERR(priv->regs)) -
> return PTR_ERR(priv->regs); + if (!priv->regs) +  return -EINVAL;
> 
> priv->tmc = ast_get_timer_counter(priv->regs, AST_TICK_TIMER);
> 
> diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c 
> index 7e11465a57..a21f9a4d14 100644 --- a/drivers/watchdog/ast_wdt.c 
> +++ b/drivers/watchdog/ast_wdt.c @@ -91,8 +91,8 @@ static int
> ast_wdt_ofdata_to_platdata(struct udevice *dev) struct ast_wdt_priv
> *priv = dev_get_priv(dev);
> 
> priv->regs = devfdt_get_addr_ptr(dev); -  if (IS_ERR(priv->regs)) -
> return PTR_ERR(priv->regs); + if (!priv->regs) +  return -EINVAL;
> 
> return 0; }
> 

Re: [PATCH 06/19] aspeed: ast2500: Read clock ofdata in the correct method

[Cédric Le Goater]

On 12/30/19 5:19 AM, Simon Glass wrote:
> At present the clock driver reads its ofdata in the probe() method. This
> is not correct although it is often harmless.
> 
> However in this case it causes a problem, something like this:
> 
> - ast_get_scu() is called (from somewhere) to get the SCI address
> - this probes the clock
>- first sets up ofdata (which does nothing at present)
>- DM marks clock device as active
>- DM calls pinctrl
>   - pinctrl probes and calls ast_get_scu() in ast2500_pinctrl_probe()
>   - ast_get_scu() probes the clock, but sees it already marked as
>probed
>   - ast_get_scu() accesses the clock's private data, with scu as NULL
>- DM calls clock probe function ast2500_clk_probe() which reads scu
> 
> By putting the read of scu into the correct method, scu is read as part of
> ofdata setup, and everything is OK.
> 
> Note: This problem did not matter until now since DM always probed all
> parents before reading a child's ofdata. The fact that pinctrl is a child
> of clock seems to trigger this strange bug.

Did you find it with QEMU ?

> 
> Signed-off-by: Simon Glass 

Reviewed-by: Cédric Le Goater 

C.

> ---
> 
>  drivers/clk/aspeed/clk_ast2500.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/aspeed/clk_ast2500.c 
> b/drivers/clk/aspeed/clk_ast2500.c
> index 9249cf9cdf..b3a3f3d4dd 100644
> --- a/drivers/clk/aspeed/clk_ast2500.c
> +++ b/drivers/clk/aspeed/clk_ast2500.c
> @@ -490,7 +490,7 @@ struct clk_ops ast2500_clk_ops = {
>   .enable = ast2500_clk_enable,
>  };
>  
> -static int ast2500_clk_probe(struct udevice *dev)
> +static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
>  {
>   struct ast2500_clk_priv *priv = dev_get_priv(dev);
>  
> @@ -525,5 +525,5 @@ U_BOOT_DRIVER(aspeed_ast2500_scu) = {
>   .priv_auto_alloc_size = sizeof(struct ast2500_clk_priv),
>   .ops= &ast2500_clk_ops,
>   .bind   = ast2500_clk_bind,
> - .probe  = ast2500_clk_probe,
> + .ofdata_to_platdata = ast2500_clk_ofdata_to_platdata,
>  };
> 

[U-Boot] [PATCH] net: ftgmac100: align RX/TX descriptors on ARCH_DMA_MINALIGN

[Cédric Le Goater]

Fixes: e766849713ff ("net: ftgmac100: convert the RX/TX descriptor arrays")
Signed-off-by: Cédric Le Goater 
---
 drivers/net/ftgmac100.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 92c38a81bd35..c14647af7844 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -71,8 +71,8 @@ enum ftgmac100_model {
 struct ftgmac100_data {
struct ftgmac100 *iobase;
 
-   struct ftgmac100_txdes txdes[PKTBUFSTX];
-   struct ftgmac100_rxdes rxdes[PKTBUFSRX];
+   struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
+   struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
int tx_index;
int rx_index;
 
@@ -309,7 +309,7 @@ static int ftgmac100_start(struct udevice *dev)
}
priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
 
-   start = (ulong)&priv->txdes[0];
+   start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
 
@@ -319,7 +319,7 @@ static int ftgmac100_start(struct udevice *dev)
}
priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
 
-   start = (ulong)&priv->rxdes[0];
+   start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
flush_dcache_range(start, end);
 
@@ -369,7 +369,7 @@ static int ftgmac100_free_pkt(struct udevice *dev, uchar 
*packet, int length)
 {
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
-   ulong des_start = (ulong)curr_des;
+   ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
 
@@ -391,7 +391,7 @@ static int ftgmac100_recv(struct udevice *dev, int flags, 
uchar **packetp)
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
unsigned short rxlen;
-   ulong des_start = (ulong)curr_des;
+   ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
ulong data_start = curr_des->rxdes3;
@@ -426,7 +426,7 @@ static int ftgmac100_recv(struct udevice *dev, int flags, 
uchar **packetp)
 static u32 ftgmac100_read_txdesc(const void *desc)
 {
const struct ftgmac100_txdes *txdes = desc;
-   ulong des_start = (ulong)txdes;
+   ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
 
invalidate_dcache_range(des_start, des_end);
@@ -444,7 +444,7 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
-   ulong des_start = (ulong)curr_des;
+   ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
ulong des_end = des_start +
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
ulong data_start;
-- 
2.21.0

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Re: [U-Boot] [PATCH v3 3/4] configs: AST2500 EVB: Enable SD controller

[Cédric Le Goater]

On 15/08/2019 21:29, Eddie James wrote:
> Enable the MMC subsystem and the Aspeed SD controller. Also enable the
> use of the device tree for probing the controller.
> 
> Signed-off-by: Eddie James 


Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  configs/evb-ast2500_defconfig | 8 
>  1 file changed, 8 insertions(+)
> 
> diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
> index 59d41cb..b47ca5b 100644
> --- a/configs/evb-ast2500_defconfig
> +++ b/configs/evb-ast2500_defconfig
> @@ -16,6 +16,7 @@ CONFIG_HUSH_PARSER=y
>  CONFIG_CMD_I2C=y
>  CONFIG_CMD_DHCP=y
>  CONFIG_CMD_MII=y
> +CONFIG_CMD_MMC=y
>  CONFIG_CMD_PING=y
>  CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
>  CONFIG_NET_RANDOM_ETHADDR=y
> @@ -36,3 +37,10 @@ CONFIG_SYS_NS16550=y
>  CONFIG_SYSRESET=y
>  CONFIG_TIMER=y
>  CONFIG_WDT=y
> +CONFIG_MMC=y
> +CONFIG_DM_MMC=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_ASPEED=y
> +CONFIG_MMC_VERBOSE=y
> +CONFIG_OF_CONTROL=y
> +CONFIG_OF_EMBED=y
> 

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Re: [U-Boot] [PATCH v3 2/4] mmc: Add Aspeed SD controller driver

[Cédric Le Goater]

On 15/08/2019 21:29, Eddie James wrote:
> Add support for the Aspeed SD host controller engine.
> 
> Signed-off-by: Eddie James 


Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  arch/arm/include/asm/gpio.h |  3 +-
>  drivers/mmc/Kconfig | 11 ++
>  drivers/mmc/Makefile|  1 +
>  drivers/mmc/aspeed_sdhci.c  | 90 
> +
>  4 files changed, 104 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/mmc/aspeed_sdhci.c
> 
> diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
> index 370031f..38a5922 100644
> --- a/arch/arm/include/asm/gpio.h
> +++ b/arch/arm/include/asm/gpio.h
> @@ -1,6 +1,7 @@
>  #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
>   !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
> - !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
> + !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
> + !defined(CONFIG_ARCH_ASPEED)
>  #include 
>  #endif
>  #include 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index c6812f6..536f66a 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -421,6 +421,17 @@ config SPL_MMC_SDHCI_ADMA
> This enables support for the ADMA (Advanced DMA) defined
> in the SD Host Controller Standard Specification Version 3.00 in SPL.
>  
> +config MMC_SDHCI_ASPEED
> + bool "Aspeed SDHCI controller"
> + depends on ARCH_ASPEED
> + depends on DM_MMC
> + depends on MMC_SDHCI
> + help
> +   Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
> +   SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
> +   specifications. On the AST2600, the device is also compatible with
> +   MMC 5.1 and eMMC 3.0.
> +
>  config MMC_SDHCI_ATMEL
>   bool "Atmel SDHCI controller support"
>   depends on ARCH_AT91
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index 6cc018b..5594195 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
>  
>  # SDHCI
>  obj-$(CONFIG_MMC_SDHCI)  += sdhci.o
> +obj-$(CONFIG_MMC_SDHCI_ASPEED)   += aspeed_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_ATMEL)+= atmel_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_BCM2835)  += bcm2835_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_BCMSTB)   += bcmstb_sdhci.o
> diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
> new file mode 100644
> index 000..1321ec3
> --- /dev/null
> +++ b/drivers/mmc/aspeed_sdhci.c
> @@ -0,0 +1,90 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 IBM Corp.
> + * Eddie James 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +struct aspeed_sdhci_plat {
> + struct mmc_config cfg;
> + struct mmc mmc;
> +};
> +
> +static int aspeed_sdhci_probe(struct udevice *dev)
> +{
> + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> + struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
> + struct sdhci_host *host = dev_get_priv(dev);
> + u32 max_clk;
> + struct clk clk;
> + int ret;
> +
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_enable(&clk);
> + if (ret)
> + goto free;
> +
> + host->name = dev->name;
> + host->ioaddr = (void *)devfdt_get_addr(dev);
> +
> + max_clk = clk_get_rate(&clk);
> + if (IS_ERR_VALUE(max_clk)) {
> + ret = max_clk;
> + goto err;
> + }
> +
> + host->max_clk = max_clk;
> + host->mmc = &plat->mmc;
> + host->mmc->dev = dev;
> + host->mmc->priv = host;
> + upriv->mmc = host->mmc;
> +
> + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
> + if (ret)
> + goto err;
> +
> + ret = sdhci_probe(dev);
> + if (ret)
> + goto err;
> +
> + return 0;
> +
> +err:
> + clk_disable(&clk);
> +free:
> + clk_free(&clk);
> + return ret;
> +}
> +
> +static int aspeed_sdhci_bind(struct udevice *dev)
> +{
> + struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
> +
> + return sdhci_bind(dev, &plat->mmc, &plat->cfg);
> +}
> +
> +static const struct udevice_id aspeed_sdhci_ids[] = {
> + { .co

Re: [U-Boot] [PATCH v2 4/4] ARM: dts: ast2500: Add SDHCI nodes

[Cédric Le Goater]

On 13/08/2019 21:31, Eddie James wrote:
> Add nodes for the Aspeed SD controllers with their necessary properties.
> 
> Signed-off-by: Eddie James 



Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  arch/arm/dts/ast2500-evb.dts | 14 ++
>  arch/arm/dts/ast2500-u-boot.dtsi | 16 
>  2 files changed, 30 insertions(+)
> 
> diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
> index ebf44fd..4796ed4 100644
> --- a/arch/arm/dts/ast2500-evb.dts
> +++ b/arch/arm/dts/ast2500-evb.dts
> @@ -59,3 +59,17 @@
>   pinctrl-names = "default";
>   pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
>  };
> +
> +&sdhci0 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sd1_default>;
> +};
> +
> +&sdhci1 {
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sd2_default>;
> +};
> diff --git a/arch/arm/dts/ast2500-u-boot.dtsi 
> b/arch/arm/dts/ast2500-u-boot.dtsi
> index 7f80bad..8ac4215 100644
> --- a/arch/arm/dts/ast2500-u-boot.dtsi
> +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> @@ -34,6 +34,22 @@
>  
>   apb {
>   u-boot,dm-pre-reloc;
> +
> + sdhci0: sdhci@1e740100 {
> + compatible = "aspeed,ast2500-sdhci";
> + reg = <0x1e740100>;
> + #reset-cells = <1>;
> + clocks = <&scu BCLK_SDCLK>;
> + resets = <&rst AST_RESET_SDIO>;
> + };
> +
> + sdhci1: sdhci@1e740200 {
> + compatible = "aspeed,ast2500-sdhci";
> + reg = <0x1e740200>;
> + #reset-cells = <1>;
> + clocks = <&scu BCLK_SDCLK>;
> + resets = <&rst AST_RESET_SDIO>;
> + };
>   };
>  
>   };
> 

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Re: [U-Boot] [PATCH v2 3/4] aspeed: Support SD controller on the ast2500 board

[Cédric Le Goater]

On 13/08/2019 21:31, Eddie James wrote:
> Initialize the MMC subsystem on the ast2500 board. Compile MMC and the
> Aspeed SD controller on the ast2500 EVB.
> 
> Signed-off-by: Eddie James 
> ---
>  arch/arm/include/asm/gpio.h  | 3 ++-
>  arch/arm/mach-aspeed/ast2500-board.c | 3 +++
>  configs/evb-ast2500_defconfig| 6 ++
>  3 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
> index 370031f..38a5922 100644
> --- a/arch/arm/include/asm/gpio.h
> +++ b/arch/arm/include/asm/gpio.h
> @@ -1,6 +1,7 @@
>  #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) && \
>   !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) && \
> - !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP)
> + !defined(CONFIG_ARCH_BCM63158) && !defined(CONFIG_ARCH_ROCKCHIP) && \
> + !defined(CONFIG_ARCH_ASPEED)
>  #include 
>  #endif
>  #include 
> diff --git a/arch/arm/mach-aspeed/ast2500-board.c 
> b/arch/arm/mach-aspeed/ast2500-board.c
> index e7edd54..52a4e05 100644
> --- a/arch/arm/mach-aspeed/ast2500-board.c
> +++ b/arch/arm/mach-aspeed/ast2500-board.c
> @@ -4,6 +4,7 @@
>   */
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -55,6 +56,8 @@ int board_init(void)
>  {
>   gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
>  
> + mmc_initialize(gd->bd);
> +

isn't that called automatically by board_init_r() already ?

C. 

>   return 0;
>  }
>  
> diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
> index 59d41cb..bfa6b32 100644
> --- a/configs/evb-ast2500_defconfig
> +++ b/configs/evb-ast2500_defconfig
> @@ -16,6 +16,7 @@ CONFIG_HUSH_PARSER=y
>  CONFIG_CMD_I2C=y
>  CONFIG_CMD_DHCP=y
>  CONFIG_CMD_MII=y
> +CONFIG_CMD_MMC=y
>  CONFIG_CMD_PING=y
>  CONFIG_DEFAULT_DEVICE_TREE="ast2500-evb"
>  CONFIG_NET_RANDOM_ETHADDR=y
> @@ -36,3 +37,8 @@ CONFIG_SYS_NS16550=y
>  CONFIG_SYSRESET=y
>  CONFIG_TIMER=y
>  CONFIG_WDT=y
> +CONFIG_MMC=y
> +CONFIG_DM_MMC=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_ASPEED=y
> +CONFIG_MMC_VERBOSE=y
> 

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Re: [U-Boot] [PATCH v2 2/4] mmc: Add Aspeed SD controller driver

[Cédric Le Goater]

On 13/08/2019 21:31, Eddie James wrote:
> Add support for the Aspeed SD host controller engine.

It looks correct and simple enough. Some comments below.

> 
> Signed-off-by: Eddie James 
> ---
>  drivers/mmc/Kconfig| 11 +++
>  drivers/mmc/Makefile   |  1 +
>  drivers/mmc/aspeed_sdhci.c | 78 
> ++
>  3 files changed, 90 insertions(+)
>  create mode 100644 drivers/mmc/aspeed_sdhci.c
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index c6812f6..536f66a 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -421,6 +421,17 @@ config SPL_MMC_SDHCI_ADMA
> This enables support for the ADMA (Advanced DMA) defined
> in the SD Host Controller Standard Specification Version 3.00 in SPL.
>  
> +config MMC_SDHCI_ASPEED
> + bool "Aspeed SDHCI controller"
> + depends on ARCH_ASPEED
> + depends on DM_MMC
> + depends on MMC_SDHCI
> + help
> +   Enables support for the Aspeed SDHCI 2.0 controller present on Aspeed
> +   SoCs. This device is compatible with SD 3.0 and/or MMC 4.3
> +   specifications. On the AST2600, the device is also compatible with
> +   MMC 5.1 and eMMC 3.0.
> +
>  config MMC_SDHCI_ATMEL
>   bool "Atmel SDHCI controller support"
>   depends on ARCH_AT91
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index 6cc018b..5594195 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
>  
>  # SDHCI
>  obj-$(CONFIG_MMC_SDHCI)  += sdhci.o
> +obj-$(CONFIG_MMC_SDHCI_ASPEED)   += aspeed_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_ATMEL)+= atmel_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_BCM2835)  += bcm2835_sdhci.o
>  obj-$(CONFIG_MMC_SDHCI_BCMSTB)   += bcmstb_sdhci.o
> diff --git a/drivers/mmc/aspeed_sdhci.c b/drivers/mmc/aspeed_sdhci.c
> new file mode 100644
> index 000..c292c42
> --- /dev/null
> +++ b/drivers/mmc/aspeed_sdhci.c
> @@ -0,0 +1,78 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019 IBM Corp.
> + * Eddie James 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +struct aspeed_sdhci_plat {
> + struct mmc_config cfg;
> + struct mmc mmc;
> +};
> +
> +static int aspeed_sdhci_probe(struct udevice *dev)
> +{
> + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
> + struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
> + struct sdhci_host *host = dev_get_priv(dev);
> + u32 max_clk;
> + struct clk clk;
> + int ret;
> +
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret)
> + return ret;
> +
> + ret = clk_enable(&clk);
> + if (ret)
> + return ret;

Don't we need to release the clock below in case of error ? 
> + host->name = dev->name;
> + host->ioaddr = (void *)devfdt_get_addr(dev);
> +
> + max_clk = clk_get_rate(&clk);
> + if (!max_clk)

may be use IS_ERR_VALUE(max_clk) and return max_clk

> + return -EINVAL;
> +
> + host->max_clk = max_clk;
> + host->mmc = &plat->mmc;
> + host->mmc->dev = dev;
> + host->mmc->priv = host;
> + upriv->mmc = host->mmc;
> +
> + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
> + if (ret)
> + return ret;
> +
> + return sdhci_probe(dev);
> +}
> +
> +static int aspeed_sdhci_bind(struct udevice *dev)
> +{
> + struct aspeed_sdhci_plat *plat = dev_get_platdata(dev);
> +
> + return sdhci_bind(dev, &plat->mmc, &plat->cfg);
> +}
> +
> +static const struct udevice_id aspeed_sdhci_ids[] = {
> + { .compatible = "aspeed,ast2400-sdhci" },
> + { .compatible = "aspeed,ast2500-sdhci" },
> + { .compatible = "aspeed,ast2600-sdhci" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(aspeed_sdhci_drv) = {
> + .name   = "aspeed_sdhci",
> + .id = UCLASS_MMC,
> + .of_match   = aspeed_sdhci_ids,
> + .ops= &sdhci_ops,
> + .bind   = aspeed_sdhci_bind,
> + .probe  = aspeed_sdhci_probe,
> + .priv_auto_alloc_size = sizeof(struct sdhci_host),
> + .platdata_auto_alloc_size = sizeof(struct aspeed_sdhci_plat),
> +};
> 

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Re: [U-Boot] [PATCH v2 1/4] clk: aspeed: Add support for SD clock

[Cédric Le Goater]

On 13/08/2019 21:31, Eddie James wrote:
> Add code to enable the SD clock on the ast2500 SoC.
> 
> Signed-off-by: Eddie James 

Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  arch/arm/include/asm/arch-aspeed/scu_ast2500.h |  3 +++
>  drivers/clk/aspeed/clk_ast2500.c   | 27 
> ++
>  drivers/pinctrl/aspeed/pinctrl_ast2500.c   |  2 ++
>  3 files changed, 32 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h 
> b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> index 4988ced..8db4901 100644
> --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> @@ -22,6 +22,8 @@
>  #define SCU_MPLL_POST_MASK   (0x3f << SCU_MPLL_POST_SHIFT)
>  #define SCU_PCLK_DIV_SHIFT   23
>  #define SCU_PCLK_DIV_MASK(7 << SCU_PCLK_DIV_SHIFT)
> +#define SCU_SDCLK_DIV_SHIFT  12
> +#define SCU_SDCLK_DIV_MASK   (7 << SCU_SDCLK_DIV_SHIFT)
>  #define SCU_HPLL_DENUM_SHIFT 0
>  #define SCU_HPLL_DENUM_MASK  0x1f
>  #define SCU_HPLL_NUM_SHIFT   5
> @@ -107,6 +109,7 @@
>  
>  #define SCU_CLKSTOP_MAC1 (1 << 20)
>  #define SCU_CLKSTOP_MAC2 (1 << 21)
> +#define SCU_CLKSTOP_SDCLK(1 << 27)
>  
>  #define SCU_D2PLL_EXT1_OFF   (1 << 0)
>  #define SCU_D2PLL_EXT1_BYPASS(1 << 1)
> diff --git a/drivers/clk/aspeed/clk_ast2500.c 
> b/drivers/clk/aspeed/clk_ast2500.c
> index dbee13a..9249cf9 100644
> --- a/drivers/clk/aspeed/clk_ast2500.c
> +++ b/drivers/clk/aspeed/clk_ast2500.c
> @@ -143,6 +143,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>   rate = rate / apb_div;
>   }
>   break;
> + case BCLK_SDCLK:
> + {
> + ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
> +   & SCU_SDCLK_DIV_MASK)
> +  >> SCU_SDCLK_DIV_SHIFT);
> + rate = ast2500_get_hpll_rate(clkin,
> +  readl(&priv->
> +scu->h_pll_param));
> + rate = rate / apb_div;
> + }
> + break;
>   case PCLK_UART1:
>   rate = ast2500_get_uart_clk_rate(priv->scu, 1);
>   break;
> @@ -436,6 +447,22 @@ static int ast2500_clk_enable(struct clk *clk)
>   struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
>  
>   switch (clk->id) {
> + case BCLK_SDCLK:
> + if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
> + ast_scu_unlock(priv->scu);
> +
> + setbits_le32(&priv->scu->sysreset_ctrl1,
> +  SCU_SYSRESET_SDIO);
> + udelay(100);
> + clrbits_le32(&priv->scu->clk_stop_ctrl1,
> +  SCU_CLKSTOP_SDCLK);
> + mdelay(10);
> + clrbits_le32(&priv->scu->sysreset_ctrl1,
> +  SCU_SYSRESET_SDIO);
> +
> + ast_scu_lock(priv->scu);
> + }
> + break;
>   /*
>* For MAC clocks the clock rate is
>* configured based on whether RGMII or RMII mode has been selected
> diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2500.c 
> b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
> index ed333b9..a6e9c0d 100644
> --- a/drivers/pinctrl/aspeed/pinctrl_ast2500.c
> +++ b/drivers/pinctrl/aspeed/pinctrl_ast2500.c
> @@ -58,6 +58,8 @@ static const struct ast2500_group_config ast2500_groups[] = 
> {
>   { "MDIO1", 3, (1 << 31) | (1 << 30) },
>   { "MAC2LINK", 1, (1 << 1) },
>   { "MDIO2", 5, (1 << 2) },
> + { "SD1", 5, (1 << 0) },
> + { "SD2", 5, (1 << 1) },
>  };
>  
>  static int ast2500_pinctrl_get_groups_count(struct udevice *dev)
> 

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Re: [U-Boot] [PATCH] ARM: aspeed: Add SD host controller driver

[Cédric Le Goater]

On 13/08/2019 08:41, Peng Fan wrote:
>> Subject: [U-Boot][PATCH] ARM: aspeed: Add SD host controller driver
>>
>> Add support for the Aspeed SD host controller engine. This involves adding an
>> MMC SDHCI driver and various additions to the clock and reset drivers for
>> Aspeed chips.
>>
>> Signed-off-by: Eddie James 
>> ---
>>  arch/arm/include/asm/arch-aspeed/scu_ast2500.h |  3 +
>>  arch/arm/include/asm/gpio.h|  3 +-
>>  arch/arm/mach-aspeed/ast2500-board.c   |  3 +
>>  drivers/clk/aspeed/clk_ast2500.c   | 27 +
>>  drivers/mmc/Kconfig| 11 
>>  drivers/mmc/Makefile   |  1 +
>>  drivers/mmc/aspeed_sdhci.c | 78
> 
> Please split the patch.

yes. a clock patch, a driver patch, a board integration patch at least,
with some DT addons for the EVB. 

Don't we want to sync up the DT from Linux also ?  
   
Thanks,

C. 

> 
> Thanks,
> Peng.
> 
>> ++
>>  drivers/pinctrl/aspeed/pinctrl_ast2500.c   |  2 +
>>  8 files changed, 127 insertions(+), 1 deletion(-)  create mode 100644
>> drivers/mmc/aspeed_sdhci.c
>>
>> diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
>> b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
>> index 4988ced..8db4901 100644
>> --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
>> +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
>> @@ -22,6 +22,8 @@
>>  #define SCU_MPLL_POST_MASK  (0x3f << SCU_MPLL_POST_SHIFT)
>>  #define SCU_PCLK_DIV_SHIFT  23
>>  #define SCU_PCLK_DIV_MASK   (7 << SCU_PCLK_DIV_SHIFT)
>> +#define SCU_SDCLK_DIV_SHIFT 12
>> +#define SCU_SDCLK_DIV_MASK  (7 << SCU_SDCLK_DIV_SHIFT)
>>  #define SCU_HPLL_DENUM_SHIFT0
>>  #define SCU_HPLL_DENUM_MASK 0x1f
>>  #define SCU_HPLL_NUM_SHIFT  5
>> @@ -107,6 +109,7 @@
>>
>>  #define SCU_CLKSTOP_MAC1(1 << 20)
>>  #define SCU_CLKSTOP_MAC2(1 << 21)
>> +#define SCU_CLKSTOP_SDCLK   (1 << 27)
>>
>>  #define SCU_D2PLL_EXT1_OFF  (1 << 0)
>>  #define SCU_D2PLL_EXT1_BYPASS   (1 << 1)
>> diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
>> index 370031f..38a5922 100644
>> --- a/arch/arm/include/asm/gpio.h
>> +++ b/arch/arm/include/asm/gpio.h
>> @@ -1,6 +1,7 @@
>>  #if !defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARCH_STI) &&
>> \
>>  !defined(CONFIG_ARCH_K3) && !defined(CONFIG_ARCH_BCM6858) &&
>> \
>> -!defined(CONFIG_ARCH_BCM63158)
>> && !defined(CONFIG_ARCH_ROCKCHIP)
>> +!defined(CONFIG_ARCH_BCM63158)
>> && !defined(CONFIG_ARCH_ROCKCHIP) && \
>> +!defined(CONFIG_ARCH_ASPEED)
>>  #include 
>>  #endif
>>  #include 
>> diff --git a/arch/arm/mach-aspeed/ast2500-board.c
>> b/arch/arm/mach-aspeed/ast2500-board.c
>> index e7edd54..52a4e05 100644
>> --- a/arch/arm/mach-aspeed/ast2500-board.c
>> +++ b/arch/arm/mach-aspeed/ast2500-board.c
>> @@ -4,6 +4,7 @@
>>   */
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>  #include 
>> @@ -55,6 +56,8 @@ int board_init(void)
>>  {
>>  gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
>>
>> +mmc_initialize(gd->bd);
>> +
>>  return 0;
>>  }
>>
>> diff --git a/drivers/clk/aspeed/clk_ast2500.c
>> b/drivers/clk/aspeed/clk_ast2500.c
>> index dbee13a..9249cf9 100644
>> --- a/drivers/clk/aspeed/clk_ast2500.c
>> +++ b/drivers/clk/aspeed/clk_ast2500.c
>> @@ -143,6 +143,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
>>  rate = rate / apb_div;
>>  }
>>  break;
>> +case BCLK_SDCLK:
>> +{
>> +ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
>> +  & SCU_SDCLK_DIV_MASK)
>> + >> SCU_SDCLK_DIV_SHIFT);
>> +rate = ast2500_get_hpll_rate(clkin,
>> + readl(&priv->
>> +   scu->h_pll_param));
>> +rate = rate / apb_div;
>> +}
>> +break;
>>  case PCLK_UART1:
>>  rate = ast2500_get_uart_clk_rate(priv->scu, 1);
>>  break;
>> @@ -436,6 +447,22 @@ static int ast2500_clk_enable(struct clk *clk)
>>  struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
>>
>>  switch (clk->id) {
>> +case BCLK_SDCLK:
>> +if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
>> +ast_scu_unlock(priv->scu);
>> +
>> +setbits_le32(&priv->scu->sysreset_ctrl1,
>> + SCU_SYSRESET_SDIO);
>> +udelay(100);
>> +clrbits_le32(&priv->scu->clk_stop_ctrl1,
>> + SCU_CLKSTOP_SDCLK);
>> +mdelay(10);
>> +clrbits_le32(&priv->scu->sysreset_ctrl1,

Re: [U-Boot] [PATCH v2 0/4] NC-SI PHY Support

[Cédric Le Goater]

On 18/06/2019 03:37, Samuel Mendoza-Jonas wrote:
> This series introduces support for the NC-SI protocol to u-boot,
> functionality which so far has only been available in vendor trees.

Would it be complex to add a romulus DT and config file ? 

Thanks,

C. 

> 
> NC-SI (Network Controller Sideband Interface) is a protocol to manage a
> sideband connection to a proper network interface, for example a BMC
> (Baseboard Management Controller) sharing the NIC of the host system.
> Probing and configuration occurs by communicating with the "remote" NIC
> via NC-SI control frames (Ethernet header 0x88f8).
> 
> Since the RFC[0] the changes have been split out into a few different
> patches to make the overall changes more obvious. Additionally a few
> small improvements have been added including adding a check to see if
> NC-SI is already configured, and marking the PHY bus "reset" as invalid
> since it does not define a bus.
> 
> An example of NC-SI setup before a normal network command:
> 
> => dhcp
> net_loop: configuring NCSI first
> ethernet@1e66: link up, 100 Mbps full-duplex mac:0c:c4:7a:d5:48:43
> NCSI: probing channels
> NCSI: configuring channel 0
> NCSI: configuration done!
> BOOTP broadcast 1
> BOOTP broadcast 2
> DHCP client bound to address 10.61.161.188 (255 ms)
> 
> [0]: https://patchwork.ozlabs.org/patch/1107087/
> 
> Changes in v2:
> - Fix endianess issue when setting MAC address
> - Make checksum offsets easier to read
> - Instantiate per-phy ncsi_priv structures
> - Update ncsi command help text
> - Used update ncsi-pkt.h version to include SPDX header
> 
> 
> Samuel Mendoza-Jonas (4):
>   phy: Add support for the NC-SI protocol
>   phy: Include NC-SI in phy setup
>   net/ftgmac100: Add NC-SI mode support
>   net: NC-SI setup and handling
> 
>  cmd/Kconfig  |   8 +
>  cmd/net.c|  18 +
>  drivers/net/ftgmac100.c  |  39 +-
>  drivers/net/phy/Kconfig  |   4 +
>  drivers/net/phy/Makefile |   1 +
>  drivers/net/phy/ncsi.c   | 896 +++
>  drivers/net/phy/phy.c|   7 +
>  include/net.h|   3 +-
>  include/net/ncsi-pkt.h   | 442 +++
>  include/net/ncsi.h   |  14 +
>  include/phy.h|  12 +
>  include/phy_interface.h  |   2 +
>  net/net.c|  27 +-
>  13 files changed, 1461 insertions(+), 12 deletions(-)
>  create mode 100644 drivers/net/phy/ncsi.c
>  create mode 100644 include/net/ncsi-pkt.h
>  create mode 100644 include/net/ncsi.h
> 

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Re: [U-Boot] [PATCH v2 3/4] net/ftgmac100: Add NC-SI mode support

[Cédric Le Goater]

On 18/06/2019 03:37, Samuel Mendoza-Jonas wrote:
> Update the ftgmac100 driver to support NC-SI instead of an mdio phy
> where available. This is a common setup for Aspeed AST2x00 platforms.
> 
> NC-SI mode is determined from the device-tree if either phy-mode sets it
> or the use-ncsi property exists. If set then normal mdio setup is
> skipped in favour of the NC-SI phy.
> 
> Signed-off-by: Samuel Mendoza-Jonas 


LGTM. Some very minor remarks below in case you resend.

Reviewed-by: Cédric Le Goater 

Thanks,

C.

> ---
>  drivers/net/ftgmac100.c | 39 +--
>  1 file changed, 29 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
> index 92c38a81bd..c0100e91c7 100644
> --- a/drivers/net/ftgmac100.c
> +++ b/drivers/net/ftgmac100.c
> @@ -18,6 +18,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #include "ftgmac100.h"
>  
> @@ -81,6 +82,7 @@ struct ftgmac100_data {
>   struct mii_dev *bus;
>   u32 phy_mode;
>   u32 max_speed;
> + bool ncsi_mode;
>  
>   struct clk_bulk clks;
>  
> @@ -181,7 +183,7 @@ static int ftgmac100_phy_adjust_link(struct 
> ftgmac100_data *priv)
>   struct phy_device *phydev = priv->phydev;
>   u32 maccr;
>  
> - if (!phydev->link) {
> + if (!phydev->link && !priv->ncsi_mode) {
>   dev_err(phydev->dev, "No link\n");
>   return -EREMOTEIO;
>   }
> @@ -217,7 +219,8 @@ static int ftgmac100_phy_init(struct udevice *dev)
>   if (!phydev)
>   return -ENODEV;
>  
> - phydev->supported &= PHY_GBIT_FEATURES;
> + if (!priv->ncsi_mode)
> + phydev->supported &= PHY_GBIT_FEATURES;
>   if (priv->max_speed) {
>   ret = phy_set_supported(phydev, priv->max_speed);
>   if (ret)
> @@ -275,7 +278,8 @@ static void ftgmac100_stop(struct udevice *dev)
>  
>   writel(0, &ftgmac100->maccr);
>  
> - phy_shutdown(priv->phydev);
> + if (!priv->ncsi_mode)
> + phy_shutdown(priv->phydev);
>  }
>  
>  static int ftgmac100_start(struct udevice *dev)
> @@ -513,6 +517,7 @@ static int ftgmac100_ofdata_to_platdata(struct udevice 
> *dev)
>   pdata->iobase = devfdt_get_addr(dev);
>   pdata->phy_interface = -1;
>   phy_mode = dev_read_string(dev, "phy-mode");
> +
>   if (phy_mode)
>   pdata->phy_interface = phy_get_interface_by_name(phy_mode);
>   if (pdata->phy_interface == -1) {
> @@ -537,8 +542,13 @@ static int ftgmac100_probe(struct udevice *dev)
>  {
>   struct eth_pdata *pdata = dev_get_platdata(dev);
>   struct ftgmac100_data *priv = dev_get_priv(dev);
> + const char *phy_mode;
>   int ret;
>  
> + phy_mode = dev_read_string(dev, "phy-mode");
> + priv->ncsi_mode = dev_read_bool(dev, "use-ncsi") ||
> + (phy_mode && strcmp(phy_mode, "NC-SI") == 0);

strncmp() may be ? I think a helper routine would make sense. 

> +
>   priv->iobase = (struct ftgmac100 *)pdata->iobase;
>   priv->phy_mode = pdata->phy_interface;
>   priv->max_speed = pdata->max_speed;
> @@ -548,10 +558,15 @@ static int ftgmac100_probe(struct udevice *dev)
>   if (ret)
>   goto out;
>  
> - ret = ftgmac100_mdio_init(dev);
> - if (ret) {
> - dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
> - goto out;
> + if (priv->ncsi_mode) {
> + printf("%s - NCSI detected\n", __func__);

"NC-SI"

> + } else {
> + ret = ftgmac100_mdio_init(dev);
> + if (ret) {
> + dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
> + goto out;
> + }
> +
>   }
>  
>   ret = ftgmac100_phy_init(dev);
> @@ -571,9 +586,13 @@ static int ftgmac100_remove(struct udevice *dev)
>  {
>   struct ftgmac100_data *priv = dev_get_priv(dev);
>  
> - free(priv->phydev);
> - mdio_unregister(priv->bus);
> - mdio_free(priv->bus);
> + if (!priv->ncsi_mode) {
> + free(priv->phydev);
> + mdio_unregister(priv->bus);
> + mdio_free(priv->bus);
> + } else {
> + free(priv->phydev);
> + }
>   clk_release_bulk(&priv->clks);
>  
>   return 0;
> 

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Re: [U-Boot] [PATCH 2/3] spi: Add support for the Aspeed ast2500 SPI controllers

[Cédric Le Goater]

Hello

On 10/10/18 2:02 PM, Cédric Le Goater wrote:
> Hello Boris,
> 
> On 10/10/18 9:32 AM, Boris Brezillon wrote:
>> Hi Cédric,
>>
>> On Wed, 10 Oct 2018 11:46:56 +0530
>> Jagan Teki  wrote:
>>
>>> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater  wrote:
>>>>
>>>> On 10/4/18 5:57 PM, Jagan Teki wrote:  
>>>>> On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater  wrote:  
>>>>>>
>>>>>> Hello Simon,
>>>>>>
>>>>>>
>>>>>> The Aspeed AST2500 FMC controller can handle SPI flash and NOR flash 
>>>>>> memory,
>>>>>> and the Aspeed AST2500 SPI Flash Controllers only SPI. If there is some
>>>>>> misunderstanding on this driver, it might come from the fact it is closer
>>>>>> to a SPI-NOR driver like we have in Linux, than a generic SPI driver.
>>>>>> The stm32 SPI driver is somewhat similar.
>>>>>>
>>>>>> Should we move it under drivers/mtd/spi/ maybe ?  
>>>>>
>>>>> Seems with new spi-mem in Linux flash memory driver rely on spi-mem
>>>>> instead of mtd/spi-nor. So I think you can handle this via new
>>>>> spi-mem. have you send any patches to Linux?  
>>>>
>>>> No, not yet. The patchset is sent  :
>>>>
>>>> https://patchwork.ozlabs.org/cover/933293/
>>>>
>>>> is not using spimem. I was not aware of that change in the spi-nor layer
>>>> at the time. I will take a look.  
>>
>> Indeed, if you have some time to convert the Linux aspeed driver to
>> the spi-mem interface that would be appreciated.
> 
> Yes. That's the plan. I have a series on the way but I will see if I can
> rework a v2 to use spi-mem. 

I took a look at spi-mem and worked on an initial spi-aspeed-smc driver
using the new framework in Linux 5.0.x. It looks good but I have a couple
of questions.  


The first is about performing direct accesses on the AHB window on which 
the flash contents is mapped. 

How do you distinguish a flash read (fast, dual, etc) from a RDSFPD command 
for instance ? Are the drivers expected to check the SPI OP command and 
depending on the target/command redirect to the appropriate address space ?   

Also, Aspeed SPI controllers have a Read Timing Compensation Register which
defines different data input delay cycles depending on SPI clock rates. This 
register is supposed to be tuned when the flash chip characteristics are 
known, after the first bus scan. Is there a way to know that our SPI slave 
is alive and well detected before starting hammering successive reads on it 
to see how it behaves.


I think the U-Boot and Linux driver will be very similar wrt the issues 
above ? 

> Same for the u-boot aspeed spi driver which needs a spi-mem refresh if 
> I understand correctly. 

U-Boot, I haven't looked at yet but I expect the driver to be very similar.

Thanks,

C.
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[U-Boot] [PATCH v5 13/13] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode

[Cédric Le Goater]

The algorithm in the ast2500_calc_clock_config() routine suffers from
integer rounding and the requested rate does not get the appropriate
set of Numerator, Denumerator, Post Divider parameters.

This is the case for the D2-PLL clock used by the MAC controllers in
RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.

The easiest way to fix this problem is to introduce an array of clock
settings defining the N, M, P parameters for well known frequencies
used by the Aspeed SoC.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/clk/aspeed/clk_ast2500.c | 38 
 1 file changed, 38 insertions(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 2182320f607f..dbee13a18297 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
 }
 
+struct ast2500_clock_config {
+   ulong input_rate;
+   ulong rate;
+   struct ast2500_div_config cfg;
+};
+
+static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
+   { 2400, 25000, { .num = 124, .denum = 1, .post_div = 5 } },
+};
+
+static bool ast2500_get_clock_config_default(ulong input_rate,
+ulong requested_rate,
+struct ast2500_div_config *cfg)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
+   const struct ast2500_clock_config *default_cfg =
+   &ast2500_clock_config_defaults[i];
+   if (default_cfg->input_rate == input_rate &&
+   default_cfg->rate == requested_rate) {
+   *cfg = default_cfg->cfg;
+   return true;
+   }
+   }
+
+   return false;
+}
+
 /*
  * @input_rate - the rate of input clock in Hz
  * @requested_rate - desired output rate in Hz
@@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rate, 
ulong requested_rate,
ulong delta = rate_khz;
ulong new_rate_khz = 0;
 
+   /*
+* Look for a well known frequency first.
+*/
+   if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
+   return requested_rate;
+
for (; it.denum <= max_vals.denum; ++it.denum) {
for (it.post_div = 0; it.post_div <= max_vals.post_div;
 ++it.post_div) {
@@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu 
*scu, ulong rate)
/*
 * The values and the meaning of the next three
 * parameters are undocumented. Taken from Aspeed SDK.
+*
+* TODO(c...@kaod.org): the SIP and SIC values depend on the
+* Numerator value
 */
const u32 d2_pll_ext_param = 0x2c;
const u32 d2_pll_sip = 0x11;
-- 
2.17.2

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[U-Boot] [PATCH v5 12/13] aspeed: Activate ethernet devices on the ast2500 Eval Board

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 arch/arm/dts/ast2500-evb.dts | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 723941ac0bee..ebf44fd707f9 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -11,6 +11,11 @@
chosen {
stdout-path = &uart5;
};
+
+   aliases {
+   ethernet0 = &mac0;
+   ethernet1 = &mac1;
+   };
 };
 
 &uart5 {
@@ -36,3 +41,21 @@
u-boot,dm-pre-reloc;
status = "okay";
 };
+
+&mac0 {
+   status = "okay";
+
+   phy-mode = "rgmii";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>;
+};
+
+&mac1 {
+   status = "okay";
+
+   phy-mode = "rgmii";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
+};
-- 
2.17.2

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[U-Boot] [PATCH v5 07/13] net: ftgmac100: handle timeouts when transmitting

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
---

 Changes since v4 :

 - defined a custom wait_for_bit_*() macro

 drivers/net/ftgmac100.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index bf8600814690..ec46add1d35c 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -28,6 +29,9 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/* Timeout for transmit */
+#define FTGMAC100_TX_TIMEOUT_MS1000
+
 /* Timeout for a mdio read/write operation */
 #define FTGMAC100_MDIO_TIMEOUT_USEC1
 
@@ -401,6 +405,19 @@ static int ftgmac100_recv(struct udevice *dev, int flags, 
uchar **packetp)
return rxlen;
 }
 
+static u32 ftgmac100_read_txdesc(const void *desc)
+{
+   const struct ftgmac100_txdes *txdes = desc;
+   ulong des_start = (ulong)txdes;
+   ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
+
+   invalidate_dcache_range(des_start, des_end);
+
+   return txdes->txdes0;
+}
+
+BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
+
 /*
  * Send a data block via Ethernet
  */
@@ -414,6 +431,7 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
ulong data_start;
ulong data_end;
+   int rc;
 
invalidate_dcache_range(des_start, des_end);
 
@@ -446,6 +464,12 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
/* Start transmit */
writel(1, &ftgmac100->txpd);
 
+   rc = wait_for_bit_ftgmac100_txdone(curr_des,
+  FTGMAC100_TXDES0_TXDMA_OWN, false,
+  FTGMAC100_TX_TIMEOUT_MS, true);
+   if (rc)
+   return rc;
+
debug("%s(): packet sent\n", __func__);
 
/* Move to next descriptor */
-- 
2.17.2

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[U-Boot] [PATCH v5 11/13] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level

[Cédric Le Goater]

This is a large update of the AST2500 SoC DTS file bringing it to the
level of commit 927c2fc2db19 :

Author:  Joel Stanley 
Date:Sat Jun 2 01:18:53 2018 -0700

 ARM: dts: aspeed: Fix hwrng register address

There are some differences on the compatibility property names. scu,
reset and clock drivers are also different.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Reviewed-by: Simon Glass 
Acked-by: Joe Hershberger 
---
 arch/arm/dts/ast2500.dtsi | 1949 ++---
 1 file changed, 1153 insertions(+), 796 deletions(-)

diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 7e0ad3a41ac5..98359bf92425 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -11,6 +11,29 @@
#size-cells = <1>;
interrupt-parent = <&vic>;
 
+   aliases {
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   i2c2 = &i2c2;
+   i2c3 = &i2c3;
+   i2c4 = &i2c4;
+   i2c5 = &i2c5;
+   i2c6 = &i2c6;
+   i2c7 = &i2c7;
+   i2c8 = &i2c8;
+   i2c9 = &i2c9;
+   i2c10 = &i2c10;
+   i2c11 = &i2c11;
+   i2c12 = &i2c12;
+   i2c13 = &i2c13;
+   serial0 = &uart1;
+   serial1 = &uart2;
+   serial2 = &uart3;
+   serial3 = &uart4;
+   serial4 = &uart5;
+   serial5 = &vuart;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -22,12 +45,80 @@
};
};
 
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0>;
+   };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
 
+   fmc: flash-controller@1e62 {
+   reg = < 0x1e62 0xc4
+   0x2000 0x1000 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-fmc";
+   status = "disabled";
+   interrupts = <19>;
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@2 {
+   reg = < 2 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   };
+
+   spi1: flash-controller@1e63 {
+   reg = < 0x1e63 0xc4
+   0x3000 0x0800 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-spi";
+   status = "disabled";
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   };
+
+   spi2: flash-controller@1e631000 {
+   reg = < 0x1e631000 0xc4
+   0x3800 0x0800 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-spi";
+   status = "disabled";
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status =

[U-Boot] [PATCH v5 08/13] net: ftgmac100: add clock support

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index ec46add1d35c..798977616756 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -11,6 +11,7 @@
  * Copyright (C) 2018, IBM Corporation.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -55,6 +56,7 @@
  * @bus: The mdio bus
  * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  * @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @clks: The bulk of clocks assigned to the device in the DT
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -69,6 +71,8 @@ struct ftgmac100_data {
struct mii_dev *bus;
u32 phy_mode;
u32 max_speed;
+
+   struct clk_bulk clks;
 };
 
 /*
@@ -489,6 +493,7 @@ static int ftgmac100_write_hwaddr(struct udevice *dev)
 static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
+   struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
 
pdata->iobase = devfdt_get_addr(dev);
@@ -503,7 +508,7 @@ static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
 
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
-   return 0;
+   return clk_get_bulk(dev, &priv->clks);
 }
 
 static int ftgmac100_probe(struct udevice *dev)
@@ -517,6 +522,10 @@ static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
 
+   ret = clk_enable_bulk(&priv->clks);
+   if (ret)
+   goto out;
+
ret = ftgmac100_mdio_init(dev);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
@@ -530,6 +539,9 @@ static int ftgmac100_probe(struct udevice *dev)
}
 
 out:
+   if (ret)
+   clk_release_bulk(&priv->clks);
+
return ret;
 }
 
@@ -540,6 +552,7 @@ static int ftgmac100_remove(struct udevice *dev)
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+   clk_release_bulk(&priv->clks);
 
return 0;
 }
-- 
2.17.2

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[U-Boot] [PATCH v5 09/13] aspeed: ast2500: fix missing break in D2PLL clock enablement

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Reviewed-by: Simon Glass 
Acked-by: Joe Hershberger 
---
 drivers/clk/aspeed/clk_ast2500.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 526470051c5d..2182320f607f 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -411,6 +411,7 @@ static int ast2500_clk_enable(struct clk *clk)
break;
case PLL_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
+   break;
default:
return -ENOENT;
}
-- 
2.17.2

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[U-Boot] [PATCH v5 05/13] net: ftgmac100: add MDIO bus and phylib support

[Cédric Le Goater]

Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c | 380 +---
 1 file changed, 160 insertions(+), 220 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 78cd9df62986..b6e6f6e5ec02 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ftgmac100.h"
 
@@ -29,6 +30,16 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/* Timeout for a mdio read/write operation */
+#define FTGMAC100_MDIO_TIMEOUT_USEC1
+
+/*
+ * MDC clock cycle threshold
+ *
+ * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
+ */
+#define MDC_CYCTHR 0x34
+
 /**
  * struct ftgmac100_data - private data for the FTGMAC100 driver
  *
@@ -38,6 +49,10 @@
  * @tx_index: Transmit descriptor index in @txdes
  * @rx_index: Receive descriptor index in @rxdes
  * @phy_addr: The PHY interface address to use
+ * @phydev: The PHY device backing the MAC
+ * @bus: The mdio bus
+ * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
+ * @max_speed: Maximum speed of Ethernet connection supported by MAC
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -48,234 +63,110 @@ struct ftgmac100_data {
struct ftgmac100_rxdes *rxdes;
int tx_index;
int rx_index;
-   int phy_addr;
+
+   u32 phy_addr;
+   struct phy_device *phydev;
+   struct mii_dev *bus;
+   u32 phy_mode;
+   u32 max_speed;
 };
 
 /*
  * struct mii_bus functions
  */
-static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr,
- int regnum)
+static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+  int reg_addr)
 {
+   struct ftgmac100_data *priv = bus->priv;
struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
-   int i;
-
-   phycr = readl(&ftgmac100->phycr);
-
-   /* preserve MDC cycle threshold */
-   phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
-   phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- |  FTGMAC100_PHYCR_REGAD(regnum)
- |  FTGMAC100_PHYCR_MIIRD;
+   int data;
+   int ret;
 
+   phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+   FTGMAC100_PHYCR_PHYAD(phy_addr) |
+   FTGMAC100_PHYCR_REGAD(reg_addr) |
+   FTGMAC100_PHYCR_MIIRD;
writel(phycr, &ftgmac100->phycr);
 
-   for (i = 0; i < 10; i++) {
-   phycr = readl(&ftgmac100->phycr);
-
-   if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
-   int data;
-
-   data = readl(&ftgmac100->phydata);
-   return FTGMAC100_PHYDATA_MIIRDATA(data);
-   }
-
-   mdelay(10);
+   ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
+!(phycr & FTGMAC100_PHYCR_MIIRD),
+FTGMAC100_MDIO_TIMEOUT_USEC);
+   if (ret) {
+   pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
+  priv->phydev->dev->name, phy_addr, reg_addr);
+   return ret;
}
 
-   debug("mdio read timed out\n");
-   return -1;
+   data = readl(&ftgmac100->phydata);
+
+   return FTGMAC100_PHYDATA_MIIRDATA(data);
 }
 
-static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int phy_addr,
-  int regnum, u16 value)
+static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int 
dev_addr,
+   int reg_addr, u16 value)
 {
+   struct ftgmac100_data *priv = bus->priv;
struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int data;
-   int i;
-
-   phycr = readl(&ftgmac100->phycr);
-
-   /* preserve MDC cycle threshold */
-   phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
-   phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- |  FTGMAC100_PHYCR_REGAD(regnum)
- |  FTGMAC100_PHYCR_MIIWR;
+   int ret;
 
+   phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+   FTGMAC100_PHYCR_PHYAD(phy_addr) |
+   FTGMAC100_PHYCR_REGAD(reg_addr) |
+   FTGMAC100_PHYCR_MIIWR;
data = FTGMAC100_PHYDATA_MIIWDATA(value);
 
writel(data, &ftgmac100->phydata);
writel(phycr, &ftgmac100->phycr);
 
-   for (i = 0; i < 10; i++) {
-   phycr = readl(&ftgmac100->phycr);
-
-   if ((phycr & F

[U-Boot] [PATCH v5 10/13] net: ftgmac100: Add support for the Aspeed SoC

[Cédric Le Goater]

The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c   | 31 +++
 configs/evb-ast2500_defconfig |  8 
 2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 798977616756..92c38a81bd35 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -43,6 +43,14 @@
  */
 #define MDC_CYCTHR 0x34
 
+/*
+ * ftgmac100 model variants
+ */
+enum ftgmac100_model {
+   FTGMAC100_MODEL_FARADAY,
+   FTGMAC100_MODEL_ASPEED,
+};
+
 /**
  * struct ftgmac100_data - private data for the FTGMAC100 driver
  *
@@ -57,6 +65,8 @@
  * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  * @max_speed: Maximum speed of Ethernet connection supported by MAC
  * @clks: The bulk of clocks assigned to the device in the DT
+ * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
+ * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -73,6 +83,10 @@ struct ftgmac100_data {
u32 max_speed;
 
struct clk_bulk clks;
+
+   /* End of RX/TX ring buffer bits. Depend on model */
+   u32 rxdes0_edorr_mask;
+   u32 txdes0_edotr_mask;
 };
 
 /*
@@ -293,7 +307,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->txdes[i].txdes3 = 0;
priv->txdes[i].txdes0 = 0;
}
-   priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+   priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
 
start = (ulong)&priv->txdes[0];
end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
@@ -303,7 +317,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
priv->rxdes[i].rxdes0 = 0;
}
-   priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+   priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
 
start = (ulong)&priv->rxdes[0];
end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
@@ -456,7 +470,7 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
flush_dcache_range(data_start, data_end);
 
/* Only one segment on TXBUF */
-   curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
+   curr_des->txdes0 &= priv->txdes0_edotr_mask;
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
FTGMAC100_TXDES0_LTS |
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
@@ -508,6 +522,14 @@ static int ftgmac100_ofdata_to_platdata(struct udevice 
*dev)
 
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
+   if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
+   priv->rxdes0_edorr_mask = BIT(30);
+   priv->txdes0_edotr_mask = BIT(30);
+   } else {
+   priv->rxdes0_edorr_mask = BIT(15);
+   priv->txdes0_edotr_mask = BIT(15);
+   }
+
return clk_get_bulk(dev, &priv->clks);
 }
 
@@ -567,7 +589,8 @@ static const struct eth_ops ftgmac100_ops = {
 };
 
 static const struct udevice_id ftgmac100_ids[] = {
-   { .compatible = "faraday,ftgmac100" },
+   { .compatible = "faraday,ftgmac100",  .data = FTGMAC100_MODEL_FARADAY },
+   { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED  },
{ }
 };
 
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 88230f4a12db..32581f5ada54 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -25,3 +25,11 @@ CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER=y
 CONFIG_WDT=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_FTGMAC100=y
+CONFIG_PHY_REALTEK=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
-- 
2.17.2

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[U-Boot] [PATCH v5 04/13] net: ftgmac100: use setbits_le32() in the reset method

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 67a7c73503c5..78cd9df62986 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -331,7 +331,7 @@ static void ftgmac100_reset(struct ftgmac100_data *priv)
 
debug("%s()\n", __func__);
 
-   writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
+   setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
 
while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
;
-- 
2.17.2

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[U-Boot] [PATCH v5 06/13] net: ftgmac100: convert the RX/TX descriptor arrays

[Cédric Le Goater]

Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c | 141 ++--
 1 file changed, 64 insertions(+), 77 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index b6e6f6e5ec02..bf8600814690 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -13,19 +13,17 @@
 
 #include 
 #include 
-#include 
 #include 
 #include 
-#include 
 #include 
 
 #include "ftgmac100.h"
 
-#define ETH_ZLEN   60
-#define CFG_XBUF_SIZE  1536
+/* Min frame ethernet frame size without FCS */
+#define ETH_ZLEN   60
 
-/* RBSR - hw default init value is also 0x640 */
-#define RBSR_DEFAULT_VALUE 0x640
+/* Receive Buffer Size Register - HW default is 0x640 */
+#define FTGMAC100_RBSR_DEFAULT 0x640
 
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
@@ -57,10 +55,8 @@
 struct ftgmac100_data {
struct ftgmac100 *iobase;
 
-   ulong txdes_dma;
-   struct ftgmac100_txdes *txdes;
-   ulong rxdes_dma;
-   struct ftgmac100_rxdes *rxdes;
+   struct ftgmac100_txdes txdes[PKTBUFSTX];
+   struct ftgmac100_rxdes rxdes[PKTBUFSRX];
int tx_index;
int rx_index;
 
@@ -266,10 +262,8 @@ static int ftgmac100_start(struct udevice *dev)
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct phy_device *phydev = priv->phydev;
-   struct ftgmac100_txdes *txdes;
-   struct ftgmac100_rxdes *rxdes;
unsigned int maccr;
-   void *buf;
+   ulong start, end;
int ret;
int i;
 
@@ -277,26 +271,6 @@ static int ftgmac100_start(struct udevice *dev)
 
ftgmac100_reset(priv);
 
-   if (!priv->txdes) {
-   txdes = dma_alloc_coherent(
-   sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
-   if (!txdes)
-   panic("ftgmac100: out of memory\n");
-   memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
-   priv->txdes = txdes;
-   }
-   txdes = priv->txdes;
-
-   if (!priv->rxdes) {
-   rxdes = dma_alloc_coherent(
-   sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
-   if (!rxdes)
-   panic("ftgmac100: out of memory\n");
-   memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
-   priv->rxdes = rxdes;
-   }
-   rxdes = priv->rxdes;
-
/* set the ethernet address */
ftgmac100_set_mac(priv, plat->enetaddr);
 
@@ -307,42 +281,37 @@ static int ftgmac100_start(struct udevice *dev)
priv->tx_index = 0;
priv->rx_index = 0;
 
-   txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
-   rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
-
for (i = 0; i < PKTBUFSTX; i++) {
-   /* TXBUF_BADR */
-   if (!txdes[i].txdes2) {
-   buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
-   if (!buf)
-   panic("ftgmac100: out of memory\n");
-   txdes[i].txdes3 = virt_to_phys(buf);
-   txdes[i].txdes2 = (uint)buf;
-   }
-   txdes[i].txdes1 = 0;
+   priv->txdes[i].txdes3 = 0;
+   priv->txdes[i].txdes0 = 0;
}
+   priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+
+   start = (ulong)&priv->txdes[0];
+   end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
+   flush_dcache_range(start, end);
 
for (i = 0; i < PKTBUFSRX; i++) {
-   /* RXBUF_BADR */
-   if (!rxdes[i].rxdes2) {
-   buf = net_rx_packets[i];
-   rxdes[i].rxdes3 = virt_to_phys(buf);
-   rxdes[i].rxdes2 = (uint)buf;
-   }
-   rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+   priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+   priv->rxdes[i].rxdes0 = 0;
}
+   priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+
+   start = (ulong)&priv->rxdes[0];
+   end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
+   flush_dcache_range(start, end);
 
/* transmit ring */
-   writel(priv->txdes_dma, &ftgmac100->txr_badr);
+   writel((u32)priv->txdes, &ftgmac100->txr_badr);
 
/* receive ring */
-   writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
+   writel((u32)priv->

[U-Boot] [PATCH v5 03/13] net: ftgmac100: convert to driver model

[Cédric Le Goater]

The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 include/netdev.h|   1 -
 drivers/net/ftgmac100.c | 223 +++-
 drivers/net/Kconfig |  26 +
 3 files changed, 157 insertions(+), 93 deletions(-)

diff --git a/include/netdev.h b/include/netdev.h
index 55001625fb92..0a1a3a2d8da2 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
 int fec_initialize (bd_t *bis);
 int fecmxc_initialize(bd_t *bis);
 int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
-int ftgmac100_initialize(bd_t *bits);
 int ftmac100_initialize(bd_t *bits);
 int ftmac110_initialize(bd_t *bits);
 void gt6426x_eth_initialize(bd_t *bis);
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index c996f5f4a167..67a7c73503c5 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -7,15 +7,16 @@
  *
  * (C) Copyright 2010 Andes Technology
  * Macpaul Lin 
+ *
+ * Copyright (C) 2018, IBM Corporation.
  */
 
-#include 
-#include 
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
-#include 
 
 #include "ftgmac100.h"
 
@@ -28,7 +29,19 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/**
+ * struct ftgmac100_data - private data for the FTGMAC100 driver
+ *
+ * @iobase: The base address of the hardware registers
+ * @txdes: The array of transmit descriptors
+ * @rxdes: The array of receive descriptors
+ * @tx_index: Transmit descriptor index in @txdes
+ * @rx_index: Receive descriptor index in @rxdes
+ * @phy_addr: The PHY interface address to use
+ */
 struct ftgmac100_data {
+   struct ftgmac100 *iobase;
+
ulong txdes_dma;
struct ftgmac100_txdes *txdes;
ulong rxdes_dma;
@@ -41,10 +54,10 @@ struct ftgmac100_data {
 /*
  * struct mii_bus functions
  */
-static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
-   int regnum)
+static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr,
+ int regnum)
 {
-   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+   struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int i;
 
@@ -76,10 +89,10 @@ static int ftgmac100_mdiobus_read(struct eth_device *dev, 
int phy_addr,
return -1;
 }
 
-static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
-   int regnum, u16 value)
+static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int phy_addr,
+  int regnum, u16 value)
 {
-   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+   struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int data;
int i;
@@ -114,9 +127,10 @@ static int ftgmac100_mdiobus_write(struct eth_device *dev, 
int phy_addr,
return -1;
 }
 
-int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
+int ftgmac100_phy_read(struct ftgmac100_data *priv, int addr, int reg,
+  u16 *value)
 {
-   *value = ftgmac100_mdiobus_read(dev , addr, reg);
+   *value = ftgmac100_mdiobus_read(priv, addr, reg);
 
if (*value == -1)
return -1;
@@ -124,31 +138,31 @@ int ftgmac100_phy_read(struct eth_device *dev, int addr, 
int reg, u16 *value)
return 0;
 }
 
-int  ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
+int ftgmac100_phy_write(struct ftgmac100_data *priv, int addr, int reg,
+   u16 value)
 {
-   if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
+   if (ftgmac100_mdiobus_write(priv, addr, reg, value) == -1)
return -1;
 
return 0;
 }
 
-static int ftgmac100_phy_reset(struct eth_device *dev)
+static int ftgmac100_phy_reset(struct ftgmac100_data *priv, struct udevice 
*dev)
 {
-   struct ftgmac100_data *priv = dev->priv;
int i;
u16 status, adv;
 
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
 
-   ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
+   ftgmac100_phy_write(priv, priv->phy_addr, MII_ADVERTISE, adv);
 
printf("%s: Starting autonegotiation...\n", dev->name);
 
-   ftgmac100_phy_write(dev, priv->phy_addr,
-   MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
+   ftgmac100_phy_write(priv, priv->phy_addr,
+   MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
 
for (i = 0; i < 10 / 100

[U-Boot] [PATCH v5 02/13] net: ftgmac100: use the aligned() macro

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index 439b14d71e4b..9a789e4d5bee 100644
--- a/drivers/net/ftgmac100.h
+++ b/drivers/net/ftgmac100.h
@@ -182,7 +182,7 @@ struct ftgmac100_txdes {
unsigned inttxdes1;
unsigned inttxdes2; /* not used by HW */
unsigned inttxdes3; /* TXBUF_BADR */
-} __attribute__ ((aligned(16)));
+} __aligned(16);
 
 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
 #define FTGMAC100_TXDES0_EDOTR BIT(15)
@@ -208,7 +208,7 @@ struct ftgmac100_rxdes {
unsigned intrxdes1;
unsigned intrxdes2; /* not used by HW */
unsigned intrxdes3; /* RXBUF_BADR */
-} __attribute__ ((aligned(16)));
+} __aligned(16);
 
 #define FTGMAC100_RXDES0_VDBC(x)   ((x) & 0x3fff)
 #define FTGMAC100_RXDES0_EDORR BIT(15)
-- 
2.17.2

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[U-Boot] [PATCH v5 01/13] net: ftgmac100: use the BIT() macro

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.h | 154 
 1 file changed, 77 insertions(+), 77 deletions(-)

diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index ffbe1f3e3fa7..439b14d71e4b 100644
--- a/drivers/net/ftgmac100.h
+++ b/drivers/net/ftgmac100.h
@@ -70,48 +70,48 @@ struct ftgmac100 {
 /*
  * Interrupt status register & interrupt enable register
  */
-#define FTGMAC100_INT_RPKT_BUF (1 << 0)
-#define FTGMAC100_INT_RPKT_FIFO(1 << 1)
-#define FTGMAC100_INT_NO_RXBUF (1 << 2)
-#define FTGMAC100_INT_RPKT_LOST(1 << 3)
-#define FTGMAC100_INT_XPKT_ETH (1 << 4)
-#define FTGMAC100_INT_XPKT_FIFO(1 << 5)
-#define FTGMAC100_INT_NO_NPTXBUF   (1 << 6)
-#define FTGMAC100_INT_XPKT_LOST(1 << 7)
-#define FTGMAC100_INT_AHB_ERR  (1 << 8)
-#define FTGMAC100_INT_PHYSTS_CHG   (1 << 9)
-#define FTGMAC100_INT_NO_HPTXBUF   (1 << 10)
+#define FTGMAC100_INT_RPKT_BUF BIT(0)
+#define FTGMAC100_INT_RPKT_FIFOBIT(1)
+#define FTGMAC100_INT_NO_RXBUF BIT(2)
+#define FTGMAC100_INT_RPKT_LOSTBIT(3)
+#define FTGMAC100_INT_XPKT_ETH BIT(4)
+#define FTGMAC100_INT_XPKT_FIFOBIT(5)
+#define FTGMAC100_INT_NO_NPTXBUF   BIT(6)
+#define FTGMAC100_INT_XPKT_LOSTBIT(7)
+#define FTGMAC100_INT_AHB_ERR  BIT(8)
+#define FTGMAC100_INT_PHYSTS_CHG   BIT(9)
+#define FTGMAC100_INT_NO_HPTXBUF   BIT(10)
 
 /*
  * Interrupt timer control register
  */
 #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
 #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
-#define FTGMAC100_ITC_RXINT_TIME_SEL   (1 << 7)
+#define FTGMAC100_ITC_RXINT_TIME_SEL   BIT(7)
 #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
 #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
-#define FTGMAC100_ITC_TXINT_TIME_SEL   (1 << 15)
+#define FTGMAC100_ITC_TXINT_TIME_SEL   BIT(15)
 
 /*
  * Automatic polling timer control register
  */
 #define FTGMAC100_APTC_RXPOLL_CNT(x)   (((x) & 0xf) << 0)
-#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
+#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
 #define FTGMAC100_APTC_TXPOLL_CNT(x)   (((x) & 0xf) << 8)
-#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
+#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
 
 /*
  * DMA burst length and arbitration control register
  */
 #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
 #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
-#define FTGMAC100_DBLAC_RX_THR_EN  (1 << 6)
+#define FTGMAC100_DBLAC_RX_THR_EN  BIT(6)
 #define FTGMAC100_DBLAC_RXBURST_SIZE(x)(((x) & 0x3) << 8)
 #define FTGMAC100_DBLAC_TXBURST_SIZE(x)(((x) & 0x3) << 10)
 #define FTGMAC100_DBLAC_RXDES_SIZE(x)  (((x) & 0xf) << 12)
 #define FTGMAC100_DBLAC_TXDES_SIZE(x)  (((x) & 0xf) << 16)
 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
-#define FTGMAC100_DBLAC_IFG_INC(1 << 23)
+#define FTGMAC100_DBLAC_IFG_INCBIT(23)
 
 /*
  * DMA FIFO status register
@@ -122,12 +122,12 @@ struct ftgmac100 {
 #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
 #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
 #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
-#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY(1 << 26)
-#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY(1 << 27)
-#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
-#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
-#define FTGMAC100_DMAFIFOS_RXDMA_REQ   (1 << 30)
-#define FTGMAC100_DMAFIFOS_TXDMA_REQ   (1 << 31)
+#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTYBIT(26)
+#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTYBIT(27)
+#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
+#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
+#define FTGMAC100_DMAFIFOS_RXDMA_REQ   BIT(30)
+#define FTGMAC100_DMAFIFOS_TXDMA_REQ   BIT(31)
 
 /*
  * Receive buffer size register
@@ -137,26 +137,26 @@ struct ftgmac100 {
 /*
  * MAC control register
  */
-#define FTGMAC100_MACCR_TXDMA_EN   (1 << 0)
-#define FTGMAC100_MACCR_RXDMA_EN   (1 << 1)
-#define FTGMAC100_MACCR_TXMAC_EN   (1 << 2)
-#define FTGMAC100_MACCR_RXMAC_EN   (1 << 3)
-#define FTGMAC100_MACCR_RM_VLAN(1 << 4)
-#define FTGMAC100_MACCR_HPTXR_EN   (1 << 5)
-#define FTGMAC100_MACCR_LOOP_EN

[U-Boot] [PATCH v5 00/13] Support for the Faraday ftgmac100 controller

[Cédric Le Goater]

Hello,

This series re-enables the Faraday ftgmac100 controller driver and its
Aspeed variant as as one can find on the OpenPOWER platforms. The
driver is largely reworked to support the driver model and also adds
the MDIO bus and phylib support. It was tested on the AST2500 evb.

Git tree available here:

  https://github.com/legoater/u-boot/commits/aspeed

Thanks,

C.

Changes since v4 :

 - introduced a wait_for_bit macro to handle timeouts when
   transmitting
 
Changes since v3 :

 It didn't seem necessary to remove the 'dev' argument from the
 ftgmac100_phy_init() and ftgmac100_phy_reset() function prototypes as
 the code is completely reworked in patch 5.

 - improved ftgmac100_mdio_init() and ftgmac100_phy_init() prototypes
 - introduced a ftgmac100_wait_for_txdone() function similar to the
   wait_for_bit_*() macros.

Changes since v2 :

 - split changes in multiple patches to preserve git history, but the
   code has not changed since the reviewed v2 patchset.
 - included a couple more changes to sync the DTS file with Linux.

Changes since v1 :

 - improved comments in the code
 - changed the type of 'iobase' to 'struct ftgmac100 *' to remove the
   casts in other routines.
 - replaced the loop in the mdio methods by a call to readl_poll_timeout()
   and fixed the returned value.
 - added a flush cache on the arrays of TX and RX descriptors in
   ftgmac100_start()
 - fixed returned value of 
 - added a timer loop to catch transmit timeouts
 - introduced a clk_bulk
 - improved Kconfig description
 - introduced a udevice_id .data model
 - dropped is_aspeed bool
 - dropped MDIO interface setting for Aspeed SoC. The default is
   correct.
 - removed the clcoks which are now handled automatically in the
   ftgmac100 driver
 - introduced a fix for the D2-PLL clock setting

Cédric Le Goater (13):
  net: ftgmac100: use the BIT() macro
  net: ftgmac100: use the aligned() macro
  net: ftgmac100: convert to driver model
  net: ftgmac100: use setbits_le32() in the reset method
  net: ftgmac100: add MDIO bus and phylib support
  net: ftgmac100: convert the RX/TX descriptor arrays
  net: ftgmac100: handle timeouts when transmitting
  net: ftgmac100: add clock support
  aspeed: ast2500: fix missing break in D2PLL clock enablement
  net: ftgmac100: Add support for the Aspeed SoC
  aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level
  aspeed: Activate ethernet devices on the ast2500 Eval Board
  aspeed: ast2500: fix D2-PLL clock setting in RGMII mode

 drivers/net/ftgmac100.h  |  158 +--
 include/netdev.h |1 -
 drivers/clk/aspeed/clk_ast2500.c |   39 +
 drivers/net/ftgmac100.c  |  732 +--
 arch/arm/dts/ast2500-evb.dts |   23 +
 arch/arm/dts/ast2500.dtsi| 1949 ++
 configs/evb-ast2500_defconfig|8 +
 drivers/net/Kconfig  |   26 +
 8 files changed, 1707 insertions(+), 1229 deletions(-)

-- 
2.17.2

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Re: [U-Boot] [PATCH v4 07/13] net: ftgmac100: handle timeouts when transmitting

[Cédric Le Goater]

Hello Joe,

On 10/22/18 9:55 PM, Joe Hershberger wrote:
> Hi Cedric,
> 
> On Tue, Oct 16, 2018 at 4:32 AM Cédric Le Goater  wrote:
>>
>> Signed-off-by: Cédric Le Goater 
>> Reviewed-by: Joel Stanley 
>> ---
>>
>>  Changes since v3 :
>>
>>  - introduced a ftgmac100_wait_for_txdone() function similar to the
>>wait_for_bit_*() macros.
>>
>>  drivers/net/ftgmac100.c | 44 +
>>  1 file changed, 44 insertions(+)
>>
>> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
>> index bf8600814690..9adfe109ebc2 100644
>> --- a/drivers/net/ftgmac100.c
>> +++ b/drivers/net/ftgmac100.c
>> @@ -14,6 +14,7 @@
>>  #include 
>>  #include 
>>  #include 
>> +#include 
>>  #include 
>>  #include 
>>
>> @@ -28,6 +29,9 @@
>>  /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
>>  #define PKTBUFSTX  4   /* must be power of 2 */
>>
>> +/* Timeout for transmit */
>> +#define FTGMAC100_TX_TIMEOUT_MS1000
>> +
>>  /* Timeout for a mdio read/write operation */
>>  #define FTGMAC100_MDIO_TIMEOUT_USEC1
>>
>> @@ -401,6 +405,41 @@ static int ftgmac100_recv(struct udevice *dev, int 
>> flags, uchar **packetp)
>> return rxlen;
>>  }
>>
>> +/*
>> + * The wait_for_bit_*() macros require a register value. This define a
>> + * similar routine which loops on the in-memory transmit descriptor to
>> + * wait for the MAC to clear the DMA_OWN bit.
>> + */
>> +static int ftgmac100_wait_for_txdone(struct ftgmac100_txdes *txdes,
>> +const unsigned int timeout_ms,
>> +const bool breakable)
>> +{
> 
> I was hoping to see something like this instead:
> 
> static u32 ftgmac100_read_txdesc(void *desc)
> {
> struct ftgmac100_txdes *txdes = desc;
> ulong des_start = (ulong)txdes;
> ulong des_end = des_start + roundup(sizeof(*txdes), 
> ARCH_DMA_MINALIGN);
> 
> invalidate_dcache_range(des_start, des_end);
> 
> return txdes->txdes0;
> }
> 
> BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
> 
> [ ... ]
> 
> ftgmac100_send( ... )
> {
> [ ... ]
> 
> rc = wait_for_bit_ftgmac100_txdone(curr_des,
> FTGMAC100_TXDES0_TXDMA_OWN, false, FTGMAC100_TX_TIMEOUT_MS, true);
> if (rc)
> return rc;
> 
> [ ... ]
> }


Yes, this is much better. A few other drivers could make use of a similar 
macro.

Sending a v5 with the proposed change.

Thanks,

C. 


>> +   ulong des_start = (ulong)txdes;
>> +   ulong des_end = des_start + roundup(sizeof(*txdes), 
>> ARCH_DMA_MINALIGN);
>> +   ulong start = get_timer(0);
>> +
>> +   while (1) {
>> +   invalidate_dcache_range(des_start, des_end);
>> +
>> +   if (!(txdes->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
>> +   return 0;
>> +
>> +   if (get_timer(start) > timeout_ms)
>> +   break;
>> +
>> +   if (breakable && ctrlc()) {
>> +   puts("Abort\n");
>> +   return -EINTR;
>> +   }
>> +
>> +   udelay(1);
>> +   WATCHDOG_RESET();
>> +   }
>> +
>> +   dev_err(dev, "transmit timeout\n");
>> +   return -ETIMEDOUT;
>> +}
>> +
>>  /*
>>   * Send a data block via Ethernet
>>   */
>> @@ -414,6 +453,7 @@ static int ftgmac100_send(struct udevice *dev, void 
>> *packet, int length)
>> roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> ulong data_start;
>> ulong data_end;
>> +   int rc;
>>
>> invalidate_dcache_range(des_start, des_end);
>>
>> @@ -446,6 +486,10 @@ static int ftgmac100_send(struct udevice *dev, void 
>> *packet, int length)
>> /* Start transmit */
>> writel(1, &ftgmac100->txpd);
>>
>> +   rc = ftgmac100_wait_for_txdone(curr_des, FTGMAC100_TX_TIMEOUT_MS, 
>> true);
>> +   if (rc)
>> +   return rc;
>> +
>> debug("%s(): packet sent\n", __func__);
>>
>> /* Move to next descriptor */
>> --
>> 2.17.2
>>
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[U-Boot] [PATCH] watchdog: aspeed: restore default value of reset_mask

[Cédric Le Goater]

This is required for the current Linux kernel to reboot. It should also
probably be fixed in Linux.

Signed-off-by: Cédric Le Goater 
---
 arch/arm/include/asm/arch-aspeed/wdt.h | 9 +
 drivers/watchdog/ast_wdt.c | 1 +
 2 files changed, 10 insertions(+)

diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h 
b/arch/arm/include/asm/arch-aspeed/wdt.h
index 8d6f292c8495..fb04d41d3cbf 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -57,6 +57,15 @@
 #define WDT_RESET_SPI  (1 << 24)
 #define WDT_RESET_MISC (1 << 25)
 
+#define WDT_RESET_DEFAULT  \
+   (WDT_RESET_ARM | WDT_RESET_COPROC | WDT_RESET_I2C | \
+WDT_RESET_MAC1 | WDT_RESET_MAC2 | WDT_RESET_GCRT | \
+WDT_RESET_USB20 | WDT_RESET_USB11_HOST | WDT_RESET_USB11_EHCI2 | \
+WDT_RESET_VIDEO | WDT_RESET_HAC | WDT_RESET_LPC |  \
+WDT_RESET_SDSDIO | WDT_RESET_MIC | WDT_RESET_CRT2C |   \
+WDT_RESET_PWM | WDT_RESET_PECI | WDT_RESET_JTAG |  \
+WDT_RESET_ADC | WDT_RESET_GPIO | WDT_RESET_MISC)
+
 #ifndef __ASSEMBLY__
 struct ast_wdt {
u32 counter_status;
diff --git a/drivers/watchdog/ast_wdt.c b/drivers/watchdog/ast_wdt.c
index 477605e7222d..59afa21efa4b 100644
--- a/drivers/watchdog/ast_wdt.c
+++ b/drivers/watchdog/ast_wdt.c
@@ -50,6 +50,7 @@ static int ast_wdt_stop(struct udevice *dev)
 
clrbits_le32(&priv->regs->ctrl, WDT_CTRL_EN);
 
+   writel(WDT_RESET_DEFAULT, &priv->regs->reset_mask);
return 0;
 }
 
-- 
2.17.2

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[U-Boot] [PATCH v4 13/13] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode

[Cédric Le Goater]

The algorithm in the ast2500_calc_clock_config() routine suffers from
integer rounding and the requested rate does not get the appropriate
set of Numerator, Denumerator, Post Divider parameters.

This is the case for the D2-PLL clock used by the MAC controllers in
RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.

The easiest way to fix this problem is to introduce an array of clock
settings defining the N, M, P parameters for well known frequencies
used by the Aspeed SoC.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/clk/aspeed/clk_ast2500.c | 38 
 1 file changed, 38 insertions(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 2182320f607f..dbee13a18297 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
 }
 
+struct ast2500_clock_config {
+   ulong input_rate;
+   ulong rate;
+   struct ast2500_div_config cfg;
+};
+
+static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
+   { 2400, 25000, { .num = 124, .denum = 1, .post_div = 5 } },
+};
+
+static bool ast2500_get_clock_config_default(ulong input_rate,
+ulong requested_rate,
+struct ast2500_div_config *cfg)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
+   const struct ast2500_clock_config *default_cfg =
+   &ast2500_clock_config_defaults[i];
+   if (default_cfg->input_rate == input_rate &&
+   default_cfg->rate == requested_rate) {
+   *cfg = default_cfg->cfg;
+   return true;
+   }
+   }
+
+   return false;
+}
+
 /*
  * @input_rate - the rate of input clock in Hz
  * @requested_rate - desired output rate in Hz
@@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rate, 
ulong requested_rate,
ulong delta = rate_khz;
ulong new_rate_khz = 0;
 
+   /*
+* Look for a well known frequency first.
+*/
+   if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
+   return requested_rate;
+
for (; it.denum <= max_vals.denum; ++it.denum) {
for (it.post_div = 0; it.post_div <= max_vals.post_div;
 ++it.post_div) {
@@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu 
*scu, ulong rate)
/*
 * The values and the meaning of the next three
 * parameters are undocumented. Taken from Aspeed SDK.
+*
+* TODO(c...@kaod.org): the SIP and SIC values depend on the
+* Numerator value
 */
const u32 d2_pll_ext_param = 0x2c;
const u32 d2_pll_sip = 0x11;
-- 
2.17.2

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[U-Boot] [PATCH v4 09/13] aspeed: ast2500: fix missing break in D2PLL clock enablement

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Reviewed-by: Simon Glass 
Acked-by: Joe Hershberger 
---
 drivers/clk/aspeed/clk_ast2500.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 526470051c5d..2182320f607f 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -411,6 +411,7 @@ static int ast2500_clk_enable(struct clk *clk)
break;
case PLL_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
+   break;
default:
return -ENOENT;
}
-- 
2.17.2

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[U-Boot] [PATCH v4 12/13] aspeed: Activate ethernet devices on the ast2500 Eval Board

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 arch/arm/dts/ast2500-evb.dts | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 723941ac0bee..ebf44fd707f9 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -11,6 +11,11 @@
chosen {
stdout-path = &uart5;
};
+
+   aliases {
+   ethernet0 = &mac0;
+   ethernet1 = &mac1;
+   };
 };
 
 &uart5 {
@@ -36,3 +41,21 @@
u-boot,dm-pre-reloc;
status = "okay";
 };
+
+&mac0 {
+   status = "okay";
+
+   phy-mode = "rgmii";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>;
+};
+
+&mac1 {
+   status = "okay";
+
+   phy-mode = "rgmii";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
+};
-- 
2.17.2

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[U-Boot] [PATCH v4 08/13] net: ftgmac100: add clock support

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 9adfe109ebc2..e1104a544748 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -11,6 +11,7 @@
  * Copyright (C) 2018, IBM Corporation.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -55,6 +56,7 @@
  * @bus: The mdio bus
  * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  * @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @clks: The bulk of clocks assigned to the device in the DT
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -69,6 +71,8 @@ struct ftgmac100_data {
struct mii_dev *bus;
u32 phy_mode;
u32 max_speed;
+
+   struct clk_bulk clks;
 };
 
 /*
@@ -509,6 +513,7 @@ static int ftgmac100_write_hwaddr(struct udevice *dev)
 static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
+   struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
 
pdata->iobase = devfdt_get_addr(dev);
@@ -523,7 +528,7 @@ static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
 
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
-   return 0;
+   return clk_get_bulk(dev, &priv->clks);
 }
 
 static int ftgmac100_probe(struct udevice *dev)
@@ -537,6 +542,10 @@ static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
 
+   ret = clk_enable_bulk(&priv->clks);
+   if (ret)
+   goto out;
+
ret = ftgmac100_mdio_init(dev);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
@@ -550,6 +559,9 @@ static int ftgmac100_probe(struct udevice *dev)
}
 
 out:
+   if (ret)
+   clk_release_bulk(&priv->clks);
+
return ret;
 }
 
@@ -560,6 +572,7 @@ static int ftgmac100_remove(struct udevice *dev)
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+   clk_release_bulk(&priv->clks);
 
return 0;
 }
-- 
2.17.2

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[U-Boot] [PATCH v4 11/13] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level

[Cédric Le Goater]

This is a large update of the AST2500 SoC DTS file bringing it to the
level of commit 927c2fc2db19 :

Author:  Joel Stanley 
Date:Sat Jun 2 01:18:53 2018 -0700

 ARM: dts: aspeed: Fix hwrng register address

There are some differences on the compatibility property names. scu,
reset and clock drivers are also different.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Reviewed-by: Simon Glass 
---
 arch/arm/dts/ast2500.dtsi | 1949 ++---
 1 file changed, 1153 insertions(+), 796 deletions(-)

diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 7e0ad3a41ac5..98359bf92425 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -11,6 +11,29 @@
#size-cells = <1>;
interrupt-parent = <&vic>;
 
+   aliases {
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   i2c2 = &i2c2;
+   i2c3 = &i2c3;
+   i2c4 = &i2c4;
+   i2c5 = &i2c5;
+   i2c6 = &i2c6;
+   i2c7 = &i2c7;
+   i2c8 = &i2c8;
+   i2c9 = &i2c9;
+   i2c10 = &i2c10;
+   i2c11 = &i2c11;
+   i2c12 = &i2c12;
+   i2c13 = &i2c13;
+   serial0 = &uart1;
+   serial1 = &uart2;
+   serial2 = &uart3;
+   serial3 = &uart4;
+   serial4 = &uart5;
+   serial5 = &vuart;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -22,12 +45,80 @@
};
};
 
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0>;
+   };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
 
+   fmc: flash-controller@1e62 {
+   reg = < 0x1e62 0xc4
+   0x2000 0x1000 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-fmc";
+   status = "disabled";
+   interrupts = <19>;
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@2 {
+   reg = < 2 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   };
+
+   spi1: flash-controller@1e63 {
+   reg = < 0x1e63 0xc4
+   0x3000 0x0800 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-spi";
+   status = "disabled";
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   };
+
+   spi2: flash-controller@1e631000 {
+   reg = < 0x1e631000 0xc4
+   0x3800 0x0800 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-spi";
+   status = "disabled";
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+  

[U-Boot] [PATCH v4 10/13] net: ftgmac100: Add support for the Aspeed SoC

[Cédric Le Goater]

The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c   | 31 +++
 configs/evb-ast2500_defconfig |  8 
 2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index e1104a544748..78abf8b984c0 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -43,6 +43,14 @@
  */
 #define MDC_CYCTHR 0x34
 
+/*
+ * ftgmac100 model variants
+ */
+enum ftgmac100_model {
+   FTGMAC100_MODEL_FARADAY,
+   FTGMAC100_MODEL_ASPEED,
+};
+
 /**
  * struct ftgmac100_data - private data for the FTGMAC100 driver
  *
@@ -57,6 +65,8 @@
  * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  * @max_speed: Maximum speed of Ethernet connection supported by MAC
  * @clks: The bulk of clocks assigned to the device in the DT
+ * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
+ * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -73,6 +83,10 @@ struct ftgmac100_data {
u32 max_speed;
 
struct clk_bulk clks;
+
+   /* End of RX/TX ring buffer bits. Depend on model */
+   u32 rxdes0_edorr_mask;
+   u32 txdes0_edotr_mask;
 };
 
 /*
@@ -293,7 +307,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->txdes[i].txdes3 = 0;
priv->txdes[i].txdes0 = 0;
}
-   priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+   priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
 
start = (ulong)&priv->txdes[0];
end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
@@ -303,7 +317,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
priv->rxdes[i].rxdes0 = 0;
}
-   priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+   priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
 
start = (ulong)&priv->rxdes[0];
end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
@@ -478,7 +492,7 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
flush_dcache_range(data_start, data_end);
 
/* Only one segment on TXBUF */
-   curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
+   curr_des->txdes0 &= priv->txdes0_edotr_mask;
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
FTGMAC100_TXDES0_LTS |
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
@@ -528,6 +542,14 @@ static int ftgmac100_ofdata_to_platdata(struct udevice 
*dev)
 
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
+   if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
+   priv->rxdes0_edorr_mask = BIT(30);
+   priv->txdes0_edotr_mask = BIT(30);
+   } else {
+   priv->rxdes0_edorr_mask = BIT(15);
+   priv->txdes0_edotr_mask = BIT(15);
+   }
+
return clk_get_bulk(dev, &priv->clks);
 }
 
@@ -587,7 +609,8 @@ static const struct eth_ops ftgmac100_ops = {
 };
 
 static const struct udevice_id ftgmac100_ids[] = {
-   { .compatible = "faraday,ftgmac100" },
+   { .compatible = "faraday,ftgmac100",  .data = FTGMAC100_MODEL_FARADAY },
+   { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED  },
{ }
 };
 
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 88230f4a12db..32581f5ada54 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -25,3 +25,11 @@ CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER=y
 CONFIG_WDT=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_FTGMAC100=y
+CONFIG_PHY_REALTEK=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
-- 
2.17.2

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[U-Boot] [PATCH v4 07/13] net: ftgmac100: handle timeouts when transmitting

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
---

 Changes since v3 :

 - introduced a ftgmac100_wait_for_txdone() function similar to the
   wait_for_bit_*() macros.

 drivers/net/ftgmac100.c | 44 +
 1 file changed, 44 insertions(+)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index bf8600814690..9adfe109ebc2 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -28,6 +29,9 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/* Timeout for transmit */
+#define FTGMAC100_TX_TIMEOUT_MS1000
+
 /* Timeout for a mdio read/write operation */
 #define FTGMAC100_MDIO_TIMEOUT_USEC1
 
@@ -401,6 +405,41 @@ static int ftgmac100_recv(struct udevice *dev, int flags, 
uchar **packetp)
return rxlen;
 }
 
+/*
+ * The wait_for_bit_*() macros require a register value. This define a
+ * similar routine which loops on the in-memory transmit descriptor to
+ * wait for the MAC to clear the DMA_OWN bit.
+ */
+static int ftgmac100_wait_for_txdone(struct ftgmac100_txdes *txdes,
+const unsigned int timeout_ms,
+const bool breakable)
+{
+   ulong des_start = (ulong)txdes;
+   ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
+   ulong start = get_timer(0);
+
+   while (1) {
+   invalidate_dcache_range(des_start, des_end);
+
+   if (!(txdes->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
+   return 0;
+
+   if (get_timer(start) > timeout_ms)
+   break;
+
+   if (breakable && ctrlc()) {
+   puts("Abort\n");
+   return -EINTR;
+   }
+
+   udelay(1);
+   WATCHDOG_RESET();
+   }
+
+   dev_err(dev, "transmit timeout\n");
+   return -ETIMEDOUT;
+}
+
 /*
  * Send a data block via Ethernet
  */
@@ -414,6 +453,7 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
ulong data_start;
ulong data_end;
+   int rc;
 
invalidate_dcache_range(des_start, des_end);
 
@@ -446,6 +486,10 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
/* Start transmit */
writel(1, &ftgmac100->txpd);
 
+   rc = ftgmac100_wait_for_txdone(curr_des, FTGMAC100_TX_TIMEOUT_MS, true);
+   if (rc)
+   return rc;
+
debug("%s(): packet sent\n", __func__);
 
/* Move to next descriptor */
-- 
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[U-Boot] [PATCH v4 06/13] net: ftgmac100: convert the RX/TX descriptor arrays

[Cédric Le Goater]

Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c | 141 ++--
 1 file changed, 64 insertions(+), 77 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index b6e6f6e5ec02..bf8600814690 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -13,19 +13,17 @@
 
 #include 
 #include 
-#include 
 #include 
 #include 
-#include 
 #include 
 
 #include "ftgmac100.h"
 
-#define ETH_ZLEN   60
-#define CFG_XBUF_SIZE  1536
+/* Min frame ethernet frame size without FCS */
+#define ETH_ZLEN   60
 
-/* RBSR - hw default init value is also 0x640 */
-#define RBSR_DEFAULT_VALUE 0x640
+/* Receive Buffer Size Register - HW default is 0x640 */
+#define FTGMAC100_RBSR_DEFAULT 0x640
 
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
@@ -57,10 +55,8 @@
 struct ftgmac100_data {
struct ftgmac100 *iobase;
 
-   ulong txdes_dma;
-   struct ftgmac100_txdes *txdes;
-   ulong rxdes_dma;
-   struct ftgmac100_rxdes *rxdes;
+   struct ftgmac100_txdes txdes[PKTBUFSTX];
+   struct ftgmac100_rxdes rxdes[PKTBUFSRX];
int tx_index;
int rx_index;
 
@@ -266,10 +262,8 @@ static int ftgmac100_start(struct udevice *dev)
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct phy_device *phydev = priv->phydev;
-   struct ftgmac100_txdes *txdes;
-   struct ftgmac100_rxdes *rxdes;
unsigned int maccr;
-   void *buf;
+   ulong start, end;
int ret;
int i;
 
@@ -277,26 +271,6 @@ static int ftgmac100_start(struct udevice *dev)
 
ftgmac100_reset(priv);
 
-   if (!priv->txdes) {
-   txdes = dma_alloc_coherent(
-   sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
-   if (!txdes)
-   panic("ftgmac100: out of memory\n");
-   memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
-   priv->txdes = txdes;
-   }
-   txdes = priv->txdes;
-
-   if (!priv->rxdes) {
-   rxdes = dma_alloc_coherent(
-   sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
-   if (!rxdes)
-   panic("ftgmac100: out of memory\n");
-   memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
-   priv->rxdes = rxdes;
-   }
-   rxdes = priv->rxdes;
-
/* set the ethernet address */
ftgmac100_set_mac(priv, plat->enetaddr);
 
@@ -307,42 +281,37 @@ static int ftgmac100_start(struct udevice *dev)
priv->tx_index = 0;
priv->rx_index = 0;
 
-   txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
-   rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
-
for (i = 0; i < PKTBUFSTX; i++) {
-   /* TXBUF_BADR */
-   if (!txdes[i].txdes2) {
-   buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
-   if (!buf)
-   panic("ftgmac100: out of memory\n");
-   txdes[i].txdes3 = virt_to_phys(buf);
-   txdes[i].txdes2 = (uint)buf;
-   }
-   txdes[i].txdes1 = 0;
+   priv->txdes[i].txdes3 = 0;
+   priv->txdes[i].txdes0 = 0;
}
+   priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+
+   start = (ulong)&priv->txdes[0];
+   end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
+   flush_dcache_range(start, end);
 
for (i = 0; i < PKTBUFSRX; i++) {
-   /* RXBUF_BADR */
-   if (!rxdes[i].rxdes2) {
-   buf = net_rx_packets[i];
-   rxdes[i].rxdes3 = virt_to_phys(buf);
-   rxdes[i].rxdes2 = (uint)buf;
-   }
-   rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+   priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+   priv->rxdes[i].rxdes0 = 0;
}
+   priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+
+   start = (ulong)&priv->rxdes[0];
+   end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
+   flush_dcache_range(start, end);
 
/* transmit ring */
-   writel(priv->txdes_dma, &ftgmac100->txr_badr);
+   writel((u32)priv->txdes, &ftgmac100->txr_badr);
 
/* receive ring */
-   writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
+   writel((u32)priv->

[U-Boot] [PATCH v4 03/13] net: ftgmac100: convert to driver model

[Cédric Le Goater]

The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
---

 It didn't seem necessary to remove the 'dev' argument from the
 ftgmac100_phy_init() and ftgmac100_phy_reset() function prototypes as
 the code is completely reworked in patch 5.

 include/netdev.h|   1 -
 drivers/net/ftgmac100.c | 223 +++-
 drivers/net/Kconfig |  26 +
 3 files changed, 157 insertions(+), 93 deletions(-)

diff --git a/include/netdev.h b/include/netdev.h
index 55001625fb92..0a1a3a2d8da2 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
 int fec_initialize (bd_t *bis);
 int fecmxc_initialize(bd_t *bis);
 int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
-int ftgmac100_initialize(bd_t *bits);
 int ftmac100_initialize(bd_t *bits);
 int ftmac110_initialize(bd_t *bits);
 void gt6426x_eth_initialize(bd_t *bis);
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index c996f5f4a167..67a7c73503c5 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -7,15 +7,16 @@
  *
  * (C) Copyright 2010 Andes Technology
  * Macpaul Lin 
+ *
+ * Copyright (C) 2018, IBM Corporation.
  */
 
-#include 
-#include 
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
-#include 
 
 #include "ftgmac100.h"
 
@@ -28,7 +29,19 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/**
+ * struct ftgmac100_data - private data for the FTGMAC100 driver
+ *
+ * @iobase: The base address of the hardware registers
+ * @txdes: The array of transmit descriptors
+ * @rxdes: The array of receive descriptors
+ * @tx_index: Transmit descriptor index in @txdes
+ * @rx_index: Receive descriptor index in @rxdes
+ * @phy_addr: The PHY interface address to use
+ */
 struct ftgmac100_data {
+   struct ftgmac100 *iobase;
+
ulong txdes_dma;
struct ftgmac100_txdes *txdes;
ulong rxdes_dma;
@@ -41,10 +54,10 @@ struct ftgmac100_data {
 /*
  * struct mii_bus functions
  */
-static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
-   int regnum)
+static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr,
+ int regnum)
 {
-   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+   struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int i;
 
@@ -76,10 +89,10 @@ static int ftgmac100_mdiobus_read(struct eth_device *dev, 
int phy_addr,
return -1;
 }
 
-static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
-   int regnum, u16 value)
+static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int phy_addr,
+  int regnum, u16 value)
 {
-   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+   struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int data;
int i;
@@ -114,9 +127,10 @@ static int ftgmac100_mdiobus_write(struct eth_device *dev, 
int phy_addr,
return -1;
 }
 
-int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
+int ftgmac100_phy_read(struct ftgmac100_data *priv, int addr, int reg,
+  u16 *value)
 {
-   *value = ftgmac100_mdiobus_read(dev , addr, reg);
+   *value = ftgmac100_mdiobus_read(priv, addr, reg);
 
if (*value == -1)
return -1;
@@ -124,31 +138,31 @@ int ftgmac100_phy_read(struct eth_device *dev, int addr, 
int reg, u16 *value)
return 0;
 }
 
-int  ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
+int ftgmac100_phy_write(struct ftgmac100_data *priv, int addr, int reg,
+   u16 value)
 {
-   if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
+   if (ftgmac100_mdiobus_write(priv, addr, reg, value) == -1)
return -1;
 
return 0;
 }
 
-static int ftgmac100_phy_reset(struct eth_device *dev)
+static int ftgmac100_phy_reset(struct ftgmac100_data *priv, struct udevice 
*dev)
 {
-   struct ftgmac100_data *priv = dev->priv;
int i;
u16 status, adv;
 
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
 
-   ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
+   ftgmac100_phy_write(priv, priv->phy_addr, MII_ADVERTISE, adv);
 
printf("%s: Starting autonegotiation...\n", dev->name);
 
-   ftgmac100_phy_write(dev, priv->phy_addr,
-   MII_BMCR, (BMCR_ANENABLE | BMCR

[U-Boot] [PATCH v4 05/13] net: ftgmac100: add MDIO bus and phylib support

[Cédric Le Goater]

Implement the MDIO bus read/write functions using the readl_poll_timeout()
routine, initialize the bus and scan for the PHY. RGMII and RMII mode
are supported.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---

 Changes since v3 :

 - improved ftgmac100_mdio_init() and ftgmac100_phy_init() prototypes

 drivers/net/ftgmac100.c | 380 +---
 1 file changed, 160 insertions(+), 220 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 78cd9df62986..b6e6f6e5ec02 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -17,6 +17,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ftgmac100.h"
 
@@ -29,6 +30,16 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/* Timeout for a mdio read/write operation */
+#define FTGMAC100_MDIO_TIMEOUT_USEC1
+
+/*
+ * MDC clock cycle threshold
+ *
+ * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
+ */
+#define MDC_CYCTHR 0x34
+
 /**
  * struct ftgmac100_data - private data for the FTGMAC100 driver
  *
@@ -38,6 +49,10 @@
  * @tx_index: Transmit descriptor index in @txdes
  * @rx_index: Receive descriptor index in @rxdes
  * @phy_addr: The PHY interface address to use
+ * @phydev: The PHY device backing the MAC
+ * @bus: The mdio bus
+ * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
+ * @max_speed: Maximum speed of Ethernet connection supported by MAC
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -48,234 +63,110 @@ struct ftgmac100_data {
struct ftgmac100_rxdes *rxdes;
int tx_index;
int rx_index;
-   int phy_addr;
+
+   u32 phy_addr;
+   struct phy_device *phydev;
+   struct mii_dev *bus;
+   u32 phy_mode;
+   u32 max_speed;
 };
 
 /*
  * struct mii_bus functions
  */
-static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr,
- int regnum)
+static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+  int reg_addr)
 {
+   struct ftgmac100_data *priv = bus->priv;
struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
-   int i;
-
-   phycr = readl(&ftgmac100->phycr);
-
-   /* preserve MDC cycle threshold */
-   phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
-   phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- |  FTGMAC100_PHYCR_REGAD(regnum)
- |  FTGMAC100_PHYCR_MIIRD;
+   int data;
+   int ret;
 
+   phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+   FTGMAC100_PHYCR_PHYAD(phy_addr) |
+   FTGMAC100_PHYCR_REGAD(reg_addr) |
+   FTGMAC100_PHYCR_MIIRD;
writel(phycr, &ftgmac100->phycr);
 
-   for (i = 0; i < 10; i++) {
-   phycr = readl(&ftgmac100->phycr);
-
-   if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
-   int data;
-
-   data = readl(&ftgmac100->phydata);
-   return FTGMAC100_PHYDATA_MIIRDATA(data);
-   }
-
-   mdelay(10);
+   ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
+!(phycr & FTGMAC100_PHYCR_MIIRD),
+FTGMAC100_MDIO_TIMEOUT_USEC);
+   if (ret) {
+   pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
+  priv->phydev->dev->name, phy_addr, reg_addr);
+   return ret;
}
 
-   debug("mdio read timed out\n");
-   return -1;
+   data = readl(&ftgmac100->phydata);
+
+   return FTGMAC100_PHYDATA_MIIRDATA(data);
 }
 
-static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int phy_addr,
-  int regnum, u16 value)
+static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int 
dev_addr,
+   int reg_addr, u16 value)
 {
+   struct ftgmac100_data *priv = bus->priv;
struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int data;
-   int i;
-
-   phycr = readl(&ftgmac100->phycr);
-
-   /* preserve MDC cycle threshold */
-   phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
-
-   phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr)
- |  FTGMAC100_PHYCR_REGAD(regnum)
- |  FTGMAC100_PHYCR_MIIWR;
+   int ret;
 
+   phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
+   FTGMAC100_PHYCR_PHYAD(phy_addr) |
+   FTGMAC100_PHYCR_REGAD(reg_addr) |
+   FTGMAC100_PHYCR_MIIWR;
data = FTGMAC100_PHYDATA_MIIWDATA(value);
 
writel(data, &ftgmac100->phydata);
writel(phycr, &ftgmac100->phycr);
 
-   for (i = 0; i < 10; i++) {
- 

[U-Boot] [PATCH v4 04/13] net: ftgmac100: use setbits_le32() in the reset method

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 67a7c73503c5..78cd9df62986 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -331,7 +331,7 @@ static void ftgmac100_reset(struct ftgmac100_data *priv)
 
debug("%s()\n", __func__);
 
-   writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
+   setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
 
while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
;
-- 
2.17.2

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[U-Boot] [PATCH v4 02/13] net: ftgmac100: use the aligned() macro

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index 439b14d71e4b..9a789e4d5bee 100644
--- a/drivers/net/ftgmac100.h
+++ b/drivers/net/ftgmac100.h
@@ -182,7 +182,7 @@ struct ftgmac100_txdes {
unsigned inttxdes1;
unsigned inttxdes2; /* not used by HW */
unsigned inttxdes3; /* TXBUF_BADR */
-} __attribute__ ((aligned(16)));
+} __aligned(16);
 
 #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff)
 #define FTGMAC100_TXDES0_EDOTR BIT(15)
@@ -208,7 +208,7 @@ struct ftgmac100_rxdes {
unsigned intrxdes1;
unsigned intrxdes2; /* not used by HW */
unsigned intrxdes3; /* RXBUF_BADR */
-} __attribute__ ((aligned(16)));
+} __aligned(16);
 
 #define FTGMAC100_RXDES0_VDBC(x)   ((x) & 0x3fff)
 #define FTGMAC100_RXDES0_EDORR BIT(15)
-- 
2.17.2

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[U-Boot] [PATCH v4 01/13] net: ftgmac100: use the BIT() macro

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Acked-by: Joe Hershberger 
---
 drivers/net/ftgmac100.h | 154 
 1 file changed, 77 insertions(+), 77 deletions(-)

diff --git a/drivers/net/ftgmac100.h b/drivers/net/ftgmac100.h
index ffbe1f3e3fa7..439b14d71e4b 100644
--- a/drivers/net/ftgmac100.h
+++ b/drivers/net/ftgmac100.h
@@ -70,48 +70,48 @@ struct ftgmac100 {
 /*
  * Interrupt status register & interrupt enable register
  */
-#define FTGMAC100_INT_RPKT_BUF (1 << 0)
-#define FTGMAC100_INT_RPKT_FIFO(1 << 1)
-#define FTGMAC100_INT_NO_RXBUF (1 << 2)
-#define FTGMAC100_INT_RPKT_LOST(1 << 3)
-#define FTGMAC100_INT_XPKT_ETH (1 << 4)
-#define FTGMAC100_INT_XPKT_FIFO(1 << 5)
-#define FTGMAC100_INT_NO_NPTXBUF   (1 << 6)
-#define FTGMAC100_INT_XPKT_LOST(1 << 7)
-#define FTGMAC100_INT_AHB_ERR  (1 << 8)
-#define FTGMAC100_INT_PHYSTS_CHG   (1 << 9)
-#define FTGMAC100_INT_NO_HPTXBUF   (1 << 10)
+#define FTGMAC100_INT_RPKT_BUF BIT(0)
+#define FTGMAC100_INT_RPKT_FIFOBIT(1)
+#define FTGMAC100_INT_NO_RXBUF BIT(2)
+#define FTGMAC100_INT_RPKT_LOSTBIT(3)
+#define FTGMAC100_INT_XPKT_ETH BIT(4)
+#define FTGMAC100_INT_XPKT_FIFOBIT(5)
+#define FTGMAC100_INT_NO_NPTXBUF   BIT(6)
+#define FTGMAC100_INT_XPKT_LOSTBIT(7)
+#define FTGMAC100_INT_AHB_ERR  BIT(8)
+#define FTGMAC100_INT_PHYSTS_CHG   BIT(9)
+#define FTGMAC100_INT_NO_HPTXBUF   BIT(10)
 
 /*
  * Interrupt timer control register
  */
 #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0)
 #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4)
-#define FTGMAC100_ITC_RXINT_TIME_SEL   (1 << 7)
+#define FTGMAC100_ITC_RXINT_TIME_SEL   BIT(7)
 #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8)
 #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12)
-#define FTGMAC100_ITC_TXINT_TIME_SEL   (1 << 15)
+#define FTGMAC100_ITC_TXINT_TIME_SEL   BIT(15)
 
 /*
  * Automatic polling timer control register
  */
 #define FTGMAC100_APTC_RXPOLL_CNT(x)   (((x) & 0xf) << 0)
-#define FTGMAC100_APTC_RXPOLL_TIME_SEL (1 << 4)
+#define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4)
 #define FTGMAC100_APTC_TXPOLL_CNT(x)   (((x) & 0xf) << 8)
-#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
+#define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12)
 
 /*
  * DMA burst length and arbitration control register
  */
 #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0)
 #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3)
-#define FTGMAC100_DBLAC_RX_THR_EN  (1 << 6)
+#define FTGMAC100_DBLAC_RX_THR_EN  BIT(6)
 #define FTGMAC100_DBLAC_RXBURST_SIZE(x)(((x) & 0x3) << 8)
 #define FTGMAC100_DBLAC_TXBURST_SIZE(x)(((x) & 0x3) << 10)
 #define FTGMAC100_DBLAC_RXDES_SIZE(x)  (((x) & 0xf) << 12)
 #define FTGMAC100_DBLAC_TXDES_SIZE(x)  (((x) & 0xf) << 16)
 #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20)
-#define FTGMAC100_DBLAC_IFG_INC(1 << 23)
+#define FTGMAC100_DBLAC_IFG_INCBIT(23)
 
 /*
  * DMA FIFO status register
@@ -122,12 +122,12 @@ struct ftgmac100 {
 #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf)
 #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3)
 #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf)
-#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY(1 << 26)
-#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY(1 << 27)
-#define FTGMAC100_DMAFIFOS_RXDMA_GRANT (1 << 28)
-#define FTGMAC100_DMAFIFOS_TXDMA_GRANT (1 << 29)
-#define FTGMAC100_DMAFIFOS_RXDMA_REQ   (1 << 30)
-#define FTGMAC100_DMAFIFOS_TXDMA_REQ   (1 << 31)
+#define FTGMAC100_DMAFIFOS_RXFIFO_EMPTYBIT(26)
+#define FTGMAC100_DMAFIFOS_TXFIFO_EMPTYBIT(27)
+#define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28)
+#define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29)
+#define FTGMAC100_DMAFIFOS_RXDMA_REQ   BIT(30)
+#define FTGMAC100_DMAFIFOS_TXDMA_REQ   BIT(31)
 
 /*
  * Receive buffer size register
@@ -137,26 +137,26 @@ struct ftgmac100 {
 /*
  * MAC control register
  */
-#define FTGMAC100_MACCR_TXDMA_EN   (1 << 0)
-#define FTGMAC100_MACCR_RXDMA_EN   (1 << 1)
-#define FTGMAC100_MACCR_TXMAC_EN   (1 << 2)
-#define FTGMAC100_MACCR_RXMAC_EN   (1 << 3)
-#define FTGMAC100_MACCR_RM_VLAN(1 << 4)
-#define FTGMAC100_MACCR_HPTXR_EN   (1 << 5)
-#define FTGMAC100_MACCR_LOOP_EN

[U-Boot] [PATCH v4 00/13] Support for the Faraday ftgmac100 controller

[Cédric Le Goater]

Hello,

This series re-enables the Faraday ftgmac100 controller driver and its
Aspeed variant as as one can find on the OpenPOWER platforms. The
driver is largely reworked to support the driver model and also adds
the MDIO bus and phylib support. It was tested on the AST2500 evb.

Git tree available here:

  https://github.com/legoater/u-boot/commits/aspeed

Thanks,

C.

Changes since v3 :

 It didn't seem necessary to remove the 'dev' argument from the
 ftgmac100_phy_init() and ftgmac100_phy_reset() function prototypes as
 the code is completely reworked in patch 5.

 - improved ftgmac100_mdio_init() and ftgmac100_phy_init() prototypes
 - introduced a ftgmac100_wait_for_txdone() function similar to the
   wait_for_bit_*() macros.

Changes since v2 :

 - split changes in multiple patches to preserve git history, but the
   code has not changed since the reviewed v2 patchset.
 - included a couple more changes to sync the DTS file with Linux.

Changes since v1 :

 - improved comments in the code
 - changed the type of 'iobase' to 'struct ftgmac100 *' to remove the
   casts in other routines.
 - replaced the loop in the mdio methods by a call to readl_poll_timeout()
   and fixed the returned value.
 - added a flush cache on the arrays of TX and RX descriptors in
   ftgmac100_start()
 - fixed returned value of 
 - added a timer loop to catch transmit timeouts
 - introduced a clk_bulk
 - improved Kconfig description
 - introduced a udevice_id .data model
 - dropped is_aspeed bool
 - dropped MDIO interface setting for Aspeed SoC. The default is
   correct.
 - removed the clcoks which are now handled automatically in the
   ftgmac100 driver
 - introduced a fix for the D2-PLL clock setting

Cédric Le Goater (13):
  net: ftgmac100: use the BIT() macro
  net: ftgmac100: use the aligned() macro
  net: ftgmac100: convert to driver model
  net: ftgmac100: use setbits_le32() in the reset method
  net: ftgmac100: add MDIO bus and phylib support
  net: ftgmac100: convert the RX/TX descriptor arrays
  net: ftgmac100: handle timeouts when transmitting
  net: ftgmac100: add clock support
  aspeed: ast2500: fix missing break in D2PLL clock enablement
  net: ftgmac100: Add support for the Aspeed SoC
  aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level
  aspeed: Activate ethernet devices on the ast2500 Eval Board
  aspeed: ast2500: fix D2-PLL clock setting in RGMII mode

 drivers/net/ftgmac100.h  |  158 +--
 include/netdev.h |1 -
 drivers/clk/aspeed/clk_ast2500.c |   39 +
 drivers/net/ftgmac100.c  |  752 ++--
 arch/arm/dts/ast2500-evb.dts |   23 +
 arch/arm/dts/ast2500.dtsi| 1949 ++
 configs/evb-ast2500_defconfig|8 +
 drivers/net/Kconfig  |   26 +
 8 files changed, 1727 insertions(+), 1229 deletions(-)

-- 
2.17.2

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Re: [U-Boot] [PATCH v3 07/13] net: ftgmac100: handle timeouts when transmitting

[Cédric Le Goater]

On 10/15/18 10:58 PM, Joe Hershberger wrote:
> On Wed, Oct 10, 2018 at 6:48 AM Cédric Le Goater  wrote:
>>
>> Signed-off-by: Cédric Le Goater 
>> ---
>>  drivers/net/ftgmac100.c | 18 ++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
>> index b46187b567c6..edf34c601c68 100644
>> --- a/drivers/net/ftgmac100.c
>> +++ b/drivers/net/ftgmac100.c
>> @@ -28,6 +28,9 @@
>>  /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
>>  #define PKTBUFSTX  4   /* must be power of 2 */
>>
>> +/* Timeout for transmit */
>> +#define FTGMAC100_TX_TIMEOUT_MS1000
>> +
>>  /* Timeout for a mdio read/write operation */
>>  #define FTGMAC100_MDIO_TIMEOUT_USEC1
>>
>> @@ -412,6 +415,7 @@ static int ftgmac100_send(struct udevice *dev, void 
>> *packet, int length)
>> roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
>> ulong data_start;
>> ulong data_end;
>> +   ulong start;
>>
>> invalidate_dcache_range(des_start, des_end);
>>
>> @@ -444,6 +448,20 @@ static int ftgmac100_send(struct udevice *dev, void 
>> *packet, int length)
>> /* Start transmit */
>> writel(1, &ftgmac100->txpd);
>>
>> +   /* Wait until packet is transmitted */
>> +   start = get_timer(0);
>> +   while (get_timer(start) < FTGMAC100_TX_TIMEOUT_MS) {
> 
> In general we prefer to use wait_bit.h for such things. Probably just
> define a BUILD_WAIT_FOR_BIT() in your .c to handle your memory access.

OK. I will take a look for v4. 

Thanks for the review.

C.


> 
>> +   invalidate_dcache_range(des_start, des_end);
>> +   if (!(curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
>> +   break;
>> +   udelay(10);
>> +   }
>> +
>> +   if (get_timer(start) >= FTGMAC100_TX_TIMEOUT_MS) {
>> +   dev_err(dev, "transmit timeout\n");
>> +   return -ETIMEDOUT;
>> +   }
>> +
>> debug("%s(): packet sent\n", __func__);
>>
>> /* Move to next descriptor */
>> --
>> 2.17.1
>>
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Re: [U-Boot] [PATCH v3 03/13] net: ftgmac100: convert to driver model

[Cédric Le Goater]

On 10/15/18 10:39 PM, Joe Hershberger wrote:
> On Wed, Oct 10, 2018 at 6:45 AM Cédric Le Goater  wrote:
>>
>> The driver is based on the previous one and the code is only adapted
>> to fit the driver model. The support for the Faraday ftgmac100
>> controller is the same with MAC and MDIO bus support for RGMII/RMII
>> modes.
>>
>> Configuration is updated to enable compile again. At this stage, the
>> driver compiles but is not yet functional.
>>
>> Signed-off-by: Cédric Le Goater 
>> ---
>>  include/netdev.h|   1 -
>>  drivers/net/ftgmac100.c | 223 +++-
>>  drivers/net/Kconfig |  26 +
>>  3 files changed, 157 insertions(+), 93 deletions(-)
>>
>> diff --git a/include/netdev.h b/include/netdev.h
>> index 55001625fb92..0a1a3a2d8da2 100644
>> --- a/include/netdev.h
>> +++ b/include/netdev.h
>> @@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
>>  int fec_initialize (bd_t *bis);
>>  int fecmxc_initialize(bd_t *bis);
>>  int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t 
>> addr);
>> -int ftgmac100_initialize(bd_t *bits);
>>  int ftmac100_initialize(bd_t *bits);
>>  int ftmac110_initialize(bd_t *bits);
>>  void gt6426x_eth_initialize(bd_t *bis);
>> diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
>> index c996f5f4a167..67a7c73503c5 100644
>> --- a/drivers/net/ftgmac100.c
>> +++ b/drivers/net/ftgmac100.c
>> @@ -7,15 +7,16 @@
>>   *
>>   * (C) Copyright 2010 Andes Technology
>>   * Macpaul Lin 
>> + *
>> + * Copyright (C) 2018, IBM Corporation.
>>   */
>>
>> -#include 
>> -#include 
>> +#include 
>> +#include 
>>  #include 
>>  #include 
>> -#include 
>> +#include 
>>  #include 
>> -#include 
>>
>>  #include "ftgmac100.h"
>>
>> @@ -28,7 +29,19 @@
>>  /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
>>  #define PKTBUFSTX  4   /* must be power of 2 */
>>
>> +/**
>> + * struct ftgmac100_data - private data for the FTGMAC100 driver
>> + *
>> + * @iobase: The base address of the hardware registers
>> + * @txdes: The array of transmit descriptors
>> + * @rxdes: The array of receive descriptors
>> + * @tx_index: Transmit descriptor index in @txdes
>> + * @rx_index: Receive descriptor index in @rxdes
>> + * @phy_addr: The PHY interface address to use
>> + */
>>  struct ftgmac100_data {
>> +   struct ftgmac100 *iobase;
>> +
>> ulong txdes_dma;
>> struct ftgmac100_txdes *txdes;
>> ulong rxdes_dma;
>> @@ -41,10 +54,10 @@ struct ftgmac100_data {
>>  /*
>>   * struct mii_bus functions
>>   */
>> -static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
>> -   int regnum)
>> +static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr,
>> + int regnum)
>>  {
>> -   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> +   struct ftgmac100 *ftgmac100 = priv->iobase;
>> int phycr;
>> int i;
>>
>> @@ -76,10 +89,10 @@ static int ftgmac100_mdiobus_read(struct eth_device 
>> *dev, int phy_addr,
>> return -1;
>>  }
>>
>> -static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
>> -   int regnum, u16 value)
>> +static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int 
>> phy_addr,
>> +  int regnum, u16 value)
>>  {
>> -   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
>> +   struct ftgmac100 *ftgmac100 = priv->iobase;
>> int phycr;
>> int data;
>> int i;
>> @@ -114,9 +127,10 @@ static int ftgmac100_mdiobus_write(struct eth_device 
>> *dev, int phy_addr,
>> return -1;
>>  }
>>
>> -int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 
>> *value)
>> +int ftgmac100_phy_read(struct ftgmac100_data *priv, int addr, int reg,
>> +  u16 *value)
>>  {
>> -   *value = ftgmac100_mdiobus_read(dev , addr, reg);
>> +   *value = ftgmac100_mdiobus_read(priv, addr, reg);
>>
>> if (*value == -1)
>> return -1;
>> @@ -124,31 +138,31 @@ int ftgmac100_phy_read(struct eth_device *dev, int 
>> addr, int reg, u16 *value)
>> return 0;
>>  }
>>
>> -int  ftgm

Re: [U-Boot] [PATCH v3 03/13] net: ftgmac100: convert to driver model

[Cédric Le Goater]

On 10/12/18 1:15 AM, Joel Stanley wrote:
> On Wed, 10 Oct 2018 at 22:12, Cédric Le Goater  wrote:
>>
>> The driver is based on the previous one and the code is only adapted
>> to fit the driver model. The support for the Faraday ftgmac100
>> controller is the same with MAC and MDIO bus support for RGMII/RMII
>> modes.
>>
>> Configuration is updated to enable compile again. At this stage, the
>> driver compiles but is not yet functional.
> 
> Is this commit message still valid?

yes. The driver compiles but does not work. That is what I meant. 


>>
>> Signed-off-by: Cédric Le Goater 
> 
> The code looks good.
> 
> Reviewed-by: Joel Stanley 
> 

Thanks,

C.
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Re: [U-Boot] [PATCH 2/3] spi: Add support for the Aspeed ast2500 SPI controllers

[Cédric Le Goater]

Hello Boris,

On 10/10/18 9:32 AM, Boris Brezillon wrote:
> Hi Cédric,
> 
> On Wed, 10 Oct 2018 11:46:56 +0530
> Jagan Teki  wrote:
> 
>> On Mon, Oct 8, 2018 at 11:32 AM Cédric Le Goater  wrote:
>>>
>>> On 10/4/18 5:57 PM, Jagan Teki wrote:  
>>>> On Fri, Sep 28, 2018 at 5:20 PM Cédric Le Goater  wrote:  
>>>>>
>>>>> Hello Simon,
>>>>>
>>>>>
>>>>> The Aspeed AST2500 FMC controller can handle SPI flash and NOR flash 
>>>>> memory,
>>>>> and the Aspeed AST2500 SPI Flash Controllers only SPI. If there is some
>>>>> misunderstanding on this driver, it might come from the fact it is closer
>>>>> to a SPI-NOR driver like we have in Linux, than a generic SPI driver.
>>>>> The stm32 SPI driver is somewhat similar.
>>>>>
>>>>> Should we move it under drivers/mtd/spi/ maybe ?  
>>>>
>>>> Seems with new spi-mem in Linux flash memory driver rely on spi-mem
>>>> instead of mtd/spi-nor. So I think you can handle this via new
>>>> spi-mem. have you send any patches to Linux?  
>>>
>>> No, not yet. The patchset is sent  :
>>>
>>> https://patchwork.ozlabs.org/cover/933293/
>>>
>>> is not using spimem. I was not aware of that change in the spi-nor layer
>>> at the time. I will take a look.  
> 
> Indeed, if you have some time to convert the Linux aspeed driver to
> the spi-mem interface that would be appreciated.

Yes. That's the plan. I have a series on the way but I will see if I can
rework a v2 to use spi-mem. 

Same for the u-boot aspeed spi driver which needs a spi-mem refresh if 
I understand correctly. 

Thanks,

C.

 
>>
>> Yes, but for newly added drivers. added spi-mem guys, may be they can 
>> comment.
> 
> Jagan, what's the plan for the spi-nor layer in u-boot? I mean, spi-mem
> is just the controller side of things, but it requires spi-mem drivers
> to support specific SPI memories. We added the spi-nand driver, but
> AFAICT, the spi-nor driver does not exist yet. There's the spi-flash
> layer already, but IIUC you were trying to replace it by a spi-nor
> framework.
> 
> I see 2 options here:
> 
> 1/ copy the spi-nor framework from linux and adjust it to make it work
>in uboot
> 2/ create a spi-nor driver which interfaces directly with the spi-mem
>layer
> 
> I know I usually recommend going for #1, but it might be a bit
> different this time around since I'm trying to get rid of the
> spi_nor interface in Linux (the one that allows people to implement
> spi-nor controller drivers) in favor of a native spi-mem driver. So
> I think it's worth considering option #2.
> 

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[U-Boot] [PATCH v3 12/13] aspeed: Activate ethernet devices on the ast2500 Eval Board

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
---
 arch/arm/dts/ast2500-evb.dts | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 723941ac0bee..ebf44fd707f9 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -11,6 +11,11 @@
chosen {
stdout-path = &uart5;
};
+
+   aliases {
+   ethernet0 = &mac0;
+   ethernet1 = &mac1;
+   };
 };
 
 &uart5 {
@@ -36,3 +41,21 @@
u-boot,dm-pre-reloc;
status = "okay";
 };
+
+&mac0 {
+   status = "okay";
+
+   phy-mode = "rgmii";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_mac1link_default &pinctrl_mdio1_default>;
+};
+
+&mac1 {
+   status = "okay";
+
+   phy-mode = "rgmii";
+
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_mac2link_default &pinctrl_mdio2_default>;
+};
-- 
2.17.1

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[U-Boot] [PATCH v3 10/13] net: ftgmac100: Add support for the Aspeed SoC

[Cédric Le Goater]

The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have
some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits).

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
---
 drivers/net/ftgmac100.c   | 31 +++
 configs/evb-ast2500_defconfig |  8 
 2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index a5f2f01b7179..fb081769c9a4 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -42,6 +42,14 @@
  */
 #define MDC_CYCTHR 0x34
 
+/*
+ * ftgmac100 model variants
+ */
+enum ftgmac100_model {
+   FTGMAC100_MODEL_FARADAY,
+   FTGMAC100_MODEL_ASPEED,
+};
+
 /**
  * struct ftgmac100_data - private data for the FTGMAC100 driver
  *
@@ -56,6 +64,8 @@
  * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  * @max_speed: Maximum speed of Ethernet connection supported by MAC
  * @clks: The bulk of clocks assigned to the device in the DT
+ * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
+ * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -72,6 +82,10 @@ struct ftgmac100_data {
u32 max_speed;
 
struct clk_bulk clks;
+
+   /* End of RX/TX ring buffer bits. Depend on model */
+   u32 rxdes0_edorr_mask;
+   u32 txdes0_edotr_mask;
 };
 
 /*
@@ -290,7 +304,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->txdes[i].txdes3 = 0;
priv->txdes[i].txdes0 = 0;
}
-   priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+   priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
 
start = (ulong)&priv->txdes[0];
end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
@@ -300,7 +314,7 @@ static int ftgmac100_start(struct udevice *dev)
priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
priv->rxdes[i].rxdes0 = 0;
}
-   priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+   priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
 
start = (ulong)&priv->rxdes[0];
end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
@@ -440,7 +454,7 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
flush_dcache_range(data_start, data_end);
 
/* Only one segment on TXBUF */
-   curr_des->txdes0 &= FTGMAC100_TXDES0_EDOTR;
+   curr_des->txdes0 &= priv->txdes0_edotr_mask;
curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
FTGMAC100_TXDES0_LTS |
FTGMAC100_TXDES0_TXBUF_SIZE(length) |
@@ -500,6 +514,14 @@ static int ftgmac100_ofdata_to_platdata(struct udevice 
*dev)
 
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
+   if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
+   priv->rxdes0_edorr_mask = BIT(30);
+   priv->txdes0_edotr_mask = BIT(30);
+   } else {
+   priv->rxdes0_edorr_mask = BIT(15);
+   priv->txdes0_edotr_mask = BIT(15);
+   }
+
return clk_get_bulk(dev, &priv->clks);
 }
 
@@ -559,7 +581,8 @@ static const struct eth_ops ftgmac100_ops = {
 };
 
 static const struct udevice_id ftgmac100_ids[] = {
-   { .compatible = "faraday,ftgmac100" },
+   { .compatible = "faraday,ftgmac100",  .data = FTGMAC100_MODEL_FARADAY },
+   { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED  },
{ }
 };
 
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 88230f4a12db..32581f5ada54 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -25,3 +25,11 @@ CONFIG_SYS_NS16550=y
 CONFIG_SYSRESET=y
 CONFIG_TIMER=y
 CONFIG_WDT=y
+CONFIG_NETDEVICES=y
+CONFIG_PHY=y
+CONFIG_DM_ETH=y
+CONFIG_FTGMAC100=y
+CONFIG_PHY_REALTEK=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
-- 
2.17.1

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[U-Boot] [PATCH v3 11/13] aspeed: Update ast2500 SoC DTS file to Linux v4.17-rc6 level

[Cédric Le Goater]

This is a large update of the AST2500 SoC DTS file bringing it to the
level of commit 927c2fc2db19 :

Author:  Joel Stanley 
Date:Sat Jun 2 01:18:53 2018 -0700

 ARM: dts: aspeed: Fix hwrng register address

There are some differences on the compatibility property names. scu,
reset and clock drivers are also different.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Reviewed-by: Simon Glass 
---

 Changes since v2 :

 - removed a couple more unused clock properties

 arch/arm/dts/ast2500.dtsi | 1949 ++---
 1 file changed, 1153 insertions(+), 796 deletions(-)

diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 7e0ad3a41ac5..98359bf92425 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -11,6 +11,29 @@
#size-cells = <1>;
interrupt-parent = <&vic>;
 
+   aliases {
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   i2c2 = &i2c2;
+   i2c3 = &i2c3;
+   i2c4 = &i2c4;
+   i2c5 = &i2c5;
+   i2c6 = &i2c6;
+   i2c7 = &i2c7;
+   i2c8 = &i2c8;
+   i2c9 = &i2c9;
+   i2c10 = &i2c10;
+   i2c11 = &i2c11;
+   i2c12 = &i2c12;
+   i2c13 = &i2c13;
+   serial0 = &uart1;
+   serial1 = &uart2;
+   serial2 = &uart3;
+   serial3 = &uart4;
+   serial4 = &uart5;
+   serial5 = &vuart;
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -22,12 +45,80 @@
};
};
 
+   memory@8000 {
+   device_type = "memory";
+   reg = <0x8000 0>;
+   };
+
ahb {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
 
+   fmc: flash-controller@1e62 {
+   reg = < 0x1e62 0xc4
+   0x2000 0x1000 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-fmc";
+   status = "disabled";
+   interrupts = <19>;
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@2 {
+   reg = < 2 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   };
+
+   spi1: flash-controller@1e63 {
+   reg = < 0x1e63 0xc4
+   0x3000 0x0800 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-spi";
+   status = "disabled";
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   };
+
+   spi2: flash-controller@1e631000 {
+   reg = < 0x1e631000 0xc4
+   0x3800 0x0800 >;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "aspeed,ast2500-spi";
+   status = "disabled";
+   flash@0 {
+   reg = < 0 >;
+   compatible = "jedec,spi-nor";
+   status = "disabled";
+   };
+   flash@1 {
+   reg = < 1 >;
+   compatible = "jedec,spi-nor"

[U-Boot] [PATCH v3 04/13] net: ftgmac100: use setbits_le32() in the reset method

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
---
 drivers/net/ftgmac100.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 67a7c73503c5..78cd9df62986 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -331,7 +331,7 @@ static void ftgmac100_reset(struct ftgmac100_data *priv)
 
debug("%s()\n", __func__);
 
-   writel(FTGMAC100_MACCR_SW_RST, &ftgmac100->maccr);
+   setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
 
while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
;
-- 
2.17.1

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[U-Boot] [PATCH v3 08/13] net: ftgmac100: add clock support

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
---
 drivers/net/ftgmac100.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index edf34c601c68..a5f2f01b7179 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -11,6 +11,7 @@
  * Copyright (C) 2018, IBM Corporation.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -54,6 +55,7 @@
  * @bus: The mdio bus
  * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
  * @max_speed: Maximum speed of Ethernet connection supported by MAC
+ * @clks: The bulk of clocks assigned to the device in the DT
  */
 struct ftgmac100_data {
struct ftgmac100 *iobase;
@@ -68,6 +70,8 @@ struct ftgmac100_data {
struct mii_dev *bus;
u32 phy_mode;
u32 max_speed;
+
+   struct clk_bulk clks;
 };
 
 /*
@@ -481,6 +485,7 @@ static int ftgmac100_write_hwaddr(struct udevice *dev)
 static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
 {
struct eth_pdata *pdata = dev_get_platdata(dev);
+   struct ftgmac100_data *priv = dev_get_priv(dev);
const char *phy_mode;
 
pdata->iobase = devfdt_get_addr(dev);
@@ -495,7 +500,7 @@ static int ftgmac100_ofdata_to_platdata(struct udevice *dev)
 
pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
 
-   return 0;
+   return clk_get_bulk(dev, &priv->clks);
 }
 
 static int ftgmac100_probe(struct udevice *dev)
@@ -509,6 +514,10 @@ static int ftgmac100_probe(struct udevice *dev)
priv->max_speed = pdata->max_speed;
priv->phy_addr = 0;
 
+   ret = clk_enable_bulk(&priv->clks);
+   if (ret)
+   goto out;
+
ret = ftgmac100_mdio_init(priv, dev->seq);
if (ret) {
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
@@ -522,6 +531,9 @@ static int ftgmac100_probe(struct udevice *dev)
}
 
 out:
+   if (ret)
+   clk_release_bulk(&priv->clks);
+
return ret;
 }
 
@@ -532,6 +544,7 @@ static int ftgmac100_remove(struct udevice *dev)
free(priv->phydev);
mdio_unregister(priv->bus);
mdio_free(priv->bus);
+   clk_release_bulk(&priv->clks);
 
return 0;
 }
-- 
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[U-Boot] [PATCH v3 07/13] net: ftgmac100: handle timeouts when transmitting

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
---
 drivers/net/ftgmac100.c | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index b46187b567c6..edf34c601c68 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -28,6 +28,9 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/* Timeout for transmit */
+#define FTGMAC100_TX_TIMEOUT_MS1000
+
 /* Timeout for a mdio read/write operation */
 #define FTGMAC100_MDIO_TIMEOUT_USEC1
 
@@ -412,6 +415,7 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
ulong data_start;
ulong data_end;
+   ulong start;
 
invalidate_dcache_range(des_start, des_end);
 
@@ -444,6 +448,20 @@ static int ftgmac100_send(struct udevice *dev, void 
*packet, int length)
/* Start transmit */
writel(1, &ftgmac100->txpd);
 
+   /* Wait until packet is transmitted */
+   start = get_timer(0);
+   while (get_timer(start) < FTGMAC100_TX_TIMEOUT_MS) {
+   invalidate_dcache_range(des_start, des_end);
+   if (!(curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN))
+   break;
+   udelay(10);
+   }
+
+   if (get_timer(start) >= FTGMAC100_TX_TIMEOUT_MS) {
+   dev_err(dev, "transmit timeout\n");
+   return -ETIMEDOUT;
+   }
+
debug("%s(): packet sent\n", __func__);
 
/* Move to next descriptor */
-- 
2.17.1

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[U-Boot] [PATCH v3 06/13] net: ftgmac100: convert the RX/TX descriptor arrays

[Cédric Le Goater]

Use simple arrays under the device priv structure to hold the RX and
TX descriptors and handle memory coherency by invalidating or flushing
the d-cache when required.

Signed-off-by: Cédric Le Goater 
---

 At this stage, the drive is functional.
 
 drivers/net/ftgmac100.c | 141 ++--
 1 file changed, 64 insertions(+), 77 deletions(-)

diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index 1929e9510c26..b46187b567c6 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -13,19 +13,17 @@
 
 #include 
 #include 
-#include 
 #include 
 #include 
-#include 
 #include 
 
 #include "ftgmac100.h"
 
-#define ETH_ZLEN   60
-#define CFG_XBUF_SIZE  1536
+/* Min frame ethernet frame size without FCS */
+#define ETH_ZLEN   60
 
-/* RBSR - hw default init value is also 0x640 */
-#define RBSR_DEFAULT_VALUE 0x640
+/* Receive Buffer Size Register - HW default is 0x640 */
+#define FTGMAC100_RBSR_DEFAULT 0x640
 
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
@@ -57,10 +55,8 @@
 struct ftgmac100_data {
struct ftgmac100 *iobase;
 
-   ulong txdes_dma;
-   struct ftgmac100_txdes *txdes;
-   ulong rxdes_dma;
-   struct ftgmac100_rxdes *rxdes;
+   struct ftgmac100_txdes txdes[PKTBUFSTX];
+   struct ftgmac100_rxdes rxdes[PKTBUFSRX];
int tx_index;
int rx_index;
 
@@ -264,10 +260,8 @@ static int ftgmac100_start(struct udevice *dev)
struct ftgmac100_data *priv = dev_get_priv(dev);
struct ftgmac100 *ftgmac100 = priv->iobase;
struct phy_device *phydev = priv->phydev;
-   struct ftgmac100_txdes *txdes;
-   struct ftgmac100_rxdes *rxdes;
unsigned int maccr;
-   void *buf;
+   ulong start, end;
int ret;
int i;
 
@@ -275,26 +269,6 @@ static int ftgmac100_start(struct udevice *dev)
 
ftgmac100_reset(priv);
 
-   if (!priv->txdes) {
-   txdes = dma_alloc_coherent(
-   sizeof(*txdes) * PKTBUFSTX, &priv->txdes_dma);
-   if (!txdes)
-   panic("ftgmac100: out of memory\n");
-   memset(txdes, 0, sizeof(*txdes) * PKTBUFSTX);
-   priv->txdes = txdes;
-   }
-   txdes = priv->txdes;
-
-   if (!priv->rxdes) {
-   rxdes = dma_alloc_coherent(
-   sizeof(*rxdes) * PKTBUFSRX, &priv->rxdes_dma);
-   if (!rxdes)
-   panic("ftgmac100: out of memory\n");
-   memset(rxdes, 0, sizeof(*rxdes) * PKTBUFSRX);
-   priv->rxdes = rxdes;
-   }
-   rxdes = priv->rxdes;
-
/* set the ethernet address */
ftgmac100_set_mac(priv, plat->enetaddr);
 
@@ -305,42 +279,37 @@ static int ftgmac100_start(struct udevice *dev)
priv->tx_index = 0;
priv->rx_index = 0;
 
-   txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
-   rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
-
for (i = 0; i < PKTBUFSTX; i++) {
-   /* TXBUF_BADR */
-   if (!txdes[i].txdes2) {
-   buf = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
-   if (!buf)
-   panic("ftgmac100: out of memory\n");
-   txdes[i].txdes3 = virt_to_phys(buf);
-   txdes[i].txdes2 = (uint)buf;
-   }
-   txdes[i].txdes1 = 0;
+   priv->txdes[i].txdes3 = 0;
+   priv->txdes[i].txdes0 = 0;
}
+   priv->txdes[PKTBUFSTX - 1].txdes0 = FTGMAC100_TXDES0_EDOTR;
+
+   start = (ulong)&priv->txdes[0];
+   end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
+   flush_dcache_range(start, end);
 
for (i = 0; i < PKTBUFSRX; i++) {
-   /* RXBUF_BADR */
-   if (!rxdes[i].rxdes2) {
-   buf = net_rx_packets[i];
-   rxdes[i].rxdes3 = virt_to_phys(buf);
-   rxdes[i].rxdes2 = (uint)buf;
-   }
-   rxdes[i].rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
+   priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
+   priv->rxdes[i].rxdes0 = 0;
}
+   priv->rxdes[PKTBUFSRX - 1].rxdes0 = FTGMAC100_RXDES0_EDORR;
+
+   start = (ulong)&priv->rxdes[0];
+   end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
+   flush_dcache_range(start, end);
 
/* transmit ring */
-   writel(priv->txdes_dma, &ftgmac100->txr_badr);
+   writel((u32)priv->txdes, &ftgmac100->txr_badr);
 
/* receive ring */
-   writel(priv->rxdes_dma, &ftgmac100->rxr_badr);
+   writel((u32)priv->rxdes, 

[U-Boot] [PATCH v3 09/13] aspeed: ast2500: fix missing break in D2PLL clock enablement

[Cédric Le Goater]

Signed-off-by: Cédric Le Goater 
Reviewed-by: Joel Stanley 
Reviewed-by: Simon Glass 
---
 drivers/clk/aspeed/clk_ast2500.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 526470051c5d..2182320f607f 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -411,6 +411,7 @@ static int ast2500_clk_enable(struct clk *clk)
break;
case PLL_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
+   break;
default:
return -ENOENT;
}
-- 
2.17.1

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[U-Boot] [PATCH v3 13/13] aspeed: ast2500: fix D2-PLL clock setting in RGMII mode

[Cédric Le Goater]

The algorithm in the ast2500_calc_clock_config() routine suffers from
integer rounding and the requested rate does not get the appropriate
set of Numerator, Denumerator, Post Divider parameters.

This is the case for the D2-PLL clock used by the MAC controllers in
RGMII mode. The requested rated is 250MHz but a 251MHz is assigned.

The easiest way to fix this problem is to introduce an array of clock
settings defining the N, M, P parameters for well known frequencies
used by the Aspeed SoC.

Signed-off-by: Cédric Le Goater 
Reviewed-by: Simon Glass 
---
 drivers/clk/aspeed/clk_ast2500.c | 38 
 1 file changed, 38 insertions(+)

diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 2182320f607f..dbee13a18297 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -165,6 +165,35 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
 }
 
+struct ast2500_clock_config {
+   ulong input_rate;
+   ulong rate;
+   struct ast2500_div_config cfg;
+};
+
+static const struct ast2500_clock_config ast2500_clock_config_defaults[] = {
+   { 2400, 25000, { .num = 124, .denum = 1, .post_div = 5 } },
+};
+
+static bool ast2500_get_clock_config_default(ulong input_rate,
+ulong requested_rate,
+struct ast2500_div_config *cfg)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(ast2500_clock_config_defaults); i++) {
+   const struct ast2500_clock_config *default_cfg =
+   &ast2500_clock_config_defaults[i];
+   if (default_cfg->input_rate == input_rate &&
+   default_cfg->rate == requested_rate) {
+   *cfg = default_cfg->cfg;
+   return true;
+   }
+   }
+
+   return false;
+}
+
 /*
  * @input_rate - the rate of input clock in Hz
  * @requested_rate - desired output rate in Hz
@@ -189,6 +218,12 @@ static ulong ast2500_calc_clock_config(ulong input_rate, 
ulong requested_rate,
ulong delta = rate_khz;
ulong new_rate_khz = 0;
 
+   /*
+* Look for a well known frequency first.
+*/
+   if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg))
+   return requested_rate;
+
for (; it.denum <= max_vals.denum; ++it.denum) {
for (it.post_div = 0; it.post_div <= max_vals.post_div;
 ++it.post_div) {
@@ -318,6 +353,9 @@ static ulong ast2500_configure_d2pll(struct ast2500_scu 
*scu, ulong rate)
/*
 * The values and the meaning of the next three
 * parameters are undocumented. Taken from Aspeed SDK.
+*
+* TODO(c...@kaod.org): the SIP and SIC values depend on the
+* Numerator value
 */
const u32 d2_pll_ext_param = 0x2c;
const u32 d2_pll_sip = 0x11;
-- 
2.17.1

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[U-Boot] [PATCH v3 03/13] net: ftgmac100: convert to driver model

[Cédric Le Goater]

The driver is based on the previous one and the code is only adapted
to fit the driver model. The support for the Faraday ftgmac100
controller is the same with MAC and MDIO bus support for RGMII/RMII
modes.

Configuration is updated to enable compile again. At this stage, the
driver compiles but is not yet functional.

Signed-off-by: Cédric Le Goater 
---
 include/netdev.h|   1 -
 drivers/net/ftgmac100.c | 223 +++-
 drivers/net/Kconfig |  26 +
 3 files changed, 157 insertions(+), 93 deletions(-)

diff --git a/include/netdev.h b/include/netdev.h
index 55001625fb92..0a1a3a2d8da2 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -43,7 +43,6 @@ int ethoc_initialize(u8 dev_num, int base_addr);
 int fec_initialize (bd_t *bis);
 int fecmxc_initialize(bd_t *bis);
 int fecmxc_initialize_multi(bd_t *bis, int dev_id, int phy_id, uint32_t addr);
-int ftgmac100_initialize(bd_t *bits);
 int ftmac100_initialize(bd_t *bits);
 int ftmac110_initialize(bd_t *bits);
 void gt6426x_eth_initialize(bd_t *bis);
diff --git a/drivers/net/ftgmac100.c b/drivers/net/ftgmac100.c
index c996f5f4a167..67a7c73503c5 100644
--- a/drivers/net/ftgmac100.c
+++ b/drivers/net/ftgmac100.c
@@ -7,15 +7,16 @@
  *
  * (C) Copyright 2010 Andes Technology
  * Macpaul Lin 
+ *
+ * Copyright (C) 2018, IBM Corporation.
  */
 
-#include 
-#include 
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
-#include 
 
 #include "ftgmac100.h"
 
@@ -28,7 +29,19 @@
 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
 #define PKTBUFSTX  4   /* must be power of 2 */
 
+/**
+ * struct ftgmac100_data - private data for the FTGMAC100 driver
+ *
+ * @iobase: The base address of the hardware registers
+ * @txdes: The array of transmit descriptors
+ * @rxdes: The array of receive descriptors
+ * @tx_index: Transmit descriptor index in @txdes
+ * @rx_index: Receive descriptor index in @rxdes
+ * @phy_addr: The PHY interface address to use
+ */
 struct ftgmac100_data {
+   struct ftgmac100 *iobase;
+
ulong txdes_dma;
struct ftgmac100_txdes *txdes;
ulong rxdes_dma;
@@ -41,10 +54,10 @@ struct ftgmac100_data {
 /*
  * struct mii_bus functions
  */
-static int ftgmac100_mdiobus_read(struct eth_device *dev, int phy_addr,
-   int regnum)
+static int ftgmac100_mdiobus_read(struct ftgmac100_data *priv, int phy_addr,
+ int regnum)
 {
-   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+   struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int i;
 
@@ -76,10 +89,10 @@ static int ftgmac100_mdiobus_read(struct eth_device *dev, 
int phy_addr,
return -1;
 }
 
-static int ftgmac100_mdiobus_write(struct eth_device *dev, int phy_addr,
-   int regnum, u16 value)
+static int ftgmac100_mdiobus_write(struct ftgmac100_data *priv, int phy_addr,
+  int regnum, u16 value)
 {
-   struct ftgmac100 *ftgmac100 = (struct ftgmac100 *)dev->iobase;
+   struct ftgmac100 *ftgmac100 = priv->iobase;
int phycr;
int data;
int i;
@@ -114,9 +127,10 @@ static int ftgmac100_mdiobus_write(struct eth_device *dev, 
int phy_addr,
return -1;
 }
 
-int ftgmac100_phy_read(struct eth_device *dev, int addr, int reg, u16 *value)
+int ftgmac100_phy_read(struct ftgmac100_data *priv, int addr, int reg,
+  u16 *value)
 {
-   *value = ftgmac100_mdiobus_read(dev , addr, reg);
+   *value = ftgmac100_mdiobus_read(priv, addr, reg);
 
if (*value == -1)
return -1;
@@ -124,31 +138,31 @@ int ftgmac100_phy_read(struct eth_device *dev, int addr, 
int reg, u16 *value)
return 0;
 }
 
-int  ftgmac100_phy_write(struct eth_device *dev, int addr, int reg, u16 value)
+int ftgmac100_phy_write(struct ftgmac100_data *priv, int addr, int reg,
+   u16 value)
 {
-   if (ftgmac100_mdiobus_write(dev, addr, reg, value) == -1)
+   if (ftgmac100_mdiobus_write(priv, addr, reg, value) == -1)
return -1;
 
return 0;
 }
 
-static int ftgmac100_phy_reset(struct eth_device *dev)
+static int ftgmac100_phy_reset(struct ftgmac100_data *priv, struct udevice 
*dev)
 {
-   struct ftgmac100_data *priv = dev->priv;
int i;
u16 status, adv;
 
adv = ADVERTISE_CSMA | ADVERTISE_ALL;
 
-   ftgmac100_phy_write(dev, priv->phy_addr, MII_ADVERTISE, adv);
+   ftgmac100_phy_write(priv, priv->phy_addr, MII_ADVERTISE, adv);
 
printf("%s: Starting autonegotiation...\n", dev->name);
 
-   ftgmac100_phy_write(dev, priv->phy_addr,
-   MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
+   ftgmac100_phy_write(priv, priv->phy_addr,
+   MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
 
for (i = 0; i < 10 / 100; i++) {
-   ftgm