[U-Boot] [PATCH 6/8] ARM: socfpga: arria10: Add u-boot include for A10 SoCDK SDMMC devicetree

[Dalon Westergreen]

From: Dalon Westergreen 

Rather then modifying the devicetree to add u-boot specific
requirements, use the -u-boot.dtsi convention to allow
binman to merge the devicetree appropriately.

Signed-off-by: Dalon Westergreen 
---
 .../socfpga_arria10_socdk_sdmmc-u-boot.dtsi   | 34 +++
 1 file changed, 34 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
new file mode 100644
index 00..3f41b1950b
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2014-2015 Altera Corporation 
+ */
+
+#include 
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10-common-u-boot.dtsi"
+
+/ {
+   chosen {
+   firmware-loader = <_loader0>;
+   };
+
+   fs_loader0: fs-loader {
+   u-boot,dm-pre-reloc;
+   compatible = "u-boot,fs-loader";
+   phandlepart = < 1>;
+   };
+};
+
+_mgr {
+   u-boot,dm-pre-reloc;
+   altr,bitstream = "fit_spl_fpga.itb";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
-- 
2.21.0

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[U-Boot] [PATCH 7/8] ARM: socfpga: arria10: Remove old A10 SoCDK Handoff dtsi

[Dalon Westergreen]

From: Dalon Westergreen 

This file is no longer needed and has been replaced with
socfpga_arria10_handoff_u-boot.dtsi and a generated header.

Signed-off-by: Dalon Westergreen 
---
 .../socfpga_arria10_socdk_sdmmc_handoff.dtsi  | 329 --
 1 file changed, 329 deletions(-)
 delete mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi 
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
deleted file mode 100644
index 60c419251b..00
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
+++ /dev/null
@@ -1,329 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * Copyright (C) 2016-2017 Intel Corporation
- *
- *
- * This code was generated by a tool based on
- * handoffs from both Qsys and Quartus.
- *
- * Changes to this file may be lost if
- * the code is regenerated.
- *
- */
-
-/ {
-   #address-cells = <1>;
-   #size-cells = <1>;
-   model = "SOCFPGA Arria10 Dev Kit";  /* Bootloader setting: 
uboot.model */
-
-   /* Clock sources */
-   clocks {
-   #address-cells = <1>;
-   #size-cells = <1>;
-
-   /* Clock source: altera_arria10_hps_eosc1 */
-   altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <2500>;
-   clock-output-names = "altera_arria10_hps_eosc1-clk";
-   };
-
-   /* Clock source: altera_arria10_hps_cb_intosc_ls */
-   altera_arria10_hps_cb_intosc_ls: 
altera_arria10_hps_cb_intosc_ls {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <6000>;
-   clock-output-names = 
"altera_arria10_hps_cb_intosc_ls-clk";
-   };
-
-   /* Clock source: altera_arria10_hps_f2h_free */
-   altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <2>;
-   clock-output-names = "altera_arria10_hps_f2h_free-clk";
-   };
-   };
-
-   /*
-* Driver: altera_arria10_soc_clock_manager_arria10_uboot_driver
-* Version: 1.0
-* Binding: device
-*/
-   i_clk_mgr: clock_manager@0xffd04000 {
-   compatible = "altr,socfpga-a10-clk-init";
-   reg = <0xffd04000 0x0200>;
-   reg-names = "soc_clock_manager_OCP_SLV";
-
-   /* Address Block: 
soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
-   mainpll {
-   vco0-psrc = <0>;/* Field: vco0.psrc */
-   vco1-denom = <1>;   /* Field: vco1.denom */
-   vco1-numer = <191>; /* Field: vco1.numer */
-   mpuclk-cnt = <0>;   /* Field: mpuclk.cnt */
-   mpuclk-src = <0>;   /* Field: mpuclk.src */
-   nocclk-cnt = <0>;   /* Field: nocclk.cnt */
-   nocclk-src = <0>;   /* Field: nocclk.src */
-   cntr2clk-cnt = <900>;   /* Field: cntr2clk.cnt */
-   cntr3clk-cnt = <900>;   /* Field: cntr3clk.cnt */
-   cntr4clk-cnt = <900>;   /* Field: cntr4clk.cnt */
-   cntr5clk-cnt = <900>;   /* Field: cntr5clk.cnt */
-   cntr6clk-cnt = <900>;   /* Field: cntr6clk.cnt */
-   cntr7clk-cnt = <900>;   /* Field: cntr7clk.cnt */
-   cntr7clk-src = <0>; /* Field: cntr7clk.src */
-   cntr8clk-cnt = <900>;   /* Field: cntr8clk.cnt */
-   cntr9clk-cnt = <900>;   /* Field: cntr9clk.cnt */
-   cntr9clk-src = <0>; /* Field: cntr9clk.src */
-   cntr15clk-cnt = <900>;  /* Field: cntr15clk.cnt */
-   nocdiv-l4mainclk = <0>; /* Field: nocdiv.l4mainclk */
-   nocdiv-l4mpclk = <0>;   /* Field: nocdiv.l4mpclk */
-   nocdiv-l4spclk = <2>;   /* Field: nocdiv.l4spclk */
-   nocdiv-csatclk = <0>;   /* Field: nocdiv.csatclk */
-   nocdiv-cstraceclk = <1>;/* Field: 
nocdiv.cstraceclk */
-   nocdiv-cspdbgclk = <1>; /* Field: nocdiv.cspdbgclk */
-   };
-
-   /* A

[U-Boot] [PATCH 4/8] ARM: socfpga: arria10: Add generic handoff devicetree include

[Dalon Westergreen]

From: Dalon Westergreen 

Generic handoff devicetree include uses a header generated by
the qts-filter-a10.sh script in mach-socfpga.  The script
creates the header based on design specific implementations
for clock and pinmux configurations.

Signed-off-by: Dalon Westergreen 
---
 .../dts/socfpga_arria10_handoff_u-boot.dtsi   | 232 --
 1 file changed, 216 insertions(+), 16 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
index ef215230c2..69854352a0 100644
--- a/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
@@ -1,91 +1,291 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 
 / {
-   chosen {
-   u-boot,dm-pre-reloc;
-   };
-
clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
u-boot,dm-pre-reloc;
 
-   altera_arria10_hps_eosc1 {
+   altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = ;
+   clock-output-names = "altera_arria10_hps_eosc1-clk";
u-boot,dm-pre-reloc;
};
 
-   altera_arria10_hps_cb_intosc_ls {
+   altera_arria10_hps_cb_intosc_ls: 
altera_arria10_hps_cb_intosc_ls {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = ;
+   clock-output-names = 
"altera_arria10_hps_cb_intosc_ls-clk";
u-boot,dm-pre-reloc;
};
 
-   altera_arria10_hps_f2h_free {
+   /* Clock source: altera_arria10_hps_f2h_free */
+   altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = ;
+   clock-output-names = "altera_arria10_hps_f2h_free-clk";
u-boot,dm-pre-reloc;
};
};
 
-   clock_manager@0xffd04000 {
+   clkmgr@0xffd04000 {
+   compatible = "altr,socfpga-a10-clk-init";
+   reg = <0xffd04000 0x0200>;
+   reg-names = "soc_clock_manager_OCP_SLV";
u-boot,dm-pre-reloc;
 
mainpll {
+   vco0-psrc = ;
+   vco1-denom = ;
+   vco1-numer = ;
+   mpuclk-cnt = ;
+   mpuclk-src = ;
+   nocclk-cnt = ;
+   nocclk-src = ;
+   cntr2clk-cnt = ;
+   cntr3clk-cnt = ;
+   cntr4clk-cnt = ;
+   cntr5clk-cnt = ;
+   cntr6clk-cnt = ;
+   cntr7clk-cnt = ;
+   cntr7clk-src = ;
+   cntr8clk-cnt = ;
+   cntr9clk-cnt = ;
+   cntr9clk-src = ;
+   cntr15clk-cnt = ;
+   nocdiv-l4mainclk = ;
+   nocdiv-l4mpclk = ;
+   nocdiv-l4spclk = ;
+   nocdiv-csatclk = ;
+   nocdiv-cstraceclk = ;
+   nocdiv-cspdbgclk = ;
u-boot,dm-pre-reloc;
};
 
perpll {
+   vco0-psrc = ;
+   vco1-denom = ;
+   vco1-numer = ;
+   cntr2clk-cnt = ;
+   cntr2clk-src = ;
+   cntr3clk-cnt = ;
+   cntr3clk-src = ;
+   cntr4clk-cnt = ;
+   cntr4clk-src = ;
+   cntr5clk-cnt = ;
+   cntr5clk-src = ;
+   cntr6clk-cnt = ;
+   cntr6clk-src = ;
+   cntr7clk-cnt = ;
+   cntr8clk-cnt = ;
+   cntr8clk-src = ;
+   cntr9clk-cnt = ;
+   emacctl-emac0sel = ;
+   emacctl-emac1sel = ;
+   emacctl-emac2sel = ;
+   gpiodiv-gpiodbclk = ;
u-boot,dm-pre-reloc;
};
 
alteragrp {
+   nocclk = ;
+   mpuclk = ;
u-boot,dm-pre-reloc;
};
};
 
-   pinmux@0xffd07000 {
+   i_io48_pin_mux: pinmux@0xffd07000 {
+   #address-cells = <1>;
+   #size-cells = &l

[U-Boot] [PATCH 5/8] ARM: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC

[Dalon Westergreen]

From: Dalon Westergreen 

Add the qts-filter-a10.sh generated handoff data for the arria10
socdk sdmmc uboot devicetree.

Signed-off-by: Dalon Westergreen 
---
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 305 ++
 1 file changed, 305 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h

diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h 
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
new file mode 100644
index 00..3fdc04
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 6000
+#define EMAC0_CLK_HZ 25000
+#define EMAC1_CLK_HZ 25000
+#define EMAC2_CLK_HZ 25000
+#define EOSC1_CLK_HZ 2500
+#define F2H_FREE_CLK_HZ 2
+#define H2F_USER0_CLK_HZ 4
+#define H2F_USER1_CLK_HZ 4
+#define L3_MAIN_FREE_CLK_HZ 2
+#define SDMMC_CLK_HZ 2
+#define TPIU_CLK_HZ 1
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_CNT 900
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 1
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 0
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 1
+#define MAINPLLGRP_VCO1_NUMER 191
+#define PERPLLGRP_CNTR2CLK_CNT 7
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 19
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 499
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 9
+#define PERPLLGRP_CNTR6CLK_SRC 1
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 1
+#define PERPLLGRP_VCO1_NUMER 159
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 11
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+   (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+   (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 0
+#define CONFIG_IO_10_PD_DRV_STRG 0
+#define CONFIG_IO_10_PD_SLW_RT 0
+#define CONFIG_IO_10_PU_DRV_STRG 0
+#define CONFIG_IO_10_PU_SLW_RT 0
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 1
+#define CONFIG_IO_11_INPUT_BUF_EN 0
+#define CONFIG_IO_11_PD_DRV_STRG 0
+#define CONFIG_IO_11_PD_SLW_RT 0
+#define CONFIG_IO_11_PU_DRV_STRG 0
+#define CONFIG_IO_11_PU_SLW_RT 0
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 1
+#define CONFIG_IO_12_INPUT_BUF_EN 1
+#define CONFIG_IO_12_PD_DRV_STRG 10
+#define CONFIG_IO_12_PD_SLW_RT 1
+#define CONFIG_IO_12_PU_DRV_STRG 8
+#define CONFIG_IO_12_PU_SLW_RT 1
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 1
+#define CONFIG_IO_13_INPUT_BUF_EN 1
+#define CONFIG_IO_13_PD_DRV_STRG 10
+#define CONFIG_IO_13_PD_SLW_RT 1
+#define CONFIG_IO_13_PU_DRV_STRG 8
+#define CONFIG_IO_13_PU_SLW_RT 1
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 1
+#define CONFIG_IO_14_INPUT_BUF_EN 1
+#define CONFIG_IO_14_PD_DRV_STRG 10
+#define CONFIG_IO_14_PD_SLW_RT 1
+#define CONFIG_IO_14_PU_DRV_STRG 8
+#define CONFIG_IO_14_PU_SLW_RT 1
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 1
+#define CONFIG_IO_15_INPUT_BUF_EN 1
+#define CONFIG_IO_15_PD_DRV_STRG 10
+#define CONFIG_IO_15_PD_SLW_RT 1
+#define CONFIG_IO_15_PU_DRV_STRG 8
+#define CONFIG_IO_15_PU_SLW_RT 1
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 1
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PU_DRV_STRG 8
+#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_RTRIM 1
+#define CONFIG_IO_16_WK_PU_EN 0
+#define CONFIG_IO_17_INPUT_BUF_E

[U-Boot] [PATCH 8/8] ARM: socfpga: Update README.socfpga to add qts-filter-a10

[Dalon Westergreen]

From: Dalon Westergreen 

Update the readme to add a simple description of using
the qts-filter-a10.sh script.

Signed-off-by: Dalon Westergreen 
---
 doc/README.socfpga | 37 +
 1 file changed, 33 insertions(+), 4 deletions(-)

diff --git a/doc/README.socfpga b/doc/README.socfpga
index cae0ef1a21..c5a3b11133 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -16,9 +16,9 @@ controller support within SOCFPGA
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256
 -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
 
---
-Generating the handoff header files for U-Boot SPL
---
+-
+Cyclone5 / Arria 5 Generating the handoff header files for U-Boot SPL
+-
 
 This text is assuming quartus 16.1, but newer versions will probably work just 
fine too;
 verified with DE1_SOC_Linux_FB demo project 
(https://github.com/VCTLabs/DE1_SOC_Linux_FB).
@@ -32,7 +32,7 @@ Rebuilding your Quartus project
 
 Choose one of the follwing methods, either command line or GUI.
 
-Using the comaand line
+Using the command line
 ~~
 
 First run the embedded command shell, using your path to the Quartus install:
@@ -147,3 +147,32 @@ Note: file sizes will differ slightly depending on the 
selected board.
 
 Now your board is ready for full mainline support including U-Boot SPL.
 The Preloader will not be needed any more.
+
+--
+Arria10 Generating the handoff header files for U-Boot SPL
+--
+
+A header file for inclusion in a devicetree for Arria10 can be generated
+by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
+file generated during the FPGA project compilation.  The header contains
+all PLL, clock, pinmux, and bridge configurations required.
+
+Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
+that includes use of the generated handoff header.
+
+Devicetree header generation
+
+
+The qts-filter-a10.sh script can process the compile time genetated hps.xml
+to create the appropriate devicetree header.
+
+
+  $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
+ \
+
+
+hps_xml  - hps_isw_handoff/hps.xml from Quartus project
+output_file  - Output filename and location for header file
+
+The script generates a single header file names  that should
+be placed in arch/arm/dts.
-- 
2.21.0

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[U-Boot] [PATCH 2/8] ARM: socfpga: arria10: Sync A10 SoCDK devicetrees

[Dalon Westergreen]

From: Dalon Westergreen 

Sync devicetree from 5.2 kernel.

Signed-off-by: Dalon Westergreen 
---
 arch/arm/dts/socfpga_arria10.dtsi| 104 ++-
 arch/arm/dts/socfpga_arria10_socdk.dtsi  |  75 +++--
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts |  53 +-
 3 files changed, 100 insertions(+), 132 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10.dtsi 
b/arch/arm/dts/socfpga_arria10.dtsi
index c11a5c0cc1..b175e05735 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright Altera Corporation (C) 2014. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #include 
@@ -21,11 +10,6 @@
#address-cells = <1>;
#size-cells = <1>;
 
-   chosen {
-   tick-timer = 
-   u-boot,dm-pre-reloc;
-   };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -60,7 +44,6 @@
device_type = "soc";
interrupt-parent = <>;
ranges;
-   u-boot,dm-pre-reloc;
 
amba {
compatible = "simple-bus";
@@ -85,6 +68,7 @@
#dma-requests = <32>;
clocks = <_main_clk>;
clock-names = "apb_pclk";
+   microcode-cached;
};
};
 
@@ -99,35 +83,29 @@
clkmgr@ffd04000 {
compatible = "altr,clk-mgr";
reg = <0xffd04000 0x1000>;
-   u-boot,dm-pre-reloc;
 
clocks {
#address-cells = <1>;
#size-cells = <0>;
-   u-boot,dm-pre-reloc;
 
cb_intosc_hs_div2_clk: 
cb_intosc_hs_div2_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
-   u-boot,dm-pre-reloc;
};
 
cb_intosc_ls_clk: cb_intosc_ls_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
-   u-boot,dm-pre-reloc;
};
 
f2s_free_clk: f2s_free_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
-   u-boot,dm-pre-reloc;
};
 
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
-   u-boot,dm-pre-reloc;
};
 
main_pll: main_pll@40 {
@@ -138,7 +116,6 @@
clocks = <>, 
<_intosc_ls_clk>,
 <_free_clk>;
reg = <0x40>;
-   u-boot,dm-pre-reloc;
 
main_mpu_base_clk: 
main_mpu_base_clk {
#clock-cells = <0>;
@@ -152,7 +129,6 @@
compatible = 
"altr,socfpga-a10-perip-clk";
clocks = <_pll>;
div-reg = <0x144 0 11>;
-   u-boot,dm-pre-reloc;
 

[U-Boot] [PATCH 3/8] ARM: socfpga: arria10: Add common u-boot devicetree include

[Dalon Westergreen]

From: Dalon Westergreen 

Add a common u-boot devicetree include file for the SocFPGA
Arria10 device.

Signed-off-by: Dalon Westergreen 
---
 .../dts/socfpga_arria10-common-u-boot.dtsi| 206 ++
 1 file changed, 206 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10-common-u-boot.dtsi

diff --git a/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
new file mode 100644
index 00..bd4f1271f3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright Altera Corporation (C) 2014. All rights reserved.
+ */
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   chosen {
+   tick-timer = 
+   u-boot,dm-pre-reloc;
+   };
+
+   memory@0 {
+   u-boot,dm-pre-reloc;
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+
+   clkmgr@ffd04000 {
+   u-boot,dm-pre-reloc;
+
+   clocks {
+   u-boot,dm-pre-reloc;
+
+   cb_intosc_hs_div2_clk {
+   u-boot,dm-pre-reloc;
+   };
+
+   cb_intosc_ls_clk {
+   u-boot,dm-pre-reloc;
+   };
+
+   f2s_free_clk {
+   u-boot,dm-pre-reloc;
+   };
+
+   osc1 {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_pll@40 {
+   u-boot,dm-pre-reloc;
+
+   main_mpu_base_clk {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_noc_base_clk {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_emaca_clk@68 {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_emacb_clk@6c {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_emac_ptp_clk@70 {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_gpio_db_clk@74 {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_sdmmc_clk@78 {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_s2f_usr0_clk@7c {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_s2f_usr1_clk@80 {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_hmc_pll_ref_clk@84 {
+   u-boot,dm-pre-reloc;
+   };
+
+   main_periph_ref_clk@9c {
+   u-boot,dm-pre-reloc;
+   };
+   };
+
+   periph_pll@c0 {
+   u-boot,dm-pre-reloc;
+
+   peri_mpu_base_clk {
+   u-boot,dm-pre-reloc;
+   };
+
+   peri_noc_base_clk {
+   u-boot,dm-pre-reloc;
+   };
+
+   peri_emaca_clk@e8 {
+   u-boot,dm-pre-reloc;
+   };
+
+   peri_

[U-Boot] [PATCH 0/8] ARM: socfpga: arria10: Cleanup devicetree and

[Dalon Westergreen]

From: Dalon Westergreen 

This series sync the arria10 devicetree to the kernel devicetree
and cleans up the inclusion of u-boot specific requirements.  It
also adds a new qts-filter-a10.sh script to allow for generation
of project specific settings required for configuration of the
device clocks, PLLs, and pinmux.

Dalon Westergreen (8):
  ARM: socfpga: arria10: Add qts-filter for arria10 socfpga
  ARM: socfpga: arria10: Sync A10 SoCDK devicetrees
  ARM: socfpga: arria10: Add common u-boot devicetree include
  ARM: socfpga: arria10: Add generic handoff devicetree include
  ARM: socfpga: arria10: Add handoff header for A10 SoCDK SDMMC
  ARM: socfpga: arria10: Add u-boot include for A10 SoCDK SDMMC
devicetree
  ARM: socfpga: arria10: Remove old A10 SoCDK Handoff dtsi
  ARM: socfpga: Update README.socfpga to add qts-filter-a10

 .../dts/socfpga_arria10-common-u-boot.dtsi| 206 +++
 arch/arm/dts/socfpga_arria10.dtsi | 104 +++---
 .../dts/socfpga_arria10_handoff_u-boot.dtsi   | 232 +++-
 arch/arm/dts/socfpga_arria10_socdk.dtsi   |  75 ++--
 .../socfpga_arria10_socdk_sdmmc-u-boot.dtsi   |  34 ++
 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts  |  53 +--
 .../socfpga_arria10_socdk_sdmmc_handoff.dtsi  | 329 --
 .../dts/socfpga_arria10_socdk_sdmmc_handoff.h | 305 
 arch/arm/mach-socfpga/qts-filter-a10.sh   | 141 
 doc/README.socfpga|  37 +-
 10 files changed, 1035 insertions(+), 481 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10-common-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc-u-boot.dtsi
 delete mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h
 create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh

-- 
2.21.0

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[U-Boot] [PATCH 1/8] ARM: socfpga: arria10: Add qts-filter for arria10 socfpga

[Dalon Westergreen]

From: Dalon Westergreen 

Add a script to process hps handoff data and generate a header
for inclusion in u-boot specific devicetree addons.  The header
should be included in the top level u-boot.dtsi.

Signed-off-by: Dalon Westergreen 
---
 arch/arm/mach-socfpga/qts-filter-a10.sh | 141 
 1 file changed, 141 insertions(+)
 create mode 100755 arch/arm/mach-socfpga/qts-filter-a10.sh

diff --git a/arch/arm/mach-socfpga/qts-filter-a10.sh 
b/arch/arm/mach-socfpga/qts-filter-a10.sh
new file mode 100755
index 00..ddb0d0a6f3
--- /dev/null
+++ b/arch/arm/mach-socfpga/qts-filter-a10.sh
@@ -0,0 +1,141 @@
+#!/bin/bash
+
+#
+# helper function to convert from DOS to Unix, if necessary, and handle
+# lines ending in '\'.
+#
+fix_newlines_in_macros() {
+   sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
+}
+
+#filter out only what we need from a10 hps.xml
+grep_a10_hps_config() {
+   egrep "clk_hz|i_clk_mgr|i_io48_pin_mux|AXI_SLAVE|AXI_MASTER"
+}
+
+#
+# Process hps.xml
+# $1:  hps.xml
+# $2:  Output File
+#
+process_a10_hps_config() {
+   hps_xml="$1"
+   outfile="$2"
+
+   (cat << EOF
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Altera Arria10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+EOF
+
+   echo "/* Clocks */"
+   fix_newlines_in_macros \
+   ${hps_xml} | egrep "clk_hz" |
+   awk -F"'" '{ gsub("\\.","_",$2) ; \
+   print "#define" " " toupper($2) " " $4}' |
+   sed 's/\.[0-9]//' |
+   sed 's/I_CLK_MGR_//' |
+   sort
+   fix_newlines_in_macros \
+   ${hps_xml} | egrep "i_clk_mgr_mainpll" |
+   awk -F"'" '{ gsub("\\.","_",$2) ; \
+   print "#define" " " toupper($2) " " $4}' |
+   sed 's/\.[0-9]//' |
+   sed 's/I_CLK_MGR_//' |
+   sort
+   fix_newlines_in_macros \
+   ${hps_xml} | egrep "i_clk_mgr_perpll" |
+   awk -F"'" '{ gsub("\\.","_",$2) ; \
+   print "#define" " " toupper($2) " " $4}' |
+   sed 's/\.[0-9]//' |
+   sed 's/I_CLK_MGR_//' |
+   sort
+   fix_newlines_in_macros \
+   ${hps_xml} | egrep "i_clk_mgr_clkmgr" |
+   awk -F"'" '{ gsub("\\.","_",$2) ; \
+   print "#define" " " toupper($2) " " $4}' |
+   sed 's/\.[0-9]//' |
+   sed 's/I_CLK_MGR_//' |
+   sort
+   fix_newlines_in_macros \
+   ${hps_xml} | egrep "i_clk_mgr_alteragrp" |
+   awk -F"'" '{ gsub("\\.","_",$2) ; \
+   print "#define" " " toupper($2) " " $4}' |
+   sed 's/\.[0-9]//' |
+   sed 's/I_CLK_MGR_//' |
+   sort
+   echo "#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\"
+   echo "  (ALTERAGRP_MPUCLK_MAINCNT))"
+   echo "#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\"
+   echo "  (ALTERAGRP_NOCCLK_MAINCNT))"
+
+   echo
+   echo "/* Pin Mux Configuration */"
+   fix_newlines_in_macros \
+   ${hps_xml} | egrep "i_io48_pin_mux" |
+   awk -F"'" '{ gsub("\\.","_",$2) ; \
+   print "#define" " " toupper($2) " " $4}' |
+   sed 's/I_IO48_PIN_MUX_//' |
+   sed 's/SHARED_3V_IO_GRP_//' |
+   sed 's/FPGA_INTERFACE_GRP_//' |
+   sed 's/DEDICATED_IO_GRP_//' |
+   sed 's/CONFIGURATION_DEDICATED/CONFIG/' |
+   sort
+
+   echo
+   echo "/* Bridge Configuration */"
+   fix_newlines_in_macros \
+   ${hps_xml} | egrep "AXI_SLAVE|AXI_MASTER" |
+   awk -F"'" '{ gsub("\\.","_",$2) ; \
+   print "#define" " " toupper($2) " " $4}' |
+   sed 's/true/1/' |
+   sed 's/false/0/' |
+   sort
+
+   echo
+   echo "/* Voltage Select for Config IO */"
+

[U-Boot] [RESEND PATCH v3 2/2] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED

[Dalon Westergreen]

From: Dalon Westergreen 

CONFIG_OF_EMBED was primarily enabled to support the stratix10
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Dalon Westergreen 
---
 configs/socfpga_stratix10_defconfig   | 1 -
 include/configs/socfpga_stratix10_socdk.h | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index 5ae53a4db9..ae1b9bead1 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -27,7 +27,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index 7b55dd14da..f9ecf9d2df 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -204,6 +204,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 
 /* SPL SDMMC boot support */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
 
 #endif /* __CONFIG_H */
-- 
2.21.0

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[U-Boot] [RESEND PATCH v3 1/2] Makefile: Add target to generate hex output for combined spl and dtb

[Dalon Westergreen]

From: Dalon Westergreen 

Stratix10 requires a hex image of the spl plus spl devicetree offset to
the Stratix10 onchip memory located at SPL_TEXT_BASE.  This patch adds
a target to generate a hex file from the u-boot-spl binary including the
dtb offset at SPL_TEST_BASE.

Objcopy is used to convert the $(SPL_BIN).bin, which includes the spl
dtb, to a hex file.  the --change-address option is used to offset the
hex to SPL_TEXT_BASE as objcopy on the spl binary will not result in
a hex file appropriately offset at SPL_TEXT_BASE.

Signed-off-by: Dalon Westergreen 

---
Changes in v3:
 -> Cleanup commit message and better describe the problem being
resolved
 -> Remove extraneous hunk
 -> use SPL_BIN instead of u-boot-spl
Changes in v2:
 -> Move spl hex file generation to SPL Makefile
 -> Create hexfile from $(SPL_BIN).bin which will include the dtb
ifneq(build_dtb,)
---
 Makefile | 8 +++-
 scripts/Makefile.spl | 7 +++
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index 1d9ade948b..0bc9d1589f 100644
--- a/Makefile
+++ b/Makefile
@@ -1152,11 +1152,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R 
.resetvec)
 
-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
-
-spl/u-boot-spl.hex: spl/u-boot-spl FORCE
-   $(call if_changed,objcopy)
-
 binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
@@ -1756,6 +1751,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl
@:
$(SPL_SIZE_CHECK)
 
+spl/u-boot-spl.hex: spl/u-boot-spl
+   @:
+
 spl/u-boot-spl: tools prepare \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7af6b120b6..551002194e 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -216,6 +216,8 @@ ifneq 
($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),)
 ALL-y  += $(obj)/$(SPL_BIN).sfp
 endif
 
+ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex
+
 ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 
@@ -363,6 +365,11 @@ endif
 $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
 
+OBJCOPYFLAGS_$(SPL_BIN).hex := -I binary -O ihex 
--change-address=$(CONFIG_SPL_TEXT_BASE)
+
+$(obj)/$(SPL_BIN).hex: $(obj)/$(SPL_BIN).bin FORCE
+   $(call if_changed,objcopy)
+
 quiet_cmd_mksunxiboot = MKSUNXI $@
 cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
-- 
2.21.0

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[U-Boot] [RESEND PATCH] ARM: socfpga: update CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot.img

[Dalon Westergreen]

From: Dalon Westergreen 

Bring cyclone5 / arria5 / arria10 in line with convention and use
u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME.

Signed-off-by: Dalon Westergreen 
---
 include/configs/socfpga_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d1034ac280..36b0ed5459 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -203,7 +203,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #endif
 #else
-- 
2.21.0

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[U-Boot] [RESEND PATCH v3 1/2] Makefile: Add target to generate hex output for combined spl and dtb

[Dalon Westergreen]

From: Dalon Westergreen 

Stratix10 requires a hex image of the spl plus spl devicetree offset to
the Stratix10 onchip memory located at SPL_TEXT_BASE.  This patch adds
a target to generate a hex file from the u-boot-spl binary including the
dtb offset at SPL_TEST_BASE.

Objcopy is used to convert the $(SPL_BIN).bin, which includes the spl
dtb, to a hex file.  the --change-address option is used to offset the
hex to SPL_TEXT_BASE as objcopy on the spl binary will not result in
a hex file appropriately offset at SPL_TEXT_BASE.

Signed-off-by: Dalon Westergreen 

---
Changes in v3:
 -> Cleanup commit message and better describe the problem being
resolved
 -> Remove extraneous hunk
 -> use SPL_BIN instead of u-boot-spl
Changes in v2:
 -> Move spl hex file generation to SPL Makefile
 -> Create hexfile from $(SPL_BIN).bin which will include the dtb
ifneq(build_dtb,)
---
 Makefile | 8 +++-
 scripts/Makefile.spl | 7 +++
 2 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index 8513db94e3..aa5c0746f0 100644
--- a/Makefile
+++ b/Makefile
@@ -1129,11 +1129,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R 
.resetvec)
 
-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
-
-spl/u-boot-spl.hex: spl/u-boot-spl FORCE
-   $(call if_changed,objcopy)
-
 binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
@@ -1715,6 +1710,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl
@:
$(SPL_SIZE_CHECK)
 
+spl/u-boot-spl.hex: spl/u-boot-spl
+   @:
+
 spl/u-boot-spl: tools prepare \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7af6b120b6..551002194e 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -216,6 +216,8 @@ ifneq 
($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),)
 ALL-y  += $(obj)/$(SPL_BIN).sfp
 endif
 
+ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex
+
 ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 
@@ -363,6 +365,11 @@ endif
 $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
 
+OBJCOPYFLAGS_$(SPL_BIN).hex := -I binary -O ihex 
--change-address=$(CONFIG_SPL_TEXT_BASE)
+
+$(obj)/$(SPL_BIN).hex: $(obj)/$(SPL_BIN).bin FORCE
+   $(call if_changed,objcopy)
+
 quiet_cmd_mksunxiboot = MKSUNXI $@
 cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
-- 
2.21.0

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[U-Boot] [RESEND PATCH v3 2/2] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED

[Dalon Westergreen]

From: Dalon Westergreen 

CONFIG_OF_EMBED was primarily enabled to support the stratix10
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Dalon Westergreen 

---
Changes in v3:
 -> Revert to u-boot.img for SPL payload name
Changes in v2:
 -> Change CONFIG_SPL_TARGET back to u-boot-spl.hex
---
 configs/socfpga_stratix10_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index fbab388b43..f27180385d 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.21.0

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[U-Boot] [PATCH] fpga: arria10: Fix error in fpga pin configuration

[Dalon Westergreen]

From: Dalon Westergreen 

Pin configuration of the FPGA devicetree block should be done
after core configuration in the arria10 fpga driver.  This fix
corrects the check of status, and ensures that the fpga pin mux
is configured on correct configuration of the core fpga image.

Signed-off-by: Dalon Westergreen 
---
 drivers/fpga/socfpga_arria10.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 285280e507..5fb9d6a191 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -936,10 +936,11 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, 
size_t rbf_size)
fpgamgr_program_write(rbf_data, rbf_size);
 
status = fpgamgr_program_finish();
-   if (status) {
-   config_pins(gd->fdt_blob, "fpga");
-   puts("FPGA: Enter user mode.\n");
-   }
+   if (status)
+   return status;
+
+   config_pins(gd->fdt_blob, "fpga");
+   puts("FPGA: Enter user mode.\n");
 
return status;
 }
-- 
2.21.0

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[U-Boot] [PATCH] ARM: socfpga: update CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot.img

[Dalon Westergreen]

From: Dalon Westergreen 

Bring cyclone5 / arria5 / arria10 in line with convention and use
u-boot.img as CONFIG_SPL_FS_LOAD_PAYLOAD_NAME.

Signed-off-by: Dalon Westergreen 
---
 include/configs/socfpga_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index d1034ac280..36b0ed5459 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -203,7 +203,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
 #endif
 #else
-- 
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[U-Boot] [PATCH v3 2/2] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED

[Dalon Westergreen]

From: Dalon Westergreen 

CONFIG_OF_EMBED was primarily enabled to support the stratix10
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Dalon Westergreen 

---
Changes in v3:
 -> Revert to u-boot.img for SPL payload name
Changes in v2:
 -> Change CONFIG_SPL_TARGET back to u-boot-spl.hex
---
 configs/socfpga_stratix10_defconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index fbab388b43..f27180385d 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
-- 
2.21.0

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[U-Boot] [PATCH v3 1/2] Makefile: Add target to generate hex output for combined spl and dtb

[Dalon Westergreen]

From: Dalon Westergreen 

Stratix10 requires a hex image of the spl plus spl devicetree offset to
the Stratix10 onchip memory located at SPL_TEXT_BASE.  This patch adds
a target to generate a hex file from the u-boot-spl binary including the
dtb offset at SPL_TEST_BASE.

Objcopy is used to convert the $(SPL_BIN).bin, which includes the spl
dtb, to a hex file.  the --change-address option is used to offset the
hex to SPL_TEXT_BASE as objcopy on the spl binary will not result in
a hex file appropriately offset at SPL_TEXT_BASE.

Signed-off-by: Dalon Westergreen 

---
Changes in v3:
 -> Cleanup commit message and better describe the problem being
resolved
 -> Remove extraneous hunk
 -> use SPL_BIN instead of u-boot-spl
Changes in v2:
 -> Move spl hex file generation to SPL Makefile
 -> Create hexfile from $(SPL_BIN).bin which will include the dtb
ifneq(build_dtb,)
---
 Makefile | 9 -
 scripts/Makefile.spl | 7 +++
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index 07106138e9..12e36ebb72 100644
--- a/Makefile
+++ b/Makefile
@@ -1124,11 +1124,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R 
.resetvec)
 
-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
-
-spl/u-boot-spl.hex: spl/u-boot-spl FORCE
-   $(call if_changed,objcopy)
-
 binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
@@ -1707,6 +1702,10 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
 
 spl/u-boot-spl.bin: spl/u-boot-spl
@:
+
+spl/u-boot-spl.hex: spl/u-boot-spl
+   @:
+
 spl/u-boot-spl: tools prepare \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7af6b120b6..551002194e 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -216,6 +216,8 @@ ifneq 
($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),)
 ALL-y  += $(obj)/$(SPL_BIN).sfp
 endif
 
+ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex
+
 ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 
@@ -363,6 +365,11 @@ endif
 $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
 
+OBJCOPYFLAGS_$(SPL_BIN).hex := -I binary -O ihex 
--change-address=$(CONFIG_SPL_TEXT_BASE)
+
+$(obj)/$(SPL_BIN).hex: $(obj)/$(SPL_BIN).bin FORCE
+   $(call if_changed,objcopy)
+
 quiet_cmd_mksunxiboot = MKSUNXI $@
 cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
-- 
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[U-Boot] [PATCH v2 2/2] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED

[Dalon Westergreen]

From: Dalon Westergreen 

CONFIG_OF_EMBED was primarily enabled to support the stratix10
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Dalon Westergreen 

---
Changes in v2:
 -> Change CONFIG_SPL_TARGET back to u-boot-spl.hex
---
 configs/socfpga_stratix10_defconfig   | 1 -
 include/configs/socfpga_stratix10_socdk.h | 2 +-
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index fbab388b43..f27180385d 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index 39d757d737..66855ff0d8 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -210,6 +210,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 
 /* SPL SDMMC boot support */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
 
 #endif /* __CONFIG_H */
-- 
2.21.0

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[U-Boot] [PATCH v2 1/2] Makefile: Add target to generate hex output for combined spl and dtb

[Dalon Westergreen]

From: Dalon Westergreen 

Some architectures, Stratix10, require a hex formatted spl that combines
the spl image and dtb.  This adds a target to create said hex file with
and offset of SPL_TEXT_BASE.

Signed-off-by: Dalon Westergreen 

---
Changes in v2:
 -> Move spl hex file generation to SPL Makefile
 -> Create hexfile from $(SPL_BIN).bin which will include the dtb
ifneq(build_dtb,)
---
 Makefile | 9 -
 scripts/Makefile.spl | 8 
 2 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/Makefile b/Makefile
index 07106138e9..12e36ebb72 100644
--- a/Makefile
+++ b/Makefile
@@ -1124,11 +1124,6 @@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R 
.resetvec)
 
-OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
-
-spl/u-boot-spl.hex: spl/u-boot-spl FORCE
-   $(call if_changed,objcopy)
-
 binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
@@ -1707,6 +1702,10 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
 
 spl/u-boot-spl.bin: spl/u-boot-spl
@:
+
+spl/u-boot-spl.hex: spl/u-boot-spl
+   @:
+
 spl/u-boot-spl: tools prepare \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7af6b120b6..419bb6e222 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -216,6 +216,8 @@ ifneq 
($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),)
 ALL-y  += $(obj)/$(SPL_BIN).sfp
 endif
 
+ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex
+
 ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 
@@ -363,6 +365,11 @@ endif
 $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
$(call if_changed,mkimage)
 
+OBJCOPYFLAGS_$(SPL_BIN).hex := -I binary -O ihex 
--change-address=$(CONFIG_SPL_TEXT_BASE)
+
+$(obj)/$(SPL_BIN).hex: $(obj)/u-boot-spl.bin FORCE
+   $(call if_changed,objcopy)
+
 quiet_cmd_mksunxiboot = MKSUNXI $@
 cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
@@ -463,3 +470,4 @@ ifdef CONFIG_ARCH_K3
 tispl.bin: $(obj)/u-boot-spl-nodtb.bin $(SHRUNK_ARCH_DTB) $(SPL_ITS) FORCE
$(call if_changed,mkfitimage)
 endif
+
-- 
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[U-Boot] [PATCH 2/2] ARM: socfpga: stratix10: Remove CONFIG_OF_EMBED

[Dalon Westergreen]

From: Dalon Westergreen 

CONFIG_OF_EMBED was primarily enabled to support the stratix10
spl hex file requirements.  Since this option now produces a
warning during build, and the spl hex can be created using
alternate methods, CONFIG_OF_EMBED is no longer needed.

Signed-off-by: Dalon Westergreen 
---
 configs/socfpga_stratix10_defconfig   | 1 -
 include/configs/socfpga_stratix10_socdk.h | 4 ++--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index 9e6d582ee3..346175fd7a 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -26,7 +26,6 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
-CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index 0e73239f56..813b96b028 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -200,7 +200,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
  * 0x8000_ .. End of SDRAM_1 (assume 2GB)
  *
  */
-#define CONFIG_SPL_TARGET  "spl/u-boot-spl.hex"
+#define CONFIG_SPL_TARGET  "spl/u-boot-spl-dtb.hex"
 #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZE
 #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
@@ -214,6 +214,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 
 /* SPL SDMMC boot support */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
 
 #endif /* __CONFIG_H */
-- 
2.20.1

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[U-Boot] [PATCH 1/2] Makefile: Add target to generate hex output for combined spl and dtb

[Dalon Westergreen]

From: Dalon Westergreen 

Some architectures, Stratix10, require a hex formatted spl that combines
the spl image and dtb.  This adds a target to create said hex file with
and offset of SPL_TEXT_BASE.

Signed-off-by: Dalon Westergreen 
---
 Makefile | 9 +
 1 file changed, 9 insertions(+)

diff --git a/Makefile b/Makefile
index c52a33b403..ecba06ffce 100644
--- a/Makefile
+++ b/Makefile
@@ -1074,6 +1074,11 @@ OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
 spl/u-boot-spl.hex: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
 
+OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex 
--change-address=$(CONFIG_SPL_TEXT_BASE)
+
+spl/u-boot-spl-dtb.hex: spl/u-boot-spl-dtb.bin FORCE
+   $(call if_changed,objcopy)
+
 binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
@@ -1643,6 +1648,10 @@ u-boot.lds: $(LDSCRIPT) prepare FORCE
 
 spl/u-boot-spl.bin: spl/u-boot-spl
@:
+
+spl/u-boot-spl-dtb.bin: spl/u-boot-spl
+   @:
+
 spl/u-boot-spl: tools prepare \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_SPL_OF_PLATDATA),dts/dt.dtb) \
$(if 
$(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_TPL_OF_PLATDATA),dts/dt.dtb)
-- 
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[U-Boot] [PATCH] ARM: socfpga: Build sfp image only for Gen5 and Arria10 devices

[Dalon Westergreen]

From: Dalon Westergreen 

The sfp file is only valid for Gen5 (Cyclone5 & Arria5) and Arria10
devices.  The file should only be built for these devices.

Signed-off-by: Dalon Westergreen 
---
 Kconfig  | 3 ++-
 scripts/Makefile.spl | 6 +-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/Kconfig b/Kconfig
index 512c7beb89..305b265ed7 100644
--- a/Kconfig
+++ b/Kconfig
@@ -226,7 +226,8 @@ config BUILD_ROM
 
 config BUILD_TARGET
string "Build target special images"
-   default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
+   default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
+   default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 9d5921606e..592c5dfe57 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -212,7 +212,11 @@ ifdef CONFIG_SAMSUNG
 ALL-y  += $(obj)/$(BOARD)-spl.bin
 endif
 
-ifdef CONFIG_ARCH_SOCFPGA
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+ALL-y  += $(obj)/$(SPL_BIN).sfp
+endif
+
+ifdef CONFIG_TARGET_SOCFPGA_GEN5
 ALL-y  += $(obj)/$(SPL_BIN).sfp
 endif
 
-- 
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[U-Boot] [PATCH v2] ARM: socfpga: Build sfp image only for Gen5 and Arria10 devices

[Dalon Westergreen]

From: Dalon Westergreen 

The sfp file is only valid for Gen5 (Cyclone5 & Arria5) and Arria10
devices.  The file should only be built for these devices.

Signed-off-by: Dalon Westergreen 
---
Changes from v1:
 -> Remove duplicate entries for GEN5 and ARRIA10
---
 Kconfig  | 3 ++-
 scripts/Makefile.spl | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/Kconfig b/Kconfig
index 512c7beb89..305b265ed7 100644
--- a/Kconfig
+++ b/Kconfig
@@ -226,7 +226,8 @@ config BUILD_ROM
 
 config BUILD_TARGET
string "Build target special images"
-   default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
+   default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10
+   default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 9d5921606e..54b160d72b 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -212,7 +212,7 @@ ifdef CONFIG_SAMSUNG
 ALL-y  += $(obj)/$(BOARD)-spl.bin
 endif
 
-ifdef CONFIG_ARCH_SOCFPGA
+ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),)
 ALL-y  += $(obj)/$(SPL_BIN).sfp
 endif
 
-- 
2.20.1

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[U-Boot] [Patch v3] socfpga: clean up sfp generation

[Dalon Westergreen]

From: Dalon Westergreen 

Move the sfp file generation entirely to the root Makefile.  This
means that the u-boot-spl.sfp will only be generated when required
and only for the socfpga variants that require it.

sfp generation is now entirely controlled by CONFIG_BUILD_TARGET
being set to either spl/u-boot-spl.sfp or more likely
u-boot-with-spl.sfp

Signed-off-by: Dalon Westergreen 

---
v3:
  -> Change ifdef to ifneq
  -> Fix error, should not use $(SPL_BIN) as it was not defined
 in Makefile
v2:
  -> condense changes to 1 patch to avoid breaking git bisect
---
 Makefile | 11 ---
 scripts/Makefile.spl | 12 
 2 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/Makefile b/Makefile
index aadd1ec8c6..5f03e534a5 100644
--- a/Makefile
+++ b/Makefile
@@ -1207,6 +1207,14 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
 
 ifneq ($(CONFIG_ARCH_SOCFPGA),)
+ifneq ($(CONFIG_TARGET_SOCFPGA_ARRIA10),)
+MKIMAGEFLAGS_u-boot-spl.sfp = -T socfpgaimage_v1
+else
+MKIMAGEFLAGS_u-boot-spl.sfp = -T socfpgaimage
+endif
+spl/u-boot-spl.sfp: spl/u-boot-spl.bin FORCE
+   $(call if_changed,mkimage)
+
 quiet_cmd_socboot = SOCBOOT $@
 cmd_socboot = cat  spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
@@ -1542,9 +1550,6 @@ spl/sunxi-spl.bin: spl/u-boot-spl
 spl/sunxi-spl-with-ecc.bin: spl/sunxi-spl.bin
@:
 
-spl/u-boot-spl.sfp: spl/u-boot-spl
-   @:
-
 spl/boot.bin: spl/u-boot-spl
@:
 
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7416abec62..a58113cee2 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -198,10 +198,6 @@ ifdef CONFIG_SAMSUNG
 ALL-y  += $(obj)/$(BOARD)-spl.bin
 endif
 
-ifdef CONFIG_ARCH_SOCFPGA
-ALL-y  += $(obj)/$(SPL_BIN).sfp
-endif
-
 ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 
@@ -324,14 +320,6 @@ LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
 endif
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
-MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1
-else
-MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
-endif
-$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
-   $(call if_changed,mkimage)
-
 quiet_cmd_mksunxiboot = MKSUNXI $@
 cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
-- 
2.17.2

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[U-Boot] [PATCH v2] socfpga: clean up sfp generation

[Dalon Westergreen]

From: Dalon Westergreen 

Move the sfp file generation entirely to the root Makefile.  This
means that the u-boot-spl.sfp will only be generated when required
and only for the socfpga variants that require it.

sfp generation is now entirely controlled by CONFIG_BUILD_TARGET
being set to either spl/u-boot-spl.sfp or more likely
u-boot-with-spl.sfp

Signed-off-by: Dalon Westergreen 

---
v2:
  -> condense changes to 1 patch to avoid breaking git bisect
---
 Makefile | 11 ---
 scripts/Makefile.spl | 12 
 2 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/Makefile b/Makefile
index aadd1ec8c6..16ce14d071 100644
--- a/Makefile
+++ b/Makefile
@@ -1207,6 +1207,14 @@ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
 
 ifneq ($(CONFIG_ARCH_SOCFPGA),)
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1
+else
+MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
+endif
+spl/u-boot-spl.sfp: spl/u-boot-spl.bin FORCE
+   $(call if_changed,mkimage)
+
 quiet_cmd_socboot = SOCBOOT $@
 cmd_socboot = cat  spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
@@ -1542,9 +1550,6 @@ spl/sunxi-spl.bin: spl/u-boot-spl
 spl/sunxi-spl-with-ecc.bin: spl/sunxi-spl.bin
@:
 
-spl/u-boot-spl.sfp: spl/u-boot-spl
-   @:
-
 spl/boot.bin: spl/u-boot-spl
@:
 
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 7416abec62..a58113cee2 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -198,10 +198,6 @@ ifdef CONFIG_SAMSUNG
 ALL-y  += $(obj)/$(BOARD)-spl.bin
 endif
 
-ifdef CONFIG_ARCH_SOCFPGA
-ALL-y  += $(obj)/$(SPL_BIN).sfp
-endif
-
 ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 
@@ -324,14 +320,6 @@ LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
 endif
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
-MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1
-else
-MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
-endif
-$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
-   $(call if_changed,mkimage)
-
 quiet_cmd_mksunxiboot = MKSUNXI $@
 cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
-- 
2.17.2

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[U-Boot] [PATCH v3] arm: socfpga: stratix10: Add CONFIG_OF_EMBED

[Dalon Westergreen]

The dtb should be embedded in the u-boot-spl image so that
the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it.

This also affects the main u-boot image, so adjust
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot.img which now
also includes the dtb.

Signed-off-by: Dalon Westergreen 
---
v2:
  -> use savedefconfig output for new defconfig
  -> fix typo in commit message
---
 configs/socfpga_stratix10_defconfig   | 1 +
 include/configs/socfpga_stratix10_socdk.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index a8b6f92b3d..d03fe60361 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -26,6 +26,7 @@ CONFIG_CMD_CACHE=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_EMBED=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_NET_RANDOM_ETHADDR=y
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index 91315a0031..e190b3d988 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -216,6 +216,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 
 /* SPL SDMMC boot support */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
 #endif /* __CONFIG_H */
-- 
2.17.1

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[U-Boot] [Patch v3] socfpga: stratix10: fix sdram_calculate_size

[Dalon Westergreen]

Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.

Signed-off-by: Dalon Westergreen 
---
v3: Fix commit message
v2: Move function type to phys_size_t to match gd->ram_size
---
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 2 +-
 drivers/ddr/altera/sdram_s10.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index 91bfc0e5ec..ca68594445 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -7,7 +7,7 @@
 #ifndef_SDRAM_S10_H_
 #define_SDRAM_S10_H_
 
-unsigned long sdram_calculate_size(void);
+phys_size_t sdram_calculate_size(void);
 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
 int sdram_calibration_full(void);
 
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 48f4f47b14..a48567c109 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -371,11 +371,11 @@ int sdram_mmr_init_full(unsigned int unused)
  * Calculate SDRAM device size based on SDRAM controller parameters.
  * Size is specified in bytes.
  */
-unsigned long sdram_calculate_size(void)
+phys_size_t sdram_calculate_size(void)
 {
u32 dramaddrw = hmc_readl(DRAMADDRW);
 
-   u32 size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+   phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
-- 
2.17.1

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[U-Boot] [Patch v2] socfpga: stratix10: fix sdram_calculate_size

[Dalon Westergreen]

Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.

v2:
  -> Move function type to phys_size_t to match gd->ram_size

Signed-off-by: Dalon Westergreen 
---
 arch/arm/mach-socfpga/include/mach/sdram_s10.h | 2 +-
 drivers/ddr/altera/sdram_s10.c | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h 
b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
index 91bfc0e5ec..ca68594445 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_s10.h
@@ -7,7 +7,7 @@
 #ifndef_SDRAM_S10_H_
 #define_SDRAM_S10_H_
 
-unsigned long sdram_calculate_size(void);
+phys_size_t sdram_calculate_size(void);
 int sdram_mmr_init_full(unsigned int sdr_phy_reg);
 int sdram_calibration_full(void);
 
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 48f4f47b14..a48567c109 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -371,11 +371,11 @@ int sdram_mmr_init_full(unsigned int unused)
  * Calculate SDRAM device size based on SDRAM controller parameters.
  * Size is specified in bytes.
  */
-unsigned long sdram_calculate_size(void)
+phys_size_t sdram_calculate_size(void)
 {
u32 dramaddrw = hmc_readl(DRAMADDRW);
 
-   u32 size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+   phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
-- 
2.17.1

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[U-Boot] [PATCH] socfpga: stratix10: fix sdram_calculate_size

[Dalon Westergreen]

Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.

Signed-off-by: Dalon Westergreen 
---
 drivers/ddr/altera/sdram_s10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 48f4f47b14..dad0147b64 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -375,7 +375,7 @@ unsigned long sdram_calculate_size(void)
 {
u32 dramaddrw = hmc_readl(DRAMADDRW);
 
-   u32 size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+   unsigned long  size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
-- 
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[U-Boot] [PATCH 3/3] socfpga: common: add CONFIG_SPL_TARGET to gen5 and arria10 socfpga header

[Dalon Westergreen]

Add CONFIG_SPL_TARGET "u-boot-with-spl.sfp" to common header
to generate the required u-boot-spl and u-boot combined
image.

Signed-off-by: Dalon Westergreen 
---
 include/configs/socfpga_common.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 2330143cf1..4777b4522d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -239,6 +239,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * 0xFFEz_ .. Malloc area (grows up to top)
  * 0xFFE3_ .. End of SRAM (top)
  */
+#define CONFIG_SPL_TARGET  "u-boot-with-spl.sfp"
 #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZE
 
-- 
2.17.1

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[U-Boot] [PATCH 1/3] spl: socfpga: remove sfp generation

[Dalon Westergreen]

In preparation to move to using CONFIG_SPL_TARGET,
remove sfp generation targets.

Signed-off-by: Dalon Westergreen 
---
 scripts/Makefile.spl | 12 
 1 file changed, 12 deletions(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 252f13826d..9314365aab 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -187,10 +187,6 @@ ifdef CONFIG_SAMSUNG
 ALL-y  += $(obj)/$(BOARD)-spl.bin
 endif
 
-ifdef CONFIG_ARCH_SOCFPGA
-ALL-y  += $(obj)/$(SPL_BIN).sfp
-endif
-
 ifdef CONFIG_ARCH_SUNXI
 ALL-y  += $(obj)/sunxi-spl.bin
 
@@ -313,14 +309,6 @@ LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)
 endif
 endif
 
-ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
-MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1
-else
-MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
-endif
-$(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE
-   $(call if_changed,mkimage)
-
 quiet_cmd_mksunxiboot = MKSUNXI $@
 cmd_mksunxiboot = $(objtree)/tools/mksunxiboot \
--default-dt $(CONFIG_DEFAULT_DEVICE_TREE) $< $@
-- 
2.17.1

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[U-Boot] [PATCH 2/3] socfpga: Add sfp generation targets

[Dalon Westergreen]

Some SOCFPGA platforms require a header be added to
u-boot-spl and a combined spl / u-boot image.  The
combined image consists of 4 replicated u-boot-spl
images with the afore mentioned header, and a u-boot
image cat'ed together.

Signed-off-by: Dalon Westergreen 
---
 Makefile | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 133d7ac773..6c93c6c129 100644
--- a/Makefile
+++ b/Makefile
@@ -1198,14 +1198,12 @@ OBJCOPYFLAGS_u-boot.spr = -I binary -O binary 
--pad-to=$(CONFIG_SPL_PAD_TO) \
 u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE
$(call if_changed,pad_cat)
 
-ifneq ($(CONFIG_ARCH_SOCFPGA),)
 quiet_cmd_socboot = SOCBOOT $@
 cmd_socboot = cat  spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
spl/u-boot-spl.sfp spl/u-boot-spl.sfp   \
u-boot.img > $@ || rm -f $@
 u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
$(call if_changed,socboot)
-endif
 
 # x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
 # reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
@@ -1518,8 +1516,13 @@ spl/sunxi-spl.bin: spl/u-boot-spl
 spl/sunxi-spl-with-ecc.bin: spl/sunxi-spl.bin
@:
 
-spl/u-boot-spl.sfp: spl/u-boot-spl
-   @:
+ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
+MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1
+else
+MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage
+endif
+spl/u-boot-spl.sfp: spl/u-boot-spl.bin FORCE
+   $(call if_changed,mkimage)
 
 spl/boot.bin: spl/u-boot-spl
@:
-- 
2.17.1

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[U-Boot] [PATCH 0/3] socfpga: clean up sfp generation

[Dalon Westergreen]

Move gen5 and arria10 to use CONFIG_SPL_TARGET to
specify the required SPL output.

Dalon Westergreen (3):
  spl: socfpga: remove sfp generation
  socfpga: Add sfp generation targets
  socfpga: common: add CONFIG_SPL_TARGET to gen5 and arria10 socfpga
header

 Makefile | 11 +++
 include/configs/socfpga_common.h |  1 +
 scripts/Makefile.spl | 12 
 3 files changed, 8 insertions(+), 16 deletions(-)

-- 
2.17.1

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[U-Boot] [PATCH 2/3] arm: socfpga: stratix10: add CONFIG_SPL_TARGET

[Dalon Westergreen]

Stratix10 combines the u-boot-spl image into the fpga configuration
bitstream so that the SDM can load the processors memory.  This
process requires a hex format of the u-boot-spl image.
CONFIG_SPL_TARGET is set to "spl/u-boot-spl.hex"

Signed-off-by: Dalon Westergreen 
---
 include/configs/socfpga_stratix10_socdk.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index b58f478004..91315a0031 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -202,6 +202,7 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
  * 0x8000_ .. End of SDRAM_1 (assume 2GB)
  *
  */
+#define CONFIG_SPL_TARGET  "spl/u-boot-spl.hex"
 #define CONFIG_SPL_TEXT_BASE   CONFIG_SYS_INIT_RAM_ADDR
 #define CONFIG_SPL_MAX_SIZECONFIG_SYS_INIT_RAM_SIZE
 #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
-- 
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[U-Boot] [PATCH 3/3] arm; socfpga: stratix10: Add CONFIG_OF_EMBED

[Dalon Westergreen]

The dtb should be embedded in the u-boot-spl image so that
the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it.

This also affects the main u-boot image, so adjust
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot,img which now
also includes the dtb.

Signed-off-by: Dalon Westergreen 
---
 configs/socfpga_stratix10_defconfig   | 1 +
 include/configs/socfpga_stratix10_socdk.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index c27985ad43..b6d804f38e 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -56,3 +56,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_OF_EMBED=y
diff --git a/include/configs/socfpga_stratix10_socdk.h 
b/include/configs/socfpga_stratix10_socdk.h
index 91315a0031..e190b3d988 100644
--- a/include/configs/socfpga_stratix10_socdk.h
+++ b/include/configs/socfpga_stratix10_socdk.h
@@ -216,6 +216,6 @@ unsigned int cm_get_l4_sys_free_clk_hz(void);
 
 /* SPL SDMMC boot support */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
-#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot.img"
 
 #endif /* __CONFIG_H */
-- 
2.17.1

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[U-Boot] [PATCH 1/3] common: add spl/u-boot-spl.hex target

[Dalon Westergreen]

Some devices, namely Intel's stratix10 SoC, require u-boot-spl in
a hex format.  This patch adds spl/u-boot-spl.hex as a possible
target.

Signed-off-by: Dalon Westergreen 
---
 Makefile | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Makefile b/Makefile
index f30dd8e9b7..133d7ac773 100644
--- a/Makefile
+++ b/Makefile
@@ -985,6 +985,11 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
 OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
 
+OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
+
+spl/u-boot-spl.hex: spl/u-boot-spl FORCE
+   $(call if_changed,objcopy)
+
 binary_size_check: u-boot-nodtb.bin FORCE
@file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \
map_size=$(shell cat u-boot.map | \
-- 
2.17.1

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[U-Boot] [PATCH 0/3] add optional hex output of u-boot-spl

[Dalon Westergreen]

This patch set adds a possible hex output of the
u-boot-spl elf and enables said output for the
Intel Stratix10 device.  Stratix10 requires a hex
output of the elf for creating the secure device manager
configuration bitstream.

Dalon Westergreen (3):
  common: add spl/u-boot-spl.hex target
  arm: socfpga: stratix10: add CONFIG_SPL_TARGET
  arm; socfpga: stratix10: Add CONFIG_OF_EMBED

 Makefile  | 5 +
 configs/socfpga_stratix10_defconfig   | 1 +
 include/configs/socfpga_stratix10_socdk.h | 3 ++-
 3 files changed, 8 insertions(+), 1 deletion(-)

-- 
2.17.1

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[U-Boot] [PATCH v2 1/2] spl: socfpga: only gen5 devices and arria10 require sfp image

[Dalon Westergreen]

Only the Cyclone5/Arria5 and Arria10 devices require the sfp
formated image for booting. This path ensures that the file is
only generated for those devices.

Signed-off-by: Dalon Westergreen 
---
 scripts/Makefile.spl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 252f13826d..76d08fd92b 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -188,7 +188,8 @@ ALL-y   += $(obj)/$(BOARD)-spl.bin
 endif
 
 ifdef CONFIG_ARCH_SOCFPGA
-ALL-y  += $(obj)/$(SPL_BIN).sfp
+ALL-$(CONFIG_TARGET_SOCFPGA_GEN5)  += $(obj)/$(SPL_BIN).sfp
+ALL-$(CONFIG_TARGET_SOCFPGA_ARRIA10)   += $(obj)/$(SPL_BIN).sfp
 endif
 
 ifdef CONFIG_ARCH_SUNXI
-- 
2.17.1

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[U-Boot] [PATCH v2 2/2] spl: socfpga: stratix10: add hex file output for spl image

[Dalon Westergreen]

Stratix10 requires a hex image of the spl for boot.  The hex
image is added to the FPGA configuration image and loaded to
the processor memory by the configuration engine.

v2:
  -> add CONFIG_OF_EMBED to include dtb in elf
  -> generate hex from elf source

Signed-off-by: Dalon Westergreen 
---
 configs/socfpga_stratix10_defconfig | 1 +
 scripts/Makefile.spl| 6 ++
 2 files changed, 7 insertions(+)

diff --git a/configs/socfpga_stratix10_defconfig 
b/configs/socfpga_stratix10_defconfig
index dceadff439..17cc732cbe 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -56,3 +56,4 @@ CONFIG_DM_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_STORAGE=y
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_OF_EMBED=y
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 76d08fd92b..b09bd40b2a 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -190,6 +190,7 @@ endif
 ifdef CONFIG_ARCH_SOCFPGA
 ALL-$(CONFIG_TARGET_SOCFPGA_GEN5)  += $(obj)/$(SPL_BIN).sfp
 ALL-$(CONFIG_TARGET_SOCFPGA_ARRIA10)   += $(obj)/$(SPL_BIN).sfp
+ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex
 endif
 
 ifdef CONFIG_ARCH_SUNXI
@@ -299,6 +300,11 @@ OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j 
.start16 -j .resetvec
 $(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE
$(call if_changed,objcopy)
 
+OBJCOPYFLAGS_$(SPL_BIN).hex = -O ihex
+
+$(obj)/$(SPL_BIN).hex: $(obj)/$(SPL_BIN) FORCE
+   $(call if_changed,objcopy)
+
 LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
 
 # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
-- 
2.17.1

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[U-Boot] [PATCH 1/2] spl: socfpga: only gen5 devices and arria10 require sfp image

[Dalon Westergreen]

Only the Cyclone5/Arria5 and Arria10 devices require the sfp
formated image for booting. This path ensures that the file is
only generated for those devices.

Signed-off-by: Dalon Westergreen 
---
 scripts/Makefile.spl | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 252f13826d..76d08fd92b 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -188,7 +188,8 @@ ALL-y   += $(obj)/$(BOARD)-spl.bin
 endif
 
 ifdef CONFIG_ARCH_SOCFPGA
-ALL-y  += $(obj)/$(SPL_BIN).sfp
+ALL-$(CONFIG_TARGET_SOCFPGA_GEN5)  += $(obj)/$(SPL_BIN).sfp
+ALL-$(CONFIG_TARGET_SOCFPGA_ARRIA10)   += $(obj)/$(SPL_BIN).sfp
 endif
 
 ifdef CONFIG_ARCH_SUNXI
-- 
2.17.1

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[U-Boot] [PATCH 2/2] spl: socfpga: stratix10: add hex file output for spl image

[Dalon Westergreen]

Stratix10 requires a hex image of the spl for boot.  The hex
image is added to the FPGA configuration image and loaded to
the processor memory by the configuration engine.

Signed-off-by: Dalon Westergreen 
---
 scripts/Makefile.spl | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 76d08fd92b..c424f87e6e 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -190,6 +190,7 @@ endif
 ifdef CONFIG_ARCH_SOCFPGA
 ALL-$(CONFIG_TARGET_SOCFPGA_GEN5)  += $(obj)/$(SPL_BIN).sfp
 ALL-$(CONFIG_TARGET_SOCFPGA_ARRIA10)   += $(obj)/$(SPL_BIN).sfp
+ALL-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += $(obj)/$(SPL_BIN).hex
 endif
 
 ifdef CONFIG_ARCH_SUNXI
@@ -299,6 +300,15 @@ OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j 
.start16 -j .resetvec
 $(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE
$(call if_changed,objcopy)
 
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+OBJCOPYFLAGS_$(SPL_BIN).hex = -I binary -O ihex --change-addresses 0xffe0
+else
+OBJCOPYFLAGS_$(SPL_BIN).hex = -I binary -O ihex
+endif
+
+$(obj)/$(SPL_BIN).hex: $(obj)/$(SPL_BIN).bin FORCE
+   $(call if_changed,objcopy)
+
 LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL)
 
 # Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
-- 
2.17.1

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[U-Boot] [PATCH 0/2] socfpga: cleanup files generated for spl

[Dalon Westergreen]

These patches add a hex output of the spl image for Stratix10
devices, and remove the sfp mkimage output for Stratix10 devices.
In Stratix10, the spl image is added to the initial FPGA configuration
bitstream.  A hex file is needed to do this. 

Dalon Westergreen (2):
  spl: socfpga: only gen5 devices and arria10 require sfp image
  spl: socfpga: stratix10: add hex file output for spl image

 scripts/Makefile.spl | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

-- 
2.17.1

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Re: [U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Dalon Westergreen]

On Fri, 2017-04-21 at 15:31 +0200, Marek Vasut wrote:
> On 04/21/2017 03:17 PM, Dalon Westergreen wrote:
> > 
> > On Fri, 2017-04-21 at 14:17 +0200, Marek Vasut wrote:
> > > 
> > > On 04/21/2017 11:45 AM, Ley Foon Tan wrote:
> > > > 
> > > > 
> > > > On Fri, Apr 21, 2017 at 4:00 AM, Dalon Westergreen
> > > > <dalon.westergr...@linux.intel.com> wrote:
> > > > > 
> > > > > 
> > > > > On Thu, 2017-04-20 at 07:12 -0700, Dalon Westergreen wrote:
> > > > > > 
> > > > > > 
> > > > > > On Wed, 2017-04-19 at 23:58 -0500, Dinh Nguyen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On Wed, Apr 19, 2017 at 6:21 PM, Dalon Westergreen
> > > > > > > <dalon.westergr...@linux.intel.com> wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Wed, 2017-04-19 at 13:54 -0700, Dalon Westergreen wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > Really including Dalon
> > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dinguyen@ker
> > > > > > > > > > > nel.
> > > > > > > > > > > org>
> > > > > > > > > > > wrote:
> > > > > > > > > > > CC: Dalon Westergreen
> > > > > > > > > > > 
> > > > > > > > > > > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > Add SPL support for Arria 10.
> > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 

Re: [U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Dalon Westergreen]

On Fri, 2017-04-21 at 14:17 +0200, Marek Vasut wrote:
> On 04/21/2017 11:45 AM, Ley Foon Tan wrote:
> > 
> > On Fri, Apr 21, 2017 at 4:00 AM, Dalon Westergreen
> > <dalon.westergr...@linux.intel.com> wrote:
> > > 
> > > On Thu, 2017-04-20 at 07:12 -0700, Dalon Westergreen wrote:
> > > > 
> > > > On Wed, 2017-04-19 at 23:58 -0500, Dinh Nguyen wrote:
> > > > > 
> > > > > 
> > > > > On Wed, Apr 19, 2017 at 6:21 PM, Dalon Westergreen
> > > > > <dalon.westergr...@linux.intel.com> wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Wed, 2017-04-19 at 13:54 -0700, Dalon Westergreen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > Really including Dalon
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dinguyen@kernel.
> > > > > > > > > org>
> > > > > > > > > wrote:
> > > > > > > > > CC: Dalon Westergreen
> > > > > > > > > 
> > > > > > > > > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > Add SPL support for Arria 10.
> > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > 
> > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@inte
> > > > > > > > > > > > > > > l.com>
> > > > > > > > > > > > > > > Signed-off-by: Ley Foon Tan <ley.foon@intel.co
> > > > > > > > > > > > > > > m>
> > > > > > > > > > > ---
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > > > > > > 
> > > > > > > > > >

Re: [U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Dalon Westergreen]

On Thu, 2017-04-20 at 07:12 -0700, Dalon Westergreen wrote:
> On Wed, 2017-04-19 at 23:58 -0500, Dinh Nguyen wrote:
> > 
> > On Wed, Apr 19, 2017 at 6:21 PM, Dalon Westergreen
> > <dalon.westergr...@linux.intel.com> wrote:
> > > 
> > > 
> > > On Wed, 2017-04-19 at 13:54 -0700, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > Really including Dalon
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dingu...@kernel.org>
> > > > > > wrote:
> > > > > > CC: Dalon Westergreen
> > > > > > 
> > > > > > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > Add SPL support for Arria 10.
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > > > > > > > > > > > Signed-off-by: Ley Foon Tan <ley.foon@intel.com>
> > > > > > > > ---
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > > 
> > > > > > > > > > > >  arch/arm/mach-socfpga/spl.c | 72
> > > > +
> > > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > >  1 file changed, 67 insertions(+), 5 deletions(-)
> > > > > > > > 
> > > > > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > > > > > > > socfpga/spl.c
> > > > > > > > index 0064fc8..f4a3cdd 100644
> > > > > > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > > > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > > > > > @@ -19,23 +19,32 @@
> > > > > > > >  #include 
> > > > > > > >  #include 
> > > > > > > >  #include 
> > > > > > > > +#include 
> > > > > > > > +#include 
> > > > > > > > +#include 
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > > > +#include 
> > > > > > > > +#endif
> > > > > > > > 
> > > > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > > > > 
> > > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > >

Re: [U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Dalon Westergreen]

On Wed, 2017-04-19 at 23:58 -0500, Dinh Nguyen wrote:
> On Wed, Apr 19, 2017 at 6:21 PM, Dalon Westergreen
> <dalon.westergr...@linux.intel.com> wrote:
> > 
> > On Wed, 2017-04-19 at 13:54 -0700, Dalon Westergreen wrote:
> > > 
> > > On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> > > > 
> > > > 
> > > > Really including Dalon
> > > > 
> > > > > 
> > > > > 
> > > > > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dingu...@kernel.org>
> > > > > wrote:
> > > > > CC: Dalon Westergreen
> > > > > 
> > > > > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > Add SPL support for Arria 10.
> > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > > > > > > > > > > Signed-off-by: Ley Foon Tan <ley.foon@intel.com>
> > > > > > > ---
> > > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > >  arch/arm/mach-socfpga/spl.c | 72
> > > +
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > >  1 file changed, 67 insertions(+), 5 deletions(-)
> > > > > > > 
> > > > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > > > > > > socfpga/spl.c
> > > > > > > index 0064fc8..f4a3cdd 100644
> > > > > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > > > > @@ -19,23 +19,32 @@
> > > > > > >  #include 
> > > > > > >  #include 
> > > > > > >  #include 
> > > > > > > +#include 
> > > > > > > +#include 
> > > > > > > +#include 
> > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > > > +#include 
> > > > > > > +#endif
> > > > > > > 
> > > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > > > 
> > > > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > > > >  static struct pl310_regs *const pl310 =
> > > > > > >  (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > > > > >  static struct scu_registers *scu_regs =
> > > > > > >  (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > > > > > >  static struct nic301_registers *nic301_regs =
> > > > > > >  (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > > > > > > -static struct socfpga_system_manager *sysmgr_regs =
> > > > > > > +#endif
> > > > > > > +
> > > > > > > +static const struct socfpga_system_manager *sysmgr_regs =
> > > > > > >  (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > > > > > > 
> > > > > > >  u32 spl_boot_device(void)
> > > > > > >  {
> > > > > > >  const u32 bsel = readl(_regs->bootinfo);
> > > > > > > 
> > > > > > > -switch (bsel & 0x7) {
> > > > > > > +switch (SYSMGR_GET_BOOTINFO

Re: [U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Dalon Westergreen]

On Wed, 2017-04-19 at 13:54 -0700, Dalon Westergreen wrote:
> On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> > 
> > Really including Dalon
> > 
> > > 
> > > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dingu...@kernel.org> wrote:
> > > CC: Dalon Westergreen
> > > 
> > > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > > 
> > > > 
> > > > 
> > > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > > 
> > > > > Add SPL support for Arria 10.
> > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > > > > > > > > Signed-off-by: Ley Foon Tan <ley.foon@intel.com>
> > > > > ---
> > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > >  arch/arm/mach-socfpga/spl.c | 72
> +
> > 
> > > 
> > > > 
> > > > > 
> > > > >  1 file changed, 67 insertions(+), 5 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
> > > > > index 0064fc8..f4a3cdd 100644
> > > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > > @@ -19,23 +19,32 @@
> > > > >  #include 
> > > > >  #include 
> > > > >  #include 
> > > > > +#include 
> > > > > +#include 
> > > > > +#include 
> > > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > > +#include 
> > > > > +#endif
> > > > > 
> > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > 
> > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > >  static struct pl310_regs *const pl310 =
> > > > >  (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > > >  static struct scu_registers *scu_regs =
> > > > >  (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > > > >  static struct nic301_registers *nic301_regs =
> > > > >  (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > > > > -static struct socfpga_system_manager *sysmgr_regs =
> > > > > +#endif
> > > > > +
> > > > > +static const struct socfpga_system_manager *sysmgr_regs =
> > > > >  (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > > > > 
> > > > >  u32 spl_boot_device(void)
> > > > >  {
> > > > >  const u32 bsel = readl(_regs->bootinfo);
> > > > > 
> > > > > -switch (bsel & 0x7) {
> > > > > +switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > > > >  case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> > > > >  return BOOT_DEVICE_RAM;
> > > > >  case 0x2:   /* NAND Flash (1.8V) */
> > > > > @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
> > > > >  }
> > > > >  #endif
> > > > > 
> > > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > >  static void socfpga_nic301_slave_ns(void)
> > > > >  {
> > > > >  writel(0x1, _regs->lwhps2fpgaregs);
> > > > > @@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
> > > > >  #endif
> > > > >  unsigned long sdram_size;
> > > > >  unsigned long reg;
> > > > > +int ret;
> > > > > 
> > > > >  /*
> > > > >   * First C code to run. Clear fake OCRAM ECC first as SBE
> > > > > @@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
> > > > >  /* Put everything into reset but L4WD0. */
> > > > >  socfpga_per_reset_all();
> > > > >  /* Put FPGA bridges into reset too. */
> > > > > -socfpga_bridges_reset(1);
> > > > > +ret = socfpga_bridges_reset(1);
> > > > > +if (ret) {
> > > > > +printf("socfpga_bridges_reset() failed: %d\n", ret);
> > >

Re: [U-Boot] [PATCH v6 13/16] arm: socfpga: Add SPL support for Arria 10

[Dalon Westergreen]

On Wed, 2017-04-19 at 15:44 -0500, Dinh Nguyen wrote:
> Really including Dalon
> 
> > On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dingu...@kernel.org> wrote:
> > CC: Dalon Westergreen
> > 
> > On 04/19/2017 02:49 PM, Dinh Nguyen wrote:
> > > 
> > > 
> > > On 04/19/2017 04:29 AM, Ley Foon Tan wrote:
> > > > Add SPL support for Arria 10.
> > > > 
> > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
> > > > > > > > Signed-off-by: Ley Foon Tan <ley.foon@intel.com>
> > > > ---
> > > > > > > >  arch/arm/mach-socfpga/spl.c | 72
+
> > > >  1 file changed, 67 insertions(+), 5 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-socfpga/spl.c
> > > > index 0064fc8..f4a3cdd 100644
> > > > --- a/arch/arm/mach-socfpga/spl.c
> > > > +++ b/arch/arm/mach-socfpga/spl.c
> > > > @@ -19,23 +19,32 @@
> > > >  #include 
> > > >  #include 
> > > >  #include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#include 
> > > > +#endif
> > > > 
> > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > 
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  static struct pl310_regs *const pl310 =
> > > >  (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > > >  static struct scu_registers *scu_regs =
> > > >  (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
> > > >  static struct nic301_registers *nic301_regs =
> > > >  (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
> > > > -static struct socfpga_system_manager *sysmgr_regs =
> > > > +#endif
> > > > +
> > > > +static const struct socfpga_system_manager *sysmgr_regs =
> > > >  (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> > > > 
> > > >  u32 spl_boot_device(void)
> > > >  {
> > > >  const u32 bsel = readl(_regs->bootinfo);
> > > > 
> > > > -switch (bsel & 0x7) {
> > > > +switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> > > >  case 0x1:   /* FPGA (HPS2FPGA Bridge) */
> > > >  return BOOT_DEVICE_RAM;
> > > >  case 0x2:   /* NAND Flash (1.8V) */
> > > > @@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
> > > >  }
> > > >  #endif
> > > > 
> > > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  static void socfpga_nic301_slave_ns(void)
> > > >  {
> > > >  writel(0x1, _regs->lwhps2fpgaregs);
> > > > @@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
> > > >  #endif
> > > >  unsigned long sdram_size;
> > > >  unsigned long reg;
> > > > +int ret;
> > > > 
> > > >  /*
> > > >   * First C code to run. Clear fake OCRAM ECC first as SBE
> > > > @@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
> > > >  /* Put everything into reset but L4WD0. */
> > > >  socfpga_per_reset_all();
> > > >  /* Put FPGA bridges into reset too. */
> > > > -socfpga_bridges_reset(1);
> > > > +ret = socfpga_bridges_reset(1);
> > > > +if (ret) {
> > > > +printf("socfpga_bridges_reset() failed: %d\n", ret);
> > > > +hang();
> > > > +}
> > > > 
> > > >  socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
> > > >  socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
> > > > @@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
> > > > 
> > > >  /* De-assert reset for peripherals and bridges based on handoff */
> > > >  reset_deassert_peripherals_handoff();
> > > > -socfpga_bridges_reset(0);
> > > > +ret = socfpga_bridges_reset(0);
> > > > +if (ret) {
> > > > +printf("socfpga_bridges_reset() failed: %d\n", ret);
> > > > +hang();
> > > 
> > > If you keep this patch the way it is, this will cause the Atlas board to
> > > hang here.
> > > 
> > 
> > Hi Dalon,
> > 
> > Can you check this patch? On the Atlas board, I'm seeing the call to
> > socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is
> > failing, because is_fpgamgr_initdone_high() is returning 0.
> > 
> > Dinh

i saw it the first go round.  i will test this out this afternoon.

--dalon

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[U-Boot] [PATCH v2] arm: socfpga: add cyclone5 based de10-nano board

[Dalon Westergreen]

Add support for the Terasic DE10-Nano board.  The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>

--
Changes in v2:
 -> fix duplicate license header
---
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/socfpga_cyclone5_de10_nano.dts |  68 +++
 arch/arm/mach-socfpga/Kconfig   |   7 +
 board/terasic/de10-nano/MAINTAINERS |   5 +
 board/terasic/de10-nano/Makefile|   7 +
 board/terasic/de10-nano/qts/iocsr_config.h  | 660 
 board/terasic/de10-nano/qts/pinmux_config.h | 219 +
 board/terasic/de10-nano/qts/pll_config.h|  85 
 board/terasic/de10-nano/qts/sdram_config.h  | 344 +++
 board/terasic/de10-nano/socfpga.c   |   6 +
 configs/socfpga_de10_nano_defconfig |  59 +++
 include/configs/socfpga_de10_nano.h |  33 ++
 12 files changed, 1494 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_nano.dts
 create mode 100644 board/terasic/de10-nano/MAINTAINERS
 create mode 100644 board/terasic/de10-nano/Makefile
 create mode 100644 board/terasic/de10-nano/qts/iocsr_config.h
 create mode 100644 board/terasic/de10-nano/qts/pinmux_config.h
 create mode 100644 board/terasic/de10-nano/qts/pll_config.h
 create mode 100644 board/terasic/de10-nano/qts/sdram_config.h
 create mode 100644 board/terasic/de10-nano/socfpga.c
 create mode 100644 configs/socfpga_de10_nano_defconfig
 create mode 100644 include/configs/socfpga_de10_nano.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce34e3e..699cbd6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -153,6 +153,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_de0_nano_soc.dtb   \
socfpga_cyclone5_de1_soc.dtb\
+   socfpga_cyclone5_de10_nano.dtb  \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts 
b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
new file mode 100644
index 000..ee62a50
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * based on socfpga_cyclone5_de0_nano_soc.dts
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+   model = "Terasic DE10-Nano";
+   compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   aliases {
+   ethernet0 = 
+   udc0 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+
+   rxd0-skew-ps = <420>;
+   rxd1-skew-ps = <420>;
+   rxd2-skew-ps = <420>;
+   rxd3-skew-ps = <420>;
+   txen-skew-ps = <0>;
+   txc-skew-ps = <1860>;
+   rxdv-skew-ps = <420>;
+   rxc-skew-ps = <1680>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9bfee04..f6e5773 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -82,6 +82,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+   bool "Terasic DE10-Nano (Cyclone V)"
+   select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -97,6 +101,7 @@ config SYS_BOARD
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+   default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -112,6 +117,7 @@ config SYS_VENDOR
de

Re: [U-Boot] [PATCH] arm: socfpga: add cyclone5 based de10-nano board

[Dalon Westergreen]

On Tue, 2017-04-18 at 17:32 +0200, Marek Vasut wrote:
> On 04/18/2017 05:11 PM, Dalon Westergreen wrote:
> > 
> > Add support for the Terasic DE10-Nano board.  The board
> > is based on the DE0-Nano-Soc board but adds a larger FPGA
> > and an HDMI output.
> > 
> > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> 
> [...]
> 
> > 
> > diff --git a/board/terasic/de10-nano/Makefile b/board/terasic/de10-
> > nano/Makefile
> > new file mode 100644
> > index 000..ab38f42
> > --- /dev/null
> > +++ b/board/terasic/de10-nano/Makefile
> > @@ -0,0 +1,9 @@
> > +#
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (C) 2017, Intel Corporation
> > +#
> > +# SPDX-License-Identifier: GPL-2.0+
> 
> The SPDX identifier is here twice (at least it's twice the same :)),
> drop one.
> 
> > 
> > +
> > +obj-y  := socfpga.o
> 
> Wasn't this patch submitted to the ML already once ? Anyway, looks OK
> expect for the nit.
> 
I believe it was dropped from a patch set including a bunch of boards with the
suggestion it should be a separate patch.  I am just getting back to it.

--dalon
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[U-Boot] [PATCH] arm: socfpga: add cyclone5 based de10-nano board

[Dalon Westergreen]

Add support for the Terasic DE10-Nano board.  The board
is based on the DE0-Nano-Soc board but adds a larger FPGA
and an HDMI output.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
---
 arch/arm/dts/Makefile   |   1 +
 arch/arm/dts/socfpga_cyclone5_de10_nano.dts |  68 +++
 arch/arm/mach-socfpga/Kconfig   |   7 +
 board/terasic/de10-nano/MAINTAINERS |   5 +
 board/terasic/de10-nano/Makefile|   9 +
 board/terasic/de10-nano/qts/iocsr_config.h  | 660 
 board/terasic/de10-nano/qts/pinmux_config.h | 219 +
 board/terasic/de10-nano/qts/pll_config.h|  85 
 board/terasic/de10-nano/qts/sdram_config.h  | 344 +++
 board/terasic/de10-nano/socfpga.c   |   6 +
 configs/socfpga_de10_nano_defconfig |  59 +++
 include/configs/socfpga_de10_nano.h |  33 ++
 12 files changed, 1496 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_de10_nano.dts
 create mode 100644 board/terasic/de10-nano/MAINTAINERS
 create mode 100644 board/terasic/de10-nano/Makefile
 create mode 100644 board/terasic/de10-nano/qts/iocsr_config.h
 create mode 100644 board/terasic/de10-nano/qts/pinmux_config.h
 create mode 100644 board/terasic/de10-nano/qts/pll_config.h
 create mode 100644 board/terasic/de10-nano/qts/sdram_config.h
 create mode 100644 board/terasic/de10-nano/socfpga.c
 create mode 100644 configs/socfpga_de10_nano_defconfig
 create mode 100644 include/configs/socfpga_de10_nano.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ce34e3e..699cbd6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -153,6 +153,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_cyclone5_socdk.dtb  \
socfpga_cyclone5_de0_nano_soc.dtb   \
socfpga_cyclone5_de1_soc.dtb\
+   socfpga_cyclone5_de10_nano.dtb  \
socfpga_cyclone5_sockit.dtb \
socfpga_cyclone5_socrates.dtb   \
socfpga_cyclone5_sr1500.dtb \
diff --git a/arch/arm/dts/socfpga_cyclone5_de10_nano.dts 
b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
new file mode 100644
index 000..ee62a50
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_de10_nano.dts
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2017, Intel Corporation
+ *
+ * based on socfpga_cyclone5_de0_nano_soc.dts
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+   model = "Terasic DE10-Nano";
+   compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+   chosen {
+   bootargs = "console=ttyS0,115200";
+   };
+
+   aliases {
+   ethernet0 = 
+   udc0 = 
+   };
+
+   memory {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x4000>; /* 1GB */
+   };
+
+   soc {
+   u-boot,dm-pre-reloc;
+   };
+};
+
+ {
+   status = "okay";
+   phy-mode = "rgmii";
+
+   rxd0-skew-ps = <420>;
+   rxd1-skew-ps = <420>;
+   rxd2-skew-ps = <420>;
+   rxd3-skew-ps = <420>;
+   txen-skew-ps = <0>;
+   txc-skew-ps = <1860>;
+   rxdv-skew-ps = <420>;
+   rxc-skew-ps = <1680>;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9bfee04..f6e5773 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -82,6 +82,10 @@ config TARGET_SOCFPGA_TERASIC_DE0_NANO
bool "Terasic DE0-Nano-Atlas (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_TERASIC_DE10_NANO
+   bool "Terasic DE10-Nano (Cyclone V)"
+   select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE1_SOC
bool "Terasic DE1-SoC (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -97,6 +101,7 @@ config SYS_BOARD
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
+   default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
@@ -112,6 +117,7 @@ config SYS_VENDOR
default "samtec" if TARGET_SOCFPGA_SAMTEC_VINI

[U-Boot] [PATCH v5 4/8] arm: socfpga: C5 SoCDK use environment in common header

[Dalon Westergreen]

This removes the default environment from the C5 SoCDK headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

In addition to the above, add support to boot from the custom
a2 type partition.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_cyclone5_defconfig   |  3 +++
 include/configs/socfpga_cyclone5_socdk.h | 32 
 2 files changed, 3 insertions(+), 32 deletions(-)

diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 8b050b9..c8b8084 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
diff --git a/include/configs/socfpga_cyclone5_socdk.h 
b/include/configs/socfpga_cyclone5_socdk.h
index 4100ef9..dfe4980 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -16,13 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"zImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -34,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v5 5/8] arm: socfpga: DE1 use environment in common header

[Dalon Westergreen]

This removes the default environment from the de1 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

This board does not have a devicetree in the upstream kernel
source so set devicetree to socfpga_cyclone5_de1_soc.dtb.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in V2:
 - Remove unneeded CONFIG_BOOTFILE
 - set devicetree name to match socfpga_{fpga model}_{board model}.dts
   pattern
---
 configs/socfpga_de1_soc_defconfig |  1 +
 include/configs/socfpga_de1_soc.h | 20 
 2 files changed, 1 insertion(+), 20 deletions(-)

diff --git a/configs/socfpga_de1_soc_defconfig 
b/configs/socfpga_de1_soc_defconfig
index 135dfac..211ea41 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_de1_soc.h 
b/include/configs/socfpga_de1_soc.h
index c6e8d81..014828b 100644
--- a/include/configs/socfpga_de1_soc.h
+++ b/include/configs/socfpga_de1_soc.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"fitImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,23 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdtaddr}\0" \
-   "bootimage=zImage\0" \
-   "fdtaddr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdtaddr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdtaddr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdtaddr} ${fdtimage}\0" \
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v5 7/8] arm: socfpga: Socrates use environment in common header

[Dalon Westergreen]

This removes the default environment from the socrates headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_socrates_defconfig |  1 +
 include/configs/socfpga_socrates.h | 26 --
 2 files changed, 1 insertion(+), 26 deletions(-)

diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index e9276f9..4246ad6 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_socrates.h 
b/include/configs/socfpga_socrates.h
index 90343b7..5dc9298 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCrates */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"zImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,29 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiroot=/dev/mtdblock0\0" \
-   "qspirootfstype=jffs2\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
-   "bootm ${loadaddr} - ${fdt_addr}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v5 6/8] arm: socfpga: SoCKit use environment in common header

[Dalon Westergreen]

This removes the default environment from the SoCKit headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_sockit_defconfig |  1 +
 include/configs/socfpga_sockit.h | 28 
 2 files changed, 1 insertion(+), 28 deletions(-)

diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index d0c2bda..bf60783 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 326310b..c9fc5c9 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"fitImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v5 8/8] arm: socfpga: sr1500 use environment in common header

[Dalon Westergreen]

This removes the default environment from the sr1500 header
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

This board has no upstream devicetree in the kernel source,
so set to socfpga_cyclone5_sr1500.dtb.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
 - set devicetree name to match socfpga_{fpga model}_{board model}.dts
   pattern
---
 configs/socfpga_sr1500_defconfig |  1 +
 include/configs/socfpga_sr1500.h | 28 
 2 files changed, 1 insertion(+), 28 deletions(-)

diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 981600b..ac1ed53 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_SR1500=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index f67fafd..64e1595 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SR1500 */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"uImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -28,31 +25,6 @@
 #define CONFIG_PHY_MARVELL
 #define PHY_ANEG_TIMEOUT   8000
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "fsloadcmd=ext2load\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* Environment */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 
-- 
2.7.4

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[U-Boot] [PATCH v5 3/8] arm: socfpga: A5 SoCDK use environment in common header

[Dalon Westergreen]

This removes the default environment from the A5 socdk headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Add support to boot from the custom a2 type partition.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v3:
 - Fix small typo in defconfig, missing "C"
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
 - Fix dtb name

a5config test

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
---
 configs/socfpga_arria5_defconfig   |  3 +++
 include/configs/socfpga_arria5_socdk.h | 32 
 2 files changed, 3 insertions(+), 32 deletions(-)

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 43c51fe..5aa8e25 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
diff --git a/include/configs/socfpga_arria5_socdk.h 
b/include/configs/socfpga_arria5_socdk.h
index 9b1f753..b60d007 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -16,13 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"zImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -34,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v5 2/8] arm: socfpga: DE0 use environment in common header

[Dalon Westergreen]

This removes the default environment from the de0 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

In addition to the above, add support to boot from the custom
a2 type partition

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_de0_nano_soc_defconfig |  3 +++
 include/configs/socfpga_de0_nano_soc.h | 20 
 2 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/configs/socfpga_de0_nano_soc_defconfig 
b/configs/socfpga_de0_nano_soc_defconfig
index af41e1e..b122135 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -58,3 +59,5 @@ CONFIG_G_DNL_MANUFACTURER="terasic"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
\ No newline at end of file
diff --git a/include/configs/socfpga_de0_nano_soc.h 
b/include/configs/socfpga_de0_nano_soc.h
index f655972..dd5933d 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"fitImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,23 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v5 1/8] arm: socfpga: Add distro boot to socfpga common header

[Dalon Westergreen]

This adds a common environment and support for distro boot
in the common socfpga header.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v5:
 - Per Frank, to support OpenSuse the ENV must be after the GPT
Changes in v4:
 - Move env back to being right after the MBR
Changes in v3:
 - fix spacing between asterix
 - remove verify=n as a default setting

Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE and fdt_addr
 - cleanup spacing in MMC env size

common

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
---
 include/configs/socfpga_common.h | 52 
 1 file changed, 48 insertions(+), 4 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 8472b52..cf02d2d 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -65,6 +65,9 @@
 #define CONFIG_SYS_HOSTNAMECONFIG_SYS_BOARD
 #endif
 
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+
 /*
  * Cache
  */
@@ -242,13 +245,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * U-Boot environment
  */
 #if !defined(CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE4096
+#define CONFIG_ENV_SIZE(8 * 1024)
 #endif
 
 /* Environment for SDMMC boot */
 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
-#define CONFIG_SYS_MMC_ENV_DEV 0   /* device 0 */
-#define CONFIG_ENV_OFFSET  512 /* just after the MBR */
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET  (34 * 512) /* just after the GPT */
 #endif
 
 /* Environment for QSPI boot */
@@ -305,8 +308,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#endif
+#else
+#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
 #endif
 #endif
 
@@ -328,4 +335,41 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
 
+/* Extra Environment */
+#ifndef CONFIG_SPL_BUILD
+#include 
+
+#ifdef CONFIG_CMD_PXE
+#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+   BOOT_TARGET_DEVICES_MMC(func) \
+   BOOT_TARGET_DEVICES_PXE(func) \
+   func(DHCP, dhcp, na)
+
+#include 
+
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "bootm_size=0xa00\0" \
+   "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
+   "fdt_addr_r=0x0200\0" \
+   "scriptaddr=0x0210\0" \
+   "pxefile_addr_r=0x0220\0" \
+   "ramdisk_addr_r=0x0230\0" \
+   BOOTENV
+
+#endif
+#endif
+
 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */
-- 
2.7.4

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[U-Boot] [PATCH v5 0/8] arm: socfpga: Move to using distro boot

[Dalon Westergreen]

This series adds support to the common socfpga header for distro boot and moves
the DE0/1, Socrates, C5/A5 SoCDK, and SoCKIT kits to use the common
environment.
 
Where available, the default devicetree is set to the devicetree for the board
available in the kernel source.  If none is available in the kernel source, the
devicetree is set to the name previously used in the board header file.

Changes in v5:
 - Fix typo in socfpga_arria5_defconfig
 - ENV must be after GPT to support opensuse
Changes in v4:
 - Move env back to immediately after MBR 
Changes in v3:
 - fix errors in 1/8 patch
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE and fdt_addr
 - Cleanup of socfpga_common.h
 - Fixed dtb names for de1, sr1500, and arria5 boards


Dalon Westergreen (8):
  arm: socfpga: Add distro boot to socfpga common header
  arm: socfpga: DE0 use environment in common header
  arm: socfpga: A5 SoCDK use environment in common header
  arm: socfpga: C5 SoCDK use environment in common header
  arm: socfpga: DE1 use environment in common header
  arm: socfpga: SoCKit use environment in common header
  arm: socfpga: Socrates use environment in common header
  arm: socfpga: sr1500 use environment in common header

 configs/socfpga_arria5_defconfig |  3 ++
 configs/socfpga_cyclone5_defconfig   |  3 ++
 configs/socfpga_de0_nano_soc_defconfig   |  3 ++
 configs/socfpga_de1_soc_defconfig|  1 +
 configs/socfpga_sockit_defconfig |  1 +
 configs/socfpga_socrates_defconfig   |  1 +
 configs/socfpga_sr1500_defconfig |  1 +
 include/configs/socfpga_arria5_socdk.h   | 32 
 include/configs/socfpga_common.h | 52 +---
 include/configs/socfpga_cyclone5_socdk.h | 32 
 include/configs/socfpga_de0_nano_soc.h   | 20 
 include/configs/socfpga_de1_soc.h| 20 
 include/configs/socfpga_sockit.h | 28 -
 include/configs/socfpga_socrates.h   | 26 
 include/configs/socfpga_sr1500.h | 28 -
 15 files changed, 61 insertions(+), 190 deletions(-)

-- 
2.7.4

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Re: [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Sun, 2017-03-05 at 18:49 +0100, Marek Vasut wrote:
> On 03/05/2017 06:38 PM, Dalon Westergreen wrote:
> > 
> > On Tue, 2017-02-28 at 06:45 -0800, Dalon Westergreen wrote:
> > > 
> > > On Mon, 2017-02-20 at 06:35 -0800, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > On Mon, 2017-02-20 at 15:24 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > On 02/20/2017 03:21 PM, Dalon Westergreen wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Mon, 2017-02-20 at 15:14 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 02/20/2017 03:10 PM, Dalon Westergreen wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Mon, 2017-02-20 at 10:07 +0100, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 02/18/2017 02:34 AM, Dalon Westergreen wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > > > > > configuration for the device.  This can lead to a boot
> > > > > > > > > > failure
> > > > > > > > > > on warm resets. This patch disables warm resets when CSEL=0.
> > > > > > > > > > This results in the clock and pll configurations being reset
> > > > > > > > > > on any reset issued when CSEL=0.
> > > > > > > > > > 
> > > > > > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > > > > > 
> > > > > > > > > What about my suggestion for V2 about just loading function
> > > > > > > > > pointer
> > > > > > > > > into
> > > > > > > > > the reset jump address register ?
> > > > > > > > 
> > > > > > > > Frankly, i really dont like relying on the existence of a
> > > > > > > > snippet of
> > > > > > > > code in
> > > > > > > > the
> > > > > > > > onchip ram being untouched to ensure a reboot/reset will occur
> > > > > > > > for
> > > > > > > > this
> > > > > > > > csel=0
> > > > > > > > case.  i am certain this case is rarely used, and confident that
> > > > > > > > it
> > > > > > > > isnt
> > > > > > > > being
> > > > > > > > used while trying to preserve sdram contents.
> > > > > > > 
> > > > > > > Well, you already rely on such snippet, it's SPL. If you corrupt
> > > > > > > SPL
> > > > > > > and
> > > > > > > do warm reset, your system hangs, I had that multiple times :)
> > > > > > 
> > > > > > True.  I would argue to just use cold resets but i think arria 10
> > > > > > has
> > > > > > more
> > > > > > use
> > > > > > for the warm reset case.
> > > > > 
> > > > > OK
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > the downside is that the scorecard is reset every boot. so the
> > > > > > > > bootrom
> > > > > > > > will
> > > > > > > > retry all the spl images again resulting in possibly longer boot
> > > > > > > > times.
> > > > > > > 
> > > > > > > Is that significant ?
> > > > > > 
> > > > > > The watchdog timeout is on the order of 1.5 seconds.  That would be
> > > > > > for
> > > > > > each
> > > > > > failed spl.
> > > > > 
> > > > > Hm, OK. But then your system is kinda broken, so you should expect
> > > > > this
> > > > > I guess.
> > > > 
> > > > My thought exactly...  I would like to see if Chin Liang or Dinh have
> > > > any
> > > > comments?
> > > 
> > > Chin Liang, Dinh, any comments?
> > 
> > Marek, I would like to propose we move forward with this patch?
> 
> TBH I'm still thinking if you turned the V2 into C code and passed a 
> function pointer into the warm reset jump address register, that'd be 
> the best.
> 
I will give it a shot, i just dont like relying on the spl image still
being present in the onchip ram.  There is nothing preventing an errant
process or user from overwriting it and i have run into customers using
that memory for their own purposes.

-dalon

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Re: [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Tue, 2017-02-28 at 06:45 -0800, Dalon Westergreen wrote:
> On Mon, 2017-02-20 at 06:35 -0800, Dalon Westergreen wrote:
> > 
> > On Mon, 2017-02-20 at 15:24 +0100, Marek Vasut wrote:
> > > 
> > > 
> > > On 02/20/2017 03:21 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > 
> > > > On Mon, 2017-02-20 at 15:14 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > On 02/20/2017 03:10 PM, Dalon Westergreen wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Mon, 2017-02-20 at 10:07 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 02/18/2017 02:34 AM, Dalon Westergreen wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > > > configuration for the device.  This can lead to a boot failure
> > > > > > > > on warm resets. This patch disables warm resets when CSEL=0.
> > > > > > > > This results in the clock and pll configurations being reset
> > > > > > > > on any reset issued when CSEL=0.
> > > > > > > > 
> > > > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > > > 
> > > > > > > What about my suggestion for V2 about just loading function
> > > > > > > pointer
> > > > > > > into
> > > > > > > the reset jump address register ?
> > > > > > 
> > > > > > Frankly, i really dont like relying on the existence of a snippet of
> > > > > > code in
> > > > > > the
> > > > > > onchip ram being untouched to ensure a reboot/reset will occur for
> > > > > > this
> > > > > > csel=0
> > > > > > case.  i am certain this case is rarely used, and confident that it
> > > > > > isnt
> > > > > > being
> > > > > > used while trying to preserve sdram contents.
> > > > > 
> > > > > Well, you already rely on such snippet, it's SPL. If you corrupt SPL
> > > > > and
> > > > > do warm reset, your system hangs, I had that multiple times :)
> > > > 
> > > > True.  I would argue to just use cold resets but i think arria 10 has
> > > > more
> > > > use
> > > > for the warm reset case.
> > > 
> > > OK
> > > 
> > > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > the downside is that the scorecard is reset every boot. so the
> > > > > > bootrom
> > > > > > will
> > > > > > retry all the spl images again resulting in possibly longer boot
> > > > > > times.
> > > > > 
> > > > > Is that significant ?
> > > > 
> > > > The watchdog timeout is on the order of 1.5 seconds.  That would be for
> > > > each
> > > > failed spl.
> > > 
> > > Hm, OK. But then your system is kinda broken, so you should expect this
> > > I guess.
> > 
> > My thought exactly...  I would like to see if Chin Liang or Dinh have any
> > comments?
> 
> Chin Liang, Dinh, any comments?

Marek, I would like to propose we move forward with this patch?

--dalon

> 
> > 
> > > 
> > > 
> > > 
> > > [...]
> > > 
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Re: [U-Boot] [PATCH 1/2] arm: socfpga: Enable abort for DE-nano-SoC SPL uboot load from MMC

[Dalon Westergreen]

On Sun, 2017-03-05 at 18:16 +0100, Marek Vasut wrote:
> On 03/05/2017 01:54 PM, Frank Kunz wrote:
> > 
> > This allows the SPL to scan the MMC for a valid uboot image on a second
> > sector location defined by CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR when
> > the default location "CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + first
> > partition offset" does not contain a valid uboot image.
> > 
> > Signed-off-by: Frank Kunz 
> > ---
> > :100644 100644 dd5933d43c... bd3e83ddea... Minclude/configs/socfpga_
> > de0_nano_soc.h
> >  include/configs/socfpga_de0_nano_soc.h | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/include/configs/socfpga_de0_nano_soc.h
> > b/include/configs/socfpga_de0_nano_soc.h
> > index dd5933d43c..bd3e83ddea 100644
> > --- a/include/configs/socfpga_de0_nano_soc.h
> > +++ b/include/configs/socfpga_de0_nano_soc.h
> > @@ -12,6 +12,8 @@
> >  #define CONFIG_FAT_WRITE
> >  #define CONFIG_HW_WATCHDOG
> > 
> > +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
> > +
> >  /* Memory configurations */
> >  #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB */
> > 
> > 
> This looks like a horrid hack , didn't Dalon add support into U-Boot SPL 
> to scan all partitions for the final u-boot image ?

I did.  The 0xA2 partition can be located on any partition number now.  I
believe Frank places the SPL image at a 64KB offset from the start of the
sdcard to skip the MBR/GPT.  But per our previous debate, it is not my
favored implementation as it relies on the bootrom to load the SPL once.

Also, i mentioned before that i would like to hold off on this patch set and
let Ley Foon et al finish the A10 stuff.

--dalon

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Re: [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Mon, 2017-02-20 at 06:35 -0800, Dalon Westergreen wrote:
> On Mon, 2017-02-20 at 15:24 +0100, Marek Vasut wrote:
> > 
> > On 02/20/2017 03:21 PM, Dalon Westergreen wrote:
> > > 
> > > 
> > > On Mon, 2017-02-20 at 15:14 +0100, Marek Vasut wrote:
> > > > 
> > > > 
> > > > On 02/20/2017 03:10 PM, Dalon Westergreen wrote:
> > > > > 
> > > > > 
> > > > > 
> > > > > On Mon, 2017-02-20 at 10:07 +0100, Marek Vasut wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On 02/18/2017 02:34 AM, Dalon Westergreen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > > configuration for the device.  This can lead to a boot failure
> > > > > > > on warm resets. This patch disables warm resets when CSEL=0.
> > > > > > > This results in the clock and pll configurations being reset
> > > > > > > on any reset issued when CSEL=0.
> > > > > > > 
> > > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > > 
> > > > > > What about my suggestion for V2 about just loading function pointer
> > > > > > into
> > > > > > the reset jump address register ?
> > > > > 
> > > > > Frankly, i really dont like relying on the existence of a snippet of
> > > > > code in
> > > > > the
> > > > > onchip ram being untouched to ensure a reboot/reset will occur for
> > > > > this
> > > > > csel=0
> > > > > case.  i am certain this case is rarely used, and confident that it
> > > > > isnt
> > > > > being
> > > > > used while trying to preserve sdram contents.
> > > > 
> > > > Well, you already rely on such snippet, it's SPL. If you corrupt SPL and
> > > > do warm reset, your system hangs, I had that multiple times :)
> > > 
> > > True.  I would argue to just use cold resets but i think arria 10 has more
> > > use
> > > for the warm reset case.
> > 
> > OK
> > 
> > > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > 
> > > > > the downside is that the scorecard is reset every boot. so the bootrom
> > > > > will
> > > > > retry all the spl images again resulting in possibly longer boot
> > > > > times.
> > > > 
> > > > Is that significant ?
> > > 
> > > The watchdog timeout is on the order of 1.5 seconds.  That would be for
> > > each
> > > failed spl.
> > 
> > Hm, OK. But then your system is kinda broken, so you should expect this
> > I guess.
> 
> My thought exactly...  I would like to see if Chin Liang or Dinh have any
> comments?

Chin Liang, Dinh, any comments?

> > 
> > 
> > [...]
> > 
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Re: [U-Boot] [PATCH v3 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Tue, 2017-02-21 at 21:00 -0700, Simon Glass wrote:
> Hi Dalon,
> 
> On 20 February 2017 at 07:56, Dalon Westergreen <dwest...@gmail.com> wrote:
> > 
> > The implementation of boot_get_fpga only supported one fpga family.
> > This modification allows for any of the fpga devices supported by
> > fpga_load to be used.
> 
[snip ...]
> > 
> >  /* configuration node */
> >  #define FIT_KERNEL_PROP"kernel"
> > @@ -955,6 +957,9 @@ int fit_image_hash_get_value(const void *fit, int
> > noffset, uint8_t **value,
> > 
> >  int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
> > 
> > +int fit_image_fpga_get_devnum(const void *fit, int noffset, int *devnum);
> > +int fit_image_fpga_is_partial(const void *fit, int noffset);
> 
> Can you put the function comments here instead of in the C file?

Doing this would be counter to every other function in the c file these
are added to, so i think it best to leave as is.

--dalon

> > 
> > +
> >  /**
> >   * fit_add_verification_data() - add verification data to FIT image nodes
> >   *
> > --
> > 2.7.4
> > 
> > ___
> > U-Boot mailing list
> > U-Boot@lists.denx.de
> > http://lists.denx.de/mailman/listinfo/u-boot
> 
> Regards,
> Simon
___
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Re: [U-Boot] [PATCH v3 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Wed, 2017-02-22 at 14:08 +0200, Tomas Melin wrote:
> Hi Dalon,
> 
> On 02/22/2017 06:00 AM, Simon Glass wrote:
> > 
> > Hi Dalon,
> > 
> > On 20 February 2017 at 07:56, Dalon Westergreen <dwest...@gmail.com> wrote:
> > > 
> > > The implementation of boot_get_fpga only supported one fpga family.
> > > This modification allows for any of the fpga devices supported by
> > > fpga_load to be used.
> > 
> > Can you add some docs somewhere to explain how this is used? E.g. you
> > could update something in doc/uImage.FIT/
> > 
> > > 
> > > 
> > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > 
> > > --
> > > Changes in v3:
> > >  - Fix typos/caps in comments
> > > Changes in v2:
> > >  - Add fitimage support for fpga-devnum and fpga-partial-image
> > >  - Use above in boot_get_fpga
> > >  - for xilinx fpgas double check using image size to determine
> > >    if image is a partial image
> > > ---
> > >  common/image-fit.c | 51
> > > +++
> > >  common/image.c | 51 -
> > > --
> > >  include/image.h|  5 +
> > >  3 files changed, 88 insertions(+), 19 deletions(-)
> > > 
> > > diff --git a/common/image-fit.c b/common/image-fit.c
> > > index 109ecfa..eb0c633 100644
> > > --- a/common/image-fit.c
> > > +++ b/common/image-fit.c
> > > @@ -916,6 +916,57 @@ ulong fit_get_end(const void *fit)
> > >  }
> > > 
> > >  /**
> > > + * fit_image_fpga_get_devnum - get fpga devnum
> > > + * @fit: pointer to the FIT format image header
> > > + * @noffset: fpga node offset
> > > + * @devnum: pointer to an int, will hold fpga devnum
> > > + *
> > > + * fit_image_fpga_get_devnum() finds the fpga devnum for which the fpga
> > > data is
> > > + * intended.  If the property is not found, we default to 0.
> 
> Repeating these function names in the decriptions could IMHO be avoided. Also
> please check double spacing.

i can remove that, i just followed what seemed like the convention in the
functions surrounding this one.

> > 
> > > 
> > > + *
> > > + * returns:
> > > + * 0, on devnum not found
> > > + * value, on devnum found
> 
> This seems to always return 0. Should it instead of providing devnum as an
> argument return devnum?

Yes, easy enough. 

> > 
> > > 
> > > + */
> > > +int fit_image_fpga_get_devnum(const void *fit, int noffset, int *devnum)
> > > +{
> > > +   int len;
> > > +   int *value;
> > > +
> > > +   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_DEVNUM_PROP,
> > > );
> > 
> > Can you use fdtdec_get_int()? It handles the endian conversion
> > automatically.
> > 
> > > 
> > > +   if (value == NULL || len != sizeof(int))
> > > +   *devnum = 0;
> > > +   else
> > > +   *devnum = *value;
> > > +
> > > +   return 0;
> > > +}
> > > +
> > > +/**
> > > + * fit_image_fpga_is_partial - is partial fpga
> > 
> > This doesn't explain very much - can you rephrase?
> > 
> > > 
> > > + * @fit: pointer to the FIT format image header
> > > + * @noffset: fpga node offset
> > > + *
> > > + * fit_image_fpga_is_partial() checks if the fpga node sets the property
> > > + * indicating the data represents a partial fpga image.
> > > + *
> > > + * returns:
> > > + * 0, on devnum not found
> > > + * value, on devnum found
> > 
> > But it seems to return 0 or 1?
> > 
> > > 
> > > + */
> > > +int fit_image_fpga_is_partial(const void *fit, int noffset)
> > > +{
> > > +   int len;
> > > +   int *value;
> > > +
> > > +   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_PARTIAL_PROP,
> > > );
> > > +   if ((value == NULL || len != sizeof(int)) || (value == 0))
> > 
> > Is this boolean? Could you use fdtdec_get_bool()?
> > 
> > > 
> > > +   return 0;
> > > +   else
> > > +   return 1;
> > > +}
> > > +
> > > +/**
> > >   * fit_set_timestamp - set node timestamp property
> > >   * @fit: pointer to the FIT form

Re: [U-Boot] [PATCH v3 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Tue, 2017-02-21 at 21:00 -0700, Simon Glass wrote:
> Hi Dalon,
> 
> On 20 February 2017 at 07:56, Dalon Westergreen <dwest...@gmail.com> wrote:
> > 
> > The implementation of boot_get_fpga only supported one fpga family.
> > This modification allows for any of the fpga devices supported by
> > fpga_load to be used.
> 
> Can you add some docs somewhere to explain how this is used? E.g. you
> could update something in doc/uImage.FIT/

sure thing. 

> > 
> > 
> > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > 
> > --
> > Changes in v3:
> >  - Fix typos/caps in comments
> > Changes in v2:
> >  - Add fitimage support for fpga-devnum and fpga-partial-image
> >  - Use above in boot_get_fpga
> >  - for xilinx fpgas double check using image size to determine
> >    if image is a partial image
> > ---
> >  common/image-fit.c | 51 +++
> >  common/image.c | 51 ---
> >  include/image.h|  5 +
> >  3 files changed, 88 insertions(+), 19 deletions(-)
> > 
> > diff --git a/common/image-fit.c b/common/image-fit.c
> > index 109ecfa..eb0c633 100644
> > --- a/common/image-fit.c
> > +++ b/common/image-fit.c
> > @@ -916,6 +916,57 @@ ulong fit_get_end(const void *fit)
> >  }
> > 
> >  /**
> > + * fit_image_fpga_get_devnum - get fpga devnum
> > + * @fit: pointer to the FIT format image header
> > + * @noffset: fpga node offset
> > + * @devnum: pointer to an int, will hold fpga devnum
> > + *
> > + * fit_image_fpga_get_devnum() finds the fpga devnum for which the fpga
> > data is
> > + * intended.  If the property is not found, we default to 0.
> > + *
> > + * returns:
> > + * 0, on devnum not found
> > + * value, on devnum found
> > + */
> > +int fit_image_fpga_get_devnum(const void *fit, int noffset, int *devnum)
> > +{
> > +   int len;
> > +   int *value;
> > +
> > +   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_DEVNUM_PROP,
> > );
> 
> Can you use fdtdec_get_int()? It handles the endian conversion automatically.
> 
> > 
> > +   if (value == NULL || len != sizeof(int))
> > +   *devnum = 0;
> > +   else
> > +   *devnum = *value;
> > +
> > +   return 0;
> > +}
> > +
> > +/**
> > + * fit_image_fpga_is_partial - is partial fpga
> 
> This doesn't explain very much - can you rephrase?

Yes, i will elaboate
> 
> > 
> > + * @fit: pointer to the FIT format image header
> > + * @noffset: fpga node offset
> > + *
> > + * fit_image_fpga_is_partial() checks if the fpga node sets the property
> > + * indicating the data represents a partial fpga image.
> > + *
> > + * returns:
> > + * 0, on devnum not found
> > + * value, on devnum found
> 
> But it seems to return 0 or 1?

Bad cut and paste... i will fix this.

> > 
> > + */
> > +int fit_image_fpga_is_partial(const void *fit, int noffset)
> > +{
> > +   int len;
> > +   int *value;
> > +
> > +   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_PARTIAL_PROP,
> > );
> > +   if ((value == NULL || len != sizeof(int)) || (value == 0))
> 
> Is this boolean? Could you use fdtdec_get_bool()?
> 
> > 
> > +   return 0;
> > +   else
> > +   return 1;
> > +}
> > +
> > +/**
> >   * fit_set_timestamp - set node timestamp property
> >   * @fit: pointer to the FIT format image header
> >   * @noffset: node offset
> > diff --git a/common/image.c b/common/image.c
> > index 0f88984..6480b0a 100644
> > --- a/common/image.c
> > +++ b/common/image.c
> > @@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t
> > arch,
> >  }
> > 
> >  #if IMAGE_ENABLE_FIT
> > -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
> > +#if defined(CONFIG_FPGA)
> >  int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
> >   uint8_t arch, const ulong *ld_start, ulong * const ld_len)
> >  {
> > @@ -1316,9 +1316,10 @@ int boot_get_fpga(int argc, char * const argv[],
> > bootm_headers_t *images,
> > int fit_img_result;
> > const char *uname, *name;
> > int err;
> > -   int devnum = 0; /* TODO support multi fpga platforms */
> > -  

Re: [U-Boot] [PATCH v3 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Mon, 2017-02-20 at 16:16 +0100, Michal Simek wrote:
> On 20.2.2017 15:56, Dalon Westergreen wrote:
> > 
> > The implementation of boot_get_fpga only supported one fpga family.
> > This modification allows for any of the fpga devices supported by
> > fpga_load to be used.
> > 
> > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > 
> > --
> > Changes in v3:
> >  - Fix typos/caps in comments
> > Changes in v2:
> >  - Add fitimage support for fpga-devnum and fpga-partial-image
> >  - Use above in boot_get_fpga
> >  - for xilinx fpgas double check using image size to determine
> >    if image is a partial image
> > ---
> >  common/image-fit.c | 51 +++
> >  common/image.c | 51 ---
> >  include/image.h|  5 +
> >  3 files changed, 88 insertions(+), 19 deletions(-)
> > 
> > diff --git a/common/image-fit.c b/common/image-fit.c
> > index 109ecfa..eb0c633 100644
> > --- a/common/image-fit.c
> > +++ b/common/image-fit.c
> > @@ -916,6 +916,57 @@ ulong fit_get_end(const void *fit)
> >  }
> >  
> >  /**
> > + * fit_image_fpga_get_devnum - get fpga devnum
> > + * @fit: pointer to the FIT format image header
> > + * @noffset: fpga node offset
> > + * @devnum: pointer to an int, will hold fpga devnum
> > + *
> > + * fit_image_fpga_get_devnum() finds the fpga devnum for which the fpga
> > data is
> > + * intended.  If the property is not found, we default to 0.
> > + *
> > + * returns:
> > + * 0, on devnum not found
> > + * value, on devnum found
> > + */
> > +int fit_image_fpga_get_devnum(const void *fit, int noffset, int *devnum)
> > +{
> > +   int len;
> > +   int *value;
> > +
> > +   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_DEVNUM_PROP,
> > );
> > +   if (value == NULL || len != sizeof(int))
> > +   *devnum = 0;
> > +   else
> > +   *devnum = *value;
> > +
> > +   return 0;
> > +}
> > +
> > +/**
> > + * fit_image_fpga_is_partial - is partial fpga
> 
> bitstream.

will do.

> > 
> > + * @fit: pointer to the FIT format image header
> > + * @noffset: fpga node offset
> > + *
> > + * fit_image_fpga_is_partial() checks if the fpga node sets the property
> > + * indicating the data represents a partial fpga image.
> > + *
> > + * returns:
> > + * 0, on devnum not found
> > + * value, on devnum found
> > + */
> > +int fit_image_fpga_is_partial(const void *fit, int noffset)
> > +{
> > +   int len;
> > +   int *value;
> > +
> > +   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_PARTIAL_PROP,
> > );
> > +   if ((value == NULL || len != sizeof(int)) || (value == 0))
> > +   return 0;
> > +   else
> > +   return 1;
> > +}
> > +
> > +/**
> >   * fit_set_timestamp - set node timestamp property
> >   * @fit: pointer to the FIT format image header
> >   * @noffset: node offset
> > diff --git a/common/image.c b/common/image.c
> > index 0f88984..6480b0a 100644
> > --- a/common/image.c
> > +++ b/common/image.c
> > @@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t
> > arch,
> >  }
> >  
> >  #if IMAGE_ENABLE_FIT
> > -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
> > +#if defined(CONFIG_FPGA)
> >  int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
> >       uint8_t arch, const ulong *ld_start, ulong * const
> > ld_len)
> >  {
> > @@ -1316,9 +1316,10 @@ int boot_get_fpga(int argc, char * const argv[],
> > bootm_headers_t *images,
> >     int fit_img_result;
> >     const char *uname, *name;
> >     int err;
> > -   int devnum = 0; /* TODO support multi fpga platforms */
> > -   const fpga_desc * const desc = fpga_get_desc(devnum);
> > -   xilinx_desc *desc_xilinx = desc->devdesc;
> > +   int devnum;
> > +   const fpga_desc *desc;
> > +   xilinx_desc *desc_xilinx;
> > +   bitstream_type bstype = BIT_FULL;
> >  
> >     /* Check to see if the images struct has a FIT configuration */
> >     if (!genimg_has_config(images)) {
> > @@ -1365,26 +1366,38 @@ int boot_get_fpga(int argc, char * const argv[],
> > bootm_headers_t *images,
> >     return fit_img_result;
> >     }
> >  
> > -   if (img_len >= desc_xilinx->size)

[U-Boot] [PATCH v3 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

The implementation of boot_get_fpga only supported one fpga family.
This modification allows for any of the fpga devices supported by
fpga_load to be used.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>

--
Changes in v3:
 - Fix typos/caps in comments
Changes in v2:
 - Add fitimage support for fpga-devnum and fpga-partial-image
 - Use above in boot_get_fpga
 - for xilinx fpgas double check using image size to determine
   if image is a partial image
---
 common/image-fit.c | 51 +++
 common/image.c | 51 ---
 include/image.h|  5 +
 3 files changed, 88 insertions(+), 19 deletions(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index 109ecfa..eb0c633 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -916,6 +916,57 @@ ulong fit_get_end(const void *fit)
 }
 
 /**
+ * fit_image_fpga_get_devnum - get fpga devnum
+ * @fit: pointer to the FIT format image header
+ * @noffset: fpga node offset
+ * @devnum: pointer to an int, will hold fpga devnum
+ *
+ * fit_image_fpga_get_devnum() finds the fpga devnum for which the fpga data is
+ * intended.  If the property is not found, we default to 0.
+ *
+ * returns:
+ * 0, on devnum not found
+ * value, on devnum found
+ */
+int fit_image_fpga_get_devnum(const void *fit, int noffset, int *devnum)
+{
+   int len;
+   int *value;
+
+   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_DEVNUM_PROP, );
+   if (value == NULL || len != sizeof(int))
+   *devnum = 0;
+   else
+   *devnum = *value;
+
+   return 0;
+}
+
+/**
+ * fit_image_fpga_is_partial - is partial fpga
+ * @fit: pointer to the FIT format image header
+ * @noffset: fpga node offset
+ *
+ * fit_image_fpga_is_partial() checks if the fpga node sets the property
+ * indicating the data represents a partial fpga image.
+ *
+ * returns:
+ * 0, on devnum not found
+ * value, on devnum found
+ */
+int fit_image_fpga_is_partial(const void *fit, int noffset)
+{
+   int len;
+   int *value;
+
+   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_PARTIAL_PROP, );
+   if ((value == NULL || len != sizeof(int)) || (value == 0))
+   return 0;
+   else
+   return 1;
+}
+
+/**
  * fit_set_timestamp - set node timestamp property
  * @fit: pointer to the FIT format image header
  * @noffset: node offset
diff --git a/common/image.c b/common/image.c
index 0f88984..6480b0a 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch,
 }
 
 #if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
 int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
  uint8_t arch, const ulong *ld_start, ulong * const ld_len)
 {
@@ -1316,9 +1316,10 @@ int boot_get_fpga(int argc, char * const argv[], 
bootm_headers_t *images,
int fit_img_result;
const char *uname, *name;
int err;
-   int devnum = 0; /* TODO support multi fpga platforms */
-   const fpga_desc * const desc = fpga_get_desc(devnum);
-   xilinx_desc *desc_xilinx = desc->devdesc;
+   int devnum;
+   const fpga_desc *desc;
+   xilinx_desc *desc_xilinx;
+   bitstream_type bstype = BIT_FULL;
 
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
@@ -1365,26 +1366,38 @@ int boot_get_fpga(int argc, char * const argv[], 
bootm_headers_t *images,
return fit_img_result;
}
 
-   if (img_len >= desc_xilinx->size) {
-   name = "full";
-   err = fpga_loadbitstream(devnum, (char *)img_data,
-img_len, BIT_FULL);
-   if (err)
-   err = fpga_load(devnum, (const void *)img_data,
-   img_len, BIT_FULL);
-   } else {
-   name = "partial";
-   err = fpga_loadbitstream(devnum, (char *)img_data,
-img_len, BIT_PARTIAL);
-   if (err)
-   err = fpga_load(devnum, (const void *)img_data,
-   img_len, BIT_PARTIAL);
+   /* Get FPGA device number, defaults to 0 */
+   fit_image_fpga_get_devnum(buf, conf_noffset, );
+
+   /* Check bitstream type */
+   if (fit_image_fpga_is_partial(buf, conf_noffset))
+   bstype = BIT_PARTIAL;
+
+   /* Legacy support detecting partial config files for Xilinx */
+   desc = fpga_get_desc(devnum);
+   if (desc->devtype == fpga_xilinx

[U-Boot] [PATCH v3 2/2] common: bootm: add support for arbitrary fgpa configuration

[Dalon Westergreen]

This adds support for fpga configuration data in fitimages for
any fpga device supported by fpga_load.  At this point fitimages
only support configuration of fpga images for fpga devnum 0.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
---
 common/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index b2c0912..4a4b47c 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -248,7 +248,7 @@ int bootm_find_images(int flag, int argc, char * const 
argv[])
 #endif
 
 #if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
/* find bitstreams */
ret = boot_get_fpga(argc, argv, , IH_ARCH_DEFAULT,
NULL, NULL);
-- 
2.7.4

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[U-Boot] [PATCH v3 0/2] common: fitimage support for arbitrary fpga type

[Dalon Westergreen]

The intent of these patches is to modify existing fitimage support for
fpga configuration to allow configuration of any fpga type supported
by the fpga_load command.
 
In the fpga node, two additional optional parameters are used to indicate
the fpga device number (for systems with multiple fpgas) and whether the fpga
image is a full or partial image.
 
fpga-devnum: FPGA device number, defaults to 0
fpga-partial-image: 0 = full, other = partial, defaults to full

Changes in v3:
 - Fix typos and caps in comments 
Changes in v2:
 - Add support for devnum and partial
 - for backward compatibility, do check of image size for xilinx to determine
   if the image is a partial image

Dalon Westergreen (2):
  common: image: update boot_get_fpga to support arbitrary fpga image
  common: bootm: add support for arbitrary fgpa configuration

 common/bootm.c |  2 +-
 common/image-fit.c | 51 +++
 common/image.c | 51 ---
 include/image.h|  5 +
 4 files changed, 89 insertions(+), 20 deletions(-)

-- 
2.7.4

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Re: [U-Boot] [PATCH v2 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Mon, 2017-02-20 at 09:14 +0100, Marek Vasut wrote:
> On 02/20/2017 04:35 AM, Dalon Westergreen wrote:
> > 
> > The implementation of boot_get_fpga only supported one fpga family.
> > This modification allows for any of the fpga devices supported by
> > fpga_load to be used.
> > 
> > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> 
> IMO looks OK, minor nits below
> 
> > 
> > --
> > Changes in v2:
> >  - Add fitimage support for fpga-devnum and fpga-partial-image
> >  - Use above in boot_get_fpga
> >  - for xilinx fpgas double check using image size to determine
> >    if image is a partial image
> > ---
> >  common/image-fit.c | 51 +++
> >  common/image.c | 51 ---
> >  include/image.h|  5 +
> >  3 files changed, 88 insertions(+), 19 deletions(-)
> > 
> > diff --git a/common/image-fit.c b/common/image-fit.c
> > index 109ecfa..eb0c633 100644
> > --- a/common/image-fit.c
> > +++ b/common/image-fit.c
> > @@ -916,6 +916,57 @@ ulong fit_get_end(const void *fit)
> >  }
> >  
> > 
[...]
> > 
> > +   fit_image_fpga_get_devnum(buf, conf_noffset, );
> > +
> > +   /* check bitstream type */
> 
> At least start the sentence with capital letter please.
> 
> > 
> > +   if (fit_image_fpga_is_partial(buf, conf_noffset))
> > +   bstype = BIT_PARTIAL;
> 
> Are there any chances there will be something else besides full and
> partial in the future ?

It's plausible but i think not a likely use case here. In Arria10 there is the
periphery/core image that configures just the io or fpga core.  I believe,
though, that this is just a special case of a partial image and is treated the
same.

--dalon

> 
> > 
> > +   /* legacy support detecting partial config files for xilinx
> > */
> 
> DTTO, start with caps.
> 
> > 
> > +   desc = fpga_get_desc(devnum);
> > +   if (desc->devtype == fpga_xilinx) {
> > +   desc_xilinx = desc->devdesc;
> > +   if (img_len < desc_xilinx->size)
> > +   bstype = BIT_PARTIAL;
> >     }
> >  
> > +   /* Try bitstream format first */
> > +   err = fpga_loadbitstream(devnum, (char *)img_data,
> > +    img_len, bstype);
> > +   if (err)
> > +   err = fpga_load(devnum, (const void *)img_data,
> > +   img_len, bstype);
> > +
> >     if (err)
> >     return err;
> >  
> > -   printf("   Programming %s bitstream... OK\n", name);
> > +   if (bstype == BIT_PARTIAL)
> > +   name = "partial";
> > +   else
> > +   name = "full";
> > +
> > +   printf("   Programming %s bitstream into fpga %d... OK\n",
> > +      name, devnum);
> >     break;
> >     default:
> >     printf("The given image format is not supported
> > (corrupt?)\n");
> > diff --git a/include/image.h b/include/image.h
> > index 1e686b7..75d2afc 100644
> > --- a/include/image.h
> > +++ b/include/image.h
> > @@ -876,6 +876,8 @@ int bootz_setup(ulong image, ulong *start, ulong *end);
> >  #define FIT_COMP_PROP  "compression"
> >  #define FIT_ENTRY_PROP "entry"
> >  #define FIT_LOAD_PROP  "load"
> > +#define FIT_FPGA_DEVNUM_PROP   "fpga-devnum"
> > +#define FIT_FPGA_PARTIAL_PROP  "fpga-partial-image"
> >  
> >  /* configuration node */
> >  #define FIT_KERNEL_PROP"kernel"
> > @@ -955,6 +957,9 @@ int fit_image_hash_get_value(const void *fit, int
> > noffset, uint8_t **value,
> >  
> >  int fit_set_timestamp(void *fit, int noffset, time_t timestamp);
> >  
> > +int fit_image_fpga_get_devnum(const void *fit, int noffset, int *devnum);
> > +int fit_image_fpga_is_partial(const void *fit, int noffset);
> > +
> >  /**
> >   * fit_add_verification_data() - add verification data to FIT image nodes
> >   *
> > 
> 
> 
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Re: [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Mon, 2017-02-20 at 15:24 +0100, Marek Vasut wrote:
> On 02/20/2017 03:21 PM, Dalon Westergreen wrote:
> > 
> > On Mon, 2017-02-20 at 15:14 +0100, Marek Vasut wrote:
> > > 
> > > On 02/20/2017 03:10 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > On Mon, 2017-02-20 at 10:07 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 02/18/2017 02:34 AM, Dalon Westergreen wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > configuration for the device.  This can lead to a boot failure
> > > > > > on warm resets. This patch disables warm resets when CSEL=0.
> > > > > > This results in the clock and pll configurations being reset
> > > > > > on any reset issued when CSEL=0.
> > > > > > 
> > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > 
> > > > > What about my suggestion for V2 about just loading function pointer
> > > > > into
> > > > > the reset jump address register ?
> > > > 
> > > > Frankly, i really dont like relying on the existence of a snippet of
> > > > code in
> > > > the
> > > > onchip ram being untouched to ensure a reboot/reset will occur for this
> > > > csel=0
> > > > case.  i am certain this case is rarely used, and confident that it isnt
> > > > being
> > > > used while trying to preserve sdram contents.
> > > 
> > > Well, you already rely on such snippet, it's SPL. If you corrupt SPL and
> > > do warm reset, your system hangs, I had that multiple times :)
> > 
> > True.  I would argue to just use cold resets but i think arria 10 has more
> > use
> > for the warm reset case.
> 
> OK
> 
> > 
> > > 
> > > > 
> > > > 
> > > > the downside is that the scorecard is reset every boot. so the bootrom
> > > > will
> > > > retry all the spl images again resulting in possibly longer boot times.
> > > 
> > > Is that significant ?
> > 
> > The watchdog timeout is on the order of 1.5 seconds.  That would be for each
> > failed spl.
> 
> Hm, OK. But then your system is kinda broken, so you should expect this
> I guess.

My thought exactly...  I would like to see if Chin Liang or Dinh have any
comments?

> 
> [...]
> 
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Re: [U-Boot] Enable AXI bridges

[Dalon Westergreen]

On Sun, 2017-02-19 at 10:03 +0200, Hossameldin Eassa wrote:
> when i run the following command from u-boot console
> 
> run bridge_enable_handoff;
> 
> 
> i have the following error
> 
> Error: "bridge_enable_handoff" not defined

In mainline uboot just do

bridge enable

or 

bridge disable

at least for the cyclone v / arria v

--dalon

> I need help to enable AXI bridge from u-boot
> 
> Beast Regards
> Hossameldin
> 
> 
>   Sent with Mailtrack
>  ail.com=22>
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Re: [U-Boot] [PATCH 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Mon, 2017-02-20 at 10:22 +0100, Michal Simek wrote:
> On 19.2.2017 21:58, Dalon Westergreen wrote:
> > 
> > On Sun, 2017-02-19 at 21:49 +0100, Marek Vasut wrote:
> > > 
> > > On 02/19/2017 09:43 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > On Sun, 2017-02-19 at 21:07 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 02/19/2017 08:49 PM, Dalon Westergreen wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > The implementation of boot_get_fpga only supported one fpga family.
> > > > > > This modification allows for any of the fpga devices supported by
> > > > > > fpga_load to be used.
> > > > > > 
> > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > 
> > > > > +CC Xilinx friends :)
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  common/image.c | 37 ++---
> > > > > >  1 file changed, 22 insertions(+), 15 deletions(-)
> > > > > > 
> > > > > > diff --git a/common/image.c b/common/image.c
> > > > > > index 0f88984..792d371 100644
> > > > > > --- a/common/image.c
> > > > > > +++ b/common/image.c
> > > > > > @@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images,
> > > > > > uint8_t
> > > > > > arch,
> > > > > >  }
> > > > > >  
> > > > > >  #if IMAGE_ENABLE_FIT
> > > > > > -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
> > > > > > +#if defined(CONFIG_FPGA)
> > > > > >  int boot_get_fpga(int argc, char * const argv[], bootm_headers_t
> > > > > > *images,
> > > > > >       uint8_t arch, const ulong *ld_start, ulong *
> > > > > > const
> > > > > > ld_len)
> > > > > >  {
> > > > > > @@ -1318,7 +1318,8 @@ int boot_get_fpga(int argc, char * const
> > > > > > argv[],
> > > > > > bootm_headers_t *images,
> > > > > >     int err;
> > > > > >     int devnum = 0; /* TODO support multi fpga platforms */
> > > > > >     const fpga_desc * const desc = fpga_get_desc(devnum);
> > > > > > -   xilinx_desc *desc_xilinx = desc->devdesc;
> > > > > > +   xilinx_desc *desc_xilinx;
> > > > > > +   bitstream_type bstype;
> > > > > >  
> > > > > >     /* Check to see if the images struct has a FIT
> > > > > > configuration */
> > > > > >     if (!genimg_has_config(images)) {
> > > > > > @@ -1365,22 +1366,28 @@ int boot_get_fpga(int argc, char * const
> > > > > > argv[],
> > > > > > bootm_headers_t *images,
> > > > > >     return fit_img_result;
> > > > > >     }
> > > > > >  
> > > > > > -   if (img_len >= desc_xilinx->size) {
> > > > > > +   switch (desc->devtype) {
> > > > > 
> > > > > Do we need the switch statement at all ? We can have full
> > > > > configuration
> > > > > as a default mode of operation and have something like
> > > > > 
> > > > > if (xilinx) {
> > > > >  if (partial reconfiguration) {
> > > > >   do_special_setup();
> > > > >  }
> > > > > }
> > > > 
> > > > I only did the switch stuff b/c i envisioned a need for partial image
> > > > support for socfpga.
> > > 
> > > That'd be seriously cool :)
> > > 
> > > > 
> > > > 
> > > > That said, i would suggest, as you mention, moving
> > > > this to platform specific code and perhaps an indication of the image
> > > > type
> > > > in the fitimage.
> > > 
> > > driver-specific code . It doesn't need to know the imagetype, just that
> > > the blob that you passed in is a partial-reconfiguration blob. I never
> > > really worked with P/R though, do you need some other metadata for that
> > > or is it contained in that P/R bitstream blob already ?
> > 
> > as far as i understand it, it is all in the blob.  All that is needed is
> > knowing
> > whether the blob is a full or partial image.  X seems to just use the image
> > size
> > to determine this, but that means having a table of all devices and their
> > respective full image size.  seems simpler to just specify the image type is
> > partial or not in the fitimage.
> 
> We did that for zynq when we did that for the first time. But not for
> zynqmp. Zynq is maybe still using it but it shouldn't now. It is not
> 100% reliable way. Definitely having DT property is the best option
> because you can add sort of "nop" which extend bitstream size and does
> nothing which breaks that checking.
> 
> For full u-boot there is loadb, loadbp, load and loadp to distinguish it.

That brings up an interesting point, right now the fpga_loadbitstream doesn't
follow the same method as fpga_load for allowing multiple FPGA types to be
supported simultaneously.  Would it not be prudent to move in that direction?
I believe only xilinx implements this right now.

--dalon

> Thanks,
> Michal
> 
> Thanks,
> Michal
> 
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Re: [U-Boot] [PATCH 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Mon, 2017-02-20 at 10:24 +0100, Michal Simek wrote:
> On 19.2.2017 22:26, Marek Vasut wrote:
> > 
> > On 02/19/2017 10:21 PM, Dalon Westergreen wrote:
> > > 
> > > On Sun, 2017-02-19 at 22:12 +0100, Marek Vasut wrote:
> > > > 
> > > > On 02/19/2017 09:58 PM, Dalon Westergreen wrote:
> > > > > 
> > > > > 
> > > > > On Sun, 2017-02-19 at 21:49 +0100, Marek Vasut wrote:
> > > > > > 
> > > > > > 
> > > > > > On 02/19/2017 09:43 PM, Dalon Westergreen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On Sun, 2017-02-19 at 21:07 +0100, Marek Vasut wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On 02/19/2017 08:49 PM, Dalon Westergreen wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > The implementation of boot_get_fpga only supported one fpga
> > > > > > > > > family.
> > > > > > > > > This modification allows for any of the fpga devices supported
> > > > > > > > > by
> > > > > > > > > fpga_load to be used.
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > > > > 
> > > > > > > > +CC Xilinx friends :)
> > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > ---
> > > > > > > > >  common/image.c | 37 ++---
> > > > > > > > >  1 file changed, 22 insertions(+), 15 deletions(-)
> > > > > > > > > 
> > > > > > > > > diff --git a/common/image.c b/common/image.c
> > > > > > > > > index 0f88984..792d371 100644
> > > > > > > > > --- a/common/image.c
> > > > > > > > > +++ b/common/image.c
> > > > > > > > > @@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t
> > > > > > > > > *images,
> > > > > > > > > uint8_t
> > > > > > > > > arch,
> > > > > > > > >  }
> > > > > > > > >  
> > > > > > > > >  #if IMAGE_ENABLE_FIT
> > > > > > > > > -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
> > > > > > > > > +#if defined(CONFIG_FPGA)
> > > > > > > > >  int boot_get_fpga(int argc, char * const argv[],
> > > > > > > > > bootm_headers_t
> > > > > > > > > *images,
> > > > > > > > >     uint8_t arch, const ulong *ld_start, ulong
> > > > > > > > > *
> > > > > > > > > const
> > > > > > > > > ld_len)
> > > > > > > > >  {
> > > > > > > > > @@ -1318,7 +1318,8 @@ int boot_get_fpga(int argc, char * const
> > > > > > > > > argv[],
> > > > > > > > > bootm_headers_t *images,
> > > > > > > > >   int err;
> > > > > > > > >   int devnum = 0; /* TODO support multi fpga platforms
> > > > > > > > > */
> > > > > > > > >   const fpga_desc * const desc = fpga_get_desc(devnum);
> > > > > > > > > - xilinx_desc *desc_xilinx = desc->devdesc;
> > > > > > > > > + xilinx_desc *desc_xilinx;
> > > > > > > > > + bitstream_type bstype;
> > > > > > > > >  
> > > > > > > > >   /* Check to see if the images struct has a FIT
> > > > > > > > > configuration */
> > > > > > > > >   if (!genimg_has_config(images)) {
> > > > > > > > > @@ -1365,22 +1366,28 @@ int boot_get_fpga(int argc, char *
> > > > &g

Re: [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Mon, 2017-02-20 at 15:14 +0100, Marek Vasut wrote:
> On 02/20/2017 03:10 PM, Dalon Westergreen wrote:
> > 
> > On Mon, 2017-02-20 at 10:07 +0100, Marek Vasut wrote:
> > > 
> > > On 02/18/2017 02:34 AM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > configuration for the device.  This can lead to a boot failure
> > > > on warm resets. This patch disables warm resets when CSEL=0.
> > > > This results in the clock and pll configurations being reset
> > > > on any reset issued when CSEL=0.
> > > > 
> > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > 
> > > What about my suggestion for V2 about just loading function pointer into
> > > the reset jump address register ?
> > 
> > Frankly, i really dont like relying on the existence of a snippet of code in
> > the
> > onchip ram being untouched to ensure a reboot/reset will occur for this
> > csel=0
> > case.  i am certain this case is rarely used, and confident that it isnt
> > being
> > used while trying to preserve sdram contents.
> 
> Well, you already rely on such snippet, it's SPL. If you corrupt SPL and
> do warm reset, your system hangs, I had that multiple times :)

True.  I would argue to just use cold resets but i think arria 10 has more use
for the warm reset case.

> > 
> > the downside is that the scorecard is reset every boot. so the bootrom will
> > retry all the spl images again resulting in possibly longer boot times.
> 
> Is that significant ?

The watchdog timeout is on the order of 1.5 seconds.  That would be for each
failed spl.

> > 
> > The
> > other is that things like sdram content preservation is not likely to work
> > or
> > the csel=0 case (but as i mentioned, i dont see this used often in cyclone5,
> > and never have i seen it when csel=0).
> 
> OK, I didn't see this requirement yet.
> 
> > 
> > > 
> > > btw --- missing before the changelog, without it the changelog will land
> > > in git history.
> > 
> > Thanks
> > 
> > > 
> > > > 
> > > > 
> > > > Changes in v3:
> > > >  - Change implementation to rely on cold reset for CSEL=0. Which
> > > >    is a much simpler approach to dealing with this special case
> > > >    during boot.
> > > > Changes in v2:
> > > >  - Fix checkpatch issues predominently due to whitespace issues
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/system_manager.h |  3 +++
> > > >  arch/arm/mach-socfpga/misc.c| 13 -
> > > >  2 files changed, 15 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > > > b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > > > index c45edea..c9c0b33 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > > > @@ -137,6 +137,9 @@ struct socfpga_system_manager {
> > > >  
> > > >  #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
> > > >  
> > > > +#define SYSMGR_BOOTINFO_CSEL_MASK  0x18
> > > > +#define SYSMGR_BOOTINFO_CSEL_LSB   3
> > > > +
> > > >  /* EMAC Group Bit definitions */
> > > >  #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII   0x0
> > > >  #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII  0x1
> > > > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> > > > index dd6b53b..9792138 100644
> > > > --- a/arch/arm/mach-socfpga/misc.c
> > > > +++ b/arch/arm/mach-socfpga/misc.c
> > > > @@ -356,6 +356,7 @@ static uint32_t iswgrp_handoff[8];
> > > >  int arch_early_init_r(void)
> > > >  {
> > > >     int i;
> > > > +   unsigned int csel;
> > > >  
> > > >     /*
> > > >      * Write magic value into magic register to unlock support for
> > > > @@ -363,8 +364,18 @@ int arch_early_init_r(void)
> > > >      * value to be written into the register by the bootloader, so
> > > >      * to support that old code, we write it here instead of in the
> > > >      * reset_cpu() function just before resetting the CPU.
> > > > + 

Re: [U-Boot] [PATCH v3] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Mon, 2017-02-20 at 10:07 +0100, Marek Vasut wrote:
> On 02/18/2017 02:34 AM, Dalon Westergreen wrote:
> > 
> > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > configuration for the device.  This can lead to a boot failure
> > on warm resets. This patch disables warm resets when CSEL=0.
> > This results in the clock and pll configurations being reset
> > on any reset issued when CSEL=0.
> > 
> > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> 
> What about my suggestion for V2 about just loading function pointer into
> the reset jump address register ?

Frankly, i really dont like relying on the existence of a snippet of code in the
onchip ram being untouched to ensure a reboot/reset will occur for this csel=0
case.  i am certain this case is rarely used, and confident that it isnt being
used while trying to preserve sdram contents.

the downside is that the scorecard is reset every boot. so the bootrom will
retry all the spl images again resulting in possibly longer boot times.  The
other is that things like sdram content preservation is not likely to work or
the csel=0 case (but as i mentioned, i dont see this used often in cyclone5,
and never have i seen it when csel=0).

> btw --- missing before the changelog, without it the changelog will land
> in git history.

Thanks

> > 
> > Changes in v3:
> >  - Change implementation to rely on cold reset for CSEL=0. Which
> >    is a much simpler approach to dealing with this special case
> >    during boot.
> > Changes in v2:
> >  - Fix checkpatch issues predominently due to whitespace issues
> > ---
> >  arch/arm/mach-socfpga/include/mach/system_manager.h |  3 +++
> >  arch/arm/mach-socfpga/misc.c| 13 -
> >  2 files changed, 15 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > index c45edea..c9c0b33 100644
> > --- a/arch/arm/mach-socfpga/include/mach/system_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h
> > @@ -137,6 +137,9 @@ struct socfpga_system_manager {
> >  
> >  #define SYSMGR_SDMMC_DRVSEL_SHIFT  0
> >  
> > +#define SYSMGR_BOOTINFO_CSEL_MASK  0x18
> > +#define SYSMGR_BOOTINFO_CSEL_LSB   3
> > +
> >  /* EMAC Group Bit definitions */
> >  #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII   0x0
> >  #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII  0x1
> > diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
> > index dd6b53b..9792138 100644
> > --- a/arch/arm/mach-socfpga/misc.c
> > +++ b/arch/arm/mach-socfpga/misc.c
> > @@ -356,6 +356,7 @@ static uint32_t iswgrp_handoff[8];
> >  int arch_early_init_r(void)
> >  {
> >     int i;
> > +   unsigned int csel;
> >  
> >     /*
> >      * Write magic value into magic register to unlock support for
> > @@ -363,8 +364,18 @@ int arch_early_init_r(void)
> >      * value to be written into the register by the bootloader, so
> >      * to support that old code, we write it here instead of in the
> >      * reset_cpu() function just before resetting the CPU.
> > +    *
> > +    * For CSEL = 0 we do not want to enable warm resets to ensure that
> > +    * on reset the clocks and plls are reset to their default states
> > as
> > +    * the bootrom, for CSEL=0, leaves the clocks untouched.  If the
> > clocks
> > +    * and plls are not reset, the bootrom will fail to load the spl
> > image.
> >      */
> > -   writel(0xae9efebc, _regs->romcodegrp_warmramgrp_enable);
> > +
> > +   csel = (readl(_regs->bootinfo) & SYSMGR_BOOTINFO_CSEL_MASK)
> > >>
> > +   SYSMGR_BOOTINFO_CSEL_LSB;
> > +
> > +   if (csel)
> > +   writel(0xae9efebc, _regs-
> > >romcodegrp_warmramgrp_enable);
> >  
> >     for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
> >     iswgrp_handoff[i] = readl(_regs->iswgrp_handoff[i]);
> > 
> 
> 
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Re: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0

[Dalon Westergreen]

On Sun, 2017-02-19 at 22:31 +0100, Marek Vasut wrote:
> On 02/18/2017 12:24 AM, Dalon Westergreen wrote:
> > 
> > On Fri, 2017-02-17 at 22:16 +0100, Marek Vasut wrote:
> > > 
> > > On 02/17/2017 07:05 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > On Wed, 2017-02-15 at 18:53 -0800, Dalon Westergreen wrote:
> > > > > 
> > > > > 
> > > > > On Wed, 2017-02-15 at 23:20 +0100, Marek Vasut wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On 02/15/2017 10:48 PM, Dalon Westergreen wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On Wed, 2017-02-15 at 22:15 +0100, Marek Vasut wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On 02/14/2017 07:28 PM, Dalon Westergreen wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > When CSEL=0x0 the socfpga bootrom does not touch the clock
> > > > > > > > > configuration for the device.  This can lead to a boot failure
> > > > > > > > > on warm resets.  To address this, the bootrom is configured to
> > > > > > > > > run a bit of code in the last 4KB of onchip ram on a warm
> > > > > > > > > reset.
> > > > > > > > > This code puts the PLLs in bypass, disables the bootrom
> > > > > > > > > configuration
> > > > > > > > > to run the code snippet, and issues a warm reset to run the
> > > > > > > > > bootrom.
> > > > > > > > > 
> > > > > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > > > > > 
> > > > > > > > > --
> > > > > > > > > Changes in V2:
> > > > > > > > >  - Fix checkpatch issues predominently due to whitespace
> > > > > > > > > issues
> > > > > > > > > ---
> > > > > > > > >  arch/arm/mach-socfpga/Makefile |  2 +-
> > > > > > > > >  arch/arm/mach-socfpga/include/mach/clock_manager.h | 26
> > > > > > > > > +++-
> > > > > > > > >  arch/arm/mach-socfpga/include/mach/reset_manager.h |  4 ++
> > > > > > > > >  .../arm/mach-socfpga/include/mach/system_manager.h |  7 ++-
> > > > > > > > >  arch/arm/mach-socfpga/misc.c   | 27
> > > > > > > > > 
> > > > > > > > >  arch/arm/mach-socfpga/reset_clock_manager.S| 71
> > > > > > > > > ++
> > > > > > > > >  6 files changed, 134 insertions(+), 3 deletions(-)
> > > > > > > > >  create mode 100644 arch/arm/mach-
> > > > > > > > > socfpga/reset_clock_manager.S
> > > > > > > > > 
> > > > > > > > > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > > > > > > > > socfpga/Makefile
> > > > > > > > > index 809cd47..6876ccf 100644
> > > > > > > > > --- a/arch/arm/mach-socfpga/Makefile
> > > > > > > > > +++ b/arch/arm/mach-socfpga/Makefile
> > > > > > > > > @@ -8,7 +8,7 @@
> > > > > > > > >  #
> > > > > > > > >  
> > > > > > > > >  obj-y+= misc.o timer.o reset_manager.o
> > > > > > > > > system_manager.o
> > > > > > > > > clock_manager.o \
> > > > > > > > > -    fpga_manager.o board.o
> > > > > > > > > +    fpga_manager.o board.o reset_clock_manager.o
> > > > > > > > >  

[U-Boot] [PATCH v2 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

The implementation of boot_get_fpga only supported one fpga family.
This modification allows for any of the fpga devices supported by
fpga_load to be used.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>

--
Changes in v2:
 - Add fitimage support for fpga-devnum and fpga-partial-image
 - Use above in boot_get_fpga
 - for xilinx fpgas double check using image size to determine
   if image is a partial image
---
 common/image-fit.c | 51 +++
 common/image.c | 51 ---
 include/image.h|  5 +
 3 files changed, 88 insertions(+), 19 deletions(-)

diff --git a/common/image-fit.c b/common/image-fit.c
index 109ecfa..eb0c633 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -916,6 +916,57 @@ ulong fit_get_end(const void *fit)
 }
 
 /**
+ * fit_image_fpga_get_devnum - get fpga devnum
+ * @fit: pointer to the FIT format image header
+ * @noffset: fpga node offset
+ * @devnum: pointer to an int, will hold fpga devnum
+ *
+ * fit_image_fpga_get_devnum() finds the fpga devnum for which the fpga data is
+ * intended.  If the property is not found, we default to 0.
+ *
+ * returns:
+ * 0, on devnum not found
+ * value, on devnum found
+ */
+int fit_image_fpga_get_devnum(const void *fit, int noffset, int *devnum)
+{
+   int len;
+   int *value;
+
+   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_DEVNUM_PROP, );
+   if (value == NULL || len != sizeof(int))
+   *devnum = 0;
+   else
+   *devnum = *value;
+
+   return 0;
+}
+
+/**
+ * fit_image_fpga_is_partial - is partial fpga
+ * @fit: pointer to the FIT format image header
+ * @noffset: fpga node offset
+ *
+ * fit_image_fpga_is_partial() checks if the fpga node sets the property
+ * indicating the data represents a partial fpga image.
+ *
+ * returns:
+ * 0, on devnum not found
+ * value, on devnum found
+ */
+int fit_image_fpga_is_partial(const void *fit, int noffset)
+{
+   int len;
+   int *value;
+
+   value = (int *)fdt_getprop(fit, noffset, FIT_FPGA_PARTIAL_PROP, );
+   if ((value == NULL || len != sizeof(int)) || (value == 0))
+   return 0;
+   else
+   return 1;
+}
+
+/**
  * fit_set_timestamp - set node timestamp property
  * @fit: pointer to the FIT format image header
  * @noffset: node offset
diff --git a/common/image.c b/common/image.c
index 0f88984..6a3d2c3 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch,
 }
 
 #if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
 int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
  uint8_t arch, const ulong *ld_start, ulong * const ld_len)
 {
@@ -1316,9 +1316,10 @@ int boot_get_fpga(int argc, char * const argv[], 
bootm_headers_t *images,
int fit_img_result;
const char *uname, *name;
int err;
-   int devnum = 0; /* TODO support multi fpga platforms */
-   const fpga_desc * const desc = fpga_get_desc(devnum);
-   xilinx_desc *desc_xilinx = desc->devdesc;
+   int devnum;
+   const fpga_desc *desc;
+   xilinx_desc *desc_xilinx;
+   bitstream_type bstype = BIT_FULL;
 
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
@@ -1365,26 +1366,38 @@ int boot_get_fpga(int argc, char * const argv[], 
bootm_headers_t *images,
return fit_img_result;
}
 
-   if (img_len >= desc_xilinx->size) {
-   name = "full";
-   err = fpga_loadbitstream(devnum, (char *)img_data,
-img_len, BIT_FULL);
-   if (err)
-   err = fpga_load(devnum, (const void *)img_data,
-   img_len, BIT_FULL);
-   } else {
-   name = "partial";
-   err = fpga_loadbitstream(devnum, (char *)img_data,
-img_len, BIT_PARTIAL);
-   if (err)
-   err = fpga_load(devnum, (const void *)img_data,
-   img_len, BIT_PARTIAL);
+   /* Get fpga devnum, defaults to 0 */
+   fit_image_fpga_get_devnum(buf, conf_noffset, );
+
+   /* check bitstream type */
+   if (fit_image_fpga_is_partial(buf, conf_noffset))
+   bstype = BIT_PARTIAL;
+
+   /* legacy support detecting partial config files for xilinx */
+   desc = fpga_get_desc(devnum);
+   if (desc->devtype == fpga_xilinx) {
+   desc_xilinx = desc

[U-Boot] [PATCH v2 2/2] common: bootm: add support for arbitrary fgpa configuration

[Dalon Westergreen]

This adds support for fpga configuration data in fitimages for
any fpga device supported by fpga_load.  At this point fitimages
only support configuration of fpga images for fpga devnum 0.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
---
 common/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index b2c0912..4a4b47c 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -248,7 +248,7 @@ int bootm_find_images(int flag, int argc, char * const 
argv[])
 #endif
 
 #if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
/* find bitstreams */
ret = boot_get_fpga(argc, argv, , IH_ARCH_DEFAULT,
NULL, NULL);
-- 
2.7.4

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[U-Boot] [PATCH v2 0/2] common: fitimage support for arbitrary fpga type

[Dalon Westergreen]

The intent of these patches is to modify existing fitimage support for
fpga configuration to allow configuration of any fpga type supported
by the fpga_load command.
 
In the fpga node, two additional optional parameters are used to indicate
the fpga device number (for systems with multiple fpgas) and whether the fpga
image is a full or partial image.
 
fpga-devnum: FPGA device number, defaults to 0
fpga-partial-image: 0 = full, other = partial, defaults to full
 
Changes in v2:
 - Add support for devnum and partial
 - for backward compatibility, do check of image size for xilinx to determine
   if the image is a partial image

Dalon Westergreen (2):
  common: image: update boot_get_fpga to support arbitrary fpga image
  common: bootm: add support for arbitrary fgpa configuration

 common/bootm.c |  2 +-
 common/image-fit.c | 51 +++
 common/image.c | 51 ---
 include/image.h|  5 +
 4 files changed, 89 insertions(+), 20 deletions(-)

-- 
2.7.4

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Re: [U-Boot] [PATCH 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Sun, 2017-02-19 at 22:12 +0100, Marek Vasut wrote:
> On 02/19/2017 09:58 PM, Dalon Westergreen wrote:
> > 
> > On Sun, 2017-02-19 at 21:49 +0100, Marek Vasut wrote:
> > > 
> > > On 02/19/2017 09:43 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > On Sun, 2017-02-19 at 21:07 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 02/19/2017 08:49 PM, Dalon Westergreen wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > The implementation of boot_get_fpga only supported one fpga family.
> > > > > > This modification allows for any of the fpga devices supported by
> > > > > > fpga_load to be used.
> > > > > > 
> > > > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > > > 
> > > > > +CC Xilinx friends :)
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > ---
> > > > > >  common/image.c | 37 ++---
> > > > > >  1 file changed, 22 insertions(+), 15 deletions(-)
> > > > > > 
> > > > > > diff --git a/common/image.c b/common/image.c
> > > > > > index 0f88984..792d371 100644
> > > > > > --- a/common/image.c
> > > > > > +++ b/common/image.c
> > > > > > @@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images,
> > > > > > uint8_t
> > > > > > arch,
> > > > > >  }
> > > > > >  
> > > > > >  #if IMAGE_ENABLE_FIT
> > > > > > -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
> > > > > > +#if defined(CONFIG_FPGA)
> > > > > >  int boot_get_fpga(int argc, char * const argv[], bootm_headers_t
> > > > > > *images,
> > > > > >       uint8_t arch, const ulong *ld_start, ulong *
> > > > > > const
> > > > > > ld_len)
> > > > > >  {
> > > > > > @@ -1318,7 +1318,8 @@ int boot_get_fpga(int argc, char * const
> > > > > > argv[],
> > > > > > bootm_headers_t *images,
> > > > > >     int err;
> > > > > >     int devnum = 0; /* TODO support multi fpga platforms */
> > > > > >     const fpga_desc * const desc = fpga_get_desc(devnum);
> > > > > > -   xilinx_desc *desc_xilinx = desc->devdesc;
> > > > > > +   xilinx_desc *desc_xilinx;
> > > > > > +   bitstream_type bstype;
> > > > > >  
> > > > > >     /* Check to see if the images struct has a FIT
> > > > > > configuration */
> > > > > >     if (!genimg_has_config(images)) {
> > > > > > @@ -1365,22 +1366,28 @@ int boot_get_fpga(int argc, char * const
> > > > > > argv[],
> > > > > > bootm_headers_t *images,
> > > > > >     return fit_img_result;
> > > > > >     }
> > > > > >  
> > > > > > -   if (img_len >= desc_xilinx->size) {
> > > > > > +   switch (desc->devtype) {
> > > > > 
> > > > > Do we need the switch statement at all ? We can have full
> > > > > configuration
> > > > > as a default mode of operation and have something like
> > > > > 
> > > > > if (xilinx) {
> > > > >  if (partial reconfiguration) {
> > > > >   do_special_setup();
> > > > >  }
> > > > > }
> > > > 
> > > > I only did the switch stuff b/c i envisioned a need for partial image
> > > > support for socfpga.
> > > 
> > > That'd be seriously cool :)
> > > 
> > > > 
> > > > 
> > > > That said, i would suggest, as you mention, moving
> > > > this to platform specific code and perhaps an indication of the image
> > > > type
> > > > in the fitimage.
> > > 
> > > driver-specific code . It doesn't need to know the imagetype, just that
> > > the blob that you passed in is a partial-reconfiguration blob. I never
> > > really worked with P/R though, do you need some other metadata for that
> > > or is it contained in that P/R bitstream

Re: [U-Boot] [PATCH 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Sun, 2017-02-19 at 21:49 +0100, Marek Vasut wrote:
> On 02/19/2017 09:43 PM, Dalon Westergreen wrote:
> > 
> > On Sun, 2017-02-19 at 21:07 +0100, Marek Vasut wrote:
> > > 
> > > On 02/19/2017 08:49 PM, Dalon Westergreen wrote:
> > > > 
> > > > 
> > > > The implementation of boot_get_fpga only supported one fpga family.
> > > > This modification allows for any of the fpga devices supported by
> > > > fpga_load to be used.
> > > > 
> > > > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > > 
> > > +CC Xilinx friends :)
> > > 
> > > > 
> > > > 
> > > > ---
> > > >  common/image.c | 37 ++---
> > > >  1 file changed, 22 insertions(+), 15 deletions(-)
> > > > 
> > > > diff --git a/common/image.c b/common/image.c
> > > > index 0f88984..792d371 100644
> > > > --- a/common/image.c
> > > > +++ b/common/image.c
> > > > @@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images,
> > > > uint8_t
> > > > arch,
> > > >  }
> > > >  
> > > >  #if IMAGE_ENABLE_FIT
> > > > -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
> > > > +#if defined(CONFIG_FPGA)
> > > >  int boot_get_fpga(int argc, char * const argv[], bootm_headers_t
> > > > *images,
> > > >       uint8_t arch, const ulong *ld_start, ulong * const
> > > > ld_len)
> > > >  {
> > > > @@ -1318,7 +1318,8 @@ int boot_get_fpga(int argc, char * const argv[],
> > > > bootm_headers_t *images,
> > > >     int err;
> > > >     int devnum = 0; /* TODO support multi fpga platforms */
> > > >     const fpga_desc * const desc = fpga_get_desc(devnum);
> > > > -   xilinx_desc *desc_xilinx = desc->devdesc;
> > > > +   xilinx_desc *desc_xilinx;
> > > > +   bitstream_type bstype;
> > > >  
> > > >     /* Check to see if the images struct has a FIT configuration */
> > > >     if (!genimg_has_config(images)) {
> > > > @@ -1365,22 +1366,28 @@ int boot_get_fpga(int argc, char * const argv[],
> > > > bootm_headers_t *images,
> > > >     return fit_img_result;
> > > >     }
> > > >  
> > > > -   if (img_len >= desc_xilinx->size) {
> > > > +   switch (desc->devtype) {
> > > 
> > > Do we need the switch statement at all ? We can have full configuration
> > > as a default mode of operation and have something like
> > > 
> > > if (xilinx) {
> > >  if (partial reconfiguration) {
> > >   do_special_setup();
> > >  }
> > > }
> > 
> > I only did the switch stuff b/c i envisioned a need for partial image
> > support for socfpga.
> 
> That'd be seriously cool :)
> 
> > 
> > That said, i would suggest, as you mention, moving
> > this to platform specific code and perhaps an indication of the image type
> > in the fitimage.
> 
> driver-specific code . It doesn't need to know the imagetype, just that
> the blob that you passed in is a partial-reconfiguration blob. I never
> really worked with P/R though, do you need some other metadata for that
> or is it contained in that P/R bitstream blob already ?

as far as i understand it, it is all in the blob.  All that is needed is knowing
whether the blob is a full or partial image.  X seems to just use the image size
to determine this, but that means having a table of all devices and their
respective full image size.  seems simpler to just specify the image type is
partial or not in the fitimage.

> > 
> > > 
> > > 
> > > But even better would be to move this platform-dependent stuff into
> > > drivers/fpga/ or somewhere there. This is common code, so it shouldn't
> > > be here in the first place.
> > 
> > My preference would be to only call fpga_load and have the platform
> 
> s/platform/driver/
> 
> > 
> > specific stuff figure out what they want to do.
> 
> Agreed
> 
> > 
> > My next comment would be
> > that perhaps it is best to add an fpgap type or some such in the fitimage
> > to specify the image is a partial image rather than looking at the image
> > size?
> 
> H, see my question above. If the driver cannot discern it from the
> blob, ma

Re: [U-Boot] [PATCH 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

On Sun, 2017-02-19 at 21:07 +0100, Marek Vasut wrote:
> On 02/19/2017 08:49 PM, Dalon Westergreen wrote:
> > 
> > The implementation of boot_get_fpga only supported one fpga family.
> > This modification allows for any of the fpga devices supported by
> > fpga_load to be used.
> > 
> > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> 
> +CC Xilinx friends :)
> 
> > 
> > ---
> >  common/image.c | 37 ++---
> >  1 file changed, 22 insertions(+), 15 deletions(-)
> > 
> > diff --git a/common/image.c b/common/image.c
> > index 0f88984..792d371 100644
> > --- a/common/image.c
> > +++ b/common/image.c
> > @@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t
> > arch,
> >  }
> >  
> >  #if IMAGE_ENABLE_FIT
> > -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
> > +#if defined(CONFIG_FPGA)
> >  int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
> >       uint8_t arch, const ulong *ld_start, ulong * const
> > ld_len)
> >  {
> > @@ -1318,7 +1318,8 @@ int boot_get_fpga(int argc, char * const argv[],
> > bootm_headers_t *images,
> >     int err;
> >     int devnum = 0; /* TODO support multi fpga platforms */
> >     const fpga_desc * const desc = fpga_get_desc(devnum);
> > -   xilinx_desc *desc_xilinx = desc->devdesc;
> > +   xilinx_desc *desc_xilinx;
> > +   bitstream_type bstype;
> >  
> >     /* Check to see if the images struct has a FIT configuration */
> >     if (!genimg_has_config(images)) {
> > @@ -1365,22 +1366,28 @@ int boot_get_fpga(int argc, char * const argv[],
> > bootm_headers_t *images,
> >     return fit_img_result;
> >     }
> >  
> > -   if (img_len >= desc_xilinx->size) {
> > +   switch (desc->devtype) {
> 
> Do we need the switch statement at all ? We can have full configuration
> as a default mode of operation and have something like
> 
> if (xilinx) {
>  if (partial reconfiguration) {
>   do_special_setup();
>  }
> }

I only did the switch stuff b/c i envisioned a need for partial image
support for socfpga.  That said, i would suggest, as you mention, moving
this to platform specific code and perhaps an indication of the image type
in the fitimage.

> 
> But even better would be to move this platform-dependent stuff into
> drivers/fpga/ or somewhere there. This is common code, so it shouldn't
> be here in the first place.

My preference would be to only call fpga_load and have the platform
specific stuff figure out what they want to do. My next comment would be
that perhaps it is best to add an fpgap type or some such in the fitimage
to specify the image is a partial image rather than looking at the image
size?

Also a consideration is that there should be a means of specifying the fpga
devnum somehow in the fitimage?  it is plausible that a system could have
multiple fpgas, no?

--dalon

> > 
> > +   case fpga_xilinx:
> > +   desc_xilinx = desc->devdesc;
> > +   if (img_len >= desc_xilinx->size) {
> > +   name = "full";
> > +   bstype = BIT_FULL;
> > +   } else {
> > +   name = "partial";
> > +   bstype = BIT_PARTIAL;
> > +   }
> > +   break;
> > +   default:
> >     name = "full";
> > -   err = fpga_loadbitstream(devnum, (char *)img_data,
> > -    img_len, BIT_FULL);
> > -   if (err)
> > -   err = fpga_load(devnum, (const void
> > *)img_data,
> > -   img_len, BIT_FULL);
> > -   } else {
> > -   name = "partial";
> > -   err = fpga_loadbitstream(devnum, (char *)img_data,
> > -    img_len, BIT_PARTIAL);
> > -   if (err)
> > -   err = fpga_load(devnum, (const void
> > *)img_data,
> > -   img_len, BIT_PARTIAL);
> > +   bstype = BIT_FULL;
> >     }
> >  
> > +   err = fpga_loadbitstream(devnum, (char *)img_data,
> > +    img_len, bstype);
> > +   if (err)
> > +   err = fpga_load(devnum, (const void *)img_data,
> > +   img_len, bstype);
> > +
> >     if (err)
> >     return err;
> >  
> > 
> 
> 
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[U-Boot] [PATCH v4 8/8] arm: socfpga: sr1500 use environment in common header

[Dalon Westergreen]

This removes the default environment from the sr1500 header
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

This board has no upstream devicetree in the kernel source,
so set to socfpga_cyclone5_sr1500.dtb.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
 - set devicetree name to match socfpga_{fpga model}_{board model}.dts
   pattern
---
 configs/socfpga_sr1500_defconfig |  1 +
 include/configs/socfpga_sr1500.h | 28 
 2 files changed, 1 insertion(+), 28 deletions(-)

diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 981600b..ac1ed53 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_SR1500=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index f67fafd..64e1595 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SR1500 */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"uImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -28,31 +25,6 @@
 #define CONFIG_PHY_MARVELL
 #define PHY_ANEG_TIMEOUT   8000
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "fsloadcmd=ext2load\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* Environment */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 
-- 
2.7.4

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Re: [U-Boot] [PATCH v4 1/8] arm: socfpga: Add distro boot to socfpga common header

[Dalon Westergreen]

On Sun, 2017-02-19 at 21:35 +0100, Marek Vasut wrote:
> On 02/19/2017 09:20 PM, Dalon Westergreen wrote:
> > 
> > This adds a common environment and support for distro boot
> > in the common socfpga header.
> > 
> > Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
> > Acked-by: Marek Vasut <ma...@denx.de>
> > 
> > --
> > Changes in v4:
> >  - Move env back to being right after the MBR
> > Changes in v3:
> >  - fix spacing between asterix
> >  - remove verify=n as a default setting
> > 
> > Changes in v2:
> >  - Remove unneeded CONFIG_BOOTFILE and fdt_addr
> >  - cleanup spacing in MMC env size
> > ---
> >  include/configs/socfpga_common.h | 52 -
> > ---
> >  1 file changed, 48 insertions(+), 4 deletions(-)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 582b04a..55e0bf9 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -67,6 +67,9 @@
> >  #define CONFIG_SYS_HOSTNAMECONFIG_SYS_BOARD
> >  #endif
> >  
> > +#define CONFIG_CMD_PXE
> > +#define CONFIG_MENU
> > +
> >  /*
> >   * Cache
> >   */
> > @@ -245,13 +248,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> >   * U-Boot environment
> >   */
> >  #if !defined(CONFIG_ENV_SIZE)
> > -#define CONFIG_ENV_SIZE4096
> > +#define CONFIG_ENV_SIZE(8 * 1024)
> >  #endif
> >  
> >  /* Environment for SDMMC boot */
> >  #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
> > -#define CONFIG_SYS_MMC_ENV_DEV 0   /* device 0 */
> > -#define CONFIG_ENV_OFFSET  512 /* just after the MBR
> > */
> > +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
> > +#define CONFIG_ENV_OFFSET  512 /* just after the MBR */
> >  #endif
> 
> You could've just dropped this part then ;-)
> 
> IMO the series is fine, let's see what others have to say ...
> 
im still a bit of a git novice... :)

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[U-Boot] [PATCH v4 6/8] arm: socfpga: SoCKit use environment in common header

[Dalon Westergreen]

This removes the default environment from the SoCKit headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_sockit_defconfig |  1 +
 include/configs/socfpga_sockit.h | 28 
 2 files changed, 1 insertion(+), 28 deletions(-)

diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index d0c2bda..bf60783 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_SOCKIT=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sockit"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sockit.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h
index 326310b..c9fc5c9 100644
--- a/include/configs/socfpga_sockit.h
+++ b/include/configs/socfpga_sockit.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"fitImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v4 7/8] arm: socfpga: Socrates use environment in common header

[Dalon Westergreen]

This removes the default environment from the socrates headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_socrates_defconfig |  1 +
 include/configs/socfpga_socrates.h | 26 --
 2 files changed, 1 insertion(+), 26 deletions(-)

diff --git a/configs/socfpga_socrates_defconfig 
b/configs/socfpga_socrates_defconfig
index e9276f9..4246ad6 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_EBV_SOCRATES=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socrates.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_socrates.h 
b/include/configs/socfpga_socrates.h
index 90343b7..5dc9298 100644
--- a/include/configs/socfpga_socrates.h
+++ b/include/configs/socfpga_socrates.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCrates */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"zImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,29 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiroot=/dev/mtdblock0\0" \
-   "qspirootfstype=jffs2\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${qspiroot} rw rootfstype=${qspirootfstype};"\
-   "bootm ${loadaddr} - ${fdt_addr}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v4 5/8] arm: socfpga: DE1 use environment in common header

[Dalon Westergreen]

This removes the default environment from the de1 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

This board does not have a devicetree in the upstream kernel
source so set devicetree to socfpga_cyclone5_de1_soc.dtb.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in V2:
 - Remove unneeded CONFIG_BOOTFILE
 - set devicetree name to match socfpga_{fpga model}_{board model}.dts
   pattern
---
 configs/socfpga_de1_soc_defconfig |  1 +
 include/configs/socfpga_de1_soc.h | 20 
 2 files changed, 1 insertion(+), 20 deletions(-)

diff --git a/configs/socfpga_de1_soc_defconfig 
b/configs/socfpga_de1_soc_defconfig
index 032deef..d78e8a1 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -6,6 +6,7 @@ CONFIG_TARGET_SOCFPGA_TERASIC_DE1_SOC=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de1_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de1_soc.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
diff --git a/include/configs/socfpga_de1_soc.h 
b/include/configs/socfpga_de1_soc.h
index 2278357..a7ab1fe 100644
--- a/include/configs/socfpga_de1_soc.h
+++ b/include/configs/socfpga_de1_soc.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"fitImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,23 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdtaddr}\0" \
-   "bootimage=zImage\0" \
-   "fdtaddr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdtaddr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdtaddr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdtaddr} ${fdtimage}\0" \
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v4 4/8] arm: socfpga: C5 SoCDK use environment in common header

[Dalon Westergreen]

This removes the default environment from the C5 SoCDK headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

In addition to the above, add support to boot from the custom
a2 type partition.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_cyclone5_defconfig   |  3 +++
 include/configs/socfpga_cyclone5_socdk.h | 32 
 2 files changed, 3 insertions(+), 32 deletions(-)

diff --git a/configs/socfpga_cyclone5_defconfig 
b/configs/socfpga_cyclone5_defconfig
index 8b050b9..c8b8084 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socdk"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_socdk.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
diff --git a/include/configs/socfpga_cyclone5_socdk.h 
b/include/configs/socfpga_cyclone5_socdk.h
index 4100ef9..dfe4980 100644
--- a/include/configs/socfpga_cyclone5_socdk.h
+++ b/include/configs/socfpga_cyclone5_socdk.h
@@ -16,13 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"zImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -34,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v4 0/8] arm: socfpga: Move to using distro boot

[Dalon Westergreen]

This series adds support to the common socfpga header for distro boot and moves
the DE0/1, Socrates, C5/A5 SoCDK, and SoCKIT kits to use the common
environment.
 
Where available, the default devicetree is set to the devicetree for the board
available in the kernel source.  If none is available in the kernel source, the
devicetree is set to the name previously used in the board header file.

Changes in v4:
 - Move env back to immediately after MBR 
Changes in v3:
 - fix errors in 1/8 patch
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE and fdt_addr
 - Cleanup of socfpga_common.h
 - Fixed dtb names for de1, sr1500, and arria5 boards

Dalon Westergreen (8):
  arm: socfpga: Add distro boot to socfpga common header
  arm: socfpga: DE0 use environment in common header
  arm: socfpga: A5 SoCDK use environment in common header
  arm: socfpga: C5 SoCDK use environment in common header
  arm: socfpga: DE1 use environment in common header
  arm: socfpga: SoCKit use environment in common header
  arm: socfpga: Socrates use environment in common header
  arm: socfpga: sr1500 use environment in common header

 configs/socfpga_arria5_defconfig |  3 ++
 configs/socfpga_cyclone5_defconfig   |  3 ++
 configs/socfpga_de0_nano_soc_defconfig   |  3 ++
 configs/socfpga_de1_soc_defconfig|  1 +
 configs/socfpga_sockit_defconfig |  1 +
 configs/socfpga_socrates_defconfig   |  1 +
 configs/socfpga_sr1500_defconfig |  1 +
 include/configs/socfpga_arria5_socdk.h   | 32 
 include/configs/socfpga_common.h | 52 +---
 include/configs/socfpga_cyclone5_socdk.h | 32 
 include/configs/socfpga_de0_nano_soc.h   | 20 
 include/configs/socfpga_de1_soc.h| 20 
 include/configs/socfpga_sockit.h | 28 -
 include/configs/socfpga_socrates.h   | 26 
 include/configs/socfpga_sr1500.h | 28 -
 15 files changed, 61 insertions(+), 190 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH v4 3/8] arm: socfpga: A5 SoCDK use environment in common header

[Dalon Westergreen]

This removes the default environment from the A5 socdk headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

Add support to boot from the custom a2 type partition.

Change default devicetree name to match devicetree name in
upstream kernel source.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
 - Fix dtb name
---
 configs/socfpga_arria5_defconfig   |  3 +++
 include/configs/socfpga_arria5_socdk.h | 32 
 2 files changed, 3 insertions(+), 32 deletions(-)

diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 43c51fe..a49f6fa 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria5_socdk.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -64,3 +65,5 @@ CONFIG_G_DNL_MANUFACTURER="altera"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+ONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
diff --git a/include/configs/socfpga_arria5_socdk.h 
b/include/configs/socfpga_arria5_socdk.h
index 9b1f753..b60d007 100644
--- a/include/configs/socfpga_arria5_socdk.h
+++ b/include/configs/socfpga_arria5_socdk.h
@@ -16,13 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"zImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
-#define CONFIG_BOOTCOMMAND "run ramboot"
-#else
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
-#endif
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -34,31 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "verify=n\0" \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-   "qspiload=sf probe && mtdparts default && run ubiload\0" \
-   "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
-   " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "ubiload=ubi part UBI && ubifsmount ubi0 && " \
-   "ubifsload ${loadaddr} /boot/${bootimage} && " \
-   "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v4 2/8] arm: socfpga: DE0 use environment in common header

[Dalon Westergreen]

This removes the default environment from the de0 headers
and instead uses the common environment provided in
socfpga_common.h which now uses distro boot.

In addition to the above, add support to boot from the custom
a2 type partition

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE
---
 configs/socfpga_de0_nano_soc_defconfig |  3 +++
 include/configs/socfpga_de0_nano_soc.h | 20 
 2 files changed, 3 insertions(+), 20 deletions(-)

diff --git a/configs/socfpga_de0_nano_soc_defconfig 
b/configs/socfpga_de0_nano_soc_defconfig
index af41e1e..b122135 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SOCFPGA_TERASIC_DE0_NANO=y
 CONFIG_SPL_STACK_R_ADDR=0x0080
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_de0_nano_soc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_de0_nano_soc.dtb"
 CONFIG_FIT=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
@@ -58,3 +59,5 @@ CONFIG_G_DNL_MANUFACTURER="terasic"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
\ No newline at end of file
diff --git a/include/configs/socfpga_de0_nano_soc.h 
b/include/configs/socfpga_de0_nano_soc.h
index f655972..dd5933d 100644
--- a/include/configs/socfpga_de0_nano_soc.h
+++ b/include/configs/socfpga_de0_nano_soc.h
@@ -16,9 +16,6 @@
 #define PHYS_SDRAM_1_SIZE  0x4000  /* 1GiB */
 
 /* Booting Linux */
-#define CONFIG_BOOTFILE"fitImage"
-#define CONFIG_BOOTARGS"console=ttyS0," 
__stringify(CONFIG_BAUDRATE)
-#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
 #define CONFIG_LOADADDR0x0100
 #define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
 
@@ -30,23 +27,6 @@
 
 #define CONFIG_ENV_IS_IN_MMC
 
-/* Extra Environment */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-   "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
-   "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "bootimage=zImage\0" \
-   "fdt_addr=100\0" \
-   "fdtimage=socfpga.dtb\0" \
-   "bootm ${loadaddr} - ${fdt_addr}\0" \
-   "mmcroot=/dev/mmcblk0p2\0" \
-   "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
-   " root=${mmcroot} rw rootwait;" \
-   "bootz ${loadaddr} - ${fdt_addr}\0" \
-   "mmcload=mmc rescan;" \
-   "load mmc 0:1 ${loadaddr} ${bootimage};" \
-   "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
-
 /* The rest of the configuration is shared */
 #include 
 
-- 
2.7.4

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[U-Boot] [PATCH v4 1/8] arm: socfpga: Add distro boot to socfpga common header

[Dalon Westergreen]

This adds a common environment and support for distro boot
in the common socfpga header.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
Acked-by: Marek Vasut <ma...@denx.de>

--
Changes in v4:
 - Move env back to being right after the MBR
Changes in v3:
 - fix spacing between asterix
 - remove verify=n as a default setting

Changes in v2:
 - Remove unneeded CONFIG_BOOTFILE and fdt_addr
 - cleanup spacing in MMC env size
---
 include/configs/socfpga_common.h | 52 
 1 file changed, 48 insertions(+), 4 deletions(-)

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 582b04a..55e0bf9 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -67,6 +67,9 @@
 #define CONFIG_SYS_HOSTNAMECONFIG_SYS_BOARD
 #endif
 
+#define CONFIG_CMD_PXE
+#define CONFIG_MENU
+
 /*
  * Cache
  */
@@ -245,13 +248,13 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  * U-Boot environment
  */
 #if !defined(CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE4096
+#define CONFIG_ENV_SIZE(8 * 1024)
 #endif
 
 /* Environment for SDMMC boot */
 #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
-#define CONFIG_SYS_MMC_ENV_DEV 0   /* device 0 */
-#define CONFIG_ENV_OFFSET  512 /* just after the MBR */
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
+#define CONFIG_ENV_OFFSET  512 /* just after the MBR */
 #endif
 
 /* Environment for QSPI boot */
@@ -308,8 +311,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 2
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME"u-boot-dtb.img"
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
+#endif
+#else
+#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
 #endif
 #endif
 
@@ -331,4 +338,41 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_STACK   CONFIG_SYS_INIT_SP_ADDR
 
+/* Extra Environment */
+#ifndef CONFIG_SPL_BUILD
+#include 
+
+#ifdef CONFIG_CMD_PXE
+#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
+#else
+#define BOOT_TARGET_DEVICES_PXE(func)
+#endif
+
+#ifdef CONFIG_CMD_MMC
+#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
+#else
+#define BOOT_TARGET_DEVICES_MMC(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+   BOOT_TARGET_DEVICES_MMC(func) \
+   BOOT_TARGET_DEVICES_PXE(func) \
+   func(DHCP, dhcp, na)
+
+#include 
+
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+   "bootm_size=0xa00\0" \
+   "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
+   "fdt_addr_r=0x0200\0" \
+   "scriptaddr=0x0210\0" \
+   "pxefile_addr_r=0x0220\0" \
+   "ramdisk_addr_r=0x0230\0" \
+   BOOTENV
+
+#endif
+#endif
+
 #endif /* __CONFIG_SOCFPGA_COMMON_H__ */
-- 
2.7.4

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Re: [U-Boot] [PATCH 1/8] arm: socfpga: Add distro boot to socfpga common header

[Dalon Westergreen]

On Sun, 2017-02-19 at 20:45 +0100, Pavel Machek wrote:
> Hi!
> 
> > 
> > > 
> > > > 
> > > > > 
> > > > > > 
> > > > > >  /* Environment for SDMMC boot */
> > > > > >  #if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
> > > > > > -#define CONFIG_SYS_MMC_ENV_DEV 0   /* device 0
> > > > > > */
> > > > > > -#define CONFIG_ENV_OFFSET  512 /* just after
> > > > > > the
> > > > > > MBR
> > > > > > */
> > > > > > +#define CONFIG_SYS_MMC_ENV_DEV 0   /*
> > > > > > device 0
> > > > > > */
> > > > > > +#define CONFIG_ENV_OFFSET  (34*512)/* just after the
> > > > > > GPT
> > > > > > */
> ...
> > 
> > I actually dont believe this will cause much of an issue. the env is placed
> > immediately after the partition table.  I know this size fits between the
> > table and the typical location of the first partition without issue.
> 
> Hmm. It is not immediately after partition table (==MBR), it is at
> sector 34. Now, by changing size you already break the setups, so
> moving it back to sector 1 does not help much, but can you explain?

Sorry, you are right. Frank had moved it after the GPT in his patchset and i
had just copied that.  i will update this to be immediately after the mbr as
it was before.

--dalon

> 
>   Pavel
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[U-Boot] [PATCH 2/2] common: bootm: add support for arbitrary fgpa configuration

[Dalon Westergreen]

This adds support for fpga configuration data in fitimages for
any fpga device supported by fpga_load.  At this point fitimages
only support configuration of fpga images for fpga devnum 0.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
---
 common/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index b2c0912..4a4b47c 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -248,7 +248,7 @@ int bootm_find_images(int flag, int argc, char * const 
argv[])
 #endif
 
 #if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
/* find bitstreams */
ret = boot_get_fpga(argc, argv, , IH_ARCH_DEFAULT,
NULL, NULL);
-- 
2.7.4

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[U-Boot] [PATCH 1/2] common: image: update boot_get_fpga to support arbitrary fpga image

[Dalon Westergreen]

The implementation of boot_get_fpga only supported one fpga family.
This modification allows for any of the fpga devices supported by
fpga_load to be used.

Signed-off-by: Dalon Westergreen <dwest...@gmail.com>
---
 common/image.c | 37 ++---
 1 file changed, 22 insertions(+), 15 deletions(-)

diff --git a/common/image.c b/common/image.c
index 0f88984..792d371 100644
--- a/common/image.c
+++ b/common/image.c
@@ -1306,7 +1306,7 @@ int boot_get_setup(bootm_headers_t *images, uint8_t arch,
 }
 
 #if IMAGE_ENABLE_FIT
-#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_XILINX)
+#if defined(CONFIG_FPGA)
 int boot_get_fpga(int argc, char * const argv[], bootm_headers_t *images,
  uint8_t arch, const ulong *ld_start, ulong * const ld_len)
 {
@@ -1318,7 +1318,8 @@ int boot_get_fpga(int argc, char * const argv[], 
bootm_headers_t *images,
int err;
int devnum = 0; /* TODO support multi fpga platforms */
const fpga_desc * const desc = fpga_get_desc(devnum);
-   xilinx_desc *desc_xilinx = desc->devdesc;
+   xilinx_desc *desc_xilinx;
+   bitstream_type bstype;
 
/* Check to see if the images struct has a FIT configuration */
if (!genimg_has_config(images)) {
@@ -1365,22 +1366,28 @@ int boot_get_fpga(int argc, char * const argv[], 
bootm_headers_t *images,
return fit_img_result;
}
 
-   if (img_len >= desc_xilinx->size) {
+   switch (desc->devtype) {
+   case fpga_xilinx:
+   desc_xilinx = desc->devdesc;
+   if (img_len >= desc_xilinx->size) {
+   name = "full";
+   bstype = BIT_FULL;
+   } else {
+   name = "partial";
+   bstype = BIT_PARTIAL;
+   }
+   break;
+   default:
name = "full";
-   err = fpga_loadbitstream(devnum, (char *)img_data,
-img_len, BIT_FULL);
-   if (err)
-   err = fpga_load(devnum, (const void *)img_data,
-   img_len, BIT_FULL);
-   } else {
-   name = "partial";
-   err = fpga_loadbitstream(devnum, (char *)img_data,
-img_len, BIT_PARTIAL);
-   if (err)
-   err = fpga_load(devnum, (const void *)img_data,
-   img_len, BIT_PARTIAL);
+   bstype = BIT_FULL;
}
 
+   err = fpga_loadbitstream(devnum, (char *)img_data,
+img_len, bstype);
+   if (err)
+   err = fpga_load(devnum, (const void *)img_data,
+   img_len, bstype);
+
if (err)
return err;
 
-- 
2.7.4

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[U-Boot] [PATCH 0/2] common: fitimage support for arbitrary fpga type

[Dalon Westergreen]

The intent of these patches is to modify existing fitimage support for
fpga configuration to allow configuration of any fpga type supported
by the fpga_load command.  Note though, that fitimage support for fpga
configuration only allows for configuration of the fpga of devnum 0.

Dalon Westergreen (2):
  common: image: update boot_get_fpga to support arbitrary fpga image
  common: bootm: add support for arbitrary fgpa configuration

 common/bootm.c |  2 +-
 common/image.c | 37 ++---
 2 files changed, 23 insertions(+), 16 deletions(-)

-- 
2.7.4

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