[PULL] u-boot-mips fixes for v2024.04
Hi Tom, please pull two bugfixes for MIPS, thanks. CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/19933 The following changes since commit f3c979dd0053c082d2df170446923e7ce5edbc2d: Prepare v2024.04-rc4 (2024-03-11 13:11:46 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-fixes-for-v2024.04 for you to fetch changes up to 6806a133cde6f99777925953ee046bf2f050d4ef: mips: fix change_k0_cca() (2024-03-13 21:15:40 +0100) - mips: implement __udivdi3 to fix building of SquashFS - mips: fix bug in cache init on MIPS32r2 or later Daniel Schwierzeck (1): mips: fix change_k0_cca() Linus Walleij (1): mips: implement __udivdi3 arch/mips/lib/Makefile | 2 +- arch/mips/lib/cache_init.S | 4 ++-- arch/mips/lib/udivdi3.c| 17 + 3 files changed, 20 insertions(+), 3 deletions(-) create mode 100644 arch/mips/lib/udivdi3.c
[PATCH] mips: fix change_k0_cca()
The intention of change_k0_cca() is to read the C0.Config register into register $t0, update $t0 with the new cache coherency mode passed in $a0 and write back $t0 to C0.Config. With MIPS32 R2 or later instruction sets, this can be achieved with a single instruction with INS. The source and destination register of the INS instruction is passed as first parameter. In case of change_k0_cca() it is register $t0. But for writing back the updated value to C0.Config, the incorrect $a0 register is used. This is only correct in the MIPS32 R1 code path. Fix the `mtc0` instruction to write back the value of the $t0 register. Fix the MIPS32 R1 code path to also store the updated value in $t0. Reported by user ddqxy138 on Github. https://github.com/u-boot/u-boot/commit/b838586086af3278bcaead3720c7a18813cf4619 Signed-off-by: Daniel Schwierzeck --- arch/mips/lib/cache_init.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index 602741c65d..d64209d76a 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -431,9 +431,9 @@ LEAF(change_k0_cca) #else xor a0, a0, t0 andia0, a0, CONF_CM_CMASK - xor a0, a0, t0 + xor t0, a0, t0 #endif - mtc0a0, CP0_CONFIG + mtc0t0, CP0_CONFIG jr.hb ra END(change_k0_cca) -- 2.41.0
[PATCH] mips: implement __udivdi3
From: Linus Walleij
Squashfs wasn't compiling because the lldiv() directives
turn into __udivdi3 and we are using private libgcc.
After this squashfs compiles for MIPS.
Signed-off-by: Linus Walleij
Signed-off-by: Daniel Schwierzeck
---
Linus, this is the updated and optimized version of your initial patch.
Sorry for the long delay ;)
arch/mips/lib/Makefile | 2 +-
arch/mips/lib/udivdi3.c | 17 +
2 files changed, 18 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/lib/udivdi3.c
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 9ee1fcb5c7..1621cc9a1f 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -14,4 +14,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-$(CONFIG_SPL_BUILD) += spl.o
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o
diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c
new file mode 100644
index 00..4d780117cf
--- /dev/null
+++ b/arch/mips/lib/udivdi3.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#include "libgcc.h"
+
+#if BITS_PER_LONG == 32
+
+#include
+
+long long __udivdi3(long long u, word_type b)
+{
+ long long ret = u;
+
+ __div64_32(, b);
+ return ret;
+}
+
+#endif /* BITS_PER_LONG == 32 */
--
2.41.0
Re: [PATCH] bmips: Add Inteno XG6846 board
On 9/20/23 09:42, Linus Walleij wrote: This adds support for the Inteno XG6846 board based on the Broadcom MIPS 6328 SoC. The default boot will read a uImage from flash and boot it. Cc: Daniel Schwierzeck Signed-off-by: Linus Walleij --- arch/mips/dts/Makefile | 1 + arch/mips/dts/inteno,xg6846.dts | 57 ++ arch/mips/mach-bmips/Kconfig| 12 + board/inteno/xg6846/Kconfig | 12 + board/inteno/xg6846/MAINTAINERS | 6 +++ board/inteno/xg6846/Makefile| 3 ++ board/inteno/xg6846/xg6846.c| 6 +++ configs/inteno_xg6846_ram_defconfig | 74 + include/configs/inteno_xg6846.h | 8 9 files changed, 179 insertions(+) create mode 100644 arch/mips/dts/inteno,xg6846.dts create mode 100644 board/inteno/xg6846/Kconfig create mode 100644 board/inteno/xg6846/MAINTAINERS create mode 100644 board/inteno/xg6846/Makefile create mode 100644 board/inteno/xg6846/xg6846.c create mode 100644 configs/inteno_xg6846_ram_defconfig create mode 100644 include/configs/inteno_xg6846.h if you remove board/inteno/xg6846/Makefile and board/inteno/xg6846/xg6846.c: Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH] bmips: Add Inteno XG6846 board
On 9/20/23 20:55, Tom Rini wrote: On Wed, Sep 20, 2023 at 08:51:07PM +0200, Linus Walleij wrote: On Wed, Sep 20, 2023 at 4:22 PM Tom Rini wrote: + * This is a diet version of the device tree from Linux, + * suitable for U-Boot. + */ We shouldn't need a diet version of the tree. If it's reasonably done and stable in the kernel, we can even move towards just passing the U-Boot tree along to Linux. The device tree is not stable in the kernel. It exists in OpenWrt and the creators of the bmips target are kind of absent for the moment. The reason it is not in Linux is that the "switch ethernet" driver and bindings need to be upstreamed before the device trees can be upstreamed. But I can try to bring in more of it for sure :) Just like ARM the goal is just to drop in the kernel dts here. I guess this approach works well for ARM but not for MIPS. Most MIPS consumer boards are just maintained in OpenWRT but not in mainline Linux. And there are a few boards which have been just mainlined in U-Boot but not Linux so them also don't have a stable Linux DT. As MIPS is a dead architecture I suggest to just go with the minimal DT suited for U-Boot ;) +++ b/board/inteno/xg6846/xg6846.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 Linus Walleij + */ + +#include So basically just an empty object file. Can we just _not_ have something here, if we perhaps don't set SYS_BOARD? I assume if there's just nothing here the link rules fail. Admittedly my knowledge of U-Boot internals are not the best and this is a bit of a copy and paste job from board/comtrend/ar5387un/ar-5387un.c which looks like this and sets a bad example I suppose. Yeah, I didn't know we had someone doing that already here, whoops. I guess you are asking me to modify U-Boots build system to make the whole .c and Makefile inside a board subdir optional so we can delete all such empty boardfiles? Well, it'd sure be nice if we could avoid having a dummy C file. If it looks like a nightmare once you take a peek, we can just live with it. I just tested it, you can simply add an empty board/inteno/xg6846/Makefile and remove board/inteno/xg6846/xg6846.c. But you can also remove the Makefile. Just the Kconfig and MAINTAINERS file are needed. -- - Daniel
Re: [PATCH] RFT: mips: implement __udivdi3
Hi Linus,
On 9/18/23 08:11, Linus Walleij wrote:
Squashfs wasn't compiling because the lldiv() directives
turn into __udivdi3 and we are using private libgcc.
This is just copied from the Linux kernel v6.6-rc1
arch/mips/include/asm/div64.h and then adjusted for
U-Boot.
After this squashfs compiles for MIPS.
Cc: Daniel Schwierzeck
Cc: Mauro Condarelli
Cc: Ralf Baechle
Signed-off-by: Linus Walleij
---
I can't test this because it didn't work for MTD devices
as I had expected, but I saw Mauro had this problem
before so I think I might have fixed it. I better put
the patch out there rather than let it sit on my drive.
thanks for the patch. IIRC the problem was due to the usage of a/b vs.
do_div(a,b). We already thought about two options: fix the SquashFS code
or add __udivdi3(). Because no upstream MIPS board enabled SquashFS,
this issue remained unresolved.
---
arch/mips/lib/Makefile | 2 +-
arch/mips/lib/udivdi3.c | 86 +
2 files changed, 87 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/lib/udivdi3.c
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 9ee1fcb5c702..1621cc9a1ff9 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -14,4 +14,4 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_GO) += boot.o
obj-$(CONFIG_SPL_BUILD) += spl.o
-lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o
+lib-$(CONFIG_USE_PRIVATE_LIBGCC) += ashldi3.o ashrdi3.o lshrdi3.o udivdi3.o
diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c
new file mode 100644
index ..6a4ee5fa46ab
--- /dev/null
+++ b/arch/mips/lib/udivdi3.c
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2000, 2004, 2021 Maciej W. Rozycki
+ * Copyright (C) 2003, 07 Ralf Baechle (r...@linux-mips.org)
+ */
+
+#include "libgcc.h"
+
+/*
+ * No traps on overflows for any of these...
+ */
+
+#define do_div64_32(res, high, low, base) ({ \
+ unsigned long __cf, __tmp, __tmp2, __i; \
+ unsigned long __quot32, __mod32;\
+ \
+ __asm__(\
+ " .setpush\n"\
+ " .setnoat\n"\
+ " .setnoreorder \n"\
+ " move%2, $0 \n"\
+ " move%3, $0 \n"\
+ " b 1f \n"\
+ " li %4, 0x21\n"\
+ "0:\n"\
+ " sll $1, %0, 0x1 \n"\
+ " srl %3, %0, 0x1f\n"\
+ " or %0, $1, %5 \n"\
+ " sll %1, %1, 0x1 \n"\
+ " sll %2, %2, 0x1 \n"\
+ "1:\n"\
+ " bnez%3, 2f \n"\
+ " sltu %5, %0, %z6 \n"\
+ " bnez%5, 3f \n"\
+ "2:\n"\
+ " addiu %4, %4, -1 \n"\
+ " subu%0, %0, %z6 \n"\
+ " addiu %2, %2, 1 \n"\
+ "3:\n"\
+ " bnez%4, 0b \n"\
+ " srl%5, %1, 0x1f\n"\
+ " .setpop" \
+ : "=" (__mod32), "=" (__tmp), \
+ "=" (__quot32), "=" (__cf), \
+ "=" (__i), "=" (__tmp2) \
+ : "Jr" (base), "0" (high), "1" (low));\
+ \
+ (res) = __quot32; \
+ __mod32;
Re: [PATCH 02/88] treewide: Correct invalid Kconfig syntax and warnings
On 1/27/23 14:45, Tom Rini wrote: On Mon, Jan 23, 2023 at 02:59:05PM -0700, Simon Glass wrote: In several places a 'select' is used to select a choice, which is not supported by Kconfig. In other places, the filename for the 'source' command is not in quites. Fix these two problems throughout the tree, so that kconfiglib does not show any more warnings. Signed-off-by: Simon Glass OK, to summarize what I just said in another email and clarify future work. Please first split this patch in to its own series that corrects each type of problem, per commit. The missing quotes for example, and then the extra whitespace ones. Next, commenting out a select is wrong, and each case needs to be better understood / fixed. I'm honestly not sure if asking endianness for MIPS is right and if we should select that from boards too, like ARC, but probably. The ARC_MMU one also should just not be asked, I suspect, but as a separate patch where you cc Alexey, we'll find out :) And so on, for each. Thanks. For MIPS the endianess (and also architecture/ISA level) needs to be able to be set by the user via menuconfig as most MIPS cores or SoCs can support multiple variants. The idea is that the specific SoC or machine just sets the supported options to restrict the options the user can choose. The board's defconfig should set the required default value for each option but must not *select* it. See the Boston board for example: config TARGET_BOSTON bool "Support Boston" ... select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_CPU_MIPS32_R6 select SUPPORTS_CPU_MIPS64_R1 select SUPPORTS_CPU_MIPS64_R2 select SUPPORTS_CPU_MIPS64_R6 select SUPPORTS_LITTLE_ENDIAN A possible fix for ARC could be: --- a/arch/Kconfig +++ b/arch/Kconfig @@ -53,8 +53,6 @@ config ARC select SUPPORT_OF_CONTROL select SYS_CACHE_SHIFT_7 select TIMER - select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN - select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN config ARM bool "ARM architecture" @@ -490,7 +488,7 @@ endif source "board/keymile/Kconfig" -if MIPS || MICROBLAZE +if MIPS || MICROBLAZE || ARC choice prompt "Endianness selection" @@ -502,11 +500,11 @@ choice config SYS_BIG_ENDIAN bool "Big endian" - depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE + depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE || (CPU_BIG_ENDIAN && ARC) config SYS_LITTLE_ENDIAN bool "Little endian" - depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE + depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE || (CPU_LITTLE_ENDIAN && ARC) endchoice A *make savedefconfig* should than automatically add *CONFIG_SYS_LITTLE_ENDIAN=y* or *CONFIG_SYS_BIG_ENDIAN=y* to the ARC board defconfig's. -- - Daniel
Re: DDR timing for vendor board
Hi Rob, On 12/9/22 12:10, Rob Kramer wrote: Hi Jack, Thanks for your suggestion, I hadn't thought of using just the rkbin ddr file together with u-boot SPL. My biggest objection was the rkbin miniloader that makes assumptions on partition layout. It seems to work, but now I'm in for some DT pain :) I don't know anything about Rockchip but from experience with other SoC's and DDR2/3 controllers I would say that the reason for this closed-source loader is likely some proprietary dynamic tuning algorithm for some memory controller parameters (e.g. DQS) to adapt to manufacturing tolerances of the board. If that's the case, the static setting of memory size and timings via DT won't be enough to run the board stable and Jack's approach would be more reliable. Cheers, Rob 9 Dec 2022 00:49:30 Jack Mitchell : On 08/12/2022 04:01, Rob Kramer wrote: Hi all, I have a RK3288 board from a Chinese display vendor that came with the usual giant Rockchip tarball that they patched here and there to make the board work. It seems to be based on a rk3288-evb, since that is what they patched in the kernel. The kernel is a 4.4 kernel with Android stuff in it (i.e. fiq-debugger) and a large amount of Rockchip patches, u-boot is 2017.09, with rk patches. It turns out that u-boot TPL/SPL won't boot because the DDR timings are incorrect, and the Chinese vendor uses the Rockchip rk3288_ddr_400MHz_v1.09.bin loader. I'm using u-boot 2022.01 for now, and I've tried to naively modify the timing in arch/arm/dts/rk3288-evb.dts, but it doesn't work at all, with varying errors on boot. The Rockchip loader provides the following info when booting: In Channel a: DDR3 400MHz Bus Width=32 Col=10 Bank=8 Row=15 CS=1 Die Bus-Width=16 Size=1024MB Memory OK OUT Boot1 Release Time: Apr 11 2018 10:32:58, version: 2.36 ChipType = 0x8, 232 I've tried various DDR3 (not LPDDR3) settings from other boards, for example for a Firefly (666 MHz DDR3): U-Boot TPL 2022.01 (Jan 10 2022 - 18:46:34) Col detect error DRAM init failed! ### ERROR ### Please RESET the board ### It was expected that 666MHz doesn't work, but if I just change the frequency in the dts, that also fails (error -22). How can I support the DDR for this board? I can't even see what the ID on the chips is, because the heatsink is blocking sight and seems to be attached with some sort of thermal glue. Is there a way to read back the DDR timings (phy-timing, sdram-params) from the kernel/SoC on a board that is booted using the proprietary loader? Cheers! Rob Hi Rob, You could be in for a world of hurt here as Rockchip are very poor at supporting different DDR init configurations in u-boot. In the past with awkward boards I've used the Rockchip DDR init blob as the TPL binary for u-boot then skip the DRAM init in the u-boot SPL. From my travels in this area I've found that single channel RAM boards are particularly difficult to get working as the majority if not all mainlined board use dual channel RAM. Sorry I can't be more help, but trying to use the DDR blob is a good starting point to get you going on mainline. Good Luck! -- Jack Mitchell, Consultant https://www.tuxable.co.uk -- - Daniel
Re: [PATCH] net: ipv6: Fix link-partner MAC address assignment
On 12/7/22 12:25, Vyacheslav Mitrofanov V wrote: On Tue, 2022-12-06 at 13:22 +0100, Daniel Schwierzeck wrote: «Внимание! Данное письмо от внешнего адресата!» On 12/6/22 08:08, Viacheslav Mitrofanov wrote: MAC address of a link-partner is not saved for future use because of bad condition of if statement. Moreover it can potentially cause to NULL-pointer dereference. Signed-off-by: Viacheslav Mitrofanov --- net/ndisc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Daniel Schwierzeck diff --git a/net/ndisc.c b/net/ndisc.c index 3c0eeeaea3..56fc6390bc 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -264,7 +264,7 @@ int ndisc_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len) ndisc_extract_enetaddr(ndisc, neigh_eth_addr); /* save address for later use */ - if (!net_nd_packet_mac) + if (net_nd_packet_mac) memcpy(net_nd_packet_mac, neigh_eth_addr, 7); /* modify header, and transmit it */ -- - Daniel This patch is not appropriate!net_nd_packet_mac is just a pointer, moreover there is no memory allocation. It has just keep a pointer to neigh_eth_addr. So the solution must be sth. like net_nd_packet_mac = neigh_eth_addr; that wouldn't make much sense. You would assign a global pointer to an array defined in local function scope. After ndisc_receive() has finished, the pointer will have an invalid address. The same problem exists in ping6_send(). Also the pointer is assigned in net_send_udp_packet6() to an array so the memcpy in ndisc_receive() would work. BTW: the same approach is used with IPv4 and the arp_wait_packet_ethaddr pointer. The pointer is assigned in net_send_ip_packet() to an array and arp_receive() does a memcpy to that pointer if it is not NULL. I think this patch is correct but you should revisit the assignment of net_nd_packet_mac in ping6_send(). You copy net_null_ethaddr to the local mac array and assign net_nd_packet_mac to the mac array. Either the assignment is useless or it should be a memcpy too. -- - Daniel
Re: [PATCH] net: ipv6: Fix link-partner MAC address assignment
On 12/6/22 08:08, Viacheslav Mitrofanov wrote: MAC address of a link-partner is not saved for future use because of bad condition of if statement. Moreover it can potentially cause to NULL-pointer dereference. Signed-off-by: Viacheslav Mitrofanov --- net/ndisc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Daniel Schwierzeck diff --git a/net/ndisc.c b/net/ndisc.c index 3c0eeeaea3..56fc6390bc 100644 --- a/net/ndisc.c +++ b/net/ndisc.c @@ -264,7 +264,7 @@ int ndisc_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len) ndisc_extract_enetaddr(ndisc, neigh_eth_addr); /* save address for later use */ - if (!net_nd_packet_mac) + if (net_nd_packet_mac) memcpy(net_nd_packet_mac, neigh_eth_addr, 7); /* modify header, and transmit it */ -- - Daniel
Re: [PATCH] net: ipv6: Add missing break into IPv6 protocol handler
On 12/6/22 08:08, Viacheslav Mitrofanov wrote: IPv6 protocol handler is not terminated with a break statment. It can lead to running unexpected code. Signed-off-by: Viacheslav Mitrofanov --- net/net.c | 1 + 1 file changed, 1 insertion(+) thanks for the quick fix Reviewed-by: Daniel Schwierzeck diff --git a/net/net.c b/net/net.c index 1c39acc493..57da9bda85 100644 --- a/net/net.c +++ b/net/net.c @@ -1269,6 +1269,7 @@ void net_process_received_packet(uchar *in_packet, int len) #if IS_ENABLED(CONFIG_IPV6) case PROT_IP6: net_ip6_handler(et, (struct ip6_hdr *)ip, len); + break; #endif case PROT_IP: debug_cond(DEBUG_NET_PKT, "Got IP\n"); -- - Daniel
Re: [PATCH v5 04/19] net: ipv6: Add Neighbor Discovery Protocol (NDP)
On 12/2/22 10:18, Viacheslav Mitrofanov wrote:
Implement basic of NDP. It doesn't include such things as Router
Solicitation, Router Advertisement and Redirect. It just has Neighbor
Solicitation and Neighbor Advertisement. Only these two features are used
in u-boot IPv6. Implementation of some NDP functions uses API that was
exposed in "net: ipv6: Add IPv6 basic primitives".
Also this patch inlcudes update in Makefile to build NDP.
Series-changes: 3
- Added structures and functions descriptions
- Fixed style problems
Series-changes: 4
- Fixed structures and functions description style
Signed-off-by: Viacheslav Mitrofanov
Reviewed-by: Ramon Fried
Reviewed-by: Simon Glass
---
include/ndisc.h | 102 +
net/Makefile| 1 +
net/ndisc.c | 289
3 files changed, 392 insertions(+)
create mode 100644 include/ndisc.h
create mode 100644 net/ndisc.c
...
+
+int ndisc_receive(struct ethernet_hdr *et, struct ip6_hdr *ip6, int len)
+{
+ struct icmp6hdr *icmp =
+ (struct icmp6hdr *)(((uchar *)ip6) + IP6_HDR_SIZE);
+ struct nd_msg *ndisc = (struct nd_msg *)icmp;
+ uchar neigh_eth_addr[6];
+
+ switch (icmp->icmp6_type) {
+ case IPV6_NDISC_NEIGHBOUR_SOLICITATION:
+ debug("received neighbor solicitation for %pI6c from %pI6c\n",
+ >target, >saddr);
+ if (ip6_is_our_addr(>target) &&
+ ndisc_has_option(ip6, ND_OPT_SOURCE_LL_ADDR)) {
+ ndisc_extract_enetaddr(ndisc, neigh_eth_addr);
+ ip6_send_na(neigh_eth_addr, >saddr,
+ >target);
+ }
+ break;
+
+ case IPV6_NDISC_NEIGHBOUR_ADVERTISEMENT:
+ /* are we waiting for a reply ? */
+ if (ip6_is_unspecified_addr(_nd_sol_packet_ip6))
+ break;
+
+ if ((memcmp(>target, _nd_rep_packet_ip6,
+ sizeof(struct in6_addr)) == 0) &&
+ ndisc_has_option(ip6, ND_OPT_TARGET_LL_ADDR)) {
+ ndisc_extract_enetaddr(ndisc, neigh_eth_addr);
+
+ /* save address for later use */
+ if (!net_nd_packet_mac)
+ memcpy(net_nd_packet_mac, neigh_eth_addr, 7);
Coverity reports the following:
CID 430977: Null pointer dereferences (FORWARD_NULL)
Passing null pointer "net_nd_packet_mac" to "memcpy", which dereferences
it. [Note: The source code implementation of the function has been
overridden by a builtin model.]
CID 430974: Memory - corruptions (OVERRUN)
Overrunning array "neigh_eth_addr" of 6 bytes by passing it to a
function which accesses it at byte offset 6 using argument "7UL". [Note:
The source code implementation of the function has been overridden by a
builtin model.]
Did you mean to write the following which would make more sense?
if (net_nd_packet_mac)
memcpy(net_nd_packet_mac, neigh_eth_addr, 7);
+
+ /* modify header, and transmit it */
+ memcpy(((struct ethernet_hdr
*)net_nd_tx_packet)->et_dest,
+ neigh_eth_addr, 6);
+
+ net_send_packet(net_nd_tx_packet,
+ net_nd_tx_packet_size);
+
+ /* no ND request pending now */
+ net_nd_sol_packet_ip6 = net_null_addr_ip6;
+ net_nd_tx_packet_size = 0;
+ net_nd_packet_mac = NULL;
+ }
+ break;
+ default:
+ debug("Unexpected ICMPv6 type 0x%x\n", icmp->icmp6_type);
+ return -1;
+ }
+
+ return 0;
+}
--
- Daniel
Re: [PATCH v5 09/19] net: ipv6: Incorporate IPv6 support into u-boot net subsystem
On 12/2/22 10:18, Viacheslav Mitrofanov wrote:
Add net_ip6_handler (an IPv6 packet handler) into net_loop. Add
neighbor discovery mechanism into network init process. That is the
main step to run IPv6 in u-boot. Now u-boot is capable to use NDP and
handle IPv6 packets.
Signed-off-by: Viacheslav Mitrofanov
Reviewed-by: Ramon Fried
Reviewed-by: Simon Glass
---
net/net.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/net/net.c b/net/net.c
index aca20e43b0..63bf962b53 100644
--- a/net/net.c
+++ b/net/net.c
@@ -91,6 +91,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -343,8 +345,17 @@ void net_auto_load(void)
static int net_init_loop(void)
{
- if (eth_get_dev())
+ if (eth_get_dev()) {
memcpy(net_ethaddr, eth_get_ethaddr(), 6);
+
+ if (IS_ENABLED(CONFIG_IPV6)) {
+ ip6_make_lladdr(_link_local_ip6, net_ethaddr);
+ if (!memcmp(_ip6, _null_addr_ip6,
+ sizeof(struct in6_addr)))
+ memcpy(_ip6, _link_local_ip6,
+ sizeof(struct in6_addr));
+ }
+ }
else
/*
* Not ideal, but there's no way to get the actual error, and I
@@ -385,6 +396,7 @@ int net_init(void)
(i + 1) * PKTSIZE_ALIGN;
}
arp_init();
+ ndisc_init();
net_clear_handlers();
/* Only need to setup buffer pointers once. */
@@ -589,6 +601,11 @@ restart:
if (arp_timeout_check() > 0)
time_start = get_timer(0);
+ if (IS_ENABLED(CONFIG_IPV6)) {
+ if (use_ip6 && (ndisc_timeout_check() > 0))
+ time_start = get_timer(0);
+ }
+
/*
* Check the ethernet for a new packet. The ethernet
* receive routine will process it.
@@ -1243,6 +1260,10 @@ void net_process_received_packet(uchar *in_packet, int
len)
case PROT_RARP:
rarp_receive(ip, len);
break;
+#endif
+#if IS_ENABLED(CONFIG_IPV6)
+ case PROT_IP6:
+ net_ip6_handler(et, (struct ip6_hdr *)ip, len);
#endif
Coverity reports the following:
CID 430975: Control flow issues (MISSING_BREAK)
The case for value "34525" is not terminated by a "break" statement.
Either a 'break;' or a 'fallthrough;' is missing. It looks like
net_ip6_handler() already handles ICMP and UDP so probably the PROT_IP
case shouldn't be executed at all. Therefore you should add a 'break;'.
case PROT_IP:
debug_cond(DEBUG_NET_PKT, "Got IP\n");
--
- Daniel
[PULL] u-boot-mips
Hi Tom, please pull the Kconfig migration for CONFIG_SYS_MIPS_TIMER_FREQ as well as the mtmips bugfix for the incorrectly converted default value for CONFIG_SPL_PAD_TO. Gitlab: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/14002 The following changes since commit cca41ed3d63f462ca044e0d2d30a34d4917fc6c5: Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-watchdog (2022-11-02 09:10:30 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2022-11-03 for you to fetch changes up to 8450b97bf4464ab8b9c1b33b5a9150ae80c6136e: mips: mtmips: spl/Kconfig: Set CONFIG_SPL_PAD_TO to 0x0 for ARCH_MTMIPS (2022-11-02 21:54:26 +0100) - MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig - MIPS: mtmips: fix incorrectly converted default value for CONFIG_SPL_PAD_TO Daniel Schwierzeck (4): MIPS: remove deprecated TARGET_VCT option MIPS: remove CONFIG_SYS_MHZ MIPS: mscc: remove unused CPU_CLOCK_RATE MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig Stefan Roese (1): mips: mtmips: spl/Kconfig: Set CONFIG_SPL_PAD_TO to 0x0 for ARCH_MTMIPS arch/mips/Kconfig | 26 ++ arch/mips/mach-jz47xx/include/mach/jz4780.h| 2 +- arch/mips/mach-jz47xx/jz4780/pll.c | 6 +- board/imgtec/ci20/ci20.c | 4 common/spl/Kconfig | 1 + configs/ap121_defconfig| 1 + configs/ap143_defconfig| 1 + configs/ap152_defconfig| 1 + configs/bcm968380gerg_ram_defconfig| 1 + configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/boston32r6_defconfig | 1 + configs/boston32r6el_defconfig | 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig | 1 + configs/boston64r6_defconfig | 1 + configs/boston64r6el_defconfig | 1 + configs/ci20_mmc_defconfig | 1 + configs/comtrend_ar5315u_ram_defconfig | 1 + configs/comtrend_ar5387un_ram_defconfig| 1 + configs/comtrend_ct5361_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/comtrend_wap5813n_ram_defconfig| 1 + configs/gardena-smart-gateway-mt7688_defconfig | 1 + configs/huawei_hg556a_ram_defconfig| 1 + configs/imgtec_xilfpga_defconfig | 1 + configs/linkit-smart-7688_defconfig| 1 + configs/malta64_defconfig | 1 + configs/malta64el_defconfig| 1 + configs/malta_defconfig| 1 + configs/maltael_defconfig | 1 + configs/mscc_jr2_defconfig | 1 + configs/mscc_luton_defconfig | 1 + configs/mscc_ocelot_defconfig | 1 + configs/mscc_serval_defconfig | 1 + configs/mscc_servalt_defconfig | 1 + configs/mt7620_mt7530_rfb_defconfig| 1 + configs/mt7620_rfb_defconfig | 1 + configs/mt7621_nand_rfb_defconfig | 1 + configs/mt7621_rfb_defconfig | 1 + configs/mt7628_rfb_defconfig | 1 + configs/netgear_cg3100d_ram_defconfig | 1 + configs/netgear_dgnd3700v2_ram_defconfig | 1 + configs/pic32mzdask_defconfig | 1 + configs/sagem_f@st1704_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + configs/tplink_wdr4300_defconfig | 1 + configs/vocore2_defconfig | 1 + include/configs/ap121.h| 3 --- include/configs/ap143.h| 3 --- include/configs/ap152.h| 3 --- include/configs/bmips_bcm3380.h| 3 --- include/configs/bmips_bcm6318.h| 3 --- include/configs/bmips_bcm63268.h | 3 --- include/configs/bmips_bcm6328.h| 3 --- include/configs/bmips_bcm6338.h| 3 --- include/configs/bmips_bcm6348.h| 3 --- include/configs/bmips_bcm6358.h| 3 --- include/configs/bmips_bcm6362.h| 3 --- include/configs/bmips_bcm6368.h| 3 --- include/configs/bmips_bcm6838.h| 3 --- include/configs/boston.h | 1 - include/configs/ci20.h | 4 include/configs/gardena-smart-gateway-mt7688.h | 3 --- include/configs/imgtec_xilfpga.h | 2 -- include/configs/linkit-smart
Re: [PATCH] mips: mtmips: spl/Kconfig: Set CONFIG_SPL_PAD_TO to 0x0 for ARCH_MTMIPS
On 10/28/22 14:46, Stefan Roese wrote:
It was noticed that while converting CONFIG_SPL_PAD_TO to Kconfig its
value for the MIPS MT762x/8x targets got not ported correctly. Its
default is not 0x1 instead of 0x0. This patch fixes this issue.
Fixes: ca8a329a1b7f ("Convert CONFIG_SPL_PAD_TO et al to Kconfig")
Signed-off-by: Stefan Roese
Cc: Ruben Winters
Cc: Weijie Gao
Cc: Daniel Schwierzeck
Cc: Tom Rini
---
common/spl/Kconfig | 1 +
1 file changed, 1 insertion(+)
applied to u-boot-mips, thanks
--
- Daniel
Re: [ISSUE] Failure to compile for MIPS32 using maltael_defconfig
On 9/29/22 05:45, Majid B. wrote: Hello, I've tried to build U-Boot 2022.07 with the following series of instructions: export CROSS_COMPILE=mipsel-linux-gnu- make mrproper make O=build maltael_defconfig make V=1 O=build -j$(nproc) Unfortunately, I seem to always run into this error: In file included from arch/mips/lib/cache.c:10: ./arch/mips/include/asm/cacheops.h: In function ‘flush_cache’: ./arch/mips/include/asm/cacheops.h:18:9: error: invalid argument to built-in function 18 | __builtin_mips_cache(op, addr); | ^~ make[1]: *** [scripts/Makefile.build:257: arch/mips/lib/cache.o] Error 1 make[1]: *** Waiting for unfinished jobs make: *** [Makefile:1906: arch/mips/lib] Error 2 make: *** Waiting for unfinished jobs What could I be doing wrong? what toolchain you are using? Is the toolchain bin path set in your PATH variable? If not, you need to include the absolute path to the toolchain in your CROSS_COMPILE variable. So either do (my example uses the kernel.org toolchains): export PATH=/opt/gcc-11.1.0-nolibc/mips-linux/bin:$PATH export CROSS_COMPILE=mips-linux- or export CROSS_COMPILE=/opt/gcc-11.1.0-nolibc/mips-linux/bin/mips-linux- To rule out toolchain issues, you could always try the kernel.org toolchains, with which all U-Boot configs are built in CI. You could use U-Boot's buildman tool to download those toolchains for each supported architecture. E.g. ./tools/buildman/buildman --fetch-arch mips ./tools/buildman/buildman --list-tool-chains I'd really appreciate any help I can get on this. Thank you in advance! Regards, Majid B. -- - Daniel
[PULL] u-boot-mips for v2022.10
Hi Tom, this time with all Kconfig migrations from -next included ;) Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/12740 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=31=results The following changes since commit 357fa8bb4d40abf411a6cca70f5a2dd6413028ea: Merge tag 'u-boot-stm32-20220712' of https://source.denx.de/u-boot/custodians/u-boot-stm (2022-07-13 08:09:20 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2022-07-13 for you to fetch changes up to dd6bf539e88aff1b8caeeccbe9af59b2191a178b: MAINTAINERS: update maintainer for MediaTek MIPS platform (2022-07-13 23:03:37 +0200) - MIPS: add drivers and board support for Mediatek MT7621 SoC Weijie Gao (25): mips: add asm/mipsmtregs.h for MIPS multi-threading mips: add more definitions for asm/cm.h mips: add __image_copy_len for SPL linker script mips: add support for noncached_alloc() mips: mtmips: add support for MediaTek MT7621 SoC mips: mtmips: add two reference boards for mt7621 doc: mediatek: add documentation for mt7621 reference boards clk: mtmips: add clock driver for MediaTek MT7621 SoC reset: mtmips: add reset controller support for MediaTek MT7621 SoC pinctrl: mtmips: add support for MediaTek MT7621 SoC usb: xhci-mtk: add support for MediaTek MT7621 SoC phy: mtk-tphy: add support for MediaTek MT7621 SoC spi: add support for MediaTek MT7621 SoC gpio: add support for MediaTek MT7621 SoC watchdog: add support for MediaTek MT7621 SoC mmc: mediatek: add support for MediaTek MT7621 SoC net: mediatek: remap iobase address net: mediatek: use regmap api to modify ethsys registers net: mediatek: add support for MediaTek MT7621 SoC nand: raw: add support for MediaTek MT7621 SoC spl: allow using nand base without standard nand driver spl: spl_legacy: fix the use of SPL_COPY_PAYLOAD_ONLY spl: nand: support loading legacy image with payload compressed tools: mtk_image: add support for MT7621 NAND images MAINTAINERS: update maintainer for MediaTek MIPS platform MAINTAINERS|8 + arch/mips/Makefile |5 + arch/mips/cpu/u-boot-spl.lds |3 + arch/mips/dts/Makefile |2 + arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 ++ arch/mips/dts/mediatek,mt7621-rfb.dts | 82 ++ arch/mips/dts/mt7621-u-boot.dtsi | 111 +++ arch/mips/dts/mt7621.dtsi | 349 +++ arch/mips/include/asm/cm.h | 67 ++ arch/mips/include/asm/mipsmtregs.h | 142 +++ arch/mips/include/asm/system.h | 20 + arch/mips/lib/cache.c | 43 + arch/mips/mach-mtmips/Kconfig | 49 +- arch/mips/mach-mtmips/Makefile |4 + arch/mips/mach-mtmips/cpu.c|2 +- arch/mips/mach-mtmips/mt7621/Kconfig | 115 +++ arch/mips/mach-mtmips/mt7621/Makefile | 14 + arch/mips/mach-mtmips/mt7621/init.c| 246 + arch/mips/mach-mtmips/mt7621/mt7621.h | 229 + arch/mips/mach-mtmips/mt7621/serial.c | 23 + arch/mips/mach-mtmips/mt7621/spl/Makefile |9 + arch/mips/mach-mtmips/mt7621/spl/cps.c | 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.c| 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.h| 39 + arch/mips/mach-mtmips/mt7621/spl/launch.c | 100 ++ arch/mips/mach-mtmips/mt7621/spl/launch.h | 52 + arch/mips/mach-mtmips/mt7621/spl/launch_ll.S | 339 +++ arch/mips/mach-mtmips/mt7621/spl/serial.c | 24 + arch/mips/mach-mtmips/mt7621/spl/spl.c | 96 ++ arch/mips/mach-mtmips/mt7621/spl/start.S | 226 + arch/mips/mach-mtmips/mt7621/sram_init.S | 22 + arch/mips/mach-mtmips/mt7621/tpl/Makefile |4 + arch/mips/mach-mtmips/mt7621/tpl/start.S | 161 arch/mips/mach-mtmips/mt7621/tpl/tpl.c | 144 +++ board/mediatek/mt7621/MAINTAINERS |8 + board/mediatek/mt7621/Makefile |3 + board/mediatek/mt7621/board.c |6 + common/spl/Kconfig |2 +- common/spl/spl_legacy.c| 21 +- common/spl/spl_nand.c | 27 + configs/mt7621_nand_rfb_defconfig | 89 ++ configs/mt7621_rfb_defconfig | 86 ++ doc/board/index.rst|1 + doc/board/mediatek/index.rst |9 + doc/board/mediatek/mt7621.rst | 48 +
[PATCH 4/4] MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
This converts the following to Kconfig: CONFIG_SYS_MIPS_TIMER_REQ Signed-off-by: Daniel Schwierzeck --- arch/mips/Kconfig | 18 ++ configs/ap121_defconfig| 1 + configs/ap143_defconfig| 1 + configs/ap152_defconfig| 1 + configs/bcm968380gerg_ram_defconfig| 1 + configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig | 1 + configs/boston32r6_defconfig | 1 + configs/boston32r6el_defconfig | 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig | 1 + configs/boston64r6_defconfig | 1 + configs/boston64r6el_defconfig | 1 + configs/ci20_mmc_defconfig | 1 + configs/comtrend_ar5315u_ram_defconfig | 1 + configs/comtrend_ar5387un_ram_defconfig| 1 + configs/comtrend_ct5361_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig | 1 + configs/comtrend_wap5813n_ram_defconfig| 1 + configs/gardena-smart-gateway-mt7688_defconfig | 1 + configs/huawei_hg556a_ram_defconfig| 1 + configs/imgtec_xilfpga_defconfig | 1 + configs/linkit-smart-7688_defconfig| 1 + configs/malta64_defconfig | 1 + configs/malta64el_defconfig| 1 + configs/malta_defconfig| 1 + configs/maltael_defconfig | 1 + configs/mscc_jr2_defconfig | 1 + configs/mscc_luton_defconfig | 1 + configs/mscc_ocelot_defconfig | 1 + configs/mscc_serval_defconfig | 1 + configs/mscc_servalt_defconfig | 1 + configs/mt7620_mt7530_rfb_defconfig| 1 + configs/mt7620_rfb_defconfig | 1 + configs/mt7621_nand_rfb_defconfig | 1 + configs/mt7621_rfb_defconfig | 1 + configs/mt7628_rfb_defconfig | 1 + configs/netgear_cg3100d_ram_defconfig | 1 + configs/netgear_dgnd3700v2_ram_defconfig | 1 + configs/pic32mzdask_defconfig | 1 + configs/sagem_f@st1704_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + configs/tplink_wdr4300_defconfig | 1 + configs/vocore2_defconfig | 1 + include/configs/ap121.h| 2 -- include/configs/ap143.h| 2 -- include/configs/ap152.h| 2 -- include/configs/bmips_bcm3380.h| 3 --- include/configs/bmips_bcm6318.h| 3 --- include/configs/bmips_bcm63268.h | 3 --- include/configs/bmips_bcm6328.h| 3 --- include/configs/bmips_bcm6338.h| 3 --- include/configs/bmips_bcm6348.h| 3 --- include/configs/bmips_bcm6358.h| 3 --- include/configs/bmips_bcm6362.h| 3 --- include/configs/bmips_bcm6368.h| 3 --- include/configs/bmips_bcm6838.h| 3 --- include/configs/boston.h | 1 - include/configs/ci20.h | 3 --- include/configs/gardena-smart-gateway-mt7688.h | 3 --- include/configs/imgtec_xilfpga.h | 2 -- include/configs/linkit-smart-7688.h| 3 --- include/configs/malta.h| 1 - include/configs/mt7620.h | 2 -- include/configs/mt7621.h | 2 -- include/configs/mt7628.h | 2 -- include/configs/pic32mzdask.h | 2 -- include/configs/tplink_wdr4300.h | 2 -- include/configs/vcoreiii.h | 5 - include/configs/vocore2.h | 3 --- scripts/config_whitelist.txt | 1 - 71 files changed, 61 insertions(+), 68 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8bef63cbb7..9af0133f10 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -14,6 +14,7 @@ choice config TARGET_MALTA bool "Support malta" + select HAS_FIXED_TIMER_FREQUENCY select BOARD_EARLY_INIT_R select DM select DM_SERIAL @@ -41,17 +42,20 @@ config TARGET_MALTA config ARCH_ATH79 bool "Support QCA/Atheros ath79" + select HAS_FIXED_TIMER_FREQUENCY select DM select OF_CONTROL imply CMD_DM config ARCH_MSCC bool "Support MSCC VCore-III" + select HAS_FIXED_TIMER_FREQUENCY select OF_CONTROL select DM config ARCH_BMIPS bool "Support BMIPS SoCs" + select HAS_FIXED_TIMER_FREQUENCY select CLK select CPU selec
[PATCH 2/4] MIPS: remove CONFIG_SYS_MHZ
Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
Remove code which depends on CONFIG_SYS_MHZ but where no board configs
actually use that code.
Signed-off-by: Daniel Schwierzeck
---
arch/mips/mach-jz47xx/include/mach/jz4780.h | 2 +-
arch/mips/mach-jz47xx/jz4780/pll.c | 6 +-
board/imgtec/ci20/ci20.c| 4
include/configs/ap121.h | 3 +--
include/configs/ap143.h | 3 +--
include/configs/ap152.h | 3 +--
include/configs/ci20.h | 3 +--
include/configs/malta.h | 3 +--
include/configs/tplink_wdr4300.h| 3 +--
scripts/config_whitelist.txt| 1 -
10 files changed, 8 insertions(+), 23 deletions(-)
diff --git a/arch/mips/mach-jz47xx/include/mach/jz4780.h
b/arch/mips/mach-jz47xx/include/mach/jz4780.h
index 4422e503ed..880445dac3 100644
--- a/arch/mips/mach-jz47xx/include/mach/jz4780.h
+++ b/arch/mips/mach-jz47xx/include/mach/jz4780.h
@@ -60,7 +60,7 @@
/* PLL setup */
#define JZ4780_SYS_EXTAL 4800
-#define JZ4780_SYS_MEM_SPEED (CONFIG_SYS_MHZ * 100)
+#define JZ4780_SYS_MEM_SPEED (1200 * 100)
#define JZ4780_SYS_MEM_DIV 3
#define JZ4780_SYS_AUDIO_SPEED (768 * 100)
diff --git a/arch/mips/mach-jz47xx/jz4780/pll.c
b/arch/mips/mach-jz47xx/jz4780/pll.c
index 323c634fb3..4519b478cc 100644
--- a/arch/mips/mach-jz47xx/jz4780/pll.c
+++ b/arch/mips/mach-jz47xx/jz4780/pll.c
@@ -399,11 +399,7 @@ static void cpu_mux_select(int pll)
((2 - 1) << CPM_CPCCR_L2DIV_BIT) |
((1 - 1) << CPM_CPCCR_CDIV_BIT);
- if (CONFIG_SYS_MHZ >= 1000)
- clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
- else
- clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT;
-
+ clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT;
clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ff, clk_ctrl);
while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY |
diff --git a/board/imgtec/ci20/ci20.c b/board/imgtec/ci20/ci20.c
index 7cbe49abd9..89f5e7ad79 100644
--- a/board/imgtec/ci20/ci20.c
+++ b/board/imgtec/ci20/ci20.c
@@ -350,10 +350,6 @@ static const struct jz4780_ddr_config
H5TQ2G83CFR_48_config = {
.pulldn = 0x0e,
};
-#if (CONFIG_SYS_MHZ != 1200)
-#error No DDR configuration for CPU speed
-#endif
-
const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
{
const int board_revision = ci20_revision();
diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 099aac5421..61cc073a8a 100644
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -6,8 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_MHZ 200
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+#define CONFIG_SYS_MIPS_TIMER_FREQ 2
#define CONFIG_SYS_SDRAM_BASE 0x8000
diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index 60b9e779fa..579b9b4f2c 100644
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -6,8 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_MHZ 325
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+#define CONFIG_SYS_MIPS_TIMER_FREQ 32500
#define CONFIG_SYS_SDRAM_BASE 0x8000
diff --git a/include/configs/ap152.h b/include/configs/ap152.h
index d165ead7bb..283762fd22 100644
--- a/include/configs/ap152.h
+++ b/include/configs/ap152.h
@@ -6,8 +6,7 @@
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_SYS_MHZ 375
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+#define CONFIG_SYS_MIPS_TIMER_FREQ 37500
#define CONFIG_SYS_SDRAM_BASE 0x8000
diff --git a/include/configs/ci20.h b/include/configs/ci20.h
index 192da015e1..7e8a9fcb80 100644
--- a/include/configs/ci20.h
+++ b/include/configs/ci20.h
@@ -10,8 +10,7 @@
#define __CONFIG_CI20_H__
/* Ingenic JZ4780 clock configuration. */
-#define CONFIG_SYS_MHZ 1200
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+#define CONFIG_SYS_MIPS_TIMER_FREQ 12
/* Memory configuration */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
diff --git a/include/configs/malta.h b/include/configs/malta.h
index c8b230ab21..717867d12a 100644
--- a/include/configs/malta.h
+++ b/include/configs/malta.h
@@ -18,8 +18,7 @@
/*
* CPU Configuration
*/
-#define CONFIG_SYS_MHZ 250 /* arbitrary value */
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+#define CONFIG_SYS_MIPS_TIMER_FREQ 25000
/*
* Memory map
diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index f5466fd509..1400a211e3 100644
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -6,8 +6,7 @@
#ifndef __CO
[PATCH 1/4] MIPS: remove deprecated TARGET_VCT option
This board has been removed a long time ago. Signed-off-by: Daniel Schwierzeck --- arch/mips/Kconfig | 8 1 file changed, 8 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 2e0793a7a7..8bef63cbb7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -39,14 +39,6 @@ config TARGET_MALTA select SWAP_IO_SPACE imply CMD_DM -config TARGET_VCT - bool "Support vct" - select ROM_EXCEPTION_VECTORS - select SUPPORTS_BIG_ENDIAN - select SUPPORTS_CPU_MIPS32_R1 - select SUPPORTS_CPU_MIPS32_R2 - select SYS_MIPS_CACHE_INIT_RAM_LOAD - config ARCH_ATH79 bool "Support QCA/Atheros ath79" select DM -- 2.37.0
[PATCH 3/4] MIPS: mscc: remove unused CPU_CLOCK_RATE
CPU_CLOCK_RATE is just used once for CONFIG_SYS_MIPS_TIMER_FREQ which is migrated to Kconfig in the next patch. Signed-off-by: Daniel Schwierzeck --- include/configs/vcoreiii.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h index 78a62a8b02..5c5036b8be 100644 --- a/include/configs/vcoreiii.h +++ b/include/configs/vcoreiii.h @@ -13,11 +13,9 @@ #define CONFIG_SYS_INIT_SP_OFFSET 0x40 #if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL) -#define CPU_CLOCK_RATE 41666 /* Clock for the MIPS core */ #define CONFIG_SYS_MIPS_TIMER_FREQ 20833 #else -#define CPU_CLOCK_RATE 5 /* Clock for the MIPS core */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) +#define CONFIG_SYS_MIPS_TIMER_FREQ 25000 #endif #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ -- 2.37.0
[PATCH 0/4] Convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
This removes CONFIG_SYS_HZ and converts CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig. The series only applies on u-boot-mips/next (based on u-boot/next and the Mediatek MT7621 series). Daniel Schwierzeck (4): MIPS: remove deprecated TARGET_VCT option MIPS: remove CONFIG_SYS_MHZ MIPS: mscc: remove unused CPU_CLOCK_RATE MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig arch/mips/Kconfig | 26 +-- arch/mips/mach-jz47xx/include/mach/jz4780.h | 2 +- arch/mips/mach-jz47xx/jz4780/pll.c| 6 + board/imgtec/ci20/ci20.c | 4 --- configs/ap121_defconfig | 1 + configs/ap143_defconfig | 1 + configs/ap152_defconfig | 1 + configs/bcm968380gerg_ram_defconfig | 1 + configs/boston32r2_defconfig | 1 + configs/boston32r2el_defconfig| 1 + configs/boston32r6_defconfig | 1 + configs/boston32r6el_defconfig| 1 + configs/boston64r2_defconfig | 1 + configs/boston64r2el_defconfig| 1 + configs/boston64r6_defconfig | 1 + configs/boston64r6el_defconfig| 1 + configs/ci20_mmc_defconfig| 1 + configs/comtrend_ar5315u_ram_defconfig| 1 + configs/comtrend_ar5387un_ram_defconfig | 1 + configs/comtrend_ct5361_ram_defconfig | 1 + configs/comtrend_vr3032u_ram_defconfig| 1 + configs/comtrend_wap5813n_ram_defconfig | 1 + .../gardena-smart-gateway-mt7688_defconfig| 1 + configs/huawei_hg556a_ram_defconfig | 1 + configs/imgtec_xilfpga_defconfig | 1 + configs/linkit-smart-7688_defconfig | 1 + configs/malta64_defconfig | 1 + configs/malta64el_defconfig | 1 + configs/malta_defconfig | 1 + configs/maltael_defconfig | 1 + configs/mscc_jr2_defconfig| 1 + configs/mscc_luton_defconfig | 1 + configs/mscc_ocelot_defconfig | 1 + configs/mscc_serval_defconfig | 1 + configs/mscc_servalt_defconfig| 1 + configs/mt7620_mt7530_rfb_defconfig | 1 + configs/mt7620_rfb_defconfig | 1 + configs/mt7621_nand_rfb_defconfig | 1 + configs/mt7621_rfb_defconfig | 1 + configs/mt7628_rfb_defconfig | 1 + configs/netgear_cg3100d_ram_defconfig | 1 + configs/netgear_dgnd3700v2_ram_defconfig | 1 + configs/pic32mzdask_defconfig | 1 + configs/sagem_f@st1704_ram_defconfig | 1 + configs/sfr_nb4-ser_ram_defconfig | 1 + configs/tplink_wdr4300_defconfig | 1 + configs/vocore2_defconfig | 1 + include/configs/ap121.h | 3 --- include/configs/ap143.h | 3 --- include/configs/ap152.h | 3 --- include/configs/bmips_bcm3380.h | 3 --- include/configs/bmips_bcm6318.h | 3 --- include/configs/bmips_bcm63268.h | 3 --- include/configs/bmips_bcm6328.h | 3 --- include/configs/bmips_bcm6338.h | 3 --- include/configs/bmips_bcm6348.h | 3 --- include/configs/bmips_bcm6358.h | 3 --- include/configs/bmips_bcm6362.h | 3 --- include/configs/bmips_bcm6368.h | 3 --- include/configs/bmips_bcm6838.h | 3 --- include/configs/boston.h | 1 - include/configs/ci20.h| 4 --- .../configs/gardena-smart-gateway-mt7688.h| 3 --- include/configs/imgtec_xilfpga.h | 2 -- include/configs/linkit-smart-7688.h | 3 --- include/configs/malta.h | 2 -- include/configs/mt7620.h | 2 -- include/configs/mt7621.h | 2 -- include/configs/mt7628.h | 2 -- include/configs/pic32mzdask.h | 2 -- include/configs/tplink_wdr4300.h | 3 --- include/configs/vcoreiii.h| 7 - include/configs/vocore2.h | 3 --- scripts/config_whitelist.txt | 2 -- 74 files changed, 63 insertions(+), 95 deletions(-) -- 2.37.0
Re: [PULL] u-boot-mips for u-boot/next (v2022.10)
On 09.07.22 14:43, Tom Rini wrote: On Sat, Jul 09, 2022 at 02:01:01PM +0200, Daniel Schwierzeck wrote: Hi Tom, On 08.07.22 18:50, Tom Rini wrote: On Fri, Jul 08, 2022 at 05:21:48PM +0200, Daniel SchwierzeckHi Tom, wrote: Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/12656 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=30=results The following changes since commit 2d2c61ff0460740d9ec5a44dbef9255a8c690696: Merge tag 'efi-2022-07-rc7' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-07-06 09:17:08 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2022-07-08 for you to fetch changes up to e5fc4022af3cfd59e3459276305671a595ac5ff0: MAINTAINERS: update maintainer for MediaTek MIPS platform (2022-07-08 15:13:29 +0200) - MIPS: add drivers and board support for Mediatek MT7621 SoC OK, we need a few changes here, sorry. There's now migrated CONFIG symbols, most of which are easy to do and I was about to, and then I saw this: #ifdef CONFIG_TPL_BUILD #define CONFIG_SPL_START_S_PATH "arch/mips/mach-mtmips/mt7621/tpl" /* .bss will not be used by TPL */ #define CONFIG_SPL_BSS_START_ADDR 0x8000 #define CONFIG_SPL_BSS_MAX_SIZE 0 #else #define CONFIG_SPL_START_S_PATH "arch/mips/mach-mtmips/mt7621/spl" #define CONFIG_SPL_BSS_START_ADDR 0x8014 #define CONFIG_SPL_BSS_MAX_SIZE 0x8 #define CONFIG_SPL_MAX_SIZE 0x3 #endif No, you cannot abuse CONFIG_TPL_BUILD to set CONFIG_SPL_foo. Those need to become CONFIG_TPL_foo, and set appropriately. And then for [ST]PL_START_S_PATH, you need to set head-$(CONFIG_ARCH_xxx) to the right file, for SPL/TPL instead. do you already have patches for converting stuff like CONFIG_SPL_BSS_START_ADDR prepared? Than I would wait with the pull request until those patches are applied to mainline and I would adapt the MT7621 patches. I could also assist with converting CONFIG_SPL_START_S_PATH because that's only used on MIPS and one ARM board. See what's in -next already? SPL_BSS_START_ADDR is migrated, but there were no TPL_BSS_START_ADDR cases. For START_S_PATH, the platform just needs to be reworked as I suggested above I believe, to achieve the desired result. sorry, didn't check the latest updates in -next and the series was too long on the list ;) TPL_BSS_START_ADDR shouldn't be necessary because MT7621 doesn't use BSS in TPL, the defined values where just dummy values. I rechecked and removed all migrated Kconfig options from mt7621.h and pushed an update to u-boot-mips/next. Weijie could you verify that? If all is okay, I'll prepare a new pull request, otherwise please send me a v7 patch series. -- - Daniel
Re: [PULL] u-boot-mips for u-boot/next (v2022.10)
Hi Tom, On 08.07.22 18:50, Tom Rini wrote: On Fri, Jul 08, 2022 at 05:21:48PM +0200, Daniel SchwierzeckHi Tom, wrote: Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/12656 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=30=results The following changes since commit 2d2c61ff0460740d9ec5a44dbef9255a8c690696: Merge tag 'efi-2022-07-rc7' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-07-06 09:17:08 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2022-07-08 for you to fetch changes up to e5fc4022af3cfd59e3459276305671a595ac5ff0: MAINTAINERS: update maintainer for MediaTek MIPS platform (2022-07-08 15:13:29 +0200) - MIPS: add drivers and board support for Mediatek MT7621 SoC OK, we need a few changes here, sorry. There's now migrated CONFIG symbols, most of which are easy to do and I was about to, and then I saw this: #ifdef CONFIG_TPL_BUILD #define CONFIG_SPL_START_S_PATH "arch/mips/mach-mtmips/mt7621/tpl" /* .bss will not be used by TPL */ #define CONFIG_SPL_BSS_START_ADDR 0x8000 #define CONFIG_SPL_BSS_MAX_SIZE 0 #else #define CONFIG_SPL_START_S_PATH "arch/mips/mach-mtmips/mt7621/spl" #define CONFIG_SPL_BSS_START_ADDR 0x8014 #define CONFIG_SPL_BSS_MAX_SIZE 0x8 #define CONFIG_SPL_MAX_SIZE 0x3 #endif No, you cannot abuse CONFIG_TPL_BUILD to set CONFIG_SPL_foo. Those need to become CONFIG_TPL_foo, and set appropriately. And then for [ST]PL_START_S_PATH, you need to set head-$(CONFIG_ARCH_xxx) to the right file, for SPL/TPL instead. do you already have patches for converting stuff like CONFIG_SPL_BSS_START_ADDR prepared? Than I would wait with the pull request until those patches are applied to mainline and I would adapt the MT7621 patches. I could also assist with converting CONFIG_SPL_START_S_PATH because that's only used on MIPS and one ARM board. -- - Daniel
[PULL] u-boot-mips for u-boot/next (v2022.10)
Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/12656 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=30=results The following changes since commit 2d2c61ff0460740d9ec5a44dbef9255a8c690696: Merge tag 'efi-2022-07-rc7' of https://source.denx.de/u-boot/custodians/u-boot-efi (2022-07-06 09:17:08 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2022-07-08 for you to fetch changes up to e5fc4022af3cfd59e3459276305671a595ac5ff0: MAINTAINERS: update maintainer for MediaTek MIPS platform (2022-07-08 15:13:29 +0200) - MIPS: add drivers and board support for Mediatek MT7621 SoC Weijie Gao (25): mips: add asm/mipsmtregs.h for MIPS multi-threading mips: add more definitions for asm/cm.h mips: add __image_copy_len for SPL linker script mips: add support for noncached_alloc() mips: mtmips: add support for MediaTek MT7621 SoC mips: mtmips: add two reference boards for mt7621 doc: mediatek: add documentation for mt7621 reference boards clk: mtmips: add clock driver for MediaTek MT7621 SoC reset: mtmips: add reset controller support for MediaTek MT7621 SoC pinctrl: mtmips: add support for MediaTek MT7621 SoC usb: xhci-mtk: add support for MediaTek MT7621 SoC phy: mtk-tphy: add support for MediaTek MT7621 SoC spi: add support for MediaTek MT7621 SoC gpio: add support for MediaTek MT7621 SoC watchdog: add support for MediaTek MT7621 SoC mmc: mediatek: add support for MediaTek MT7621 SoC net: mediatek: remap iobase address net: mediatek: use regmap api to modify ethsys registers net: mediatek: add support for MediaTek MT7621 SoC nand: raw: add support for MediaTek MT7621 SoC spl: allow using nand base without standard nand driver spl: spl_legacy: fix the use of SPL_COPY_PAYLOAD_ONLY spl: nand: support loading legacy image with payload compressed tools: mtk_image: add support for MT7621 NAND images MAINTAINERS: update maintainer for MediaTek MIPS platform MAINTAINERS|8 + arch/mips/cpu/u-boot-spl.lds |3 + arch/mips/dts/Makefile |2 + arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 ++ arch/mips/dts/mediatek,mt7621-rfb.dts | 82 ++ arch/mips/dts/mt7621-u-boot.dtsi | 111 +++ arch/mips/dts/mt7621.dtsi | 349 +++ arch/mips/include/asm/cm.h | 67 ++ arch/mips/include/asm/mipsmtregs.h | 142 +++ arch/mips/include/asm/system.h | 20 + arch/mips/lib/cache.c | 43 + arch/mips/mach-mtmips/Kconfig | 49 +- arch/mips/mach-mtmips/Makefile |4 + arch/mips/mach-mtmips/cpu.c|2 +- arch/mips/mach-mtmips/mt7621/Kconfig | 115 +++ arch/mips/mach-mtmips/mt7621/Makefile | 14 + arch/mips/mach-mtmips/mt7621/init.c| 246 + arch/mips/mach-mtmips/mt7621/mt7621.h | 229 + arch/mips/mach-mtmips/mt7621/serial.c | 23 + arch/mips/mach-mtmips/mt7621/spl/Makefile |9 + arch/mips/mach-mtmips/mt7621/spl/cps.c | 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.c| 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.h| 39 + arch/mips/mach-mtmips/mt7621/spl/launch.c | 100 ++ arch/mips/mach-mtmips/mt7621/spl/launch.h | 52 + arch/mips/mach-mtmips/mt7621/spl/launch_ll.S | 339 +++ arch/mips/mach-mtmips/mt7621/spl/serial.c | 24 + arch/mips/mach-mtmips/mt7621/spl/spl.c | 95 ++ arch/mips/mach-mtmips/mt7621/spl/start.S | 226 + arch/mips/mach-mtmips/mt7621/sram_init.S | 22 + arch/mips/mach-mtmips/mt7621/tpl/Makefile |4 + arch/mips/mach-mtmips/mt7621/tpl/start.S | 161 arch/mips/mach-mtmips/mt7621/tpl/tpl.c | 144 +++ board/mediatek/mt7621/MAINTAINERS |8 + board/mediatek/mt7621/Makefile |3 + board/mediatek/mt7621/board.c |6 + common/spl/Kconfig |2 +- common/spl/spl_legacy.c| 21 +- common/spl/spl_nand.c | 27 + configs/mt7621_nand_rfb_defconfig | 85 ++ configs/mt7621_rfb_defconfig | 82 ++ doc/board/index.rst|1 + doc/board/mediatek/index.rst |9 + doc/board/mediatek/mt7621.rst | 48 + drivers/clk/mtmips/Makefile|1 + drivers/clk/mtmips/clk-mt7621.c| 288 ++
Re: [PATCH v6 00/25] Add support for MediaTek MT7621 SoC - v6
On 20.05.22 05:21, Weijie Gao wrote: This series will add support for MediaTek MT7621 SoC with two reference boards and related drivers. The MediaTek MT7621 is a network processor integrating a dual-core dual-threaded MIPS 1004Kc processor running at a normal frequency of 880MHz. This chip can be found in many wireless routers. This series add all basic drivers which are useful in u-boot, like usb, sdxc, ethernet, spi, nand and serial. Building the u-boot requires external binary blob which is described in doc/board/mediatek/mt7621.rst Thanks, Weijie v6 changes: - Use FIELD_GET/FIELD_PREP for register fields instead of shift opertations - Rename fixed clock node name in mt7621.dtsi - Panic if dram binary blob is wrong in spl - Remove redundant nop's if noreorder is not used - Use execution_hazard_barrier() in tpl v5 changes: - Adjust mt7621.dtsi, clkctrl node moved to sysc, pinctrl default states moved to board dts files - Modify clk driver due to its node changed in mt7621.dtsi - Minor fixes v4 changes: - Add full support for booting from flash v3 changes: - Rewrite clk driver to follow definitions from upstream kernel - Implement noncached_alloc() for MIPS platform - Update register remap for mtk-eth driver needed by mt7621 v2 changes: - Add a kconfig for max supported ram size - Remove network configs from default config file - Add config file for mt7621-rfb boards Weijie Gao (25): mips: add asm/mipsmtregs.h for MIPS multi-threading mips: add more definitions for asm/cm.h mips: add __image_copy_len for SPL linker script mips: add support for noncached_alloc() mips: mtmips: add support for MediaTek MT7621 SoC mips: mtmips: add two reference boards for mt7621 doc: mediatek: add documentation for mt7621 reference boards clk: mtmips: add clock driver for MediaTek MT7621 SoC reset: mtmips: add reset controller support for MediaTek MT7621 SoC pinctrl: mtmips: add support for MediaTek MT7621 SoC usb: xhci-mtk: add support for MediaTek MT7621 SoC phy: mtk-tphy: add support for MediaTek MT7621 SoC spi: add support for MediaTek MT7621 SoC gpio: add support for MediaTek MT7621 SoC watchdog: add support for MediaTek MT7621 SoC mmc: mediatek: add support for MediaTek MT7621 SoC net: mediatek: remap iobase address net: mediatek: use regmap api to modify ethsys registers net: mediatek: add support for MediaTek MT7621 SoC nand: raw: add support for MediaTek MT7621 SoC spl: allow using nand base without standard nand driver spl: spl_legacy: fix the use of SPL_COPY_PAYLOAD_ONLY spl: nand: support loading legacy image with payload compressed tools: mtk_image: add support for MT7621 NAND images MAINTAINERS: update maintainer for MediaTek MIPS platform MAINTAINERS |8 + arch/mips/cpu/u-boot-spl.lds |3 + arch/mips/dts/Makefile|2 + arch/mips/dts/mediatek,mt7621-nand-rfb.dts| 67 + arch/mips/dts/mediatek,mt7621-rfb.dts | 82 ++ arch/mips/dts/mt7621-u-boot.dtsi | 111 ++ arch/mips/dts/mt7621.dtsi | 349 + arch/mips/include/asm/cm.h| 67 + arch/mips/include/asm/mipsmtregs.h| 142 ++ arch/mips/include/asm/system.h| 20 + arch/mips/lib/cache.c | 43 + arch/mips/mach-mtmips/Kconfig | 49 +- arch/mips/mach-mtmips/Makefile|4 + arch/mips/mach-mtmips/cpu.c |2 +- arch/mips/mach-mtmips/mt7621/Kconfig | 115 ++ arch/mips/mach-mtmips/mt7621/Makefile | 14 + arch/mips/mach-mtmips/mt7621/init.c | 246 arch/mips/mach-mtmips/mt7621/mt7621.h | 229 arch/mips/mach-mtmips/mt7621/serial.c | 23 + arch/mips/mach-mtmips/mt7621/spl/Makefile |9 + arch/mips/mach-mtmips/mt7621/spl/cps.c| 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.c | 153 +++ arch/mips/mach-mtmips/mt7621/spl/dram.h | 39 + arch/mips/mach-mtmips/mt7621/spl/launch.c | 100 ++ arch/mips/mach-mtmips/mt7621/spl/launch.h | 52 + arch/mips/mach-mtmips/mt7621/spl/launch_ll.S | 339 + arch/mips/mach-mtmips/mt7621/spl/serial.c | 24 + arch/mips/mach-mtmips/mt7621/spl/spl.c| 95 ++ arch/mips/mach-mtmips/mt7621/spl/start.S | 226 arch/mips/mach-mtmips/mt7621/sram_init.S | 22 + arch/mips/mach-mtmips/mt7621/tpl/Makefile |4 + arch/mips/mach-mtmips/mt7621/tpl/start.S | 161 +++ arch/mips/mach-mtmips/mt7621/tpl/tpl.c| 144 ++ board/mediatek/mt7621/MAINTAINERS |8 + board/mediatek/mt7621/Makefile|3 + board/mediatek/mt7621/board.c |6 + common/spl/Kconfig|2 +- common/spl/spl_legacy.c | 21 +-
Re: [PATCH v6 00/25] Add support for MediaTek MT7621 SoC - v6
Hi Weijie, On 20.05.22 05:21, Weijie Gao wrote: This series will add support for MediaTek MT7621 SoC with two reference boards and related drivers. The MediaTek MT7621 is a network processor integrating a dual-core dual-threaded MIPS 1004Kc processor running at a normal frequency of 880MHz. This chip can be found in many wireless routers. This series add all basic drivers which are useful in u-boot, like usb, sdxc, ethernet, spi, nand and serial. Building the u-boot requires external binary blob which is described in doc/board/mediatek/mt7621.rst Thanks, Weijie I applied v6 to u-boot-mips/next for the upcoming merge window. I needed to add some fixups to make CI happy. Could you check if the changes are okay, especially the Kconfig migration of CONFIG_SYS_NAND_U_BOOT_OFFS? https://source.denx.de/u-boot/custodians/u-boot-mips/-/commits/next/ https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/12637 Thanks, Daniel
Re: [PATCH] Kconfig: hide options not intended for users in arch/Kconfig
On 18.05.22 17:22, Tom Rini wrote: On Wed, May 18, 2022 at 05:12:13PM +0200, Daniel Schwierzeck wrote: On 18.05.22 14:18, Tom Rini wrote: On Tue, May 17, 2022 at 10:53:53PM +0200, Daniel Schwierzeck wrote: Those options show up in menuconfig when selecting ARM or MIPS which is dangerous if a user accidently sets them. This also clutters up the menuconfig top-level screen. Because those options should only be set by SoC specific or board specific configs, make them invisible. Signed-off-by: Daniel Schwierzeck --- arch/Kconfig | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 12de8a1165..e3e28d0628 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -365,7 +365,7 @@ config SYS_DISABLE_DCACHE_OPS this functionality. config SYS_IMMR - hex "Address for the Internal Memory-Mapped Registers (IMMR) window" + hex depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A default 0xFF00 if MPC8xx default 0xF000 if ARCH_MPC8313 But now these aren't user selectable on the right platforms either. Maybe we need more menu organization, and so can have sub-menus depend on PPC, or whatever, and so things aren't cluttered on other architectures? my main concern was with SKIP_LOWLEVEL_INIT which definitely should not be selectable by the user. Maybe I was to overambitious with changing the SYS_IMMR option too, I could revert that part ;) I'd be agreeable to a patch that makes everyone that enables it today select it instead. I'll look into it. Would moving this to top-level Kconfig and the "General setup" menu be an option? BTW: SYS_IMMR seems to be specific for PPC. Maybe it could be moved to arch/powerpc/Kconfig? It's PowerPC or the 64bit ARM Layerscape platforms. There's I think only several imperfect places today for the options that are present in both due to the IP blocks / etc being updated by NXP for use in their current ARM HW. -- - Daniel
Re: [PATCH] Kconfig: hide options not intended for users in arch/Kconfig
On 18.05.22 14:18, Tom Rini wrote: On Tue, May 17, 2022 at 10:53:53PM +0200, Daniel Schwierzeck wrote: Those options show up in menuconfig when selecting ARM or MIPS which is dangerous if a user accidently sets them. This also clutters up the menuconfig top-level screen. Because those options should only be set by SoC specific or board specific configs, make them invisible. Signed-off-by: Daniel Schwierzeck --- arch/Kconfig | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 12de8a1165..e3e28d0628 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -365,7 +365,7 @@ config SYS_DISABLE_DCACHE_OPS this functionality. config SYS_IMMR - hex "Address for the Internal Memory-Mapped Registers (IMMR) window" + hex depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A default 0xFF00 if MPC8xx default 0xF000 if ARCH_MPC8313 But now these aren't user selectable on the right platforms either. Maybe we need more menu organization, and so can have sub-menus depend on PPC, or whatever, and so things aren't cluttered on other architectures? my main concern was with SKIP_LOWLEVEL_INIT which definitely should not be selectable by the user. Maybe I was to overambitious with changing the SYS_IMMR option too, I could revert that part ;) BTW: SYS_IMMR seems to be specific for PPC. Maybe it could be moved to arch/powerpc/Kconfig? -- - Daniel
Re: [PATCH v5 24/25] tools: mtk_image: add support for MT7621 NAND images
On 16.05.22 04:44, Weijie Gao wrote: The BootROM of MT7621 requires a image header for SPL to record its size and load address when booting from NAND. To create such an image, one can use the following command line: mkimage -T mtk_image -a 0x8020 -e 0x8020 -n "mt7621=1" -d u-boot-spl-ddr.bin u-boot-spl-ddr.img Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- tools/mtk_image.c | 182 ++ tools/mtk_image.h | 24 ++ 2 files changed, 206 insertions(+) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 23/25] spl: nand: support loading legacy image with payload compressed
On 16.05.22 04:44, Weijie Gao wrote: Add support to load legacy image with payload compressed. This redirects the boot flow for all legacy images. If the payload is not compresses, the s/compresses/compressed/ actual behavior will remain unchanged. Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- common/spl/spl_nand.c | 27 +++ 1 file changed, 27 insertions(+) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 22/25] spl: spl_legacy: fix the use of SPL_COPY_PAYLOAD_ONLY
On 16.05.22 04:44, Weijie Gao wrote: If the payload is compressed, SPL_COPY_PAYLOAD_ONLY should always be set since the payload will not be directly read to its load address. The payload will first be read to a temporary buffer, and then be decompressed to its load address, without image header. If the payload is not compressed, and SPL_COPY_PAYLOAD_ONLY is set, image header should be skipped on loading. Otherwise image header should also be read to its load address. Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- common/spl/spl_legacy.c | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 18/25] net: mediatek: use regmap api to modify ethsys registers
On 16.05.22 04:43, Weijie Gao wrote: The address returned by regmap_get_range() is not remapped. Directly r/w to this address is ok for ARM platforms since it's idential to the virtual address. But for MIPS platform only virtual address should be used for access. To solve this issue, the regmap api regmap_read/regmap_write should be used since they will remap address before accessing. Reviewed-by: Ramon Fried Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- drivers/net/mtk_eth.c | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 10/25] pinctrl: mtmips: add support for MediaTek MT7621 SoC
On 16.05.22 04:43, Weijie Gao wrote: This patch adds pinctrl support for MediaTek MT7621 SoC. The MT7621 SoC supports pinconf, but it is not the same as mt7628. Signed-off-by: Weijie Gao --- v5 changes: Remove the use of common.h v4 changes: none v3 changes: none v2 changes: none --- drivers/pinctrl/mtmips/Kconfig| 9 + drivers/pinctrl/mtmips/Makefile | 1 + drivers/pinctrl/mtmips/pinctrl-mt7621.c | 306 ++ .../pinctrl/mtmips/pinctrl-mtmips-common.c| 4 +- .../pinctrl/mtmips/pinctrl-mtmips-common.h| 12 + 5 files changed, 330 insertions(+), 2 deletions(-) create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7621.c Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 07/25] doc: mediatek: add documentation for mt7621 reference boards
On 16.05.22 04:42, Weijie Gao wrote: The MT7621 requires external binary blob being executed during u-boot's boot-up flow. It's necessary to provide a guide here for users to correctly build the u-boot. Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- doc/board/mediatek/mt7621.rst | 48 +++ 1 file changed, 48 insertions(+) create mode 100644 doc/board/mediatek/mt7621.rst Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 06/25] mips: mtmips: add two reference boards for mt7621
On 16.05.22 04:42, Weijie Gao wrote: The mt7621_rfb board supports integrated giga PHYs plus one external giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1 slots, SDXC and USB. The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it uses NAND flash and SDXC is not available. Reviewed-by: Stefan Roese Reviewed-by: Daniel Schwierzeck Signed-off-by: Weijie Gao --- v5 changes: Fix defconfig file names in MAINTAINERS Remove unused configs in defconfig files Move pinctrl default states to board dts files v4 changes: Modify defconfig files for booting from flash v3 changes: none v2 changes: Add config file for mt7621-rfb boards --- arch/mips/dts/Makefile | 2 + arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 + arch/mips/dts/mediatek,mt7621-rfb.dts | 82 + arch/mips/mach-mtmips/mt7621/Kconfig | 20 ++ board/mediatek/mt7621/MAINTAINERS | 8 +++ board/mediatek/mt7621/Makefile | 3 + board/mediatek/mt7621/board.c | 6 ++ configs/mt7621_nand_rfb_defconfig | 83 ++ configs/mt7621_rfb_defconfig | 82 + 9 files changed, 353 insertions(+) create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts create mode 100644 board/mediatek/mt7621/MAINTAINERS create mode 100644 board/mediatek/mt7621/Makefile create mode 100644 board/mediatek/mt7621/board.c create mode 100644 configs/mt7621_nand_rfb_defconfig create mode 100644 configs/mt7621_rfb_defconfig Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 05/25] mips: mtmips: add support for MediaTek MT7621 SoC
On 16.05.22 04:42, Weijie Gao wrote:
This patch adds support for MediaTek MT7621 SoC.
All files are dedicated for u-boot.
The default build target is u-boot-mt7621.bin.
The specification of this chip:
https://www.mediatek.com/products/homenetworking/mt7621
Signed-off-by: Weijie Gao
---
v5 changes:
Fix dram binary blob loading procedure
Adjust mt7621.dtsi, clkctrl moved under sysc, pinctrl default states removed
v4 changes:
Add full support for booting from flash (SPL/TPL support)
Boot all cores/VPEs
Use binman to generate final binary
Use binman to embed external binary blob
v3 changes:
Update clock name for mt7621.dtsi due to clk driver changed
v2 changes:
Add a kconfig for max supported ram size
Remove network configs from default config file
---
arch/mips/dts/mt7621-u-boot.dtsi | 111 ++
arch/mips/dts/mt7621.dtsi| 349 ++
arch/mips/mach-mtmips/Kconfig| 49 ++-
arch/mips/mach-mtmips/Makefile | 4 +
arch/mips/mach-mtmips/cpu.c | 2 +-
arch/mips/mach-mtmips/mt7621/Kconfig | 95 +
arch/mips/mach-mtmips/mt7621/Makefile| 14 +
arch/mips/mach-mtmips/mt7621/init.c | 229
arch/mips/mach-mtmips/mt7621/mt7621.h| 229
arch/mips/mach-mtmips/mt7621/serial.c| 23 ++
arch/mips/mach-mtmips/mt7621/spl/Makefile| 9 +
arch/mips/mach-mtmips/mt7621/spl/cps.c | 152
arch/mips/mach-mtmips/mt7621/spl/dram.c | 155
arch/mips/mach-mtmips/mt7621/spl/dram.h | 39 ++
arch/mips/mach-mtmips/mt7621/spl/launch.c| 100 ++
arch/mips/mach-mtmips/mt7621/spl/launch.h| 52 +++
arch/mips/mach-mtmips/mt7621/spl/launch_ll.S | 357 +++
arch/mips/mach-mtmips/mt7621/spl/serial.c| 24 ++
arch/mips/mach-mtmips/mt7621/spl/spl.c | 95 +
arch/mips/mach-mtmips/mt7621/spl/start.S | 226
arch/mips/mach-mtmips/mt7621/sram_init.S | 22 ++
arch/mips/mach-mtmips/mt7621/tpl/Makefile| 4 +
arch/mips/mach-mtmips/mt7621/tpl/start.S | 161 +
arch/mips/mach-mtmips/mt7621/tpl/tpl.c | 146
include/configs/mt7621.h | 67
25 files changed, 2708 insertions(+), 6 deletions(-)
create mode 100644 arch/mips/dts/mt7621-u-boot.dtsi
create mode 100644 arch/mips/dts/mt7621.dtsi
create mode 100644 arch/mips/mach-mtmips/mt7621/Kconfig
create mode 100644 arch/mips/mach-mtmips/mt7621/Makefile
create mode 100644 arch/mips/mach-mtmips/mt7621/init.c
create mode 100644 arch/mips/mach-mtmips/mt7621/mt7621.h
create mode 100644 arch/mips/mach-mtmips/mt7621/serial.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/Makefile
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/cps.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/dram.h
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch.h
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/launch_ll.S
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/serial.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/spl.c
create mode 100644 arch/mips/mach-mtmips/mt7621/spl/start.S
create mode 100644 arch/mips/mach-mtmips/mt7621/sram_init.S
create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/Makefile
create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/start.S
create mode 100644 arch/mips/mach-mtmips/mt7621/tpl/tpl.c
create mode 100644 include/configs/mt7621.h
Reviewed-by: Daniel Schwierzeck
some nits below
diff --git a/arch/mips/dts/mt7621-u-boot.dtsi b/arch/mips/dts/mt7621-u-boot.dtsi
new file mode 100644
index 00..c5a8aa357f
--- /dev/null
+++ b/arch/mips/dts/mt7621-u-boot.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 MediaTek Inc. All rights reserved.
+ *
+ * Author: Weijie Gao
+ */
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+};
+
+ {
+ u-boot-spl-ddr {
+ align = <4>;
+ align-size = <4>;
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+
+ u-boot-spl {
+ align-end = <4>;
+ filename = "u-boot-spl.bin";
+ };
+
+ stage_bin {
+ filename = "mt7621_stage_sram.bin";
+ type = "blob-ext";
+ };
+
[PATCH] Kconfig: hide options not intended for users in arch/Kconfig
Those options show up in menuconfig when selecting ARM or MIPS which is dangerous if a user accidently sets them. This also clutters up the menuconfig top-level screen. Because those options should only be set by SoC specific or board specific configs, make them invisible. Signed-off-by: Daniel Schwierzeck --- arch/Kconfig | 14 +++--- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 12de8a1165..e3e28d0628 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -365,7 +365,7 @@ config SYS_DISABLE_DCACHE_OPS this functionality. config SYS_IMMR - hex "Address for the Internal Memory-Mapped Registers (IMMR) window" + hex depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A default 0xFF00 if MPC8xx default 0xF000 if ARCH_MPC8313 @@ -377,7 +377,7 @@ config SYS_IMMR to configure the features of many Freescale / NXP SoCs. config SKIP_LOWLEVEL_INIT - bool "Skip the calls to certain low level initialization functions" + bool depends on ARM || MIPS || RISCV help If enabled, then certain low level initializations (like setting up @@ -388,7 +388,7 @@ config SKIP_LOWLEVEL_INIT debugger which performs these initializations itself. config SPL_SKIP_LOWLEVEL_INIT - bool "Skip the calls to certain low level initialization functions" + bool depends on SPL && (ARM || MIPS || RISCV) help If enabled, then certain low level initializations (like setting up @@ -399,7 +399,7 @@ config SPL_SKIP_LOWLEVEL_INIT debugger which performs these initializations itself. config TPL_SKIP_LOWLEVEL_INIT - bool "Skip the calls to certain low level initialization functions" + bool depends on SPL && ARM help If enabled, then certain low level initializations (like setting up @@ -410,7 +410,7 @@ config TPL_SKIP_LOWLEVEL_INIT debugger which performs these initializations itself. config SKIP_LOWLEVEL_INIT_ONLY - bool "Skip the call to lowlevel_init during early boot ONLY" + bool depends on ARM help This allows just the call to lowlevel_init() to be skipped. The @@ -418,7 +418,7 @@ config SKIP_LOWLEVEL_INIT_ONLY performed. config SPL_SKIP_LOWLEVEL_INIT_ONLY - bool "Skip the call to lowlevel_init during early boot ONLY" + bool depends on SPL && ARM help This allows just the call to lowlevel_init() to be skipped. The @@ -426,7 +426,7 @@ config SPL_SKIP_LOWLEVEL_INIT_ONLY performed. config TPL_SKIP_LOWLEVEL_INIT_ONLY - bool "Skip the call to lowlevel_init during early boot ONLY" + bool depends on TPL && ARM help This allows just the call to lowlevel_init() to be skipped. The -- 2.36.1
Re: [PATCH v5 04/25] mips: add support for noncached_alloc()
On 16.05.22 04:42, Weijie Gao wrote: This patch adds support for noncached_alloc() which was only supported by ARM platform. Unlike the ARM platform, MMU is not used in u-boot for MIPS. Instead, KSEG is provided to access uncached memory. So most code of this patch is copied from cache.c of ARM platform, with only two differences: 1. MMU is untouched in noncached_set_region() 2. Address returned by noncached_alloc() is converted using KSEG1ADDR() Signed-off-by: Weijie Gao --- v5 changes: change KSEG1ADDR to CKSEG1ADDR v4 changes: new --- arch/mips/include/asm/system.h | 20 arch/mips/lib/cache.c | 43 ++ 2 files changed, 63 insertions(+) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 03/25] mips: add __image_copy_len for SPL linker script
On 16.05.22 04:42, Weijie Gao wrote: This patch adds __image_copy_len needed by TPL of MT7621 SoC. The __image_copy_len represents the binary blob size of both SPL/TPL binaries. To achieve this, __text_start/end are added for calculation. Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- arch/mips/cpu/u-boot-spl.lds | 3 +++ 1 file changed, 3 insertions(+) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 02/25] mips: add more definitions for asm/cm.h
On 16.05.22 04:42, Weijie Gao wrote: This patch add more definitions needed for MT7621 initialization. MT7621 needs to initialize GIC/CPC and other related parts. Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- arch/mips/include/asm/cm.h | 67 ++ 1 file changed, 67 insertions(+) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v5 01/25] mips: add asm/mipsmtregs.h for MIPS multi-threading
On 16.05.22 04:42, Weijie Gao wrote: To be compatible with old u-boot used by lots of MT7621 devices, the u-boot needs to boot-up MT7621's all cores, and all VPES of each core. This patch adds asm/mipsmtregs.h from linux kernel which is need for boot-up VPEs. Signed-off-by: Weijie Gao --- v5 changes: none v4 changes: new --- arch/mips/include/asm/mipsmtregs.h | 142 + 1 file changed, 142 insertions(+) create mode 100644 arch/mips/include/asm/mipsmtregs.h Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH v2 00/52] mips: octeon: Add ethernet support
Hi Stefan, Am 02.05.22 um 18:00 schrieb Stefan Roese: Hi Daniel, On 07.04.22 09:11, Stefan Roese wrote: This patchset adds the networking files and drivers including device helper headers and C files. Please excuse the massive amount of files in this patch series. Also the sometimes huge files (mostly headers with register definitions) that I needed to include. The infrastructure code with all the headers is ported mistly without any intended functional changes from the 2013 Cavium / Marvell U-Boot version. It has undergone many hours of extensive code cleanup and reformatting. Some of it done by using tools (checkpatch, Lindent, clang format etc) and also some of it done manually, as I couldn't find some tools that could do the needed work in a reliable and functional way. The result is that checkpatch now only throws a "few" warnings that are left. Some of those can't be removed without an even more extensive cleanup / rewrite of the code, like the addition of typedefs. The added header, helper and infrastructure files in the first part of the patch-series (patches 1-43) are the foundation, that is used by the main Octeon U-Boot ethernet driver (patch 50/52). Patches 47-49 add the DT nodes and properties to the corresponding dtsi / dts files. Patches 51 & 52 finally enable the ethernet support both MIPS Octeon boards, EBB7304 & NIC23. All this is tested on the 2 Cavium / Marvell MIPS Octeon boards: EBB7304 & NIC23 This patchset including the small Marvell PHY patches is available in this gitlab branch: https://source.denx.de/u-boot/custodians/u-boot-marvell/-/tree/mips-octeon-ethernet-v2-2022-04-07 Changes in v2: - As suggested by Daniel, remove all unreferenced functions from the source code by manually inspecting u-boot.map [1] - Rebased on latest TOT [1] Here the diffstat comarison between v1 and v2: v1: 77 files changed, 42315 insertions(+), 586 deletions(-) v2: 78 files changed, 33672 insertions(+), 2524 deletions(-) Thanks, Stefan Daniel, do you have any comments on this patchset? Tom has assigned it to me in patchwork and I would really like to get it merged into mainline, if possible. So if you don't have any obejctions, then I would pull it via the Marvell tree soon. for the parts that I can reasonably review, I don't have any objections. I'd be happy if you pull it yourself as I'm currently really busy ;) -- - Daniel
Re: [PATCH v3] mips: dts: add initial support for ls1c300 SoC
sorry for the late response but I was on vacation ;) Am Donnerstag, dem 21.04.2022 um 20:31 -0400 schrieb Sean Anderson: > On 4/18/22 4:45 PM, Du Huanpeng wrote: > > Loongson 1C is a cost-effective SOC chip for industrial control and > > the Internet of Things. The Loongson 1C includes a floating-point > > processing unit, supports multiple types of memory, and supports > > high-capacity MLC NAND Flash. Loongson 1C provides developers with > > a > > wealth of peripheral interfaces and on-chip modules, including > > Camera > > controller, USB OTG and USB HOST interfaces, AC97/I2S controller, > > LCD > > controller, SPI interface, UART interface, etc., providing > > sufficient > > computing power and multi-application connectivity. > > > > Some highlights of this SoC are: > > - Single core LS232, MIPS32 instruction set compatible, main > > frequency > > 300MHZ > > - 16KB data cache and 16KB instruction cache > > - 64 bit float unit, hardware division > > - 8/16 bit SDRAM controller, 45 ~ 133MHz > > - 8/16 bit SRAM, NAND > > - I2S/AC97, LCD, MAC, USB, OTG, SPI, I2C, PWM, CAN, SDIO, ADC > > - 12 UARTs > > > > See Technical Reference Manual for details: > > https://www.loongson.cn/ > > > > introduce base support for the ls1c300 SoC. > > - debug UART2 > > - serial console > > - clock > > - watchdog > > - sysreset > > - many uarts > > > > Signed-off-by: Du Huanpeng > > --- > > Changelog for v3: > > - change cpu clock id from CLK_CPU to CLK_CPU_THROT > > - migrate all APB dev's clock id to CLK_APB > > - remove uarts' property to use default value <0> > > - move /clocks/acc node to /soc/acc > > - call clk_request() before use a clk > > - make get_tbclk() return 1/2 clock of cpu > > - disable debug_uart by default > > - add ops for cpu_throt_factor clk > > - declare MSEC_PER_SEC for converting between sec and msec > > - return a error code when the wdt clock is out of range > > - minor format and codingstyle fixes > > - rebase to [9859465bfe838bc8264d45e1a1bed847bba74bad] > > > > Changelog for v2: > > 1. dtsi: > > add status disabled for uart0 ~ uart11 > > remove bootargs from chosen > > make serial0 alias for uart2 > > oscillator remove @0 unit-address > > change uart2 address to kuseg > > > > 2. cleanup Kconfig and update defconfig > > - make these options configurable, disabled by default: > > CMD_DM > > DM_ETH > > DM_GPIO > > DM_SPI > > DM_SPI_FLASH > > DM_RESET > > PINCONF > > PINCTRL > > PINMUX > > RESET_LSMIPS > > - make these options configurable, enabled by default: > > CLK > > DISPLAY_CPUINFO > > SYSRESET > > ROM_EXCEPTION_VECTORS > > - disabled: > > CONFIG_ENV_IS_IN_SPI_FLASH > > > > 3. fix codingstyle drivers/watchdog/lsmips-wdt.c > > - priv->base + offset > > - add comment for default clock value > > > > 4. remove address base definition header > > - remove arch/mips/mach-lsmips/ls1c300/ls1c300.h > > - clean up files uses this header > > > > 5. spl and debug uart > > - add comment for spl & debug uart pinmuxing > > - cleanup unused registers base header > > > > 6. dtsi > > - add "loongson,ls1c300-uart" to all uart node > > > > 7. board dts > > - add memory node to board dts, start at 0x8000, size 64MB > > > > 8. Kconfig > > - make ROM_EXCEPTION_VECTORS user configureable > > - enable ROM_EXCEPTION_VECTORS in defconfig > > > > 9. > > - seperate sdram_init to sdram_init.S > > - add macro helpers to do sdram, pll lowlevel init > > > > 10. dtsi > > - move clock nodes to /clocks/xxx > > > > 11. > > - define CONFIG_SKIP_LOWLEVEL_INIT to 1 > > > > 12. > > - remove option PINCTRL_LS1C300 from Kconfig > > > > 13. > > - dram_init, use get_ram_size() to detect ram size. > > > > 14. clk driver > > - create custom clock ops for PLL > > - remove debug code > > > > 15. > > - rebase to 59bffec43a657598b194b9eb30dc01eec06078c7 > > - remove CONFIG_SYS_MONITOR_BASE from include/configs/ > > > > > commit e4d741f8abc4a92426d3a826f99390c3abe02d61 > > > Author: Tom Rini > > > Date: Thu Mar 24 17:18:05 2022 -0400 > > > > > > Convert CONFIG_SYS_MONITOR_BASE to Kconfig > > > > MAINTAINERS | 13 ++ > > arch/mips/Kconfig | 11 ++ > > arch/mips/Makefile| 1 + > > arch/mips/dts/Makefile| 1 + > > arch/mips/dts/loongson32-ls1c300b.dtsi| 141 > > ++ > > arch/mips/dts/ls1c300-eval.dts| 31 +++ > > arch/mips/mach-lsmips/Kconfig | 76 > > arch/mips/mach-lsmips/Makefile| 6 + > > arch/mips/mach-lsmips/cpu.c | 19 ++ > > arch/mips/mach-lsmips/include/mach/serial.h | 16 ++ > > arch/mips/mach-lsmips/ls1c300/Makefile| 7 + > > arch/mips/mach-lsmips/ls1c300/gpio.c | 66 +++ > > arch/mips/mach-lsmips/ls1c300/init.c
Re: [PATCH 00/52] mips: octeon: Add ethernet support
Am Mittwoch, dem 30.03.2022 um 12:06 +0200 schrieb Stefan Roese: > This patchset adds the networking files and drivers including device > helper headers and C files. Please excuse the massive amount of files > in this patch series. Also the sometimes huge files (mostly headers > with register definitions) that I needed to include. > > The infrastructure code with all the headers is ported mistly without > any intended functional changes from the 2013 Cavium / Marvell U-Boot > version. It has undergone many hours of extensive code cleanup and > reformatting. Some of it done by using tools (checkpatch, Lindent, > clang > format etc) and also some of it done manually, as I couldn't find > some > tools that could do the needed work in a reliable and functional way. > The result is that checkpatch now only throws a "few" warnings that > are > left. Some of those can't be removed without an even more extensive > cleanup / rewrite of the code, like the addition of typedefs. > > The added header, helper and infrastructure files in the first part > of > the patch-series (patches 1-43) are the foundation, that is used by > the > main Octeon U-Boot ethernet driver (patch 50/52). Patches 47-49 add > the > DT nodes and properties to the corresponding dtsi / dts files. > Patches > 51 & 52 finally enable the ethernet support both MIPS Octeon boards, > EBB7304 & NIC23. > > All this is tested on the 2 Cavium / Marvell MIPS Octeon boards: > EBB7304 & NIC23 > > This patchset including the small Marvell PHY patches is available in > this gitlab branch: > > https://source.denx.de/u-boot/custodians/u-boot-marvell/-/tree/mips-octeon-ethernet-v1-2022-03-30 > > Thanks, > Stefan > > Aaron Williams (40): > mips: octeon: Add misc cvmx-* header files > mips: octeon: Add cvmx-ilk-defs.h header file > mips: octeon: Add cvmx-iob-defs.h header file > mips: octeon: Add cvmx-lbk-defs.h header file > mips: octeon: Add cvmx-npei-defs.h header file > mips: octeon: Add cvmx-pcsxx-defs.h header file > mips: octeon: Add cvmx-xcv-defs.h header file > mips: octeon: Add cvmx-helper-agl.c > mips: octeon: Add cvmx-helper-bgx.c > mips: octeon: Add cvmx-helper-board.c > mips: octeon: Add cvmx-helper-fpa.c > mips: octeon: Add cvmx-helper-igl.c > mips: octeon: Add cvmx-helper-ipd.c > mips: octeon: Add cvmx-helper-loop.c > mips: octeon: Add cvmx-helper-npi.c > mips: octeon: Add cvmx-helper-pki.c > mips: octeon: Add cvmx-helper-pko.c > mips: octeon: Add cvmx-helper-pko3.c > mips: octeon: Add cvmx-helper-rgmii.c > mips: octeon: Add cvmx-helper-sgmii.c > mips: octeon: Add cvmx-helper-sfp.c > mips: octeon: Add cvmx-helper-xaui.c > mips: octeon: Add cvmx-agl.c > mips: octeon: Add cvmx-cmd-queue.c > mips: octeon: Add cvmx-fau-compat.c > mips: octeon: Add cvmx-fpa.c > mips: octeon: Add cvmx-fpa-resource.c > mips: octeon: Add cvmx-global-resource.c > mips: octeon: Add cvmx-ilk.c > mips: octeon: Add cvmx-ipd.c > mips: octeon: Add cvmx-pki.c > mips: octeon: Add cvmx-pki-resources.c > mips: octeon: Add cvmx-pko.c > mips: octeon: Add cvmx-pko3.c > mips: octeon: Add cvmx-pko3-queue.c > mips: octeon: Add cvmx-pko3-compat.c > mips: octeon: Add cvmx-pko3-resources.c > mips: octeon: Add cvmx-pko-internal-ports-range.c > mips: octeon: Add cvmx-qlm-tables.c > mips: octeon: Add cvmx-range.c are those 10 millions helper functions really used by the ethernet driver? Do you really need features like SFP modules in U-Boot? Maybe it helps to have a look at u-boot.map to see which functions are unused and are discarded by the linker. Those functions could be actually removed to reduce the LoC count ;) > > Stefan Roese (12): > mips: octeon: Misc changes to existing headers for upcoming eth > support > mips: octeon: Misc changes to existing C files for upcoming eth > support > mips: octeon: Makefile: Enable building of the newly added C files > mips: octeon: cpu.c: Move bootmem init to arch_early_init_r() > mips: octeon: cpu.c: Implement configure_lmtdma_window() > mips: octeon: octeon_common.h: Move init SP because of increased > image > size > mips: octeon: mrvl,cn73xx.dtsi: Add ethernet (BGX) and SMI DT nodes > mips: octeon: mrvl,octeon-ebb7304.dts: Add ethernet DT support > mips: octeon: mrvl,octeon-nic23.dts: Add ethernet DT support > net: Add ethernet support for MIPS Octeon > mips: octeon: ebb7304: Enable ethernet support > mips: octeon: nic23: Enable ethernet support > > arch/mips/Kconfig |1 + > arch/mips/dts/mrvl,cn73xx.dtsi| 35 + > arch/mips/dts/mrvl,octeon-ebb7304.dts | 45 + > arch/mips/dts/mrvl,octeon-nic23.dts | 238 ++ > arch/mips/mach-octeon/Makefile| 35 +- > arch/mips/mach-octeon/cpu.c | 47 +- > arch/mips/mach-octeon/cvmx-agl.c | 216 + > arch/mips/mach-octeon/cvmx-bootmem.c |3 +- >
Re: [RFC PATCH] mips: dts: add initial support for ls1c300 SoC
Am Mittwoch, dem 30.03.2022 um 03:30 +0800 schrieb Du Huanpeng: > Loongson 1C is a cost-effective SOC chip for industrial control and > the Internet of Things. The Loongson 1C includes a floating-point > processing unit, supports multiple types of memory, and supports > high-capacity MLC NAND Flash. Loongson 1C provides developers with a > wealth of peripheral interfaces and on-chip modules, including Camera > controller, USB OTG and USB HOST interfaces, AC97/I2S controller, LCD > controller, SPI interface, UART interface, etc., providing sufficient > computing power and multi-application connectivity. > > Some highlights of this SoC are: > - Single core LS232, MIPS32 instruction set compatible, main > frequency > 300MHZ > - 16KB data cache and 16KB instruction cache > - 64 bit float unit, hardware division > - 8/16 bit SDRAM controller, 45 ~ 133MHz > - 8/16 bit SRAM, NAND > - I2S/AC97, LCD, MAC, USB, OTG, SPI, I2C, PWM, CAN, SDIO, ADC > - 12 UARTs > > See Techinical Reference Manual for details: https://www.loongson.cn/ > > introduce base support for the ls1c300 SoC. > - debug UART2 > - serial console > - clock > - watchdog > - sysreset > - many uarts > > Signed-off-by: Du Huanpeng Sean already addressed most points, so only just some additional comments below. > --- > arch/mips/Kconfig | 25 +++ > arch/mips/Makefile| 1 + > arch/mips/dts/Makefile| 1 + > arch/mips/dts/loongson32-ls1c300b.dtsi| 138 > + > arch/mips/dts/ls1c300-eval.dts| 27 > arch/mips/mach-lsmips/Kconfig | 77 ++ > arch/mips/mach-lsmips/Makefile| 6 + > arch/mips/mach-lsmips/cpu.c | 24 +++ > arch/mips/mach-lsmips/include/mach/serial.h | 16 ++ > arch/mips/mach-lsmips/ls1c300/Makefile| 6 + > arch/mips/mach-lsmips/ls1c300/gpio.c | 60 > arch/mips/mach-lsmips/ls1c300/init.c | 60 > arch/mips/mach-lsmips/ls1c300/lowlevel_init.S | 123 +++ > arch/mips/mach-lsmips/ls1c300/ls1c300.h | 52 +++ > arch/mips/mach-lsmips/ls1c300/serial.c| 112 ++ > arch/mips/mach-lsmips/spl.c | 47 ++ you should use mach-loongson. If you copied the naming from mtmips, then don't ;) mtmips only exists because mediatek was already used for the ARM specific SoC's and we needed some different Kconfig symbols for the MIPS SoC's. > board/loongson/ls1c300-eval/Kconfig | 12 ++ > board/loongson/ls1c300-eval/MAINTAINERS | 7 + > board/loongson/ls1c300-eval/Makefile | 3 + > board/loongson/ls1c300-eval/board.c | 20 +++ > configs/ls1c300_defconfig | 65 > drivers/clk/Makefile | 1 + > drivers/clk/lsmips/Makefile | 3 + > drivers/clk/lsmips/clk-ls1c300.c | 145 > ++ > drivers/watchdog/Kconfig | 8 + > drivers/watchdog/Makefile | 1 + > drivers/watchdog/lsmips_wdt.c | 126 +++ > include/configs/ls1c300.h | 61 > include/dt-bindings/clock/ls1c300-clk.h | 48 ++ > 29 files changed, 1275 insertions(+) > create mode 100644 arch/mips/dts/loongson32-ls1c300b.dtsi > create mode 100644 arch/mips/dts/ls1c300-eval.dts > create mode 100644 arch/mips/mach-lsmips/Kconfig > create mode 100644 arch/mips/mach-lsmips/Makefile > create mode 100644 arch/mips/mach-lsmips/cpu.c > create mode 100644 arch/mips/mach-lsmips/include/mach/serial.h > create mode 100644 arch/mips/mach-lsmips/ls1c300/Makefile > create mode 100644 arch/mips/mach-lsmips/ls1c300/gpio.c > create mode 100644 arch/mips/mach-lsmips/ls1c300/init.c > create mode 100644 arch/mips/mach-lsmips/ls1c300/lowlevel_init.S > create mode 100644 arch/mips/mach-lsmips/ls1c300/ls1c300.h > create mode 100644 arch/mips/mach-lsmips/ls1c300/serial.c > create mode 100644 arch/mips/mach-lsmips/spl.c > create mode 100644 board/loongson/ls1c300-eval/Kconfig > create mode 100644 board/loongson/ls1c300-eval/MAINTAINERS > create mode 100644 board/loongson/ls1c300-eval/Makefile > create mode 100644 board/loongson/ls1c300-eval/board.c > create mode 100644 configs/ls1c300_defconfig > create mode 100644 drivers/clk/lsmips/Makefile > create mode 100644 drivers/clk/lsmips/clk-ls1c300.c > create mode 100644 drivers/watchdog/lsmips_wdt.c > create mode 100644 include/configs/ls1c300.h > create mode 100644 include/dt-bindings/clock/ls1c300-clk.h > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 28234aa0bb..d95868ef4b 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -93,6 +93,30 @@ config ARCH_MTMIPS > select SUPPORTS_LITTLE_ENDIAN > select SUPPORT_SPL > > +config ARCH_LSMIPS > + bool "Support Loongson MIPS platforms" > +
Re: [PATCH v4 02/13] mips: Avoid using config_enabled() directly
Am Sonntag, dem 16.01.2022 um 13:19 -0700 schrieb Simon Glass:
> Use IS_ENABLED() instead, which is the correct macro for checking a
> CONFIG
> option.
>
> Signed-off-by: Simon Glass
Reviewed-by: Daniel Schwierzeck
> ---
>
> (no changes since v1)
>
> arch/mips/lib/cache.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
> index 51a8f433475..ec652f0fba8 100644
> --- a/arch/mips/lib/cache.c
> +++ b/arch/mips/lib/cache.c
> @@ -38,7 +38,7 @@ static void probe_l2(void)
> l2c = read_c0_config5() & MIPS_CONF5_L2C;
> }
>
> - if (l2c && config_enabled(CONFIG_MIPS_CM)) {
> + if (l2c && IS_ENABLED(CONFIG_MIPS_CM)) {
> gd->arch.l2_line_size = mips_cm_l2_line_size();
> } else if (l2c) {
> /* We don't know how to retrieve L2 config on this
> system */
--
- Daniel
Re: [PATCH 02/14] mips: mtmips: add two reference boards for mt7621
Am Donnerstag, dem 04.11.2021 um 17:48 +0800 schrieb Weijie Gao: > The mt7621_rfb board supports integrated giga PHYs plus one external > giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e > x1 > slots, SDXC and USB. > > The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but > it > uses NAND flash and SDXC is not available. > > Signed-off-by: Weijie Gao > --- > arch/mips/dts/Makefile | 2 + > arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 52 +++ > arch/mips/dts/mediatek,mt7621-rfb.dts | 68 > arch/mips/mach-mtmips/mt7621/Kconfig | 20 ++ > board/mediatek/mt7621/MAINTAINERS | 8 +++ > board/mediatek/mt7621/Makefile | 3 + > board/mediatek/mt7621/board.c | 6 ++ > configs/mt7621_nand_rfb_ramboot_defconfig | 71 > + > configs/mt7621_rfb_ramboot_defconfig | 74 > ++ > 9 files changed, 304 insertions(+) > create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts > create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts > create mode 100644 board/mediatek/mt7621/MAINTAINERS > create mode 100644 board/mediatek/mt7621/Makefile > create mode 100644 board/mediatek/mt7621/board.c > create mode 100644 configs/mt7621_nand_rfb_ramboot_defconfig > create mode 100644 configs/mt7621_rfb_ramboot_defconfig > > Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH 01/14] mips: mtmips: add support for MediaTek MT7621 SoC
Am Donnerstag, dem 04.11.2021 um 17:48 +0800 schrieb Weijie Gao:
> This patch adds support for MediaTek MT7621 SoC.
> All files are dedicated for u-boot.
>
> Currently only ramboot is supported.
> The default build target is u-boot-lzma.img.
> This file can be booted using bootm command, or be used as a payload
> of the
> SDK preloader of MT7621.
>
> The specification of this chip:
> https://www.mediatek.com/products/homenetworking/mt7621
>
> Signed-off-by: Weijie Gao
> ---
> arch/mips/dts/mt7621.dtsi | 372
> ++
> arch/mips/mach-mtmips/Kconfig | 29 +-
> arch/mips/mach-mtmips/Makefile| 5 +
> arch/mips/mach-mtmips/cpu.c | 4 +
> arch/mips/mach-mtmips/mt7621/Kconfig | 23 ++
> arch/mips/mach-mtmips/mt7621/Makefile | 5 +
> arch/mips/mach-mtmips/mt7621/compat.c | 21 ++
> arch/mips/mach-mtmips/mt7621/init.c | 156 +++
> arch/mips/mach-mtmips/mt7621/mt7621.h | 204 ++
> arch/mips/mach-mtmips/mt7621/serial.c | 23 ++
> include/configs/mt7621.h | 41 +++
> 11 files changed, 879 insertions(+), 4 deletions(-)
> create mode 100644 arch/mips/dts/mt7621.dtsi
> create mode 100644 arch/mips/mach-mtmips/mt7621/Kconfig
> create mode 100644 arch/mips/mach-mtmips/mt7621/Makefile
> create mode 100644 arch/mips/mach-mtmips/mt7621/compat.c
> create mode 100644 arch/mips/mach-mtmips/mt7621/init.c
> create mode 100644 arch/mips/mach-mtmips/mt7621/mt7621.h
> create mode 100644 arch/mips/mach-mtmips/mt7621/serial.c
> create mode 100644 include/configs/mt7621.h
>
> diff --git a/arch/mips/dts/mt7621.dtsi b/arch/mips/dts/mt7621.dtsi
> new file mode 100644
> index 00..c09350b370
> --- /dev/null
> +++ b/arch/mips/dts/mt7621.dtsi
> @@ -0,0 +1,372 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 MediaTek Inc. All rights reserved.
> + *
> + * Author: Weijie Gao
> + */
> +
> +#include
> +#include
> +#include
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "mediatek,mt7621-soc";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + device_type = "cpu";
> + compatible = "mips,mips1004Kc";
> + reg = <0>;
> + };
> +
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "mips,mips1004Kc";
> + reg = <0>;
> + };
> + };
> +
> + clk48m: clk48m@0 {
> + compatible = "fixed-clock";
> +
> + clock-frequency = <4800>;
> +
> + #clock-cells = <0>;
> + };
> +
> + clk50m: clk50m@0 {
> + compatible = "fixed-clock";
> +
> + clock-frequency = <5000>;
> +
> + #clock-cells = <0>;
> + };
> +
> + sysc: sysc@1e00 {
> + compatible = "mediatek,mt7621-sysc", "syscon";
> + reg = <0x1e00 0x100>;
> + };
> +
> + clkctrl: clkctrl@1e30 {
> + compatible = "mediatek,mt7621-clk";
> + mediatek,sysc = <>;
> + mediatek,memc = <>;
> +
> + #clock-cells = <1>;
> + u-boot,dm-pre-reloc;
> + };
> +
> + rstctrl: rstctrl@1e34 {
> + compatible = "mediatek,mtmips-reset";
> + reg = <0x1e34 0x4>;
> + #reset-cells = <1>;
> + };
> +
> + reboot: resetctl-reboot {
> + compatible = "resetctl-reboot";
> +
> + resets = < RST_SYS>;
> + reset-names = "sysreset";
> + };
> +
> + memc: memc@1e005000 {
> + compatible = "mediatek,mt7621-memc", "syscon";
> + reg = <0x1e005000 0x1000>;
> + };
> +
> + pinctrl: pinctrl@1e60 {
> + compatible = "mediatek,mt7621-pinctrl";
> + reg = <0x1e48 0x30>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <_default>;
> +
> + state_default: pin_state {
> + uart1 {
> + groups = "uart1";
> + function = "uart";
> + };
> +
> + gpios {
> + groups = "i2c", "uart3", "pcie reset";
> + function = "gpio";
> + };
> +
> + jtag {
> + groups = "jtag";
> + function = "jtag";
> + };
> +
> + wdt {
> + groups = "wdt";
> + function = "wdt rst";
> + };
> + };
> +
> + uart1_pins: uart1_pins {
> + groups = "uart1";
> + function = "uart";
> + };
> +
> + uart2_pins: uart2_pins {
> +
Re: [PATCH 03/12] lmb: Add generic arch_lmb_reserve_generic()
Am Freitag, dem 10.09.2021 um 22:47 +0200 schrieb Marek Vasut:
> The arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve()
> implementations
> are all mostly the same, except for a couple of details. Implement a
> generic arch_lmb_reserve_generic() function which can be parametrized
> enough to cater for those differences between architectures. This can
> also be parametrized enough so it can handle cases where U-Boot is
> not
> relocated to the end of DRAM e.g. because there is some other
> reserved
> memory past U-Boot (e.g. unmovable firmware for coprocessor), it is
> not
> relocated at all, and other such use cases.
>
> Signed-off-by: Marek Vasut
> Cc: Alexey Brodkin
> Cc: Angelo Dureghello
> Cc: Daniel Schwierzeck
> Cc: Eugeniy Paltsev
> Cc: Hai Pham
> Cc: Michal Simek
> Cc: Simon Goldschmidt
> Cc: Tom Rini
> Cc: Wolfgang Denk
> ---
> V2: Reword code comment
> ---
> include/lmb.h | 1 +
> lib/lmb.c | 35 +++
> 2 files changed, 36 insertions(+)
>
> diff --git a/include/lmb.h b/include/lmb.h
> index 3c4afdf9f0..1984291132 100644
> --- a/include/lmb.h
> +++ b/include/lmb.h
> @@ -122,6 +122,7 @@ lmb_size_bytes(struct lmb_region *type, unsigned
> long region_nr)
>
> void board_lmb_reserve(struct lmb *lmb);
> void arch_lmb_reserve(struct lmb *lmb);
> +void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end,
> ulong align);
>
> /* Low level functions */
>
> diff --git a/lib/lmb.c b/lib/lmb.c
> index 7bd1255f7a..793647724c 100644
> --- a/lib/lmb.c
> +++ b/lib/lmb.c
> @@ -12,6 +12,10 @@
> #include
> #include
>
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> #define LMB_ALLOC_ANYWHERE 0
>
> static void lmb_dump_region(struct lmb_region *rgn, char *name)
> @@ -113,6 +117,37 @@ void lmb_init(struct lmb *lmb)
> lmb->reserved.cnt = 0;
> }
>
> +void arch_lmb_reserve_generic(struct lmb *lmb, ulong sp, ulong end,
> ulong align)
> +{
> + ulong bank_end;
> + int bank;
> +
> + /*
> + * Reserve memory from aligned address below the bottom of U-
> Boot stack
> + * until end of U-Boot area using LMB to prevent U-Boot from
> overwriting
> + * that memory.
> + */
> + debug("## Current stack ends at 0x%08lx ", sp);
> +
> + /* adjust sp by 4K to be safe */
nit: comment doesn't fit anymore
> + sp -= align;
> + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> + if (!gd->bd->bi_dram[bank].size ||
> + sp < gd->bd->bi_dram[bank].start)
> + continue;
> + /* Watch out for RAM at end of address space! */
> + bank_end = gd->bd->bi_dram[bank].start +
> + gd->bd->bi_dram[bank].size - 1;
> + if (sp > bank_end)
> + continue;
> + if (bank_end > end)
> + bank_end = end - 1;
isn't that all already taken care of when initializing gd->ram_top as
well as gd->relocaddr and gd->start_addr_sp (based on gd->ram_top)? So
gd->ram_top is already guaranteed to be less or equal some DRAM bank
end address. AFAIK arch_lmb_reserve() should just protect the U-Boot
area from gd->start_addr_sp up to gd->ram_top as well as the stack area
from the current stack pointer up to the initial stack pointer in gd-
>start_addr_sp. Also you changed all callers to always pass gd->ram_top
in "ulong end". Thus I think arch_lmb_reserve_generic() could omit
those redundant checks and could be simplified to:
sp -= align;
lmb_reserve(lmb, sp, gd->ram_top - sp);
Or am I overlooking something? Is that a valid use case to have U-Boot
area and stack area in different memory banks? If yes, shouldn't then
lmb_reserve() be called twice by arch_lmb_reserve() to protect stack
area AND U-Boot area?
> +
> + lmb_reserve(lmb, sp, bank_end - sp + 1);
> + break;
> + }
> +}
> +
> static void lmb_reserve_common(struct lmb *lmb, void *fdt_blob)
> {
> arch_lmb_reserve(lmb);
--
- Daniel
Re: [PATCH] Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig
Am Montag, dem 30.08.2021 um 22:48 -0400 schrieb Tom Rini: > On Tue, Aug 31, 2021 at 04:45:10AM +0200, Daniel Schwierzeck wrote: > > Am Freitag, dem 27.08.2021 um 21:18 -0400 schrieb Tom Rini: > > > This converts the following to Kconfig: > > >CONFIG_SKIP_LOWLEVEL_INIT > > >CONFIG_SKIP_LOWLEVEL_INIT_ONLY > > > > > > In order to do this, we need to introduce SPL and TPL variants of > > > these > > > options so that we can clearly disable these options only in SPL > > > in > > > some > > > cases, and both instances in other cases. > > > > > > Signed-off-by: Tom Rini > > > --- > > > README| 16 -- > > > arch/Kconfig | 57 > > > +++ > > > arch/arm/cpu/arm1136/start.S | 8 +-- > > > arch/arm/cpu/arm720t/start.S | 10 ++-- > > > arch/arm/cpu/arm920t/start.S | 8 +-- > > > arch/arm/cpu/arm926ejs/start.S| 8 +-- > > > arch/arm/cpu/arm946es/start.S | 6 +- > > > arch/arm/cpu/armv7/Makefile | 2 +- > > > arch/arm/cpu/armv7/start.S| 8 +-- > > > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++ > > > arch/arm/cpu/pxa/start.S | 6 +- > > > arch/arm/cpu/sa1100/start.S | 4 +- > > > arch/arm/include/asm/arch-am33xx/chilisom.h | 2 +- > > > arch/arm/mach-at91/arm920t/lowlevel_init.S| 4 +- > > > arch/arm/mach-imx/mx7/soc.c | 2 +- > > > arch/arm/mach-imx/syscounter.c| 2 +- > > > arch/arm/mach-mvebu/include/mach/config.h | 4 -- > > > arch/arm/mach-omap2/Kconfig | 1 + > > > arch/arm/mach-omap2/am33xx/Makefile | 2 +- > > > arch/arm/mach-omap2/am33xx/board.c| 6 +- > > > arch/arm/mach-omap2/am33xx/chilisom.c | 4 +- > > > arch/arm/mach-omap2/omap3/board.c | 4 +- > > > arch/arm/mach-omap2/omap3/lowlevel_init.S | 4 +- > > > arch/arm/mach-orion5x/Makefile| 2 +- > > > arch/arm/mach-rockchip/Kconfig| 1 + > > > arch/arm/mach-tegra/Kconfig | 1 + > > > arch/mips/cpu/start.S | 4 +- > > > arch/mips/mach-mtmips/mt7628/lowlevel_init.S | 4 +- > > > arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S| 4 +- > > > arch/nds32/cpu/n1213/ag101/lowlevel_init.S| 4 +- > > > arch/nds32/cpu/n1213/start.S | 2 +- > > > board/bosch/guardian/Makefile | 2 +- > > > board/bosch/guardian/board.c | 2 +- > > > board/eets/pdu001/Makefile| 2 +- > > > board/eets/pdu001/board.c | 4 +- > > > board/freescale/ls1021aqds/README | 5 +- > > > board/freescale/ls1021atwr/README | 5 +- > > > board/grinn/chiliboard/board.c| 6 +- > > > board/qca/ap152/ap152.c | 2 +- > > > board/tcl/sl50/Makefile | 2 +- > > > board/tcl/sl50/board.c| 2 +- > > > board/ti/am335x/Makefile | 2 +- > > > board/ti/am335x/board.c | 2 +- > > > board/ti/am43xx/Makefile | 2 +- > > > board/ti/am43xx/board.c | 2 +- > > > board/tplink/wdr4300/wdr4300.c| 2 +- > > > board/vscom/baltos/Makefile | 2 +- > > > configs/SBx81LIFKW_defconfig | 1 + > > > configs/SBx81LIFXCAT_defconfig| 1 + > > > configs/adp-ae3xx_defconfig | 1 + > > > configs/adp-ag101p_defconfig | 1 + > > > configs/am43xx_evm_defconfig | 1 + > > > configs/am43xx_evm_rtconly_defconfig | 1 + > > > configs/am43xx_evm_usbhost_boot_defconfig | 1 + > > > configs/am43xx_hs_evm_defconfig | 1 + > > > configs/am64x_evm_a53_defconfig | 1 + > > > configs/am65x_evm_a53_defconfig | 1 + > > > configs/am65x_hs_evm_a53_defconfig| 1 + > > > configs/arndale_defconfig | 2 + > > > configs/aspenite_defconfig| 1 + > > > configs/at91sam9260ek_data
Re: [PATCH] Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig
Am Freitag, dem 27.08.2021 um 21:18 -0400 schrieb Tom Rini: > This converts the following to Kconfig: >CONFIG_SKIP_LOWLEVEL_INIT >CONFIG_SKIP_LOWLEVEL_INIT_ONLY > > In order to do this, we need to introduce SPL and TPL variants of > these > options so that we can clearly disable these options only in SPL in > some > cases, and both instances in other cases. > > Signed-off-by: Tom Rini > --- > README| 16 -- > arch/Kconfig | 57 > +++ > arch/arm/cpu/arm1136/start.S | 8 +-- > arch/arm/cpu/arm720t/start.S | 10 ++-- > arch/arm/cpu/arm920t/start.S | 8 +-- > arch/arm/cpu/arm926ejs/start.S| 8 +-- > arch/arm/cpu/arm946es/start.S | 6 +- > arch/arm/cpu/armv7/Makefile | 2 +- > arch/arm/cpu/armv7/start.S| 8 +-- > arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 ++ > arch/arm/cpu/pxa/start.S | 6 +- > arch/arm/cpu/sa1100/start.S | 4 +- > arch/arm/include/asm/arch-am33xx/chilisom.h | 2 +- > arch/arm/mach-at91/arm920t/lowlevel_init.S| 4 +- > arch/arm/mach-imx/mx7/soc.c | 2 +- > arch/arm/mach-imx/syscounter.c| 2 +- > arch/arm/mach-mvebu/include/mach/config.h | 4 -- > arch/arm/mach-omap2/Kconfig | 1 + > arch/arm/mach-omap2/am33xx/Makefile | 2 +- > arch/arm/mach-omap2/am33xx/board.c| 6 +- > arch/arm/mach-omap2/am33xx/chilisom.c | 4 +- > arch/arm/mach-omap2/omap3/board.c | 4 +- > arch/arm/mach-omap2/omap3/lowlevel_init.S | 4 +- > arch/arm/mach-orion5x/Makefile| 2 +- > arch/arm/mach-rockchip/Kconfig| 1 + > arch/arm/mach-tegra/Kconfig | 1 + > arch/mips/cpu/start.S | 4 +- > arch/mips/mach-mtmips/mt7628/lowlevel_init.S | 4 +- > arch/nds32/cpu/n1213/ae3xx/lowlevel_init.S| 4 +- > arch/nds32/cpu/n1213/ag101/lowlevel_init.S| 4 +- > arch/nds32/cpu/n1213/start.S | 2 +- > board/bosch/guardian/Makefile | 2 +- > board/bosch/guardian/board.c | 2 +- > board/eets/pdu001/Makefile| 2 +- > board/eets/pdu001/board.c | 4 +- > board/freescale/ls1021aqds/README | 5 +- > board/freescale/ls1021atwr/README | 5 +- > board/grinn/chiliboard/board.c| 6 +- > board/qca/ap152/ap152.c | 2 +- > board/tcl/sl50/Makefile | 2 +- > board/tcl/sl50/board.c| 2 +- > board/ti/am335x/Makefile | 2 +- > board/ti/am335x/board.c | 2 +- > board/ti/am43xx/Makefile | 2 +- > board/ti/am43xx/board.c | 2 +- > board/tplink/wdr4300/wdr4300.c| 2 +- > board/vscom/baltos/Makefile | 2 +- > configs/SBx81LIFKW_defconfig | 1 + > configs/SBx81LIFXCAT_defconfig| 1 + > configs/adp-ae3xx_defconfig | 1 + > configs/adp-ag101p_defconfig | 1 + > configs/am43xx_evm_defconfig | 1 + > configs/am43xx_evm_rtconly_defconfig | 1 + > configs/am43xx_evm_usbhost_boot_defconfig | 1 + > configs/am43xx_hs_evm_defconfig | 1 + > configs/am64x_evm_a53_defconfig | 1 + > configs/am65x_evm_a53_defconfig | 1 + > configs/am65x_hs_evm_a53_defconfig| 1 + > configs/arndale_defconfig | 2 + > configs/aspenite_defconfig| 1 + > configs/at91sam9260ek_dataflash_cs0_defconfig | 1 + > configs/at91sam9260ek_dataflash_cs1_defconfig | 1 + > configs/at91sam9260ek_nandflash_defconfig | 1 + > configs/at91sam9261ek_dataflash_cs0_defconfig | 1 + > configs/at91sam9261ek_dataflash_cs3_defconfig | 1 + > configs/at91sam9261ek_nandflash_defconfig | 1 + > configs/at91sam9263ek_dataflash_cs0_defconfig | 1 + > configs/at91sam9263ek_dataflash_defconfig | 1 + > configs/at91sam9263ek_nandflash_defconfig | 1 + > configs/at91sam9263ek_norflash_defconfig | 1 + > configs/at91sam9g10ek_dataflash_cs0_defconfig | 1 + > configs/at91sam9g10ek_dataflash_cs3_defconfig | 1 + > configs/at91sam9g10ek_nandflash_defconfig | 1 + > configs/at91sam9g20ek_2mmc_defconfig | 1 + > .../at91sam9g20ek_2mmc_nandflash_defconfig| 1 + > configs/at91sam9g20ek_dataflash_cs0_defconfig | 1 + > configs/at91sam9g20ek_dataflash_cs1_defconfig | 1 + > configs/at91sam9g20ek_nandflash_defconfig | 1 + > configs/at91sam9m10g45ek_mmc_defconfig| 1 + > configs/at91sam9m10g45ek_nandflash_defconfig | 1 + > configs/at91sam9n12ek_mmc_defconfig
Re: [PATCH] Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig
Am Donnerstag, dem 26.08.2021 um 11:47 -0400 schrieb Tom Rini: > We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to > arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of > 16. > Introduce select statements for other architectures based on current > usage. For MIPS, we take the existing arch-specific symbol and > migrate > to the generic symbol. This lets us remove a little bit of otherwise > unused code. > > Cc: Alexey Brodkin > Cc: Anup Patel > Cc: Atish Patra > Cc: Bin Meng > Cc: Daniel Schwierzeck > Cc: Leo > Cc: Palmer Dabbelt > Cc: Paul Walmsley > Cc: Rick Chen > Cc: Sean Anderson > Cc: Simon Glass > Signed-off-by: Tom Rini > --- > I'm Cc'ing a bunch of RISC-V folks since that's where I'm least > confident and just put it per-board for now. > --- > arch/Kconfig | 25 + > arch/arc/include/asm/cache.h | 3 --- > arch/arm/Kconfig | 15 --- > arch/mips/Kconfig | 26 +++--- > arch/mips/include/asm/cache.h | 12 +--- > arch/mips/mach-bmips/Kconfig | 20 ++-- > arch/mips/mach-mtmips/Kconfig | 4 ++-- > arch/mips/mach-pic32/Kconfig | 2 +- > arch/powerpc/cpu/mpc83xx/Kconfig | 6 ++ > arch/powerpc/cpu/mpc85xx/Kconfig | 15 +++ > arch/powerpc/cpu/mpc8xx/Kconfig| 2 ++ > arch/powerpc/include/asm/cache.h | 7 --- > arch/riscv/Kconfig | 2 ++ > arch/sandbox/include/asm/cache.h | 1 - > arch/x86/include/asm/cache.h | 7 +-- > include/configs/M5208EVBE.h| 1 - > include/configs/M5235EVB.h | 1 - > include/configs/M5249EVB.h | 1 - > include/configs/M5253DEMO.h| 1 - > include/configs/M5272C3.h | 1 - > include/configs/M5275EVB.h | 1 - > include/configs/M5282EVB.h | 1 - > include/configs/M53017EVB.h| 1 - > include/configs/M5329EVB.h | 1 - > include/configs/M5373EVB.h | 1 - > include/configs/amcore.h | 1 - > include/configs/astro_mcf5373l.h | 1 - > include/configs/cobra5272.h| 1 - > include/configs/eb_cpu5282.h | 1 - > include/configs/mx7ulp_evk.h | 2 -- > include/configs/rk3188_common.h| 2 -- > include/configs/rk3368_common.h| 2 -- > include/configs/sifive-unmatched.h | 2 -- > include/configs/sipeed-maix.h | 1 - > include/configs/stmark2.h | 1 - > 35 files changed, 68 insertions(+), 103 deletions(-) > > diff --git a/arch/Kconfig b/arch/Kconfig > index b6f9e177b645..25f4a15b19f9 100644 > --- a/arch/Kconfig > +++ b/arch/Kconfig > @@ -7,6 +7,27 @@ config HAVE_ARCH_IOREMAP > config NEEDS_MANUAL_RELOC > bool > > +config SYS_CACHE_SHIFT_4 > + bool > + > +config SYS_CACHE_SHIFT_5 > + bool > + > +config SYS_CACHE_SHIFT_6 > + bool > + > +config SYS_CACHE_SHIFT_7 > + bool > + > +config SYS_CACHELINE_SIZE > + int > + default 128 if SYS_CACHE_SHIFT_7 > + default 64 if SYS_CACHE_SHIFT_6 > + default 32 if SYS_CACHE_SHIFT_5 > + default 16 if SYS_CACHE_SHIFT_4 > + # Fall-back for MIPS > + default 32 if MIPS can't we get rid of the SYS_ prefix? Also _CACHE_ is ambiguous, L1_CACHE_SHIFT_* and L1_CACHELINE_SIZE are possibly more suitable. Otherwise: Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH 18/33] pci: msc01: Drop use of DM_PCI
Am Montag, den 26.07.2021, 07:34 -0600 schrieb Simon Glass: > Now that DM_PCI is always enabled we don't need to check it. Drop > this > old code. > > Signed-off-by: Simon Glass > --- > > drivers/pci/pci_msc01.c | 64 - > > 1 file changed, 64 deletions(-) > > Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH 17/33] pci: gt64120: Drop use of DM_PCI
Am Montag, den 26.07.2021, 07:34 -0600 schrieb Simon Glass: > Now that DM_PCI is always enabled we don't need to check it. Drop > this > old code. > > Signed-off-by: Simon Glass > --- > > drivers/pci/pci_gt64120.c | 64 --- > > 1 file changed, 64 deletions(-) > > Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: [PATCH 15/33] ppc: malta: Drop use of DM_PCI
Am Montag, den 26.07.2021, 07:34 -0600 schrieb Simon Glass: > Now that DM_PCI is always enabled we don't need to check it. Drop > this > old code. > > Signed-off-by: Simon Glass > --- > > board/imgtec/malta/malta.c | 67 > -- > 1 file changed, 67 deletions(-) > > commit subject should be "mips: malta: ..." and not "ppc: malta: ..." ;) Reviewed-by: Daniel Schwierzeck -- - Daniel
Re: U-Boot loaded RAMDisk crashes Linux on MT7623
Hi Daniel, Am Montag, den 19.07.2021, 18:34 +0100 schrieb Daniel Golle: > Hi, > > I writing in the hope that someone has a good idea about why U-boot > is > handing over a broken memory address for a loaded ramdisk which > results > in Linux crashing very early on boot on MediaTek's MT7623N SoC > (ARMv7). > If anyone has a good idea why this is happening, I'd be very glad, as > this currently prevents me from updating that target in OpenWrt. > Background: > OpenWrt used to have the initramdisk built-into the kernel itself. > Having it separate is nicer as then you won't need to recompile the > kernel or even have a compiler installed in order to modify the > ramdisk. This already works great on MT7622 and it'd be great to have > it the same way on MT7623 (and MT7629 in future). > > So when loading a uImage.FIT with RAMDisk subimage to me it looks > like > U-Boot is not translating the address of the ramdisk correctly, see > logs below: > > U-Boot> tftpboot 0x8800 openwrt-mediatek-mt7623-bpi_bananapi-r2- > initramfs-recovery.itb > Using ethernet@1b10 device > TFTP from server 192.168.5.2; our IP address is 192.168.5.100 > Filename 'openwrt-mediatek-mt7623-bpi_bananapi-r2-initramfs- > recovery.itb'. > Load address: 0x8800 > Loading: > # > > # > > # > > # > > # > > # > > # > > # > > # > > # > > # > 13 MiB/s > done > Bytes transferred = 10492520 (a01a68 hex) > U-Boot> bootm > ## Loading kernel from FIT Image at 8800 ... >Using 'config-1' configuration >Trying 'kernel-1' kernel subimage > Description: ARM OpenWrt Linux-5.10.51 > Type: Kernel Image > Compression: gzip compressed > Data Start: 0x88e4 > Data Size:4944975 Bytes = 4.7 MiB > Architecture: ARM > OS: Linux > Load Address: 0x80008000 > Entry Point: 0x80008000 > Hash algo:crc32 > Hash value: 9da8225f > Hash algo:sha1 > Hash value: ea4e69501bed0925ecdee0bb6b3a3b489fedc38c >Verifying Hash Integrity ... crc32+ sha1+ OK > ## Loading ramdisk from FIT Image at 8800 ... >Using 'config-1' configuration >Trying 'initrd-1' ramdisk subimage > Description: ARM OpenWrt bpi_bananapi-r2 initrd > Type: RAMDisk Image > Compression: Unknown Compression > Data Start: 0x884b7668 > Data Size:5511960 Bytes = 5.3 MiB > Architecture: ARM > OS: Linux > Load Address: unavailable > Entry Point: unavailable you could try to explicitely set load and entry address to 0. > Hash algo:crc32 > Hash value: 01e5fbf0 > Hash algo:sha1 > Hash value: 6ceb78df26920d97dee505ddeb0318e0c1522ba0 >Verifying Hash Integrity ... crc32+ sha1+ OK > WARNING: 'compression' nodes for ramdisks are deprecated, please fix > your .its file! > ## Loading fdt from FIT Image at 8800 ... >Using 'config-1' configuration >Trying 'fdt-1' fdt subimage > Description: ARM OpenWrt bpi_bananapi-r2 device tree blob > Type: Flat Device Tree > Compression: uncompressed > Data Start: 0x889f9288 > Data Size:33453 Bytes = 32.7 KiB > Architecture: ARM > Hash algo:crc32 > Hash value: a2599155 > Hash algo:sha1 > Hash value: 59c64737be8bda92b33417dfadca87e9c4662be2 >Verifying Hash Integrity ... crc32+ sha1+ OK >Booting using the fdt blob at 0x889f9288 >Uncompressing Kernel Image >Loading Ramdisk to ff4b9000, end ff9fab18 ... OK >^^ >Using Device Tree in place at 889f9288, end 88a04534 > > Starting kernel ... > > [0.00] Booting Linux on physical CPU 0x0 > [0.00] Linux version 5.10.51 (daniel@box) (arm-openwrt-linux- > muslgnueabi-gcc (OpenWrt GCC 8.4.0 r17073+11-8bb4437c01) 8.4.0, GNU > ld (GNU Binutils) 2.34) #0 SMP PREEMPT Mon Jul 19 12:26:15 2021 > [0.00] CPU: ARMv7 Processor [410fc073] revision 3 (ARMv7), > cr=10c5387d > [0.00] CPU: div instructions available: patching division > code > [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing > instruction cache > [
[PULL] u-boot-mips
Gitlab: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/8294 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=25=results The following changes since commit f929ce50727bf1019323d6c199dfd3a5755c5474: Merge branch '2021-07-16-cleanup-image-support' (2021-07-17 11:39:50 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2021-07-18 for you to fetch changes up to 526ceb43878bfcaaeffbb988e363e89500695bee: MIPS: malta: enable PCI driver model (2021-07-18 20:37:39 +0200) - mips: gardena-smart-gateway: adjust config to new production values - mips: malta: convert to PCI DM and ETH DM Daniel Schwierzeck (6): dm: pci: add option to map virtual system memory base address pci: gt64120: convert to driver model pci: msc01: convert to driver model MIPS: malta: add DT bindings for PCI host controller MIPS: malta: add support for PCI driver model MIPS: malta: enable PCI driver model Reto Schneider (1): mips: mt7688: gardena-smart-gateway: Adjust to production values arch/mips/Kconfig | 4 ++ arch/mips/dts/mti,malta.dts| 28 + board/imgtec/malta/malta.c | 80 +- configs/gardena-smart-gateway-mt7688_defconfig | 11 +++- drivers/pci/Kconfig| 13 + drivers/pci/pci-uclass.c | 9 ++- drivers/pci/pci_gt64120.c | 74 +++- drivers/pci/pci_msc01.c| 72 ++- 8 files changed, 284 insertions(+), 7 deletions(-)
Re: [PATCH v2 0/6] Convert MIPS Malta boards to PCI DM
Am Donnerstag, den 15.07.2021, 20:53 +0200 schrieb Daniel Schwierzeck: > This series converts the PCI host controller drivers used by MIPS > Malta and the board-specific PCI setup code to PCI driver model. > Because the AMD PCNET driver is already converted to ETH driver > model, simply enable CONFIG_DM_ETH as well. > > A patch in PCI uclass core is currently required for MIPS wanting > to use PCI DM (except Octeon MIPS64) due to CONFIG_SYS_SDRAM_BASE > being used as a virtual address on all MIPS boards. > > The series for now is only tested with Qemu and the GT64120 PCI > controller. The Malta Qemu tests are already covered by U-Boot CI > Support for the MSC01 controller is prepared. The used PCI controller > depends on the plugged core card (Qemu emulates the CoreLV card with > GT64120). > > Dynamic selection of the according PCI DT nodes via > CONFIG_OF_BOARD_FIXUP > is prepared but not yet enabled. This requires fixing of the call > order of > fix_fdt() in board_init_f, otherwise the passed-in rw_fdt_blob > pointer > will point to a read-only NOR flash address. I'll send a separate > RFC patch for this. > > I'll send a cleanup series for removing non-DM code after the merge > windows has closed and the PCI DM conversion deadline has been > enforced. > > Changes in v2: > - add empty line before return statements > - add empty line before return statements > - use dm_pci_clrset_config32() where possible > > Daniel Schwierzeck (6): > dm: pci: add option to map virtual system memory base address > pci: gt64120: convert to driver model > pci: msc01: convert to driver model > MIPS: malta: add DT bindings for PCI host controller > MIPS: malta: add support for PCI driver model > MIPS: malta: enable PCI driver model > > arch/mips/Kconfig | 4 ++ > arch/mips/dts/mti,malta.dts | 28 + > board/imgtec/malta/malta.c | 80 > - > drivers/pci/Kconfig | 13 ++ > drivers/pci/pci-uclass.c| 9 +++-- > drivers/pci/pci_gt64120.c | 74 +- > drivers/pci/pci_msc01.c | 72 - > 7 files changed, 274 insertions(+), 6 deletions(-) > applied to u-boot-mips -- - Daniel
[PATCH v2 6/6] MIPS: malta: enable PCI driver model
Enable DM_PCI and DM_ETH on MIPS Malta. Signed-off-by: Daniel Schwierzeck --- (no changes since v1) arch/mips/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e54801673b..6b1f10d9a0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -14,8 +14,11 @@ choice config TARGET_MALTA bool "Support malta" + select BOARD_EARLY_INIT_R select DM select DM_SERIAL + select DM_PCI + select DM_ETH select DYNAMIC_IO_PORT_BASE select MIPS_CM select MIPS_INSERT_BOOT_CONFIG @@ -23,6 +26,7 @@ config TARGET_MALTA select MIPS_L2_CACHE select OF_CONTROL select OF_ISA_BUS + select PCI_MAP_SYSTEM_MEMORY select ROM_EXCEPTION_VECTORS select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 -- 2.32.0
[PATCH v2 5/6] MIPS: malta: add support for PCI driver model
As almost all peripherals are connected via PCI dependent on the
used core card, PCI setup is always required. Thus run pci_init()
including PCI scanning and probing and core card specific setups
in board_early_init_r().
Also prepare support for dynamically managing the status of the
different PCI DT nodes dependent on used core card via option
CONFIG_OF_BOARD_FIXUP. Before this feature can be enabled,
the call order of the fix_fdt() init hook in board_init_f
needs to be changed. Otherwise rw_fdt_blob points to a read-only
NOR flash address. Thus this options needs to stay disabled
until the board_init_f problem could be solved. This breaks
running the default U-Boot image on real HW using the FPGA core
card but Qemu emulation still works. Currently Qemu is more
important as MIPS CI tests depend on Malta and the deadline
for PCI DM conversion will be enforced soon.
Signed-off-by: Daniel Schwierzeck
---
Changes in v2:
- use dm_pci_clrset_config32() where possible
board/imgtec/malta/malta.c | 80 +-
1 file changed, 79 insertions(+), 1 deletion(-)
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index c04f727961..9af1f92e5d 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -4,7 +4,8 @@
* Copyright (C) 2013 Imagination Technologies
*/
-#include
+#include
+#include
#include
#include
#include
@@ -24,6 +25,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define MALTA_GT_PATH "/pci0@1be0"
+#define MALTA_MSC_PATH "/pci0@1bd0"
+
enum core_card {
CORE_UNKNOWN,
CORE_LV,
@@ -120,10 +124,12 @@ int checkboard(void)
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_ETH)
int board_eth_init(struct bd_info *bis)
{
return pci_eth_init(bis);
}
+#endif
void _machine_restart(void)
{
@@ -167,6 +173,77 @@ int misc_init_r(void)
return 0;
}
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+/*
+ * TODO: currently doesn't work because rw_fdt_blob points to a
+ * NOR flash address. This needs some changes in board_init_f.
+ */
+int board_fix_fdt(void *rw_fdt_blob)
+{
+ int node = -1;
+
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
+ break;
+ default:
+ case SYSCON_MSC01:
+ node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
+ break;
+ }
+
+ return fdt_status_okay(rw_fdt_blob, node);
+}
+#endif
+
+#if IS_ENABLED(CONFIG_DM_PCI)
+int board_early_init_r(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ pci_init();
+
+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
+PCI_DEVICE_ID_INTEL_82371AB_0, 0, );
+ if (ret)
+ panic("Failed to find PIIX4 PCI bridge\n");
+
+ /* setup PCI interrupt routing */
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+ /* mux SERIRQ onto SERIRQ pin */
+ dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
+ PCI_CFG_PIIX4_GENCFG_SERIRQ);
+
+ /* enable SERIRQ - Linux currently depends upon this */
+ dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
+ PCI_CFG_PIIX4_SERIRQC_EN |
PCI_CFG_PIIX4_SERIRQC_CONT);
+
+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
+PCI_DEVICE_ID_INTEL_82371AB, 0, );
+ if (ret)
+ panic("Failed to find PIIX4 IDE controller\n");
+
+ /* enable bus master & IO access */
+ dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
+ PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
+ /* set latency */
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+ /* enable IDE/ATA */
+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+
+ return 0;
+}
+#else
void pci_init_board(void)
{
pci_dev_t bdf;
@@ -231,3 +308,4 @@ void pci_init_board(void)
pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
PCI_CFG_PIIX4_IDETIM_IDE);
}
+#endif
--
2.32.0
[PATCH v2 4/6] MIPS: malta: add DT bindings for PCI host controller
Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.
Signed-off-by: Daniel Schwierzeck
---
(no changes since v1)
arch/mips/dts/mti,malta.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
index d339229c2a..ef47a340bb 100644
--- a/arch/mips/dts/mti,malta.dts
+++ b/arch/mips/dts/mti,malta.dts
@@ -29,4 +29,32 @@
u-boot,dm-pre-reloc;
};
};
+
+ pci0@1bd0 {
+ compatible = "mips,pci-msc01";
+ device_type = "pci";
+ reg = <0x1bd0 0x2000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ ranges = <0x0100 0 0x 0x 0 0x80
/* I/O */
+ 0x0200 0 0x1000 0xb000 0 0x1000
/* MEM */>;
+
+ status = "disabled";
+ };
+
+ pci0@1be0 {
+ compatible = "marvell,pci-gt64120";
+ device_type = "pci";
+ reg = <0x1be0 0x2000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ ranges = <0x0100 0 0x 0x 0 0x2
/* I/O */
+ 0x0200 0 0x1000 0x1000 0 0x800
/* MEM */>;
+
+ status = "okay";
+ };
};
--
2.32.0
[PATCH v2 3/6] pci: msc01: convert to driver model
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
Reviewed-by: Simon Glass
---
Changes in v2:
- add empty line before return statements
drivers/pci/pci_msc01.c | 72 -
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index 04838200a8..c17da475d0 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -4,7 +4,7 @@
* Author: Paul Burton
*/
-#include
+#include
#include
#include
#include
@@ -62,6 +62,7 @@ static int msc01_config_access(struct msc01_pci_controller
*msc01,
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -123,3 +124,72 @@ void msc01_pci_init(void *base, unsigned long sys_bus,
unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+uint where, ulong *val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, )) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+
+ return 0;
+}
+
+static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where,
))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, );
+
+ return 0;
+}
+
+static int msc01_pci_probe(struct udevice *dev)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+
+ msc01->base = dev_remap_addr(dev);
+ if (!msc01->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops msc01_pci_ops = {
+ .read_config= msc01_pci_read_config,
+ .write_config = msc01_pci_write_config,
+};
+
+static const struct udevice_id msc01_pci_ids[] = {
+ { .compatible = "mips,pci-msc01" },
+ { }
+};
+
+U_BOOT_DRIVER(msc01_pci) = {
+ .name = "msc01_pci",
+ .id = UCLASS_PCI,
+ .of_match = msc01_pci_ids,
+ .ops= _pci_ops,
+ .probe = msc01_pci_probe,
+ .priv_auto = sizeof(struct msc01_pci_controller),
+};
+#endif
--
2.32.0
[PATCH v2 2/6] pci: gt64120: convert to driver model
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
Reviewed-by: Simon Glass
---
Changes in v2:
- add empty line before return statements
drivers/pci/pci_gt64120.c | 74 ++-
1 file changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index 80f11fedd1..e57fedf036 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -8,7 +8,7 @@
*Maciej W. Rozycki
*/
-#include
+#include
#include
#include
#include
@@ -114,6 +114,7 @@ static int gt_config_access(struct gt64120_pci_controller
*gt,
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -175,3 +176,74 @@ void gt64120_pci_init(void *regs, unsigned long sys_bus,
unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong *val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, )) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+
+ return 0;
+}
+
+static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, ))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, );
+
+ return 0;
+}
+
+static int gt64120_pci_probe(struct udevice *dev)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+
+ gt->regs = dev_remap_addr(dev);
+ if (!gt->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops gt64120_pci_ops = {
+ .read_config= gt64120_pci_read_config,
+ .write_config = gt64120_pci_write_config,
+};
+
+static const struct udevice_id gt64120_pci_ids[] = {
+ { .compatible = "marvell,pci-gt64120" },
+ { }
+};
+
+U_BOOT_DRIVER(gt64120_pci) = {
+ .name = "gt64120_pci",
+ .id = UCLASS_PCI,
+ .of_match = gt64120_pci_ids,
+ .ops= _pci_ops,
+ .probe = gt64120_pci_probe,
+ .priv_auto = sizeof(struct gt64120_pci_controller),
+};
+#endif
--
2.32.0
[PATCH v2 1/6] dm: pci: add option to map virtual system memory base address
On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workaround is required for MIPS boards with
PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved.
Add a compile-time option to let the PCI uclass core optionally map
the DRAM address to a physical address when adding the PCI region
of type PCI_REGION_SYS_MEMORY.
Signed-off-by: Daniel Schwierzeck
Reviewed-by: Stefan Roese
---
(no changes since v1)
drivers/pci/Kconfig | 13 +
drivers/pci/pci-uclass.c | 9 ++---
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 517cf956ea..c49cb6eac9 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY
region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus.
+config PCI_MAP_SYSTEM_MEMORY
+ bool "Map local system memory from a virtual base address"
+ depends on PCI || DM_PCI
+ depends on MIPS
+ default n
+ help
+ Say Y if base address of system memory is being used as a virtual
address
+ instead of a physical address (e.g. on MIPS). The PCI core will then
remap
+ the virtual memory base address to a physical address when adding the
PCI
+ region of type PCI_REGION_SYS_MEMORY.
+ This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is
still
+ being used as virtual address.
+
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
depends on PCI || DM_PCI
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index cb9aa81835..110a12b94b 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1003,10 +1003,13 @@ static void decode_regions(struct pci_controller *hose,
ofnode parent_node,
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
+ phys_addr_t start = bd->bi_dram[i].start;
+
+ if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
+ start = virt_to_phys((void
*)(uintptr_t)bd->bi_dram[i].start);
+
pci_set_region(hose->regions + hose->region_count++,
- bd->bi_dram[i].start,
- bd->bi_dram[i].start,
- bd->bi_dram[i].size,
+ start, start, bd->bi_dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
}
}
--
2.32.0
[PATCH v2 0/6] Convert MIPS Malta boards to PCI DM
This series converts the PCI host controller drivers used by MIPS Malta and the board-specific PCI setup code to PCI driver model. Because the AMD PCNET driver is already converted to ETH driver model, simply enable CONFIG_DM_ETH as well. A patch in PCI uclass core is currently required for MIPS wanting to use PCI DM (except Octeon MIPS64) due to CONFIG_SYS_SDRAM_BASE being used as a virtual address on all MIPS boards. The series for now is only tested with Qemu and the GT64120 PCI controller. The Malta Qemu tests are already covered by U-Boot CI Support for the MSC01 controller is prepared. The used PCI controller depends on the plugged core card (Qemu emulates the CoreLV card with GT64120). Dynamic selection of the according PCI DT nodes via CONFIG_OF_BOARD_FIXUP is prepared but not yet enabled. This requires fixing of the call order of fix_fdt() in board_init_f, otherwise the passed-in rw_fdt_blob pointer will point to a read-only NOR flash address. I'll send a separate RFC patch for this. I'll send a cleanup series for removing non-DM code after the merge windows has closed and the PCI DM conversion deadline has been enforced. Changes in v2: - add empty line before return statements - add empty line before return statements - use dm_pci_clrset_config32() where possible Daniel Schwierzeck (6): dm: pci: add option to map virtual system memory base address pci: gt64120: convert to driver model pci: msc01: convert to driver model MIPS: malta: add DT bindings for PCI host controller MIPS: malta: add support for PCI driver model MIPS: malta: enable PCI driver model arch/mips/Kconfig | 4 ++ arch/mips/dts/mti,malta.dts | 28 + board/imgtec/malta/malta.c | 80 - drivers/pci/Kconfig | 13 ++ drivers/pci/pci-uclass.c| 9 +++-- drivers/pci/pci_gt64120.c | 74 +- drivers/pci/pci_msc01.c | 72 - 7 files changed, 274 insertions(+), 6 deletions(-) -- 2.32.0
Re: [PATCH] mips: mt7688: gardena-smart-gateway: Adjust to production values
Am Donnerstag, den 17.06.2021, 18:09 +0200 schrieb Reto Schneider: > From: Reto Schneider > > This commit updates the default config with the values that will > be used soon on the MediaTek MT7688 based GARDENA smart gateway. > > CONFIG_SPL_SYS_MALLOC_F_LEN had to be increased due to the more > demanding new configuration. > > Signed-off-by: Reto Schneider > --- > > configs/gardena-smart-gateway-mt7688_defconfig | 13 +++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > applied to u-boot-mips, thanks. -- - Daniel
Re: [PATCH 5/6] MIPS: malta: add support for PCI driver model
Hi Simon,
Am Samstag, den 10.07.2021, 18:00 -0600 schrieb Simon Glass:
> () Hi Daniel,
>
> On Tue, 6 Jul 2021 at 08:22, Daniel Schwierzeck
> wrote:
> > As almost all peripherals are connected via PCI dependent on the
> > used core card, PCI setup is always required. Thus run pci_init()
> > including PCI scanning and probing and core card specific setups
> > in board_early_init_r().
> >
> > Also prepare support for dynamically managing the status of the
> > different PCI DT nodes dependent on used core card via option
> > CONFIG_OF_BOARD_FIXUP. Before this feature can be enabled,
> > the call order of the fix_fdt() init hook in board_init_f
> > needs to be changed. Otherwise rw_fdt_blob points to a read-only
> > NOR flash address. Thus this options needs to stay disabled
> > until the board_init_f problem could be solved. This breaks
> > running the default U-Boot image on real HW using the FPGA core
> > card but Qemu emulation still works. Currently Qemu is more
> > important as MIPS CI tests depend on Malta and the deadline
> > for PCI DM conversion will be enforced soon.
> >
> > Signed-off-by: Daniel Schwierzeck
> > ---
> >
> > board/imgtec/malta/malta.c | 84
> > +-
> > 1 file changed, 83 insertions(+), 1 deletion(-)
> >
> > diff --git a/board/imgtec/malta/malta.c
> > b/board/imgtec/malta/malta.c
> > index c04f727961..e78d5a7fbc 100644
> > --- a/board/imgtec/malta/malta.c
> > +++ b/board/imgtec/malta/malta.c
> > @@ -4,7 +4,8 @@
> > * Copyright (C) 2013 Imagination Technologies
> > */
> >
> > -#include
> > +#include
> > +#include
> > #include
> > #include
> > #include
> > @@ -24,6 +25,9 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +#define MALTA_GT_PATH "/pci0@1be0"
> > +#define MALTA_MSC_PATH "/pci0@1bd0"
> > +
> > enum core_card {
> > CORE_UNKNOWN,
> > CORE_LV,
> > @@ -120,10 +124,12 @@ int checkboard(void)
> > return 0;
> > }
> >
> > +#if !IS_ENABLED(CONFIG_DM_ETH)
> > int board_eth_init(struct bd_info *bis)
> > {
> > return pci_eth_init(bis);
> > }
> > +#endif
> >
> > void _machine_restart(void)
> > {
> > @@ -167,6 +173,81 @@ int misc_init_r(void)
> > return 0;
> > }
> >
> > +#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
> > +/*
> > + * TODO: currently doesn't work because rw_fdt_blob points to a
> > + * NOR flash address. This needs some changes in board_init_f.
> > + */
> > +int board_fix_fdt(void *rw_fdt_blob)
> > +{
> > + int node = -1;
> > +
> > + switch (malta_sys_con()) {
> > + case SYSCON_GT64120:
> > + node = fdt_path_offset(rw_fdt_blob,
> > MALTA_GT_PATH);
> > + break;
> > + default:
> > + case SYSCON_MSC01:
> > + node = fdt_path_offset(rw_fdt_blob,
> );
> > + break;
> > + }
> > +
> > + return fdt_status_okay(rw_fdt_blob, node);
> > +}
> > +#endif
> > +
> > +#if IS_ENABLED(CONFIG_DM_PCI)
> > +int board_early_init_r(void)
> > +{
> > + struct udevice *dev;
> > + u32 val32;
> > + u8 val8;
> > + int ret;
> > +
> > + pci_init();
> > +
> > + ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
> > +PCI_DEVICE_ID_INTEL_82371AB_0, 0,
> > );
>
> This feels a bit wonky to me. How about a sysinfo driver for your
> board which does this init? Then you could just probe it.
>
> As to finding PCI devices, your sysinfo driver could have a few
> phandle properties to point to the two devices you need.
>
> But if these are really SYSCON devices, why not use the SYSCON
> devices, give them a unique ID (perhaps you already have with
> SYSCON_MSC01) and then call syscon_get_regmap_by_driver_data() ?
This is just a reimplementation of the original pci_init_board()
function. I wanted to keep the changes small and to keep the original
PCI init behaviour to get the PCI DM conversion done and get this patch
series merged in this merge window ;) The Malta board is the reference
board for MIPS Qemu and essential for testing and U-Boot CI. Therefore
it would be very bad if it gets removed due to the PCI DM conversion
deadline.
I already tried to add PIIX4 IRQ and ATA drivers for this init code.
But those drivers were just bound and I didn't have an idea ho
[PATCH 6/6] MIPS: malta: enable PCI driver model
Enable DM_PCI and DM_ETH on MIPS Malta. Signed-off-by: Daniel Schwierzeck --- arch/mips/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e54801673b..6b1f10d9a0 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -14,8 +14,11 @@ choice config TARGET_MALTA bool "Support malta" + select BOARD_EARLY_INIT_R select DM select DM_SERIAL + select DM_PCI + select DM_ETH select DYNAMIC_IO_PORT_BASE select MIPS_CM select MIPS_INSERT_BOOT_CONFIG @@ -23,6 +26,7 @@ config TARGET_MALTA select MIPS_L2_CACHE select OF_CONTROL select OF_ISA_BUS + select PCI_MAP_SYSTEM_MEMORY select ROM_EXCEPTION_VECTORS select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 -- 2.32.0
[PATCH 5/6] MIPS: malta: add support for PCI driver model
As almost all peripherals are connected via PCI dependent on the
used core card, PCI setup is always required. Thus run pci_init()
including PCI scanning and probing and core card specific setups
in board_early_init_r().
Also prepare support for dynamically managing the status of the
different PCI DT nodes dependent on used core card via option
CONFIG_OF_BOARD_FIXUP. Before this feature can be enabled,
the call order of the fix_fdt() init hook in board_init_f
needs to be changed. Otherwise rw_fdt_blob points to a read-only
NOR flash address. Thus this options needs to stay disabled
until the board_init_f problem could be solved. This breaks
running the default U-Boot image on real HW using the FPGA core
card but Qemu emulation still works. Currently Qemu is more
important as MIPS CI tests depend on Malta and the deadline
for PCI DM conversion will be enforced soon.
Signed-off-by: Daniel Schwierzeck
---
board/imgtec/malta/malta.c | 84 +-
1 file changed, 83 insertions(+), 1 deletion(-)
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index c04f727961..e78d5a7fbc 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -4,7 +4,8 @@
* Copyright (C) 2013 Imagination Technologies
*/
-#include
+#include
+#include
#include
#include
#include
@@ -24,6 +25,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#define MALTA_GT_PATH "/pci0@1be0"
+#define MALTA_MSC_PATH "/pci0@1bd0"
+
enum core_card {
CORE_UNKNOWN,
CORE_LV,
@@ -120,10 +124,12 @@ int checkboard(void)
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_ETH)
int board_eth_init(struct bd_info *bis)
{
return pci_eth_init(bis);
}
+#endif
void _machine_restart(void)
{
@@ -167,6 +173,81 @@ int misc_init_r(void)
return 0;
}
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+/*
+ * TODO: currently doesn't work because rw_fdt_blob points to a
+ * NOR flash address. This needs some changes in board_init_f.
+ */
+int board_fix_fdt(void *rw_fdt_blob)
+{
+ int node = -1;
+
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
+ break;
+ default:
+ case SYSCON_MSC01:
+ node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
+ break;
+ }
+
+ return fdt_status_okay(rw_fdt_blob, node);
+}
+#endif
+
+#if IS_ENABLED(CONFIG_DM_PCI)
+int board_early_init_r(void)
+{
+ struct udevice *dev;
+ u32 val32;
+ u8 val8;
+ int ret;
+
+ pci_init();
+
+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
+PCI_DEVICE_ID_INTEL_82371AB_0, 0, );
+ if (ret)
+ panic("Failed to find PIIX4 PCI bridge\n");
+
+ /* setup PCI interrupt routing */
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+ /* mux SERIRQ onto SERIRQ pin */
+ dm_pci_read_config32(dev, PCI_CFG_PIIX4_GENCFG, );
+ val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_GENCFG, val32);
+
+ /* enable SERIRQ - Linux currently depends upon this */
+ dm_pci_read_config8(dev, PCI_CFG_PIIX4_SERIRQC, );
+ val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_SERIRQC, val8);
+
+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
+PCI_DEVICE_ID_INTEL_82371AB, 0, );
+ if (ret)
+ panic("Failed to find PIIX4 IDE controller\n");
+
+ /* enable bus master & IO access */
+ val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
+ dm_pci_write_config32(dev, PCI_COMMAND, val32);
+
+ /* set latency */
+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
+
+ /* enable IDE/ATA */
+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
+ PCI_CFG_PIIX4_IDETIM_IDE);
+
+ return 0;
+}
+#else
void pci_init_board(void)
{
pci_dev_t bdf;
@@ -231,3 +312,4 @@ void pci_init_board(void)
pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
PCI_CFG_PIIX4_IDETIM_IDE);
}
+#endif
--
2.32.0
[PATCH 4/6] MIPS: malta: add DT bindings for PCI host controller
Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.
Signed-off-by: Daniel Schwierzeck
---
arch/mips/dts/mti,malta.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/mips/dts/mti,malta.dts b/arch/mips/dts/mti,malta.dts
index d339229c2a..ef47a340bb 100644
--- a/arch/mips/dts/mti,malta.dts
+++ b/arch/mips/dts/mti,malta.dts
@@ -29,4 +29,32 @@
u-boot,dm-pre-reloc;
};
};
+
+ pci0@1bd0 {
+ compatible = "mips,pci-msc01";
+ device_type = "pci";
+ reg = <0x1bd0 0x2000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ ranges = <0x0100 0 0x 0x 0 0x80
/* I/O */
+ 0x0200 0 0x1000 0xb000 0 0x1000
/* MEM */>;
+
+ status = "disabled";
+ };
+
+ pci0@1be0 {
+ compatible = "marvell,pci-gt64120";
+ device_type = "pci";
+ reg = <0x1be0 0x2000>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0x0>;
+ ranges = <0x0100 0 0x 0x 0 0x2
/* I/O */
+ 0x0200 0 0x1000 0x1000 0 0x800
/* MEM */>;
+
+ status = "okay";
+ };
};
--
2.32.0
[PATCH 3/6] pci: msc01: convert to driver model
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
---
drivers/pci/pci_msc01.c | 70 -
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index 04838200a8..ad203c86d0 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -4,7 +4,7 @@
* Author: Paul Burton
*/
-#include
+#include
#include
#include
#include
@@ -62,6 +62,7 @@ static int msc01_config_access(struct msc01_pci_controller
*msc01,
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -123,3 +124,70 @@ void msc01_pci_init(void *base, unsigned long sys_bus,
unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+uint where, ulong *val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where, )) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+ return 0;
+}
+
+static int msc01_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val, enum pci_size_t size)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (msc01_config_access(msc01, PCI_ACCESS_READ, bdf, where,
))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ msc01_config_access(msc01, PCI_ACCESS_WRITE, bdf, where, );
+ return 0;
+}
+
+static int msc01_pci_probe(struct udevice *dev)
+{
+ struct msc01_pci_controller *msc01 = dev_get_priv(dev);
+
+ msc01->base = dev_remap_addr(dev);
+ if (!msc01->base)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops msc01_pci_ops = {
+ .read_config= msc01_pci_read_config,
+ .write_config = msc01_pci_write_config,
+};
+
+static const struct udevice_id msc01_pci_ids[] = {
+ { .compatible = "mips,pci-msc01" },
+ { }
+};
+
+U_BOOT_DRIVER(msc01_pci) = {
+ .name = "msc01_pci",
+ .id = UCLASS_PCI,
+ .of_match = msc01_pci_ids,
+ .ops= _pci_ops,
+ .probe = msc01_pci_probe,
+ .priv_auto = sizeof(struct msc01_pci_controller),
+};
+#endif
--
2.32.0
[PATCH 1/6] dm: pci: add option to map virtual system memory base address
On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workaround is required for MIPS boards with
PCI support until the CONFIG_SYS_SDRAM_BASE issue could be solved.
Add a compile-time option to let the PCI uclass core optionally map
the DRAM address to a physical address when adding the PCI region
of type PCI_REGION_SYS_MEMORY.
Signed-off-by: Daniel Schwierzeck
---
drivers/pci/Kconfig | 13 +
drivers/pci/pci-uclass.c | 9 ++---
2 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index b2b7b253f8..02c34077e2 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -54,6 +54,19 @@ config PCI_REGION_MULTI_ENTRY
region type. This helps to add support for SoC's like OcteonTX/TX2
where every peripheral is on the PCI bus.
+config PCI_MAP_SYSTEM_MEMORY
+ bool "Map local system memory from a virtual base address"
+ depends on PCI || DM_PCI
+ depends on MIPS
+ default n
+ help
+ Say Y if base address of system memory is being used as a virtual
address
+ instead of a physical address (e.g. on MIPS). The PCI core will then
remap
+ the virtual memory base address to a physical address when adding the
PCI
+ region of type PCI_REGION_SYS_MEMORY.
+ This should only be required on MIPS where CONFIG_SYS_SDRAM_BASE is
still
+ being used as virtual address.
+
config PCI_SRIOV
bool "Enable Single Root I/O Virtualization support for PCI"
depends on PCI || DM_PCI
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 22a033e632..1e2ed5426e 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -998,10 +998,13 @@ static void decode_regions(struct pci_controller *hose,
ofnode parent_node,
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
+ phys_addr_t start = bd->bi_dram[i].start;
+
+ if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
+ start = virt_to_phys((void
*)(uintptr_t)bd->bi_dram[i].start);
+
pci_set_region(hose->regions + hose->region_count++,
- bd->bi_dram[i].start,
- bd->bi_dram[i].start,
- bd->bi_dram[i].size,
+ start, start, bd->bi_dram[i].size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
}
}
--
2.32.0
[PATCH 2/6] pci: gt64120: convert to driver model
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
---
drivers/pci/pci_gt64120.c | 72 ++-
1 file changed, 71 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index 80f11fedd1..973815928b 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -8,7 +8,7 @@
*Maciej W. Rozycki
*/
-#include
+#include
#include
#include
#include
@@ -114,6 +114,7 @@ static int gt_config_access(struct gt64120_pci_controller
*gt,
return 0;
}
+#if !IS_ENABLED(CONFIG_DM_PCI)
static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
@@ -175,3 +176,72 @@ void gt64120_pci_init(void *regs, unsigned long sys_bus,
unsigned long sys_phys,
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}
+#else
+static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong *val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, )) {
+ *val = pci_get_ff(size);
+ return 0;
+ }
+
+ *val = pci_conv_32_to_size(data, where, size);
+ return 0;
+}
+
+static int gt64120_pci_write_config(struct udevice *dev, pci_dev_t bdf,
+ uint where, ulong val,
+ enum pci_size_t size)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+ u32 data = 0;
+
+ if (size == PCI_SIZE_32) {
+ data = val;
+ } else {
+ u32 old;
+
+ if (gt_config_access(gt, PCI_ACCESS_READ, bdf, where, ))
+ return 0;
+
+ data = pci_conv_size_to_32(old, val, where, size);
+ }
+
+ gt_config_access(gt, PCI_ACCESS_WRITE, bdf, where, );
+ return 0;
+}
+
+static int gt64120_pci_probe(struct udevice *dev)
+{
+ struct gt64120_pci_controller *gt = dev_get_priv(dev);
+
+ gt->regs = dev_remap_addr(dev);
+ if (!gt->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_pci_ops gt64120_pci_ops = {
+ .read_config= gt64120_pci_read_config,
+ .write_config = gt64120_pci_write_config,
+};
+
+static const struct udevice_id gt64120_pci_ids[] = {
+ { .compatible = "marvell,pci-gt64120" },
+ { }
+};
+
+U_BOOT_DRIVER(gt64120_pci) = {
+ .name = "gt64120_pci",
+ .id = UCLASS_PCI,
+ .of_match = gt64120_pci_ids,
+ .ops= _pci_ops,
+ .probe = gt64120_pci_probe,
+ .priv_auto = sizeof(struct gt64120_pci_controller),
+};
+#endif
--
2.32.0
[PATCH 0/6] Convert MIPS Malta boards to PCI DM
This series converts the PCI host controller drivers used by MIPS Malta and the board-specific PCI setup code to PCI driver model. Because the AMD PCNET driver is already converted to ETH driver model, simply enable CONFIG_DM_ETH as well. A patch in PCI uclass core is currently required for MIPS wanting to use PCI DM (except Octeon MIPS64) due to CONFIG_SYS_SDRAM_BASE being used as a virtual address on all MIPS boards. The series for now is only tested with Qemu and the GT64120 PCI controller. The Malta Qemu tests are already covered by U-Boot CI Support for the MSC01 controller is prepared. The used PCI controller depends on the plugged core card (Qemu emulates the CoreLV card with GT64120). Dynamic selection of the according PCI DT nodes via CONFIG_OF_BOARD_FIXUP is prepared but not yet enabled. This requires fixing of the call order of fix_fdt() in board_init_f, otherwise the passed-in rw_fdt_blob pointer will point to a read-only NOR flash address. I'll send a separate RFC patch for this. I'll send a cleanup series for removing non-DM code after the merge windows has closed and the PCI DM conversion deadline has been enforced. Daniel Schwierzeck (6): dm: pci: add option to map virtual system memory base address pci: gt64120: convert to driver model pci: msc01: convert to driver model MIPS: malta: add DT bindings for PCI host controller MIPS: malta: add support for PCI driver model MIPS: malta: enable PCI driver model arch/mips/Kconfig | 4 ++ arch/mips/dts/mti,malta.dts | 28 + board/imgtec/malta/malta.c | 84 - drivers/pci/Kconfig | 13 ++ drivers/pci/pci-uclass.c| 9 ++-- drivers/pci/pci_gt64120.c | 72 ++- drivers/pci/pci_msc01.c | 70 ++- 7 files changed, 274 insertions(+), 6 deletions(-) -- 2.32.0
Re: [PATCH] net: Remove ne2000 driver
Am Dienstag, den 25.05.2021, 11:54 -0400 schrieb Tom Rini: > With the last user of this driver removed, remove the driver. > > Signed-off-by: Tom Rini > --- > doc/README.ne2000 | 27 -- > drivers/net/8390.h| 124 -- > drivers/net/Makefile | 1 - > drivers/net/ne2000.c | 260 - > drivers/net/ne2000.h | 94 - > drivers/net/ne2000_base.c | 792 > -- > drivers/net/ne2000_base.h | 305 --- > 7 files changed, 1603 deletions(-) > delete mode 100644 doc/README.ne2000 > delete mode 100644 drivers/net/8390.h > delete mode 100644 drivers/net/ne2000.c > delete mode 100644 drivers/net/ne2000.h > delete mode 100644 drivers/net/ne2000_base.c > delete mode 100644 drivers/net/ne2000_base.h Reviewed-by: Daniel Schwierzeck There are still some references in config_whitelist.txt: $ git grep -in ne2000 -- scripts/config_whitelist.txt scripts/config_whitelist.txt:303:CONFIG_DRIVER_NE2000 scripts/config_whitelist.txt:304:CONFIG_DRIVER_NE2000_BASE -- - Daniel
[PULL] u-boot-mips
Hi Tom, please pull a minor bugfix for MIPS64 Octeon and the removal of qemu_mips boards. Gitlab: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/7625 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=24=results The following changes since commit e1bf0336a58cfe873a34c36ff53e5e3806f2d263: Prepare v2021.07-rc3 (2021-05-24 20:53:13 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2021-05-25 for you to fetch changes up to 835b4fdf3bf5ec778e1fb7610f00707754454974: doc: update and fix Qemu MIPS documentation (2021-05-25 15:35:06 +0200) - MIPS: octeon: fix CFI flash setup - MIPS: remove qemu_mips boards Daniel Schwierzeck (2): MIPS: remove deprecated qemu_mips board doc: update and fix Qemu MIPS documentation Stefan Roese (1): mips: octeon: octeon_ebb7304_defconfig: Fix CFI flash setup .azure-pipelines.yml | 12 -- .gitlab-ci.yml| 24 arch/mips/Kconfig | 11 -- board/qemu-mips/Kconfig | 26 board/qemu-mips/MAINTAINERS | 14 -- board/qemu-mips/Makefile | 7 - board/qemu-mips/lowlevel_init.S | 40 -- board/qemu-mips/qemu-mips.c | 85 configs/octeon_ebb7304_defconfig | 5 +- configs/qemu_mips64_defconfig | 29 configs/qemu_mips64el_defconfig | 30 - configs/qemu_mips_defconfig | 27 configs/qemu_mipsel_defconfig | 28 doc/board/emulation/qemu-mips.rst | 273 +++--- include/configs/qemu-mips.h | 89 - include/configs/qemu-mips64.h | 89 - scripts/config_whitelist.txt | 1 - 17 files changed, 81 insertions(+), 709 deletions(-) delete mode 100644 board/qemu-mips/Kconfig delete mode 100644 board/qemu-mips/MAINTAINERS delete mode 100644 board/qemu-mips/Makefile delete mode 100644 board/qemu-mips/lowlevel_init.S delete mode 100644 board/qemu-mips/qemu-mips.c delete mode 100644 configs/qemu_mips64_defconfig delete mode 100644 configs/qemu_mips64el_defconfig delete mode 100644 configs/qemu_mips_defconfig delete mode 100644 configs/qemu_mipsel_defconfig delete mode 100644 include/configs/qemu-mips.h delete mode 100644 include/configs/qemu-mips64.h
Re: [PATCH 06/27] mips: Remove malta boards
Hi Tom, Am Freitag, den 14.05.2021, 21:34 -0400 schrieb Tom Rini: > These boards have not been converted to CONFIG_DM_PCI by the > deadline. > Remove them. > > Cc: Paul Burton > Cc: Daniel Schwierzeck > Signed-off-by: Tom Rini > --- > As I hope these boards will get converted quickly I've not removed > all > of the other references to Malta and the associated PCI host > controller > drivers. it is not trivial to convert Malta and Paul is not involved with any MIPS anymore since 2019. I have this on my todo list for over one year but didn't find time ;) But Malta is rather important because it is the reference board for MIPS Qemu. It's also important for U-Boot CI due to build coverage for LE/BE and 32/64 bit and Qemu tests. The qemu_mips board also used for CI is deprecated and I definitely won't convert that. In fact I already sent patches to remove it with this release. Anyway I started to convert things and made good progress. But I need some more days to finish and test. When do you plan to apply the removal patch series? -- - Daniel
Re: [RFC 4/7] pinctrl: mscc: Fix multiple definition error
Am Montag, den 03.05.2021, 16:48 -0400 schrieb Tom Rini: > With gcc-11 we get a multiple errors here as the declarations for > mscc_pinctrl_ops and mscc_gpio_ops are missing an extern. > > CC: Gregory CLEMENT > Cc: Lars Povlsen > Cc: Horatiu Vultur > Signed-off-by: Tom Rini > --- > drivers/pinctrl/mscc/mscc-common.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Daniel Schwierzeck -- Daniel
Re: [PATCH] pinctrl: mscc: fix multiple definitions
Am Dienstag, den 04.05.2021, 14:45 -0400 schrieb Tom Rini: > On Tue, May 04, 2021 at 08:40:40PM +0200, Daniel Schwierzeck wrote: > > > gcc-11 complains about multiple definitions: > > > > /opt/gcc-11.0.20210426-nolibc/mips-linux/bin/mips-linux-ld.bfd: > > drivers/pinctrl/mscc/pinctrl-ocelot.o:drivers/pinctrl/mscc/mscc- > > common.h:64: multiple definition of `mscc_pinctrl_ops'; > > drivers/pinctrl/mscc/mscc-common.o:drivers/pinctrl/mscc/mscc- > > common.h:64: first defined here > > /opt/gcc-11.0.20210426-nolibc/mips-linux/bin/mips-linux-ld.bfd: > > drivers/pinctrl/mscc/pinctrl-ocelot.o:drivers/pinctrl/mscc/mscc- > > common.h:66: multiple definition of `mscc_gpio_ops'; > > drivers/pinctrl/mscc/mscc-common.o:drivers/pinctrl/mscc/mscc- > > common.h:66: first defined here > > > > mscc_pinctrl_ops and mscc_gpio_ops are instantiated in mscc- > > common.c and > > just referenced by SoC specific pinctrl drivers. Annotate the > > exports > > in mscc-common.h with `extern` to avoid creating new instances > > when including mscc-common.h. > > > > Signed-off-by: Daniel Schwierzeck > > I posted this yesterday as part of: > https://patchwork.ozlabs.org/project/uboot/list/?series=241916=* > BTW. okay, I only saw your patch 7/7 in my inbox ;) -- - Daniel
[PATCH] pinctrl: mscc: fix multiple definitions
gcc-11 complains about multiple definitions: /opt/gcc-11.0.20210426-nolibc/mips-linux/bin/mips-linux-ld.bfd: drivers/pinctrl/mscc/pinctrl-ocelot.o:drivers/pinctrl/mscc/mscc-common.h:64: multiple definition of `mscc_pinctrl_ops'; drivers/pinctrl/mscc/mscc-common.o:drivers/pinctrl/mscc/mscc-common.h:64: first defined here /opt/gcc-11.0.20210426-nolibc/mips-linux/bin/mips-linux-ld.bfd: drivers/pinctrl/mscc/pinctrl-ocelot.o:drivers/pinctrl/mscc/mscc-common.h:66: multiple definition of `mscc_gpio_ops'; drivers/pinctrl/mscc/mscc-common.o:drivers/pinctrl/mscc/mscc-common.h:66: first defined here mscc_pinctrl_ops and mscc_gpio_ops are instantiated in mscc-common.c and just referenced by SoC specific pinctrl drivers. Annotate the exports in mscc-common.h with `extern` to avoid creating new instances when including mscc-common.h. Signed-off-by: Daniel Schwierzeck --- drivers/pinctrl/mscc/mscc-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mscc/mscc-common.h b/drivers/pinctrl/mscc/mscc-common.h index 3c5c1faf84..9eb1321f89 100644 --- a/drivers/pinctrl/mscc/mscc-common.h +++ b/drivers/pinctrl/mscc/mscc-common.h @@ -61,6 +61,6 @@ int mscc_pinctrl_probe(struct udevice *dev, int num_func, const struct mscc_pin_data *mscc_pins, int num_pins, char * const *function_names, const unsigned long *mscc_gpios); -const struct pinctrl_ops mscc_pinctrl_ops; -const struct dm_gpio_ops mscc_gpio_ops; +extern const struct pinctrl_ops mscc_pinctrl_ops; +extern const struct dm_gpio_ops mscc_gpio_ops; -- 2.31.1
Re: [PATCH] mips: octeon: octeon_ebb7304_defconfig: Fix CFI flash setup
Am Montag, den 26.04.2021, 16:43 +0200 schrieb Stefan Roese: > This patch makes the necessary adjustments in the defconfig to fully > support the CFI flash on the Octeon EBB7304. > > Signed-off-by: Stefan Roese > Cc: Aaron Williams > Cc: Chandrakala Chavva > Cc: Daniel Schwierzeck > --- > configs/octeon_ebb7304_defconfig | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > applied to u-boot-mips, thanks. -- - Daniel
Re: [PATCH v1 00/15] mips: octeon: MIPS Octeon misc updates: NIC23, AHCI, serial-remote tools etc
Am Mittwoch, den 07.04.2021, 09:12 +0200 schrieb Stefan Roese: > This patchset adds the following updates / fixes for Marvell MIPS > Octeon: > - MIPS Octeon NIC23 base support > - Add serial_octeon_pcie_console to support the Marvell remote tool > "oct-remote-console" > - Add serial_octeon_bootcmd to support the Marvell remote tools > "oct-remote-load" & "oct-remote-bootcmd" > - Fix AHCI driver to support big-endian platforms > - Misc minor updates & fixes to the MIPS Octeon platform code > - EBB7304: Enable USB storage support > - EBB7304: Add I2C support (devices & commands) > > This patchset requires the MIPS Octeon serdes & PCIe patchset which > was > posted to the list 2020-12-11. > > Thanks, > Stefan > > > Aaron Williams (2): > mips: octeon: dts/dtsi: Change UART DT node to use clocks property > mips: octeon: ebb7304: Add support for some I2C devices > > Stefan Roese (13): > mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h > mips: octeon: cvmx-bootmem: Fix compare in "if" statement > mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with > DEBUG > defined > serial: serial_octeon_pcie_console.c: Add PCI remote console > support > serial: serial_octeon_bootcmd.c: Add PCI remote console support > mips: octeon: cpu.c: Add arch_misc_init() for pci-console & > pci-bootcmd > mips: octeon: cpu.c: Enable AHCI/SATA support > sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon > ata: ahci: Fix usage on big-endian platforms > scsi: Add ata_swap_buf_le16() to support big-endian platforms > mips: octeon: mrvl,cn73xx.dtsi: Add AHCI/SATA DT node > mips: octeon: Add Octeon III NIC23 board support > mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support series applied to u-boot-mips, thanks. > > arch/mips/dts/Makefile| 1 + > arch/mips/dts/mrvl,cn73xx.dtsi| 21 + > arch/mips/dts/mrvl,octeon-ebb7304.dts | 15 +- > arch/mips/dts/mrvl,octeon-nic23.dts | 162 > arch/mips/mach-octeon/Kconfig | 7 + > arch/mips/mach-octeon/cpu.c | 348 > - > arch/mips/mach-octeon/cvmx-bootmem.c | 4 +- > .../mach-octeon/include/mach/cvmx-coremask.h | 5 +- > .../mips/mach-octeon/include/mach/cvmx-regs.h | 1 + > .../mach-octeon/include/mach/octeon_ddr.h | 2 - > board/Marvell/octeon_nic23/Kconfig| 19 + > board/Marvell/octeon_nic23/MAINTAINERS| 7 + > board/Marvell/octeon_nic23/Makefile | 8 + > board/Marvell/octeon_nic23/board.c| 106 + > board/Marvell/octeon_nic23/board_ddr.h| 269 + > configs/octeon_ebb7304_defconfig | 9 +- > configs/octeon_nic23_defconfig| 70 > drivers/ata/Kconfig | 2 +- > drivers/ata/ahci.c| 23 +- > drivers/ata/ahci_mvebu.c | 3 +- > drivers/scsi/scsi.c | 6 + > drivers/serial/Kconfig| 24 ++ > drivers/serial/Makefile | 2 + > drivers/serial/serial_octeon_bootcmd.c| 182 + > drivers/serial/serial_octeon_pcie_console.c | 365 > ++ > include/configs/octeon_nic23.h| 21 + > 26 files changed, 1656 insertions(+), 26 deletions(-) > create mode 100644 arch/mips/dts/mrvl,octeon-nic23.dts > create mode 100644 board/Marvell/octeon_nic23/Kconfig > create mode 100644 board/Marvell/octeon_nic23/MAINTAINERS > create mode 100644 board/Marvell/octeon_nic23/Makefile > create mode 100644 board/Marvell/octeon_nic23/board.c > create mode 100644 board/Marvell/octeon_nic23/board_ddr.h > create mode 100644 configs/octeon_nic23_defconfig > create mode 100644 drivers/serial/serial_octeon_bootcmd.c > create mode 100644 drivers/serial/serial_octeon_pcie_console.c > create mode 100644 include/configs/octeon_nic23.h > -- - Daniel
Re: [PATCH v1 00/50] mips: octeon: Add serdes and device helper support incl. DM PCIe driver
Am Freitag, den 11.12.2020, 17:05 +0100 schrieb Stefan Roese: > This patchset adds the serdes and (mostly networking) device helper > macros and functions, needed to support the still missing Octeon II / > III devices in mainline U-Boot. > > Please excuse the massive amount of files in this patch series. Also > the > sometimes huge files (mostly headers with register definitions) that > I > needed to include. > > The infrastructure code with all the headers is ported without any > intended functional changes from the 2013 Cavium / Marvell U-Boot > version. It has undergone many hours of extensive code cleanup and > reformatting. Some of it done by using tools (checkpatch, Lindent, > clang > format etc) and also some of it done manually, as I couldn't find > some > tools that could do the needed work in a reliable and functional way. > The result is that checkpatch now only throws a "few" warnings that > are > left. Some of those can't be removed without an even more extensive > cleanup / rewrite of the code, like the addition of typedefs. > > The added headers and helper functions will be used by the upcoming > support for the Octeon II / III networking drivers, including PHY & > switch support. It was not easily possible to split these > infrastructure > files into a separate patchset, as it is heavily interconnected in > the > common QLM/DLM serdes interface initialization. The result is, that > the > upcoming ethernet driver support will be much smaller (this is at > least > my current assumption). > > The added PCIe RC support with the included DM PCIe driver is the > first > driver making use of this Octeon serdes infrastructure. This has been > tested with an Intel E1000 PCIe network card in the Octeon 7304 EBB. > > Thanks, > Stefan > series applied to u-boot-mips, thanks. > > Aaron Williams (42): > mips: octeon: Add misc cvmx-helper header files > mips: octeon: Add cvmx-agl-defs.h header file > mips: octeon: Add cvmx-asxx-defs.h header file > mips: octeon: Add cvmx-bgxx-defs.h header file > mips: octeon: Add cvmx-ciu-defs.h header file > mips: octeon: Add cvmx-dbg-defs.h header file > mips: octeon: Add cvmx-dpi-defs.h header file > mips: octeon: Add cvmx-dtx-defs.h header file > mips: octeon: Add cvmx-fpa-defs.h header file > mips: octeon: Add cvmx-gmxx-defs.h header file > mips: octeon: Add cvmx-gserx-defs.h header file > mips: octeon: Add cvmx-ipd-defs.h header file > mips: octeon: Add cvmx-l2c-defs.h header file > mips: octeon: Add cvmx-mio-defs.h header file > mips: octeon: Add cvmx-npi-defs.h header file > mips: octeon: Add cvmx-pcieepx-defs.h header file > mips: octeon: Add cvmx-pciercx-defs.h header file > mips: octeon: Add cvmx-pcsx-defs.h header file > mips: octeon: Add cvmx-pemx-defs.h header file > mips: octeon: Add cvmx-pepx-defs.h header file > mips: octeon: Add cvmx-pip-defs.h header file > mips: octeon: Add cvmx-pki-defs.h header file > mips: octeon: Add cvmx-pko-defs.h header file > mips: octeon: Add cvmx-pow-defs.h header file > mips: octeon: Add cvmx-rst-defs.h header file > mips: octeon: Add cvmx-sata-defs.h header file > mips: octeon: Add cvmx-sli-defs.h header file > mips: octeon: Add cvmx-smix-defs.h header file > mips: octeon: Add cvmx-sriomaintx-defs.h header file > mips: octeon: Add cvmx-sriox-defs.h header file > mips: octeon: Add cvmx-sso-defs.h header file > mips: octeon: Add misc remaining header files > mips: octeon: Add cvmx-helper-cfg.c > mips: octeon: Add cvmx-helper-fdt.c > mips: octeon: Add cvmx-helper-jtag.c > mips: octeon: Add cvmx-helper-util.c > mips: octeon: Add cvmx-helper.c > mips: octeon: Add cvmx-pcie.c > mips: octeon: Add cvmx-qlm.c > mips: octeon: Add octeon_fdt.c > mips: octeon: Add octeon_qlm.c > mips: octeon: octeon_ebb7304: Add board specific QLM init code > > Stefan Roese (8): > mips: global_data.h: Add Octeon specific data to arch_global_data > struct > mips: octeon: Misc changes required because of the newly added > headers > mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to mach > mips: octeon: Makefile: Enable building of the newly added C files > mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT > mips: octeon: mrvl,cn73xx.dtsi: Add PCIe controller DT node > mips: octeon: Add Octeon PCIe host controller driver > mips: octeon: octeon_ebb7304_defconfig: Enable Octeon PCIe and > E1000 > > arch/mips/dts/mrvl,cn73xx.dtsi| 16 + > arch/mips/include/asm/global_data.h |9 + > arch/mips/mach-octeon/Kconfig |4 + > arch/mips/mach-octeon/Makefile| 11 + > arch/mips/mach-octeon/bootoctlinux.c |1 + > arch/mips/mach-octeon/cvmx-bootmem.c |6 - > arch/mips/mach-octeon/cvmx-coremask.c |1 + > arch/mips/mach-octeon/cvmx-helper-cfg.c | 1914 > arch/mips/mach-octeon/cvmx-helper-fdt.c | 970 ++ >
[PULL] u-boot-mips
Hi Tom, please pull some major updates and minor fixes for MIPS Octeon III. The changeset is quite large because all support for PCI-E, SGMII, SATA etc. depends on the Octeon QLM (Quad Lane Modules) controller which needs to be configured and tuned for each mode and that configuration is quite complex but already required in U-Boot. Stefan ensured me that the code is already massively stripped down to the minimum required parts. Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/7291 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=23=results The following changes since commit 91ce06ad340ef12fc3fd0ee3a5d040cc0bba731e: mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support (2021-04-22 03:02:37 +0200) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2021-04-24 for you to fetch changes up to b1d9554e058e5e8510a9d22183ae8321290ee87b: mips: octeon: ebb7304: Add support for some I2C devices (2021-04-23 21:23:30 +0200) - MIPS: octeon: fix minor bugs of initial merge - MIPS: octeon: add support for QLM and PCI-E controller - MIPS: octeon: add support for AHCI and SATA - MIPS: octeon: add E1000 ethernet support - MIPS: octeon: add Octeon III NIC23 board - ata/scsi: add support for Big Endian platforms Aaron Williams (44): mips: octeon: Add misc cvmx-helper header files mips: octeon: Add cvmx-agl-defs.h header file mips: octeon: Add cvmx-asxx-defs.h header file mips: octeon: Add cvmx-bgxx-defs.h header file mips: octeon: Add cvmx-ciu-defs.h header file mips: octeon: Add cvmx-dbg-defs.h header file mips: octeon: Add cvmx-dpi-defs.h header file mips: octeon: Add cvmx-dtx-defs.h header file mips: octeon: Add cvmx-fpa-defs.h header file mips: octeon: Add cvmx-gmxx-defs.h header file mips: octeon: Add cvmx-gserx-defs.h header file mips: octeon: Add cvmx-ipd-defs.h header file mips: octeon: Add cvmx-l2c-defs.h header file mips: octeon: Add cvmx-mio-defs.h header file mips: octeon: Add cvmx-npi-defs.h header file mips: octeon: Add cvmx-pcieepx-defs.h header file mips: octeon: Add cvmx-pciercx-defs.h header file mips: octeon: Add cvmx-pcsx-defs.h header file mips: octeon: Add cvmx-pemx-defs.h header file mips: octeon: Add cvmx-pepx-defs.h header file mips: octeon: Add cvmx-pip-defs.h header file mips: octeon: Add cvmx-pki-defs.h header file mips: octeon: Add cvmx-pko-defs.h header file mips: octeon: Add cvmx-pow-defs.h header file mips: octeon: Add cvmx-rst-defs.h header file mips: octeon: Add cvmx-sata-defs.h header file mips: octeon: Add cvmx-sli-defs.h header file mips: octeon: Add cvmx-smix-defs.h header file mips: octeon: Add cvmx-sriomaintx-defs.h header file mips: octeon: Add cvmx-sriox-defs.h header file mips: octeon: Add cvmx-sso-defs.h header file mips: octeon: Add misc remaining header files mips: octeon: Add cvmx-helper-cfg.c mips: octeon: Add cvmx-helper-fdt.c mips: octeon: Add cvmx-helper-jtag.c mips: octeon: Add cvmx-helper-util.c mips: octeon: Add cvmx-helper.c mips: octeon: Add cvmx-pcie.c mips: octeon: Add cvmx-qlm.c mips: octeon: Add octeon_fdt.c mips: octeon: Add octeon_qlm.c mips: octeon: octeon_ebb7304: Add board specific QLM init code mips: octeon: dts/dtsi: Change UART DT node to use clocks property mips: octeon: ebb7304: Add support for some I2C devices Stefan Roese (20): mips: global_data.h: Add Octeon specific data to arch_global_data struct mips: octeon: Misc changes required because of the newly added headers mips: octeon: Move cvmx-lmcx-defs.h from mach/cvmx to mach mips: octeon: Makefile: Enable building of the newly added C files mips: octeon: Kconfig: Enable CONFIG_SYS_PCI_64BIT mips: octeon: mrvl, cn73xx.dtsi: Add PCIe controller DT node mips: octeon: Add Octeon PCIe host controller driver mips: octeon: octeon_ebb7304_defconfig: Enable Octeon PCIe and E1000 mips: octeon: Move CVMX_SYNC from octeon_ddr.h to cvmx-regs.h mips: octeon: cvmx-bootmem: Fix compare in "if" statement mips: octeon: cvmx-coremask.h: Fix cvmx_coremask_dprint() with DEBUG defined serial: serial_octeon_pcie_console.c: Add PCI remote console support serial: serial_octeon_bootcmd.c: Add PCI remote console support mips: octeon: cpu.c: Add arch_misc_init() for pci-console & pci-bootcmd mips: octeon: cpu.c: Enable AHCI/SATA support sata: ahci_mvebu.c: Enable AHCI/SATA driver for MIPS Octeon ata: ahci: Fix usage on big-endian platforms scsi: Add ata_swap_buf_le16() to support
[PULL] u-boot-mips
Hi Tom, please pull some updates and fixes for MIPS. Gitlab CI: https://source.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/7255 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=22=results The following changes since commit 842d049be23976ebcbb2522fa8d752d3aae8631a: Merge branch '2021-04-20-assorted-improvements' (2021-04-20 07:32:04 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-mips.git/ tags/mips-pull-2021-04-22 for you to fetch changes up to 91ce06ad340ef12fc3fd0ee3a5d040cc0bba731e: mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support (2021-04-22 03:02:37 +0200) - net: fix traffic problems in MSCC Jaguar 2 network driver - MIPS: mt7628: fix DDR memory init - MIPS: octeon: add MMC and USB support Horatiu Vultur (2): net: jr2: Reset switch net: jr2: Fix Serdes6G configuration Stefan Roese (5): mmc: octeontx_hsmmc: Add support for MIPS Octeon mips: octeon: mrvl,cn73xx.dtsi: Add MMC DT node mips: octeon: mrvl,octeon_ebb7304.dts: Add MMC DT node mips: octeon: octeon_ebb7304_defconfig: Enable MMC support mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support Weijie Gao (2): mips: mt7628: fix ddr_type for MT7688KN mips: mt7628: fix the displayed DDR type of mt7628 arch/mips/dts/mrvl,cn73xx.dtsi | 27 + arch/mips/dts/mrvl,octeon-ebb7304.dts | 57 ++ arch/mips/dts/mscc,jr2.dtsi| 6 +- arch/mips/mach-mtmips/mt7628/ddr.c | 6 +- arch/mips/mach-mtmips/mt7628/init.c| 3 + .../mach-octeon/include/mach/cvmx-mio-emm-defs.h | 614 + configs/octeon_ebb7304_defconfig | 13 +- drivers/mmc/Kconfig| 10 +- drivers/mmc/octeontx_hsmmc.c | 195 +-- drivers/net/mscc_eswitch/jr2_switch.c | 43 +- 10 files changed, 906 insertions(+), 68 deletions(-) create mode 100644 arch/mips/mach-octeon/include/mach/cvmx-mio-emm-defs.h
Re: [PATCH] mips: octeon: octeon_ebb7304_defconfig: Enable USB storage support
Am Freitag, den 19.02.2021, 14:02 +0100 schrieb Stefan Roese: > This patch enables USB storage support with the necessary partition > support on the MIPS Octeon EBB7304. > > Signed-off-by: Stefan Roese > Cc: Aaron Williams > Cc: Chandrakala Chavva > --- > configs/octeon_ebb7304_defconfig | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > applied to u-boot-mips, thanks. -- - Daniel
Re: [PATCH] mips: mt7628: fix the displayed DDR type of mt7628
Am Freitag, den 05.03.2021, 11:13 +0800 schrieb Weijie Gao: > The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR > type > from bootstrap register must be ignored, and always be assumed as > DDR1. > > This patch fixes the displayed DDR type of mt7628. > > Signed-off-by: Weijie Gao > --- > arch/mips/mach-mtmips/mt7628/init.c | 3 +++ > 1 file changed, 3 insertions(+) > applied to u-boot-mips, thanks. -- - Daniel
Re: [PATCH] mips: mt7628: fix ddr_type for MT7688KN
Am Dienstag, den 23.02.2021, 15:12 +0800 schrieb Weijie Gao: > The MT7688KN is a multi-chip package with 8MiB DDR1 KGD. So the DDR > type > from bootstrap register must be ignored, and always be assumed as > DDR1. > > This patch fixes an issue that mt7628_ddr_pad_ldo_config() may be > passed > with a wrong ddr_type in MT7688KN. > > Signed-off-by: Weijie Gao > --- > arch/mips/mach-mtmips/mt7628/ddr.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > applied to u-boot-mips, thanks. -- - Daniel
Re: [PATCH 0/2] net: jr2: Fix for jr2 switch
Am Mittwoch, den 10.03.2021, 09:31 +0100 schrieb Horatiu Vultur: > This patch series contains two patches. The first patch resets the > switch at probe time while the second one fixes an issue with the > serdes6g configuration which is used on jr2_pcb111 board > > Horatiu Vultur (2): > net: jr2: Reset switch > net: jr2: Fix Serdes6G configuration > > arch/mips/dts/mscc,jr2.dtsi | 6 ++-- > drivers/net/mscc_eswitch/jr2_switch.c | 43 +++ > > 2 files changed, 42 insertions(+), 7 deletions(-) > applied to u-boot-mips, thanks. -- - Daniel
[PATCH 1/2] MIPS: remove deprecated qemu_mips board
Remove qemu_mips boards because DM migration doesn't make sense. The board support for qemu_mips is already marked as deprecated in Qemu in favour of the Malta board. Also qemu_mips support has been removed from Linux a long time ago. The official replacement is the Malta board. The same Malta U-Boot image can be used with Qemu and on physical hardware. All combinations of Big Endian and Little Endian as well as 32 bit and 64 bit are supported. Signed-off-by: Daniel Schwierzeck --- .azure-pipelines.yml| 12 - .gitlab-ci.yml | 24 - arch/mips/Kconfig | 11 board/qemu-mips/Kconfig | 26 -- board/qemu-mips/MAINTAINERS | 14 -- board/qemu-mips/Makefile| 7 --- board/qemu-mips/lowlevel_init.S | 40 --- board/qemu-mips/qemu-mips.c | 85 --- configs/qemu_mips64_defconfig | 29 --- configs/qemu_mips64el_defconfig | 30 --- configs/qemu_mips_defconfig | 27 -- configs/qemu_mipsel_defconfig | 28 --- include/configs/qemu-mips.h | 89 - include/configs/qemu-mips64.h | 89 - scripts/config_whitelist.txt| 1 - 15 files changed, 512 deletions(-) delete mode 100644 board/qemu-mips/Kconfig delete mode 100644 board/qemu-mips/MAINTAINERS delete mode 100644 board/qemu-mips/Makefile delete mode 100644 board/qemu-mips/lowlevel_init.S delete mode 100644 board/qemu-mips/qemu-mips.c delete mode 100644 configs/qemu_mips64_defconfig delete mode 100644 configs/qemu_mips64el_defconfig delete mode 100644 configs/qemu_mips_defconfig delete mode 100644 configs/qemu_mipsel_defconfig delete mode 100644 include/configs/qemu-mips.h delete mode 100644 include/configs/qemu-mips64.h diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index d176e045e1..cb482063cc 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -205,18 +205,6 @@ jobs: qemu_arm64: TEST_PY_BD: "qemu_arm64" TEST_PY_TEST_SPEC: "not sleep" -qemu_mips: - TEST_PY_BD: "qemu_mips" - TEST_PY_TEST_SPEC: "not sleep" -qemu_mipsel: - TEST_PY_BD: "qemu_mipsel" - TEST_PY_TEST_SPEC: "not sleep" -qemu_mips64: - TEST_PY_BD: "qemu_mips64" - TEST_PY_TEST_SPEC: "not sleep" -qemu_mips64el: - TEST_PY_BD: "qemu_mips64el" - TEST_PY_TEST_SPEC: "not sleep" qemu_malta: TEST_PY_BD: "malta" TEST_PY_ID: "--id qemu" diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 51bd64308a..469992f69e 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -225,30 +225,6 @@ qemu_arm64 test.py: TEST_PY_TEST_SPEC: "not sleep" <<: *buildman_and_testpy_dfn -qemu_mips test.py: - variables: -TEST_PY_BD: "qemu_mips" -TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu_mipsel test.py: - variables: -TEST_PY_BD: "qemu_mipsel" -TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu_mips64 test.py: - variables: -TEST_PY_BD: "qemu_mips64" -TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - -qemu_mips64el test.py: - variables: -TEST_PY_BD: "qemu_mips64el" -TEST_PY_TEST_SPEC: "not sleep" - <<: *buildman_and_testpy_dfn - qemu_malta test.py: variables: TEST_PY_BD: "malta" diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 77f563e98e..e54801673b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -12,16 +12,6 @@ choice prompt "Target select" optional -config TARGET_QEMU_MIPS - bool "Support qemu-mips" - select ROM_EXCEPTION_VECTORS - select SUPPORTS_BIG_ENDIAN - select SUPPORTS_CPU_MIPS32_R1 - select SUPPORTS_CPU_MIPS32_R2 - select SUPPORTS_CPU_MIPS64_R1 - select SUPPORTS_CPU_MIPS64_R2 - select SUPPORTS_LITTLE_ENDIAN - config TARGET_MALTA bool "Support malta" select DM @@ -174,7 +164,6 @@ endchoice source "board/imgtec/boston/Kconfig" source "board/imgtec/malta/Kconfig" source "board/imgtec/xilfpga/Kconfig" -source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig deleted file mode 100644 index e696a12192..00 --- a/board/qemu-mips/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -if TARGET_QEMU_MIPS - -config SYS_BOARD - default "qemu-mips" - -config SYS_CONFIG_NAME - default
[PATCH 2/2] doc: update and fix Qemu MIPS documentation
Update description to use the MIPS Malta board for Qemu.
Signed-off-by: Daniel Schwierzeck
---
doc/board/emulation/qemu-mips.rst | 273 +-
1 file changed, 78 insertions(+), 195 deletions(-)
diff --git a/doc/board/emulation/qemu-mips.rst
b/doc/board/emulation/qemu-mips.rst
index d35925126a..5fd8a0a23b 100644
--- a/doc/board/emulation/qemu-mips.rst
+++ b/doc/board/emulation/qemu-mips.rst
@@ -1,246 +1,129 @@
.. SPDX-License-Identifier: GPL-2.0+
-.. sectionauthor:: Vlad Lungu
+.. sectionauthor:: Daniel Schwierzeck
QEMU MIPS
=
-Qemu is a full system emulator. See http://www.nongnu.org/qemu/
+Qemu for MIPS is based on the MIPS Malta board. The built Malta U-Boot
+images can be used for Qemu and on physical hardware. The Malta board
+supports all combinations of Little and Big Endian as well as 32 bit
+and 64 bit.
Limitations & comments
--
-Supports the "-M mips" configuration of qemu: serial,NE2000,IDE.
-Supports little and big endian as well as 32 bit and 64 bit.
-Derived from au1x00 with a lot of things cut out.
-
-Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
-recent qemu versions. When using emulated flash, launch with
--pflash and erase mips_bios.bin.
-
-
-Notes for the Qemu MIPS port
-
+The memory size for Qemu is hard-coded to 256 MiB. For Malta Little Endian
+targets an extra endianness swapped image named *u-boot-swap.bin* is
+generated and required for Qemu.
Example usage
-^
-
-Using u-boot.bin as ROM (replaces Qemu monitor):
+-
-32 bit, big endian
+Build for 32 bit, big endian:
.. code-block:: bash
- make qemu_mips_defconfig
- qemu-system-mips -M mips -bios u-boot.bin -nographic
+ make malta_defconfig
+ make
+ UBOOT_BIN=u-boot.bin
+ QEMU_BIN=qemu-system-mips
+ QEMU_CPU=24Kc
-32 bit, little endian
+Build for 32 bit, little endian:
.. code-block:: bash
- make qemu_mipsel_defconfig
- qemu-system-mipsel -M mips -bios u-boot.bin -nographic
+ make maltael_defconfig
+ make
+ UBOOT_BIN=u-boot-swap.bin
+ QEMU_BIN=qemu-system-mipsel
+ QEMU_CPU=24Kc
-64 bit, big endian
+Build for 64 bit, big endian:
.. code-block:: bash
- make qemu_mips64_defconfig
- qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
+ make malta64_defconfig
+ make
+ UBOOT_BIN=u-boot.bin
+ QEMU_BIN=qemu-system-mips64
+ QEMU_CPU=MIPS64R2-generic
-64 bit, little endian
+Build for 64 bit, little endian:
.. code-block:: bash
- make qemu_mips64el_defconfig
- qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin
-nographic
+ make malta64el_defconfig
+ make
+ UBOOT_BIN=u-boot-swap.bin
+ QEMU_BIN=qemu-system-mips64el
+ QEMU_CPU=MIPS64R2-generic
-or using u-boot.bin from emulated flash:
-
-if you use a QEMU version after commit 4224
+Generate NOR flash image with U-Boot binary:
.. code-block:: bash
- # create image:
- dd of=flash bs=1k count=4k if=/dev/zero
- dd of=flash bs=1k conv=notrunc if=u-boot.bin
- # start it (see above):
- qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash
-nographic
-
-Download kernel + initrd
-
-
-On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
-you can downland::
+ dd if=/dev/zero bs=1M count=4 | tr '\000' '\377' > pflash.img
+ dd if=${UBOOT_BIN} of=pflash.img conv=notrunc
- #config to build the kernel
- qemu_mips_defconfig
- #patch to fix mips interrupt init on 2.6.24.y kernel
- qemu_mips_kernel.patch
- initrd.gz
- vmlinux
- vmlinux.bin
- System.map
-
-Generate uImage
-^^^
-
-.. code-block:: bash
-
- tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x8001 -e
0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
-
-Copy uImage to Flash
-
+Start Qemu:
.. code-block:: bash
- dd if=uImage bs=1k conv=notrunc seek=224 of=flash
-
-Generate Ide Disk
-^
+ mkdir tftproot
+ ${QEMU_BIN} -nographic -cpu ${QEMU_CPU} -m 256 -drive
if=pflash,file="$(pwd)/pflash.img",format=raw -netdev
user,id=net0,tftp="$(pwd)/tftproot" -device pcnet,netdev=net0
.. code-block:: bash
- dd of=ide bs=1k count=100k if=/dev/zero
+ U-Boot 2021.04-00963-g60279a2b1d (Apr 21 2021 - 19:54:32 +0200)
- # Create partion table
- sudo sfdisk ide << EOF
- label: dos
- label-id: 0x6fe3a999
- device: image
- unit: sectors
- image1 : start= 63, size=32067, Id=83
- image2 : start=32130, size=32130, Id=83
- image3 : start=64260, size= 4128705, Id=83
- EOF
+ Board: MIPS Malta CoreLV
+ DRAM: 256 MiB
+ Flash: 4 MiB
+ Loading Environment from Flash... *** Warning - bad CRC, using default
environment
-Copy to ide
-^^^
+ In:serial@3f8
+ Out: serial@3f8
+ Err: serial@3f8
+ Net: pcnet#0
+ IDE: Bus 0: not av
Re: Patches pending for review
Am Montag, den 15.03.2021, 21:24 + schrieb Aleksandar Gerasimovski: > Hi Folks, > > Hope you are all well! > > I guess you have verry busy times, but I have to ask about the state > of my last two patches on patchwork: > > https://patchwork.ozlabs.org/project/uboot/patch/vi1pr06mb402989c0efee6a5121437c68d2...@vi1pr06mb4029.eurprd06.prod.outlook.com/ > https://patchwork.ozlabs.org/project/uboot/patch/vi1pr06mb40297747ee7a342b4d3f0e2fd2...@vi1pr06mb4029.eurprd06.prod.outlook.com/ > > They are in same state since almost a month, and for me it looks like > they are forgotten. > Is it possible to get attention from some of you? Thanks in advance! I don't know why the patches were assigned to me and who did that. Also the patches were in state "Changes requested" so they were not visible in my patchwork inbox. Maybe someone's patchwork script went crazy ;) I've reassigned the patches to Priyanka who is NXP maintainer and changed the state to "New". Hope this helps ;) -- - Daniel
Re: [PATCH 0/2] Fix MIPS/Malta target and its IDE work
Am Dienstag, den 23.02.2021, 15:19 +0100 schrieb Reinoud Zandijk:
> Hi Daniel,
>
> On Tue, Feb 23, 2021 at 01:03:05AM +0100, Daniel Schwierzeck wrote:
> > Am Montag, den 22.02.2021, 20:56 +0100 schrieb Reinoud Zandijk:
> > > If I remove it, the machine just spins in Qemu, no output,
> > > nothing.
> > > If I add
> > > it, it works fine again. I found out by bisecting. I have no idea
> > > why
> > > the
> > > tests aren't picking this up. Could it be a qemu/gcc/binutils
> > > combination
> > > issue? A symbol not set as expected?
> > >
> > > qemu 5.1.0
> > > gcc 8.3.0
> > > binutils 2.32
> > >
> >
> > which board config did you try exactly? malta or maltael?
>
> Both malta and maltael have the same behaviour. And yeah, for maltael
> i needed
> the u-boot-swap.bin indeed! That was not that obvious at first but
> trial and
> error showed it.
>
> How are the tests performed? Are the actual u-boot images passed as
> compiled
> with `-bios' to qemu and that alone? Or are the tests also sneaking
> in the FDT
> to qemu? By f.e. appending them?
we use the images as built by the default configs. We don't use "-bios"
but "-drive if=pflash,file=${U_BOOT_BUILD_DIR}/flash.img,format=raw" to
emulate NOR flash and to be closer to hardware.
flash.img is created with that script:
https://gitlab.denx.de/u-boot/u-boot-test-hooks/-/blob/master/bin/flash.qemu_gen_padded_image
--
- Daniel
Re: [PATCH 0/2] Fix MIPS/Malta target and its IDE work
Am Montag, den 22.02.2021, 20:56 +0100 schrieb Reinoud Zandijk: > Hi Daniel, > > On Mon, Feb 22, 2021 at 07:23:26PM +0100, Daniel Schwierzeck wrote: > > Am Montag, den 22.02.2021, 18:05 +0100 schrieb Reinoud Zandijk: > > > Patch 0001 re-enables FDT inclusion into the u-boot binary to > > > make > > > them boot > > > again. The code might not have adjusted well enough in the past > > > to > > > handle the > > > separate one. > > > > what exactly is the issue? Do you see it just on real hardware? > > > > Booting all Malta variants in Qemu is contained in official U-Boot > > CI > > and showed no boot failures until now. Unfortuneately I don't have > > Malta hardware myself for testing. > > If I remove it, the machine just spins in Qemu, no output, nothing. > If I add > it, it works fine again. I found out by bisecting. I have no idea why > the > tests aren't picking this up. Could it be a qemu/gcc/binutils > combination > issue? A symbol not set as expected? > > qemu 5.1.0 > gcc 8.3.0 > binutils 2.32 > which board config did you try exactly? malta or maltael? For maltael and malta64el an extra U-Boot binary named u-boot-swap.bin is generated which is booted with Qemu. See also [1] respectively all conf.malta*_qemu configs for working Qemu configurations for all Malta variants. The reason for that extra image is that the original MIPS YAMON loader builds a combined EB/EL image and links it to EB. With some assembly magic the start code determines immediately after the reset vector which endianess the CPU is running and branches to the according EB or LE image. This is replicated in the Qemu Malta machine implementation. The Malta EL machine code excepts a bootloader in EB format and swaps the code back to EL before executing it. To workaround this, we need to feed this u-boot-swap.bin to Qemu. [1] https://gitlab.denx.de/u-boot/u-boot-test-hooks/-blob/master/bin/travis-ci/conf.maltael_qemu -- - Daniel
Re: [PATCH 0/2] Fix MIPS/Malta target and its IDE work
Am Montag, den 22.02.2021, 18:05 +0100 schrieb Reinoud Zandijk: > Patch 0001 re-enables FDT inclusion into the u-boot binary to make > them boot > again. The code might not have adjusted well enough in the past to > handle the > separate one. what exactly is the issue? Do you see it just on real hardware? Booting all Malta variants in Qemu is contained in official U-Boot CI and showed no boot failures until now. Unfortuneately I don't have Malta hardware myself for testing. Also CONFIG_OF_EMBED is just a debug option and should be avoided for production builds. So if there is a real problem, I would prefer to rather fix that instead of enabling CONFIG_OF_EMBED. > > Patch 0002 fixes IDE issues found on the Malta board: > > 1) DMA implied commands were sent to the controller in stead of the > PIO > variants. The rest of the code is DMA free and written for PIO > operation. > > 2) direct pointer access was used to read and write the registers > instead of > the inb/inw/outb/outw functions/macros. Registers don't have to be > memory > mapped and ATA_CURR_BASE() does not have to return an offset from > address > zero. > > 3) Endian isues in ide_ident() and reading/writing data in general. > Names were > corrupted and sizes misreported. > > With the fixes, malta_defconfig and maltael_defconfig work again in > Qemu. > > Reinoud Zandijk (2): > Re-embed the FDTs for the Malta targets. > Fix IDE commands issued, fix endian issues, fix non MMIO > > configs/malta64_defconfig | 1 + > configs/malta64el_defconfig | 1 + > configs/malta_defconfig | 1 + > configs/maltael_defconfig | 1 + > drivers/block/ide.c | 143 ++-- > > include/ata.h | 3 +- > 6 files changed, 46 insertions(+), 104 deletions(-) > > Signed-off-by: Reinoud Zandijk > -- - Daniel
Re: [PATCH 01/26] Revert "pci: pci-uclass: Dynamically allocate the PCI regions"
Am Sonntag, den 14.02.2021, 09:52 -0500 schrieb Tom Rini: ... > > > > > > > > > > > > > Tom, do you know the situation here? > > > > > > > > > > So, I made a lack of DM_PCI migration be fatal and got a > > > > > build done > > > > > here: > > > > > https://gitlab.denx.de/u-boot/u-boot/-/pipelines/6348 > > > > > > > > > > Of note, MIPS malta fails, so I had to drop that from pytest > > > > > to complete > > > > > the world build. There's then a handful of ARM boards, > > > > > another large > > > > > chunk of PowerPC, and then a few others such as r7780mp. SH > > > > > is the big > > > > > what to do here to me, other than PowerPC, as other than > > > > > r2dplus > > > > > everything is missing the main "convert to DM" migration > > > > > deadline as > > > > > well. > > > > > > > > What should we do for this patch? > > > > > > > > If the plan is to drop all boards that are not converted to DM > > > > PCI in > > > > 2021.04, I can drop this revert patch in v2. > > > > > > I've posted the patch to drop the SH boards. Daniel, what about > > > Malta? > > > > Malta should be fixed, since it's mips used in CI. > > There's also qemu_mips* in CI, so it depends on what Daniel thinks is > the right overall answer here. > Malta is the MIPS reference board physically as well as in Qemu. qemu_mips is actually deprecated and is going to be removed from Qemu sooner or later. That's why I added Malta to CI with the goal to remove qemu_mips. The problem with MIPS and DM_PCI is that there are some generic issues with memory mapping and CONFIG_SYS_SDRAM_BASE being used as virtual address. Actually I have a pending patch queue from Paul Burton for Malta for converting to DM_PCI, but that requires resolving the generic issues with some refactoring for all MIPS boards. It's still on my TODO list ;) Until I can spare enough time to resolve all issues, I could try to disable the PCI driver in Malta defconfig and mark the driver as broken in Kconfig. This way we can avoid removing the whole board. -- - Daniel
[PULL] u-boot-mips
Hi Tom, please pull updates for MIPS. This adds support for Mediatek MT7620 SoCs. Gitlab CI: https://gitlab.denx.de/u-boot/custodians/u-boot-mips/-/pipelines/6039 Azure: https://dev.azure.com/danielschwierzeck/u-boot/_build/results?buildId=15=results The following changes since commit 69d29fe1c0aeb33f42633a7d30b7921c02aa: Merge tag 'efi-2021-04-rc1-3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi (2021-01-23 19:07:00 -0500) are available in the Git repository at: https://gitlab.denx.de/u-boot/custodians/u-boot-mips.git tags/mips-pull-2021-01-24 for you to fetch changes up to 9f03585e8dd5554f131bbe507ccebbc30354f493: MAINTAINERS: add maintainer for MediaTek MIPS platform (2021-01-24 21:39:27 +0100) - MIPS: add support for Mediatek MT7620 SoCs Weijie Gao (23): mips: dts: switch to board defines for dtb for mtmips mips: mtmips: move mt7628 related Kconfig into mt7628 subdirectory mips: mtmips: select SYSRESET for mt7628 only mips: mtmips: fix dram size detection in dram_init mips: enable _machine_restart for spl mips: mtmips: add support to initialize SDRAM mips: mtmips: add support for MediaTek MT7620 SoC mips: mtmips: add two reference boards for mt7620 configs: mtmips: refresh for mt7628 based boards serial: add uart driver for MediaTek MT7620 SoC clk: add clock driver for MediaTek MT7620 SoC reset: mtmips: add reset controller support for MediaTek MT7620 SoC pinctrl: mtmips: add support for MediaTek MT7620 SoC watchdog: add watchdog driver for MediaTek MT7620 SoC gpio: add GPIO controller driver for MediaTek MT7620 SoC spi: add spi controller support for MediaTek MT7620 SoC phy: add USB PHY driver for MediaTek MT7620 SoC net: add ethernet driver for MediaTek MT7620 SoC mmc: mtk-sd: fix sclk cycles shift value mmc: mtk-sd: add pad control settings for MediaTek MT7620/MT76x8 SoCs mmc: mtk-sd: assign plat->cfg.f_max with a correct value reset: reset-mtmips: add DM_FLAG_PRE_RELOC flag MAINTAINERS: add maintainer for MediaTek MIPS platform MAINTAINERS | 23 + arch/mips/Kconfig|1 - arch/mips/cpu/cpu.c |2 +- arch/mips/dts/Makefile |7 +- arch/mips/dts/mediatek,mt7620-mt7530-rfb.dts | 100 ++ arch/mips/dts/mediatek,mt7620-rfb.dts| 97 ++ arch/mips/dts/mt7620-u-boot.dtsi | 14 + arch/mips/dts/mt7620.dtsi| 296 ++ arch/mips/mach-mtmips/Kconfig| 72 +- arch/mips/mach-mtmips/Makefile |1 + arch/mips/mach-mtmips/cpu.c |5 +- arch/mips/mach-mtmips/ddr_init.c | 59 ++ arch/mips/mach-mtmips/include/mach/ddr.h |4 + arch/mips/mach-mtmips/include/mach/mt7620-sysc.h | 54 + arch/mips/mach-mtmips/mt7620/Kconfig | 71 ++ arch/mips/mach-mtmips/mt7620/Makefile| 10 + arch/mips/mach-mtmips/mt7620/dram.c | 113 ++ arch/mips/mach-mtmips/mt7620/init.c | 193 arch/mips/mach-mtmips/mt7620/lowlevel_init.S | 53 + arch/mips/mach-mtmips/mt7620/mt7620.h| 103 ++ arch/mips/mach-mtmips/mt7620/serial.c| 36 + arch/mips/mach-mtmips/mt7620/sysc.c | 172 +++ arch/mips/mach-mtmips/mt7628/Kconfig | 53 + board/mediatek/mt7620/Kconfig| 12 + board/mediatek/mt7620/MAINTAINERS|9 + board/mediatek/mt7620/Makefile |3 + board/mediatek/mt7620/board.c|6 + configs/gardena-smart-gateway-mt7688_defconfig |1 + configs/linkit-smart-7688_defconfig |1 + configs/mt7620_mt7530_rfb_defconfig | 58 + configs/mt7620_rfb_defconfig | 76 ++ configs/mt7628_rfb_defconfig |1 + configs/vocore2_defconfig|1 + drivers/clk/mtmips/Makefile |1 + drivers/clk/mtmips/clk-mt7620.c | 159 +++ drivers/gpio/Kconfig |8 + drivers/gpio/Makefile|1 + drivers/gpio/mt7620_gpio.c | 146 +++ drivers/mmc/mtk-sd.c | 136 ++- drivers/net/Kconfig | 12 + drivers/net/Makefile |1 + drivers/net/mt7620-eth.c | 1222 ++ drivers/phy/Kconfig |7 + drivers/phy/Makefile |1 + drivers/phy/mt7620-usb-phy.c | 110 ++
Re: [PATCH v4 01/23] mips: dts: switch to board defines for dtb for mtmips
Hi Weijie, Am Dienstag, den 19.01.2021, 08:58 +0800 schrieb Weijie Gao: > > > > > > Hi Daniel, > > > > > > Gentle ping > > > > > > I'm just curious when can the patch series be merged into u-boot/master? > > > > > > > Hi Weijie, > > > > thanks for the reminder, I missed the opening of the merge window ;) > > > > I rebased the MIPS next branch and triggered all CI builds. If all is > > ok, I'll prepare a pull request. > > > > got it. thanks. in mainline there was a lot of renaming in DM core. I created fixup commits in u-boot-mips/next to fix all build errors. Could you give it short look and test? Thanks. -- - Daniel
Re: [PATCH v4 01/23] mips: dts: switch to board defines for dtb for mtmips
Am Montag, den 18.01.2021, 15:54 +0800 schrieb Weijie Gao: > On Fri, 2020-11-27 at 21:19 +0100, Daniel Schwierzeck wrote: > > Am Donnerstag, den 12.11.2020, 16:35 +0800 schrieb Weijie Gao: > > > Previous the dts files for gardena-smart-gateway-mt7688 and > > > linkit-smart-7688 are set to be built when mtmips is selected. > > > > > > This can lead to a compilation error if another soc is added to this arch > > > with different dtsi files. > > > > > > So it's better to build the dtb only if their board is selected. > > > > > > Reviewed-by: Stefan Roese > > > Signed-off-by: Weijie Gao > > > --- > > > v4 changes: none > > > v3 changes: none > > > v2 changes: none > > > --- > > > arch/mips/dts/Makefile | 5 ++--- > > > 1 file changed, 2 insertions(+), 3 deletions(-) > > > > > > > > > > series applied to u-boot-mips/next, thanks. > > > > Hi Daniel, > > Gentle ping > > I'm just curious when can the patch series be merged into u-boot/master? > Hi Weijie, thanks for the reminder, I missed the opening of the merge window ;) I rebased the MIPS next branch and triggered all CI builds. If all is ok, I'll prepare a pull request. -- - Daniel
