Re: [PATCH v3 08/10] spi: dw: Add mem_ops
> From: Sean Anderson > Sent: Monday, September 14, 2020 18:35 > To: u-boot@lists.denx.de; uboot-snps-...@synopsys.com > Cc: Marek Vasut; Horatiu Vultur; Eugeniy Paltsev; Jagan Teki; Heinrich > Schuchardt; Sean Anderson > Subject: [PATCH v3 08/10] spi: dw: Add mem_ops > > Changes in v3: > - Use constant 0x1 instead of SZ_64K. The latter is not included on > some platforms and I'm too lazy to figure out what the correct header is. ??? #include
Re: [PATCH v2 00/10] riscv: Add SPI support for Kendryte K210
FYI: I've tested on commit aa68b00a8259aa026591475f21a5c51311252ef2 (current branch head) and I don't see any build/runtime issues. Tested-by Eugeniy Paltsev --- Eugeniy Paltsev From: Sean Anderson Sent: Monday, August 10, 2020 14:13 To: Eugeniy Paltsev; u-boot@lists.denx.de; uboot-snps-...@synopsys.com Cc: Heinrich Schuchardt; Jagan Teki; Horatiu Vultur; Marek Vasut; Alexey Brodkin; Daniel Schwierzeck; Gregory CLEMENT; Lars Povlsen; Ley Foon Tan; Rick Chen; Simon Goldschmidt Subject: Re: [PATCH v2 00/10] riscv: Add SPI support for Kendryte K210 On 8/10/20 6:49 AM, Eugeniy Paltsev wrote: > Hi Sean, > > do you have any public git branch with this patch series? > I want to test these changes on our board with DW SPI controller. https://urldefense.com/v3/__https://github.com/Forty-Bot/u-boot/tree/maix_spi__;!!A4F2R9G_pg!JnihRPoojBUo2j8mMgJNH_K5dis6o-g7c2YGmb0SYh2wBkWGASlPXxMFW-TPbdSOtlYUiTs$ --Sean
Re: [PATCH v2 00/10] riscv: Add SPI support for Kendryte K210
Hi Sean, do you have any public git branch with this patch series? I want to test these changes on our board with DW SPI controller. Thanks. --- Eugeniy Paltsev From: Sean Anderson Sent: Friday, August 7, 2020 17:43 To: u-boot@lists.denx.de; uboot-snps-...@synopsys.com Cc: Heinrich Schuchardt; Jagan Teki; Eugeniy Paltsev; Horatiu Vultur; Marek Vasut; Sean Anderson; Alexey Brodkin; Alexey Brodkin; Daniel Schwierzeck; Gregory CLEMENT; Lars Povlsen; Ley Foon Tan; Rick Chen; Simon Goldschmidt Subject: [PATCH v2 00/10] riscv: Add SPI support for Kendryte K210 This series adds support for SPI on the Kendryte K210. This covers the MMC slot (currently broken) and SPI flash on the Sipeed Maix Bit. This series makes significant changes to the designware SPI driver. I would really appreciate if the maintainers I CC'd could test this series and ensure that SPI still works on all their devices. I have tried my best not to affect existing devices, but I'd rather find out if this breaks stuff now rather than later. In particular: Ley Foon Tan, can you try using dw_spi_dw32_init with the Stratix 10 and Agilex SoCFPGAs? From their documentation, it is unclear whether one should use the DFS or DFS_32 field. I have used dw_spi_dw16_init for these devices, since that keeps the same behavior as before this series, but I am interested in seeing whether the DFS_32 works. Gregory Clement, Lars Povlsen, and Horatiu Vultur, can you confirm the register layout of ctrlr0 and version of the device on the MSCC Ocelot and Jaguar 2? I couldn't find any documentation for the device on those SoCs online. Alexey Brodkin and Eugeniy Paltsev, can you confirm the register layout of ctrlr0 and version of the device on ARC SoCs? I couldn't find any documentation for the device on those SoCs online. In addition, can you clarify the nature of SSI_MAX_XFER_SIZE? Is it set once before the device is fabricated, or is it set at runtime? Is there any way to detect it at runtime? Is my supposition that it was introduced in version 3.23 correct? Have there been any other breaking changes which I have overlooked? I tried investigating some of this, but I was unable to find any definitive ruling on the matter. All I could find was this forum post which doesn't really explain anything [1]. [1] https://urldefense.com/v3/__https://community.intel.com/t5/Intel-Makers/D2000-SPI-word-frame-size/td-p/276520__;!!A4F2R9G_pg!PEqqmGgI-XfH0K6kaLF8oIuYYMfBugTtH4ysThH7wyY4Q01OMi_rGRiRi2hs0S7bdAf8nWI$ This series was previously part of https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/uboot/list/?series=161576__;!!A4F2R9G_pg!PEqqmGgI-XfH0K6kaLF8oIuYYMfBugTtH4ysThH7wyY4Q01OMi_rGRiRi2hs0S7bo-OeOVc$ This series depends on https://urldefense.com/v3/__https://patchwork.ozlabs.org/project/uboot/list/?series=185489__;!!A4F2R9G_pg!PEqqmGgI-XfH0K6kaLF8oIuYYMfBugTtH4ysThH7wyY4Q01OMi_rGRiRi2hs0S7b478gncg$ Known bugs: - The MMC cannot be accessed with the dw_spi driver Changes in v2: - Add Gigadevice SPI chips to dependencies - Add external gpio cs support - Clean up exec_op - Configure ctrlr0 register layout based on compatible string - Convert debug calls to log_ instead of removing the ones which affect timing - Document new compatible strings - Limit data transfers to 64k - Remove broken-wp property (implicit due to no wp gpio) - Remove ctrl0 field offsets from device tree - Switch to new compatible strings - Switch to new pinmux binding style Sean Anderson (10): spi: dw: Convert calls to debug to log_* spi: dw: Rename "cs-gpio" to "cs-gpios" spi: dw: Use generic function to read reg address spi: dw: Rearrange struct dw_spi_priv spi: dw: Add SoC-specific compatible strings spi: dw: Configure ctrlr0 layout based on compatible string spi: dw: Document devicetree binding spi: dw: Add mem_ops riscv: Add device tree bindings for SPI riscv: Add support for SPI on Kendryte K210 arch/arc/dts/axs10x_mb.dtsi | 5 +- arch/arc/dts/hsdk-common.dtsi | 5 +- arch/arm/dts/socfpga.dtsi | 6 +- arch/arm/dts/socfpga_agilex.dtsi | 6 +- arch/arm/dts/socfpga_arria10.dtsi | 6 +- arch/arm/dts/socfpga_stratix10.dtsi | 6 +- arch/mips/dts/mscc,jr2.dtsi | 2 +- arch/mips/dts/mscc,ocelot.dtsi| 2 +- arch/riscv/dts/k210-maix-bit.dts | 46 ++- arch/riscv/dts/k210.dtsi | 15 +- board/sipeed/maix/Kconfig | 11 + configs/sipeed_maix_bitm_defconfig| 8 + doc/board/sipeed/maix.rst | 94 +++-- .../spi/snps,dw-apb-ssi.txt | 56 +++ drivers/spi/designware_spi.c | 381 ++ 15 files changed, 528 insertions(+), 121 deletions(-) create mode 100644 doc/device-tree-bindings/spi/snps,dw-apb-ssi.txt -- 2.28.0
[PATCH 7/8] CLK: ARC: HSDK: define clock map with DT binding constants
Define clock map with DT binding constants so clock map can be
discontinuous.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 56 --
1 file changed, 29 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index dd665b13587..a44382d9586 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -15,6 +15,8 @@
#include
#include
+#include
+
/*
* Synopsys ARC HSDK clock tree.
*
@@ -287,33 +289,33 @@ struct cgu_clk_map {
};
static const struct cgu_clk_map clock_map[] = {
- { CGU_ARC_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_ARC_PLL, CGU_ARC_IDIV, _pll_dat, idiv_get, cpu_clk_set,
idiv_off },
- { CGU_DDR_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_SYS_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_SYS_PLL, CGU_SYS_IDIV_APB, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, _pll_dat, idiv_get, axi_clk_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_USB, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_DMA, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CFG, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_TUN_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, _pll_dat, idiv_get, tun_clk_set,
idiv_off },
- { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_TUN_PLL, CGU_TUN_IDIV_TIMER, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_HDMI_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, _pll_dat, idiv_get, idiv_set,
idiv_off }
+ [CLK_ARC_PLL]= { CGU_ARC_PLL, 0,
_pll_dat, pll_get, pll_set, NULL },
+ [CLK_ARC]= { CGU_ARC_PLL, CGU_ARC_IDIV,
_pll_dat, idiv_get, cpu_clk_set, idiv_off },
+ [CLK_DDR_PLL]= { CGU_DDR_PLL, 0,
_pll_dat, pll_get, pll_set, NULL },
+ [CLK_SYS_PLL]= { CGU_SYS_PLL, 0,
_pll_dat, pll_get, pll_set, NULL },
+ [CLK_SYS_APB]= { CGU_SYS_PLL, CGU_SYS_IDIV_APB,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_AXI]= { CGU_SYS_PLL, CGU_SYS_IDIV_AXI,
_pll_dat, idiv_get, axi_clk_set, idiv_off },
+ [CLK_SYS_ETH]= { CGU_SYS_PLL, CGU_SYS_IDIV_ETH,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_USB]= { CGU_SYS_PLL, CGU_SYS_IDIV_USB,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_SDIO] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_HDMI] = { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_GFX_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_GFX_DMA]= { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_DMA,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_GFX_CFG]= { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CFG,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_DMAC_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_DMAC_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_SDIO_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_SPI_REF]= { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_I2C_REF]= { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_SYS_UART_REF
[PATCH 8/8] CLK: ARC: HSDK: add separate clock map for HSDK-4xD
HSDK and HSDK-4xD clock trees are slightly different.
commit 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock")
introduce regression for HSDK board cause crash when setting
tunnel clock. Fix that.
Fixes: 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock")
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/Kconfig| 7 ++--
drivers/clk/clk-hsdk-cgu.c | 68 +-
2 files changed, 64 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1992d4a4b47..8b8b715 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -100,10 +100,11 @@ config CLK_TI_SCI
managed by the TI System Controller, say Y here. Otherwise, say N.
config CLK_HSDK
- bool "Enable cgu clock driver for HSDK"
- depends on CLK
+ bool "Enable cgu clock driver for HSDK boards"
+ depends on CLK && TARGET_HSDK
help
- Enable this to support the cgu clocks on Synopsys ARC HSDK
+ Enable this to support the cgu clocks on Synopsys ARC HSDK and
+ Synopsys ARC HSDK-4xD boards
config CLK_VERSAL
bool "Enable clock driver support for Versal"
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index a44382d9586..2de3a6a30b0 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
@@ -141,7 +142,7 @@ struct hsdk_div_full_cfg {
const struct hsdk_idiv_cfg idiv[];
};
-static const struct hsdk_div_full_cfg tun_clk_cfg = {
+static const struct hsdk_div_full_cfg hsdk_4xd_tun_clk_cfg = {
{ 2500, 5000, 7500, 1, 12500, 15000 },
{ 6, 6, 6, 6, 75000, 6 }, {
{ CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
@@ -152,6 +153,16 @@ static const struct hsdk_div_full_cfg tun_clk_cfg = {
}
};
+static const struct hsdk_div_full_cfg hsdk_tun_clk_cfg = {
+ { 2500, 5000, 7500, 1, 12500, 15000 },
+ { 6, 6, 6, 6, 75000, 6 }, {
+ { CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
+ { CGU_TUN_IDIV_ROM, { 4,4, 4, 4, 5, 4 } },
+ { CGU_TUN_IDIV_PWM, { 8,8, 8, 8, 10, 8 } },
+ { /* last one */ }
+ }
+};
+
static const struct hsdk_div_full_cfg axi_clk_cfg = {
{ 2,4, 6, 8 },
{ 8,8, 6, 8 }, {
@@ -273,7 +284,8 @@ static const struct hsdk_pll_devdata hdmi_pll_dat = {
static ulong idiv_set(struct clk *, ulong);
static ulong cpu_clk_set(struct clk *, ulong);
static ulong axi_clk_set(struct clk *, ulong);
-static ulong tun_clk_set(struct clk *, ulong);
+static ulong tun_hsdk_set(struct clk *, ulong);
+static ulong tun_h4xd_set(struct clk *, ulong);
static ulong idiv_get(struct clk *);
static int idiv_off(struct clk *);
static ulong pll_set(struct clk *, ulong);
@@ -288,7 +300,7 @@ struct cgu_clk_map {
const int (*const disable)(struct clk *clk);
};
-static const struct cgu_clk_map clock_map[] = {
+static const struct cgu_clk_map hsdk_clk_map[] = {
[CLK_ARC_PLL]= { CGU_ARC_PLL, 0,
_pll_dat, pll_get, pll_set, NULL },
[CLK_ARC]= { CGU_ARC_PLL, CGU_ARC_IDIV,
_pll_dat, idiv_get, cpu_clk_set, idiv_off },
[CLK_DDR_PLL]= { CGU_DDR_PLL, 0,
_pll_dat, pll_get, pll_set, NULL },
@@ -310,7 +322,37 @@ static const struct cgu_clk_map clock_map[] = {
[CLK_SYS_UART_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF,
_pll_dat, idiv_get, idiv_set, idiv_off },
[CLK_SYS_EBI_REF]= { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF,
_pll_dat, idiv_get, idiv_set, idiv_off },
[CLK_TUN_PLL]= { CGU_TUN_PLL, 0,
_pll_dat, pll_get, pll_set, NULL },
- [CLK_TUN_TUN]= { CGU_TUN_PLL, CGU_TUN_IDIV_TUN,
_pll_dat, idiv_get, tun_clk_set, idiv_off },
+ [CLK_TUN_TUN]= { CGU_TUN_PLL, CGU_TUN_IDIV_TUN,
_pll_dat, idiv_get, tun_hsdk_set, idiv_off },
+ [CLK_TUN_ROM]= { CGU_TUN_PLL, CGU_TUN_IDIV_ROM,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_TUN_PWM]= { CGU_TUN_PLL, CGU_TUN_IDIV_PWM,
_pll_dat, idiv_get, idiv_set, idiv_off },
+ [CLK_TUN_TIMER] = { /* missing in HSDK */ },
+ [CLK_HDMI_PLL] = { CGU_HDMI_PLL, 0,
_pll_dat, pll_get, pll_set, NULL },
+ [CLK_HDMI] = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB,
_pll_dat, idiv_get, idiv_set, idiv_off }
+};
+
+static const stru
[PATCH 1/8] CLK: ARC: HSDK: avoid code duplication
hsdk_axi_clk_cfg and hsdk_tun_clk_cfg clock divider structures
and functions for their processing are almost the same so
merge them to avoid code duplication.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 112 +
1 file changed, 40 insertions(+), 72 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 3035c5fb38e..a51e78071a9 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -126,45 +126,31 @@
#define PARENT_RATE_27 2700 /* fixed clock - xtal */
#define CGU_MAX_CLOCKS 27
-#define CGU_SYS_CLOCKS 16
-#define MAX_AXI_CLOCKS 4
+#define MAX_FREQ_VARIATIONS6
-#define CGU_TUN_CLOCKS 4
-#define MAX_TUN_CLOCKS 6
-
-struct hsdk_tun_idiv_cfg {
+struct hsdk_idiv_cfg {
u32 oft;
- u8 val[MAX_TUN_CLOCKS];
+ u8 val[MAX_FREQ_VARIATIONS];
};
-struct hsdk_tun_clk_cfg {
- const u32 clk_rate[MAX_TUN_CLOCKS];
- const u32 pll_rate[MAX_TUN_CLOCKS];
- const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
+struct hsdk_div_full_cfg {
+ const u32 clk_rate[MAX_FREQ_VARIATIONS];
+ const u32 pll_rate[MAX_FREQ_VARIATIONS];
+ const struct hsdk_idiv_cfg idiv[];
};
-static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
+static const struct hsdk_div_full_cfg tun_clk_cfg = {
{ 2500, 5000, 7500, 1, 12500, 15000 },
{ 6, 6, 6, 6, 75000, 6 }, {
{ CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
{ CGU_TUN_IDIV_ROM, { 4,4, 4, 4, 5, 4 } },
{ CGU_TUN_IDIV_PWM, { 8,8, 8, 8, 10, 8 } },
- { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } }
+ { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } },
+ { /* last one */ }
}
};
-struct hsdk_sys_idiv_cfg {
- u32 oft;
- u8 val[MAX_AXI_CLOCKS];
-};
-
-struct hsdk_axi_clk_cfg {
- const u32 clk_rate[MAX_AXI_CLOCKS];
- const u32 pll_rate[MAX_AXI_CLOCKS];
- const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
-};
-
-static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
+static const struct hsdk_div_full_cfg axi_clk_cfg = {
{ 2,4, 6, 8 },
{ 8,8, 6, 8 }, {
{ CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
@@ -182,7 +168,8 @@ static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
{ CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
{ CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
{ CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
- { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
+ { CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } }, /* EBI-REF */
+ { /* last one */ }
}
};
@@ -546,8 +533,13 @@ static ulong cpu_clk_set(struct clk *sclk, ulong rate)
return ret;
}
-/* Special behavior: wen we set this clock we set both idiv and pll and all
pll dividers */
-static ulong axi_clk_set(struct clk *sclk, ulong rate)
+/*
+ * Special behavior:
+ * when we set these clocks we set both PLL and all idiv dividers related to
+ * this PLL domain.
+ */
+static ulong common_div_clk_set(struct clk *sclk, ulong rate,
+ const struct hsdk_div_full_cfg *cfg)
{
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
ulong pll_rate;
@@ -556,71 +548,47 @@ static ulong axi_clk_set(struct clk *sclk, ulong rate)
pll_rate = pll_get(sclk);
- for (i = 0; i < MAX_AXI_CLOCKS; i++) {
- if (axi_clk_cfg.clk_rate[i] == rate) {
+ for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
+ /* unused freq variations are filled with 0 */
+ if (!cfg->clk_rate[i])
+ break;
+
+ if (cfg->clk_rate[i] == rate) {
freq_idx = i;
break;
}
}
if (freq_idx < 0) {
- pr_err("axi clk: invalid rate=%ld Hz\n", rate);
+ pr_err("clk: invalid rate=%ld Hz\n", rate);
return -EINVAL;
}
/* configure PLL before dividers */
- if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
- ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
+ if (cfg->pll_rate[freq_idx] < pll_rate)
+ ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
/* configure SYS dividers */
- for (i = 0; i < CGU_SYS_CLOCKS; i++) {
- clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
-
[PATCH 6/8] CLK: ARC: HSDK: make set_clock optional
We don't want to allow change some clocks, i.e. DDR clock. So allow to have set_clock to be unset in clock map. Signed-off-by: Eugeniy Paltsev --- drivers/clk/clk-hsdk-cgu.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c index 6aba4587a44..dd665b13587 100644 --- a/drivers/clk/clk-hsdk-cgu.c +++ b/drivers/clk/clk-hsdk-cgu.c @@ -662,7 +662,10 @@ static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate) if (hsdk_prepare_clock_tree_branch(sclk)) return -EINVAL; - return clk->map[sclk->id].set_rate(sclk, rate); + if (clk->map[sclk->id].set_rate) + return clk->map[sclk->id].set_rate(sclk, rate); + + return -ENOTSUPP; } static int hsdk_cgu_disable(struct clk *sclk) -- 2.21.3
[PATCH 3/8] CLK: ARC: HSDK: use appropriate config data types
* constify clocks config data where is possible
* use more appropriate data types for clocks config
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 41 +++---
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index ad0b74fbdb9..30690b72f3c 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -129,8 +129,8 @@
#define MAX_FREQ_VARIATIONS6
struct hsdk_idiv_cfg {
- u32 oft;
- u8 val[MAX_FREQ_VARIATIONS];
+ const u32 oft;
+ const u8 val[MAX_FREQ_VARIATIONS];
};
struct hsdk_div_full_cfg {
@@ -174,11 +174,11 @@ static const struct hsdk_div_full_cfg axi_clk_cfg = {
};
struct hsdk_pll_cfg {
- u32 rate;
- u32 idiv;
- u32 fbdiv;
- u32 odiv;
- u32 band;
+ const u32 rate;
+ const u8 idiv;
+ const u8 fbdiv;
+ const u8 odiv;
+ const u8 band;
};
static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
@@ -233,9 +233,10 @@ struct hsdk_cgu_clk {
struct hsdk_pll_devdata {
const u32 parent_rate;
- const struct hsdk_pll_cfg *pll_cfg;
- int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
- const struct hsdk_pll_cfg *cfg);
+ const struct hsdk_pll_cfg *const pll_cfg;
+ const int (*const update_rate)(struct hsdk_cgu_clk *clk,
+ unsigned long rate,
+ const struct hsdk_pll_cfg *cfg);
};
static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
@@ -271,12 +272,12 @@ static ulong pll_set(struct clk *, ulong);
static ulong pll_get(struct clk *);
struct hsdk_cgu_clock_map {
- u32 cgu_pll_oft;
- u32 cgu_div_oft;
- const struct hsdk_pll_devdata *pll_devdata;
- ulong (*get_rate)(struct clk *clk);
- ulong (*set_rate)(struct clk *clk, ulong rate);
- int (*disable)(struct clk *clk);
+ const u32 cgu_pll_oft;
+ const u32 cgu_div_oft;
+ const struct hsdk_pll_devdata *const pll_devdata;
+ const ulong (*const get_rate)(struct clk *clk);
+ const ulong (*const set_rate)(struct clk *clk, ulong rate);
+ const int (*const disable)(struct clk *clk);
};
static const struct hsdk_cgu_clock_map clock_map[] = {
@@ -345,10 +346,10 @@ static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk
*clk,
u32 val = 0;
/* Powerdown and Bypass bits should be cleared */
- val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
- val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
- val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
- val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
+ val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
+ val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
+ val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
+ val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
pr_debug("write configurarion: %#x\n", val);
--
2.21.3
[PATCH 5/8] CLK: ARC: HSDK: prepare for multiple clock maps support
The clock trees of HSDK and HSDK-4xD vary so we need to prepare
CGU driver for multiple clock maps support.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index d7cb4f46242..6aba4587a44 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -227,6 +227,7 @@ struct hsdk_cgu_domain {
};
struct hsdk_cgu_clk {
+ const struct cgu_clk_map *map;
/* CGU block register */
void __iomem *cgu_regs;
/* CREG block register */
@@ -632,37 +633,47 @@ static int hsdk_prepare_clock_tree_branch(struct clk
*sclk)
if (sclk->id >= CGU_MAX_CLOCKS)
return -EINVAL;
- clk->curr_domain.pll = clock_map[sclk->id].pll_devdata;
- clk->curr_domain.pll_regs = clk->cgu_regs +
clock_map[sclk->id].cgu_pll_oft;
+ /* clocks missing in current map have their entry zeroed */
+ if (!clk->map[sclk->id].pll_devdata)
+ return -EINVAL;
+
+ clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
+ clk->curr_domain.pll_regs = clk->cgu_regs +
clk->map[sclk->id].cgu_pll_oft;
clk->curr_domain.spec_regs = clk->creg_regs;
- clk->curr_domain.idiv_regs = clk->cgu_regs +
clock_map[sclk->id].cgu_div_oft;
+ clk->curr_domain.idiv_regs = clk->cgu_regs +
clk->map[sclk->id].cgu_div_oft;
return 0;
}
static ulong hsdk_cgu_get_rate(struct clk *sclk)
{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
if (hsdk_prepare_clock_tree_branch(sclk))
return -EINVAL;
- return clock_map[sclk->id].get_rate(sclk);
+ return clk->map[sclk->id].get_rate(sclk);
}
static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
if (hsdk_prepare_clock_tree_branch(sclk))
return -EINVAL;
- return clock_map[sclk->id].set_rate(sclk, rate);
+ return clk->map[sclk->id].set_rate(sclk, rate);
}
static int hsdk_cgu_disable(struct clk *sclk)
{
+ struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+
if (hsdk_prepare_clock_tree_branch(sclk))
return -EINVAL;
- if (clock_map[sclk->id].disable)
- return clock_map[sclk->id].disable(sclk);
+ if (clk->map[sclk->id].disable)
+ return clk->map[sclk->id].disable(sclk);
return -ENOTSUPP;
}
@@ -679,6 +690,8 @@ static int hsdk_cgu_clk_probe(struct udevice *dev)
BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
+ hsdk_clk->map = clock_map;
+
hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
if (!hsdk_clk->cgu_regs)
return -EINVAL;
--
2.21.3
[PATCH 0/8] CLK: ARC: HSDK: add separate clock map for HSDK-4xD
HSDK and HSDK-4xD clock trees are slightly different.
commit 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock")
introduce regression for HSDK board cause crash when setting
tunnel clock.
Fix that and do required code cleanup.
Eugeniy Paltsev (8):
CLK: ARC: HSDK: avoid code duplication
CLK: ARC: HSDK: drop unused offset
CLK: ARC: HSDK: use appropriate config data types
CLK: ARC: HSDK: driver cleanup
CLK: ARC: HSDK: prepare for multiple clock maps support
CLK: ARC: HSDK: make set_clock optional
CLK: ARC: HSDK: define clock map with DT binding constants
CLK: ARC: HSDK: add separate clock map for HSDK-4xD
drivers/clk/Kconfig| 7 +-
drivers/clk/clk-hsdk-cgu.c | 355 +
2 files changed, 202 insertions(+), 160 deletions(-)
--
2.21.3
[PATCH 4/8] CLK: ARC: HSDK: driver cleanup
Minor code cleanup to improve readability. No functional change intended.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 75 --
1 file changed, 39 insertions(+), 36 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 30690b72f3c..d7cb4f46242 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -214,23 +214,28 @@ static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
{}
};
-struct hsdk_cgu_clk {
- /* CGU block register */
- void __iomem *cgu_regs;
- /* CREG block register */
- void __iomem *creg_regs;
-
+struct hsdk_cgu_domain {
/* PLLs registers */
- void __iomem *regs;
+ void __iomem *pll_regs;
/* PLLs special registers */
void __iomem *spec_regs;
/* PLLs devdata */
- const struct hsdk_pll_devdata *pll_devdata;
+ const struct hsdk_pll_devdata *pll;
/* Dividers registers */
void __iomem *idiv_regs;
};
+struct hsdk_cgu_clk {
+ /* CGU block register */
+ void __iomem *cgu_regs;
+ /* CREG block register */
+ void __iomem *creg_regs;
+
+ /* The domain we are working with */
+ struct hsdk_cgu_domain curr_domain;
+};
+
struct hsdk_pll_devdata {
const u32 parent_rate;
const struct hsdk_pll_cfg *const pll_cfg;
@@ -271,7 +276,7 @@ static int idiv_off(struct clk *);
static ulong pll_set(struct clk *, ulong);
static ulong pll_get(struct clk *);
-struct hsdk_cgu_clock_map {
+struct cgu_clk_map {
const u32 cgu_pll_oft;
const u32 cgu_div_oft;
const struct hsdk_pll_devdata *const pll_devdata;
@@ -280,7 +285,7 @@ struct hsdk_cgu_clock_map {
const int (*const disable)(struct clk *clk);
};
-static const struct hsdk_cgu_clock_map clock_map[] = {
+static const struct cgu_clk_map clock_map[] = {
{ CGU_ARC_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
{ CGU_ARC_PLL, CGU_ARC_IDIV, _pll_dat, idiv_get, cpu_clk_set,
idiv_off },
{ CGU_DDR_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
@@ -312,32 +317,32 @@ static const struct hsdk_cgu_clock_map clock_map[] = {
static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
{
- iowrite32(val, clk->idiv_regs);
+ iowrite32(val, clk->curr_domain.idiv_regs);
}
static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
{
- return ioread32(clk->idiv_regs);
+ return ioread32(clk->curr_domain.idiv_regs);
}
static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
{
- iowrite32(val, clk->regs + reg);
+ iowrite32(val, clk->curr_domain.pll_regs + reg);
}
static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
{
- return ioread32(clk->regs + reg);
+ return ioread32(clk->curr_domain.pll_regs + reg);
}
static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32
val)
{
- iowrite32(val, clk->spec_regs + reg);
+ iowrite32(val, clk->curr_domain.spec_regs + reg);
}
static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
{
- return ioread32(clk->spec_regs + reg);
+ return ioread32(clk->curr_domain.spec_regs + reg);
}
static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
@@ -372,7 +377,7 @@ static ulong pll_get(struct clk *sclk)
u64 rate;
u32 idiv, fbdiv, odiv;
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
- u32 parent_rate = clk->pll_devdata->parent_rate;
+ u32 parent_rate = clk->curr_domain.pll->parent_rate;
val = hsdk_pll_read(clk, CGU_PLL_CTRL);
@@ -404,7 +409,7 @@ static unsigned long hsdk_pll_round_rate(struct clk *sclk,
unsigned long rate)
int i;
unsigned long best_rate;
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
- const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+ const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
if (pll_cfg[0].rate == 0)
return -EINVAL;
@@ -480,19 +485,17 @@ static ulong pll_set(struct clk *sclk, ulong rate)
int i;
unsigned long best_rate;
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
- const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
+ const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
+ const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
best_rate = hsdk_pll_round_rate(sclk, rate);
- for (i = 0; pll_cfg[i].rate != 0; i++) {
- if (pll_cfg[i].rate == best_rate) {
- return clk->pll_devdata->update_rate(clk, best_rate,
-_cfg[i]);
- }
- }
+ for (i = 0; pll_cfg[i].rate != 0; i++)
+ if (pll_cfg[i].ra
[PATCH 2/8] CLK: ARC: HSDK: drop unused offset
Drop creg_div_oft offset as it doesn't vary (due to it is used for
CPU PLL only).
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 57 +++---
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index a51e78071a9..ad0b74fbdb9 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -272,7 +272,6 @@ static ulong pll_get(struct clk *);
struct hsdk_cgu_clock_map {
u32 cgu_pll_oft;
- u32 creg_div_oft;
u32 cgu_div_oft;
const struct hsdk_pll_devdata *pll_devdata;
ulong (*get_rate)(struct clk *clk);
@@ -281,33 +280,33 @@ struct hsdk_cgu_clock_map {
};
static const struct hsdk_cgu_clock_map clock_map[] = {
- { CGU_ARC_PLL, 0, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_ARC_PLL, 0, CGU_ARC_IDIV, _pll_dat, idiv_get, cpu_clk_set,
idiv_off },
- { CGU_DDR_PLL, 0, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_SYS_PLL, 0, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, _pll_dat, idiv_get,
axi_clk_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, _pll_dat, idiv_get,
idiv_set, idiv_off },
- { CGU_TUN_PLL, 0, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, _pll_dat, idiv_get,
tun_clk_set, idiv_off },
- { CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, _pll_dat, idiv_get, idiv_set,
idiv_off },
- { CGU_HDMI_PLL, 0, 0, _pll_dat, pll_get, pll_set, NULL },
- { CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, _pll_dat, idiv_get,
idiv_set, idiv_off }
+ { CGU_ARC_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
+ { CGU_ARC_PLL, CGU_ARC_IDIV, _pll_dat, idiv_get, cpu_clk_set,
idiv_off },
+ { CGU_DDR_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
+ { CGU_SYS_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_APB, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, _pll_dat, idiv_get, axi_clk_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_USB, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_DMA, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CFG, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, _pll_dat, idiv_get,
idiv_set, idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_TUN_PLL, 0, _pll_dat, pll_get, pll_set, NULL },
+ { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, _pll_dat, idiv_get, tun_clk_set,
idiv_off },
+ { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, _pll_dat, idiv_get, idiv_set,
idiv_off
[PATCH] ARC: DTS: cleanup USB node names
Remove redundant '0x' from node names.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/axs10x_mb.dtsi | 4 ++--
arch/arc/dts/hsdk-common.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 5b77642b8d7..33b05934387 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -62,12 +62,12 @@
max-speed = <100>;
};
- ehci@0x4 {
+ ehci@4 {
compatible = "generic-ehci";
reg = < 0x4 0x100 >;
};
- ohci@0x6 {
+ ohci@6 {
compatible = "generic-ohci";
reg = < 0x6 0x100 >;
};
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index ea6cc468f83..9aa10e4b25d 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -84,7 +84,7 @@
phy-mode = "gmii";
};
- ehci@0xf004 {
+ ehci@f004 {
compatible = "generic-ehci";
reg = <0xf004 0x100>;
@@ -96,7 +96,7 @@
resets = <_rst HSDK_USB_RESET>;
};
- ohci@0xf006 {
+ ohci@f006 {
compatible = "generic-ohci";
reg = <0xf006 0x100>;
};
--
2.21.3
[PATCH] ARC: HSDK: add reset for EHCI
Add reset phandle to EHCI device tree node to make on-chip reset
controller usable with EHCI.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/hsdk-common.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index fd4245e1646..ea6cc468f83 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -87,6 +87,13 @@
ehci@0xf004 {
compatible = "generic-ehci";
reg = <0xf004 0x100>;
+
+ /*
+* OHCI and EHCI have reset line shared so we don't add
+* reset property to OHCI node as it is probed later and
+* it will reset sucessfuly probed and configured EHCI HW.
+*/
+ resets = <_rst HSDK_USB_RESET>;
};
ohci@0xf006 {
--
2.21.3
[PATCH] ARC: HSDK: anounce state of BIM switch
Anounce state of BIM switch which defines if U-boot is loaded
and started by preloader or not.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index a3e0563ff45..8ccd84ca600 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -42,6 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define CREG_CPU_START_MASK0xF
#define CREG_CPU_START_POL BIT(4)
+#define CREG_CORE_BOOT_IMAGE GENMASK(5, 4)
+
#define CREG_CPU_0_ENTRY (CREG_BASE + 0x404)
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
@@ -1241,11 +1243,16 @@ int board_late_init(void)
int checkboard(void)
{
+ u32 reg;
+
printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
if (board_mismatch())
printf("WARN: U-boot is configured NOT for this board but for
%s!\n",
board_name(get_board_type_config()));
+ reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
+ printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");
+
return 0;
};
--
2.21.1
Re: [PATCH] CMD: random: fix return code
Hi Simon, Tom, I guess it's perfect time to apply this patch. Thanks! --- Eugeniy Paltsev From: Simon Glass Sent: Monday, March 23, 2020 18:37 To: Eugeniy Paltsev Cc: Tom Rini; U-Boot Mailing List; uboot-snps-...@synopsys.com; Alexey Brodkin; linux-snps-...@lists.infradead.org Subject: Re: [PATCH] CMD: random: fix return code On Fri, 20 Mar 2020 at 10:38, Eugeniy Paltsev wrote: > > As of today 'random' command return 1 (CMD_RET_FAILURE) in case > of successful execution and 0 (CMD_RET_SUCCESS) in case of bad > arguments. Fix that. > > NOTE: we remove printing usage information from command body > so it won't print twice. > > Signed-off-by: Eugeniy Paltsev > --- > cmd/mem.c | 9 - > 1 file changed, 4 insertions(+), 5 deletions(-) > Reviewed-by: Simon Glass
[PATCH] BDINFO: ARC: print info about relocations
Print relocation information in bdinfo.
NOTE: this patch changes only ARC part of bdinfo code.
Signed-off-by: Eugeniy Paltsev
---
cmd/bdinfo.c | 4
1 file changed, 4 insertions(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index d6a7175b379..31ec4615641 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -439,20 +439,24 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char
* const argv[])
return 0;
}
#elif defined(CONFIG_ARC)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
bd_t *bd = gd->bd;
print_bi_mem(bd);
+ if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
+ print_num("relocaddr", gd->relocaddr);
+ print_num("reloc off", gd->reloc_off);
+ }
print_eth_ip_addr();
print_baudrate();
return 0;
}
#elif defined(CONFIG_XTENSA)
int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
--
2.21.1
[PATCH 13/14] ARC: HSDK-4xD: use separate config file
HSDK-4xD has quite different environment so let's split
HSDK and HSDK-4xD configs file.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/Kconfig | 3 +-
board/synopsys/hsdk/MAINTAINERS | 2 +
include/configs/hsdk-4xd.h | 120
3 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 include/configs/hsdk-4xd.h
diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig
index 5e23b3229a9..d9c0e27a41d 100644
--- a/board/synopsys/hsdk/Kconfig
+++ b/board/synopsys/hsdk/Kconfig
@@ -7,7 +7,8 @@ config SYS_VENDOR
default "synopsys"
config SYS_CONFIG_NAME
- default "hsdk"
+ default "hsdk" if BOARD_HSDK
+ default "hsdk-4xd" if BOARD_HSDK_4XD
choice
prompt "HSDK board type"
diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
index d385951048f..73f71fd06bc 100644
--- a/board/synopsys/hsdk/MAINTAINERS
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -4,3 +4,5 @@ S: Maintained
F: board/synopsys/hsdk/
F: configs/hsdk_defconfig
F: configs/hsdk_4xd_defconfig
+F: include/configs/hsdk-4xd.h
+F: include/configs/hsdk.h
diff --git a/include/configs/hsdk-4xd.h b/include/configs/hsdk-4xd.h
new file mode 100644
index 000..4628108075e
--- /dev/null
+++ b/include/configs/hsdk-4xd.h
@@ -0,0 +1,120 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev
+ */
+
+#ifndef _CONFIG_HSDK_H_
+#define _CONFIG_HSDK_H_
+
+#include
+
+/*
+ * CPU configuration
+ */
+#define NR_CPUS4
+#define ARC_PERIPHERAL_BASE0xF000
+#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000)
+#define ARC_DWGMAC_BASE(ARC_PERIPHERAL_BASE + 0x18000)
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_MONITOR_BASECONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x8000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE SZ_1G
+
+#define CONFIG_SYS_INIT_SP_ADDR\
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN SZ_2M
+#define CONFIG_SYS_BOOTM_LEN SZ_128M
+#define CONFIG_SYS_LOAD_ADDR 0x8200
+
+/*
+ * UART configuration
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_CLK
+#define CONFIG_SYS_NS16550_MEM32
+
+/*
+ * Ethernet PHY configuration
+ */
+
+/*
+ * USB 1.1 configuration
+ */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+/*
+ * Environment settings
+ */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "upgrade=if mmc rescan && " \
+ "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \
+ "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \
+ "\"Fail to upgrade.\n" \
+ "Do you have u-boot-update.scr and u-boot.head on first (FAT)
SD card partition?\"" \
+ "; fi\0" \
+ "core_mask=0xF\0" \
+ "hsdk_hs45d=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x0; setenv csm_location 0x10; \
+setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs47d=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs47d_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x0; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48=setenv core_mask 0x1; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48_ccm=setenv core_mask 0x2; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \
+setenv core_dccm_1 0x8; setenv non_volatile_limit 0xF;\0" \
+ "hsdk_hs48x2=run hsdk_hs47dx2;\0" \
+ "hsdk_hs47dx2=setenv core_mask 0x3; setenv haps_apb_location 0x1; \
+setenv l2_cache_ena 0x1; setenv icache_ena 0x1; setenv csm_location 0x10; \
+setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \
+setenv core_dccm_0 0x10; setenv non_volatile_
[PATCH 11/14] ARC: HSDK-4xD: add CSM configuration support
Add support for CSM enable/disable and CSM relocation via
hsdk_init command. We allow to relocate CSM to the beginning of
any aperture even if HW support finer granularity.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/arcregs.h | 3 +++
board/synopsys/hsdk/hsdk.c | 27 +++
2 files changed, 30 insertions(+)
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index f3cd4a889ac..516c14e105b 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -51,6 +51,9 @@
#define ARC_AUX_DCCM_BASE 0x18/* DCCM Base Addr ARCv2 */
#define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
+/* CSM auxiliary registers */
+#define ARC_AUX_CSM_ENABLE 0x9A0
+
/* Timer related auxiliary registers */
#define ARC_AUX_TIMER0_CNT 0x21/* Timer 0 count */
#define ARC_AUX_TIMER0_CTRL0x22/* Timer 0 control */
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index b25b1331874..2cbb59d8092 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -80,6 +80,7 @@ struct hsdk_env_common_ctl {
u32_env nvlim;
u32_env icache;
u32_env dcache;
+ u32_env csm_location;
u32_env l2_cache;
};
@@ -132,6 +133,7 @@ static const struct env_map_common env_map_common[] = {
{ "dcache_ena", ENV_HEX, true, 0, 1, _common.dcache },
#if defined(CONFIG_BOARD_HSDK_4XD)
{ "l2_cache_ena", ENV_HEX, true, 0, 1,
_common.l2_cache },
+ { "csm_location", ENV_HEX, true, 0, NO_CCM,
_common.csm_location },
#endif /* CONFIG_BOARD_HSDK_4XD */
{}
};
@@ -299,6 +301,30 @@ static void init_cluster_slc(void)
slc_disable();
}
+#define CREG_CSM_BASE (CREG_BASE + 0x210)
+
+static void init_cluster_csm(void)
+{
+ /* ARC HS38 in HSDK SoC doesn't include CSM */
+ if (!is_board_match_config(T_BOARD_HSDK_4XD))
+ return;
+
+ if (env_common.csm_location.val == NO_CCM) {
+ write_aux_reg(ARC_AUX_CSM_ENABLE, 0);
+ } else {
+ /*
+* CSM base address is 256kByte aligned but we allow to map
+* CSM only to aperture start (256MByte aligned)
+* The field in CREG_CSM_BASE is in 17:2 bits itself so we need
+* to shift it.
+*/
+ u32 csm_base = (env_common.csm_location.val * SZ_1K) << 2;
+
+ write_aux_reg(ARC_AUX_CSM_ENABLE, 1);
+ writel(csm_base, (void __iomem *)CREG_CSM_BASE);
+ }
+}
+
static void init_master_icache(void)
{
if (icache_status()) {
@@ -678,6 +704,7 @@ static void do_init_cluster(void)
* cores.
*/
init_cluster_nvlim();
+ init_cluster_csm();
init_cluster_slc();
}
--
2.21.1
[PATCH 14/14] ARC: HSDK-4xD: make init status resistant to U-boot reloading
Use register instead of static variable to store HSDK init status as
we want to avoid the situation when we reload U-boot via MDB after
previous init is done but HW reset (board reset) isn't done. So
let's store the init status in unused register - CREG_CPU_0_ENTRY
so status will survive after U-boot is reloaded via MDB.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 329427ed4ba..a3e0563ff45 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -42,6 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define CREG_CPU_START_MASK0xF
#define CREG_CPU_START_POL BIT(4)
+#define CREG_CPU_0_ENTRY (CREG_BASE + 0x404)
+
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
#define SDIO_UHS_REG_EXT_DIV_2 (2 << 30)
@@ -969,9 +971,29 @@ U_BOOT_CMD(
"hsdk_go halt - Boot stand-alone application on HSDK, halt CPU just
before application run\n"
);
+/*
+ * We may simply use static variable here to store init status, but we also
want
+ * to avoid the situation when we reload U-boot via MDB after previous
+ * init is done but HW reset (board reset) isn't done. So let's store the
+ * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will
+ * survive after U-boot is reloaded via MDB.
+ */
+#define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY)
+/* must be equal to INIT_MARKER_REGISTER reset value */
+#define INIT_MARKER_PENDING0
+
+static bool init_marker_get(void)
+{
+ return readl(INIT_MARKER_REGISTER) != INIT_MARKER_PENDING;
+}
+
+static void init_mark_done(void)
+{
+ writel(~INIT_MARKER_PENDING, INIT_MARKER_REGISTER);
+}
+
static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const
argv[])
{
- static bool done = false;
int ret;
if (board_mismatch()) {
@@ -980,14 +1002,14 @@ static int do_hsdk_init(cmd_tbl_t *cmdtp, int flag, int
argc, char *const argv[]
}
/* hsdk_init can be run only once */
- if (done) {
+ if (init_marker_get()) {
printf("HSDK HW is already initialized! Please reset the board
if you want to change the configuration.\n");
return CMD_RET_FAILURE;
}
ret = prepare_cpus();
if (!ret)
- done = true;
+ init_mark_done();
return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
}
--
2.21.1
[PATCH 07/14] ARC: HSDK-4xD: print info about HDMI clocks
HSDK-4xD has HDMI working so let's print info about HDMI clocks.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 577893de2a1..45bc5ebe7db 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -985,7 +985,8 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
soc_clk_ctl("eth-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("usb-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("sdio-clk", NULL, CLK_PRINT | CLK_MHZ);
-/* soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ); */
+ if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+ soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
@@ -1003,9 +1004,11 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
printf("\n");
/* HDMI clock domain */
-/* soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ); */
-/* soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ); */
-/* printf("\n"); */
+ if (is_board_match_runtime(T_BOARD_HSDK_4XD)) {
+ soc_clk_ctl("hdmi-pll", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("hdmi-clk", NULL, CLK_PRINT | CLK_MHZ);
+ printf("\n");
+ }
/* TUN clock domain */
soc_clk_ctl("tun-pll", NULL, CLK_PRINT | CLK_MHZ);
--
2.21.1
[PATCH 04/14] ARC: HSDK: split HSDK and HSDK-4xD DTS
Split HSDK and HSDK-4xD device tree files so they can have
different model names.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/Makefile | 2 +-
arch/arc/dts/hsdk-4xd.dts | 12 +++
arch/arc/dts/hsdk-common.dtsi | 150 ++
arch/arc/dts/hsdk.dts | 145 +---
configs/hsdk_4xd_defconfig| 2 +-
5 files changed, 167 insertions(+), 144 deletions(-)
create mode 100644 arch/arc/dts/hsdk-4xd.dts
create mode 100644 arch/arc/dts/hsdk-common.dtsi
diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile
index 4f1e4637ce9..515fe1fe535 100644
--- a/arch/arc/dts/Makefile
+++ b/arch/arc/dts/Makefile
@@ -5,7 +5,7 @@ dtb-$(CONFIG_TARGET_AXS103) += axs103.dtb
dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb
dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb
-dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb
+dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb
dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb
targets += $(dtb-y)
diff --git a/arch/arc/dts/hsdk-4xd.dts b/arch/arc/dts/hsdk-4xd.dts
new file mode 100644
index 000..b245eea7692
--- /dev/null
+++ b/arch/arc/dts/hsdk-4xd.dts
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev
+ */
+/dts-v1/;
+
+#include "hsdk-common.dtsi"
+
+/ {
+ model = "snps,hsdk-4xd";
+};
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
new file mode 100644
index 000..7292a8da514
--- /dev/null
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017-2020 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev
+ */
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include "dt-bindings/clock/snps,hsdk-cgu.h"
+#include "dt-bindings/reset/snps,hsdk-reset.h"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aliases {
+ console =
+ spi0 =
+ };
+
+ cpu_card {
+ core_clk: core_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <5>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clk-fmeas {
+ clocks = <_clk CLK_ARC_PLL>, <_clk CLK_SYS_PLL>,
+<_clk CLK_TUN_PLL>, <_clk CLK_DDR_PLL>,
+<_clk CLK_ARC>, <_clk CLK_HDMI_PLL>,
+<_clk CLK_TUN_TUN>, <_clk CLK_HDMI>,
+<_clk CLK_SYS_APB>, <_clk CLK_SYS_AXI>,
+<_clk CLK_SYS_ETH>, <_clk CLK_SYS_USB>,
+<_clk CLK_SYS_SDIO>, <_clk CLK_SYS_HDMI>,
+<_clk CLK_SYS_GFX_CORE>, <_clk
CLK_SYS_GFX_DMA>,
+<_clk CLK_SYS_GFX_CFG>, <_clk
CLK_SYS_DMAC_CORE>,
+<_clk CLK_SYS_DMAC_CFG>, <_clk
CLK_SYS_SDIO_REF>,
+<_clk CLK_SYS_SPI_REF>, <_clk CLK_SYS_I2C_REF>,
+<_clk CLK_SYS_UART_REF>, <_clk
CLK_SYS_EBI_REF>,
+<_clk CLK_TUN_ROM>, <_clk CLK_TUN_PWM>;
+ clock-names = "cpu-pll", "sys-pll",
+ "tun-pll", "ddr-clk",
+ "cpu-clk", "hdmi-pll",
+ "tun-clk", "hdmi-clk",
+ "apb-clk", "axi-clk",
+ "eth-clk", "usb-clk",
+ "sdio-clk", "hdmi-sys-clk",
+ "gfx-core-clk", "gfx-dma-clk",
+ "gfx-cfg-clk", "dmac-core-clk",
+ "dmac-cfg-clk", "sdio-ref-clk",
+ "spi-clk", "i2c-clk",
+ "uart-clk", "ebi-clk",
+ "rom-clk", "pwm-clk";
+ };
+
+ cgu_clk: cgu-clk@f000 {
+ compatible = "snps,hsdk-cgu-clock";
+ reg = <0xf000 0x10>, <0xf00014B8 0x4>;
+ #clock-cells = <1>;
+ };
+
+ cgu_rst: reset-controller@f8a0 {
+ compatible = "snps,hsdk-reset";
+ #reset-cells = <1>;
+ reg = <0xf8a0 0x4>, <0xfff0 0x4>;
+ };
+
+ uart0: serial0@f0005000 {
+ compatib
[PATCH 10/14] ARC: HSDK-4xD: add support for SLC enable/disable
Add support for SLC enable/disable via hsdk_init command.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index b8b995db47d..b25b1331874 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -80,6 +80,7 @@ struct hsdk_env_common_ctl {
u32_env nvlim;
u32_env icache;
u32_env dcache;
+ u32_env l2_cache;
};
/*
@@ -129,6 +130,9 @@ static const struct env_map_common env_map_common[] = {
{ "non_volatile_limit", ENV_HEX, true, 0, 0xF, _common.nvlim },
{ "icache_ena", ENV_HEX, true, 0, 1, _common.icache },
{ "dcache_ena", ENV_HEX, true, 0, 1, _common.dcache },
+#if defined(CONFIG_BOARD_HSDK_4XD)
+ { "l2_cache_ena", ENV_HEX, true, 0, 1,
_common.l2_cache },
+#endif /* CONFIG_BOARD_HSDK_4XD */
{}
};
@@ -188,6 +192,11 @@ static bool is_board_match_runtime(enum board_type
type_req)
return get_board_type_runtime() == type_req;
}
+static bool is_board_match_config(enum board_type type_req)
+{
+ return get_board_type_config() == type_req;
+}
+
static const char * board_name(enum board_type type)
{
switch (type) {
@@ -278,6 +287,18 @@ static void init_cluster_nvlim(void)
flush_n_invalidate_dcache_all();
}
+static void init_cluster_slc(void)
+{
+ /* ARC HS38 doesn't support SLC disabling */
+ if (!is_board_match_config(T_BOARD_HSDK_4XD))
+ return;
+
+ if (env_common.l2_cache.val)
+ slc_enable();
+ else
+ slc_disable();
+}
+
static void init_master_icache(void)
{
if (icache_status()) {
@@ -657,6 +678,7 @@ static void do_init_cluster(void)
* cores.
*/
init_cluster_nvlim();
+ init_cluster_slc();
}
static int check_master_cpu_id(void)
--
2.21.1
[PATCH 12/14] ARC: HSDK-4xD: tweak memory map
For HSDK-4xD we do additional AXI bridge tweaking while doing
hsdk_init command:
- we shrink IOC region.
- we configure ARC HS CORE SLV1 aperture depending on
haps_apb_location environment variable.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 58 ++
1 file changed, 58 insertions(+)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 2cbb59d8092..329427ed4ba 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -82,6 +82,7 @@ struct hsdk_env_common_ctl {
u32_env dcache;
u32_env csm_location;
u32_env l2_cache;
+ u32_env haps_apb;
};
/*
@@ -134,6 +135,7 @@ static const struct env_map_common env_map_common[] = {
#if defined(CONFIG_BOARD_HSDK_4XD)
{ "l2_cache_ena", ENV_HEX, true, 0, 1,
_common.l2_cache },
{ "csm_location", ENV_HEX, true, 0, NO_CCM,
_common.csm_location },
+ { "haps_apb_location", ENV_HEX, true, 0, 1,
_common.haps_apb },
#endif /* CONFIG_BOARD_HSDK_4XD */
{}
};
@@ -671,6 +673,61 @@ void init_memory_bridge(void)
writel(UPDATE_VAL, CREG_PAE_UPDT);
}
+/*
+ * For HSDK-4xD we do additional AXI bridge tweaking in hsdk_init command:
+ * - we shrink IOC region.
+ * - we configure HS CORE SLV1 aperture depending on haps_apb_location
+ * environment variable.
+ *
+ * As we've already configured AXI bridge in init_memory_bridge we don't
+ * do full configuration here but reconfigure changed part.
+ *
+ * m master AXI_M_m_SLV0AXI_M_m_SLV1AXI_M_m_OFFSET0
AXI_M_m_OFFSET1
+ * 0 HS (CBU)0x 0x6311 0xFEDCBA98
0x0E543210 [haps_apb_location = 0]
+ * 0 HS (CBU)0x 0x6111 0xFEDCBA98
0x06543210 [haps_apb_location = 1]
+ * 1 HS (RTT)0x 0x 0xFEDCBA98
0x76543210
+ * 2 AXI Tunnel 0x 0x 0xFEDCBA98
0x76543210
+ * 3 HDMI-VIDEO 0x 0x 0xFEDCBA98
0x76543210
+ * 4 HDMI-ADUIO 0x 0x 0xFEDCBA98
0x76543210
+ * 5 USB-HOST0x 0x 0xFEDCBA98
0x7654BA98
+ * 6 ETHERNET0x 0x 0xFEDCBA98
0x7654BA98
+ * 7 SDIO0x 0x 0xFEDCBA98
0x7654BA98
+ * 8 GPU 0x 0x 0xFEDCBA98
0x76543210
+ * 9 DMAC (port #1) 0x 0x 0xFEDCBA98
0x76543210
+ * 10 DMAC (port #2) 0x 0x 0xFEDCBA98
0x76543210
+ * 11 DVFS0x 0x6000 0x
0x
+ */
+void tweak_memory_bridge_cfg(void)
+{
+ /*
+* Only HSDK-4xD requre additional AXI bridge tweaking depending on
+* haps_apb_location environment variable
+*/
+ if (!is_board_match_config(T_BOARD_HSDK_4XD))
+ return;
+
+ if (env_common.haps_apb.val) {
+ writel(0x6111, CREG_AXI_M_SLV1(M_HS_CORE));
+ writel(0x06543210, CREG_AXI_M_OFT1(M_HS_CORE));
+ } else {
+ writel(0x6311, CREG_AXI_M_SLV1(M_HS_CORE));
+ writel(0x0E543210, CREG_AXI_M_OFT1(M_HS_CORE));
+ }
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_HS_CORE));
+
+ writel(0x, CREG_AXI_M_SLV1(M_USB_HOST));
+ writel(0x7654BA98, CREG_AXI_M_OFT1(M_USB_HOST));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_USB_HOST));
+
+ writel(0x, CREG_AXI_M_SLV1(M_ETHERNET));;
+ writel(0x7654BA98, CREG_AXI_M_OFT1(M_ETHERNET));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_ETHERNET));
+
+ writel(0x, CREG_AXI_M_SLV1(M_SDIO));
+ writel(0x7654BA98, CREG_AXI_M_OFT1(M_SDIO));
+ writel(UPDATE_VAL, CREG_AXI_M_UPDT(M_SDIO));
+}
+
static void setup_clocks(void)
{
ulong rate;
@@ -706,6 +763,7 @@ static void do_init_cluster(void)
init_cluster_nvlim();
init_cluster_csm();
init_cluster_slc();
+ tweak_memory_bridge_cfg();
}
static int check_master_cpu_id(void)
--
2.21.1
[PATCH 08/14] ARC: HSDK-4xD: drop additional GPU clock info
HSDK-4xD has other GPU type so it consumes only GPU core clock.
Even we have additional GPU clock dividers they are not routed
to anything. So drop information about those additional clocks
in hsdk_clock print_all command.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 45bc5ebe7db..7ba2a56c331 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -988,8 +988,10 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
if (is_board_match_runtime(T_BOARD_HSDK_4XD))
soc_clk_ctl("hdmi-sys-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("gfx-core-clk", NULL, CLK_PRINT | CLK_MHZ);
- soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
- soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+ if (is_board_match_runtime(T_BOARD_HSDK)) {
+ soc_clk_ctl("gfx-dma-clk", NULL, CLK_PRINT | CLK_MHZ);
+ soc_clk_ctl("gfx-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
+ }
soc_clk_ctl("dmac-core-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("dmac-cfg-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("sdio-ref-clk", NULL, CLK_PRINT | CLK_MHZ);
--
2.21.1
[PATCH 06/14] ARC: HSDK-4xD: fix headerize script for HSDK-4xD compatibility
ARC HS CPU in HSDK-4xD has ARC ID = 0x54, so fix headerize script
accordingly.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/config.mk | 12 ++--
board/synopsys/hsdk/headerize-hsdk.py | 2 +-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk
index 1d01ef50379..def944aad2b 100644
--- a/board/synopsys/hsdk/config.mk
+++ b/board/synopsys/hsdk/config.mk
@@ -6,18 +6,26 @@ ifdef CONFIG_BOARD_HSDK
PLATFORM_CPPFLAGS += -mcpu=hs38_linux -mlittle-endian -matomic -mll64 \
-mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
-mfpu=fpud_all
+
+bsp-generate: u-boot u-boot.bin
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
+ --arc-id 0x52 --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+ $(Q)tools/mkimage -T script -C none -n 'uboot update script' \
+ -d $(srctree)/u-boot-update.txt \
+ $(srctree)/u-boot-update.scr &> /dev/null
endif
ifdef CONFIG_BOARD_HSDK_4XD
PLATFORM_CPPFLAGS += -mcpu=hs4x_rel31 -mlittle-endian -matomic -mll64 \
-mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
-mfpu=fpud_all
-endif
bsp-generate: u-boot u-boot.bin
$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
- --arc-id 0x52 --image $(srctree)/u-boot.bin \
+ --arc-id 0x54 --image $(srctree)/u-boot.bin \
--elf $(srctree)/u-boot
$(Q)tools/mkimage -T script -C none -n 'uboot update script' \
-d $(srctree)/u-boot-update.txt \
$(srctree)/u-boot-update.scr &> /dev/null
+endif
diff --git a/board/synopsys/hsdk/headerize-hsdk.py
b/board/synopsys/hsdk/headerize-hsdk.py
index fce749723ed..7b047cf4a38 100644
--- a/board/synopsys/hsdk/headerize-hsdk.py
+++ b/board/synopsys/hsdk/headerize-hsdk.py
@@ -27,7 +27,7 @@ def calc_check_sum(filename):
def arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id):
-if arc_id not in [0x52, 0x53]:
+if arc_id not in [0x52, 0x53, 0x54]:
print("unknown ARC ID: " + hex(arc_id))
sys.exit(2)
--
2.21.1
[PATCH 09/14] ARC: HSDK-4xD: print timer clock value
Print timer clock value in hsdk_clock print_all command.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/hsdk-common.dtsi | 6 --
board/synopsys/hsdk/hsdk.c| 2 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arc/dts/hsdk-common.dtsi b/arch/arc/dts/hsdk-common.dtsi
index 7292a8da514..fd4245e1646 100644
--- a/arch/arc/dts/hsdk-common.dtsi
+++ b/arch/arc/dts/hsdk-common.dtsi
@@ -40,7 +40,8 @@
<_clk CLK_SYS_DMAC_CFG>, <_clk
CLK_SYS_SDIO_REF>,
<_clk CLK_SYS_SPI_REF>, <_clk CLK_SYS_I2C_REF>,
<_clk CLK_SYS_UART_REF>, <_clk
CLK_SYS_EBI_REF>,
-<_clk CLK_TUN_ROM>, <_clk CLK_TUN_PWM>;
+<_clk CLK_TUN_ROM>, <_clk CLK_TUN_PWM>,
+<_clk CLK_TUN_TIMER>;
clock-names = "cpu-pll", "sys-pll",
"tun-pll", "ddr-clk",
"cpu-clk", "hdmi-pll",
@@ -53,7 +54,8 @@
"dmac-cfg-clk", "sdio-ref-clk",
"spi-clk", "i2c-clk",
"uart-clk", "ebi-clk",
- "rom-clk", "pwm-clk";
+ "rom-clk", "pwm-clk",
+ "timer-clk";
};
cgu_clk: cgu-clk@f000 {
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 7ba2a56c331..b8b995db47d 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -1017,6 +1017,8 @@ static int do_hsdk_clock_print_all(cmd_tbl_t *cmdtp, int
flag, int argc,
soc_clk_ctl("tun-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("rom-clk", NULL, CLK_PRINT | CLK_MHZ);
soc_clk_ctl("pwm-clk", NULL, CLK_PRINT | CLK_MHZ);
+ if (is_board_match_runtime(T_BOARD_HSDK_4XD))
+ soc_clk_ctl("timer-clk", NULL, CLK_PRINT | CLK_MHZ);
printf("\n");
return CMD_RET_SUCCESS;
--
2.21.1
[PATCH 03/14] ARC: HSDK-4xD: add initial board support
Add initial HSDK-4xD board support.
The ARC HS4x/HS4xD Development Kit includes a multicore ARC HS4xD-based
chip that integrates a wide range of interfaces including Ethernet,
HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and
GPIO, as well as a Think Silicon GPU.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/Kconfig| 2 +-
board/synopsys/hsdk/Kconfig | 17
board/synopsys/hsdk/MAINTAINERS | 3 +-
board/synopsys/hsdk/config.mk | 8
board/synopsys/hsdk/hsdk.c | 71 -
configs/hsdk_4xd_defconfig | 67 +++
6 files changed, 164 insertions(+), 4 deletions(-)
create mode 100644 configs/hsdk_4xd_defconfig
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 63413d90bb2..6ff201fa816 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -173,7 +173,7 @@ config TARGET_EMSDP
select CPU_ARCEM6
config TARGET_HSDK
- bool "Support Synpsys HS DevelopmentKit board"
+ bool "Support Synopsys HSDK or HSDK-4xD board"
config TARGET_IOT_DEVKIT
bool "Synopsys Brite IoT Development kit"
diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig
index e8c00a6e7d0..5e23b3229a9 100644
--- a/board/synopsys/hsdk/Kconfig
+++ b/board/synopsys/hsdk/Kconfig
@@ -9,4 +9,21 @@ config SYS_VENDOR
config SYS_CONFIG_NAME
default "hsdk"
+choice
+ prompt "HSDK board type"
+ default BOARD_HSDK
+
+config BOARD_HSDK
+ bool "ARC HS Development Kit"
+ help
+ ARC HS Development Kit based on quard core ARC HS38 processor
+
+config BOARD_HSDK_4XD
+ bool "ARC HS4x/HS4xD Development Kit"
+ help
+ ARC HS4x/HS4xD Development Kit based on quard core ARC HS48/HS47D
+ processor
+
+endchoice
+
endif
diff --git a/board/synopsys/hsdk/MAINTAINERS b/board/synopsys/hsdk/MAINTAINERS
index e22bd1e40b2..d385951048f 100644
--- a/board/synopsys/hsdk/MAINTAINERS
+++ b/board/synopsys/hsdk/MAINTAINERS
@@ -1,5 +1,6 @@
-HSDK BOARD
+HSDK BOARDs
M: Eugeniy Paltsev
S: Maintained
F: board/synopsys/hsdk/
F: configs/hsdk_defconfig
+F: configs/hsdk_4xd_defconfig
diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk
index 5ae22fa2b75..1d01ef50379 100644
--- a/board/synopsys/hsdk/config.mk
+++ b/board/synopsys/hsdk/config.mk
@@ -2,9 +2,17 @@
#
# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+ifdef CONFIG_BOARD_HSDK
PLATFORM_CPPFLAGS += -mcpu=hs38_linux -mlittle-endian -matomic -mll64 \
-mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
-mfpu=fpud_all
+endif
+
+ifdef CONFIG_BOARD_HSDK_4XD
+PLATFORM_CPPFLAGS += -mcpu=hs4x_rel31 -mlittle-endian -matomic -mll64 \
+ -mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \
+ -mfpu=fpud_all
+endif
bsp-generate: u-boot u-boot.bin
$(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 67a29e334d7..771f7bbf886 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -154,6 +154,56 @@ static const struct env_map_percpu env_map_go[] = {
{}
};
+enum board_type {
+ T_BOARD_NONE,
+ T_BOARD_HSDK,
+ T_BOARD_HSDK_4XD
+};
+
+static inline enum board_type get_board_type_runtime(void)
+{
+ u32 arc_id = read_aux_reg(ARC_AUX_IDENTITY) & 0xFF;
+
+ if (arc_id == 0x52)
+ return T_BOARD_HSDK;
+ else if (arc_id == 0x54)
+ return T_BOARD_HSDK_4XD;
+ else
+ return T_BOARD_NONE;
+}
+
+static inline enum board_type get_board_type_config(void)
+{
+ if (IS_ENABLED(CONFIG_BOARD_HSDK))
+ return T_BOARD_HSDK;
+ else if (IS_ENABLED(CONFIG_BOARD_HSDK_4XD))
+ return T_BOARD_HSDK_4XD;
+ else
+ return T_BOARD_NONE;
+}
+
+static bool is_board_match_runtime(enum board_type type_req)
+{
+ return get_board_type_runtime() == type_req;
+}
+
+static const char * board_name(enum board_type type)
+{
+ switch (type) {
+ case T_BOARD_HSDK:
+ return "ARC HS Development Kit";
+ case T_BOARD_HSDK_4XD:
+ return "ARC HS4x/HS4xD Development Kit";
+ default:
+ return "?";
+ }
+}
+
+static bool board_mismatch(void)
+{
+ return get_board_type_config() != get_board_type_runtime();
+}
+
static void sync_cross_cpu_data(void)
{
u32 value;
@@ -221,7 +271,9 @@ static void init_cluster_nvlim(void)
flush_dcache_all();
write_aux_reg(ARC_AUX_NON_VOLATILE_LIMIT, val);
- write_aux_reg(AUX_AUX_CACHE_LIMIT, val);
+ /* AUX_AUX_CACHE_LIMIT reg is missing starting from HS48 */
[PATCH 05/14] ARC: HSDK-4xD: use active low polarity of cpu_start pulse
Add quirk for HSDK-4xD - due to HW issues HSDK can use any pulse
polarity but HSDK-4xD require active low polarity of cpu_start pulse.
So use low polarity of cpu_start pulse for both board.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/hsdk.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 771f7bbf886..577893de2a1 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -40,6 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
#define CREG_CPU_START (CREG_BASE + 0x400)
#define CREG_CPU_START_MASK0xF
+#define CREG_CPU_START_POL BIT(4)
#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
#define SDIO_UHS_REG_EXT (SDIO_BASE + 0x108)
@@ -331,25 +332,36 @@ static inline void halt_this_cpu(void)
__builtin_arc_flag(1);
}
-static void smp_kick_cpu_x(u32 cpu_id)
+static u32 get_masked_cpu_ctart_reg(void)
{
int cmd = readl((void __iomem *)CREG_CPU_START);
+ /*
+* Quirk for HSDK-4xD - due to HW issues HSDK can use any pulse polarity
+* and HSDK-4xD require active low polarity of cpu_start pulse.
+*/
+ cmd &= ~CREG_CPU_START_POL;
+
+ cmd &= ~CREG_CPU_START_MASK;
+
+ return cmd;
+}
+
+static void smp_kick_cpu_x(u32 cpu_id)
+{
+ int cmd;
+
if (cpu_id > NR_CPUS)
return;
- cmd &= ~CREG_CPU_START_MASK;
+ cmd = get_masked_cpu_ctart_reg();
cmd |= (1 << cpu_id);
writel(cmd, (void __iomem *)CREG_CPU_START);
}
static u32 prepare_cpu_ctart_reg(void)
{
- int cmd = readl((void __iomem *)CREG_CPU_START);
-
- cmd &= ~CREG_CPU_START_MASK;
-
- return cmd | env_common.core_mask.val;
+ return get_masked_cpu_ctart_reg() | env_common.core_mask.val;
}
/* slave CPU entry for configuration */
--
2.21.1
[PATCH 01/14] ARC: ARCv2: handle DSP presence in HW
In case of DSP extension presence in HW some instructions
(related to integer multiply, multiply-accumulate, and divide
operation) executes on this DSP execution unit. So their
execution will depend on dsp configuration register (DSP_CTRL)
As we want these instructions to execute the same way regardless
of DSP presence we need to set DSP_CTRL properly.
NOTE:
we do the same adjustments in Linux kernel, see in kernel tree:
commit 4827d0cf744e ("ARC: handle DSP presence in HW")
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/arcregs.h | 1 +
arch/arc/lib/start.S | 15 +++
2 files changed, 16 insertions(+)
diff --git a/arch/arc/include/asm/arcregs.h b/arch/arc/include/asm/arcregs.h
index fff6591c681..f3cd4a889ac 100644
--- a/arch/arc/include/asm/arcregs.h
+++ b/arch/arc/include/asm/arcregs.h
@@ -100,6 +100,7 @@
/* DSP-extensions related auxiliary registers */
#define ARC_AUX_DSP_BUILD 0x7A
+#define ARC_AUX_DSP_CTRL 0x59F
/* ARC Subsystems related auxiliary registers */
#define ARC_AUX_SUBSYS_BUILD 0xF0
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index 8c744f5be7f..016ae85be23 100644
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -61,6 +61,21 @@ ENTRY(_start)
1:
#endif
+#ifdef CONFIG_ISA_ARCV2
+ ; In case of DSP extension presence in HW some instructions
+ ; (related to integer multiply, multiply-accumulate, and divide
+ ; operation) executes on this DSP execution unit. So their
+ ; execution will depend on dsp configuration register (DSP_CTRL)
+ ; As we want these instructions to execute the same way regardless
+ ; of DSP presence we need to set DSP_CTRL properly.
+ lr r5, [ARC_AUX_DSP_BUILD]
+ bmskr5, r5, 7
+ breqr5, 0, 1f
+ mov r5, 0
+ sr r5, [ARC_AUX_DSP_CTRL]
+1:
+#endif
+
#ifdef __ARC_UNALIGNED__
/*
* Enable handling of unaligned access in the CPU as by default
--
2.21.1
[PATCH 02/14] ARC: HSDK: CGU: add support for timer clock
Add support for additional timer clock which belongs to tunnel
domain.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c| 9 ++---
include/dt-bindings/clock/snps,hsdk-cgu.h | 5 +++--
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 6eaafdeaf99..3035c5fb38e 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -67,6 +67,7 @@
#define CGU_TUN_IDIV_TUN 0x380
#define CGU_TUN_IDIV_ROM 0x390
#define CGU_TUN_IDIV_PWM 0x3A0
+#define CGU_TUN_IDIV_TIMER 0x3B0
#define CGU_HDMI_IDIV_APB 0x480
#define CGU_SYS_IDIV_APB 0x180
#define CGU_SYS_IDIV_AXI 0x190
@@ -123,12 +124,12 @@
#define MIN_PLL_RATE 1 /* 100 MHz */
#define PARENT_RATE_33 /* fixed clock - xtal */
#define PARENT_RATE_27 2700 /* fixed clock - xtal */
-#define CGU_MAX_CLOCKS 26
+#define CGU_MAX_CLOCKS 27
#define CGU_SYS_CLOCKS 16
#define MAX_AXI_CLOCKS 4
-#define CGU_TUN_CLOCKS 3
+#define CGU_TUN_CLOCKS 4
#define MAX_TUN_CLOCKS 6
struct hsdk_tun_idiv_cfg {
@@ -147,7 +148,8 @@ static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
{ 6, 6, 6, 6, 75000, 6 }, {
{ CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
{ CGU_TUN_IDIV_ROM, { 4,4, 4, 4, 5, 4 } },
- { CGU_TUN_IDIV_PWM, { 8,8, 8, 8, 10, 8 } }
+ { CGU_TUN_IDIV_PWM, { 8,8, 8, 8, 10, 8 } },
+ { CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } }
}
};
@@ -316,6 +318,7 @@ static const struct hsdk_cgu_clock_map clock_map[] = {
{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, _pll_dat, idiv_get,
tun_clk_set, idiv_off },
{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, _pll_dat, idiv_get, idiv_set,
idiv_off },
{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, _pll_dat, idiv_get, idiv_set,
idiv_off },
+ { CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, _pll_dat, idiv_get, idiv_set,
idiv_off },
{ CGU_HDMI_PLL, 0, 0, _pll_dat, pll_get, pll_set, NULL },
{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, _pll_dat, idiv_get,
idiv_set, idiv_off }
};
diff --git a/include/dt-bindings/clock/snps,hsdk-cgu.h
b/include/dt-bindings/clock/snps,hsdk-cgu.h
index 2cfe34eb35f..1ce7661cd93 100644
--- a/include/dt-bindings/clock/snps,hsdk-cgu.h
+++ b/include/dt-bindings/clock/snps,hsdk-cgu.h
@@ -36,7 +36,8 @@
#define CLK_TUN_TUN21
#define CLK_TUN_ROM22
#define CLK_TUN_PWM23
-#define CLK_HDMI_PLL 24
-#define CLK_HDMI 25
+#define CLK_TUN_TIMER 24
+#define CLK_HDMI_PLL 25
+#define CLK_HDMI 26
#endif /* __DT_BINDINGS_CLK_HSDK_CGU_H_ */
--
2.21.1
[PATCH 00/14] ARC: add HSDK-4xD board support
Eugeniy Paltsev (14): ARC: ARCv2: handle DSP presence in HW ARC: HSDK: CGU: add support for timer clock ARC: HSDK-4xD: add initial board support ARC: HSDK: split HSDK and HSDK-4xD DTS ARC: HSDK-4xD: use active low polarity of cpu_start pulse ARC: HSDK-4xD: fix headerize script for HSDK-4xD compatibility ARC: HSDK-4xD: print info about HDMI clocks ARC: HSDK-4xD: drop additional GPU clock info ARC: HSDK-4xD: print timer clock value ARC: HSDK-4xD: add support for SLC enable/disable ARC: HSDK-4xD: add CSM configuration support ARC: HSDK-4xD: tweak memory map ARC: HSDK-4xD: use separate config file ARC: HSDK-4xD: make init status resistant to U-boot reloading arch/arc/Kconfig | 2 +- arch/arc/dts/Makefile | 2 +- arch/arc/dts/hsdk-4xd.dts | 12 ++ arch/arc/dts/hsdk-common.dtsi | 152 + arch/arc/dts/hsdk.dts | 145 + arch/arc/include/asm/arcregs.h| 4 + arch/arc/lib/start.S | 15 ++ board/synopsys/hsdk/Kconfig | 20 +- board/synopsys/hsdk/MAINTAINERS | 5 +- board/synopsys/hsdk/config.mk | 16 ++ board/synopsys/hsdk/headerize-hsdk.py | 2 +- board/synopsys/hsdk/hsdk.c| 251 -- configs/hsdk_4xd_defconfig| 67 ++ drivers/clk/clk-hsdk-cgu.c| 9 +- include/configs/hsdk-4xd.h| 120 +++ include/dt-bindings/clock/snps,hsdk-cgu.h | 5 +- 16 files changed, 657 insertions(+), 170 deletions(-) create mode 100644 arch/arc/dts/hsdk-4xd.dts create mode 100644 arch/arc/dts/hsdk-common.dtsi create mode 100644 configs/hsdk_4xd_defconfig create mode 100644 include/configs/hsdk-4xd.h -- 2.21.1
[PATCH] ARC: AXS10x: cleanup kconfig
As we've dropped NAND support for AXS101 and AXS103
see commit 4f5e552d95bb ("ARC: AXS10x: drop NAND support")
we don't need bounce buffer anymore.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index ea875711e70..6ff201fa816 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -164,11 +164,9 @@ config TARGET_NSIM
config TARGET_AXS101
bool "Support Synopsys Designware SDP board AXS101"
- select BOUNCE_BUFFER if CMD_NAND
config TARGET_AXS103
bool "Support Synopsys Designware SDP board AXS103"
- select BOUNCE_BUFFER if CMD_NAND
config TARGET_EMSDP
bool "Synopsys EM Software Development Platform"
--
2.21.1
[PATCH] ARC: HSDK: CGU: fix tunnel clock calculation
We set wrong tunnel PLL frequency when we request 125MHz tunnel clock.
Fix that.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 4637b9fdf15..6eaafdeaf99 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -144,7 +144,7 @@ struct hsdk_tun_clk_cfg {
static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
{ 2500, 5000, 7500, 1, 12500, 15000 },
- { 6, 6, 6, 6, 7, 6 }, {
+ { 6, 6, 6, 6, 75000, 6 }, {
{ CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
{ CGU_TUN_IDIV_ROM, { 4,4, 4, 4, 5, 4 } },
{ CGU_TUN_IDIV_PWM, { 8,8, 8, 8, 10, 8 } }
@@ -205,6 +205,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
{ 5, 0, 14, 1, 0 },
{ 6, 0, 17, 1, 0 },
{ 7, 0, 20, 1, 0 },
+ { 75000, 1, 44, 1, 0 },
{ 8, 0, 23, 1, 0 },
{ 9, 1, 26, 0, 0 },
{ 10, 1, 29, 0, 0 },
--
2.21.1
[PATCH v2 2/3] ARC: IO: add compiler barriers to IO accessors
We must use compiler barriers in C-version read/write IO accessors
before and after operation (read or write) so it won't be reordered
by compiler.
Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors")
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/io.h | 31 ---
1 file changed, 20 insertions(+), 11 deletions(-)
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 1f1ae889f3a..50c88456002 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -9,6 +9,13 @@
#include
#include
+
+/*
+ * Compiler barrier. It prevents compiler from reordering instructions before
+ * and after it. It doesn't prevent HW (CPU) from any reordering though.
+ */
+#define __comp_b() asm volatile("" : : : "memory")
+
#ifdef __ARCHS__
/*
@@ -45,8 +52,8 @@
#define __iormb() rmb()
#define __iowmb() wmb()
#else
-#define __iormb() asm volatile("" : : : "memory")
-#define __iowmb() asm volatile("" : : : "memory")
+#define __iormb() __comp_b()
+#define __iowmb() __comp_b()
#endif
static inline void sync(void)
@@ -58,16 +65,18 @@ static inline void sync(void)
* We must use 'volatile' in C-version read/write IO accessors implementation
* to avoid merging several reads (writes) into one read (write), or optimizing
* them out by compiler.
+ * We must use compiler barriers before and after operation (read or write) so
+ * it won't be reordered by compiler.
*/
-#define __arch_getb(a) (*(volatile u8 *)(a))
-#define __arch_getw(a) (*(volatile u16 *)(a))
-#define __arch_getl(a) (*(volatile u32 *)(a))
-#define __arch_getq(a) (*(volatile u64 *)(a))
-
-#define __arch_putb(v, a) (*(volatile u8 *)(a) = (v))
-#define __arch_putw(v, a) (*(volatile u16 *)(a) = (v))
-#define __arch_putl(v, a) (*(volatile u32 *)(a) = (v))
-#define __arch_putq(v, a) (*(volatile u64 *)(a) = (v))
+#define __arch_getb(a) ({ u8 __v; __comp_b(); __v = *(volatile u8
*)(a); __comp_b(); __v; })
+#define __arch_getw(a) ({ u16 __v; __comp_b(); __v = *(volatile u16
*)(a); __comp_b(); __v; })
+#define __arch_getl(a) ({ u32 __v; __comp_b(); __v = *(volatile u32
*)(a); __comp_b(); __v; })
+#define __arch_getq(a) ({ u64 __v; __comp_b(); __v = *(volatile u64
*)(a); __comp_b(); __v; })
+
+#define __arch_putb(v, a) ({ __comp_b(); *(volatile u8 *)(a) = (v);
__comp_b(); })
+#define __arch_putw(v, a) ({ __comp_b(); *(volatile u16 *)(a) = (v);
__comp_b(); })
+#define __arch_putl(v, a) ({ __comp_b(); *(volatile u32 *)(a) = (v);
__comp_b(); })
+#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v);
__comp_b(); })
#define __raw_writeb(v, a) __arch_putb(v, a)
--
2.21.1
[PATCH v2 1/3] ARC: IO: add volatile to accessors
We must use 'volatile' in C-version read/write IO accessors
implementation to avoid merging several reads (writes) into
one read (write), or optimizing them out by compiler.
Fixes commit 07906b3dad15 ("ARC: Switch to generic accessors")
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/io.h | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 70d050590de..1f1ae889f3a 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -54,15 +54,21 @@ static inline void sync(void)
/* Not yet implemented */
}
-#define __arch_getb(a) (*(unsigned char *)(a))
-#define __arch_getw(a) (*(unsigned short *)(a))
-#define __arch_getl(a) (*(unsigned int *)(a))
-#define __arch_getq(a) (*(unsigned long long *)(a))
-
-#define __arch_putb(v, a) (*(unsigned char *)(a) = (v))
-#define __arch_putw(v, a) (*(unsigned short *)(a) = (v))
-#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
-#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
+/*
+ * We must use 'volatile' in C-version read/write IO accessors implementation
+ * to avoid merging several reads (writes) into one read (write), or optimizing
+ * them out by compiler.
+ */
+#define __arch_getb(a) (*(volatile u8 *)(a))
+#define __arch_getw(a) (*(volatile u16 *)(a))
+#define __arch_getl(a) (*(volatile u32 *)(a))
+#define __arch_getq(a) (*(volatile u64 *)(a))
+
+#define __arch_putb(v, a) (*(volatile u8 *)(a) = (v))
+#define __arch_putw(v, a) (*(volatile u16 *)(a) = (v))
+#define __arch_putl(v, a) (*(volatile u32 *)(a) = (v))
+#define __arch_putq(v, a) (*(volatile u64 *)(a) = (v))
+
#define __raw_writeb(v, a) __arch_putb(v, a)
#define __raw_writew(v, a) __arch_putw(v, a)
--
2.21.1
[PATCH v2 3/3] ARC: IO: add MB for __raw_* memory accessors
We add memory barriers for __raw_readX / __raw_writeX accessors same
way as it is done for readX and writeX accessors as lots of U-boot
driver uses __raw_readX / __raw_writeX instead of proper accessor
with barrier.
It will save us from lot's of debugging in the future and it is OK
as U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not
super fast as we only being executed once.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/io.h | 58 +++
1 file changed, 35 insertions(+), 23 deletions(-)
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 50c88456002..e770a1fe4b8 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -79,21 +79,29 @@ static inline void sync(void)
#define __arch_putq(v, a) ({ __comp_b(); *(volatile u64 *)(a) = (v);
__comp_b(); })
-#define __raw_writeb(v, a) __arch_putb(v, a)
-#define __raw_writew(v, a) __arch_putw(v, a)
-#define __raw_writel(v, a) __arch_putl(v, a)
-#define __raw_writeq(v, a) __arch_putq(v, a)
+/*
+ * We add memory barriers for __raw_readX / __raw_writeX accessors same way as
+ * it is done for readX and writeX accessors as lots of U-boot driver uses
+ * __raw_readX / __raw_writeX instead of proper accessor with barrier.
+ */
+#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })
+#define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); })
+#define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); })
+#define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); })
+
+#define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
+#define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
+#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
-#define __raw_readb(a) __arch_getb(a)
-#define __raw_readw(a) __arch_getw(a)
-#define __raw_readl(a) __arch_getl(a)
-#define __raw_readq(a) __arch_getq(a)
static inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
{
u8 *buf = (uint8_t *)data;
+ __iowmb();
+
while (bytelen--)
__arch_putb(*buf++, addr);
}
@@ -103,6 +111,8 @@ static inline void __raw_writesw(unsigned long addr, const
void *data,
{
u16 *buf = (uint16_t *)data;
+ __iowmb();
+
while (wordlen--)
__arch_putw(*buf++, addr);
}
@@ -112,6 +122,8 @@ static inline void __raw_writesl(unsigned long addr, const
void *data,
{
u32 *buf = (uint32_t *)data;
+ __iowmb();
+
while (longlen--)
__arch_putl(*buf++, addr);
}
@@ -122,6 +134,8 @@ static inline void __raw_readsb(unsigned long addr, void
*data, int bytelen)
while (bytelen--)
*buf++ = __arch_getb(addr);
+
+ __iormb();
}
static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
@@ -130,6 +144,8 @@ static inline void __raw_readsw(unsigned long addr, void
*data, int wordlen)
while (wordlen--)
*buf++ = __arch_getw(addr);
+
+ __iormb();
}
static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
@@ -138,6 +154,8 @@ static inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
while (longlen--)
*buf++ = __arch_getl(addr);
+
+ __iormb();
}
/*
@@ -145,21 +163,15 @@ static inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
* ordering rules but do not guarantee any ordering relative to Normal memory
* accesses.
*/
-#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
-#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
- __raw_readw(c)); __r; })
-#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
- __raw_readl(c)); __r; })
-#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
- __raw_readq(c)); __r; })
-
-#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
-#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
- cpu_to_le16(v), (c)))
-#define writel_relaxed(v, c) ((void)__raw_writel((__force u32) \
- cpu_to_le32(v), (c)))
-#define writeq_relaxed(v, c) ((void)__raw_writeq((__force u64) \
- cpu_to_le64(v), (c)))
+#define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; })
+#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force
__le16)__arch_getw(c)); __r; })
+#define
[PATCH v2 0/3] ARC: IO: rework IO accessors
Fixing of DW SPI which was broken by
commit 07906b3dad15 ("ARC: Switch to generic accessors")
lead me to several fixes in ARC IO accessors code.
Eugeniy Paltsev (3):
ARC: IO: add volatile to accessors
ARC: IO: add compiler barriers to IO accessors
ARC: IO: add MB for __raw_* memory accessors
arch/arc/include/asm/io.h | 93 +--
1 file changed, 60 insertions(+), 33 deletions(-)
--
2.21.1
[PATCH] ARC: fix up memory accessors
Commit 07906b3dad15 ("ARC: Switch to generic accessors") introduces
a regression as it removes compiler barriers from __raw_readX \
__raw_writeX accessors. It breaks DW SPI driver (and possibly others)
Let's fix that and return compiler barriers back. However that's
not all. Let's add read/write barriers to __raw_readX \ __raw_writeX
accessors as lots of drivers use them instead of regular readX \
writeX accessors.
It will save us from lot's of debugging in the future and it is OK
as U-Boot is not that performance oriented as real run-time
software like OS or user bare-metal app so we may afford being not
super fast as we only being executed once.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/io.h | 49 ++-
1 file changed, 33 insertions(+), 16 deletions(-)
diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h
index 70d050590de..46cf11ff893 100644
--- a/arch/arc/include/asm/io.h
+++ b/arch/arc/include/asm/io.h
@@ -64,21 +64,28 @@ static inline void sync(void)
#define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
#define __arch_putq(v, a) (*(unsigned long long *)(a) = (v))
-#define __raw_writeb(v, a) __arch_putb(v, a)
-#define __raw_writew(v, a) __arch_putw(v, a)
-#define __raw_writel(v, a) __arch_putl(v, a)
-#define __raw_writeq(v, a) __arch_putq(v, a)
+/*
+ * We add memory barriers for __raw_* operations as lots of U-boot driver uses
+ * then instead of proper accessor with barrier.
+ */
+#define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); })
+#define __raw_writew(v, c) ({ __iowmb(); __arch_putw(v, c); })
+#define __raw_writel(v, c) ({ __iowmb(); __arch_putl(v, c); })
+#define __raw_writeq(v, c) ({ __iowmb(); __arch_putq(v, c); })
+
+#define __raw_readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
+#define __raw_readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
+#define __raw_readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
+#define __raw_readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; })
-#define __raw_readb(a) __arch_getb(a)
-#define __raw_readw(a) __arch_getw(a)
-#define __raw_readl(a) __arch_getl(a)
-#define __raw_readq(a) __arch_getq(a)
static inline void __raw_writesb(unsigned long addr, const void *data,
int bytelen)
{
u8 *buf = (uint8_t *)data;
+ __iowmb();
+
while (bytelen--)
__arch_putb(*buf++, addr);
}
@@ -88,6 +95,8 @@ static inline void __raw_writesw(unsigned long addr, const
void *data,
{
u16 *buf = (uint16_t *)data;
+ __iowmb();
+
while (wordlen--)
__arch_putw(*buf++, addr);
}
@@ -97,6 +106,8 @@ static inline void __raw_writesl(unsigned long addr, const
void *data,
{
u32 *buf = (uint32_t *)data;
+ __iowmb();
+
while (longlen--)
__arch_putl(*buf++, addr);
}
@@ -107,6 +118,8 @@ static inline void __raw_readsb(unsigned long addr, void
*data, int bytelen)
while (bytelen--)
*buf++ = __arch_getb(addr);
+
+ __iormb();
}
static inline void __raw_readsw(unsigned long addr, void *data, int wordlen)
@@ -115,6 +128,8 @@ static inline void __raw_readsw(unsigned long addr, void
*data, int wordlen)
while (wordlen--)
*buf++ = __arch_getw(addr);
+
+ __iormb();
}
static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
@@ -123,6 +138,8 @@ static inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
while (longlen--)
*buf++ = __arch_getl(addr);
+
+ __iormb();
}
/*
@@ -130,20 +147,20 @@ static inline void __raw_readsl(unsigned long addr, void
*data, int longlen)
* ordering rules but do not guarantee any ordering relative to Normal memory
* accesses.
*/
-#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
+#define readb_relaxed(c) ({ u8 __r = __arch_getb(c); __r; })
#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
- __raw_readw(c)); __r; })
+ __arch_getw(c)); __r; })
#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
- __raw_readl(c)); __r; })
+ __arch_getl(c)); __r; })
#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64) \
- __raw_readq(c)); __r; })
+ __arch_getq(c)); __r; })
-#define writeb_relaxed(v, c) ((void)__raw_writeb((v), (c)))
-#define writew_relaxed(v, c) ((void)__raw_writew((__force u16) \
+#define writeb_relaxed(v, c) ((void)__arch_putb((v), (c)))
+#define writew_relaxed(v, c) ((void)_
[PATCH] CMD: random: fix return code
As of today 'random' command return 1 (CMD_RET_FAILURE) in case
of successful execution and 0 (CMD_RET_SUCCESS) in case of bad
arguments. Fix that.
NOTE: we remove printing usage information from command body
so it won't print twice.
Signed-off-by: Eugeniy Paltsev
---
cmd/mem.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/cmd/mem.c b/cmd/mem.c
index 6d54f195272..6b4897dfd94 100644
--- a/cmd/mem.c
+++ b/cmd/mem.c
@@ -1102,10 +1102,8 @@ static int do_random(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])
unsigned char *buf8;
unsigned int i;
- if (argc < 3 || argc > 4) {
- printf("usage: %s []\n", argv[0]);
- return 0;
- }
+ if (argc < 3 || argc > 4)
+ return CMD_RET_USAGE;
len = simple_strtoul(argv[2], NULL, 16);
addr = simple_strtoul(argv[1], NULL, 16);
@@ -1132,7 +1130,8 @@ static int do_random(cmd_tbl_t *cmdtp, int flag, int
argc, char * const argv[])
unmap_sysmem(start);
printf("%lu bytes filled with random data\n", len);
- return 1;
+
+ return CMD_RET_SUCCESS;
}
#endif
--
2.21.1
Re: [PATCH v1 6/8] spi: dw: Add mem_ops
Hi Sean,
even after fixing build errors with this patch I still have issues with
communications to flash IC.
Now it is detected correctly (JEDEC id is valid) but I have issues with read or
write.
I need to look to that more intently.
---
Eugeniy Paltsev
From: Sean Anderson
Sent: Saturday, March 7, 2020 00:20
To: Eugeniy Paltsev; u-boot@lists.denx.de
Cc: Simon Glass; Jagan Teki; Alexey Brodkin
Subject: Re: [PATCH v1 6/8] spi: dw: Add mem_ops
On 3/6/20 12:03 PM, Eugeniy Paltsev wrote:
> Hi Sean,
>
> I've tested the SPI (with SPI flash) on HSDK board (which have DW SPI) with
> your changes.
> It completely break SPI on HSDK:
>
> ->8--
> # sf probe
> unrecognized JEDEC id bytes: ff, ff, ff
> Failed to initialize SPI flash at 0:0 (error -2)
> ->8--
>
> Tested from maix_spi HEAD (e338571bf528f58b3ced7fbd0c1f5d923caa1cfd)
>
> ---
> Eugeniy Paltsev
Actually, it just occured to me that I did not add support for a gpio cs
to the xfer function, so it's likely that the chip is not enabling the
cs. Can you try testing with the following patch
---
drivers/spi/designware_spi.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 298d1dbab5..a4e3dbd948 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -517,6 +517,8 @@ static int dw_spi_exec_op(struct spi_slave *slave, const
struct spi_mem_op *op)
if (op->dummy.nbytes)
memset(op_buf + pos, 0xff, op->dummy.nbytes);
+ external_cs_manage(dev, false);
+
priv->tx = _buf;
priv->tx_end = priv->tx + op_len;
priv->rx = NULL;
@@ -586,6 +588,8 @@ static int dw_spi_exec_op(struct spi_slave *slave, const
struct spi_mem_op *op)
}
dw_write(priv, DW_SPI_SER, 0);
+ external_cs_manage(dev, true);
+
debug("%s: %u bytes xfered\n", __func__, op->data.nbytes);
return ret;
}
--
2.25.0
[PATCH] ARC: HSDK: Enable on-chip reset controller
As the driver of on-chip reset controller became available
we are ready to enable it.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/hsdk.dts | 7 +++
configs/hsdk_defconfig | 1 +
2 files changed, 8 insertions(+)
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 34ef3a620a3..cf2ce8a1f6c 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -6,6 +6,7 @@
#include "skeleton.dtsi"
#include "dt-bindings/clock/snps,hsdk-cgu.h"
+#include "dt-bindings/reset/snps,hsdk-reset.h"
/ {
model = "snps,hsdk";
@@ -62,6 +63,12 @@
#clock-cells = <1>;
};
+ cgu_rst: reset-controller@f8a0 {
+ compatible = "snps,hsdk-reset";
+ #reset-cells = <1>;
+ reg = <0xf8a0 0x4>, <0xfff0 0x4>;
+ };
+
uart0: serial0@f0005000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0005000 0x1000>;
diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index 4830158d55a..84b22ed7c04 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_MII=y
+CONFIG_DM_RESET=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
--
2.21.1
[PATCH 1/2] ARC: CACHE: add support for SL$ disable
Since version 3.0 ARC HS supports SL$ (L2 system level cache)
disable. So add support for SL$ disable/enable to code.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/include/asm/cache.h | 7 +++
arch/arc/lib/cache.c | 114 ---
2 files changed, 114 insertions(+), 7 deletions(-)
diff --git a/arch/arc/include/asm/cache.h b/arch/arc/include/asm/cache.h
index 0fdcf2d2dd5..ab61846b5ab 100644
--- a/arch/arc/include/asm/cache.h
+++ b/arch/arc/include/asm/cache.h
@@ -40,6 +40,13 @@ static const inline int is_ioc_enabled(void)
return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
}
+/*
+ * We export SLC control functions to use them in platform configuration code.
+ * They maust not be used in any generic code!
+ */
+void slc_enable(void);
+void slc_disable(void);
+
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARC_CACHE_H */
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 1340776c669..c42723daeb2 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -89,8 +89,7 @@
*
* [ NOTE 2 ]:
* As of today we only support the following cache configurations on ARC.
- * Other configurations may exist in HW (for example, since version 3.0 HS
- * supports SL$ (L2 system level cache) disable) but we don't support it in SW.
+ * Other configurations may exist in HW but we don't support it in SW.
* Configuration 1:
*__
* | |
@@ -120,7 +119,8 @@
* | |
* | L2 (SL$) |
* |__|
- * always must be on
+ * always on (ARCv2, HS < 3.0)
+ * on/off(ARCv2, HS >= 3.0)
*___|__|
* | |
* | main memory|
@@ -178,6 +178,8 @@ DECLARE_GLOBAL_DATA_PTR;
static inlined_cachefunc void __ic_entire_invalidate(void);
static inlined_cachefunc void __dc_entire_op(const int cacheop);
+static inlined_cachefunc void __slc_entire_op(const int op);
+static inline bool ioc_enabled(void);
static inline bool pae_exists(void)
{
@@ -238,6 +240,70 @@ static inlined_cachefunc bool slc_exists(void)
return false;
}
+enum slc_dis_status {
+ ST_SLC_MISSING = 0,
+ ST_SLC_NO_DISABLE_CTRL,
+ ST_SLC_DISABLE_CTRL
+};
+
+/*
+ * ARCv1 -> ST_SLC_MISSING
+ * ARCv2 && SLC absent -> ST_SLC_MISSING
+ * ARCv2 && SLC exists && SLC version <= 2 -> ST_SLC_NO_DISABLE_CTRL
+ * ARCv2 && SLC exists && SLC version > 2-> ST_SLC_DISABLE_CTRL
+ */
+static inlined_cachefunc enum slc_dis_status slc_disable_supported(void)
+{
+ if (is_isa_arcv2()) {
+ union bcr_generic sbcr;
+
+ sbcr.word = read_aux_reg(ARC_BCR_SLC);
+ if (sbcr.fields.ver == 0)
+ return ST_SLC_MISSING;
+ else if (sbcr.fields.ver <= 2)
+ return ST_SLC_NO_DISABLE_CTRL;
+ else
+ return ST_SLC_DISABLE_CTRL;
+ }
+
+ return ST_SLC_MISSING;
+}
+
+static inlined_cachefunc bool __slc_enabled(void)
+{
+ return !(read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_DIS);
+}
+
+static inlined_cachefunc void __slc_enable(void)
+{
+ unsigned int ctrl;
+
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
+ ctrl &= ~SLC_CTRL_DIS;
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
+}
+
+static inlined_cachefunc void __slc_disable(void)
+{
+ unsigned int ctrl;
+
+ ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
+ ctrl |= SLC_CTRL_DIS;
+ write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
+}
+
+static inlined_cachefunc bool slc_enabled(void)
+{
+ enum slc_dis_status slc_status = slc_disable_supported();
+
+ if (slc_status == ST_SLC_MISSING)
+ return false;
+ else if (slc_status == ST_SLC_NO_DISABLE_CTRL)
+ return true;
+ else
+ return __slc_enabled();
+}
+
static inlined_cachefunc bool slc_data_bypass(void)
{
/*
@@ -247,6 +313,39 @@ static inlined_cachefunc bool slc_data_bypass(void)
return !dcache_enabled();
}
+void slc_enable(void)
+{
+ if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
+ return;
+
+ if (__slc_enabled())
+ return;
+
+ __slc_enable();
+}
+
+/* TODO: warn if we are not able to disable SLC */
+void slc_disable(void)
+{
+ if (slc_disable_supported() != ST_SLC_DISABLE_CTRL)
+ return;
+
+ /* we don't support SLC disabling if we use IOC */
+ if (ioc_enabled())
+ return;
+
+ if (!__slc_enabled())
+ return;
+
+ /*
+* We need to flush L1D$ to guarantee that we won't have any
+* writeback operations during SLC disabling.
+*/
+ __dc_entire_op(OP_FLUSH);
+ __slc_entire_op(OP_FLUS
[PATCH 0/2] ARC cache subsystem updates
Eugeniy Paltsev (2): ARC: CACHE: add support for SL$ disable ARC: CACHE: mark IOC helper functions as inlined_cachefunc arch/arc/include/asm/cache.h | 7 +++ arch/arc/lib/cache.c | 118 --- 2 files changed, 116 insertions(+), 9 deletions(-) -- 2.21.1
[PATCH 2/2] ARC: CACHE: mark IOC helper functions as inlined_cachefunc
Force inlining of IOC related functions used in other cache
functions. This is preventive change.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/lib/cache.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index c42723daeb2..8a1d67870a8 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -179,7 +179,7 @@ DECLARE_GLOBAL_DATA_PTR;
static inlined_cachefunc void __ic_entire_invalidate(void);
static inlined_cachefunc void __dc_entire_op(const int cacheop);
static inlined_cachefunc void __slc_entire_op(const int op);
-static inline bool ioc_enabled(void);
+static inlined_cachefunc bool ioc_enabled(void);
static inline bool pae_exists(void)
{
@@ -346,7 +346,7 @@ void slc_disable(void)
__slc_disable();
}
-static inline bool ioc_exists(void)
+static inlined_cachefunc bool ioc_exists(void)
{
if (is_isa_arcv2()) {
union bcr_clust_cfg cbcr;
@@ -358,7 +358,7 @@ static inline bool ioc_exists(void)
return false;
}
-static inline bool ioc_enabled(void)
+static inlined_cachefunc bool ioc_enabled(void)
{
/*
* We check only CONFIG option instead of IOC HW state check as IOC
--
2.21.1
Re: [PATCH v1 6/8] spi: dw: Add mem_ops
Hi Sean, I've tested the SPI (with SPI flash) on HSDK board (which have DW SPI) with your changes. It completely break SPI on HSDK: ->8-- # sf probe unrecognized JEDEC id bytes: ff, ff, ff Failed to initialize SPI flash at 0:0 (error -2) ->8-- Tested from maix_spi HEAD (e338571bf528f58b3ced7fbd0c1f5d923caa1cfd) --- Eugeniy Paltsev From: Sean Anderson Sent: Friday, March 6, 2020 03:48 To: Eugeniy Paltsev; u-boot@lists.denx.de Cc: Simon Glass; Jagan Teki; Alexey Brodkin Subject: Re: [PATCH v1 6/8] spi: dw: Add mem_ops On 3/5/20 5:15 PM, Eugeniy Paltsev wrote: > Hi Sean, > > do you have branch with this code (all dw spi changes) in some public repo? > I would like to test it with our board (which have DW SPI). > > --- > Eugeniy Paltsev A full tree is available at https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_Forty-2DBot_u-2Dboot_tree_maix-5Fspi=DwICaQ=DPL6_X_6JkXFx7AXWqB0tg=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI=EmfUzvFjhqLxmNa2GVtV9Ph9bW4C8gFi0EhXqFqucSU=23UJFSwfnLIPXRyp6h_whXzJJJCbiceE8X6ydfb11_A= --Sean
Re: [PATCH v1 6/8] spi: dw: Add mem_ops
Hi Sean,
do you have branch with this code (all dw spi changes) in some public repo?
I would like to test it with our board (which have DW SPI).
---
Eugeniy Paltsev
From: Sean Anderson
Sent: Thursday, March 5, 2020 22:19
To: u-boot@lists.denx.de
Cc: Simon Glass; Jagan Teki; Sean Anderson; Eugeniy Paltsev
Subject: [PATCH v1 6/8] spi: dw: Add mem_ops
The designware ssi device has "broken" chip select behaviour [1], and needs
specific manipulation to use the built-in chip select. The existing fix is
to use an external GPIO for chip select, but typically the K210 has SPI3
directly connected to a flash chip with dedicated pins. This makes it
impossible to use the spi_xfer function to use spi, since the CS is
de-asserted in between calls. This patch adds an implementation of
exec_op, which gives correct behaviour when reading/writing spi flash.
Work on this device has been difficult because the only example code I have
to work off is Kendryte's sdk, and I do not have access to the datasheet
(if anyone does, I would love to have a look!). The MMC device is still not
working, but I have been making progress.
[1]
https://urldefense.proofpoint.com/v2/url?u=https-3A__lkml.org_lkml_2015_12_23_132=DwIDAg=DPL6_X_6JkXFx7AXWqB0tg=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI=WVwKMzBXasdUvVoschXNTC5C7t39Ta0E7Ly3uEPRT_0=7dEhNfWpefL5yAqFi1Ztrve9SBPM_n3OoIJoH40hgpQ=
Signed-off-by: Sean Anderson
---
drivers/spi/designware_spi.c | 128 ++-
1 file changed, 126 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 613eb0d0e6..298d1dbab5 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -108,8 +109,8 @@ struct dw_spi_priv {
int len;
u32 fifo_len; /* depth of the FIFO buffer */
- void *tx;
- void *tx_end;
+ const void *tx;
+ const void *tx_end;
void *rx;
void *rx_end;
@@ -471,6 +472,124 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
return ret;
}
+/*
+ * This function is necessary for reading SPI flash with the native CS
+ * c.f.
https://urldefense.proofpoint.com/v2/url?u=https-3A__lkml.org_lkml_2015_12_23_132=DwIDAg=DPL6_X_6JkXFx7AXWqB0tg=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI=WVwKMzBXasdUvVoschXNTC5C7t39Ta0E7Ly3uEPRT_0=7dEhNfWpefL5yAqFi1Ztrve9SBPM_n3OoIJoH40hgpQ=
+ */
+static int dw_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
+{
+ bool read = op->data.dir == SPI_MEM_DATA_IN;
+ int pos, i, ret = 0;
+ struct udevice *bus = slave->dev->parent;
+ struct dw_spi_platdata *plat = dev_get_platdata(bus);
+ struct dw_spi_priv *priv = dev_get_priv(bus);
+ u8 op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
+ u8 op_buf[op_len];
+ u32 cr0;
+
+ if (read)
+ priv->tmode = SPI_TMOD_EPROMREAD;
+ else
+ priv->tmode = SPI_TMOD_TO;
+
+ debug("%s: buf=%p len=%u [bytes]\n",
+ __func__, op->data.buf.in, op->data.nbytes);
+
+ cr0 = GEN_CTRL0(priv, plat);
+ debug("%s: cr0=%08x\n", __func__, cr0);
+
+ spi_enable_chip(priv, 0);
+ dw_write(priv, DW_SPI_CTRL0, cr0);
+ if (read)
+ dw_write(priv, DW_SPI_CTRL1, op->data.nbytes - 1);
+ spi_enable_chip(priv, 1);
+
+ /* From spi_mem_exec_op */
+ pos = 0;
+ op_buf[pos++] = op->cmd.opcode;
+ if (op->addr.nbytes) {
+ for (i = 0; i < op->addr.nbytes; i++)
+ op_buf[pos + i] = op->addr.val >>
+ (8 * (op->addr.nbytes - i - 1));
+
+ pos += op->addr.nbytes;
+ }
+ if (op->dummy.nbytes)
+ memset(op_buf + pos, 0xff, op->dummy.nbytes);
+
+ priv->tx = _buf;
+ priv->tx_end = priv->tx + op_len;
+ priv->rx = NULL;
+ priv->rx_end = NULL;
+ while (priv->tx != priv->tx_end) {
+ dw_writer(priv);
+ /* This loop needs a delay otherwise we can hang */
+ udelay(1);
+ }
+
+ /*
+* XXX: The following are tight loops! Enabling debug messages may cause
+* them to fail because we are not reading/writing the fifo fast enough.
+*
+* We heuristically break out of the loop when we stop getting data.
+* This is to stop us from hanging if the device doesn't send any data
+* (either at all, or after sending a response). For example, one flash
+* chip I tested did not send anything back after the first 64K of data.
+*/
+ if (read) {
+ /* If we have gotten any data back ye
[PATCH] ARC: rework setting of ARC CPU specific compiler options
It's a very rare if at all existing occasion when ARC CPU template is used as is w/o any changes - in the end it's a beauty and competitive advantage of ARC cores to be tailored for a particular use-case - and so it doesn't make a lot of sense to offer template-based "-mcpu" selection. Given for each and every platform we end-up adding quite a few more flags it's logical to move "-mcpu" selection to platform's definition as well which we exactly do here. Signed-off-by: Eugeniy Paltsev --- arch/arc/config.mk | 20 board/abilis/tb100/config.mk| 5 + board/synopsys/axs10x/config.mk | 6 ++ board/synopsys/emsdp/config.mk | 2 +- board/synopsys/hsdk/config.mk | 4 board/synopsys/iot_devkit/config.mk | 3 ++- board/synopsys/nsim/Kconfig | 9 + board/synopsys/nsim/config.mk | 8 configs/nsim_700_defconfig | 1 + configs/nsim_700be_defconfig| 1 + configs/nsim_hs38_defconfig | 1 + configs/nsim_hs38be_defconfig | 1 + 12 files changed, 39 insertions(+), 22 deletions(-) create mode 100644 board/abilis/tb100/config.mk create mode 100644 board/synopsys/nsim/config.mk diff --git a/arch/arc/config.mk b/arch/arc/config.mk index 18005d99930..6fa29adae81 100644 --- a/arch/arc/config.mk +++ b/arch/arc/config.mk @@ -22,26 +22,6 @@ ifdef CONFIG_ARC_MMU_VER CONFIG_MMU = 1 endif -ifdef CONFIG_CPU_ARC750D -PLATFORM_CPPFLAGS += -mcpu=arc700 -endif - -ifdef CONFIG_CPU_ARC770D -PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape -endif - -ifdef CONFIG_CPU_ARCEM6 -PLATFORM_CPPFLAGS += -mcpu=arcem -endif - -ifdef CONFIG_CPU_ARCHS34 -PLATFORM_CPPFLAGS += -mcpu=archs -endif - -ifdef CONFIG_CPU_ARCHS38 -PLATFORM_CPPFLAGS += -mcpu=archs -endif - PLATFORM_CPPFLAGS += -ffixed-r25 -D__ARC__ -gdwarf-2 -mno-sdata PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections -fno-common diff --git a/board/abilis/tb100/config.mk b/board/abilis/tb100/config.mk new file mode 100644 index 000..9e8dee49bd3 --- /dev/null +++ b/board/abilis/tb100/config.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020 Synopsys, Inc. All rights reserved. + +PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape diff --git a/board/synopsys/axs10x/config.mk b/board/synopsys/axs10x/config.mk index 81ff498f818..ccac5442908 100644 --- a/board/synopsys/axs10x/config.mk +++ b/board/synopsys/axs10x/config.mk @@ -2,6 +2,12 @@ # # Copyright (C) 2018 Synopsys, Inc. All rights reserved. +ifdef CONFIG_TARGET_AXS103 + PLATFORM_CPPFLAGS += -mcpu=archs +else + PLATFORM_CPPFLAGS += -mcpu=arc700 -mlock -mswape +endif + bsp-generate: u-boot u-boot.bin ifdef CONFIG_ISA_ARCV2 $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-axs.py \ diff --git a/board/synopsys/emsdp/config.mk b/board/synopsys/emsdp/config.mk index 67fd7bf82a3..5bd10442aff 100644 --- a/board/synopsys/emsdp/config.mk +++ b/board/synopsys/emsdp/config.mk @@ -1,2 +1,2 @@ -PLATFORM_CPPFLAGS += -mlittle-endian -mnorm -mswap -mmpy-option=3 \ +PLATFORM_CPPFLAGS += -mcpu=arcem -mlittle-endian -mnorm -mswap -mmpy-option=3 \ -mbarrel-shifter -mfpu=fpuda_all -mcode-density diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk index 9e280f921a1..5ae22fa2b75 100644 --- a/board/synopsys/hsdk/config.mk +++ b/board/synopsys/hsdk/config.mk @@ -2,6 +2,10 @@ # # Copyright (C) 2018 Synopsys, Inc. All rights reserved. +PLATFORM_CPPFLAGS += -mcpu=hs38_linux -mlittle-endian -matomic -mll64 \ + -mdiv-rem -mswap -mnorm -mmpy-option=9 -mbarrel-shifter \ + -mfpu=fpud_all + bsp-generate: u-boot u-boot.bin $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \ --arc-id 0x52 --image $(srctree)/u-boot.bin \ diff --git a/board/synopsys/iot_devkit/config.mk b/board/synopsys/iot_devkit/config.mk index 120733538a4..e1e546a3d04 100644 --- a/board/synopsys/iot_devkit/config.mk +++ b/board/synopsys/iot_devkit/config.mk @@ -1,2 +1,3 @@ -PLATFORM_CPPFLAGS += -mlittle-endian -mcode-density -mdiv-rem -mswap -mnorm -mmpy-option=6 -mbarrel-shifter +PLATFORM_CPPFLAGS += -mcpu=em4_fpuda -mlittle-endian -mcode-density -mdiv-rem \ + -mswap -mnorm -mmpy-option=6 -mbarrel-shifter LDSCRIPT = $(srctree)/board/synopsys/iot_devkit/u-boot.lds diff --git a/board/synopsys/nsim/Kconfig b/board/synopsys/nsim/Kconfig index 22287032bf5..b6966b2991e 100644 --- a/board/synopsys/nsim/Kconfig +++ b/board/synopsys/nsim/Kconfig @@ -9,4 +9,13 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "nsim" +config NSIM_BOARD_CPPFLAGS + string "board arc-specific compiler options" + help + For nSIM we allow to set custom arc-specific compiler options + (like -mcpu=) instead of hardcoding them in its makefile as nSIM + target is used for representing targets without fix
[PATCH 2/2] CLK: HSDK: fix HDMI clock calculation
HDMI PLL has its own xtal with 27 MHz output but we treat it the same
way as other PLLs with 33.33 MHz input.
Fix that.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 31 +--
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 69e6b24b66c..4637b9fdf15 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -46,17 +46,21 @@
*||-->|CGU_TUN_IDIV_ROM|--->
*||-->|CGU_TUN_IDIV_PWM|--->
*|
- *|
- *|-->| HDMI PLL |
- *|
- *||
- *||-->|CGU_HDMI_IDIV_APB|-->
- *|
*| ---
*|-->| DDR PLL |
*---
* |
* |>
+ *
+ * --
+ * | 27.00 MHz xtal |
+ * --
+ *|
+ *|
+ *|-->| HDMI PLL |
+ *
+ * |
+ * |-->|CGU_HDMI_IDIV_APB|-->
*/
#define CGU_ARC_IDIV 0x080
@@ -117,7 +121,8 @@
#define CREG_CORE_IF_CLK_DIV_2 0x1
#define MIN_PLL_RATE 1 /* 100 MHz */
-#define PARENT_RATE /* fixed clock - xtal */
+#define PARENT_RATE_33 /* fixed clock - xtal */
+#define PARENT_RATE_27 2700 /* fixed clock - xtal */
#define CGU_MAX_CLOCKS 26
#define CGU_SYS_CLOCKS 16
@@ -237,6 +242,7 @@ struct hsdk_cgu_clk {
};
struct hsdk_pll_devdata {
+ const u32 parent_rate;
const struct hsdk_pll_cfg *pll_cfg;
int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
const struct hsdk_pll_cfg *cfg);
@@ -248,16 +254,19 @@ static int hsdk_pll_comm_update_rate(struct hsdk_cgu_clk
*, unsigned long,
const struct hsdk_pll_cfg *);
static const struct hsdk_pll_devdata core_pll_dat = {
+ .parent_rate = PARENT_RATE_33,
.pll_cfg = asdt_pll_cfg,
.update_rate = hsdk_pll_core_update_rate,
};
static const struct hsdk_pll_devdata sdt_pll_dat = {
+ .parent_rate = PARENT_RATE_33,
.pll_cfg = asdt_pll_cfg,
.update_rate = hsdk_pll_comm_update_rate,
};
static const struct hsdk_pll_devdata hdmi_pll_dat = {
+ .parent_rate = PARENT_RATE_27,
.pll_cfg = hdmi_pll_cfg,
.update_rate = hsdk_pll_comm_update_rate,
};
@@ -372,6 +381,7 @@ static ulong pll_get(struct clk *sclk)
u64 rate;
u32 idiv, fbdiv, odiv;
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
+ u32 parent_rate = clk->pll_devdata->parent_rate;
val = hsdk_pll_read(clk, CGU_PLL_CTRL);
@@ -379,7 +389,7 @@ static ulong pll_get(struct clk *sclk)
/* Check if PLL is bypassed */
if (val & CGU_PLL_CTRL_BYPASS)
- return PARENT_RATE;
+ return parent_rate;
/* Check if PLL is disabled */
if (val & CGU_PLL_CTRL_PD)
@@ -392,7 +402,7 @@ static ulong pll_get(struct clk *sclk)
/* output divider = 2^(reg.odiv) */
odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
- rate = (u64)PARENT_RATE * fbdiv;
+ rate = (u64)parent_rate * fbdiv;
do_div(rate, idiv * odiv);
return rate;
@@ -490,7 +500,8 @@ static ulong pll_set(struct clk *sclk, ulong rate)
}
}
- pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
PARENT_RATE);
+ pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
+ clk->pll_devdata->parent_rate);
return -EINVAL;
}
--
2.21.0
[PATCH 1/2] CLK: HSDK: Check for PLL bypass firstly
Pll bypass has priority over enable/disable.
Signed-off-by: Eugeniy Paltsev
---
drivers/clk/clk-hsdk-cgu.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 56ef08c032b..69e6b24b66c 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -377,14 +377,14 @@ static ulong pll_get(struct clk *sclk)
pr_debug("current configurarion: %#x\n", val);
- /* Check if PLL is disabled */
- if (val & CGU_PLL_CTRL_PD)
- return 0;
-
/* Check if PLL is bypassed */
if (val & CGU_PLL_CTRL_BYPASS)
return PARENT_RATE;
+ /* Check if PLL is disabled */
+ if (val & CGU_PLL_CTRL_PD)
+ return 0;
+
/* input divider = reg.idiv + 1 */
idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
/* fb divider = 2*(reg.fbdiv + 1) */
--
2.21.0
Re: [PATCH] ARC: enable unit tests on development platforms
Hi Alexey, ping! --- Eugeniy Paltsev From: Eugeniy Paltsev Sent: Thursday, November 28, 2019 18:54 To: uboot-snps-...@synopsys.com; Alexey Brodkin Cc: u-boot@lists.denx.de; Eugeniy Paltsev Subject: Re: [PATCH] ARC: enable unit tests on development platforms Hi Alexey, ping! --- Eugeniy Paltsev From: Eugeniy Paltsev Sent: Friday, November 8, 2019 18:31 To: uboot-snps-...@synopsys.com; Alexey Brodkin Cc: u-boot@lists.denx.de; Eugeniy Paltsev Subject: [PATCH] ARC: enable unit tests on development platforms Enable unit tests on HSDK and AXS103 development platforms to run it in verification flow. Signed-off-by: Eugeniy Paltsev --- configs/axs103_defconfig | 2 ++ configs/hsdk_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 8255d9fa068..73a224fa145 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -59,3 +59,5 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_UNIT_TEST=y +CONFIG_UT_TIME=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index e28ceae289c..c0b45513afd 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_PANIC_HANG=y +CONFIG_UNIT_TEST=y +CONFIG_UT_TIME=y -- 2.21.0
Re: [U-Boot] [PATCH] ARC: enable unit tests on development platforms
Hi Alexey, ping! --- Eugeniy Paltsev From: Eugeniy Paltsev Sent: Friday, November 8, 2019 18:31 To: uboot-snps-...@synopsys.com; Alexey Brodkin Cc: u-boot@lists.denx.de; Eugeniy Paltsev Subject: [PATCH] ARC: enable unit tests on development platforms Enable unit tests on HSDK and AXS103 development platforms to run it in verification flow. Signed-off-by: Eugeniy Paltsev --- configs/axs103_defconfig | 2 ++ configs/hsdk_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 8255d9fa068..73a224fa145 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -59,3 +59,5 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_UNIT_TEST=y +CONFIG_UT_TIME=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index e28ceae289c..c0b45513afd 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_PANIC_HANG=y +CONFIG_UNIT_TEST=y +CONFIG_UT_TIME=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARC: enable unit tests on development platforms
Enable unit tests on HSDK and AXS103 development platforms to run it in verification flow. Signed-off-by: Eugeniy Paltsev --- configs/axs103_defconfig | 2 ++ configs/hsdk_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 8255d9fa068..73a224fa145 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -59,3 +59,5 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_UNIT_TEST=y +CONFIG_UT_TIME=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index e28ceae289c..c0b45513afd 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -63,3 +63,5 @@ CONFIG_USB_OHCI_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USE_PRIVATE_LIBGCC=y CONFIG_PANIC_HANG=y +CONFIG_UNIT_TEST=y +CONFIG_UT_TIME=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARC: [plat-axs101]: migrate to DM_MMC
Signed-off-by: Eugeniy Paltsev --- configs/axs101_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 0bfb532fc74..38c8ae998fd 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -35,7 +35,9 @@ CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_HSDK_CREG_GPIO=y CONFIG_MMC=y +CONFIG_DM_MMC=y CONFIG_MMC_DW=y +CONFIG_MMC_DW_SNPS=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] ARC: HSDK: introduce reset driver
Introduce reset driver for Synopsys ARC HSDK SoC
Signed-off-by: Eugeniy Paltsev
---
drivers/reset/Kconfig | 7 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-hsdk.c | 116
include/dt-bindings/reset/snps,hsdk-reset.h | 17 +++
4 files changed, 141 insertions(+)
create mode 100644 drivers/reset/reset-hsdk.c
create mode 100644 include/dt-bindings/reset/snps,hsdk-reset.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6ec6f39c85f..3071af5f692 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -91,6 +91,13 @@ config RESET_ROCKCHIP
though is that some reset signals, like I2C or MISC reset multiple
devices.
+config RESET_HSDK
+ bool "Synopsys HSDK Reset Driver"
+ depends on DM_RESET && TARGET_HSDK
+ default y
+ help
+ This enables the reset controller driver for HSDK board.
+
config RESET_MESON
bool "Reset controller driver for Amlogic Meson SoCs"
depends on DM_RESET && ARCH_MESON
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 7fec75bb492..1c4401c7f2b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_STM32_RESET) += stm32-reset.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
+obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
diff --git a/drivers/reset/reset-hsdk.c b/drivers/reset/reset-hsdk.c
new file mode 100644
index 000..213d6c87be1
--- /dev/null
+++ b/drivers/reset/reset-hsdk.c
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * HSDK SoC Reset Controller driver
+ *
+ * Copyright (C) 2019 Synopsys, Inc. All rights reserved.
+ * Author: Eugeniy Paltsev
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct hsdk_rst {
+ void __iomem*regs_ctl;
+ void __iomem*regs_rst;
+};
+
+static const u32 rst_map[] = {
+ BIT(16), /* APB_RST */
+ BIT(17), /* AXI_RST */
+ BIT(18), /* ETH_RST */
+ BIT(19), /* USB_RST */
+ BIT(20), /* SDIO_RST */
+ BIT(21), /* HDMI_RST */
+ BIT(22), /* GFX_RST */
+ BIT(25), /* DMAC_RST */
+ BIT(31), /* EBI_RST */
+};
+
+#define HSDK_MAX_RESETSARRAY_SIZE(rst_map)
+
+#define CGU_SYS_RST_CTRL 0x0
+#define CGU_IP_SW_RESET0x0
+#define CGU_IP_SW_RESET_DELAY_SHIFT16
+#define CGU_IP_SW_RESET_DELAY_MASK GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
+#define CGU_IP_SW_RESET_DELAY 0
+#define CGU_IP_SW_RESET_RESET BIT(0)
+#define SW_RESET_TIMEOUT 1
+
+static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
+{
+ writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
+}
+
+static int hsdk_reset_do(struct hsdk_rst *rst)
+{
+ u32 reg;
+
+ reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
+ reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
+ reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
+ reg |= CGU_IP_SW_RESET_RESET;
+ writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
+
+ /* wait till reset bit is back to 0 */
+ return readl_poll_timeout(rst->regs_rst + CGU_IP_SW_RESET, reg,
+ !(reg & CGU_IP_SW_RESET_RESET), SW_RESET_TIMEOUT);
+}
+
+static int hsdk_reset_reset(struct reset_ctl *rst_ctl)
+{
+ struct udevice *dev = rst_ctl->dev;
+ struct hsdk_rst *rst = dev_get_priv(dev);
+
+ if (rst_ctl->id >= HSDK_MAX_RESETS)
+ return -EINVAL;
+
+ debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, rst_ctl,
+ rst_ctl->dev, rst_ctl->id);
+
+ hsdk_reset_config(rst, rst_ctl->id);
+ return hsdk_reset_do(rst);
+}
+
+static int hsdk_reset_noop(struct reset_ctl *rst_ctl)
+{
+ return 0;
+}
+
+static const struct reset_ops hsdk_reset_ops = {
+ .request= hsdk_reset_noop,
+ .free = hsdk_reset_noop,
+ .rst_assert = hsdk_reset_noop,
+ .rst_deassert = hsdk_reset_reset,
+};
+
+static const struct udevice_id hsdk_reset_dt_match[] = {
+ { .compatible = "snps,hsdk-reset" },
+ { },
+};
+
+static int hsdk_reset_probe(struct udevice *dev)
+{
+ struct hsdk_rst *rst = dev_get_priv(dev);
+
+ rst->regs_ctl = dev_remap_addr_index(dev, 0);
+ if (!rst->regs_ctl)
+ return -EINVAL;
+
+ rst->regs_rst = dev_remap_addr_index(dev, 1);
+ if (!rst->regs_rst)
+ return -EINVAL;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(hsdk_reset) = {
+ .name = "hsdk-r
[U-Boot] [PATCH 2/2] MAINTAINERS: add info about ARC HSDK reset driver
Signed-off-by: Eugeniy Paltsev --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index e752e4b3de0..4cecbb6d134 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -94,6 +94,13 @@ L: uboot-snps-...@synopsys.com F: doc/device-tree-bindings/gpio/snps,creg-gpio.txt F: drivers/gpio/hsdk-creg-gpio.c +ARC HSDK RESET +M: Eugeniy Paltsev +S: Maintained +L: uboot-snps-...@synopsys.com +F: include/dt-bindings/reset/snps,hsdk-reset.h +F: drivers/reset/reset-hsdk.c + ARC SYNOPSYS DW MMC EXTENSIONS M: Eugeniy Paltsev S: Maintained -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] NET: DW: fix regression for ARC boards
The commit
642b80d256e ("net: designware: drop compatible altr, socfpga-stmmac")
breaks designware ethernet for all ARC boards. It removes
"altr, socfpga-stmmac" compatible from "drivers/net/designware.c"
without changing compatible in the boards which use it.
Fix that by adding "snps,arc-dwmac-3.70a" compatible string to
"drivers/net/designware.c" and using it in ARC boards device tree.
Signed-off-by: Eugeniy Paltsev
---
Tom, could you please pick this patch to 2019.10?
arch/arc/dts/axs10x_mb.dtsi | 2 +-
arch/arc/dts/hsdk.dts | 2 +-
drivers/net/designware.c| 1 +
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 6d97de9fd8c..5b77642b8d7 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -53,7 +53,7 @@
};
ethernet@18000 {
- compatible = "altr,socfpga-stmmac";
+ compatible = "snps,arc-dwmac-3.70a";
reg = < 0x18000 0x2000 >;
phy-mode = "gmii";
snps,pbl = < 32 >;
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 7028050447b..34ef3a620a3 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -71,7 +71,7 @@
ethernet@f0008000 {
#interrupt-cells = <1>;
- compatible = "altr,socfpga-stmmac";
+ compatible = "snps,arc-dwmac-3.70a";
reg = <0xf0008000 0x2000>;
phy-mode = "gmii";
};
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 145eeac45fd..00313700858 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -852,6 +852,7 @@ static const struct udevice_id designware_eth_ids[] = {
{ .compatible = "amlogic,meson-gxbb-dwmac" },
{ .compatible = "amlogic,meson-axg-dwmac" },
{ .compatible = "st,stm32-dwmac" },
+ { .compatible = "snps,arc-dwmac-3.70a" },
{ }
};
--
2.21.0
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*
0] SF: 16 bytes @ 0x18 Read: OK 8100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OK AXS# mw 0x8100 0 5 && sf write 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 06 | [0B -] [ret 0] 02 00 18 00 00 | [16B out] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ret 0] 05 | [1B in] 9c [ret 0] 70 | [1B in] 81 [ret 0] SF: 16 bytes @ 0x18 Written: OK OK AXS# sf read 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 0b 00 18 00 00 | [16B in] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ret 0] SF: 16 bytes @ 0x18 Read: OK OK ->8-- --- Eugeniy Paltsev From: Vignesh Raghavendra Sent: Wednesday, September 25, 2019 11:11 To: Eugeniy Paltsev; Jagan Teki; Ashish Kumar; Simon Goldschmidt Cc: u-boot@lists.denx.de; Tom Rini; Alexey Brodkin Subject: Re: [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512* On 24/09/19 10:53 PM, Eugeniy Paltsev wrote: > Hi Vignesh, > > I've check this patches on top of 31e086e460f. > The read/write/erase seems to work. > > However, as I can see 'sf protect lock' doesn't work - it finish successfully > but the area remains unlocked. Did you verify that area is indeed unlocked by writing data and then reading it back? I was able to find a board with mt25qu512a which is same as n25q512a in terms of locking I see it works fine: => sf probe SF: Detected n25q512a with page size 256 Bytes, erase size 4 KiB, total 64 MiB => sf protect lock 0 0x400; echo $? 0 => sf write 0x8200 0x3FF 0x100 device 0 offset 0x3ff, size 0x100 SF: 256 bytes @ 0x3ff Written: ERROR -5 If you still see failures wrt locking, could you provide debug logs from spi_mem_exec_op() (in drivers/spi/spi-mem.c) just like last time? Regards Vignesh > As I remember It worked with old u-boot spi-nor code, but I need to check it. > > --- > Eugeniy Paltsev > > > > From: Vignesh Raghavendra > Sent: Tuesday, September 24, 2019 08:56 > To: Jagan Teki; Eugeniy Paltsev; Ashish Kumar; Simon Goldschmidt > Cc: Vignesh Raghavendra; u-boot@lists.denx.de; Tom Rini; Alexey Brodkin > Subject: [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for > n25q256 and n25q512* > > This series removes SPI_NOR_4B_OPCODES flags from legacy variants of > n25q256* and n25q512* and adds entries for newer variants of those > flashes that support 4 Byte opcodes. > > I don't have the flash devices. So its only compile tested. > > Ashish, Simon, > > I would greatly appreciate if you could test these patches and make sure > 4 Byte opcodes are being used. (Probably by enabling/adding prints to > cmd->opcode in spi_mem_exec_op() in drivers/spi/spi-mem.c > > Euginey, > > Could you test this series on top of latest u-boot master and confirm > that your test cases still work? > > Regards > Vignesh > > Vignesh Raghavendra (3): > spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and > n25q256* > spi-nor: spi-nor-ids: Rename mt25qu512a entry > spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and > n25q512* > > drivers/mtd/spi/spi-nor-ids.c | 13 - > 1 file changed, 8 insertions(+), 5 deletions(-) > > -- > 2.23.0 > -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*
Hi Vignesh, I've check this patches on top of 31e086e460f. The read/write/erase seems to work. However, as I can see 'sf protect lock' doesn't work - it finish successfully but the area remains unlocked. As I remember It worked with old u-boot spi-nor code, but I need to check it. --- Eugeniy Paltsev From: Vignesh Raghavendra Sent: Tuesday, September 24, 2019 08:56 To: Jagan Teki; Eugeniy Paltsev; Ashish Kumar; Simon Goldschmidt Cc: Vignesh Raghavendra; u-boot@lists.denx.de; Tom Rini; Alexey Brodkin Subject: [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512* This series removes SPI_NOR_4B_OPCODES flags from legacy variants of n25q256* and n25q512* and adds entries for newer variants of those flashes that support 4 Byte opcodes. I don't have the flash devices. So its only compile tested. Ashish, Simon, I would greatly appreciate if you could test these patches and make sure 4 Byte opcodes are being used. (Probably by enabling/adding prints to cmd->opcode in spi_mem_exec_op() in drivers/spi/spi-mem.c Euginey, Could you test this series on top of latest u-boot master and confirm that your test cases still work? Regards Vignesh Vignesh Raghavendra (3): spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* spi-nor: spi-nor-ids: Rename mt25qu512a entry spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512* drivers/mtd/spi/spi-nor-ids.c | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Regressions in MTD / SPI FLASH
: 16 bytes @ 0x18 Read: OK OK AXS# md.b 0x8100 0x10 8100: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff AXS# mw 0x8100 0 5 AXS# sf write 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 06 | [0B -] [ret 0] 02 00 18 00 00 | [16B out] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ret 0] 05 | [1B in] 00 [ret 0] 70 | [1B in] 81 [ret 0] SF: 16 bytes @ 0x18 Written: OK OK AXS# sf read 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 0b 00 18 00 00 | [16B in] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ret 0] SF: 16 bytes @ 0x18 Read: OK OK AXS# md.b 0x8100 0x10 8100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 AXS# -->8 All tests were performed on 4b95daf5dca with your commit (for disabling 4B opcodes) applied. --- Eugeniy Paltsev ____________ From: Vignesh Raghavendra Sent: Monday, September 23, 2019 08:31 To: Eugeniy Paltsev Cc: uboot-snps-...@synopsys.com; Alexey Brodkin Subject: Re: [U-Boot] Regressions in MTD / SPI FLASH Hi Eugeniy On 12/09/19 5:59 PM, Eugeniy Paltsev wrote: > Hi Vignesh, > > I doesn't have access to board with n25q512ax3 currently, however I can test > this on Monday (16.09) Could you provide please provide logs that I requested below? " > Could you enable CONFIG_SPI_FLASH_SFDP_SUPPORT and also enable debug > prints in spi_mem_exec_op() (in drivers/spi/spi-mem.c like before) and > provide logs? " There are some objections to the fixes[1] that I provided to you. Above logs will helps me in justifying the fix or provide better patch. I would like to close this as soon as possible before 2019.10 is out. Appreciate you help! [1] https://urldefense.proofpoint.com/v2/url?u=http-3A__patchwork.ozlabs.org_patch_1160501_=DwICaQ=DPL6_X_6JkXFx7AXWqB0tg=ZlJN1MriPUTkBKCrPSx67GmaplEUGcAEk9yPtCLdUXI=Yb1WwCtRxov5WTaRZMp5FA3-x1hLIH-G-192fad-opU=w3B4OJ4ml06qS7q7BjbvhzZXkLQswsLfXxuPt7McUU4= > > --- > Eugeniy Paltsev > > > > From: Vignesh Raghavendra > Sent: Tuesday, September 10, 2019 15:27 > To: Eugeniy Paltsev; Jagan Teki > Cc: u-boot@lists.denx.de; Alexey Brodkin; tr...@konsulko.com; > uboot-snps-...@synopsys.com > Subject: Re: [U-Boot] Regressions in MTD / SPI FLASH > > Hi Eugeniy, > > One more request: > > I am trying to find a better way to identify parts that don't support > 4byte addressing. > > Could you enable CONFIG_SPI_FLASH_SFDP_SUPPORT and also enable debug > prints in spi_mem_exec_op() (in drivers/spi/spi-mem.c like before) and > provide logs? > > Just logs of "sf probe" should be sufficient. > > Regards > Vignesh > > On 10/09/19 5:24 PM, Vignesh Raghavendra wrote: >> >> >> On 10/09/19 5:11 PM, Eugeniy Paltsev wrote: >>> Hi Vignesh, >>> >>> that patch helps - both erase and write works fine. >>> >> >> Thanks for testing! I will cleanup the patches and send formal patches >> to the list with your tested by. >> >> Regards >> Vignesh >> >>> For n25q512ax3: >>> Tested-by: "Eugeniy Paltsev " >>> >>> --- >>> Eugeniy Paltsev >>> >>> >>> ________ >>> From: Vignesh Raghavendra >>> Sent: Tuesday, September 10, 2019 08:07 >>> To: Eugeniy Paltsev; Jagan Teki >>> Cc: u-boot@lists.denx.de; uboot-snps-...@synopsys.com; Alexey Brodkin; >>> tr...@konsulko.com >>> Subject: Re: Regressions in MTD / SPI FLASH >>> >>> Hi, >>> >>> On 10/09/19 12:18 AM, Eugeniy Paltsev wrote: >>>> Hi! >>>> Comments are inlined: >>>> >>>>> On 04/09/19 11:37 PM, Eugeniy Paltsev wrote: >>>>>> We faced with regressions caused by >>>>>> commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) >>>>>> This switch was performed by removing entire u-boot spi-flash >>>>>> core implementation and copying it from another project. >>>>>> However the switch is performed without proper testing and >>>>>> investigations about fixes/improvements were made in u-boot >>>>>> spi-flash core. This results in regressions. >>>>>> >>>>> >>>>> Apologies for the trouble... >>>>> As stated in cover letter, this change was necessary as U-Boot SPI flash >>>>> stack at that time did not features such as 4 byte addressing, SFDP >>>>> parsing, SPI c
Re: [U-Boot] Regressions in MTD / SPI FLASH
Hi Vignesh, I doesn't have access to board with n25q512ax3 currently, however I can test this on Monday (16.09) --- Eugeniy Paltsev From: Vignesh Raghavendra Sent: Tuesday, September 10, 2019 15:27 To: Eugeniy Paltsev; Jagan Teki Cc: u-boot@lists.denx.de; Alexey Brodkin; tr...@konsulko.com; uboot-snps-...@synopsys.com Subject: Re: [U-Boot] Regressions in MTD / SPI FLASH Hi Eugeniy, One more request: I am trying to find a better way to identify parts that don't support 4byte addressing. Could you enable CONFIG_SPI_FLASH_SFDP_SUPPORT and also enable debug prints in spi_mem_exec_op() (in drivers/spi/spi-mem.c like before) and provide logs? Just logs of "sf probe" should be sufficient. Regards Vignesh On 10/09/19 5:24 PM, Vignesh Raghavendra wrote: > > > On 10/09/19 5:11 PM, Eugeniy Paltsev wrote: >> Hi Vignesh, >> >> that patch helps - both erase and write works fine. >> > > Thanks for testing! I will cleanup the patches and send formal patches > to the list with your tested by. > > Regards > Vignesh > >> For n25q512ax3: >> Tested-by: "Eugeniy Paltsev " >> >> --- >> Eugeniy Paltsev >> >> >> ________ >> From: Vignesh Raghavendra >> Sent: Tuesday, September 10, 2019 08:07 >> To: Eugeniy Paltsev; Jagan Teki >> Cc: u-boot@lists.denx.de; uboot-snps-...@synopsys.com; Alexey Brodkin; >> tr...@konsulko.com >> Subject: Re: Regressions in MTD / SPI FLASH >> >> Hi, >> >> On 10/09/19 12:18 AM, Eugeniy Paltsev wrote: >>> Hi! >>> Comments are inlined: >>> >>>> On 04/09/19 11:37 PM, Eugeniy Paltsev wrote: >>>>> We faced with regressions caused by >>>>> commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) >>>>> This switch was performed by removing entire u-boot spi-flash >>>>> core implementation and copying it from another project. >>>>> However the switch is performed without proper testing and >>>>> investigations about fixes/improvements were made in u-boot >>>>> spi-flash core. This results in regressions. >>>>> >>>> >>>> Apologies for the trouble... >>>> As stated in cover letter, this change was necessary as U-Boot SPI flash >>>> stack at that time did not features such as 4 byte addressing, SFDP >>>> parsing, SPI controllers with MMIO interfaces etc. Also there was need >>>> to move to SPI MEM framework to support both SPI NAND and SPI NOR >>>> flashes using a single SPI controller drivers. >>>> I have to disagree on the part that there was no proper testing... As >>>> evident from mailing list archives, patch series was reviewed by >>>> multiple reviewers and tested on their platforms as well... >>>> Unfortunately its impossible to get all boards owners to test it. >>> >>> I'm not talking about getting all customers board and testing changes on >>> them. >>> It could be done another way - i.e. like it is done for u-boot driver-model >>> migration: >>> by introducing the option for choosing which stack will be used and allow >>> customers >>> to switch the flash IC they use to new stack until some deadline. >>> >> >> I did start off with this. But maintaining two stacks is too cumbersome >> and adds to code size (which is a big factor for SPL stage) >> >> >>>>> One of regression we faced with is related to SST26 flash series which >>>>> is used on HSDK board. The cause is that SST26 protection ops >>>>> implementation was dropped. The fix of this regression is send >>>>> as a patch in this series. >>>>> >>>> >>>> I retained most U-Boot specific code as is (like support for BANK >>>> address registers, restriction in transfer sizes) but I somehow >>>> overlooked this part. Sorry for that >>>> >>>>> However there are another regressions. I.E: we also faced with broken >>>>> SPI flash on another SNPS boards - AXS101 and AXS103. They use different >>>>> flash IC (n25q512ax3) and I didn't investigate the cause yet. >>>>> >>>> >>>> Could you provide more details here: >>>> What exactly fails? Is the detected correctly? Does reads work fine? Is >>>> Erase or Write broken? >>> >>> It seems to me that something is wrong with protection ops. >>> The erase and write finish wit
Re: [U-Boot] Regressions in MTD / SPI FLASH
Hi Vignesh,
that patch helps - both erase and write works fine.
For n25q512ax3:
Tested-by: "Eugeniy Paltsev "
---
Eugeniy Paltsev
From: Vignesh Raghavendra
Sent: Tuesday, September 10, 2019 08:07
To: Eugeniy Paltsev; Jagan Teki
Cc: u-boot@lists.denx.de; uboot-snps-...@synopsys.com; Alexey Brodkin;
tr...@konsulko.com
Subject: Re: Regressions in MTD / SPI FLASH
Hi,
On 10/09/19 12:18 AM, Eugeniy Paltsev wrote:
> Hi!
> Comments are inlined:
>
>> On 04/09/19 11:37 PM, Eugeniy Paltsev wrote:
>>> We faced with regressions caused by
>>> commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
>>> This switch was performed by removing entire u-boot spi-flash
>>> core implementation and copying it from another project.
>>> However the switch is performed without proper testing and
>>> investigations about fixes/improvements were made in u-boot
>>> spi-flash core. This results in regressions.
>>>
>>
>> Apologies for the trouble...
>> As stated in cover letter, this change was necessary as U-Boot SPI flash
>> stack at that time did not features such as 4 byte addressing, SFDP
>> parsing, SPI controllers with MMIO interfaces etc. Also there was need
>> to move to SPI MEM framework to support both SPI NAND and SPI NOR
>> flashes using a single SPI controller drivers.
>> I have to disagree on the part that there was no proper testing... As
>> evident from mailing list archives, patch series was reviewed by
>> multiple reviewers and tested on their platforms as well...
>> Unfortunately its impossible to get all boards owners to test it.
>
> I'm not talking about getting all customers board and testing changes on them.
> It could be done another way - i.e. like it is done for u-boot driver-model
> migration:
> by introducing the option for choosing which stack will be used and allow
> customers
> to switch the flash IC they use to new stack until some deadline.
>
I did start off with this. But maintaining two stacks is too cumbersome
and adds to code size (which is a big factor for SPL stage)
>>> One of regression we faced with is related to SST26 flash series which
>>> is used on HSDK board. The cause is that SST26 protection ops
>>> implementation was dropped. The fix of this regression is send
>>> as a patch in this series.
>>>
>>
>> I retained most U-Boot specific code as is (like support for BANK
>> address registers, restriction in transfer sizes) but I somehow
>> overlooked this part. Sorry for that
>>
>>> However there are another regressions. I.E: we also faced with broken
>>> SPI flash on another SNPS boards - AXS101 and AXS103. They use different
>>> flash IC (n25q512ax3) and I didn't investigate the cause yet.
>>>
>>
>> Could you provide more details here:
>> What exactly fails? Is the detected correctly? Does reads work fine? Is
>> Erase or Write broken?
>
> It seems to me that something is wrong with protection ops.
> The erase and write finish without errors however nothing actually happens.
>
I doubt so, because if the blocks were protected, erase/write would have failed
and Read status/Read flag status register should have reported error values.
Anyways, I guess I found a wrt how 4 Byte addressing is handled wrt n25q512*
series.
Could you try with below patch helps[1]?
If not please provide logs similar what you have provide now.
If below patch does not help, then please try enabling CONFIG_SPI_FLASH_BAR and
see if that helps.
[1]
---8<-
From 1de4c447cd4b2590c98f9ceccf8ed32029b42d36 Mon Sep 17 00:00:00 2001
From: Vignesh Raghavendra
Date: Tue, 10 Sep 2019 10:25:17 +0530
Subject: [TST PATCH] mtd: spi: spi-nor-ids: Disable SPI_NOR_4B_OPCODES
Not all variants of n25q256* and n25q512* support 4 Byte stateless
addressing and there is no easy way to discover this at runtime.
Therefore don't set SPI_NOR_4B_OPCODES for these flashes
Signed-off-by: Vignesh Raghavendra
---
drivers/mtd/spi/spi-nor-ids.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a3920ba520e0..66ac3256e8f5 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -161,12 +161,10 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("n25q064a",0x20bb17, 0, 64 * 1024, 128, SECT_4K |
SPI_NOR_QUAD_READ) },
{ INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K |
SPI_NOR_QUAD_READ) },
{ INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K |
SPI_NOR_QUAD_READ) },
- { INFO("n25q256a",0x20ba19, 0, 64 * 1024, 512, SECT_4K |
SPI_NO
[U-Boot] [PATCH v2 1/2] MTD: SPI: add missing SST26* flash IC protection ops
Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
proper testing/investigations which results in a regressions for
SST26 flash series.
Add missing SST26* flash IC protection ops which were introduced
previously by
Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs
protection ops)
Signed-off-by: Eugeniy Paltsev
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 181 +
include/linux/mtd/spi-nor.h| 4 +
3 files changed, 186 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index a6bf734830a..e6da768bf36 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -65,6 +65,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
};
extern const struct flash_info spi_nor_ids[];
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1acff745d1a..990e39d7c2f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -945,6 +945,177 @@ read_err:
}
#ifdef CONFIG_SPI_FLASH_SST
+/*
+ * sst26 flash series has its own block protection implementation:
+ * 4x - 8 KByte blocks - read & write protection bits - upper addresses
+ * 1x - 32 KByte blocks - write protection bits
+ * rest - 64 KByte blocks - write protection bits
+ * 1x - 32 KByte blocks - write protection bits
+ * 4x - 8 KByte blocks - read & write protection bits - lower addresses
+ *
+ * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
+ * will be treated as single block.
+ */
+#define SST26_BPR_8K_NUM 4
+#define SST26_MAX_BPR_REG_LEN (18 + 1)
+#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
+
+enum lock_ctl {
+ SST26_CTL_LOCK,
+ SST26_CTL_UNLOCK,
+ SST26_CTL_CHECK
+};
+
+static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl
ctl)
+{
+ switch (ctl) {
+ case SST26_CTL_LOCK:
+ cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
+ break;
+ case SST26_CTL_UNLOCK:
+ cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
+ break;
+ case SST26_CTL_CHECK:
+ return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
+ }
+
+ return false;
+}
+
+/*
+ * Lock, unlock or check lock status of the flash region of the flash
(depending
+ * on the lock_ctl value)
+ */
+static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum
lock_ctl ctl)
+{
+ struct mtd_info *mtd = >mtd;
+ u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
+ bool lower_64k = false, upper_64k = false;
+ u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
+ int ret;
+
+ /* Check length and offset for 64k alignment */
+ if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
+ dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
+ return -EINVAL;
+ }
+
+ if (ofs + len > mtd->size) {
+ dev_err(nor->dev, "range is more than device size: %#llx +
%#llx > %#llx\n",
+ ofs, len, mtd->size);
+ return -EINVAL;
+ }
+
+ /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
+ if (mtd->size != SZ_2M &&
+ mtd->size != SZ_4M &&
+ mtd->size != SZ_8M)
+ return -EINVAL;
+
+ bpr_size = 2 + (mtd->size / SZ_64K / 8);
+
+ ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
+ if (ret < 0) {
+ dev_err(nor->dev, "fail to read block-protection register\n");
+ return ret;
+ }
+
+ rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
+ lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
+
+ upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
+ lower_64k = (ofs < SST26_BOUND_REG_SIZE);
+
+ /* Lower bits in block-protection register are about 64k region */
+ bpr_ptr = lptr_64k / SZ_64K - 1;
+
+ /* Process 64K blocks region */
+ while (lptr_64k < rptr_64k) {
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+ lptr_64k += SZ_64K;
+ }
+
+ /* 32K and 8K region bits in BPR are after 64k region bits */
+ bpr_ptr = (mtd->size - 2 * SST26_BOUND_REG_SIZE) / SZ_64K;
+
+ /* Process lower 32K block region
[U-Boot] [PATCH v2 2/2] MTD: SPI: enable protection ops for SST26 flash series
Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
proper testing/investigations which results in a regressions for
SST26 flash series.
Enable protection ops for SST26 flash series which were
previously enabled by
Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs
protection ops)
Signed-off-by: Eugeniy Paltsev
---
drivers/mtd/spi/spi-nor-ids.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index a3920ba520e..6996c0a2864 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -214,10 +214,10 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("sst25wf040b", 0x621613, 0, 64 * 1024, 8, SECT_4K) },
{ INFO("sst25wf040", 0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE)
},
{ INFO("sst25wf080", 0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE)
},
- { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K |
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
- { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K) },
- { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K) },
- { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("sst26vf064b", 0xbf2643, 0, 64 * 1024, 128, SECT_4K |
SPI_NOR_HAS_SST26LOCK | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("sst26wf016", 0xbf2651, 0, 64 * 1024, 32, SECT_4K |
SPI_NOR_HAS_SST26LOCK) },
+ { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K |
SPI_NOR_HAS_SST26LOCK) },
+ { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K |
SPI_NOR_HAS_SST26LOCK) },
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO/* STMICRO */
/* ST Microelectronics -- newer production may have feature updates */
--
2.21.0
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Re: [U-Boot] [PATCH 1/1] MTD: SPI: revert removing SST26* flash IC protection ops
>On Wed, Sep 4, 2019 at 11:37 PM Eugeniy Paltsev
> wrote:
>>
>> Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
>> performs switch from previous 'spi_flash' infrastructure without
>> proper testing/investigations which results in regressions.
>>
>> Fix regression related to SST26 flash IC series which is lacking
>> protection ops implementation which were introduced previously by
>> Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs
>> protection ops)
>>
>> Signed-off-by: Eugeniy Paltsev
>> ---
>> Tom, could you please pick this patch to 2019.10?
>>
[snip]
>> + { INFO("sst26wf032", 0xbf2622, 0, 64 * 1024, 64, SECT_4K |
>> SPI_NOR_HAS_SST26LOCK) },
>> + { INFO("sst26wf064", 0xbf2643, 0, 64 * 1024, 128, SECT_4K |
>> SPI_NOR_HAS_SST26LOCK) },
>
>Thought the commit message says it is revert, the patch contents seems
>adding new changes.
Revert of removing functionality is adding functionality, isn't it? ;)
> So, better add them by saying missing
>functionalities. If possible please break the patches into multiple
>patches.
Ok, I'll split this patch for adding SST26 protection ops part and
applying this ops to corresponding flash ICs.
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Re: [U-Boot] Regressions in MTD / SPI FLASH
Hi! Comments are inlined: >On 04/09/19 11:37 PM, Eugeniy Paltsev wrote: >> We faced with regressions caused by >> commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) >> This switch was performed by removing entire u-boot spi-flash >> core implementation and copying it from another project. >> However the switch is performed without proper testing and >> investigations about fixes/improvements were made in u-boot >> spi-flash core. This results in regressions. >> > >Apologies for the trouble... >As stated in cover letter, this change was necessary as U-Boot SPI flash >stack at that time did not features such as 4 byte addressing, SFDP >parsing, SPI controllers with MMIO interfaces etc. Also there was need >to move to SPI MEM framework to support both SPI NAND and SPI NOR >flashes using a single SPI controller drivers. >I have to disagree on the part that there was no proper testing... As >evident from mailing list archives, patch series was reviewed by >multiple reviewers and tested on their platforms as well... >Unfortunately its impossible to get all boards owners to test it. I'm not talking about getting all customers board and testing changes on them. It could be done another way - i.e. like it is done for u-boot driver-model migration: by introducing the option for choosing which stack will be used and allow customers to switch the flash IC they use to new stack until some deadline. >> One of regression we faced with is related to SST26 flash series which >> is used on HSDK board. The cause is that SST26 protection ops >> implementation was dropped. The fix of this regression is send >> as a patch in this series. >> > >I retained most U-Boot specific code as is (like support for BANK >address registers, restriction in transfer sizes) but I somehow >overlooked this part. Sorry for that > >> However there are another regressions. I.E: we also faced with broken >> SPI flash on another SNPS boards - AXS101 and AXS103. They use different >> flash IC (n25q512ax3) and I didn't investigate the cause yet. >> > >Could you provide more details here: >What exactly fails? Is the detected correctly? Does reads work fine? Is >Erase or Write broken? It seems to me that something is wrong with protection ops. The erase and write finish without errors however nothing actually happens. >Could you enable debug prints in your driver as well as debug prints in >spi_mem_exec_op() (in drivers/spi/spi-mem.c) and post the logs? Here is it. As you can see all commands finish successfully however erase and write don't change flash content. ->8- AXS# sf probe && echo OK spi_flash_std_probe: slave=9fdabfc0, cs=0 9f | [6B in] 20 ba 20 10 00 00 [ret 0] SF: Detected n25q512ax3 with page size 256 Bytes, erase size 4 KiB, total 64 MiB OK AXS# sf read 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 0c 00 18 00 00 | [16B in] 53 00 f8 d9 04 00 52 fc ff ff 80 de ad be af af [ret 0] SF: 16 bytes @ 0x18 Read: OK OK AXS# md.b 0x8100 0x10 8100: 53 00 f8 d9 04 00 52 fc ff ff 80 de ad be af afS.R. AXS# sf protect unlock 0x0 0x400 && echo OK 05 | [1B in] 00 [ret 0] OK AXS# sf erase 0x18 0x1000 && echo OK 06 | [0B -] [ret 0] 21 00 18 00 00 | [0B -] [ret 0] 05 | [1B in] 02 [ret 0] 70 | [1B in] 80 [ret 0] 04 | [0B -] [ret 0] SF: 4096 bytes @ 0x18 Erased: OK OK AXS# sf read 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 0c 00 18 00 00 | [16B in] 53 00 f8 d9 04 00 52 fc ff ff 80 de ad be af af [ret 0] SF: 16 bytes @ 0x18 Read: OK OK AXS# md.b 0x8100 0x10 8100: 53 00 f8 d9 04 00 52 fc ff ff 80 de ad be af afS.R. AXS# mw 0x8100 0 5 AXS# sf write 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 06 | [0B -] [ret 0] 12 00 18 00 00 | [16B out] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 [ret 0] 05 | [1B in] 00 [ret 0] 70 | [1B in] 80 [ret 0] SF: 16 bytes @ 0x18 Written: OK OK AXS# sf read 0x8100 0x18 0x10 && echo OK device 0 offset 0x18, size 0x10 0c 00 18 00 00 | [16B in] 53 00 f8 d9 04 00 52 fc ff ff 80 de ad be af af [ret 0] SF: 16 bytes @ 0x18 Read: OK OK AXS# md.b 0x8100 0x10 8100: 53 00 f8 d9 04 00 52 fc ff ff 80 de ad be af afS.R. ->8- Here is how it should work (tested on v2018.09): ->8- AXS# sf probe && echo OK SF: Detected n25q512 with page size 256 Bytes, erase size 4 KiB, total 64 MiB OK AXS# sf read 0x8100 0x18 0x10 && echo OK device 0 offset 0x18
[U-Boot] Regressions in MTD / SPI FLASH
We faced with regressions caused by commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) This switch was performed by removing entire u-boot spi-flash core implementation and copying it from another project. However the switch is performed without proper testing and investigations about fixes/improvements were made in u-boot spi-flash core. This results in regressions. One of regression we faced with is related to SST26 flash series which is used on HSDK board. The cause is that SST26 protection ops implementation was dropped. The fix of this regression is send as a patch in this series. However there are another regressions. I.E: we also faced with broken SPI flash on another SNPS boards - AXS101 and AXS103. They use different flash IC (n25q512ax3) and I didn't investigate the cause yet. I can also expect regressions among other u-boot users and I believe that subsystem changes mustn't be done such harmful way. Eugeniy Paltsev (1): MTD: SPI: revert removing SST26* flash IC protection ops drivers/mtd/spi/sf_internal.h | 1 + drivers/mtd/spi/spi-nor-core.c | 181 + drivers/mtd/spi/spi-nor-ids.c | 8 +- include/linux/mtd/spi-nor.h| 4 + 4 files changed, 190 insertions(+), 4 deletions(-) -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] MTD: SPI: revert removing SST26* flash IC protection ops
Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
proper testing/investigations which results in regressions.
Fix regression related to SST26 flash IC series which is lacking
protection ops implementation which were introduced previously by
Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs
protection ops)
Signed-off-by: Eugeniy Paltsev
---
Tom, could you please pick this patch to 2019.10?
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 181 +
drivers/mtd/spi/spi-nor-ids.c | 8 +-
include/linux/mtd/spi-nor.h| 4 +
4 files changed, 190 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index a6bf734830a..e6da768bf36 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -65,6 +65,7 @@ struct flash_info {
#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
+#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
};
extern const struct flash_info spi_nor_ids[];
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1acff745d1a..990e39d7c2f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -945,6 +945,177 @@ read_err:
}
#ifdef CONFIG_SPI_FLASH_SST
+/*
+ * sst26 flash series has its own block protection implementation:
+ * 4x - 8 KByte blocks - read & write protection bits - upper addresses
+ * 1x - 32 KByte blocks - write protection bits
+ * rest - 64 KByte blocks - write protection bits
+ * 1x - 32 KByte blocks - write protection bits
+ * 4x - 8 KByte blocks - read & write protection bits - lower addresses
+ *
+ * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
+ * will be treated as single block.
+ */
+#define SST26_BPR_8K_NUM 4
+#define SST26_MAX_BPR_REG_LEN (18 + 1)
+#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
+
+enum lock_ctl {
+ SST26_CTL_LOCK,
+ SST26_CTL_UNLOCK,
+ SST26_CTL_CHECK
+};
+
+static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl
ctl)
+{
+ switch (ctl) {
+ case SST26_CTL_LOCK:
+ cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
+ break;
+ case SST26_CTL_UNLOCK:
+ cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
+ break;
+ case SST26_CTL_CHECK:
+ return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
+ }
+
+ return false;
+}
+
+/*
+ * Lock, unlock or check lock status of the flash region of the flash
(depending
+ * on the lock_ctl value)
+ */
+static int sst26_lock_ctl(struct spi_nor *nor, loff_t ofs, uint64_t len, enum
lock_ctl ctl)
+{
+ struct mtd_info *mtd = >mtd;
+ u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
+ bool lower_64k = false, upper_64k = false;
+ u8 bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
+ int ret;
+
+ /* Check length and offset for 64k alignment */
+ if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1))) {
+ dev_err(nor->dev, "length or offset is not 64KiB allighned\n");
+ return -EINVAL;
+ }
+
+ if (ofs + len > mtd->size) {
+ dev_err(nor->dev, "range is more than device size: %#llx +
%#llx > %#llx\n",
+ ofs, len, mtd->size);
+ return -EINVAL;
+ }
+
+ /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
+ if (mtd->size != SZ_2M &&
+ mtd->size != SZ_4M &&
+ mtd->size != SZ_8M)
+ return -EINVAL;
+
+ bpr_size = 2 + (mtd->size / SZ_64K / 8);
+
+ ret = nor->read_reg(nor, SPINOR_OP_READ_BPR, bpr_buff, bpr_size);
+ if (ret < 0) {
+ dev_err(nor->dev, "fail to read block-protection register\n");
+ return ret;
+ }
+
+ rptr_64k = min_t(u32, ofs + len, mtd->size - SST26_BOUND_REG_SIZE);
+ lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
+
+ upper_64k = ((ofs + len) > (mtd->size - SST26_BOUND_REG_SIZE));
+ lower_64k = (ofs < SST26_BOUND_REG_SIZE);
+
+ /* Lower bits in block-protection register are about 64k region */
+ bpr_ptr = lptr_64k / SZ_64K - 1;
+
+ /* Process 64K blocks region */
+ while (lptr_64k < rptr_64k) {
+ if (sst26_process_bpr(bpr_size, bpr_buff, bpr_ptr, ctl))
+ return EACCES;
+
+ bpr_ptr++;
+ lptr_64k += SZ_64K;
+ }
+
+ /* 32K and 8K region bits in BPR are after 64
[U-Boot] [PATCH] ARC: AXS10x: drop NAND support
On AXS10x boards we have non-standard NAND controller
which was never really used a lot as there're other much more
convenient [as they are standard & removable] persistent media
like SD-card and USB mass storage.
Moreover after recent changes we face with some NAND controller
runtime issues. So instead of keeping support of yet another
non-standard peripheral we're dropping its support for good.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/axs10x/Makefile | 1 -
board/synopsys/axs10x/nand.c | 242 -
configs/axs101_defconfig | 1 -
configs/axs103_defconfig | 1 -
include/configs/axs10x.h | 6 -
5 files changed, 251 deletions(-)
delete mode 100644 board/synopsys/axs10x/nand.c
diff --git a/board/synopsys/axs10x/Makefile b/board/synopsys/axs10x/Makefile
index 340e12c4432..dd5ee680e7b 100644
--- a/board/synopsys/axs10x/Makefile
+++ b/board/synopsys/axs10x/Makefile
@@ -3,4 +3,3 @@
# Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved.
obj-y += axs10x.o
-obj-$(CONFIG_CMD_NAND) += nand.o
diff --git a/board/synopsys/axs10x/nand.c b/board/synopsys/axs10x/nand.c
deleted file mode 100644
index 8108460f581..000
--- a/board/synopsys/axs10x/nand.c
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include "axs10x.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define BUS_WIDTH 8 /* AXI data bus width in bytes */
-
-/* DMA buffer descriptor bits & masks */
-#define BD_STAT_OWN(1 << 31)
-#define BD_STAT_BD_FIRST (1 << 3)
-#define BD_STAT_BD_LAST(1 << 2)
-#define BD_SIZES_BUFFER1_MASK 0xfff
-
-#define BD_STAT_BD_COMPLETE(BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
-
-/* Controller command flags */
-#define B_WFR (1 << 19) /* 1b - Wait for ready */
-#define B_LC (1 << 18) /* 1b - Last cycle */
-#define B_IWC (1 << 13) /* 1b - Interrupt when complete */
-
-/* NAND cycle types */
-#define B_CT_ADDRESS (0x0 << 16) /* Address operation*/
-#define B_CT_COMMAND (0x1 << 16) /* Command operation*/
-#define B_CT_WRITE (0x2 << 16) /* Write operation */
-#define B_CT_READ (0x3 << 16) /* Write operation */
-
-enum nand_isr_t {
- NAND_ISR_DATAREQUIRED = 0,
- NAND_ISR_TXUNDERFLOW,
- NAND_ISR_TXOVERFLOW,
- NAND_ISR_DATAAVAILABLE,
- NAND_ISR_RXUNDERFLOW,
- NAND_ISR_RXOVERFLOW,
- NAND_ISR_TXDMACOMPLETE,
- NAND_ISR_RXDMACOMPLETE,
- NAND_ISR_DESCRIPTORUNAVAILABLE,
- NAND_ISR_CMDDONE,
- NAND_ISR_CMDAVAILABLE,
- NAND_ISR_CMDERROR,
- NAND_ISR_DATATRANSFEROVER,
- NAND_ISR_NONE
-};
-
-enum nand_regs_t {
- AC_FIFO = 0,/* address and command fifo */
- IDMAC_BDADDR = 0x18,/* idmac descriptor list base address */
- INT_STATUS = 0x118, /* interrupt status register */
- INT_CLR_STATUS = 0x120, /* interrupt clear status register */
-};
-
-struct nand_bd {
- uint32_t status;/* DES0 */
- uint32_t sizes; /* DES1 */
- uint32_t buffer_ptr0; /* DES2 */
- uint32_t buffer_ptr1; /* DES3 */
-};
-
-#define NAND_REG_WRITE(r, v) \
- writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
-#define NAND_REG_READ(r) \
- readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
-
-static struct nand_bd *bd; /* DMA buffer descriptors */
-
-/**
- * axs101_nand_write_buf - write buffer to chip
- * @mtd: MTD device structure
- * @buf: data buffer
- * @len: number of bytes to write
- */
-static uint32_t nand_flag_is_set(uint32_t flag)
-{
- uint32_t reg = NAND_REG_READ(INT_STATUS);
-
- if (reg & (1 << NAND_ISR_CMDERROR))
- return 0;
-
- if (reg & (1 << flag)) {
- NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
- return 1;
- }
-
- return 0;
-}
-
-/**
- * axs101_nand_write_buf - write buffer to chip
- * @mtd: MTD device structure
- * @buf: data buffer
- * @len: number of bytes to write
- */
-static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
- int len)
-{
- struct bounce_buffer bbstate;
-
- bounce_buffer_start(, (void *)buf, len, GEN_BB_READ);
-
- /* Setup buffer descriptor */
- writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, >status);
- writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, >sizes);
- writel(bbstate.bounce_buffer, >buffer_ptr0);
- writel(0, >buffer_ptr1);
-
- /* Flu
[U-Boot] [PATCH 3/3] ARC: [plat-axs10x]: migrate to DM_MMC
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/axs10x_mb.dtsi| 28
board/synopsys/axs10x/axs10x.c | 29 -
configs/axs103_defconfig | 2 ++
3 files changed, 30 insertions(+), 29 deletions(-)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index dfc03810ca0..caff5158b16 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -31,6 +31,25 @@
#clock-cells = <0>;
u-boot,dm-pre-reloc;
};
+
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ /*
+* DW sdio controller has external ciu clock
divider
+* controlled via register in SDIO IP. It
divides
+* sdio_ref_clk (which comes from CGU) by 16 for
+* default. So default mmcclk clock (which comes
+* to sdk_in) is 2500 Hz.
+*/
+ clock-frequency = <2500>;
+ #clock-cells = <0>;
+ };
+
+ mmcclk_biu: mmcclk-biu {
+ compatible = "fixed-clock";
+ clock-frequency = <5000>;
+ #clock-cells = <0>;
+ };
};
ethernet@18000 {
@@ -53,6 +72,15 @@
reg = < 0x6 0x100 >;
};
+ mmc: mmc@15000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x15000 0x400>;
+ bus-width = <4>;
+ clocks = <_biu>, <_ciu>;
+ clock-names = "biu", "ciu";
+ max-frequency = <2500>;
+ };
+
uart0: serial0@22000 {
compatible = "snps,dw-apb-uart";
reg = <0x22000 0x100>;
diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c
index ffa7c154b54..7c4fcf281cb 100644
--- a/board/synopsys/axs10x/axs10x.c
+++ b/board/synopsys/axs10x/axs10x.c
@@ -11,35 +11,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int board_mmc_init(bd_t *bis)
-{
- struct dwmci_host *host = NULL;
-
- host = malloc(sizeof(struct dwmci_host));
- if (!host) {
- printf("dwmci_host malloc fail!\n");
- return 1;
- }
-
- memset(host, 0, sizeof(struct dwmci_host));
- host->name = "Synopsys Mobile storage";
- host->ioaddr = (void *)ARC_DWMMC_BASE;
- host->buswidth = 4;
- host->dev_index = 0;
- host->bus_hz = 5000;
-
- add_dwmci(host, host->bus_hz / 2, 40);
-
- return 0;
-}
-
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct dwmci_host *host = mmc->priv;
-
- return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
-}
-
#define AXS_MB_CREG0xE0011000
int board_early_init_f(void)
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index e7894d297cd..31c8fd152a6 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -35,7 +35,9 @@ CONFIG_DM=y
CONFIG_DM_GPIO=y
CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
+CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_BAR=y
--
2.14.5
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[U-Boot] [PATCH 2/3] ARC: [plat-hsdk]: migrate to DM_MMC
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/hsdk.dts | 26 ++
board/synopsys/hsdk/hsdk.c | 41 ++---
configs/hsdk_defconfig | 2 ++
3 files changed, 34 insertions(+), 35 deletions(-)
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index f024b96925e..de3c9daeefa 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -86,6 +86,32 @@
reg = <0xf006 0x100>;
};
+ mmcclk_ciu: mmcclk-ciu {
+ compatible = "fixed-clock";
+ /*
+* DW sdio controller has external ciu clock divider
+* controlled via register in SDIO IP. Due to its
+* unexpected default value (it should divide by 1
+* but it divides by 8) SDIO IP uses wrong clock and
+* works unstable (see STAR 9001204800)
+* We switched to the minimum possible value of the
+* divisor (div-by-2) in HSDK platform code.
+* So default mmcclk ciu clock is 5000 Hz.
+*/
+ clock-frequency = <5000>;
+ #clock-cells = <0>;
+ };
+
+ mmc: mmc0@f000a000 {
+ compatible = "snps,dw-mshc";
+ reg = <0xf000a000 0x400>;
+ bus-width = <4>;
+ fifo-depth = <256>;
+ clocks = <_clk CLK_SYS_SDIO>, <_ciu>;
+ clock-names = "biu", "ciu";
+ max-frequency = <2500>;
+ };
+
spi0: spi@f002 {
compatible = "snps,dw-apb-ssi";
reg = <0xf002 0x1000>;
diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c
index 8a2c201477c..ac4d980c49f 100644
--- a/board/synopsys/hsdk/hsdk.c
+++ b/board/synopsys/hsdk/hsdk.c
@@ -982,6 +982,12 @@ int board_early_init_f(void)
*/
init_memory_bridge();
+ /*
+* Switch SDIO external ciu clock divider from default div-by-8 to
+* minimum possible div-by-2.
+*/
+ writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
+
return 0;
}
@@ -1019,41 +1025,6 @@ int board_late_init(void)
return 0;
}
-int board_mmc_getcd(struct mmc *mmc)
-{
- struct dwmci_host *host = mmc->priv;
-
- return !(dwmci_readl(host, DWMCI_CDETECT) & 1);
-}
-
-int board_mmc_init(bd_t *bis)
-{
- struct dwmci_host *host = NULL;
-
- host = malloc(sizeof(struct dwmci_host));
- if (!host) {
- printf("dwmci_host malloc fail!\n");
- return 1;
- }
-
- /*
-* Switch SDIO external ciu clock divider from default div-by-8 to
-* minimum possible div-by-2.
-*/
- writel(SDIO_UHS_REG_EXT_DIV_2, (void __iomem *)SDIO_UHS_REG_EXT);
-
- memset(host, 0, sizeof(struct dwmci_host));
- host->name = "Synopsys Mobile storage";
- host->ioaddr = (void *)ARC_DWMMC_BASE;
- host->buswidth = 4;
- host->dev_index = 0;
- host->bus_hz = 5000;
-
- add_dwmci(host, host->bus_hz / 2, 40);
-
- return 0;
-}
-
int checkboard(void)
{
puts("Board: Synopsys ARC HS Development Kit\n");
diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index e0eb6bdb343..e28ceae289c 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -38,7 +38,9 @@ CONFIG_CLK_HSDK=y
CONFIG_DM_GPIO=y
CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
+CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
+CONFIG_MMC_DW_SNPS=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SST=y
--
2.14.5
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[U-Boot] [PATCH 1/3] ARC: dwmmc: Adding DesignWare MMC driver support for ARC devboards
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys
ARC devboards. It is created to switch ARC devboards to use DM_MMC.
It required information such as clocks (Bus Interface Unit clock,
Card Interface Unit clock) and SDIO bus width.
Signed-off-by: Eugeniy Paltsev
---
MAINTAINERS | 7 +
doc/device-tree-bindings/mmc/snps,dw-mmc.txt | 33 +
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/snps_dw_mmc.c| 199 +++
5 files changed, 250 insertions(+)
create mode 100644 doc/device-tree-bindings/mmc/snps,dw-mmc.txt
create mode 100644 drivers/mmc/snps_dw_mmc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 0fb089807c5..7a197f75a9b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -79,6 +79,13 @@ L: uboot-snps-...@synopsys.com
F: doc/device-tree-bindings/gpio/snps,creg-gpio.txt
F: drivers/gpio/hsdk-creg-gpio.c
+ARC SYNOPSYS DW MMC EXTENSIONS
+M: Eugeniy Paltsev
+S: Maintained
+L: uboot-snps-...@synopsys.com
+F: doc/device-tree-bindings/mmc/snps,dw-mmc.txt
+F: drivers/mmc/snps_dw_mmc.c
+
ARM
M: Albert Aribaud
S: Maintained
diff --git a/doc/device-tree-bindings/mmc/snps,dw-mmc.txt
b/doc/device-tree-bindings/mmc/snps,dw-mmc.txt
new file mode 100644
index 000..69faefa95e9
--- /dev/null
+++ b/doc/device-tree-bindings/mmc/snps,dw-mmc.txt
@@ -0,0 +1,33 @@
+Synopsys Designware Mobile Storage Host Controller extensions
+used in Synopsys ARC devboards
+
+Required Properties:
+
+* compatible: should be - "snps,dw-mshc".
+* bus-width: number of data lines connected to the controller.
+* clocks: from common clock binding: handle to biu and ciu clocks for the
+ bus interface unit clock and the card interface unit clock.
+* clock-names: from common clock binding: Shall be "biu" and "ciu".
+
+Optional properties:
+
+* fifo-depth: The maximum size of the tx/rx fifo's. If this property is not
+ specified, the default value of the fifo size is determined from the
+ controller registers.
+* fifo-mode: Don't use DMA.
+* max-frequency: Maximum operating clock frequency, driver uses 'ciu' clock
+ frequency if it is not set.
+
+Example:
+
+mmc0@f000a000 {
+ compatible = "snps,dw-mshc";
+ reg = <0xf000a000 0x400>;
+
+ bus-width = <4>;
+ fifo-depth = <256>;
+ clocks = <_biu>, <_ciu>;
+ clock-names = "biu", "ciu";
+ max-frequency = <2500>;
+};
+
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index fbd13964a08..bac0d683ea9 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -221,6 +221,16 @@ config MMC_DW_SOCFPGA
Synopsys DesignWare Memory Card Interface driver. Select this option
for platforms based on Altera SOCFPGA.
+config MMC_DW_SNPS
+ bool "Extensions for DW Memory Card Interface used in Synopsys ARC
devboards"
+ depends on MMC_DW
+ depends on DM_MMC
+ depends on OF_CONTROL
+ depends on CLK
+ help
+ This selects support for Synopsys DesignWare Memory Card Interface
driver
+ extensions used in various Synopsys ARC devboards.
+
config MMC_MESON_GX
bool "Meson GX EMMC controller support"
depends on DM_MMC && BLK && ARCH_MESON
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 801a26d8219..14aede34f15 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_MMC_DW_EXYNOS) += exynos_dw_mmc.o
obj-$(CONFIG_MMC_DW_K3)+= hi6220_dw_mmc.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += rockchip_dw_mmc.o
obj-$(CONFIG_MMC_DW_SOCFPGA) += socfpga_dw_mmc.o
+obj-$(CONFIG_MMC_DW_SNPS) += snps_dw_mmc.o
obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
diff --git a/drivers/mmc/snps_dw_mmc.c b/drivers/mmc/snps_dw_mmc.c
new file mode 100644
index 000..5a413f0ec78
--- /dev/null
+++ b/drivers/mmc/snps_dw_mmc.c
@@ -0,0 +1,199 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Synopsys DesignWare Multimedia Card Interface driver
+ * extensions used in various Synopsys ARC devboards.
+ *
+ * Copyright (C) 2019 Synopsys
+ * Author: Eugeniy Paltsev
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CLOCK_MIN 40 /* 400 kHz */
+#define FIFO_MIN 8
+#define FIFO_MAX 4096
+
+struct snps_dwmci_plat {
+ struct mmc_config cfg;
+ struct mmc mmc;
+};
+
+struct snps_dwmci_priv_data {
+ struct dwmci_host host;
+ u32 f_max;
+};
+
+static int snps_dwmmc_clk_setup(struct udevice *dev)
+{
+ s
[U-Boot] [PATCH 0/3] ARC: DM_MMC migration
Introduce DesignWare MMC driver extension and migrate several ARC devboard to DM_MMC Eugeniy Paltsev (3): ARC: dwmmc: Adding DesignWare MMC driver support for ARC devboards ARC: [plat-hsdk]: migrate to DM_MMC ARC: [plat-axs10x]: migrate to DM_MMC MAINTAINERS | 7 + arch/arc/dts/axs10x_mb.dtsi | 28 arch/arc/dts/hsdk.dts| 33 + board/synopsys/axs10x/axs10x.c | 29 board/synopsys/hsdk/hsdk.c | 41 +- configs/axs103_defconfig | 2 + configs/hsdk_defconfig | 2 + doc/device-tree-bindings/mmc/snps,dw-mmc.txt | 33 + drivers/mmc/Kconfig | 10 ++ drivers/mmc/Makefile | 1 + drivers/mmc/snps_dw_mmc.c| 199 +++ 11 files changed, 321 insertions(+), 64 deletions(-) create mode 100644 doc/device-tree-bindings/mmc/snps,dw-mmc.txt create mode 100644 drivers/mmc/snps_dw_mmc.c -- 2.14.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [uboot-snps-arc] [PATCH v3 2/5] dts: switch spi-flash to jedec, spi-nor compatible
Hi Neil,
On Tue, 2019-01-15 at 13:59 +0100, Neil Armstrong wrote:
> There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot
> dts files. This compatible has been added in sf_probe, let use it.
>
> This patch switches to jedec,spi-nor when spi-flash is used in the DTS
> and DTSI files, and removed spi-flash when jedec,spi-nor is already
> present.
>
> The x86 dts are switched in a separate commit since it depends on a change
> in fdtdec.
>
> Signed-off-by: Neil Armstrong
> Acked-by: Stefan Roese
> Reviewed-by: Simon Goldschmidt
> ---
For the ARC part:
> arch/arc/dts/axs10x_mb.dtsi | 2 +-
> arch/arc/dts/hsdk.dts | 2 +-
Reviewed-by: Evgeniy Paltsev
> diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
> index dfc03810ca..b5aacd5170 100644
> --- a/arch/arc/dts/axs10x_mb.dtsi
> +++ b/arch/arc/dts/axs10x_mb.dtsi
> @@ -71,7 +71,7 @@
> clock-names = "spi_clk";
> cs-gpio = <_gpio 0>;
> spi_flash@0 {
> - compatible = "spi-flash";
> + compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <400>;
> };
> diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
> index f024b96925..5e9ba054a4 100644
> --- a/arch/arc/dts/hsdk.dts
> +++ b/arch/arc/dts/hsdk.dts
> @@ -96,7 +96,7 @@
> clock-names = "spi_clk";
> cs-gpio = <_gpio 0>;
> spi_flash@0 {
> - compatible = "spi-flash";
> + compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <400>;
> };
>
--
Eugeniy Paltsev
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[U-Boot] [PATCH] ARC: HSDK: Fix timer frequency value
CPU (and hence cpu timers) on HSDK board runs at 500MHz after
preloader so fix wrong CPU frequency value in hsdk.dts
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/hsdk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index e41e4ce84b..673bc5b26a 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -20,7 +20,7 @@
core_clk: core_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <10>;
+ clock-frequency = <5>;
u-boot,dm-pre-reloc;
};
};
--
2.14.4
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[U-Boot] [PATCH] ARC: AXS10x: add tool and make target to generate bsp
AXS10x boards have preloader that reads SPI flash pages and searches
special image header to fetch and load binary.
Add tool, make target (bsp-generate) to generate
update script and u-boot binary image with header for preloader.
Also add script to default environment to apply updates.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/axs10x/config.mk| 23 +
board/synopsys/axs10x/headerize-axs.py | 176 +
include/configs/axs10x.h | 7 ++
3 files changed, 206 insertions(+)
create mode 100644 board/synopsys/axs10x/config.mk
create mode 100644 board/synopsys/axs10x/headerize-axs.py
diff --git a/board/synopsys/axs10x/config.mk b/board/synopsys/axs10x/config.mk
new file mode 100644
index 00..db04b986d1
--- /dev/null
+++ b/board/synopsys/axs10x/config.mk
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+
+bsp-generate: u-boot u-boot.bin
+ifdef CONFIG_ISA_ARCV2
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-axs.py \
+ --header-type v2 \
+ --arc-id 0x53 \
+ --spi-flash-offset 0x20 \
+ --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+else
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-axs.py \
+ --header-type v1 \
+ --arc-id 0x434 \
+ --spi-flash-offset 0x0 \
+ --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+endif
+ $(Q)mkimage -T script -C none -n 'uboot update script' \
+ -d $(srctree)/u-boot-update.txt \
+ $(srctree)/u-boot-update.img &> /dev/null
diff --git a/board/synopsys/axs10x/headerize-axs.py
b/board/synopsys/axs10x/headerize-axs.py
new file mode 100644
index 00..fa6aaf350c
--- /dev/null
+++ b/board/synopsys/axs10x/headerize-axs.py
@@ -0,0 +1,176 @@
+#!/usr/bin/env python3
+
+#we can use binascii instead of zlib
+import os, getopt, sys, zlib
+from elftools.elf.elffile import ELFFile
+
+
+def usage(exit_code):
+print("typical usage:")
+print("AXS101:")
+print(sys.argv[0] + \
+" --header-type v1 --arc-id 0x434 --spi-flash-offset 0x0 --image
u-boot.bin --elf u-boot")
+print("AXS103:")
+print(sys.argv[0] + \
+" --header-type v2 --arc-id 0x53 --spi-flash-offset 0x20 --image
u-boot.bin --elf u-boot")
+sys.exit(exit_code)
+
+
+def elf_get_entry(filename):
+with open(filename, 'rb') as f:
+elffile = ELFFile(f)
+return elffile.header['e_entry']
+
+
+def calc_check_sum(filename):
+# Calculate u-boot image check_sum: it is sum of all u-boot binary bytes
+with open(filename, "rb") as file:
+ba = bytearray(file.read())
+return sum(ba) & 0xFF
+
+
+def arg_verify(uboot_bin_filename, uboot_elf_filename, header_type):
+if not os.path.isfile(uboot_bin_filename):
+print("uboot bin file not exists: " + uboot_bin_filename)
+sys.exit(2)
+
+if not os.path.isfile(uboot_elf_filename):
+print("uboot elf file not exists: " + uboot_elf_filename)
+sys.exit(2)
+
+if header_type not in ("v1", "v2"):
+print("unknown header type: " + header_type)
+print("choose between 'v1' (most likely AXS101) and 'v2' (most likely
AXS103)")
+sys.exit(2)
+
+
+def main():
+try:
+opts, args = getopt.getopt(sys.argv[1:],
+"ht:a:s:i:l:e:",
+["help", "header-type=", "arc-id=", "spi-flash-offset=", "image=",
"elf="])
+except getopt.GetoptError as err:
+print(err)
+usage(2)
+
+# default filenames
+uboot_elf_filename = "u-boot"
+uboot_bin_filename = "u-boot.bin"
+headerised_filename = "u-boot.head"
+uboot_scrypt_file = "u-boot-update.txt"
+
+# default values
+spi_flash_offset= 0x20
+header_type = "v2"
+arc_id = 0x53
+
+# initial header values: place where preloader will store u-boot binary,
+# should be equal to CONFIG_SYS_TEXT_BASE
+image_copy_adr = 0x8100
+
+# initial constant header values, do not change these values
+magic1 = 0xdeadbeafaf # big endian byte order
+magic2 = [# big endian byte order
+0x20202a2020202020202020202a20202020207c5c2e20202020202e2f7c20202020207c2d,
+0x2e5c2020202f2e2d7c20202020205c2020602d2d2d6020202f20202020202f205f202020,
+0x205f20205c20202020207c205f60712070205f207c2020202020272e5f3d2f205c3d5f2e,
+0x272020202020202020605c202f60202020202020202020202020206f2020202020202020]
+
+for opt, arg in opts:
+if opt in ('-h', "--help"):usage
[U-Boot] [PATCH v2] AXS10x: add spi flash support
AXS10x boards have n25q512 spi flash IC, so add corresponding
nodes to device tree and enaple corresponding options in
defconfig.
Signed-off-by: Eugeniy Paltsev
---
NOTE: this patch has prerequisite:
http://patchwork.ozlabs.org/patch/926871/
Changes v1->v2:
* change SPI CS gpio compatible name.
arch/arc/dts/axs10x_mb.dtsi | 34 ++
configs/axs101_defconfig| 12
configs/axs103_defconfig| 12
3 files changed, 58 insertions(+)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 3855a34dc2..dfc03810ca 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -4,6 +4,10 @@
*/
/ {
+ aliases {
+ spi0 =
+ };
+
axs10x_mb@e000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -56,5 +60,35 @@
reg-shift = <2>;
reg-io-width = <4>;
};
+
+ spi0: spi@0 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <400>;
+ clocks = <>;
+ clock-names = "spi_clk";
+ cs-gpio = <_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <400>;
+ };
+ };
+
+ cs_gpio: gpio@11218 {
+ compatible = "snps,creg-gpio";
+ reg = <0x11218 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "axs-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <1>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
};
};
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index d056719e14..a981398cb5 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -15,6 +15,8 @@ CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@@ -30,8 +32,15 @@ CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
@@ -39,6 +48,9 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index f0fccf4d9f..e524e6a9c6 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -15,6 +15,8 @@ CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@@ -30,8 +32,15 @@ CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
@@ -39,6 +48,9 @@ CONFIG_DM_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_OHCI_HCD=y
--
2.14.3
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[U-Boot] [PATCH] AXS10x: add spi flash support
AXS10x boards have n25q512 spi flash IC, so add corresponding
nodes to device tree and enaple corresponding options in
defconfig.
Signed-off-by: Eugeniy Paltsev
---
NOTE: this patch has prerequisite:
http://patchwork.ozlabs.org/patch/926871/
arch/arc/dts/axs10x_mb.dtsi | 34 ++
configs/axs101_defconfig| 12
configs/axs103_defconfig| 12
3 files changed, 58 insertions(+)
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index 3855a34dc2..56b993fdfc 100644
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -4,6 +4,10 @@
*/
/ {
+ aliases {
+ spi0 =
+ };
+
axs10x_mb@e000 {
compatible = "simple-bus";
#address-cells = <1>;
@@ -56,5 +60,35 @@
reg-shift = <2>;
reg-io-width = <4>;
};
+
+ spi0: spi@0 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <400>;
+ clocks = <>;
+ clock-names = "spi_clk";
+ cs-gpio = <_gpio 0>;
+ spi_flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <400>;
+ };
+ };
+
+ cs_gpio: gpio@11218 {
+ compatible = "snps,hsdk-creg-gpio";
+ reg = <0x11218 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "axs-spi-cs";
+ gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <1>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
+ };
};
};
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 25b10888ce..ae2f92faab 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -12,6 +12,8 @@ CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@@ -27,13 +29,23 @@ CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index b9d387b88a..6b0edd4127 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -12,6 +12,8 @@ CONFIG_SYS_PROMPT="AXS# "
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@@ -27,13 +29,23 @@ CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
CONFIG_MMC_DW=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_OHCI_HCD=y
--
2.14.3
___
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U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/2] CREG GPIO: add device tree bindings
Signed-off-by: Eugeniy Paltsev
---
MAINTAINERS | 1 +
doc/device-tree-bindings/gpio/snps,creg-gpio.txt | 43
2 files changed, 44 insertions(+)
create mode 100644 doc/device-tree-bindings/gpio/snps,creg-gpio.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 642c448093..0ea730e33c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -74,6 +74,7 @@ ARC HSDK CREG GPIO
M: Eugeniy Paltsev
S: Maintained
L: uboot-snps-...@synopsys.com
+F: doc/device-tree-bindings/gpio/snps,creg-gpio.txt
F: drivers/gpio/hsdk-creg-gpio.c
ARM
diff --git a/doc/device-tree-bindings/gpio/snps,creg-gpio.txt
b/doc/device-tree-bindings/gpio/snps,creg-gpio.txt
new file mode 100644
index 00..46ceb65c53
--- /dev/null
+++ b/doc/device-tree-bindings/gpio/snps,creg-gpio.txt
@@ -0,0 +1,43 @@
+GPIO via CREG (control registers) driver
+
+31 975 0 < bit number
+| ||| |
+[ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
+ ^^
+ ||
+write 0x2 == set output to "1" (activate)
+write 0x3 == set output to "0" (deactivate)
+
+Required properties:
+- compatible : "snps,creg-gpio"
+- reg : Exactly one register range with length 0x4.
+- #gpio-cells : Should be one - the pin number.
+- gpio-controller : Marks the device node as a GPIO controller.
+- gpio-count: Number of GPIO pins.
+- gpio-bit-per-line: Number of bits per gpio line (see picture).
+- gpio-first-shift: Shift (in bits) of the first GPIO field in register
+ (see picture).
+- gpio-activate-val: Value should be set in corresponding field to set
+ output to "1" (see picture). Applied to all GPIO ports.
+- gpio-deactivate-val: Value should be set in corresponding field to set
+ output to "0" (see picture). Applied to all GPIO ports.
+
+Optional properties:
+- gpio-bank-name: name of bank (as default driver name is used is used)
+- gpio-default-val: array of default output values (must me 0 or 1)
+
+Example (see picture):
+
+gpio: gpio@f00014b0 {
+ compatible = "snps,creg-gpio";
+ reg = <0xf00014b0 0x4>;
+ gpio-controller;
+ #gpio-cells = <1>;
+ gpio-bank-name = "hsdk-spi-cs";
+ gpio-count = <2>;
+ gpio-first-shift = <5>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <2>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1 1>;
+};
--
2.14.3
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 0/2] GPIO: CREG: improve flexibility of hsdk-creg-gpio driver
CREG GPIO is a driver for weird soc-specific output ports, which are controlled by some fields in memory mapped register. Example: 31 975 0 < bit number | ||| | [ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register ^^ || write 0x2 == set output to "1" (activate) write 0x3 == set output to "0" (deactivate) As of tooday we only support fixed (hardcoded) bit per gpio line, activate / deactivatei and shift values. Fix that by read them from device tree to be able to use this driver for other boards. Eugeniy Paltsev (2): GPIO: CREG: improve flexibility of hsdk-creg-gpio driver CREG GPIO: add device tree bindings MAINTAINERS | 1 + arch/arc/dts/hsdk.dts| 7 +- doc/device-tree-bindings/gpio/snps,creg-gpio.txt | 43 ++ drivers/gpio/hsdk-creg-gpio.c| 103 ++- 4 files changed, 131 insertions(+), 23 deletions(-) create mode 100644 doc/device-tree-bindings/gpio/snps,creg-gpio.txt -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] GPIO: CREG: improve flexibility of hsdk-creg-gpio driver
CREG GPIO is a driver for weird soc-specific output ports, which are
controlled by some fields in memory mapped register.
Example:
31 975 0 < bit number
| ||| |
[ not used | gpio-1 | gpio-0 | <-shift-> ] < 32 bit register
^^
||
write 0x2 == set output to "1" (activate)
write 0x3 == set output to "0" (deactivate)
As of tooday we only support fixed (hardcoded) bit per gpio line,
activate / deactivatei and shift values. Fix that by read them from
device tree to be able to use this driver for other boards.
Remove "hsdk" prefix from compatible string as this driver can be
used with different boards like HSDK, AXS101, AXS103, etc.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/dts/hsdk.dts | 7 ++-
drivers/gpio/hsdk-creg-gpio.c | 103 +-
2 files changed, 87 insertions(+), 23 deletions(-)
diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
index 264512877e..e41e4ce84b 100644
--- a/arch/arc/dts/hsdk.dts
+++ b/arch/arc/dts/hsdk.dts
@@ -101,11 +101,16 @@
};
cs_gpio: gpio@f00014b0 {
- compatible = "snps,hsdk-creg-gpio";
+ compatible = "snps,creg-gpio";
reg = <0xf00014b0 0x4>;
gpio-controller;
#gpio-cells = <1>;
gpio-bank-name = "hsdk-spi-cs";
gpio-count = <1>;
+ gpio-first-shift = <0>;
+ gpio-bit-per-line = <2>;
+ gpio-activate-val = <2>;
+ gpio-deactivate-val = <3>;
+ gpio-default-val = <1>;
};
};
diff --git a/drivers/gpio/hsdk-creg-gpio.c b/drivers/gpio/hsdk-creg-gpio.c
index 084a2da652..800027f18e 100644
--- a/drivers/gpio/hsdk-creg-gpio.c
+++ b/drivers/gpio/hsdk-creg-gpio.c
@@ -16,25 +16,24 @@
#include
#include
-#define HSDK_CREG_MAX_GPIO 8
-
-#define GPIO_ACTIVATE 0x2
-#define GPIO_DEACTIVATE0x3
-#define GPIO_PIN_MASK 0x3
-#define BIT_PER_GPIO 2
+#define DRV_NAME "gpio_creg"
struct hsdk_creg_gpio {
- uint32_t *regs;
+ u32 *regs;
+ u8 shift;
+ u8 activate;
+ u8 deactivate;
+ u8 bit_per_gpio;
};
static int hsdk_creg_gpio_set_value(struct udevice *dev, unsigned oft, int val)
{
struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
- uint32_t reg = readl(hcg->regs);
- uint32_t cmd = val ? GPIO_DEACTIVATE : GPIO_ACTIVATE;
+ u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift;
+ u32 reg = readl(hcg->regs);
- reg &= ~(GPIO_PIN_MASK << (oft * BIT_PER_GPIO));
- reg |= (cmd << (oft * BIT_PER_GPIO));
+ reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift);
+ reg |= ((val ? hcg->deactivate : hcg->activate) << reg_shift);
writel(reg, hcg->regs);
@@ -51,7 +50,9 @@ static int hsdk_creg_gpio_direction_output(struct udevice
*dev, unsigned oft,
static int hsdk_creg_gpio_direction_input(struct udevice *dev, unsigned oft)
{
- pr_err("hsdk-creg-gpio can't be used as input!\n");
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ pr_err("%s can't be used as input!\n", uc_priv->bank_name);
return -ENOTSUPP;
}
@@ -59,10 +60,11 @@ static int hsdk_creg_gpio_direction_input(struct udevice
*dev, unsigned oft)
static int hsdk_creg_gpio_get_value(struct udevice *dev, unsigned int oft)
{
struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
- uint32_t val = readl(hcg->regs);
+ u32 val = readl(hcg->regs);
- val = (val >> (oft * BIT_PER_GPIO)) & GPIO_PIN_MASK;
- return (val == GPIO_DEACTIVATE) ? 1 : 0;
+ val >>= oft * hcg->bit_per_gpio + hcg->shift;
+ val &= GENMASK(hcg->bit_per_gpio - 1, 0);
+ return (val == hcg->deactivate) ? 1 : 0;
}
static const struct dm_gpio_ops hsdk_creg_gpio_ops = {
@@ -76,17 +78,74 @@ static int hsdk_creg_gpio_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct hsdk_creg_gpio *hcg = dev_get_priv(dev);
+ u32 shift, bit_per_gpio, activate, deactivate, gpio_count;
+ const u8 *defaults;
- hcg->regs = (uint32_t *)devfdt_get_addr_ptr(dev);
-
- uc_priv->gpio_count = dev_read_u32_default(dev, "gpio-count", 1);
- if (uc_priv->gpio_count > HSDK_CREG_MAX_GPIO)
- uc_priv->gpio_count = HSDK_CREG_MAX_GPIO;
+ hcg->regs = (u32 *)devfdt_get_addr_ptr(dev);
+ gpio_count = dev_read_u32_default(dev, "gpio-count
[U-Boot] [PATCH v2] ARC: HSDK: add tool and make target to generate bsp
HSDK board has preloader that reads SPI flash pages and searches
special image header to fetch and load binary.
Add tool, make target (bsp-generate) to generate
update script and u-boot binary image with header for preloader.
Also add script to default environment to apply updates.
Signed-off-by: Eugeniy Paltsev
---
Changes v1->v2:
* Comments change
board/synopsys/hsdk/config.mk | 11 +++
board/synopsys/hsdk/headerize-hsdk.py | 149 ++
include/configs/hsdk.h| 6 ++
3 files changed, 166 insertions(+)
create mode 100644 board/synopsys/hsdk/config.mk
create mode 100644 board/synopsys/hsdk/headerize-hsdk.py
diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk`
new file mode 100644
index 00..7a0ed3ca36
--- /dev/null
+++ b/board/synopsys/hsdk/config.mk
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+
+bsp-generate: u-boot u-boot.bin
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
+ --arc-id 0x52 --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+ $(Q)mkimage -T script -C none -n 'uboot update script' \
+ -d $(srctree)/u-boot-update.txt \
+ $(srctree)/u-boot-update.img &> /dev/null
diff --git a/board/synopsys/hsdk/headerize-hsdk.py
b/board/synopsys/hsdk/headerize-hsdk.py
new file mode 100644
index 00..fce749723e
--- /dev/null
+++ b/board/synopsys/hsdk/headerize-hsdk.py
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+# Author: Eugeniy Paltsev
+
+import os, getopt, sys, zlib
+from elftools.elf.elffile import ELFFile
+
+
+def usage(exit_code):
+print("usage:")
+print(sys.argv[0] + " --arc-id 0x52 --image u-boot.bin --elf u-boot")
+sys.exit(exit_code)
+
+
+def elf_get_entry(filename):
+with open(filename, 'rb') as f:
+elffile = ELFFile(f)
+return elffile.header['e_entry']
+
+
+def calc_check_sum(filename):
+# u-boot.head check_sum for preloader - it is sum of all u-boot binary
bytes
+with open(filename, "rb") as file:
+ba = bytearray(file.read())
+return sum(ba) & 0xFF
+
+
+def arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id):
+if arc_id not in [0x52, 0x53]:
+print("unknown ARC ID: " + hex(arc_id))
+sys.exit(2)
+
+if not os.path.isfile(uboot_bin_filename):
+print("uboot bin file not exists: " + uboot_bin_filename)
+sys.exit(2)
+
+if not os.path.isfile(uboot_elf_filename):
+print("uboot elf file not exists: " + uboot_elf_filename)
+sys.exit(2)
+
+
+def main():
+try:
+opts, args = getopt.getopt(sys.argv[1:],
+"ha:i:l:e:", ["help", "arc-id=", "image=", "elf="])
+except getopt.GetoptError as err:
+print(err)
+usage(2)
+
+# default filenames
+uboot_elf_filename = "u-boot"
+uboot_bin_filename = "u-boot.bin"
+headerised_filename = "u-boot.head"
+uboot_scrypt_file = "u-boot-update.txt"
+
+# initial header values: place where preloader will store u-boot binary,
+# should be equal to CONFIG_SYS_TEXT_BASE
+image_copy_adr = 0x8100
+
+# initial constant header values, do not change these values
+arc_id = 0x52 # 0x52 for 1st HSDK release (hardcoded in
RTL)
+magic1 = 0xdeadbeafaf # big endian byte order
+flash_address = 0x0
+flash_type = 0x0 # 0 - SPI flash, 1 - NOR flash
+magic2 = [# big endian byte order
+0x20202a2020202020202020202a20202020207c5c2e20202020202e2f7c20202020207c2d,
+0x2e5c2020202f2e2d7c20202020205c2020602d2d2d6020202f20202020202f205f202020,
+0x205f20205c20202020207c205f60712070205f207c2020202020272e5f3d2f205c3d5f2e,
+0x272020202020202020605c202f60202020202020202020202020206f2020202020202020]
+
+for opt, arg in opts:
+if opt in ('-h', "--help"): usage(0)
+if opt in ('-a', "--arc-id"): arc_id = int(arg, 16)
+if opt in ('-i', "--image"): uboot_bin_filename = arg
+if opt in ('-e', "--elf"):uboot_elf_filename = arg
+
+arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id)
+
+uboot_img_size = os.path.getsize(uboot_bin_filename)
+jump_address = elf_get_entry(uboot_elf_filename)
+check_sum = calc_check_sum(uboot_bin_filename)
+
+# write header to file
+with open(headerised_filename, "wb") as file:
+file.write(arc_id.to_bytes(2, byteorder='little'))
+file.write(uboot_img_size.to_bytes(4, byteorder='little'))
+file.write(check_sum.to_bytes(1, byteorder='little'))
+
[U-Boot] [PATCH] ARC: HSDK: add tool and make target to generate bsp
HSDK board has preloader that reads SPI flash pages and searches
special image header to fetch and load binary.
Add tool, make target (bsp-generate) to generate
update script and u-boot binary image with header for preloader.
Also add script to default environment to apply updates.
Signed-off-by: Eugeniy Paltsev
---
board/synopsys/hsdk/config.mk | 11 +++
board/synopsys/hsdk/headerize-hsdk.py | 147 ++
include/configs/hsdk.h| 6 ++
3 files changed, 164 insertions(+)
create mode 100644 board/synopsys/hsdk/config.mk
create mode 100644 board/synopsys/hsdk/headerize-hsdk.py
diff --git a/board/synopsys/hsdk/config.mk b/board/synopsys/hsdk/config.mk
new file mode 100644
index 00..7a0ed3ca36
--- /dev/null
+++ b/board/synopsys/hsdk/config.mk
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+
+bsp-generate: u-boot u-boot.bin
+ $(Q)python3 $(srctree)/board/$(BOARDDIR)/headerize-hsdk.py \
+ --arc-id 0x52 --image $(srctree)/u-boot.bin \
+ --elf $(srctree)/u-boot
+ $(Q)mkimage -T script -C none -n 'uboot update script' \
+ -d $(srctree)/u-boot-update.txt \
+ $(srctree)/u-boot-update.img &> /dev/null
diff --git a/board/synopsys/hsdk/headerize-hsdk.py
b/board/synopsys/hsdk/headerize-hsdk.py
new file mode 100644
index 00..97510474c4
--- /dev/null
+++ b/board/synopsys/hsdk/headerize-hsdk.py
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Synopsys, Inc. All rights reserved.
+# Author: Eugeniy Paltsev
+
+import os, getopt, sys, zlib
+from elftools.elf.elffile import ELFFile
+
+
+def usage(exit_code):
+print("usage:")
+print(sys.argv[0] + " --arc-id 0x52 --image u-boot.bin --elf u-boot")
+sys.exit(exit_code)
+
+
+def elf_get_entry(filename):
+with open(filename, 'rb') as f:
+elffile = ELFFile(f)
+return elffile.header['e_entry']
+
+
+def calc_check_sum(filename):
+# u-boot.head check_sum for preloader - it is sum of all u-boot binary
bytes
+with open(filename, "rb") as file:
+ba = bytearray(file.read())
+return sum(ba) & 0xFF
+
+
+def arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id):
+if arc_id not in [0x52, 0x53]:
+print("unknown ARC ID: " + hex(arc_id))
+sys.exit(2)
+
+if not os.path.isfile(uboot_bin_filename):
+print("uboot bin file not exists: " + uboot_bin_filename)
+sys.exit(2)
+
+if not os.path.isfile(uboot_elf_filename):
+print("uboot elf file not exists: " + uboot_elf_filename)
+sys.exit(2)
+
+
+def main():
+try:
+opts, args = getopt.getopt(sys.argv[1:],
+"ha:i:l:e:", ["help", "arc-id=", "image=", "elf="])
+except getopt.GetoptError as err:
+print(err)
+usage(2)
+
+# default filenames
+uboot_elf_filename = "u-boot"
+uboot_bin_filename = "u-boot.bin"
+headerised_filename = "u-boot.head"
+uboot_scrypt_file = "u-boot-update.txt"
+
+# initial header values
+arc_id = 0x52 # 0x52 for first HSDK release
+image_copy_adr = 0x8100 # place where preloader will store u-boot
binary
+# initial constant header values, do not change these values
+magic1 = 0xdeadbeafaf # big endian byte order
+flash_address = 0x0
+flash_type = 0x0 # 0 - SPI flash, 1 - NOR flash
+magic2 = [# big endian byte order
+0x20202a2020202020202020202a20202020207c5c2e20202020202e2f7c20202020207c2d,
+0x2e5c2020202f2e2d7c20202020205c2020602d2d2d6020202f20202020202f205f202020,
+0x205f20205c20202020207c205f60712070205f207c2020202020272e5f3d2f205c3d5f2e,
+0x272020202020202020605c202f60202020202020202020202020206f2020202020202020]
+
+for opt, arg in opts:
+if opt in ('-h', "--help"): usage(0)
+if opt in ('-a', "--arc-id"): arc_id = int(arg, 16)
+if opt in ('-i', "--image"): uboot_bin_filename = arg
+if opt in ('-e', "--elf"):uboot_elf_filename = arg
+
+arg_verify(uboot_bin_filename, uboot_elf_filename, arc_id)
+
+uboot_img_size = os.path.getsize(uboot_bin_filename)
+jump_address = elf_get_entry(uboot_elf_filename)
+check_sum = calc_check_sum(uboot_bin_filename)
+
+# write header to file
+with open(headerised_filename, "wb") as file:
+file.write(arc_id.to_bytes(2, byteorder='little'))
+file.write(uboot_img_size.to_bytes(4, byteorder='little'))
+file.write(check_sum.to_bytes(1, byteorder='little'))
+file.write(image_copy_adr.to_bytes(4, byteorder='little'))
+file.write(magic1.to_bytes(5, byte
[U-Boot] [PATCH 2/2] ARC: enable debug uart for HSDK and AXS10x boards
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> --- configs/axs101_defconfig | 5 + configs/axs103_defconfig | 5 + configs/hsdk_defconfig | 5 + 3 files changed, 15 insertions(+) diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 25b10888ced..559ed4734c1 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -3,6 +3,7 @@ CONFIG_TARGET_AXS101=y CONFIG_SYS_TEXT_BASE=0x8100 CONFIG_SYS_CLK_FREQ=75000 CONFIG_DEFAULT_DEVICE_TREE="axs101" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" @@ -33,6 +34,10 @@ CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_BASE=0xe0022000 +CONFIG_DEBUG_UART_CLOCK= +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index b9d387b88a8..8b66451307d 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -3,6 +3,7 @@ CONFIG_ISA_ARCV2=y CONFIG_SYS_TEXT_BASE=0x8100 CONFIG_SYS_CLK_FREQ=1 CONFIG_DEFAULT_DEVICE_TREE="axs103" +CONFIG_DEBUG_UART=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" @@ -33,6 +34,10 @@ CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_ETH_DESIGNWARE=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_BASE=0xe0022000 +CONFIG_DEBUG_UART_CLOCK= +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index d23acfeb878..28cd1dd70c4 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -4,6 +4,7 @@ CONFIG_TARGET_HSDK=y CONFIG_SYS_TEXT_BASE=0x8100 CONFIG_SYS_CLK_FREQ=5 CONFIG_DEFAULT_DEVICE_TREE="hsdk" +CONFIG_DEBUG_UART=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" CONFIG_BOARD_EARLY_INIT_F=y @@ -42,6 +43,10 @@ CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_BASE=0xf0005000 +CONFIG_DEBUG_UART_CLOCK= +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/2] ARC: enable debug uart for HSDK and AXS10x boards
Eugeniy Paltsev (2): ARC: init debug uart in early common arc code ARC: enable debug uart for HSDK and AXS10x boards arch/arc/lib/start.S | 5 + configs/axs101_defconfig | 5 + configs/axs103_defconfig | 5 + configs/hsdk_defconfig | 5 + 4 files changed, 20 insertions(+) -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/2] ARC: init debug uart in early common arc code
The debug UART is intended for use very early in U-Boot to debug problems before serial drivers are up. Call debug_uart_init right before board_init_f. Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> --- arch/arc/lib/start.S | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index c78dd001d81..cb8ea0fd363 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -76,6 +76,11 @@ ENTRY(_start) /* Initialize reserved area - note: r0 already contains address */ bl board_init_f_init_reserve +#ifdef CONFIG_DEBUG_UART + /* Earliest point to set up early debug uart */ + bl debug_uart_init +#endif + /* Zero the one and only argument of "board_init_f" */ mov_s %r0, 0 bl board_init_f -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] DW SPI: invert wait condition in dw_spi_xfer
While switching to readl_poll_timeout macros from custom code
the waiting condition was accidently inverted, so it was pure
luck that this code works at least in some conditions.
Fix that by inverting exit condition for readl_poll_timeout.
Fixes: c6b4f031d9 ("DW SPI: fix tx data loss on FIFO flush")
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
drivers/spi/designware_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 0e93b62eee..5e2d290ddc 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -425,7 +425,7 @@ static int dw_spi_xfer(struct udevice *dev, unsigned int
bitlen,
* in the beginning of new transfer.
*/
if (readl_poll_timeout(priv->regs + DW_SPI_SR, val,
- !(val & SR_TF_EMPT) || (val & SR_BUSY),
+ (val & SR_TF_EMPT) && !(val & SR_BUSY),
RX_TIMEOUT * 1000)) {
ret = -ETIMEDOUT;
}
--
2.14.3
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[U-Boot] [PATCH] ARC: remove unused DECLARE_GLOBAL_DATA_PTR from init_helpers.c
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
arch/arc/lib/init_helpers.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arc/lib/init_helpers.c b/arch/arc/lib/init_helpers.c
index 435fe96ef4..822318ff43 100644
--- a/arch/arc/lib/init_helpers.c
+++ b/arch/arc/lib/init_helpers.c
@@ -7,8 +7,6 @@
#include
#include
-DECLARE_GLOBAL_DATA_PTR;
-
int init_cache_f_r(void)
{
sync_n_cleanup_cache_all();
--
2.14.3
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[U-Boot] [PATCH] ARC: update ARC architecture maintainers
Update ARC architecture maintainers and add uboot-snps-...@synopsys.com mailing list. Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 44eeefa635..9f653a0137 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -55,7 +55,9 @@ Maintainers List (try to look for most precise areas first) --- ARC M: Alexey Brodkin <alexey.brod...@synopsys.com> +M: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> S: Maintained +L: uboot-snps-...@synopsys.com T: git git://git.denx.de/u-boot-arc.git F: arch/arc/ -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARC: AXS10x: enable hush shell
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> --- configs/axs101_defconfig | 1 + configs/axs103_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig index 174b80aeed..25b10888ce 100644 --- a/configs/axs101_defconfig +++ b/configs/axs101_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig index 9530061568..b9d387b88a 100644 --- a/configs/axs103_defconfig +++ b/configs/axs103_defconfig @@ -7,6 +7,7 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS3,115200n8" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="AXS# " # CONFIG_CMD_FLASH is not set CONFIG_CMD_MMC=y -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] ARC: HSDK: fix cpu frequency value
CPU on HSDK board runs at 500MHz after preloader so fix wrong cpu orequency value in hsdk_defconfig in hsdk. Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> --- configs/hsdk_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig index 37f61902d3..844decad2d 100644 --- a/configs/hsdk_defconfig +++ b/configs/hsdk_defconfig @@ -2,7 +2,7 @@ CONFIG_ARC=y CONFIG_ISA_ARCV2=y CONFIG_TARGET_HSDK=y CONFIG_SYS_TEXT_BASE=0x8100 -CONFIG_SYS_CLK_FREQ=10 +CONFIG_SYS_CLK_FREQ=5 CONFIG_DEFAULT_DEVICE_TREE="hsdk" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/2] SPI Flash: add support of sst26wf* flash ICs protection ops
Hi Jagan! Any comments? On Tue, 2018-04-10 at 14:40 +0300, Eugeniy Paltsev wrote: > sst26wf flash series block protection implementation differs > from other SST series, so add specific implementation > flash_lock/flash_unlock/flash_is_locked functions for sst26wf > flash ICs. > > Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com> > --- > Changes v4->v5: > * Return EACCES when flash is locked instead of custom define (SF_LOCKED) > * Add SST26_CTL_* prefix to sst27 lock ops enum. > * Move all sst26 code inside of existing CONFIG_SPI_FLASH_SST #ifdef. > > Changes v3->v4: > * Make sst26_process_bpr() and sst26_lock_ctl() functions static. > > Changes v2->v3: > * Move SST26 command defenition to sf_internal.h > * Merge sst26_set_bpr, sst26_clear_bpr and sst26_check_bpr functions >into single sst26_process_bpr function. > * Use SF_UNLOCKED/SF_LOCKED instead of magic numbers in >sst26_lock_ctl() > > Changes v1->v2: > * Use generic defines from linux/sizes.h instead of custom ones. > > diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c [snip] -- Eugeniy Paltsev ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v5 1/2] SPI Flash: add support of sst26wf* flash ICs protection ops
Hi Jagan,
Maybe you have any comments or remarks about this patch? And if you don't could
you please apply it.
Thanks!
On Tue, 2018-04-10 at 14:40 +0300, Eugeniy Paltsev wrote:
> sst26wf flash series block protection implementation differs
> from other SST series, so add specific implementation
> flash_lock/flash_unlock/flash_is_locked functions for sst26wf
> flash ICs.
>
> Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
> ---
> Changes v4->v5:
> * Return EACCES when flash is locked instead of custom define (SF_LOCKED)
> * Add SST26_CTL_* prefix to sst27 lock ops enum.
> * Move all sst26 code inside of existing CONFIG_SPI_FLASH_SST #ifdef.
>
> Changes v3->v4:
> * Make sst26_process_bpr() and sst26_lock_ctl() functions static.
>
> Changes v2->v3:
> * Move SST26 command defenition to sf_internal.h
> * Merge sst26_set_bpr, sst26_clear_bpr and sst26_check_bpr functions
>into single sst26_process_bpr function.
> * Use SF_UNLOCKED/SF_LOCKED instead of magic numbers in
>sst26_lock_ctl()
>
> Changes v1->v2:
> * Use generic defines from linux/sizes.h instead of custom ones.
>
> drivers/mtd/spi/sf_internal.h | 13
> drivers/mtd/spi/spi_flash.c | 168
> ++
> 2 files changed, 181 insertions(+)
>
> diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
> index 839cdbe1b0..614a293234 100644
> --- a/drivers/mtd/spi/sf_internal.h
> +++ b/drivers/mtd/spi/sf_internal.h
> @@ -87,6 +87,19 @@ enum spi_nor_option_flags {
>
> /* SST specific */
> #ifdef CONFIG_SPI_FLASH_SST
> +#define SST26_CMD_READ_BPR 0x72
> +#define SST26_CMD_WRITE_BPR 0x42
> +
> +#define SST26_BPR_8K_NUM 4
> +#define SST26_MAX_BPR_REG_LEN(18 + 1)
> +#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
> +
> +enum lock_ctl {
> + SST26_CTL_LOCK,
> + SST26_CTL_UNLOCK,
> + SST26_CTL_CHECK
> +};
> +
> # define CMD_SST_BP 0x02/* Byte Program */
> # define CMD_SST_AAI_WP 0xAD/* Auto Address Incr Word
> Program */
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 2e61685d3e..5e5bd5d533 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -16,6 +16,7 @@
> #include
> #include
> #include
> +#include
> #include
>
> #include "sf_internal.h"
> @@ -541,6 +542,164 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
> offset,
> }
>
> #ifdef CONFIG_SPI_FLASH_SST
> +static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl
> ctl)
> +{
> + switch (ctl) {
> + case SST26_CTL_LOCK:
> + cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
> + break;
> + case SST26_CTL_UNLOCK:
> + cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
> + break;
> + case SST26_CTL_CHECK:
> + return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
> + }
> +
> + return false;
> +}
> +
> +/*
> + * sst26wf016/sst26wf032/sst26wf064 have next block protection:
> + * 4x - 8 KByte blocks - read & write protection bits - upper addresses
> + * 1x - 32 KByte blocks - write protection bits
> + * rest - 64 KByte blocks - write protection bits
> + * 1x - 32 KByte blocks - write protection bits
> + * 4x - 8 KByte blocks - read & write protection bits - lower addresses
> + *
> + * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
> + * will be treated as single block.
> + */
> +
> +/*
> + * Lock, unlock or check lock status of the flash region of the flash
> (depending
> + * on the lock_ctl value)
> + */
> +static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum
> lock_ctl ctl)
> +{
> + u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
> + bool lower_64k = false, upper_64k = false;
> + u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
> + int ret;
> +
> + /* Check length and offset for 64k alignment */
> + if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
> + return -EINVAL;
> +
> + if (ofs + len > flash->size)
> + return -EINVAL;
> +
> + /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
> + if (flash->size != SZ_2M &&
> + flash->size != SZ_4M &&
> + flash->size != SZ_8M)
> + return -EINVAL;
> +
> + bpr_size = 2 + (flash->size
[U-Boot] [PATCH v5 2/2] SF: add support for sst26wf016, sst26wf032, sst26wf064
This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v4->v5:
* None.
Changes v3->v4:
* None.
Changes v2->v3:
* None.
Changes v1->v2:
* None.
drivers/mtd/spi/spi_flash_ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index b789219e4e..dbb4ac4d32 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -151,6 +151,9 @@ const struct spi_flash_info spi_flash_ids[] = {
{"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K |
SST_WR) },
{"sst25wf040b",INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) },
{"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024,16, SECT_4K |
SST_WR) },
+ {"sst26wf016", INFO(0xbf2651, 0x0, 64 * 1024,32, SECT_4K) },
+ {"sst26wf032", INFO(0xbf2622, 0x0, 64 * 1024,64, SECT_4K) },
+ {"sst26wf064", INFO(0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND/* WINBOND */
{"w25p80", INFO(0xef2014, 0x0, 64 * 1024,16, 0) },
--
2.14.3
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[U-Boot] [PATCH v5 1/2] SPI Flash: add support of sst26wf* flash ICs protection ops
sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v4->v5:
* Return EACCES when flash is locked instead of custom define (SF_LOCKED)
* Add SST26_CTL_* prefix to sst27 lock ops enum.
* Move all sst26 code inside of existing CONFIG_SPI_FLASH_SST #ifdef.
Changes v3->v4:
* Make sst26_process_bpr() and sst26_lock_ctl() functions static.
Changes v2->v3:
* Move SST26 command defenition to sf_internal.h
* Merge sst26_set_bpr, sst26_clear_bpr and sst26_check_bpr functions
into single sst26_process_bpr function.
* Use SF_UNLOCKED/SF_LOCKED instead of magic numbers in
sst26_lock_ctl()
Changes v1->v2:
* Use generic defines from linux/sizes.h instead of custom ones.
drivers/mtd/spi/sf_internal.h | 13
drivers/mtd/spi/spi_flash.c | 168 ++
2 files changed, 181 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 839cdbe1b0..614a293234 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -87,6 +87,19 @@ enum spi_nor_option_flags {
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
+#define SST26_CMD_READ_BPR 0x72
+#define SST26_CMD_WRITE_BPR0x42
+
+#define SST26_BPR_8K_NUM 4
+#define SST26_MAX_BPR_REG_LEN (18 + 1)
+#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
+
+enum lock_ctl {
+ SST26_CTL_LOCK,
+ SST26_CTL_UNLOCK,
+ SST26_CTL_CHECK
+};
+
# define CMD_SST_BP0x02/* Byte Program */
# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word
Program */
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 2e61685d3e..5e5bd5d533 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include "sf_internal.h"
@@ -541,6 +542,164 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
}
#ifdef CONFIG_SPI_FLASH_SST
+static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl
ctl)
+{
+ switch (ctl) {
+ case SST26_CTL_LOCK:
+ cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
+ break;
+ case SST26_CTL_UNLOCK:
+ cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
+ break;
+ case SST26_CTL_CHECK:
+ return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
+ }
+
+ return false;
+}
+
+/*
+ * sst26wf016/sst26wf032/sst26wf064 have next block protection:
+ * 4x - 8 KByte blocks - read & write protection bits - upper addresses
+ * 1x - 32 KByte blocks - write protection bits
+ * rest - 64 KByte blocks - write protection bits
+ * 1x - 32 KByte blocks - write protection bits
+ * 4x - 8 KByte blocks - read & write protection bits - lower addresses
+ *
+ * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
+ * will be treated as single block.
+ */
+
+/*
+ * Lock, unlock or check lock status of the flash region of the flash
(depending
+ * on the lock_ctl value)
+ */
+static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum
lock_ctl ctl)
+{
+ u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
+ bool lower_64k = false, upper_64k = false;
+ u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
+ int ret;
+
+ /* Check length and offset for 64k alignment */
+ if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
+ return -EINVAL;
+
+ if (ofs + len > flash->size)
+ return -EINVAL;
+
+ /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
+ if (flash->size != SZ_2M &&
+ flash->size != SZ_4M &&
+ flash->size != SZ_8M)
+ return -EINVAL;
+
+ bpr_size = 2 + (flash->size / SZ_64K / 8);
+
+ cmd = SST26_CMD_READ_BPR;
+ ret = spi_flash_read_common(flash, , 1, bpr_buff, bpr_size);
+ if (ret < 0) {
+ printf("SF: fail to read block-protection register\n");
+ return ret;
+ }
+
+ rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
+ lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
+
+ upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
+ lower_64k = (ofs < SST26_BOUND_REG_SIZE);
+
+ /* Lower bits in block-protection register are about 64k region */
+ bpr_ptr = lptr_64k / SZ_64K - 1;
+
+ /* Process 64K blocks region */
+ while (lptr_64k < rptr_64k) {
+ if (sst
[U-Boot] [PATCH v5 0/2] SF: add support for sst26wf016, sst26wf032, sst26wf064
Add support for the SST sst26wf016, sst26wf032 and sst26wf064 flash IC: sst26wf*** flash series block protection implementation differs from other SST series, so we add implementation for sst26wf*** lock/unlock/is_locked functions. Add sst26wf016, sst26wf032 and sst26wf064 flash IC info to spi_flash_ids list. Changes v4->v5: * Return EACCES when flash is locked instead of custom define (SF_LOCKED) * Add SST26_CTL_* prefix to sst27 lock ops enum. * Move all sst26 code inside of existing CONFIG_SPI_FLASH_SST #ifdef. Changes v3->v4: * Make sst26_process_bpr() and sst26_lock_ctl() functions static. Changes v2->v3: * Move SST26 command defenition to sf_internal.h * Merge sst26_set_bpr, sst26_clear_bpr and sst26_check_bpr functions into single sst26_process_bpr function. * Use SF_UNLOCKED/SF_LOCKED instead of magic numbers in sst26_lock_ctl() Changes v1->v2: * Use generic defines from linux/sizes.h instead of custom ones. Eugeniy Paltsev (2): SPI Flash: add support of sst26wf* flash ICs protection ops SF: add support for sst26wf016, sst26wf032, sst26wf064 drivers/mtd/spi/sf_internal.h | 18 + drivers/mtd/spi/spi_flash.c | 165 drivers/mtd/spi/spi_flash_ids.c | 3 + 3 files changed, 186 insertions(+) -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/2] SPI Flash: add support of sst26wf* flash ICs protection ops
Hi Jagan,
On Mon, 2018-04-09 at 16:52 +0530, Jagan Teki wrote:
> On Mon, Apr 9, 2018 at 4:27 PM, Eugeniy Paltsev
> <eugeniy.palt...@synopsys.com> wrote:
> > sst26wf flash series block protection implementation differs
> > from other SST series, so add specific implementation
> > flash_lock/flash_unlock/flash_is_locked functions for sst26wf
> > flash ICs.
> >
> > +enum flash_lock_status {
> > + SF_UNLOCKED = 0,
> > + SF_LOCKED = 1,
> > +};
>
> Try to use existing relevant error codes.
Hmm, I can return something like EACCES (positive value) if flash is locked. Is
it OK?
> > +
> > #define SPI_FLASH_3B_ADDR_LEN 3
> > +enum lock_ctl {
> > + CTL_LOCK,
> > + CTL_UNLOCK,
> > + CTL_CHECK
> > +};
>
> SST26_CTL_* ?
OK.
> >
> > +#if defined(CONFIG_SPI_FLASH_SST)
>
> Please move this code inside of existing #ifdef of SST (commented same
> in previous version)
OK.
[snip]
> >
> > #ifdef CONFIG_SPI_FLASH_MACRONIX
> > static int macronix_quad_enable(struct spi_flash *flash)
> > @@ -1033,6 +1189,15 @@ int spi_flash_scan(struct spi_flash *flash)
> > }
> > #endif
> >
> > +/* sst26wf series block protection implementation differs from other
> > series */
> > +#if defined(CONFIG_SPI_FLASH_SST)
> > + if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST && info->id[1] ==
> > 0x26) {
> > + flash->flash_lock = sst26_lock;
> > + flash->flash_unlock = sst26_unlock;
> > + flash->flash_is_locked = sst26_is_locked;
> > + }
> > +#endif
>
> Previous version comment need to fix here? (about switch case with
> existing lock ops)?
I guess switch case isn't suitable here:
we need check several parameters (JEDEC_MFR and Device Type) and we need to
check
CONFIG_SPI_FLASH_*** ifdefs.
Also we have only two lock ops: "stm_*" and "sst26_*" (which I add by this
patch).
So I guess using switch here is unnecessarily.
> Jagan.
--
Eugeniy Paltsev
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[U-Boot] [PATCH v4 1/2] SPI Flash: add support of sst26wf* flash ICs protection ops
sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v3->v4:
* Make sst26_process_bpr() and sst26_lock_ctl() functions static.
Changes v2->v3:
* Move SST26 command defenition to sf_internal.h
* Merge sst26_set_bpr, sst26_clear_bpr and sst26_check_bpr functions
into single sst26_process_bpr function.
* Use SF_UNLOCKED/SF_LOCKED instead of magic numbers in
sst26_lock_ctl()
Changes v1->v2:
* Use generic defines from linux/sizes.h instead of custom ones.
drivers/mtd/spi/sf_internal.h | 18 +
drivers/mtd/spi/spi_flash.c | 165 ++
2 files changed, 183 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 839cdbe1b0..a17dcc4de1 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -26,6 +26,11 @@ enum spi_nor_option_flags {
SNOR_F_USE_UPAGE= BIT(3),
};
+enum flash_lock_status {
+ SF_UNLOCKED = 0,
+ SF_LOCKED = 1,
+};
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
@@ -87,6 +92,19 @@ enum spi_nor_option_flags {
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
+#define SST26_CMD_READ_BPR 0x72
+#define SST26_CMD_WRITE_BPR0x42
+
+#define SST26_BPR_8K_NUM 4
+#define SST26_MAX_BPR_REG_LEN (18 + 1)
+#define SST26_BOUND_REG_SIZE ((32 + SST26_BPR_8K_NUM * 8) * SZ_1K)
+
+enum lock_ctl {
+ CTL_LOCK,
+ CTL_UNLOCK,
+ CTL_CHECK
+};
+
# define CMD_SST_BP0x02/* Byte Program */
# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word
Program */
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 2e61685d3e..0f4e7fd5d4 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include "sf_internal.h"
@@ -842,6 +843,161 @@ int stm_unlock(struct spi_flash *flash, u32 ofs, size_t
len)
}
#endif
+#if defined(CONFIG_SPI_FLASH_SST)
+static bool sst26_process_bpr(u32 bpr_size, u8 *cmd, u32 bit, enum lock_ctl
ctl)
+{
+ switch (ctl) {
+ case CTL_LOCK:
+ cmd[bpr_size - (bit / 8) - 1] |= BIT(bit % 8);
+ break;
+ case CTL_UNLOCK:
+ cmd[bpr_size - (bit / 8) - 1] &= ~BIT(bit % 8);
+ break;
+ case CTL_CHECK:
+ return !!(cmd[bpr_size - (bit / 8) - 1] & BIT(bit % 8));
+ }
+
+ return false;
+}
+
+/*
+ * sst26wf016/sst26wf032/sst26wf064 have next block protection:
+ * 4x - 8 KByte blocks - read & write protection bits - upper addresses
+ * 1x - 32 KByte blocks - write protection bits
+ * rest - 64 KByte blocks - write protection bits
+ * 1x - 32 KByte blocks - write protection bits
+ * 4x - 8 KByte blocks - read & write protection bits - lower addresses
+ *
+ * We'll support only per 64k lock/unlock so lower and upper 64 KByte region
+ * will be treated as single block.
+ */
+
+/*
+ * Lock, unlock or check lock status of the flash region of the flash
(depending
+ * on the lock_ctl value)
+ */
+static int sst26_lock_ctl(struct spi_flash *flash, u32 ofs, size_t len, enum
lock_ctl ctl)
+{
+ u32 i, bpr_ptr, rptr_64k, lptr_64k, bpr_size;
+ bool lower_64k = false, upper_64k = false;
+ u8 cmd, bpr_buff[SST26_MAX_BPR_REG_LEN] = {};
+ int ret;
+
+ /* Check length and offset for 64k alignment */
+ if ((ofs & (SZ_64K - 1)) || (len & (SZ_64K - 1)))
+ return -EINVAL;
+
+ if (ofs + len > flash->size)
+ return -EINVAL;
+
+ /* SST26 family has only 16 Mbit, 32 Mbit and 64 Mbit IC */
+ if (flash->size != SZ_2M &&
+ flash->size != SZ_4M &&
+ flash->size != SZ_8M)
+ return -EINVAL;
+
+ bpr_size = 2 + (flash->size / SZ_64K / 8);
+
+ cmd = SST26_CMD_READ_BPR;
+ ret = spi_flash_read_common(flash, , 1, bpr_buff, bpr_size);
+ if (ret < 0) {
+ printf("SF: fail to read block-protection register\n");
+ return ret;
+ }
+
+ rptr_64k = min_t(u32, ofs + len , flash->size - SST26_BOUND_REG_SIZE);
+ lptr_64k = max_t(u32, ofs, SST26_BOUND_REG_SIZE);
+
+ upper_64k = ((ofs + len) > (flash->size - SST26_BOUND_REG_SIZE));
+ lower_64k = (ofs < SST26_BOUND_REG_SIZE);
+
+ /* Lower bits in block-protection register are about 64k region */
+ b
[U-Boot] [PATCH v4 2/2] SF: add support for sst26wf016, sst26wf032, sst26wf064
This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.
Signed-off-by: Eugeniy Paltsev <eugeniy.palt...@synopsys.com>
---
Changes v3->v4:
* None.
Changes v2->v3:
* None.
Changes v1->v2:
* None.
drivers/mtd/spi/spi_flash_ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index b789219e4e..dbb4ac4d32 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -151,6 +151,9 @@ const struct spi_flash_info spi_flash_ids[] = {
{"sst25wf040", INFO(0xbf2504, 0x0, 64 * 1024, 8, SECT_4K |
SST_WR) },
{"sst25wf040b",INFO(0x621613, 0x0, 64 * 1024, 8, SECT_4K) },
{"sst25wf080", INFO(0xbf2505, 0x0, 64 * 1024,16, SECT_4K |
SST_WR) },
+ {"sst26wf016", INFO(0xbf2651, 0x0, 64 * 1024,32, SECT_4K) },
+ {"sst26wf032", INFO(0xbf2622, 0x0, 64 * 1024,64, SECT_4K) },
+ {"sst26wf064", INFO(0xbf2643, 0x0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND/* WINBOND */
{"w25p80", INFO(0xef2014, 0x0, 64 * 1024,16, 0) },
--
2.14.3
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[U-Boot] [PATCH v4 0/2] SF: add support for sst26wf016, sst26wf032, sst26wf064
Add support for the SST sst26wf016, sst26wf032 and sst26wf064 flash IC: sst26wf*** flash series block protection implementation differs from other SST series, so we add implementation for sst26wf*** lock/unlock/is_locked functions. Add sst26wf016, sst26wf032 and sst26wf064 flash IC info to spi_flash_ids list. Changes v3->v4: * Make sst26_process_bpr() and sst26_lock_ctl() functions static. Changes v2->v3: * Move SST26 command defenition to sf_internal.h * Merge sst26_set_bpr, sst26_clear_bpr and sst26_check_bpr functions into single sst26_process_bpr function. * Use SF_UNLOCKED/SF_LOCKED instead of magic numbers in sst26_lock_ctl() Changes v1->v2: * Use generic defines from linux/sizes.h instead of custom ones. Eugeniy Paltsev (2): SPI Flash: add support of sst26wf* flash ICs protection ops SF: add support for sst26wf016, sst26wf032, sst26wf064 drivers/mtd/spi/sf_internal.h | 18 + drivers/mtd/spi/spi_flash.c | 165 drivers/mtd/spi/spi_flash_ids.c | 3 + 3 files changed, 186 insertions(+) -- 2.14.3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
