[U-Boot] [PATCH v2 2/2] Remove #define BIT in local files.
Since BIT macro is visiable to include/common.h there is no
need to define again it on local headers hence removed.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
Changes for v2:
- none
arch/arm/include/asm/arch-am33xx/cpu.h | 1 -
arch/arm/include/asm/arch-omap5/cpu.h| 2 --
arch/arm/include/asm/arch-tegra20/dc.h | 2 --
arch/arm/mach-davinci/cpu.c | 2 --
arch/arm/mach-keystone/include/mach/clock_defs.h | 2 --
arch/arm/mvebu-common/mbus.c | 2 --
board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | 2 --
drivers/mtd/nand/jz4740_nand.c | 1 -
drivers/net/mvneta.c | 1 -
drivers/spi/andes_spi.h | 2 --
drivers/spi/davinci_spi.h| 2 --
drivers/spi/ep93xx_spi.c | 2 --
include/fsl-mc/fsl_mc.h | 1 -
13 files changed, 22 deletions(-)
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h
b/arch/arm/include/asm/arch-am33xx/cpu.h
index 13a9cad..112ac5e 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -17,7 +17,6 @@
#include asm/arch/hardware.h
-#define BIT(x) (1 x)
#define CL_BIT(x) (0 x)
/* Timer register bits */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h
b/arch/arm/include/asm/arch-omap5/cpu.h
index 6109b92..b1513e9 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -56,8 +56,6 @@ struct watchdog {
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL_STRICT_NAMES */
-#define BIT(x) (1 (x))
-
#define WD_UNLOCK1 0x
#define WD_UNLOCK2 0x
diff --git a/arch/arm/include/asm/arch-tegra20/dc.h
b/arch/arm/include/asm/arch-tegra20/dc.h
index 20790b6..cdacdfb 100644
--- a/arch/arm/include/asm/arch-tegra20/dc.h
+++ b/arch/arm/include/asm/arch-tegra20/dc.h
@@ -351,8 +351,6 @@ struct dc_ctlr {
struct dc_winbuf_reg winbuf;/* WINBUF A/B/C 0x800 ~ 0x80a */
};
-#define BIT(pos) (1U pos)
-
/* DC_CMD_DISPLAY_COMMAND 0x032 */
#define CTRL_MODE_SHIFT5
#define CTRL_MODE_MASK (0x3 CTRL_MODE_SHIFT)
diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index ff61147..74c3d5d 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -28,8 +28,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
-#define BIT(x) (1 (x))
-
/* SOC-specific pll info */
#ifdef CONFIG_SOC_DM355
#define ARM_PLLDIV PLLC_PLLDIV1
diff --git a/arch/arm/mach-keystone/include/mach/clock_defs.h
b/arch/arm/mach-keystone/include/mach/clock_defs.h
index 85a046b..a0d1e5d 100644
--- a/arch/arm/mach-keystone/include/mach/clock_defs.h
+++ b/arch/arm/mach-keystone/include/mach/clock_defs.h
@@ -11,8 +11,6 @@
#include asm/arch/hardware.h
-#define BIT(x) (1 (x))
-
/* PLL Control Registers */
struct pllctl_regs {
u32 ctl;/* 00 */
diff --git a/arch/arm/mvebu-common/mbus.c b/arch/arm/mvebu-common/mbus.c
index 05c9ef2..7bb20ec 100644
--- a/arch/arm/mvebu-common/mbus.c
+++ b/arch/arm/mvebu-common/mbus.c
@@ -54,8 +54,6 @@
#include asm/arch/soc.h
#include linux/mbus.h
-#define BIT(nr)(1UL (nr))
-
/* DDR target is the same on all platforms */
#define TARGET_DDR 0
diff --git a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
index b3dae89..8263d27 100644
--- a/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
+++ b/board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c
@@ -12,8 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define BIT(nr)(1UL (nr))
-
#define ETH_PHY_CTRL_REG 0
#define ETH_PHY_CTRL_POWER_DOWN_BIT11
#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 ETH_PHY_CTRL_POWER_DOWN_BIT)
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index 7a62cc3..abcedc2 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -16,7 +16,6 @@
#define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
#define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x1)
-#define BIT(x) (1 (x))
#define JZ_NAND_ECC_CTRL_ENCODING BIT(3)
#define JZ_NAND_ECC_CTRL_RSBIT(2)
#define JZ_NAND_ECC_CTRL_RESET BIT(1)
diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c
index 484d64c..0daa79e 100644
--- a/drivers/net/mvneta.c
+++ b/drivers/net/mvneta.c
@@ -41,7 +41,6 @@
printf(fmt, ##args)
#define CONFIG_NR_CPUS 1
-#define BIT(nr)(1UL (nr))
#define ETH_HLEN 14 /* Total octets in header */
/* 2(HW hdr) 14(MAC hdr) 4(CRC) 32(extra for cache prefetch) */
diff --git a/drivers/spi/andes_spi.h b/drivers/spi/andes_spi.h
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pick this PR. thanks! Jagan. The following changes since commit d77447fdb122dab290fb1ad184a62456011e6e06: serial: pl01x: fix PL010 regression (2015-04-21 10:05:42 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to c650ca7b4c160193791dc7a52381c71c6a29e871: sf: Fix to compute proper sector_size (2015-04-28 13:31:36 +0530) Bin Meng (2): dm: sf: Save flash flags to struct spi_flash dm: sf: Make SST flash write op work again David Dueck (1): spi: omap3: Fix timeout handling Jagannadha Sutradharudu Teki (2): Revert spi: add config option to enable the WP pin function on st micron flashes sf: Fix to compute proper sector_size Pavel Machek (1): spi flash: fix trivial problems Peng Fan (1): mtd: spi: check return value of spi_setup_slave Simon Glass (1): dm: spi: Correct SPI claim/release_bus() methods Siva Durga Prasad Paladugu (3): sf: Correct the macros as per new array fast read command sf: Poll both the read status and flag status zynq: spi: Remove unnecessary error condition Stefan Roese (1): cmd_sf: Fix problem with sf update and unaligned length README| 11 -- common/cmd_sf.c | 16 +++--- drivers/mtd/spi/sf_internal.h | 7 ++- drivers/mtd/spi/sf_ops.c | 32 +--- drivers/mtd/spi/sf_probe.c| 49 +-- drivers/spi/exynos_spi.c | 6 -- drivers/spi/omap3_spi.c | 20 +++--- drivers/spi/spi-uclass.c | 4 ++-- drivers/spi/tegra114_spi.c| 3 ++- drivers/spi/tegra20_sflash.c | 3 ++- drivers/spi/tegra20_slink.c | 3 ++- drivers/spi/zynq_spi.c| 3 --- include/spi.h | 21 ++- include/spi_flash.h | 9 14 files changed, 93 insertions(+), 94 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] sf: Fix to compute proper sector_size
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Bug report (from Bin Meng):
= sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at ffe0
= sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OK
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Reported-by: Bin Meng bmeng...@gmail.com
Tested-by: Bin Meng bmeng...@gmail.com
---
Changes for v3:
- Updated comments
Changes for v2:
- Minimize the code logic
drivers/mtd/spi/sf_internal.h | 3 ++-
drivers/mtd/spi/sf_probe.c| 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index bd834dc..4158e13 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -119,7 +119,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset,
size_t len,
* @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
* @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
* @ext_jedec: Device ext_jedec ID
- * @sector_size: Sector size of this device
+ * @sector_size: Isn't necessarily a sector size from vendor,
+ * the size listed here is what works with CMD_ERASE_64K
* @nr_sectors:No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
* @flags: Important param, for flash specific behaviour
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index de8d0b7..3f6b882 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -184,6 +184,9 @@ static int spi_flash_validate_params(struct spi_slave *spi,
u8 *idcode,
flash-erase_size = flash-sector_size;
}
+ /* Now erase size becomes valid sector size */
+ flash-sector_size = flash-erase_size;
+
/* Look for the fastest read cmd */
cmd = fls(params-e_rd_cmd flash-spi-op_mode_rx);
if (cmd) {
--
1.9.1
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[U-Boot] [U-Boot PATCH v2] sf: Fix to compute proper sector_size
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Bug report (from Bin Meng):
= sf probe
SF: Detected SST25VF016B with page size 256 Bytes, erase size 4 KiB,
total 2 MiB, mapped at ffe0
= sf erase 0 +100
SF: 65536 bytes @ 0x0 Erased: OK
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Reported-by: Bin Meng bmeng...@gmail.com
---
Changes for v2:
-
drivers/mtd/spi/sf_internal.h | 3 ++-
drivers/mtd/spi/sf_probe.c| 3 +++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index bd834dc..bef8701 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -119,7 +119,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset,
size_t len,
* @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
* @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
* @ext_jedec: Device ext_jedec ID
- * @sector_size: Sector size of this device
+ * @sector_size: Isn't necessarily a sector size from vendor,
+ * the size here is what works with Sector erase (64KB)
* @nr_sectors:No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
* @flags: Important param, for flash specific behaviour
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index de8d0b7..3f6b882 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -184,6 +184,9 @@ static int spi_flash_validate_params(struct spi_slave *spi,
u8 *idcode,
flash-erase_size = flash-sector_size;
}
+ /* Now erase size becomes valid sector size */
+ flash-sector_size = flash-erase_size;
+
/* Look for the fastest read cmd */
cmd = fls(params-e_rd_cmd flash-spi-op_mode_rx);
if (cmd) {
--
1.9.1
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[U-Boot] [U-Boot 3/7] dts: zynq: Add zynq spi controller nodes
This patch adds zynq spi controller nodes in zynq-7000.dtsi.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-7000.dtsi | 24
doc/device-tree-bindings/spi/spi-zynq.txt | 27 +++
2 files changed, 51 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/spi-zynq.txt
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 2d076f1..f66f8dc 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -109,6 +109,30 @@
interrupts = 0 50 4;
};
+ spi0: spi@e0006000 {
+ compatible = xlnx,zynq-spi;
+ reg = 0xe0006000 0x1000;
+ status = disabled;
+ interrupt-parent = intc;
+ interrupts = 0 26 4;
+ clocks = clkc 25, clkc 34;
+ clock-names = ref_clk, pclk;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
+ spi1: spi@e0007000 {
+ compatible = xlnx,zynq-spi;
+ reg = 0xe0007000 0x1000;
+ status = disabled;
+ interrupt-parent = intc;
+ interrupts = 0 49 4;
+ clocks = clkc 26, clkc 35;
+ clock-names = ref_clk, pclk;
+ #address-cells = 1;
+ #size-cells = 0;
+ };
+
gem0: ethernet@e000b000 {
compatible = cdns,gem;
reg = 0xe000b000 0x4000;
diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt
b/doc/device-tree-bindings/spi/spi-zynq.txt
new file mode 100644
index 000..a7c2757
--- /dev/null
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -0,0 +1,27 @@
+Zynq SPI controller Device Tree Bindings
+
+
+Required properties:
+- compatible : Should be xlnx,spi-zynq.
+- reg : Physical base address and size of SPI registers map.
+- status : Status will be disabled in dtsi and enabled in
required dts.
+- interrupt-parent : Must be core interrupt controller.
+- interrupts : Property with a value describing the interrupt
+ number.
+- clocks : Clock phandles (see clock bindings for details).
+- clock-names : List of input clock names - ref_clk, pclk
+ (See clock bindings for details).
+
+Example:
+
+ spi@e0006000 {
+ compatible = xlnx,zynq-spi;
+ reg = 0xe0006000 0x1000;
+ status = disabled;
+ interrupt-parent = intc;
+ interrupts = 0 26 4;
+ clocks = clkc 25, clkc 34;
+ clock-names = ref_clk, pclk;
+ #address-cells = 1;
+ #size-cells = 0;
+ } ;
--
1.9.1
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[U-Boot] [U-Boot 2/7] zynq: Kconfig: Enable dm spi and spi_flash
Enabled CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH for zynq soc. Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Simon Glass s...@chromium.org Cc: Michal Simek michal.si...@xilinx.com Cc: Siva Durga Prasad Paladugu siva...@xilinx.com --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3702bb0..40f1186 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -670,6 +670,8 @@ config ZYNQ select CPU_V7 select SUPPORT_SPL select DM + select DM_SPI + select DM_SPI_FLASH config TARGET_XILINX_ZYNQMP bool Support Xilinx ZynqMP Platform -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot 6/7] dm: spi: xilinx_spi: Convert to driver model
This converts the xilinx spi driver to use the driver model.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
---
Note: Michal, can you test this, I don't have hardware.
drivers/spi/xilinx_spi.c | 212 +++
1 file changed, 124 insertions(+), 88 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 3803c4c..4acade4 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -4,6 +4,7 @@
* Supports 8 bit SPI transfers only, with or w/o FIFO
*
* Based on bfin_spi.c, by way of altera_spi.c
+ * Copyright (c) 2015 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
* Copyright (c) 2012 Stephan Linz l...@li-pro.net
* Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
* Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
@@ -14,6 +15,8 @@
#include config.h
#include common.h
+#include dm.h
+#include errno.h
#include malloc.h
#include spi.h
@@ -79,7 +82,7 @@
#endif
/* xilinx spi register set */
-struct xilinx_spi_reg {
+struct xilinx_spi_regs {
u32 __space0__[7];
u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
u32 ipisr; /* IP Interrupt Status Register (IPISR) */
@@ -97,113 +100,76 @@ struct xilinx_spi_reg {
u32 spirfor;/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
};
-/* xilinx spi slave */
-struct xilinx_spi_slave {
- struct spi_slave slave;
- struct xilinx_spi_reg *regs;
+/* xilinx spi priv */
+struct xilinx_spi_priv {
+ struct xilinx_spi_regs *regs;
unsigned int freq;
unsigned int mode;
+ unsigned int cs;
};
-static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
- struct spi_slave *slave)
-{
- return container_of(slave, struct xilinx_spi_slave, slave);
-}
-
static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int xilinx_spi_probe(struct udevice *bus)
{
- return bus ARRAY_SIZE(xilinx_spi_base_list) cs 32;
-}
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ priv-regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus-seq];
+ priv-cs = spi_chip_select(bus);
- writel(SPISSR_ACT(slave-cs), xilspi-regs-spissr);
-}
+ writel(SPISSR_RESET_VALUE, regs-srr);
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
-
- writel(SPISSR_OFF, xilspi-regs-spissr);
-}
-
-void spi_init(void)
-{
- /* do nothing */
+ return 0;
}
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
+static void spi_cs_activate(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi;
-
- if (!spi_cs_is_valid(bus, cs)) {
- printf(XILSPI error: unsupported bus %d / cs %d\n, bus, cs);
- return NULL;
- }
-
- xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
- if (!xilspi) {
- printf(XILSPI error: malloc of SPI structure failed\n);
- return NULL;
- }
- xilspi-regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
- xilspi-freq = max_hz;
- xilspi-mode = mode;
- debug(spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n,
- bus, cs, xilspi-regs, xilspi-mode, xilspi-freq);
-
- writel(SPISSR_RESET_VALUE, xilspi-regs-srr);
+ struct udevice *bus = dev-parent;
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- return xilspi-slave;
+ writel(SPISSR_ACT(priv-cs), regs-spissr);
}
-void spi_free_slave(struct spi_slave *slave)
+static void spi_cs_deactivate(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
+ struct udevice *bus = dev-parent;
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- free(xilspi);
+ writel(SPISSR_OFF, regs-spissr);
}
-int spi_claim_bus(struct spi_slave *slave)
+static int xilinx_spi_claim_bus(struct udevice *dev)
{
- struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
- u32 spicr;
+ struct udevice *bus = dev-parent;
+ struct xilinx_spi_priv *priv = dev_get_priv(bus);
+ struct xilinx_spi_regs *regs = priv-regs;
- debug(spi_claim_bus: bus:%i cs:%i\n, slave-bus, slave-cs);
- writel(SPISSR_OFF, xilspi-regs-spissr);
+ writel(SPISSR_OFF, regs-spissr);
+ writel(XILSPI_SPICR_DFLT_ON, regs
[U-Boot] [U-Boot 1/7] dm: spi: zynq_spi: Convert to driver model
This converts the zynq spi driver to use the driver model.
Minimal functional changes like using meaningful name on
structure members wrt mainlined dm spi drivers.
- input_hz - frequency
- req_hz - freq
- base - regs
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
Note: Siva Durga Prasad, can you test this on zc770_xm010
drivers/spi/zynq_spi.c | 305 +
1 file changed, 181 insertions(+), 124 deletions(-)
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index ff1ec6a..62edbbe 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -1,5 +1,6 @@
/*
* (C) Copyright 2013 Inc.
+ * (C) Copyright 2015 Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
*
* Xilinx Zynq PS SPI controller driver (master mode only)
*
@@ -8,6 +9,8 @@
#include config.h
#include common.h
+#include dm.h
+#include errno.h
#include malloc.h
#include spi.h
#include asm/io.h
@@ -44,180 +47,142 @@ struct zynq_spi_regs {
u32 rxdr; /* 0x20 */
};
-/* zynq spi slave */
-struct zynq_spi_slave {
- struct spi_slave slave;
- struct zynq_spi_regs *base;
- u8 mode;
- u8 fifo_depth;
+
+/* zynq spi platform data */
+struct zynq_spi_platdata {
+ struct zynq_spi_regs *regs;
+ u32 frequency; /* input frequency */
u32 speed_hz;
- u32 input_hz;
- u32 req_hz;
};
-static inline struct zynq_spi_slave *to_zynq_spi_slave(struct spi_slave *slave)
-{
- return container_of(slave, struct zynq_spi_slave, slave);
-}
+/* zynq spi priv */
+struct zynq_spi_priv {
+ struct zynq_spi_regs *regs;
+ u8 cs;
+ u8 mode;
+ u8 fifo_depth;
+ u32 freq; /* required frequency */
+};
-static inline struct zynq_spi_regs *get_zynq_spi_base(int dev)
+static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
{
- if (dev)
+ if (bus-seq)
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
else
return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
}
-static void zynq_spi_init_hw(struct zynq_spi_slave *zslave)
+static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
+{
+ struct zynq_spi_platdata *plat = bus-platdata;
+
+ plat-regs = get_zynq_spi_regs(bus);
+ plat-frequency = 16700;
+ plat-speed_hz = plat-frequency / 2;
+
+ return 0;
+}
+
+static void zynq_spi_init_hw(struct zynq_spi_priv *priv)
{
+ struct zynq_spi_regs *regs = priv-regs;
u32 confr;
/* Disable SPI */
- writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, zslave-base-enr);
+ writel(~ZYNQ_SPI_ENR_SPI_EN_MASK, regs-enr);
/* Disable Interrupts */
- writel(ZYNQ_SPI_IXR_ALL_MASK, zslave-base-idr);
+ writel(ZYNQ_SPI_IXR_ALL_MASK, regs-idr);
/* Clear RX FIFO */
- while (readl(zslave-base-isr)
+ while (readl(regs-isr)
ZYNQ_SPI_IXR_RXNEMPTY_MASK)
- readl(zslave-base-rxdr);
+ readl(regs-rxdr);
/* Clear Interrupts */
- writel(ZYNQ_SPI_IXR_ALL_MASK, zslave-base-isr);
+ writel(ZYNQ_SPI_IXR_ALL_MASK, regs-isr);
/* Manual slave select and Auto start */
confr = ZYNQ_SPI_CR_MCS_MASK | ZYNQ_SPI_CR_CS_MASK |
ZYNQ_SPI_CR_MSTREN_MASK;
confr = ~ZYNQ_SPI_CR_MSA_MASK;
- writel(confr, zslave-base-cr);
+ writel(confr, regs-cr);
/* Enable SPI */
- writel(ZYNQ_SPI_ENR_SPI_EN_MASK, zslave-base-enr);
+ writel(ZYNQ_SPI_ENR_SPI_EN_MASK, regs-enr);
}
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+static int zynq_spi_probe(struct udevice *bus)
{
- /* 2 bus with 3 chipselect */
- return bus 2 cs 3;
+ struct zynq_spi_platdata *plat = dev_get_platdata(bus);
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+
+ priv-regs = plat-regs;
+ priv-cs = spi_chip_select(bus);
+ priv-fifo_depth = ZYNQ_SPI_FIFO_DEPTH;
+
+ /* init the zynq spi hw */
+ zynq_spi_init_hw(priv);
+
+ return 0;
}
-void spi_cs_activate(struct spi_slave *slave)
+static void spi_cs_activate(struct udevice *dev)
{
- struct zynq_spi_slave *zslave = to_zynq_spi_slave(slave);
+ struct udevice *bus = dev-parent;
+ struct zynq_spi_priv *priv = dev_get_priv(bus);
+ struct zynq_spi_regs *regs = priv-regs;
u32 cr;
- debug(spi_cs_activate: 0x%08x\n, (u32)slave);
-
- clrbits_le32(zslave-base-cr, ZYNQ_SPI_CR_CS_MASK);
- cr = readl(zslave-base-cr);
+ clrbits_le32(regs-cr, ZYNQ_SPI_CR_CS_MASK);
+ cr = readl(regs-cr);
/*
* CS cal logic: CS[13:10]
* xxx0 - cs0
* xx01 - cs1
* x011 - cs2
*/
- cr |= (~(0x1 slave-cs) 10
[U-Boot] [U-Boot 7/7] spi: xilinx_spi: Add asm/io.h include file
This patch includes asm/io.h for readl and writel calls. build errors: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe': drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration] drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Cc: Michal Simek michal.si...@xilinx.com --- drivers/spi/xilinx_spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 4acade4..e9ff804 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -19,6 +19,7 @@ #include errno.h #include malloc.h #include spi.h +#include asm/io.h /* * [0]: http://www.xilinx.com/support/documentation -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot 5/7] dts: zynq: Enable spi1 for zc770_xm010 board
This patch enables spi1 for zynq zc770_xm010 board dts.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-zc770-xm010.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynq-zc770-xm010.dts
b/arch/arm/dts/zynq-zc770-xm010.dts
index 5e66174..e793a61 100644
--- a/arch/arm/dts/zynq-zc770-xm010.dts
+++ b/arch/arm/dts/zynq-zc770-xm010.dts
@@ -21,3 +21,7 @@
reg = 0 0x4000;
};
};
+
+spi1 {
+ status = okay;
+};
--
1.9.1
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[U-Boot] [U-Boot PATCH v2] Revert spi: add config option to enable the WP pin function on st micron flashes
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Note: Even un-reverting this patch couldn't works as expected, based
on the latest testing from Heiko Schocher.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Heiko Schocher h...@denx.de
---
README| 11 ---
drivers/mtd/spi/sf_internal.h | 4
drivers/mtd/spi/sf_probe.c| 30 --
3 files changed, 45 deletions(-)
diff --git a/README b/README
index fc1fd52..82224f7 100644
--- a/README
+++ b/README
@@ -3086,17 +3086,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
Currently Xilinx Zynq qspi supports these type of connections.
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
- SystemACE Support:
CONFIG_SYSTEMACE
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a9..bd834dc 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -97,10 +97,6 @@ enum {
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD(1 7) /* SR write protect */
-#endif
-
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 2ee228d..de8d0b7 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -288,34 +288,6 @@ int spi_flash_decode_fdt(const void *blob, struct
spi_flash *flash)
}
#endif /* CONFIG_OF_CONTROL */
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- u8 status;
- int ret;
-
- ret = spi_flash_cmd_read_status(flash, status);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_disable(flash);
- if (ret 0)
- return ret;
-
- return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- return 0;
-}
-#endif
-
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
@@ -394,8 +366,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct
spi_flash *flash)
puts( Full access #define CONFIG_SPI_FLASH_BAR\n);
}
#endif
- if (spi_enable_wp_pin(flash))
- puts(Enable WP pin failed\n);
/* Release spi bus */
spi_release_bus(spi);
--
1.9.1
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[U-Boot] [U-Boot 4/7] spi: zynq_spi: Add fdt support in driver
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying okay on respective board dts to use
the devicetree generated platdata.
Ex:
spi1 {
status = okay;
};
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Simon Glass s...@chromium.org
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu siva...@xilinx.com
---
arch/arm/dts/zynq-7000.dtsi | 2 ++
arch/arm/include/asm/arch-zynq/hardware.h | 2 --
doc/device-tree-bindings/spi/spi-zynq.txt | 2 ++
drivers/spi/zynq_spi.c| 23 +--
4 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index f66f8dc..9207159 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -117,6 +117,7 @@
interrupts = 0 26 4;
clocks = clkc 25, clkc 34;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
};
@@ -129,6 +130,7 @@
interrupts = 0 49 4;
clocks = clkc 26, clkc 35;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
};
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h
b/arch/arm/include/asm/arch-zynq/hardware.h
index e2e0b73..df9b06b 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/include/asm/arch-zynq/hardware.h
@@ -19,8 +19,6 @@
#define ZYNQ_SDHCI_BASEADDR1 0xE0101000
#define ZYNQ_I2C_BASEADDR0 0xE0004000
#define ZYNQ_I2C_BASEADDR1 0xE0005000
-#define ZYNQ_SPI_BASEADDR0 0xE0006000
-#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
#define ZYNQ_SMC_BASEADDR 0xE000E000
#define ZYNQ_NAND_BASEADDR 0xE100
diff --git a/doc/device-tree-bindings/spi/spi-zynq.txt
b/doc/device-tree-bindings/spi/spi-zynq.txt
index a7c2757..f397a36 100644
--- a/doc/device-tree-bindings/spi/spi-zynq.txt
+++ b/doc/device-tree-bindings/spi/spi-zynq.txt
@@ -11,6 +11,7 @@ Required properties:
- clocks : Clock phandles (see clock bindings for details).
- clock-names : List of input clock names - ref_clk, pclk
(See clock bindings for details).
+- spi-max-frequency: Maximum SPI clocking speed of device in Hz
Example:
@@ -22,6 +23,7 @@ Example:
interrupts = 0 26 4;
clocks = clkc 25, clkc 34;
clock-names = ref_clk, pclk;
+ spi-max-frequency = 16700;
#address-cells = 1;
#size-cells = 0;
} ;
diff --git a/drivers/spi/zynq_spi.c b/drivers/spi/zynq_spi.c
index 62edbbe..df4a99e 100644
--- a/drivers/spi/zynq_spi.c
+++ b/drivers/spi/zynq_spi.c
@@ -13,9 +13,12 @@
#include errno.h
#include malloc.h
#include spi.h
+#include fdtdec.h
#include asm/io.h
#include asm/arch/hardware.h
+DECLARE_GLOBAL_DATA_PTR;
+
/* zynq spi register bit masks ZYNQ_SPI_REG_BIT_MASK */
#define ZYNQ_SPI_CR_MSA_MASK BIT(15) /* Manual start enb */
#define ZYNQ_SPI_CR_MCS_MASK BIT(14) /* Manual chip select */
@@ -64,22 +67,22 @@ struct zynq_spi_priv {
u32 freq; /* required frequency */
};
-static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
-{
- if (bus-seq)
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
- else
- return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
-}
-
static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
{
struct zynq_spi_platdata *plat = bus-platdata;
+ const void *blob = gd-fdt_blob;
+ int node = bus-of_offset;
+
+ plat-regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node, reg);
- plat-regs = get_zynq_spi_regs(bus);
- plat-frequency = 16700;
+ /* FIXME: Use 250MHz as a suitable default */
+ plat-frequency = fdtdec_get_int(blob, node, spi-max-frequency,
+ 25000);
plat-speed_hz = plat-frequency / 2;
+ debug(zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n,
+ plat-regs, plat-frequency);
+
return 0;
}
--
1.9.1
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[U-Boot] [U-Boot 0/7] dm: spi: Convert few drivers to driver model
Driver model conversion, patches. - drivers/spi/zynq_spi.c and drivers/spi/xilinx_spi.c thanks! -- Jagan. Jagannadha Sutradharudu Teki (7): dm: spi: zynq_spi: Convert to driver model zynq: Kconfig: Enable dm spi and spi_flash dts: zynq: Add zynq spi controller nodes spi: zynq_spi: Add fdt support in driver dts: zynq: Enable spi1 for zc770_xm010 board dm: spi: xilinx_spi: Convert to driver model spi: xilinx_spi: Add asm/io.h include file arch/arm/Kconfig | 2 + arch/arm/dts/zynq-7000.dtsi | 26 +++ arch/arm/dts/zynq-zc770-xm010.dts | 4 + arch/arm/include/asm/arch-zynq/hardware.h | 2 - doc/device-tree-bindings/spi/spi-zynq.txt | 29 +++ drivers/spi/xilinx_spi.c | 213 +++- drivers/spi/zynq_spi.c| 312 ++ 7 files changed, 372 insertions(+), 216 deletions(-) create mode 100644 doc/device-tree-bindings/spi/spi-zynq.txt -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] sf: Fix to compute proper sector_size
Upto now flash sector_size is assigned from params which isn't
necessarily a sector size from vendor, so based on the SECT_*
flags from flash_params the erase_size will compute and it will
become the sector_size finally.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Reported-by: Bin Meng bmeng...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 3 ++-
drivers/mtd/spi/sf_probe.c| 10 +++---
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d273d30..6c73992 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -123,7 +123,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset,
size_t len,
* @name: Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
* @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
* @ext_jedec: Device ext_jedec ID
- * @sector_size: Sector size of this device
+ * @sector_size: Isn't necessarily a sector size from vendor, the size
here
+ * is what works with Sector erase (64KB)
* @nr_sectors:No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
* @flags: Important param, for flash specific behaviour
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index d19138d..68ec583 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -165,8 +165,9 @@ static int spi_flash_validate_params(struct spi_slave *spi,
u8 *idcode,
flash-page_size = 256;
}
flash-page_size = flash-shift;
- flash-sector_size = params-sector_size flash-shift;
- flash-size = flash-sector_size * params-nr_sectors flash-shift;
+ params-nr_sectors = flash-shift;
+ params-sector_size = flash-shift;
+ flash-size = params-sector_size * params-nr_sectors;
#ifdef CONFIG_SF_DUAL_FLASH
if (flash-dual_flash SF_DUAL_STACKED_FLASH)
flash-size = 1;
@@ -181,9 +182,12 @@ static int spi_flash_validate_params(struct spi_slave
*spi, u8 *idcode,
flash-erase_size = 32768 flash-shift;
} else {
flash-erase_cmd = CMD_ERASE_64K;
- flash-erase_size = flash-sector_size;
+ flash-erase_size = info-sector_size;
}
+ /* Now erase size becomes valid sector size */
+ flash-sector_size = flash-erase_size;
+
/* Look for the fastest read cmd */
cmd = fls(params-e_rd_cmd flash-spi-op_mode_rx);
if (cmd) {
--
1.9.1
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[U-Boot] [U-Boot PATCH 4/8] spi: Zap oc_tiny_spi driver
Zap oc_tiny_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Thomas Chou tho...@wytron.com.tw
---
drivers/spi/Makefile | 1 -
drivers/spi/oc_tiny_spi.c | 245 --
2 files changed, 246 deletions(-)
delete mode 100644 drivers/spi/oc_tiny_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 1e3611d..507c315 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
obj-$(CONFIG_MXS_SPI) += mxs_spi.o
-obj-$(CONFIG_OC_TINY_SPI) += oc_tiny_spi.o
obj-$(CONFIG_OMAP3_SPI) += omap3_spi.o
obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
diff --git a/drivers/spi/oc_tiny_spi.c b/drivers/spi/oc_tiny_spi.c
deleted file mode 100644
index 4de5d00..000
--- a/drivers/spi/oc_tiny_spi.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Opencore tiny_spi driver
- *
- * http://opencores.org/project,tiny_spi
- *
- * based on bfin_spi.c
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2010 Thomas Chou tho...@wytron.com.tw
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include common.h
-#include asm/io.h
-#include malloc.h
-#include spi.h
-#include asm/gpio.h
-
-#define TINY_SPI_STATUS_TXE 0x1
-#define TINY_SPI_STATUS_TXR 0x2
-
-struct tiny_spi_regs {
- unsigned rxdata;/* Rx data reg */
- unsigned txdata;/* Tx data reg */
- unsigned status;/* Status reg */
- unsigned control; /* Control reg */
- unsigned baud; /* Baud reg */
-};
-
-struct tiny_spi_host {
- uint base;
- uint freq;
- uint baudwidth;
-};
-static const struct tiny_spi_host tiny_spi_host_list[] =
- CONFIG_SYS_TINY_SPI_LIST;
-
-struct tiny_spi_slave {
- struct spi_slave slave;
- const struct tiny_spi_host *host;
- uint mode;
- uint baud;
- uint flg;
-};
-#define to_tiny_spi_slave(s) container_of(s, struct tiny_spi_slave, slave)
-
-int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-{
- return bus ARRAY_SIZE(tiny_spi_host_list) gpio_is_valid(cs);
-}
-
-void spi_cs_activate(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- unsigned int cs = slave-cs;
-
- gpio_set_value(cs, tiny_spi-flg);
- debug(%s: SPI_CS_GPIO:%x\n, __func__, gpio_get_value(cs));
-}
-
-void spi_cs_deactivate(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- unsigned int cs = slave-cs;
-
- gpio_set_value(cs, !tiny_spi-flg);
- debug(%s: SPI_CS_GPIO:%x\n, __func__, gpio_get_value(cs));
-}
-
-void spi_set_speed(struct spi_slave *slave, uint hz)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- const struct tiny_spi_host *host = tiny_spi-host;
-
- tiny_spi-baud = min(DIV_ROUND_UP(host-freq, hz * 2),
-(1 host-baudwidth)) - 1;
- debug(%s: speed %u actual %u\n, __func__, hz,
- host-freq / ((tiny_spi-baud + 1) * 2));
-}
-
-void spi_init(void)
-{
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int hz, unsigned int mode)
-{
- struct tiny_spi_slave *tiny_spi;
-
- if (!spi_cs_is_valid(bus, cs) || gpio_request(cs, tiny_spi))
- return NULL;
-
- tiny_spi = spi_alloc_slave(struct tiny_spi_slave, bus, cs);
- if (!tiny_spi)
- return NULL;
-
- tiny_spi-host = tiny_spi_host_list[bus];
- tiny_spi-mode = mode (SPI_CPOL | SPI_CPHA);
- tiny_spi-flg = mode SPI_CS_HIGH ? 1 : 0;
- spi_set_speed(tiny_spi-slave, hz);
-
- debug(%s: bus:%i cs:%i base:%lx\n, __func__,
- bus, cs, tiny_spi-host-base);
- return tiny_spi-slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
-
- gpio_free(slave-cs);
- free(tiny_spi);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct tiny_spi_slave *tiny_spi = to_tiny_spi_slave(slave);
- struct tiny_spi_regs *regs = (void *)tiny_spi-host-base;
-
- debug(%s: bus:%i cs:%i\n, __func__, slave-bus, slave-cs);
- gpio_direction_output(slave-cs, !tiny_spi-flg);
- writel(tiny_spi-mode, regs-control);
- writel(tiny_spi-baud, regs-baud);
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- debug(%s: bus:%i cs:%i\n, __func__, slave-bus, slave-cs);
-}
-
-#ifndef CONFIG_TINY_SPI_IDLE_VAL
-# define CONFIG_TINY_SPI_IDLE_VAL 0xff
-#endif
-
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
-void *din, unsigned long flags)
-{
- struct tiny_spi_slave *tiny_spi
[U-Boot] [U-Boot PATCH 6/8] spi: xilinx_spi: Driver clean-up
- Zap unneeded macros
- Re-arrange the code
- Removed __attribute__((weak))
- Replace __func__ macro with func names to save macro transition.
- Re-arranged comment lines.
- Arrange driver code in more readable format[1]
[1] http://lists.denx.de/pipermail/u-boot/2013-August/160473.html
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Michal Simek michal.si...@xilinx.com
---
drivers/spi/xilinx_spi.c | 164 ---
1 file changed, 57 insertions(+), 107 deletions(-)
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 8073edc..650e494 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -1,79 +1,31 @@
/*
* Xilinx SPI driver
*
- * supports 8 bit SPI transfers only, with or w/o FIFO
+ * Supports 8 bit SPI transfers only, with or w/o FIFO
*
- * based on bfin_spi.c, by way of altera_spi.c
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
- * Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
+ * Based on bfin_spi.c, by way of altera_spi.c
* Copyright (c) 2012 Stephan Linz l...@li-pro.net
+ * Copyright (c) 2010 Graeme Smecher graeme.smec...@mail.mcgill.ca
+ * Copyright (c) 2010 Thomas Chou tho...@wytron.com.tw
+ * Copyright (c) 2005-2008 Analog Devices Inc.
*
* SPDX-License-Identifier:GPL-2.0+
- *
- * [0]: http://www.xilinx.com/support/documentation
- *
- * [S]:[0]/ip_documentation/xps_spi.pdf
- * [0]/ip_documentation/axi_spi_ds742.pdf
*/
+
#include config.h
#include common.h
#include malloc.h
#include spi.h
/*
- * Xilinx SPI Register Definition
+ * [0]: http://www.xilinx.com/support/documentation
*
+ * Xilinx SPI Register Definitions
* [1]:[0]/ip_documentation/xps_spi.pdf
* page 8, Register Descriptions
* [2]:[0]/ip_documentation/axi_spi_ds742.pdf
* page 7, Register Overview Table
*/
-struct xilinx_spi_reg {
- u32 __space0__[7];
- u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
- u32 ipisr; /* IP Interrupt Status Register (IPISR) */
- u32 __space1__;
- u32 ipier; /* IP Interrupt Enable Register (IPIER) */
- u32 __space2__[5];
- u32 srr;/* Softare Reset Register (SRR) */
- u32 __space3__[7];
- u32 spicr; /* SPI Control Register (SPICR) */
- u32 spisr; /* SPI Status Register (SPISR) */
- u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
- u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
- u32 spissr; /* SPI Slave Select Register (SPISSR) */
- u32 spitfor;/* SPI Transmit FIFO Occupancy Register (SPITFOR) */
- u32 spirfor;/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
-};
-
-/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
-#define DGIER_GIE (1 31)
-
-/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
-#define IPISR_DRR_NOT_EMPTY(1 8)
-#define IPISR_SLAVE_SELECT (1 7)
-#define IPISR_TXF_HALF_EMPTY (1 6)
-#define IPISR_DRR_OVERRUN (1 5)
-#define IPISR_DRR_FULL (1 4)
-#define IPISR_DTR_UNDERRUN (1 3)
-#define IPISR_DTR_EMPTY(1 2)
-#define IPISR_SLAVE_MODF (1 1)
-#define IPISR_MODF (1 0)
-
-/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
-#define IPIER_DRR_NOT_EMPTY(1 8)
-#define IPIER_SLAVE_SELECT (1 7)
-#define IPIER_TXF_HALF_EMPTY (1 6)
-#define IPIER_DRR_OVERRUN (1 5)
-#define IPIER_DRR_FULL (1 4)
-#define IPIER_DTR_UNDERRUN (1 3)
-#define IPIER_DTR_EMPTY(1 2)
-#define IPIER_SLAVE_MODF (1 1)
-#define IPIER_MODF (1 0)
-
-/* Softare Reset Register (srr), [1] p9, [2] p8 */
-#define SRR_RESET_CODE 0x000A
/* SPI Control Register (spicr), [1] p9, [2] p8 */
#define SPICR_LSB_FIRST(1 9)
@@ -110,17 +62,42 @@ struct xilinx_spi_reg {
#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
#define SPISSR_OFF ~0UL
-/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
-#define SPITFOR_OCYVAL_POS 0
-#define SPITFOR_OCYVAL_MASK(0xf SPITFOR_OCYVAL_POS)
-
-/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
-#define SPIRFOR_OCYVAL_POS 0
-#define SPIRFOR_OCYVAL_MASK(0xf SPIRFOR_OCYVAL_POS)
-
/* SPI Software Reset Register (ssr) */
#define SPISSR_RESET_VALUE 0x0a
+#define XILSPI_MAX_XFER_BITS 8
+#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
+ SPICR_SPE)
+#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
+
+#ifndef CONFIG_XILINX_SPI_IDLE_VAL
+#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
+#endif
+
+#ifndef CONFIG_SYS_XILINX_SPI_LIST
+#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
+#endif
+
+/* xilinx spi register set */
+struct
[U-Boot] [U-Boot PATCH 3/8] spi: Zap ftssp010_spi driver
Zap ftssp010_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Kuo-Jung Su dant...@faraday-tech.com
Cc: Axel Lin axel@ingics.com
---
drivers/spi/Makefile | 1 -
drivers/spi/ftssp010_spi.c | 498 -
2 files changed, 499 deletions(-)
delete mode 100644 drivers/spi/ftssp010_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 93065b7..1e3611d 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -28,7 +28,6 @@ obj-$(CONFIG_CF_QSPI) += cf_qspi.o
obj-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o
obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
-obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
diff --git a/drivers/spi/ftssp010_spi.c b/drivers/spi/ftssp010_spi.c
deleted file mode 100644
index c7d6480..000
--- a/drivers/spi/ftssp010_spi.c
+++ /dev/null
@@ -1,498 +0,0 @@
-/*
- * (C) Copyright 2013
- * Faraday Technology Corporation. http://www.faraday-tech.com/tw/
- * Kuo-Jung Su dant...@gmail.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include common.h
-#include linux/compat.h
-#include asm/io.h
-#include malloc.h
-#include spi.h
-
-#ifndef CONFIG_FTSSP010_BASE_LIST
-#define CONFIG_FTSSP010_BASE_LIST { CONFIG_FTSSP010_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_BASE
-#define CONFIG_FTSSP010_GPIO_BASE 0
-#endif
-
-#ifndef CONFIG_FTSSP010_GPIO_LIST
-#define CONFIG_FTSSP010_GPIO_LIST { CONFIG_FTSSP010_GPIO_BASE }
-#endif
-
-#ifndef CONFIG_FTSSP010_CLOCK
-#define CONFIG_FTSSP010_CLOCK clk_get_rate(SSP);
-#endif
-
-#ifndef CONFIG_FTSSP010_TIMEOUT
-#define CONFIG_FTSSP010_TIMEOUT 100
-#endif
-
-/* FTSSP010 chip registers */
-struct ftssp010_regs {
- uint32_t cr[3];/* control register */
- uint32_t sr; /* status register */
- uint32_t icr; /* interrupt control register */
- uint32_t isr; /* interrupt status register */
- uint32_t dr; /* data register */
- uint32_t rsvd[17];
- uint32_t revr; /* revision register */
- uint32_t fear; /* feature register */
-};
-
-/* Control Register 0 */
-#define CR0_FFMT_MASK (7 12)
-#define CR0_FFMT_SSP(0 12)
-#define CR0_FFMT_SPI(1 12)
-#define CR0_FFMT_MICROWIRE (2 12)
-#define CR0_FFMT_I2S(3 12)
-#define CR0_FFMT_AC97 (4 12)
-#define CR0_FLASH (1 11)
-#define CR0_FSDIST(x) (((x) 0x03) 8)
-#define CR0_LOOP(1 7) /* loopback mode */
-#define CR0_LSB (1 6) /* LSB */
-#define CR0_FSPO(1 5) /* fs atcive low (I2S only) */
-#define CR0_FSJUSTIFY (1 4)
-#define CR0_OPM_SLAVE (0 2)
-#define CR0_OPM_MASTER (3 2)
-#define CR0_OPM_I2S_MSST(3 2) /* master stereo mode */
-#define CR0_OPM_I2S_MSMO(2 2) /* master mono mode */
-#define CR0_OPM_I2S_SLST(1 2) /* slave stereo mode */
-#define CR0_OPM_I2S_SLMO(0 2) /* slave mono mode */
-#define CR0_SCLKPO (1 1) /* clock polarity */
-#define CR0_SCLKPH (1 0) /* clock phase */
-
-/* Control Register 1 */
-#define CR1_PDL(x) (((x) 0xff) 24) /* padding length */
-#define CR1_SDL(x) x) - 1) 0x1f) 16) /* data length */
-#define CR1_DIV(x) (((x) - 1) 0x) /* clock divider */
-
-/* Control Register 2 */
-#define CR2_CS(x)(((x) 3) 10) /* CS/FS select */
-#define CR2_FS (1 9) /* CS/FS signal level */
-#define CR2_TXEN (1 8) /* tx enable */
-#define CR2_RXEN (1 7) /* rx enable */
-#define CR2_RESET(1 6) /* chip reset */
-#define CR2_TXFC (1 3) /* tx fifo Clear */
-#define CR2_RXFC (1 2) /* rx fifo Clear */
-#define CR2_TXDOE(1 1) /* tx data output enable */
-#define CR2_EN (1 0) /* chip enable */
-
-/* Status Register */
-#define SR_RFF (1 0) /* rx fifo full */
-#define SR_TFNF (1 1) /* tx fifo not full */
-#define SR_BUSY (1 2) /* chip busy */
-#define SR_RFVE(reg) (((reg) 4) 0x1f) /* rx fifo valid entries */
-#define SR_TFVE(reg) (((reg) 12) 0x1f) /* tx fifo valid entries */
-
-/* Feature Register */
-#define FEAR_BITS(reg) reg) 0) 0xff) + 1) /* data width */
-#define FEAR_RFSZ(reg) reg) 8) 0xff) + 1) /* rx fifo size */
-#define FEAR_TFSZ(reg) reg) 16) 0xff) + 1) /* tx fifo size */
-#define FEAR_AC97(1 24)
-#define FEAR_I2S (1 25)
-#define FEAR_SPI_MWR (1 26)
-#define FEAR_SSP (1 27)
-#define FEAR_SPDIF (1 28)
-
-/* FTGPIO010 chip registers */
-struct ftgpio010_regs {
- uint32_t out; /* 0x00: Data Output */
- uint32_t in; /* 0x04: Data Input */
- uint32_t dir; /* 0x08: Direction */
- uint32_t bypass; /* 0x0c: Bypass */
- uint32_t set; /* 0x10: Data Set */
- uint32_t clr
[U-Boot] [U-Boot PATCH 2/8] spi: Zap andes_spi driver
Zap andes_spi driver since the boards used this driver
is no longer been active.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Macpaul Lin macp...@andestech.com
---
drivers/spi/Makefile| 1 -
drivers/spi/andes_spi.c | 284
drivers/spi/andes_spi.h | 115
3 files changed, 400 deletions(-)
delete mode 100644 drivers/spi/andes_spi.c
delete mode 100644 drivers/spi/andes_spi.h
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e288692..93065b7 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -17,7 +17,6 @@ endif
obj-$(CONFIG_EP93XX_SPI) += ep93xx_spi.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
-obj-$(CONFIG_ANDES_SPI) += andes_spi.o
obj-$(CONFIG_ARMADA100_SPI) += armada100_spi.o
obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
diff --git a/drivers/spi/andes_spi.c b/drivers/spi/andes_spi.c
deleted file mode 100644
index 82aed75..000
--- a/drivers/spi/andes_spi.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Driver of Andes SPI Controller
- *
- * (C) Copyright 2011 Andes Technology
- * Macpaul Lin macp...@andestech.com
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#include common.h
-#include malloc.h
-#include spi.h
-
-#include asm/io.h
-#include andes_spi.h
-
-void spi_init(void)
-{
- /* do nothing */
-}
-
-static void andes_spi_spit_en(struct andes_spi_slave *ds)
-{
- unsigned int dcr = readl(ds-regs-dcr);
-
- debug(%s: dcr: %x, write value: %x\n,
- __func__, dcr, (dcr | ANDES_SPI_DCR_SPIT));
-
- writel((dcr | ANDES_SPI_DCR_SPIT), ds-regs-dcr);
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct andes_spi_slave *ds;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- ds = spi_alloc_slave(struct andes_spi_slave, bus, cs);
- if (!ds)
- return NULL;
-
- ds-regs = (struct andes_spi_regs *)CONFIG_SYS_SPI_BASE;
-
- /*
-* The hardware of andes_spi will set its frequency according
-* to APB/AHB bus clock. Hence the hardware doesn't allow changing of
-* requency and so the user requested speed is always ignored.
-*/
- ds-freq = max_hz;
-
- return ds-slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
-
- free(ds);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
- unsigned int apb;
- unsigned int baud;
-
- /* Enable the SPI hardware */
- writel(ANDES_SPI_CR_SPIRST, ds-regs-cr);
- udelay(1000);
-
- /* setup format */
- baud = ((CONFIG_SYS_CLK_FREQ / CONFIG_SYS_SPI_CLK / 2) - 1) 0xFF;
-
- /*
-* SPI_CLK = AHB bus clock / ((BAUD + 1)*2)
-* BAUD = AHB bus clock / SPI_CLK / 2) - 1
-*/
- apb = (readl(ds-regs-apb) 0xff00) | baud;
- writel(apb, ds-regs-apb);
-
- /* no interrupts */
- writel(0, ds-regs-ie);
-
- return 0;
-}
-
-void spi_release_bus(struct spi_slave *slave)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
-
- /* Disable the SPI hardware */
- writel(ANDES_SPI_CR_SPIRST, ds-regs-cr);
-}
-
-static int andes_spi_read(struct spi_slave *slave, unsigned int len,
- u8 *rxp, unsigned long flags)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
- unsigned int i, left;
- unsigned int data;
-
- debug(%s: slave: %x, len: %d, rxp: %x, flags: %d\n,
- __func__, slave, len, rxp, flags);
-
- debug(%s: data: , __func__);
- while (len 0) {
- left = min(len, 4);
- data = readl(ds-regs-data);
-
- debug( );
- for (i = 0; i left; i++) {
- debug(%02x , data 0xff);
- *rxp++ = data;
- data = 8;
- len--;
- }
- }
- debug(\n);
-
- return 0;
-}
-
-static int andes_spi_write(struct spi_slave *slave, unsigned int wlen,
- unsigned int rlen, const u8 *txp, unsigned long flags)
-{
- struct andes_spi_slave *ds = to_andes_spi(slave);
- unsigned int data;
- unsigned int i, left;
- unsigned int spit_enabled = 0;
-
- debug(%s: slave: %x, wlen: %d, rlen: %d, txp: %x, flags: %x\n,
- __func__, slave, wlen, rlen, txp, flags);
-
- /* The value of wlen and rlen wrote to register must minus 1 */
- if (rlen == 0) /* write only */
- writel(ANDES_SPI_DCR_MODE_WO | ANDES_SPI_DCR_WCNT(wlen-1) |
- ANDES_SPI_DCR_RCNT(0), ds-regs-dcr);
- else
[U-Boot] [U-Boot PATCH] linux/bitops.h: Add BIT macro
Updated in spi relevent files.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sandbox.c | 4 +--
drivers/mtd/spi/sf_internal.h | 10 +++
drivers/spi/altera_spi.c | 26 -
drivers/spi/atmel_spi.h| 52 +-
drivers/spi/bfin_spi6xx.c | 8 +++---
drivers/spi/cadence_qspi_apb.c | 28 +-
drivers/spi/davinci_spi.c | 2 --
drivers/spi/designware_spi.c | 14 -
drivers/spi/exynos_spi.c | 4 +--
drivers/spi/fsl_dspi.c | 2 +-
drivers/spi/fsl_espi.c | 20 ++---
drivers/spi/fsl_qspi.c | 4 +--
drivers/spi/ich.c | 4 +--
drivers/spi/mpc8xxx_spi.c | 2 +-
drivers/spi/omap3_spi.h| 48 +++
drivers/spi/sh_qspi.c | 16 +--
drivers/spi/tegra114_spi.c | 64 +-
drivers/spi/tegra20_sflash.c | 50 -
drivers/spi/tegra20_slink.c| 56 ++--
drivers/spi/ti_qspi.c | 10 +++
drivers/spi/xilinx_spi.c | 32 ++---
drivers/spi/zynq_spi.c | 16 +--
include/linux/bitops.h | 1 +
include/spi.h | 22 +++
24 files changed, 247 insertions(+), 248 deletions(-)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index d576d31..54baa42 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -53,8 +53,8 @@ static const char *sandbox_sf_state_name(enum
sandbox_sf_state state)
}
/* Bits for the status register */
-#define STAT_WIP (1 0)
-#define STAT_WEL (1 1)
+#define STAT_WIP BIT(0)
+#define STAT_WEL BIT(1)
/* Assume all SPI flashes have 3 byte addresses since they do atm */
#define SF_ADDR_LEN3
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 58007de..d273d30 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -92,13 +92,13 @@ enum {
#endif
/* Common status */
-#define STATUS_WIP (1 0)
-#define STATUS_QEB_WINSPAN (1 1)
-#define STATUS_QEB_MXIC(1 6)
-#define STATUS_PEC (1 7)
+#define STATUS_WIP BIT(0)
+#define STATUS_QEB_WINSPAN BIT(1)
+#define STATUS_QEB_MXICBIT(6)
+#define STATUS_PEC BIT(7)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD(1 7) /* SR write protect */
+#define STATUS_SRWDBIT(7) /* SR write protect */
#endif
/* Flash timeout values */
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c
index a4d03d9..2302117 100644
--- a/drivers/spi/altera_spi.c
+++ b/drivers/spi/altera_spi.c
@@ -29,19 +29,19 @@ struct altera_spi_regs {
u32 slave_sel;
};
-#define ALTERA_SPI_STATUS_ROE_MSK (1 3)
-#define ALTERA_SPI_STATUS_TOE_MSK (1 4)
-#define ALTERA_SPI_STATUS_TMT_MSK (1 5)
-#define ALTERA_SPI_STATUS_TRDY_MSK (1 6)
-#define ALTERA_SPI_STATUS_RRDY_MSK (1 7)
-#define ALTERA_SPI_STATUS_E_MSK(1 8)
-
-#define ALTERA_SPI_CONTROL_IROE_MSK(1 3)
-#define ALTERA_SPI_CONTROL_ITOE_MSK(1 4)
-#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 6)
-#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 7)
-#define ALTERA_SPI_CONTROL_IE_MSK (1 8)
-#define ALTERA_SPI_CONTROL_SSO_MSK (1 10)
+#define ALTERA_SPI_STATUS_ROE_MSK BIT(3)
+#define ALTERA_SPI_STATUS_TOE_MSK BIT(4)
+#define ALTERA_SPI_STATUS_TMT_MSK BIT(5)
+#define ALTERA_SPI_STATUS_TRDY_MSK BIT(6)
+#define ALTERA_SPI_STATUS_RRDY_MSK BIT(7)
+#define ALTERA_SPI_STATUS_E_MSKBIT(8)
+
+#define ALTERA_SPI_CONTROL_IROE_MSKBIT(3)
+#define ALTERA_SPI_CONTROL_ITOE_MSKBIT(4)
+#define ALTERA_SPI_CONTROL_ITRDY_MSK BIT(6)
+#define ALTERA_SPI_CONTROL_IRRDY_MSK BIT(7)
+#define ALTERA_SPI_CONTROL_IE_MSK BIT(8)
+#define ALTERA_SPI_CONTROL_SSO_MSK BIT(10)
static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST;
diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h
index 1538a23..5b892d2 100644
--- a/drivers/spi/atmel_spi.h
+++ b/drivers/spi/atmel_spi.h
@@ -15,19 +15,19 @@
#define ATMEL_SPI_VERSION 0x00fc
/* Bits in CR */
-#define ATMEL_SPI_CR_SPIEN (1 0)
-#define ATMEL_SPI_CR_SPIDIS(1 1)
-#define ATMEL_SPI_CR_SWRST (1 7)
-#define ATMEL_SPI_CR_LASTXFER (1 24)
+#define ATMEL_SPI_CR_SPIEN BIT(0)
+#define ATMEL_SPI_CR_SPIDISBIT(1)
+#define ATMEL_SPI_CR_SWRST BIT(7)
+#define ATMEL_SPI_CR_LASTXFER BIT(24)
/* Bits in MR */
-#define ATMEL_SPI_MR_MSTR (1 0)
-#define ATMEL_SPI_MR_PS(1 1)
-#define ATMEL_SPI_MR_PCSDEC
[U-Boot] [U-Boot PATCH 8/8] spi: davinci_spi: Driver cleanup
Arrange driver code in more readable format[1] for easy accessing
and readable.
[1] http://lists.denx.de/pipermail/u-boot/2013-August/160473.html
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Rex Chang rch...@ti.com
Cc: Murali Karicheri m-kariche...@ti.com
---
drivers/spi/davinci_spi.c | 343 +++---
1 file changed, 173 insertions(+), 170 deletions(-)
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index e0ecf99..0a036cc 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -8,39 +8,13 @@
*
* SPDX-License-Identifier:GPL-2.0+
*/
+
#include common.h
#include spi.h
#include malloc.h
#include asm/io.h
#include asm/arch/hardware.h
-struct davinci_spi_regs {
- dv_reg gcr0; /* 0x00 */
- dv_reg gcr1; /* 0x04 */
- dv_reg int0; /* 0x08 */
- dv_reg lvl;/* 0x0c */
- dv_reg flg;/* 0x10 */
- dv_reg pc0;/* 0x14 */
- dv_reg pc1;/* 0x18 */
- dv_reg pc2;/* 0x1c */
- dv_reg pc3;/* 0x20 */
- dv_reg pc4;/* 0x24 */
- dv_reg pc5;/* 0x28 */
- dv_reg rsvd[3];
- dv_reg dat0; /* 0x38 */
- dv_reg dat1; /* 0x3c */
- dv_reg buf;/* 0x40 */
- dv_reg emu;/* 0x44 */
- dv_reg delay; /* 0x48 */
- dv_reg def;/* 0x4c */
- dv_reg fmt0; /* 0x50 */
- dv_reg fmt1; /* 0x54 */
- dv_reg fmt2; /* 0x58 */
- dv_reg fmt3; /* 0x5c */
- dv_reg intvec0;/* 0x60 */
- dv_reg intvec1;/* 0x64 */
-};
-
#define BIT(x) (1 (x))
/* SPIGCR0 */
@@ -112,6 +86,35 @@ struct davinci_spi_regs {
#define SPI2_BASE CONFIG_SYS_SPI2_BASE
#endif
+/* davinci spi register set */
+struct davinci_spi_regs {
+ dv_reg gcr0; /* 0x00 */
+ dv_reg gcr1; /* 0x04 */
+ dv_reg int0; /* 0x08 */
+ dv_reg lvl;/* 0x0c */
+ dv_reg flg;/* 0x10 */
+ dv_reg pc0;/* 0x14 */
+ dv_reg pc1;/* 0x18 */
+ dv_reg pc2;/* 0x1c */
+ dv_reg pc3;/* 0x20 */
+ dv_reg pc4;/* 0x24 */
+ dv_reg pc5;/* 0x28 */
+ dv_reg rsvd[3];
+ dv_reg dat0; /* 0x38 */
+ dv_reg dat1; /* 0x3c */
+ dv_reg buf;/* 0x40 */
+ dv_reg emu;/* 0x44 */
+ dv_reg delay; /* 0x48 */
+ dv_reg def;/* 0x4c */
+ dv_reg fmt0; /* 0x50 */
+ dv_reg fmt1; /* 0x54 */
+ dv_reg fmt2; /* 0x58 */
+ dv_reg fmt3; /* 0x5c */
+ dv_reg intvec0;/* 0x60 */
+ dv_reg intvec1;/* 0x64 */
+};
+
+/* davinci spi slave */
struct davinci_spi_slave {
struct spi_slave slave;
struct davinci_spi_regs *regs;
@@ -123,111 +126,6 @@ static inline struct davinci_spi_slave
*to_davinci_spi(struct spi_slave *slave)
return container_of(slave, struct davinci_spi_slave, slave);
}
-void spi_init()
-{
- /* do nothing */
-}
-
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
- unsigned int max_hz, unsigned int mode)
-{
- struct davinci_spi_slave*ds;
-
- if (!spi_cs_is_valid(bus, cs))
- return NULL;
-
- ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
- if (!ds)
- return NULL;
-
- switch (bus) {
- case SPI0_BUS:
- ds-regs = (struct davinci_spi_regs *)SPI0_BASE;
- break;
-#ifdef CONFIG_SYS_SPI1
- case SPI1_BUS:
- ds-regs = (struct davinci_spi_regs *)SPI1_BASE;
- break;
-#endif
-#ifdef CONFIG_SYS_SPI2
- case SPI2_BUS:
- ds-regs = (struct davinci_spi_regs *)SPI2_BASE;
- break;
-#endif
- default: /* Invalid bus number */
- return NULL;
- }
-
- ds-freq = max_hz;
-
- return ds-slave;
-}
-
-void spi_free_slave(struct spi_slave *slave)
-{
- struct davinci_spi_slave *ds = to_davinci_spi(slave);
-
- free(ds);
-}
-
-int spi_claim_bus(struct spi_slave *slave)
-{
- struct davinci_spi_slave *ds = to_davinci_spi(slave);
- unsigned int scalar;
-
- /* Enable the SPI hardware */
- writel(SPIGCR0_SPIRST_MASK, ds-regs-gcr0);
- udelay(1000);
- writel(SPIGCR0_SPIENA_MASK, ds-regs-gcr0);
-
- /* Set master mode, powered up and not activated */
- writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, ds-regs-gcr1);
-
- /* CS, CLK, SIMO and SOMI are functional pins */
- writel(((1 slave-cs
[U-Boot] [U-Boot PATCH 5/8] spi: xilinx_spi: Move header code to driver
Move the header code into driver for more readable and
easy to access it.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Michal Simek michal.si...@xilinx.com
---
drivers/spi/xilinx_spi.c | 113 +-
drivers/spi/xilinx_spi.h | 138 ---
2 files changed, 112 insertions(+), 139 deletions(-)
delete mode 100644 drivers/spi/xilinx_spi.h
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 56d99d1..8073edc 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -21,7 +21,118 @@
#include malloc.h
#include spi.h
-#include xilinx_spi.h
+/*
+ * Xilinx SPI Register Definition
+ *
+ * [1]:[0]/ip_documentation/xps_spi.pdf
+ * page 8, Register Descriptions
+ * [2]:[0]/ip_documentation/axi_spi_ds742.pdf
+ * page 7, Register Overview Table
+ */
+struct xilinx_spi_reg {
+ u32 __space0__[7];
+ u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
+ u32 ipisr; /* IP Interrupt Status Register (IPISR) */
+ u32 __space1__;
+ u32 ipier; /* IP Interrupt Enable Register (IPIER) */
+ u32 __space2__[5];
+ u32 srr;/* Softare Reset Register (SRR) */
+ u32 __space3__[7];
+ u32 spicr; /* SPI Control Register (SPICR) */
+ u32 spisr; /* SPI Status Register (SPISR) */
+ u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
+ u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
+ u32 spissr; /* SPI Slave Select Register (SPISSR) */
+ u32 spitfor;/* SPI Transmit FIFO Occupancy Register (SPITFOR) */
+ u32 spirfor;/* SPI Receive FIFO Occupancy Register (SPIRFOR) */
+};
+
+/* Device Global Interrupt Enable Register (dgier), [1] p15, [2] p15 */
+#define DGIER_GIE (1 31)
+
+/* IP Interrupt Status Register (ipisr), [1] p15, [2] p15 */
+#define IPISR_DRR_NOT_EMPTY(1 8)
+#define IPISR_SLAVE_SELECT (1 7)
+#define IPISR_TXF_HALF_EMPTY (1 6)
+#define IPISR_DRR_OVERRUN (1 5)
+#define IPISR_DRR_FULL (1 4)
+#define IPISR_DTR_UNDERRUN (1 3)
+#define IPISR_DTR_EMPTY(1 2)
+#define IPISR_SLAVE_MODF (1 1)
+#define IPISR_MODF (1 0)
+
+/* IP Interrupt Enable Register (ipier), [1] p17, [2] p18 */
+#define IPIER_DRR_NOT_EMPTY(1 8)
+#define IPIER_SLAVE_SELECT (1 7)
+#define IPIER_TXF_HALF_EMPTY (1 6)
+#define IPIER_DRR_OVERRUN (1 5)
+#define IPIER_DRR_FULL (1 4)
+#define IPIER_DTR_UNDERRUN (1 3)
+#define IPIER_DTR_EMPTY(1 2)
+#define IPIER_SLAVE_MODF (1 1)
+#define IPIER_MODF (1 0)
+
+/* Softare Reset Register (srr), [1] p9, [2] p8 */
+#define SRR_RESET_CODE 0x000A
+
+/* SPI Control Register (spicr), [1] p9, [2] p8 */
+#define SPICR_LSB_FIRST(1 9)
+#define SPICR_MASTER_INHIBIT (1 8)
+#define SPICR_MANUAL_SS(1 7)
+#define SPICR_RXFIFO_RESEST(1 6)
+#define SPICR_TXFIFO_RESEST(1 5)
+#define SPICR_CPHA (1 4)
+#define SPICR_CPOL (1 3)
+#define SPICR_MASTER_MODE (1 2)
+#define SPICR_SPE (1 1)
+#define SPICR_LOOP (1 0)
+
+/* SPI Status Register (spisr), [1] p11, [2] p10 */
+#define SPISR_SLAVE_MODE_SELECT(1 5)
+#define SPISR_MODF (1 4)
+#define SPISR_TX_FULL (1 3)
+#define SPISR_TX_EMPTY (1 2)
+#define SPISR_RX_FULL (1 1)
+#define SPISR_RX_EMPTY (1 0)
+
+/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
+#define SPIDTR_8BIT_MASK (0xff 0)
+#define SPIDTR_16BIT_MASK (0x 0)
+#define SPIDTR_32BIT_MASK (0x 0)
+
+/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
+#define SPIDRR_8BIT_MASK (0xff 0)
+#define SPIDRR_16BIT_MASK (0x 0)
+#define SPIDRR_32BIT_MASK (0x 0)
+
+/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
+#define SPISSR_MASK(cs)(1 (cs))
+#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
+#define SPISSR_OFF ~0UL
+
+/* SPI Transmit FIFO Occupancy Register (spitfor), [1] p13, [2] p14 */
+#define SPITFOR_OCYVAL_POS 0
+#define SPITFOR_OCYVAL_MASK(0xf SPITFOR_OCYVAL_POS)
+
+/* SPI Receive FIFO Occupancy Register (spirfor), [1] p14, [2] p14 */
+#define SPIRFOR_OCYVAL_POS 0
+#define SPIRFOR_OCYVAL_MASK(0xf SPIRFOR_OCYVAL_POS)
+
+/* SPI Software Reset Register (ssr) */
+#define SPISSR_RESET_VALUE 0x0a
+
+struct xilinx_spi_slave {
+ struct spi_slave slave;
+ struct xilinx_spi_reg *regs;
+ unsigned int freq;
+ unsigned int mode;
+};
+
+static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
+ struct spi_slave *slave)
+{
+ return container_of(slave, struct xilinx_spi_slave, slave);
+}
#ifndef CONFIG_SYS_XILINX_SPI_LIST
[U-Boot] [U-Boot PATCH 7/8] spi: davinci_spi: Move header code to driver
Move the header code into driver for more readable and
easy to access it.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Rex Chang rch...@ti.com
Cc: Murali Karicheri m-kariche...@ti.com
---
drivers/spi/davinci_spi.c | 110 -
drivers/spi/davinci_spi.h | 121 --
2 files changed, 109 insertions(+), 122 deletions(-)
delete mode 100644 drivers/spi/davinci_spi.h
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index bf18362..e0ecf99 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -13,7 +13,115 @@
#include malloc.h
#include asm/io.h
#include asm/arch/hardware.h
-#include davinci_spi.h
+
+struct davinci_spi_regs {
+ dv_reg gcr0; /* 0x00 */
+ dv_reg gcr1; /* 0x04 */
+ dv_reg int0; /* 0x08 */
+ dv_reg lvl;/* 0x0c */
+ dv_reg flg;/* 0x10 */
+ dv_reg pc0;/* 0x14 */
+ dv_reg pc1;/* 0x18 */
+ dv_reg pc2;/* 0x1c */
+ dv_reg pc3;/* 0x20 */
+ dv_reg pc4;/* 0x24 */
+ dv_reg pc5;/* 0x28 */
+ dv_reg rsvd[3];
+ dv_reg dat0; /* 0x38 */
+ dv_reg dat1; /* 0x3c */
+ dv_reg buf;/* 0x40 */
+ dv_reg emu;/* 0x44 */
+ dv_reg delay; /* 0x48 */
+ dv_reg def;/* 0x4c */
+ dv_reg fmt0; /* 0x50 */
+ dv_reg fmt1; /* 0x54 */
+ dv_reg fmt2; /* 0x58 */
+ dv_reg fmt3; /* 0x5c */
+ dv_reg intvec0;/* 0x60 */
+ dv_reg intvec1;/* 0x64 */
+};
+
+#define BIT(x) (1 (x))
+
+/* SPIGCR0 */
+#define SPIGCR0_SPIENA_MASK0x1
+#define SPIGCR0_SPIRST_MASK0x0
+
+/* SPIGCR0 */
+#define SPIGCR1_CLKMOD_MASKBIT(1)
+#define SPIGCR1_MASTER_MASKBIT(0)
+#define SPIGCR1_SPIENA_MASKBIT(24)
+
+/* SPIPC0 */
+#define SPIPC0_DIFUN_MASK BIT(11) /* SIMO */
+#define SPIPC0_DOFUN_MASK BIT(10) /* SOMI */
+#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
+#define SPIPC0_EN0FUN_MASK BIT(0)
+
+/* SPIFMT0 */
+#define SPIFMT_SHIFTDIR_SHIFT 20
+#define SPIFMT_POLARITY_SHIFT 17
+#define SPIFMT_PHASE_SHIFT 16
+#define SPIFMT_PRESCALE_SHIFT 8
+
+/* SPIDAT1 */
+#define SPIDAT1_CSHOLD_SHIFT 28
+#define SPIDAT1_CSNR_SHIFT 16
+
+/* SPIDELAY */
+#define SPI_C2TDELAY_SHIFT 24
+#define SPI_T2CDELAY_SHIFT 16
+
+/* SPIBUF */
+#define SPIBUF_RXEMPTY_MASKBIT(31)
+#define SPIBUF_TXFULL_MASK BIT(29)
+
+/* SPIDEF */
+#define SPIDEF_CSDEF0_MASK BIT(0)
+
+#define SPI0_BUS 0
+#define SPI0_BASE CONFIG_SYS_SPI_BASE
+/*
+ * Define default SPI0_NUM_CS as 1 for existing platforms that uses this
+ * driver. Platform can configure number of CS using CONFIG_SYS_SPI0_NUM_CS
+ * if more than one CS is supported and by defining CONFIG_SYS_SPI0.
+ */
+#ifndef CONFIG_SYS_SPI0
+#define SPI0_NUM_CS1
+#else
+#define SPI0_NUM_CSCONFIG_SYS_SPI0_NUM_CS
+#endif
+
+/*
+ * define CONFIG_SYS_SPI1 when platform has spi-1 device (bus #1) and
+ * CONFIG_SYS_SPI1_NUM_CS defines number of CS on this bus
+ */
+#ifdef CONFIG_SYS_SPI1
+#define SPI1_BUS 1
+#define SPI1_NUM_CSCONFIG_SYS_SPI1_NUM_CS
+#define SPI1_BASE CONFIG_SYS_SPI1_BASE
+#endif
+
+/*
+ * define CONFIG_SYS_SPI2 when platform has spi-2 device (bus #2) and
+ * CONFIG_SYS_SPI2_NUM_CS defines number of CS on this bus
+ */
+#ifdef CONFIG_SYS_SPI2
+#define SPI2_BUS 2
+#define SPI2_NUM_CSCONFIG_SYS_SPI2_NUM_CS
+#define SPI2_BASE CONFIG_SYS_SPI2_BASE
+#endif
+
+struct davinci_spi_slave {
+ struct spi_slave slave;
+ struct davinci_spi_regs *regs;
+ unsigned int freq;
+};
+
+static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave)
+{
+ return container_of(slave, struct davinci_spi_slave, slave);
+}
void spi_init()
{
diff --git a/drivers/spi/davinci_spi.h b/drivers/spi/davinci_spi.h
deleted file mode 100644
index d4612d3..000
--- a/drivers/spi/davinci_spi.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
- *
- * Register definitions for the DaVinci SPI Controller
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-#ifndef _DAVINCI_SPI_H_
-#define _DAVINCI_SPI_H_
-
-struct davinci_spi_regs {
- dv_reg gcr0; /* 0x00 */
- dv_reg gcr1; /* 0x04 */
- dv_reg int0; /* 0x08 */
- dv_reg lvl;/* 0x0c */
- dv_reg flg;/* 0x10 */
- dv_reg pc0;/* 0x14 */
- dv_reg pc1;/* 0x18 */
- dv_reg pc2;/* 0x1c */
- dv_reg pc3;/* 0x20
[U-Boot] [U-Boot PATCH 0/8] spi: Driver cleanup series
Driver cleanup series list - Minor code cleanups - tab space, comments etc - Zapping unneeded drivers - Moving header code into driver .c files for easy accessing - Arranged the driver code format to [1] for more readable [1] http://lists.denx.de/pipermail/u-boot/2013-August/160473.html thanks! -- Jagan. Jagannadha Sutradharudu Teki (8): sf: Adjust tab space's spi: Zap andes_spi driver spi: Zap ftssp010_spi driver spi: Zap oc_tiny_spi driver spi: xilinx_spi: Move header code to driver spi: xilinx_spi: Driver clean-up spi: davinci_spi: Move header code to driver spi: davinci_spi: Driver cleanup drivers/mtd/spi/sf_internal.h | 20 +- drivers/spi/Makefile | 3 - drivers/spi/andes_spi.c | 284 drivers/spi/andes_spi.h | 115 -- drivers/spi/davinci_spi.c | 369 --- drivers/spi/davinci_spi.h | 121 -- drivers/spi/ftssp010_spi.c| 498 -- drivers/spi/oc_tiny_spi.c | 245 - drivers/spi/xilinx_spi.c | 153 + drivers/spi/xilinx_spi.h | 138 include/spi.h | 12 +- include/spi_flash.h | 8 +- 12 files changed, 367 insertions(+), 1599 deletions(-) delete mode 100644 drivers/spi/andes_spi.c delete mode 100644 drivers/spi/andes_spi.h delete mode 100644 drivers/spi/davinci_spi.h delete mode 100644 drivers/spi/ftssp010_spi.c delete mode 100644 drivers/spi/oc_tiny_spi.c delete mode 100644 drivers/spi/xilinx_spi.h -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [U-Boot PATCH 1/8] sf: Adjust tab space's
Tab space's got adjusted on relevent files.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 20 ++--
include/spi.h | 12 ++--
include/spi_flash.h | 8
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a9..58007de 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -31,9 +31,9 @@ enum spi_read_cmds {
};
/* Normal - Extended - Full command set */
-#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
-#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
-#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
+#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
enum {
@@ -67,12 +67,12 @@ enum {
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS0x05
+#define CMD_READ_STATUS0x05
#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG0x35
-#define CMD_FLAG_STATUS0x70
+#define CMD_READ_CONFIG0x35
+#define CMD_FLAG_STATUS0x70
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -94,7 +94,7 @@ enum {
/* Common status */
#define STATUS_WIP (1 0)
#define STATUS_QEB_WINSPAN (1 1)
-#define STATUS_QEB_MXIC(1 6)
+#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
@@ -103,13 +103,13 @@ enum {
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
# define CMD_SST_BP0x02/* Byte Program */
-# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word Program */
+# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word
Program */
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
@@ -124,7 +124,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset,
size_t len,
* @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
* @ext_jedec: Device ext_jedec ID
* @sector_size: Sector size of this device
- * @nr_sectors:No.of sectors on this device
+ * @nr_sectors:No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
* @flags: Important param, for flash specific behaviour
*/
diff --git a/include/spi.h b/include/spi.h
index 7829063..44abe68 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,7 +30,7 @@
#define SPI_XFER_MMAP 0x08/* Memory Mapped start */
#define SPI_XFER_MMAP_END 0x10/* Memory Mapped End */
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE(1 5)
+#define SPI_XFER_U_PAGE (1 5)
/* SPI TX operation modes */
#define SPI_OPM_TX_QPP (1 0)
@@ -43,18 +43,18 @@
#define SPI_OPM_RX_DIO (1 3)
#define SPI_OPM_RX_QOF (1 4)
#define SPI_OPM_RX_QIOF(1 5)
-#define SPI_OPM_RX_EXTN(SPI_OPM_RX_AS | SPI_OPM_RX_AF |
SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
- SPI_OPM_RX_QIOF)
+#define SPI_OPM_RX_EXTN(SPI_OPM_RX_AS | SPI_OPM_RX_AF | \
+ SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO | \
+ SPI_OPM_RX_QOF | SPI_OPM_RX_QIOF)
/* SPI bus connection options - see enum spi_dual_flash */
#define SPI_CONN_DUAL_SHARED (1 0)
-#define SPI_CONN_DUAL_SEPARATED(1 1)
+#define SPI_CONN_DUAL_SEPARATED (1 1)
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
-#define SPI_DEFAULT_WORDLEN 8
+#define SPI_DEFAULT_WORDLEN 8
#ifdef CONFIG_DM_SPI
/* TODO(s...@chromium.org): Remove this and use max_hz from struct spi_slave */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 4791b94..481b4dd 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -38,12 +38,12 @@ struct spi_slave;
*
* @spi: SPI slave
* @name: Name of SPI flash
- * @dual_flash:Indicates dual flash
[U-Boot] [PATCH] sf: Adjust tab space's
Tab space's got adjusted on relevent files.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 20 ++--
include/spi.h | 12 ++--
include/spi_flash.h | 6 +++---
3 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a9..58007de 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -31,9 +31,9 @@ enum spi_read_cmds {
};
/* Normal - Extended - Full command set */
-#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
-#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
-#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
+#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
enum {
@@ -67,12 +67,12 @@ enum {
#define CMD_WRITE_STATUS 0x01
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
-#define CMD_READ_STATUS0x05
+#define CMD_READ_STATUS0x05
#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
-#define CMD_READ_CONFIG0x35
-#define CMD_FLAG_STATUS0x70
+#define CMD_READ_CONFIG0x35
+#define CMD_FLAG_STATUS0x70
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -94,7 +94,7 @@ enum {
/* Common status */
#define STATUS_WIP (1 0)
#define STATUS_QEB_WINSPAN (1 1)
-#define STATUS_QEB_MXIC(1 6)
+#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
@@ -103,13 +103,13 @@ enum {
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
# define CMD_SST_BP0x02/* Byte Program */
-# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word Program */
+# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word
Program */
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
@@ -124,7 +124,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset,
size_t len,
* @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
* @ext_jedec: Device ext_jedec ID
* @sector_size: Sector size of this device
- * @nr_sectors:No.of sectors on this device
+ * @nr_sectors:No.of sectors on this device
* @e_rd_cmd: Enum list for read commands
* @flags: Important param, for flash specific behaviour
*/
diff --git a/include/spi.h b/include/spi.h
index 7829063..44abe68 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,7 +30,7 @@
#define SPI_XFER_MMAP 0x08/* Memory Mapped start */
#define SPI_XFER_MMAP_END 0x10/* Memory Mapped End */
#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
-#define SPI_XFER_U_PAGE(1 5)
+#define SPI_XFER_U_PAGE (1 5)
/* SPI TX operation modes */
#define SPI_OPM_TX_QPP (1 0)
@@ -43,18 +43,18 @@
#define SPI_OPM_RX_DIO (1 3)
#define SPI_OPM_RX_QOF (1 4)
#define SPI_OPM_RX_QIOF(1 5)
-#define SPI_OPM_RX_EXTN(SPI_OPM_RX_AS | SPI_OPM_RX_AF |
SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
- SPI_OPM_RX_QIOF)
+#define SPI_OPM_RX_EXTN(SPI_OPM_RX_AS | SPI_OPM_RX_AF | \
+ SPI_OPM_RX_DOUT | SPI_OPM_RX_DIO | \
+ SPI_OPM_RX_QOF | SPI_OPM_RX_QIOF)
/* SPI bus connection options - see enum spi_dual_flash */
#define SPI_CONN_DUAL_SHARED (1 0)
-#define SPI_CONN_DUAL_SEPARATED(1 1)
+#define SPI_CONN_DUAL_SEPARATED (1 1)
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
-#define SPI_DEFAULT_WORDLEN 8
+#define SPI_DEFAULT_WORDLEN 8
#ifdef CONFIG_DM_SPI
/* TODO(s...@chromium.org): Remove this and use max_hz from struct spi_slave */
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 03f8306..481b4dd 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -43,7 +43,7 @@ struct spi_slave;
* @size: Total flash size
* @page_size: Write (page) size
* @sector_size: Sector size
- * @erase_size
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 662e2acb46250881ec26bc8366fc9eb1856cb7c2: sunxi: UTOO_P66: Add missing MAINTAINERS entry (2015-03-29 14:56:48 +0200) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 52091ad146d766cdc5ccd65430b2a4e5cb7aec32: spi: designware_spi: revisit FIFO size detection again (2015-03-30 01:42:49 +0530) Axel Lin (6): spi: cf_qspi: Fixup to_cf_qspi_slave macro spi: davinci: Remove duplicate code to set bus and cs for slave spi: ftssp010_spi: Use to_ftssp010_spi() to ensure free correct address spi: cf_spi: Use to_cf_spi_slave to resolve cfslave from slave spi: cf_spi: Staticize local functions spi: designware_spi: revisit FIFO size detection again Ravi Babu (1): qspi: dra7x: enable quad mode read for ti-qspi driver drivers/spi/cf_qspi.c| 2 +- drivers/spi/cf_spi.c | 31 --- drivers/spi/davinci_spi.c| 3 --- drivers/spi/designware_spi.c | 4 ++-- drivers/spi/ftssp010_spi.c | 4 +++- drivers/spi/ti_qspi.c| 7 +++ include/configs/dra7xx_evm.h | 1 + 7 files changed, 30 insertions(+), 22 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit d622ac39274a949b6445f1bfd92dc1644014388b: powerpc: mpc824x: remove MPC824X cpu support (2015-01-05 12:08:55 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to adc0fabfd9662fa690e866332cd4277351f991c4: imx:mx6sxsabresd support qspi AHB read (2015-01-09 00:03:28 +0530) Axel Lin (3): spi: designware_spi: Fix detecting FIFO depth spi: cadence_qspi: Fix checking return value of fdt_first_subnode() spi: ftssp010_spi: Simplify code flow in ftssp010_[wait|wait_tx|wait_rx] Marek Vasut (2): dt: socfpga: Rename snps, dw-spi-mmio to snps, dw-apb-ssi dt: socfpga: Replace num-chipselect with num-cs Peng Fan (4): spi:fsl-quadspi support bank register read write mx6sxsabresd: support qspi flash bigger than 16MB qspi:fsl implement AHB read imx:mx6sxsabresd support qspi AHB read arch/arm/dts/socfpga.dtsi | 10 +- drivers/spi/cadence_qspi.c | 2 +- drivers/spi/designware_spi.c | 6 +- drivers/spi/fsl_qspi.c | 297 + drivers/spi/fsl_qspi.h | 15 +++ drivers/spi/ftssp010_spi.c | 36 ++--- include/configs/mx6sxsabresd.h | 8 ++ 7 files changed, 316 insertions(+), 58 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit babe6994ca28e5a354ee32b33b7a54b0276d9df1: sf: sf_params: Add S25FL164K flash identifier info (2014-12-18 18:48:30 +0530) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to be2fde60b0de7723d29035ba952a970d9e1ca94d: imx:mx6slevk add spi nor boot support (2014-12-31 14:54:01 +0530) Peng Fan (6): QuadSPI: use QSPI_CMD_xx instead of flash opcodes QuadSPI: use correct amba_base arm:mx6sx add QSPI support imx:qspi add 4K erase support imx:mx6sxsabresd add qspi support imx:mx6slevk add spi nor boot support arch/arm/cpu/armv7/mx6/clock.c | 50 ++ arch/arm/include/asm/arch-mx6/clock.h | 1 + arch/arm/include/asm/arch-mx6/imx-regs.h| 12 +-- board/freescale/mx6slevk/MAINTAINERS| 1 + board/freescale/mx6sxsabresd/mx6sxsabresd.c | 40 configs/mx6slevk_spinor_defconfig | 3 + drivers/spi/fsl_qspi.c | 137 +++- include/configs/mx6slevk.h | 13 ++- include/configs/mx6sxsabresd.h | 12 +++ 9 files changed, 221 insertions(+), 48 deletions(-) create mode 100644 configs/mx6slevk_spinor_defconfig ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit e3bf81b1e841ecabe7c8b3d48621256db8b8623e: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2014-12-16 15:20:02 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to babe6994ca28e5a354ee32b33b7a54b0276d9df1: sf: sf_params: Add S25FL164K flash identifier info (2014-12-18 18:48:30 +0530) Adnan Ali (2): sf: sf_params: Add S25FL116K flash support sf: sf_params: Add S25FL164K flash identifier info Jagannadha Sutradharudu Teki (1): mtd: sf: Zap ramtron driver Shengzhou Liu (1): mtd/spi: Add support for SST25WF040B drivers/mtd/spi/Makefile| 1 - drivers/mtd/spi/ramtron.c | 404 drivers/mtd/spi/sf_params.c | 3 + 3 files changed, 3 insertions(+), 405 deletions(-) delete mode 100644 drivers/mtd/spi/ramtron.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Revert spi: add config option to enable the WP pin function on st micron flashes
This reverts commit 562f8df18da62ae02c4ace1e530451fe82c3312d.
Never see the issue with N25Q128 flash without need of W#/Vpp signal
during probe.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Heiko Schocher h...@denx.de
---
README| 11 ---
drivers/mtd/spi/sf_internal.h | 4
drivers/mtd/spi/sf_probe.c| 30 --
3 files changed, 45 deletions(-)
diff --git a/README b/README
index 4ca04d0..908646f 100644
--- a/README
+++ b/README
@@ -3090,17 +3090,6 @@ CBFS (Coreboot Filesystem) support
memories can be connected with a given cs line.
currently Xilinx Zynq qspi support these type of connections.
- CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
- enable the W#/Vpp signal to disable writing to the status
- register on ST MICRON flashes like the N25Q128.
- The status register write enable/disable bit, combined with
- the W#/VPP signal provides hardware data protection for the
- device as follows: When the enable/disable bit is set to 1,
- and the W#/VPP signal is driven LOW, the status register
- nonvolatile bits become read-only and the WRITE STATUS REGISTER
- operation will not execute. The only way to exit this
- hardware-protected mode is to drive W#/VPP HIGH.
-
- SystemACE Support:
CONFIG_SYSTEMACE
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 785f7a9..bd834dc 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -97,10 +97,6 @@ enum {
#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC (1 7)
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-#define STATUS_SRWD(1 7) /* SR write protect */
-#endif
-
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index ce9987f..3b0e652 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -287,34 +287,6 @@ int spi_flash_decode_fdt(const void *blob, struct
spi_flash *flash)
}
#endif /* CONFIG_OF_CONTROL */
-#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
-/* enable the W#/Vpp signal to disable writing to the status register */
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- u8 status;
- int ret;
-
- ret = spi_flash_cmd_read_status(flash, status);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_status(flash, STATUS_SRWD);
- if (ret 0)
- return ret;
-
- ret = spi_flash_cmd_write_disable(flash);
- if (ret 0)
- return ret;
-
- return 0;
-}
-#else
-static int spi_enable_wp_pin(struct spi_flash *flash)
-{
- return 0;
-}
-#endif
-
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
@@ -393,8 +365,6 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct
spi_flash *flash)
puts( Full access #define CONFIG_SPI_FLASH_BAR\n);
}
#endif
- if (spi_enable_wp_pin(flash))
- puts(Enable WP pin failed\n);
/* Release spi bus */
spi_release_bus(spi);
--
1.9.1
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 0/6] sf: SST changes, Byte program
This patch-set added byte program support for sst flashes and some implementation changes in sf to support array slow and byte program specific controllers. Changes for v2: - commit message fixes Bin Meng (3): spi: sf: Support byte program for sst spi flash x86: ich-spi: Set the rx operation mode for ich 7 x86: ich-spi: Set the tx operation mode for ich 7 Jagannadha Sutradharudu Teki (2): sf: Fix look for the fastest read command sf: Enable byte program support Simon Glass (1): spi: Fix flag collision for SST_WP drivers/mtd/spi/sf_internal.h | 22 ++--- drivers/mtd/spi/sf_ops.c | 31 + drivers/mtd/spi/sf_params.c | 102 +- drivers/mtd/spi/sf_probe.c| 9 +++- drivers/spi/ich.c | 9 include/spi.h | 1 + 6 files changed, 114 insertions(+), 60 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/6] sf: Fix look for the fastest read command
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Tested-by: Bin Meng bmeng...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 13 +++---
drivers/mtd/spi/sf_params.c | 102 +-
drivers/mtd/spi/sf_probe.c| 1 +
3 files changed, 60 insertions(+), 56 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 5b7670c..e159f04 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -23,13 +23,16 @@ enum spi_dual_flash {
/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = 1 0,
- DUAL_OUTPUT_FAST= 1 1,
- DUAL_IO_FAST= 1 2,
- QUAD_OUTPUT_FAST= 1 3,
- QUAD_IO_FAST= 1 4,
+ ARRAY_FAST = 1 1,
+ DUAL_OUTPUT_FAST= 1 2,
+ DUAL_IO_FAST= 1 3,
+ QUAD_OUTPUT_FAST= 1 4,
+ QUAD_IO_FAST= 1 5,
};
-#define RD_EXTN(ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+/* Normal - Extended - Full command set */
+#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 61545ca..0f1f837 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -15,42 +15,42 @@
/* SPI/QSPI flash device params structure */
const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, 0,
SECT_4K},
- {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, 0,
SECT_4K},
- {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, 0,
SECT_4K},
- {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, 0,
SECT_4K},
- {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
- {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, 0,
0},
- {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, 0,
0},
- {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, 0,
0},
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, RD_NORM,
0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM,
0},
+ {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, RD_NORM,
0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {MX25L2006E, 0xc22012, 0x0, 64 * 1024, 4, 0,
0
[U-Boot] [PATCH v2 2/6] spi: Fix flag collision for SST_WP
From: Simon Glass s...@chromium.org
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann jens.rottm...@adlinktech.com
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index e159f04..7218e69 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -41,6 +41,7 @@ enum {
SECT_32K= 1 1,
E_FSR = 1 2,
WR_QPP = 1 3,
+ SST_WP = 1 4,
};
#define SPI_FLASH_3B_ADDR_LEN 3
@@ -104,7 +105,6 @@ enum {
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP0x01/* Supports AAI word program */
# define CMD_SST_BP0x02/* Byte Program */
# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word Program */
--
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[U-Boot] [PATCH v2 6/6] x86: ich-spi: Set the tx operation mode for ich 7
From: Bin Meng bmeng...@gmail.com
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.
Signed-off-by: Bin Meng bmeng...@gmail.com
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/spi/ich.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index 0ef8bd4..d5cea39 100644
--- a/drivers/spi/ich.c
+++ b/drivers/spi/ich.c
@@ -141,9 +141,14 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
ich-slave.max_write_size = ctlr.databytes;
ich-speed = max_hz;
- /* ICH 7 SPI controller only supports array read command */
- if (ctlr.ich_version == 7)
+ /*
+* ICH 7 SPI controller only supports array read command
+* and byte program command for SST flash
+*/
+ if (ctlr.ich_version == 7) {
ich-slave.op_mode_rx = SPI_OPM_RX_AS;
+ ich-slave.op_mode_tx = SPI_OPM_TX_BP;
+ }
return ich-slave;
}
--
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[U-Boot] [PATCH v2 4/6] sf: Enable byte program support
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.
A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Tested-by: Bin Meng bmeng...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 5 -
drivers/mtd/spi/sf_params.c | 18 +-
drivers/mtd/spi/sf_probe.c| 8 ++--
include/spi.h | 1 +
4 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index fb53cb0..785f7a9 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -40,10 +40,13 @@ enum {
SECT_4K = 1 0,
SECT_32K= 1 1,
E_FSR = 1 2,
- WR_QPP = 1 3,
+ SST_BP = 1 3,
SST_WP = 1 4,
+ WR_QPP = 1 5,
};
+#define SST_WR (SST_BP | SST_WP)
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 0f1f837..30875b3 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -89,16 +89,16 @@ const struct spi_flash_params spi_flash_params_table[] = {
{N25Q1024A, 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL,
WR_QPP | E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST/* SST */
- {SST25VF040B,0xbf258d, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF080B,0xbf258e, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF016B,0xbf2541, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF032B,0xbf254a, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K | SST_WP},
+ {SST25VF040B,0xbf258d, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF080B,0xbf258e, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF016B,0xbf2541, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF032B,0xbf254a, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K | SST_WR},
{SST25VF064C,0xbf254b, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
- {SST25WF512, 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF010, 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF020, 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF040, 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF080, 0xbf2505, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WP},
+ {SST25WF512, 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF010, 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF020, 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF040, 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF080, 0xbf2505, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WR},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND/* WINBOND */
{W25P80, 0xef2014, 0x0, 64 * 1024,16, RD_NORM,
0},
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 7cde4c0..ce9987f 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -136,8 +136,12 @@ static int spi_flash_validate_params(struct spi_slave
*spi, u8 *idcode,
#ifndef CONFIG_DM_SPI_FLASH
flash-write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
- if (params-flags SST_WP)
- flash-write = sst_write_wp;
+ if (params-flags SST_WR) {
+ if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
+ flash-write = sst_write_bp;
+ else
+ flash-write = sst_write_wp;
+ }
#endif
flash-erase = spi_flash_cmd_erase_ops;
flash-read = spi_flash_cmd_read_ops;
diff --git a/include/spi.h b/include/spi.h
index 5b78271..ec17bd0 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -34,6 +34,7 @@
/* SPI TX operation modes */
#define SPI_OPM_TX_QPP (1 0)
+#define SPI_OPM_TX_BP (1 1)
/* SPI RX operation modes */
#define SPI_OPM_RX_AS (1 0)
--
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[U-Boot] [PATCH v2 3/6] spi: sf: Support byte program for sst spi flash
From: Bin Meng bmeng...@gmail.com
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 31 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7218e69..fb53cb0 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -110,6 +110,8 @@ enum {
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf);
#endif
/**
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 759231f..34bc54e 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -517,4 +517,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset,
size_t len,
spi_release_bus(flash-spi);
return ret;
}
+
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf)
+{
+ size_t actual;
+ int ret;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: Unable to claim SPI bus\n);
+ return ret;
+ }
+
+ for (actual = 0; actual len; actual++) {
+ ret = sst_byte_write(flash, offset, buf + actual);
+ if (ret) {
+ debug(SF: sst byte program failed\n);
+ break;
+ }
+ offset++;
+ }
+
+ if (!ret)
+ ret = spi_flash_cmd_write_disable(flash);
+
+ debug(SF: sst: program %s %zu bytes @ 0x%zx\n,
+ ret ? failure : success, len, offset - actual);
+
+ spi_release_bus(flash-spi);
+ return ret;
+}
#endif
--
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[U-Boot] [PATCH v2 5/6] x86: ich-spi: Set the rx operation mode for ich 7
From: Bin Meng bmeng...@gmail.com ICH 7 SPI controller only supports array read command (03h). Fast array read command (0Bh) is not supported. Signed-off-by: Bin Meng bmeng...@gmail.com Acked-by: Simon Glass s...@chromium.org Tested-by: Simon Glass s...@chromium.org Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com --- drivers/spi/ich.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index f5c6f3e..0ef8bd4 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -141,6 +141,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ich-slave.max_write_size = ctlr.databytes; ich-speed = max_hz; + /* ICH 7 SPI controller only supports array read command */ + if (ctlr.ich_version == 7) + ich-slave.op_mode_rx = SPI_OPM_RX_AS; + return ich-slave; } -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] sf: SST changes, Byte program
This patch-set added byte program support for sst flashes and some implementation changes in sf to support array slow and byte program specific controllers. Bin Meng (1): spi: sf: Support byte program for sst spi flash Jagannadha Sutradharudu Teki (2): sf: Fix look for the fastest read command sf: Enable byte program support Simon Glass (1): spi: Fix flag collision for SST_WP drivers/mtd/spi/sf_internal.h | 22 ++--- drivers/mtd/spi/sf_ops.c | 31 + drivers/mtd/spi/sf_params.c | 102 +- drivers/mtd/spi/sf_probe.c| 9 +++- include/spi.h | 1 + 5 files changed, 105 insertions(+), 60 deletions(-) -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] spi: Fix flag collision for SST_WP
From: Simon Glass s...@chromium.org
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.
Reported-by: Jens Rottmann jens.rottm...@adlinktech.com
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index e159f04..7218e69 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -41,6 +41,7 @@ enum {
SECT_32K= 1 1,
E_FSR = 1 2,
WR_QPP = 1 3,
+ SST_WP = 1 4,
};
#define SPI_FLASH_3B_ADDR_LEN 3
@@ -104,7 +105,6 @@ enum {
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
-# define SST_WP0x01/* Supports AAI word program */
# define CMD_SST_BP0x02/* Byte Program */
# define CMD_SST_AAI_WP0xAD/* Auto Address Incr Word Program */
--
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[U-Boot] [PATCH 4/4] sf: Enable byte program support
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch
gives a rx transfer flag to set the BP so-that sf
will operate on byte program transfer.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 5 -
drivers/mtd/spi/sf_params.c | 18 +-
drivers/mtd/spi/sf_probe.c| 8 ++--
include/spi.h | 1 +
4 files changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index fb53cb0..785f7a9 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -40,10 +40,13 @@ enum {
SECT_4K = 1 0,
SECT_32K= 1 1,
E_FSR = 1 2,
- WR_QPP = 1 3,
+ SST_BP = 1 3,
SST_WP = 1 4,
+ WR_QPP = 1 5,
};
+#define SST_WR (SST_BP | SST_WP)
+
#define SPI_FLASH_3B_ADDR_LEN 3
#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 0f1f837..30875b3 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -89,16 +89,16 @@ const struct spi_flash_params spi_flash_params_table[] = {
{N25Q1024A, 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL,
WR_QPP | E_FSR | SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_SST/* SST */
- {SST25VF040B,0xbf258d, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF080B,0xbf258e, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF016B,0xbf2541, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K | SST_WP},
- {SST25VF032B,0xbf254a, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K | SST_WP},
+ {SST25VF040B,0xbf258d, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF080B,0xbf258e, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF016B,0xbf2541, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K | SST_WR},
+ {SST25VF032B,0xbf254a, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K | SST_WR},
{SST25VF064C,0xbf254b, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
- {SST25WF512, 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF010, 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF020, 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF040, 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WP},
- {SST25WF080, 0xbf2505, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WP},
+ {SST25WF512, 0xbf2501, 0x0, 64 * 1024, 1, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF010, 0xbf2502, 0x0, 64 * 1024, 2, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF020, 0xbf2503, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF040, 0xbf2504, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K | SST_WR},
+ {SST25WF080, 0xbf2505, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K | SST_WR},
#endif
#ifdef CONFIG_SPI_FLASH_WINBOND/* WINBOND */
{W25P80, 0xef2014, 0x0, 64 * 1024,16, RD_NORM,
0},
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 7cde4c0..ce9987f 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -136,8 +136,12 @@ static int spi_flash_validate_params(struct spi_slave
*spi, u8 *idcode,
#ifndef CONFIG_DM_SPI_FLASH
flash-write = spi_flash_cmd_write_ops;
#if defined(CONFIG_SPI_FLASH_SST)
- if (params-flags SST_WP)
- flash-write = sst_write_wp;
+ if (params-flags SST_WR) {
+ if (flash-spi-op_mode_tx SPI_OPM_TX_BP)
+ flash-write = sst_write_bp;
+ else
+ flash-write = sst_write_wp;
+ }
#endif
flash-erase = spi_flash_cmd_erase_ops;
flash-read = spi_flash_cmd_read_ops;
diff --git a/include/spi.h b/include/spi.h
index 5b78271..ec17bd0 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -34,6 +34,7 @@
/* SPI TX operation modes */
#define SPI_OPM_TX_QPP (1 0)
+#define SPI_OPM_TX_BP (1 1)
/* SPI RX operation modes */
#define SPI_OPM_RX_AS (1 0)
--
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[U-Boot] [PATCH 1/4] sf: Fix look for the fastest read command
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.
So this fix on sf will correctly handle the slow read supported
controllers.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
drivers/mtd/spi/sf_internal.h | 13 +++---
drivers/mtd/spi/sf_params.c | 102 +-
drivers/mtd/spi/sf_probe.c| 1 +
3 files changed, 60 insertions(+), 56 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 5b7670c..e159f04 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -23,13 +23,16 @@ enum spi_dual_flash {
/* Enum list - Full read commands */
enum spi_read_cmds {
ARRAY_SLOW = 1 0,
- DUAL_OUTPUT_FAST= 1 1,
- DUAL_IO_FAST= 1 2,
- QUAD_OUTPUT_FAST= 1 3,
- QUAD_IO_FAST= 1 4,
+ ARRAY_FAST = 1 1,
+ DUAL_OUTPUT_FAST= 1 2,
+ DUAL_IO_FAST= 1 3,
+ QUAD_OUTPUT_FAST= 1 4,
+ QUAD_IO_FAST= 1 5,
};
-#define RD_EXTN(ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
+/* Normal - Extended - Full command set */
+#define RD_NORM(ARRAY_SLOW | ARRAY_FAST)
+#define RD_EXTN(RD_NORM | DUAL_OUTPUT_FAST | DUAL_IO_FAST)
#define RD_FULL(RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST)
/* sf param flags */
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 61545ca..0f1f837 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -15,42 +15,42 @@
/* SPI/QSPI flash device params structure */
const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, 0,
SECT_4K},
- {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, 0,
SECT_4K},
- {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, 0,
SECT_4K},
- {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, 0,
SECT_4K},
- {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, RD_NORM,
SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, RD_NORM,
SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, RD_NORM,
SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, RD_NORM,
SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
- {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, 0,
0},
- {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, 0,
0},
- {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, 0,
0},
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, RD_NORM,
0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, RD_NORM,
0},
+ {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, RD_NORM,
0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, RD_NORM,
SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, RD_NORM,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
- {MX25L2006E, 0xc22012, 0x0, 64 * 1024, 4, 0,
0},
- {MX25L4005, 0xc22013, 0x0
[U-Boot] [PATCH 3/4] spi: sf: Support byte program for sst spi flash
From: Bin Meng bmeng...@gmail.com
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.
A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
Tested-by: Simon Glass s...@chromium.org
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 31 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7218e69..fb53cb0 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -110,6 +110,8 @@ enum {
int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
const void *buf);
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf);
#endif
/**
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 759231f..34bc54e 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -517,4 +517,35 @@ int sst_write_wp(struct spi_flash *flash, u32 offset,
size_t len,
spi_release_bus(flash-spi);
return ret;
}
+
+int sst_write_bp(struct spi_flash *flash, u32 offset, size_t len,
+ const void *buf)
+{
+ size_t actual;
+ int ret;
+
+ ret = spi_claim_bus(flash-spi);
+ if (ret) {
+ debug(SF: Unable to claim SPI bus\n);
+ return ret;
+ }
+
+ for (actual = 0; actual len; actual++) {
+ ret = sst_byte_write(flash, offset, buf + actual);
+ if (ret) {
+ debug(SF: sst byte program failed\n);
+ break;
+ }
+ offset++;
+ }
+
+ if (!ret)
+ ret = spi_flash_cmd_write_disable(flash);
+
+ debug(SF: sst: program %s %zu bytes @ 0x%zx\n,
+ ret ? failure : success, len, offset - actual);
+
+ spi_release_bus(flash-spi);
+ return ret;
+}
#endif
--
1.9.1
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC PATCH] sf: New SF-NOR framework
This is long lasting work that I did last few months back,
I'm sure it's where much need now.
- spi driver: drivers/spi/fsl_qspi.c
- flash attributes in spi_slave {} and
- etc ...
making spi subsystem becomes more flash specific rather operating
as a generic spi bus. So SF-NOR divides normal spi flash operations
through generic SPI API's(sf_spi.c) and more spi flash(sf) specific
operations through SF NOR API's.
So the controllers those are operating more on flash needs to
write a driver on drivers/mtd/spi/ example fsl_qspi.c
I have not tested more accuratly as of now, will come back again
with new feature additions/removal, zynq_qspi additions and more...
Note: dm-spi ops can gets effected with this new framework
{ .ops= spi_flash_std_ops, } and will fix that in next
version patches.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
doc/SPI/README.sf-nor | 51 ++
drivers/mtd/spi/Makefile | 4 +-
drivers/mtd/spi/sf_core.c | 389 ++
drivers/mtd/spi/sf_core.h | 263 +++
drivers/mtd/spi/sf_ops.c | 147 +++---
drivers/mtd/spi/sf_spi.c | 230 +++
include/spi_flash.h | 15 +-
7 files changed, 996 insertions(+), 103 deletions(-)
create mode 100644 doc/SPI/README.sf-nor
create mode 100644 drivers/mtd/spi/sf_core.c
create mode 100644 drivers/mtd/spi/sf_core.h
create mode 100644 drivers/mtd/spi/sf_spi.c
diff --git a/doc/SPI/README.sf-nor b/doc/SPI/README.sf-nor
new file mode 100644
index 000..ded60f1
--- /dev/null
+++ b/doc/SPI/README.sf-nor
@@ -0,0 +1,51 @@
+SF-NOR framework:
+
+
+1. Introduction
+
+Due to vast increasing of new spi flash features and operations the current
+serial flash framework in u-boot is difficult to manage the relation between
+spi bus vs spi flash(one of the connected slave). All newly added features
+are effecting spi_slave {} to become flash specific rather than generic spi
bus.
+
+So there is a new framework that divides normal flash operations through
generic
+SPI API's and more spi flash(sf) specific operations through SF NOR API's.
+
+This division of operations are taken care by new framework called sf-nor.
+
+2. SF NOR
+
+___
+ | |
+ |cmd_sf.c |
+ |___|
+ |
+ |
+___V___
+ | |
+ | spi_flash.h |
+ |___|
+ |
+ |
+ _V_
+ | |
+ |sf_core|
+ |(sf_core.c)|
+ |___|
+| |
+| |
+V |
+ | ||
+ | sf_spi.c||
+ |_||
+| |
+| |
+V V
+ drivers/spi/*drivers/mtd/spi/zynq_qspi.c
+
+common/cmd_sf.c: spi flash command interface
+include/spi_flash.h: spi flash api interface
+drivers/mtd/spi/sf_core.c: SF Core
+drivers/mtd/spi/sf_spi.c: sf emulation for all drivers/spi/*
+drivers/spi: spi drivers
+drivers/mtd/spi/zynq_qspi.c: zynq qspi controller driver
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 15789a0..2ddeadf 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -13,9 +13,9 @@ obj-$(CONFIG_SPL_SPI_BOOT)+= fsl_espi_spl.o
endif
#ifndef CONFIG_DM_SPI
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o
+obj-$(CONFIG_SPI_FLASH) += sf_core.o
#endif
-obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_CMD_SF) += sf_spi.o
obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_core.c b/drivers/mtd/spi/sf_core.c
new file mode 100644
index 000..dcc78a7
--- /dev/null
+++ b/drivers/mtd/spi/sf_core.c
@@ -0,0 +1,389 @@
+/*
+ * SPI flash probing
+ *
+ * Copyright (C) 2008 Atmel Corporation
+ * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include dm.h
+#include errno.h
+#include fdtdec.h
+#include malloc.h
+#include spi.h
+#include spi_flash.h
+#include asm/io.h
+
+#include sf_core.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Read commands array */
+static u8 spi_read_cmds_array[] = {
+ CMD_READ_ARRAY_SLOW,
+ CMD_READ_DUAL_OUTPUT_FAST,
+ CMD_READ_DUAL_IO_FAST,
+ CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_QUAD_IO_FAST,
+};
+
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+static int spi_flash_set_qeb_mxic(struct sf_nor *nor)
+{
+ u8 qeb_status
[U-Boot] [PATCH] mtd: sf: Zap ramtron driver
Removed ramtron driver since the EMK boards are
no longer been active, and these are the only boards
used this flash driver.
Commit details for EMK zap:
ppc/arm: zap EMK boards
(sha1: d58a9451e7339ed4cf2b2627e534611f427fb791)
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Cc: Reinhard Meyer reinhard.me...@emk-elektronik.de
---
drivers/mtd/spi/Makefile | 1 -
drivers/mtd/spi/ramtron.c | 404 --
2 files changed, 405 deletions(-)
delete mode 100644 drivers/mtd/spi/ramtron.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 15789a0..c61b784 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -17,6 +17,5 @@ obj-$(CONFIG_SPI_FLASH) += sf_probe.o
#endif
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
-obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
deleted file mode 100644
index a23032c..000
--- a/drivers/mtd/spi/ramtron.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/*
- * (C) Copyright 2010
- * Reinhard Meyer, EMK Elektronik, reinhard.me...@emk-elektronik.de
- *
- * SPDX-License-Identifier:GPL-2.0+
- */
-
-/*
- * Note: RAMTRON SPI FRAMs are ferroelectric, nonvolatile RAMs
- * with an interface identical to SPI flash devices.
- * However since they behave like RAM there are no delays or
- * busy polls required. They can sustain read or write at the
- * allowed SPI bus speed, which can be 40 MHz for some devices.
- *
- * Unfortunately some RAMTRON devices do not have a means of
- * identifying them. They will leave the SO line undriven when
- * the READ-ID command is issued. It is therefore mandatory
- * that the MISO line has a proper pull-up, so that READ-ID
- * will return a row of 0xff. This 0xff pseudo-id will cause
- * probes by all vendor specific functions that are designed
- * to handle it. If the MISO line is not pulled up, READ-ID
- * could return any random noise, even mimicking another
- * device.
- *
- * We use CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC
- * to define which device will be assumed after a simple status
- * register verify. This method is prone to false positive
- * detection and should therefore be the last to be tried.
- * Enter it in the last position in the table in spi_flash.c!
- *
- * The define CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC both activates
- * compilation of the special handler and defines the device
- * to assume.
- */
-
-#include common.h
-#include malloc.h
-#include spi.h
-#include spi_flash.h
-#include sf_internal.h
-
-/*
- * Properties of supported FRAMs
- * Note: speed is currently not used because we have no method to deliver that
- * value to the upper layers
- */
-struct ramtron_spi_fram_params {
- u32 size; /* size in bytes */
- u8 addr_len; /* number of address bytes */
- u8 merge_cmd; /* some address bits are in the command byte */
- u8 id1;/* device ID 1 (family, density) */
- u8 id2;/* device ID 2 (sub, rev, rsvd) */
- u32 speed; /* max. SPI clock in Hz */
- const char *name; /* name for display and/or matching */
-};
-
-struct ramtron_spi_fram {
- struct spi_flash flash;
- const struct ramtron_spi_fram_params *params;
-};
-
-static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash
-*flash)
-{
- return container_of(flash, struct ramtron_spi_fram, flash);
-}
-
-/*
- * table describing supported FRAM chips:
- * chips without RDID command must have the values 0xff for id1 and id2
- */
-static const struct ramtron_spi_fram_params ramtron_spi_fram_table[] = {
- {
- .size = 32*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x22,
- .id2 = 0x00,
- .speed = 4000,
- .name = FM25V02,
- },
- {
- .size = 32*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x22,
- .id2 = 0x01,
- .speed = 4000,
- .name = FM25VN02,
- },
- {
- .size = 64*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x23,
- .id2 = 0x00,
- .speed = 4000,
- .name = FM25V05,
- },
- {
- .size = 64*1024,
- .addr_len = 2,
- .merge_cmd = 0,
- .id1 = 0x23,
- .id2 = 0x01,
- .speed = 4000,
- .name = FM25VN05,
- },
- {
- .size = 128*1024,
- .addr_len = 3,
- .merge_cmd = 0,
- .id1 = 0x24
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. thanks! -- Jagan. The following changes since commit 0ce4af99c07acebf4fce9a91f1099d2460629293: Merge branch 'master' of git://git.denx.de/u-boot-imx (2014-10-27 09:08:42 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 027a9a002455a1175b0f5b7c7c5350afab2b4421: SPI: mxc_spi: delay initialisation until claim bus (2014-10-27 22:37:03 +0530) Marek Vasut (7): spi: altera: Use struct-based register access spi: altera: Clean up bit definitions spi: altera: Clean up most checkpatch issues spi: altera: Zap endless loop spi: altera: Clean up the use of variable d spi: altera: Add short note about EPCS/EPCQx1 spi: altera: Move the config options to the top Markus Niebel (2): SPI: mxc_spi: remove second reset from ECSPI config handler SPI: mxc_spi: delay initialisation until claim bus doc/SPI/README.altera_spi | 6 +++ drivers/spi/altera_spi.c | 132 ++ drivers/spi/mxc_spi.c | 40 +++--- 3 files changed, 101 insertions(+), 77 deletions(-) create mode 100644 doc/SPI/README.altera_spi ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 47d3debe1ab8315dc9ade22279e02f60eceda25b: Merge git://git.denx.de/u-boot-dm (2014-09-23 15:21:43 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to bf9b86dc47988a404964c97c74e541a129719f9c: spi: kirkwood_spi.c: cosmetic: Fix minor coding style issues (2014-09-24 17:48:56 +0530) Nikita Kiryanov (3): mtd: spi: add support for M25PE16 and M25PX16 spi: mxc: fix sf probe when using mxc_spi spl: replace CONFIG_SPL_SPI_* with CONFIG_SF_DEFAULT_* Stefan Roese (5): sf: Add M25PX64 SPI NOR flash ID arm: kirkwood: spi.h: Add some missing parenthesis spi: kirkwood_spi.c: Some fixes and cleanup spi: kirkwood_spi.c: Make global variable static spi: kirkwood_spi.c: cosmetic: Fix minor coding style issues arch/arm/include/asm/arch-kirkwood/spi.h | 8 ++--- board/boundary/nitrogen6x/nitrogen6x.c| 5 +++ board/embest/mx6boards/mx6boards.c| 5 +++ board/freescale/mx6qsabreauto/mx6qsabreauto.c | 7 board/freescale/mx6sabresd/mx6sabresd.c | 7 board/freescale/mx6slevk/mx6slevk.c | 5 +++ board/gateworks/gw_ventana/gw_ventana.c | 7 +++- board/genesi/mx51_efikamx/efikamx.c | 5 +++ board/ttcontrol/vision2/vision2.c | 5 +++ common/cmd_sf.c | 13 drivers/mtd/spi/sf_params.c | 3 ++ drivers/mtd/spi/spi_spl_load.c| 6 ++-- drivers/spi/kirkwood_spi.c| 27 +++ drivers/spi/mxc_spi.c | 48 ++- include/configs/am335x_evm.h | 2 -- include/configs/da850evm.h| 4 --- include/configs/dra7xx_evm.h | 2 -- include/configs/embestmx6boards.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/ks2_evm.h | 2 -- include/configs/mx51_efikamx.h| 4 +-- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6slevk.h| 2 +- include/configs/nitrogen6x.h | 2 +- include/configs/pcm051.h | 2 -- include/configs/sama5d3xek.h | 2 -- include/configs/siemens-am33x-common.h| 2 -- include/configs/tseries.h | 2 -- include/configs/vision2.h | 4 +-- include/configs/zynq-common.h | 2 -- include/spi_flash.h | 13 31 files changed, 115 insertions(+), 87 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] sandbox: Update minor documentation changes
From: Jagannadha Sutradharudu Teki jaga...@gmail.com - Use _defconfig instead of _config, but still _config is working. - Corrected README.sandbox path in ./README Signed-off-by: Jagannadha Sutradharudu Teki jaga...@gmail.com --- Changes for v2: - Fixed board path in 'board/sandbox/README.sandbox' README | 2 +- board/sandbox/README.sandbox | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/README b/README index 1e63f04..e88184b 100644 --- a/README +++ b/README @@ -272,7 +272,7 @@ board. This allows feature development which is not board- or architecture- specific to be undertaken on a native platform. The sandbox is also used to run some of U-Boot's tests. -See board/sandbox/sandbox/README.sandbox for more details. +See board/sandbox/README.sandbox for more details. Configuration Options: diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index 529c447..5f879f5 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -19,7 +19,7 @@ create unit tests which we can run to test this upper level code. CONFIG_SANDBOX is defined when building a native board. The chosen vendor and board names are also 'sandbox', so there is a single -board in board/sandbox/sandbox. +board in board/sandbox. CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian machines. @@ -32,7 +32,7 @@ Basic Operation To run sandbox U-Boot use something like: - make sandbox_config all + make sandbox_defconfig all ./u-boot Note: @@ -41,7 +41,7 @@ Note: build sandbox without SDL (i.e. no display/keyboard support) by removing the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using: - make sandbox_config all NO_SDL=1 + make sandbox_defconfig all NO_SDL=1 ./u-boot -- 2.0.0.rc1.4.gd8779e1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] doc: Use KBUILD_OUTPUT instead of BUILD_DIR
From: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
Now saving output files in a separate directory through
KBUILD_OUTPUT not with BUILD_DIR, so updated the documentation
accordingly.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
Changes for v2:
- none
MAKEALL | 12 ++--
README | 10 +-
doc/README.kwbimage | 4 ++--
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 392ea8d..187770b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -42,7 +42,7 @@ usage()
architecture ARCH. Substitute ARCH for any
supported architecture (default: )
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
- BUILD_DIRoutput build directory (default: ./)
+ KBUILD_OUTPUToutput build directory (default: ./)
BUILD_NBUILDSnumber of parallel targets (default: 1)
Examples:
@@ -223,14 +223,14 @@ BUILD_MANY=0
if [ ${BUILD_NBUILDS} -gt 1 ] ; then
BUILD_MANY=1
- : ${BUILD_DIR:=./build}
- mkdir -p ${BUILD_DIR}/ERR
- find ${BUILD_DIR}/ERR/ -type f -exec rm -f {} +
+ : ${KBUILD_OUTPUT:=./build}
+ mkdir -p ${KBUILD_OUTPUT}/ERR
+ find ${KBUILD_OUTPUT}/ERR/ -type f -exec rm -f {} +
fi
-: ${BUILD_DIR:=.}
+: ${KBUILD_OUTPUT:=.}
-OUTPUT_PREFIX=${BUILD_DIR}
+OUTPUT_PREFIX=${KBUILD_OUTPUT}
[ -d ${LOG_DIR} ] || mkdir ${LOG_DIR} || exit 1
if [ $CONTINUE != 'y' -a $REBUILD_ERRORS != 'y' ] ; then
diff --git a/README b/README
index e88184b..8e05f69 100644
--- a/README
+++ b/README
@@ -4969,14 +4969,14 @@ this behavior and build U-Boot to some external
directory:
make O=/tmp/build NAME_defconfig
make O=/tmp/build all
-2. Set environment variable BUILD_DIR to point to the desired location:
+2. Set environment variable KBUILD_OUTPUT to point to the desired location:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make NAME_defconfig
make all
-Note that the command line O= setting overrides the BUILD_DIR environment
+Note that the command line O= setting overrides the KBUILD_OUTPUT environment
variable.
@@ -5032,13 +5032,13 @@ or to build on a native PowerPC system you can type
When using the MAKEALL script, the default behaviour is to build
U-Boot in the source directory. This location can be changed by
-setting the BUILD_DIR environment variable. Also, for each target
+setting the KBUILD_OUTPUT environment variable. Also, for each target
built, the MAKEALL script saves two log files (target.ERR and
target.MAKEALL) in the source dir/LOG directory. This default
location can be changed by setting the MAKEALL_LOGDIR environment
variable. For example:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
export MAKEALL_LOGDIR=/tmp/log
CROSS_COMPILE=ppc_8xx- MAKEALL
diff --git a/doc/README.kwbimage b/doc/README.kwbimage
index 13f6f92..8c02298 100644
--- a/doc/README.kwbimage
+++ b/doc/README.kwbimage
@@ -30,10 +30,10 @@ kwbimage support available with mkimage utility will
generate kirkwood boot
image that can be flashed on the board NAND/SPI flash. The make target
which uses mkimage to produce such an image is u-boot.kwb. For example:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make yourboard_config
- make $BUILD_DIR/u-boot.kwb
+ make $KBUILD_OUTPUT/u-boot.kwb
Board specific configuration file specifications:
--
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[U-Boot] [PATCH 1/2] sandbox: Update minor documentation changes
From: Jagannadha Sutradharudu Teki jaga...@xilinx.com - Use _defconfig instead of _config, but _config is still working. - Corrected README.sandbox path in ./README Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- README | 2 +- board/sandbox/README.sandbox | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/README b/README index 1e63f04..e88184b 100644 --- a/README +++ b/README @@ -272,7 +272,7 @@ board. This allows feature development which is not board- or architecture- specific to be undertaken on a native platform. The sandbox is also used to run some of U-Boot's tests. -See board/sandbox/sandbox/README.sandbox for more details. +See board/sandbox/README.sandbox for more details. Configuration Options: diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index 529c447..2613c46 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -32,7 +32,7 @@ Basic Operation To run sandbox U-Boot use something like: - make sandbox_config all + make sandbox_defconfig all ./u-boot Note: @@ -41,7 +41,7 @@ Note: build sandbox without SDL (i.e. no display/keyboard support) by removing the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using: - make sandbox_config all NO_SDL=1 + make sandbox_defconfig all NO_SDL=1 ./u-boot -- 2.0.0.rc1.4.gd8779e1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] doc: Use KBUILD_OUTPUT instead of BUILD_DIR
Now saving output files in a separate directory through
KBUILD_OUTPUT not with BUILD_DIR, so updated the documentation
accordingly.
Signed-off-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com
---
MAKEALL | 12 ++--
README | 10 +-
doc/README.kwbimage | 4 ++--
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/MAKEALL b/MAKEALL
index 392ea8d..42f09e8 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -42,7 +42,7 @@ usage()
architecture ARCH. Substitute ARCH for any
supported architecture (default: )
MAKEALL_LOGDIR output all logs to here (default: ./LOG/)
- BUILD_DIRoutput build directory (default: ./)
+ KBUILD_OUTPUToutput build directory (default: ./)
BUILD_NBUILDSnumber of parallel targets (default: 1)
Examples:
@@ -223,14 +223,14 @@ BUILD_MANY=0
if [ ${BUILD_NBUILDS} -gt 1 ] ; then
BUILD_MANY=1
- : ${BUILD_DIR:=./build}
- mkdir -p ${BUILD_DIR}/ERR
- find ${BUILD_DIR}/ERR/ -type f -exec rm -f {} +
+ : ${KBUILD_OUTPUT:=./build}
+ mkdir -p ${KBUILD_OUTPUT}/ERR
+ find ${KBUILD_OUTPUT}/ERR/ -type f -exec rm -f {} +
fi
-: ${BUILD_DIR:=.}
+: ${KBUILD_OUTPUT:=.}
-OUTPUT_PREFIX=${BUILD_DIR}
+OUTPUT_PREFIX=${KBUILD_OUTPUT}
[ -d ${LOG_DIR} ] || mkdir ${LOG_DIR} || exit 1
if [ $CONTINUE != 'y' -a $REBUILD_ERRORS != 'y' ] ; then
diff --git a/README b/README
index e88184b..8e05f69 100644
--- a/README
+++ b/README
@@ -4969,14 +4969,14 @@ this behavior and build U-Boot to some external
directory:
make O=/tmp/build NAME_defconfig
make O=/tmp/build all
-2. Set environment variable BUILD_DIR to point to the desired location:
+2. Set environment variable KBUILD_OUTPUT to point to the desired location:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make NAME_defconfig
make all
-Note that the command line O= setting overrides the BUILD_DIR environment
+Note that the command line O= setting overrides the KBUILD_OUTPUT environment
variable.
@@ -5032,13 +5032,13 @@ or to build on a native PowerPC system you can type
When using the MAKEALL script, the default behaviour is to build
U-Boot in the source directory. This location can be changed by
-setting the BUILD_DIR environment variable. Also, for each target
+setting the KBUILD_OUTPUT environment variable. Also, for each target
built, the MAKEALL script saves two log files (target.ERR and
target.MAKEALL) in the source dir/LOG directory. This default
location can be changed by setting the MAKEALL_LOGDIR environment
variable. For example:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
export MAKEALL_LOGDIR=/tmp/log
CROSS_COMPILE=ppc_8xx- MAKEALL
diff --git a/doc/README.kwbimage b/doc/README.kwbimage
index 13f6f92..8c02298 100644
--- a/doc/README.kwbimage
+++ b/doc/README.kwbimage
@@ -30,10 +30,10 @@ kwbimage support available with mkimage utility will
generate kirkwood boot
image that can be flashed on the board NAND/SPI flash. The make target
which uses mkimage to produce such an image is u-boot.kwb. For example:
- export BUILD_DIR=/tmp/build
+ export KBUILD_OUTPUT=/tmp/build
make distclean
make yourboard_config
- make $BUILD_DIR/u-boot.kwb
+ make $KBUILD_OUTPUT/u-boot.kwb
Board specific configuration file specifications:
--
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[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please pull this PR. thanks! Jagan. The following changes since commit 25b4adbba018633b943a99322bfb2fb819c0bafb: include: remove CONFIG_SPL/CONFIG_TPL definition in config headers (2014-07-30 14:42:03 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to f659b57361c4a351ef2a5fc23b9197428e2e67f0: spi, spi_mxc: do not hang in spi_xchg_single (2014-08-06 00:18:01 +0530) Heiko Schocher (1): spi, spi_mxc: do not hang in spi_xchg_single Marek Vasut (1): sf: sf_ops: Stop leaking memory Simon Glass (3): cros_ec: Fix two bugs in the SPI implementation exynos: spi: Fix calculation of SPI transaction start time spi: Support half-duplex mode in FDT decode README | 4 doc/device-tree-bindings/spi/spi-bus.txt | 2 ++ drivers/misc/cros_ec_spi.c | 4 ++-- drivers/mtd/spi/sf_ops.c | 1 + drivers/spi/exynos_spi.c | 9 + drivers/spi/mxc_spi.c| 17 +++-- drivers/spi/spi.c| 2 ++ 7 files changed, 31 insertions(+), 8 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please take this PR. thanks! Jagan. The following changes since commit 3e1fa221f94b7ae3389d166882b77f1da5895f22: Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx (2014-06-05 17:38:30 -0400) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 1f436a6ddf7eb7f2da1c8df6c13100429baf844a: sf: probe: Fix quad bit set path (2014-06-08 23:12:27 +0530) Andrew Ruder (1): spi: soft_spi: Support NULL din/dout buffers Poddar, Sourav (1): sf: probe: Fix quad bit set path Siva Durga Prasad Paladugu (1): sf: params: Added support for Spansion S25FL512S_512K drivers/mtd/spi/sf_params.c | 1 + drivers/mtd/spi/sf_probe.c | 20 ++-- drivers/spi/soft_spi.c | 18 -- 3 files changed, 23 insertions(+), 16 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please take this PR, few fixes. thanks! -- Jagan. The following changes since commit 194ba5d4ecb2ad1195333cc7453f291e5b316479: sh: ecovec: correct romImage address in comment (2014-03-14 14:50:28 +0900) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to bf64035a159f114d0fb93391acb7f5e73eb020e6: mtd: spi: Fix page size for S25FL032P,S25FL064P (2014-03-17 21:54:57 +0530) Axel Lin (1): spi: atmel_dataflash: Simplify AT91F_SpiEnable implementation Jagannadha Sutradharudu Teki (1): sf: ops: Squash the malloc+memset combo Marek Vasut (4): sf: Fix entries for S25FL256S_256K and S25FL512S_256K sf: Add S25FL128S_256K IDs sf: Squash the malloc+memset combo mtd: spi: Fix page size for S25FL032P,S25FL064P drivers/mtd/spi/sf_ops.c | 8 ++-- drivers/mtd/spi/sf_params.c | 5 +++-- drivers/mtd/spi/sf_probe.c| 19 --- drivers/spi/atmel_dataflash_spi.c | 31 --- 4 files changed, 37 insertions(+), 26 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, Please take this PR, few fixes and pending patches on qspi am43xx. thanks! -- Jagan. The following changes since commit 22a240c32c1340183fce12867ae5f8736b92a638: serial/serial_arc - add driver for ARC UART (2014-02-07 12:55:07 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 9ea09e20376abbca21760ed4ba87d6b5c4df465c: doc: SPI: Add qspi test details on AM43xx (2014-02-18 22:41:09 +0530) Markus Niebel (3): spi: spi-mxc: add defines for clk inactive state for ECSPI spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3 spi: mxc_spi: i.MX6 DL/S have only 4 eCSPI controller Michal Simek (1): spi: xilinx: Move timeout calculation out of the loop Sourav Poddar (5): am43xx: Add qspi support am437x_epos_evm: add SPL API, QSPI, and serial flash support spi: ti_qspi: Add AM43xx specifics changes spi: ti_qspi: Add delay before xfer for am43xx doc: SPI: Add qspi test details on AM43xx arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 1 + arch/arm/include/asm/arch-am33xx/cpu.h | 4 +- arch/arm/include/asm/arch-am33xx/omap.h | 1 + arch/arm/include/asm/arch-mx5/imx-regs.h | 7 +-- arch/arm/include/asm/arch-mx6/imx-regs.h | 9 ++-- board/ti/am43xx/mux.c| 11 + doc/SPI/README.ti_qspi_am43x_test| 76 drivers/spi/mxc_spi.c| 9 +++- drivers/spi/ti_qspi.c| 33 -- drivers/spi/xilinx_spi.c | 8 ++-- include/configs/am43xx_evm.h | 20 + 11 files changed, 163 insertions(+), 16 deletions(-) create mode 100644 doc/SPI/README.ti_qspi_am43x_test ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 5/5] sf: Update bank configuration
Updated bank configuration code to more readable.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_probe.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 22b6335..c0a3a35 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -217,21 +217,22 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- u8 curr_bank = 0;
if (flash-size SPI_FLASH_16MB_BOUN) {
- flash-bank_read_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
- flash-bank_write_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
+ switch (idcode[0]) {
+ case SPI_FLASH_CFI_MFR_SPANSION:
+ flash-bank_read_cmd = CMD_BANKADDR_BRRD;
+ flash-bank_write_cmd = CMD_BANKADDR_BRWR;
+ break;
+ default:
+ flash-bank_read_cmd = CMD_EXTNADDR_RDEAR;
+ flash-bank_write_cmd = CMD_EXTNADDR_WREAR;
+ }
if (spi_flash_read_common(flash, flash-bank_read_cmd, 1,
- curr_bank, 1)) {
- debug(SF: fail to read bank addr register\n);
+ flash-bank_curr, 1)) {
+ debug(SF: Fail to read bank addr register\n);
return NULL;
}
- flash-bank_curr = curr_bank;
- } else {
- flash-bank_curr = curr_bank;
}
#endif
--
1.8.3
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[U-Boot] [PATCH v4 0/5] sf: Optimize spi_flash features code
Shrinked spi_slave and spi_flash code with respect to added flash features. V4: - Use braces in bit fileds m n becomes (m n) - Use mode instead of mode_bits V3: - Return -ENOMEM for calloc fails V2: - Divide dual_flash code into two patches. Jagannadha Sutradharudu Teki (5): sf: ops: Squash the malloc+memset combo sf: Optimize flash features code sf: Use slave mode for dual_flash connection doc: SPI: Update the dual_flash info sf: Update bank configuration doc/SPI/README.dual-flash | 5 +- doc/SPI/README.sf-features| 124 ++ drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 1 - drivers/mtd/spi/sf_ops.c | 16 ++-- drivers/mtd/spi/sf_params.c | 172 +- drivers/mtd/spi/sf_probe.c| 101 - include/spi.h | 42 --- include/spi_flash.h | 34 - 9 files changed, 302 insertions(+), 197 deletions(-) create mode 100644 doc/SPI/README.sf-features -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 3/5] sf: Use slave mode for dual_flash connection
SF uses mode from driver side for informing whether flash can operated in single or dual connections. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- drivers/mtd/spi/sf_probe.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 036f48d..22b6335 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -123,7 +123,6 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash-spi = spi; flash-name = params-name; flash-memory_map = spi-memory_map; - flash-dual_flash = flash-spi-option; /* Assign spi_flash ops */ flash-read = spi_flash_cmd_read_ops; @@ -133,7 +132,13 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, if (params-flags SST_WP) flash-write = sst_write_wp; #endif - + /* Get the dual flash connection modes */ +#ifdef CONFIG_SF_DUAL_FLASH + if (flash-spi-mode SPI_SHARED) + flash-dual_flash = SF_DUAL_STACKED_FLASH; + else if (flash-spi-mode SPI_SEPARATED) + flash-dual_flash = SF_DUAL_PARALLEL_FLASH; +#endif /* Compute the flash size */ flash-shift = (flash-dual_flash SF_DUAL_PARALLEL_FLASH) ? 1 : 0; flash-page_size = ((ext_jedec == 0x4d00) ? 512 : 256) flash-shift; -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 2/5] sf: Optimize flash features code
- Shrink spi_slave {}
- Shrink spi_flash_params {}
- Documentation for sf features
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
doc/SPI/README.sf-features| 121 +
drivers/mtd/spi/sf.c | 4 +-
drivers/mtd/spi/sf_internal.h | 1 -
drivers/mtd/spi/sf_ops.c | 8 +-
drivers/mtd/spi/sf_params.c | 172 +-
drivers/mtd/spi/sf_probe.c| 71 -
include/spi.h | 42 ---
include/spi_flash.h | 34 -
8 files changed, 272 insertions(+), 181 deletions(-)
create mode 100644 doc/SPI/README.sf-features
diff --git a/doc/SPI/README.sf-features b/doc/SPI/README.sf-features
new file mode 100644
index 000..e203bc0
--- /dev/null
+++ b/doc/SPI/README.sf-features
@@ -0,0 +1,121 @@
+SPI FLASH feature enhancements:
+==
+
+This document describes how to extend the current data structures in spi
subsystem
+for making use of new flash features/operations w.r.t to controller driver
support.
+
+1. spi_slave:
+
+struct spi_slave {
+..
+u32 mode;
+
+};
+
+@mode can be used to expose the SPI RX/TX operation modes, bus options and
+few flags which are used to extended the flash specific features/operations
+- include/spi.h
+
+mode:
+- SPI_TX_QPP: 4-wire tx transfer
+- SPI_RX_SLOW: 1-wire rx transfer
+- SPI_RX_DUAL: 2-wire rx transfer
+- SPI_RX_DUAL_IO: 2-wire io rx transfer
+- SPI_RX_QUAD: 4-wire rx transfer
+- SPI_RX_QUAD_IO: 4-wire io rx transfer
+- SPI_SHARED: bus shared with two slaves
+- SPI_SEPARATED: bus parallel with two slaves
+- SPI_U_PAGE: access second slave in bus shared
+
+2. spi_flash_params:
+
+struct spi_flash_params {
+
+u16 flags;
+..
+};
+
+@flags can be use to verify the flash supported features/operations with
respect
+to controller driven through @mode and also some internal flash specific
+operations - include/spi_flash.h
+
+flags:
+- SST_WP: SST flash write protection
+- SECT_4K: 4K erase sector
+- SECT_32K: 32 erase sector
+- E_FSR: Flag status register for erase/write for micron 256MB flash
+- WR_QPP: Quad page program
+- RD_SLOW: Array slow read
+- RD_DUAL: Dual fast read
+- RD_DUAL_IO: Dual IO read
+- RD_QUAD: Quad fast read
+- RD_QUAD_IO: Quad IO read
+- RD_2WIRE: All 2-wire read commands
+- RD_FULL: All read commands
+- ALL_CMDS: All read and write commands [1]
+
+3. spi_flash:
+
+struct spi_flash {
+...
+ u8 dual_flash;
+u8 shift;
+ u8 poll_cmd;
+u8 erase_cmd;
+u8 read_cmd;
+u8 write_cmd;
+u8 dummy_byte;
+
+};
+
+Few varibles from spi_flash {} can be used to perform the internal operations
+based on the selected flash features/operations from spi_slave {} and
+spi_flash_params {} - include/spi_flash.h
+
+@dual_flash: flash can be operated in dual flash [2]
+@shift: variable shift operator useful for dual parallel
+@poll_cmd: find the read_status or flag_status for polling erase/write
operations
+@erase_cmd: discovered erase command
+@read_cmd: discovered read command
+@write_cmd: discovered write command
+@dummy_byte: read dummy_byte based on read dummy_cycles.
+
+dummy byte is determined based on the dummy cycles of a particular command.
+Fast commands - dummy_byte = dummy_cycles/8
+I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
+For I/O commands except cmd[0] everything goes on no.of lines based on
+particular command but in case of fast commands except data all go on
+single line irrespective of command.
+
+4. Usage:
+
+In drivers/spi/*.c assign spi_slave {} with supported features through mode.
+Ex: drivers/spi/ti_qspi.c
+
+struct ti_qspi_slave {
+
+ struct spi_slave slave;
+ ..
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ .
+
+ qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
+ if (!qslave) {
+ printf(SPI_error: Fail to allocate ti_qspi_slave\n);
+ return NULL;
+ }
+
+ qslave-slave.mode = SPI_TX_QPP | SPI_RX_QUAD;
+
+}
+
+[1] http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
+[2] doc/SPI/README.dual-flash
+
+--
+Jagannadha Sutradharudu Teki jaga...@xilinx.com
+Sat Jan 18 14:44:28 IST 2014
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index 664e860..b4d7e6c 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -19,8 +19,8 @@ static int spi_flash_read_write(struct spi_slave *spi,
int ret;
#ifdef CONFIG_SF_DUAL_FLASH
- if (spi-flags SPI_XFER_U_PAGE)
- flags |= SPI_XFER_U_PAGE;
+ if (spi-mode SPI_U_PAGE)
+ flags |= SPI_U_PAGE;
#endif
if (data_len == 0)
flags |= SPI_XFER_END;
diff
[U-Boot] [PATCH v4 4/5] doc: SPI: Update the dual_flash info
Updated the dual_flash documentation as it uses
mode from spi drivers to inform the sf framework.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
doc/SPI/README.dual-flash | 5 +++--
doc/SPI/README.sf-features | 3 +++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
index 6c88d65..3398acb 100644
--- a/doc/SPI/README.dual-flash
+++ b/doc/SPI/README.dual-flash
@@ -9,7 +9,8 @@ to a given controller with single chip select line, but there
are some
hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
connected with a single chip select line from a controller.
-dual_flash from include/spi.h describes these types of connection mode
+dual_flash from include/spi_flash.h describes these types of connection mode
+in spi flash side and mode options for controller driver.
Possible connections:
@@ -54,7 +55,7 @@ SF_DUAL_STACKED_FLASH:
by default, if U_PAGE is unset lower memory should accessible,
once user wants to access upper memory need to set U_PAGE.
-SPI_FLASH_CONN_DUALPARALLEL:
+SF_DUAL_PARALLEL_FLASH:
- dual spi/qspi flash memories are connected with a single chipselect
line and these two memories are operating parallel with separate
buses.
- xilinx zynq qspi controller has implemented this feature [1]
diff --git a/doc/SPI/README.sf-features b/doc/SPI/README.sf-features
index e203bc0..f427c13 100644
--- a/doc/SPI/README.sf-features
+++ b/doc/SPI/README.sf-features
@@ -73,6 +73,9 @@ based on the selected flash features/operations from
spi_slave {} and
spi_flash_params {} - include/spi_flash.h
@dual_flash: flash can be operated in dual flash [2]
+- SF_SINGLE_FLASH: default connection single flash
+- SF_DUAL_STACKED_FLASH: dual flash with dual stacked connection
+- SF_DUAL_PARALLEL_FLASH: dual flash with dual parallel connection
@shift: variable shift operator useful for dual parallel
@poll_cmd: find the read_status or flag_status for polling erase/write
operations
@erase_cmd: discovered erase command
--
1.8.3
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[U-Boot] [PATCH v4 1/5] sf: ops: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_ops.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 1f1bb36..ef91b92 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,7 @@
*/
#include common.h
+#include errno.h
#include malloc.h
#include spi.h
#include spi_flash.h
@@ -381,8 +382,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
}
cmdsz = SPI_FLASH_CMD_LEN + flash-dummy_byte;
- cmd = malloc(cmdsz);
- memset(cmd, 0, cmdsz);
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug(SF: Failed to allocate cmd\n);
+ return -ENOMEM;
+ }
cmd[0] = flash-read_cmd;
while (len) {
--
1.8.3
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[U-Boot] Pull request: u-boot-spi/master
Hi Tom, SF code optimized stuff and few fixes. -- Thanks! Jagan. The following changes since commit 0876703cf2ee107372b56037d4eeeb7604c56796: boards.cfg: Keep the entries sorted (2014-01-27 08:28:35 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 6dc0ce128f1d3ec8a06f98606d9c6f5020b98b3f: sf: Update bank configuration (2014-01-27 22:47:17 +0530) Jagannadha Sutradharudu Teki (5): sf: ops: Squash the malloc+memset combo sf: Optimize flash features code sf: Use slave mode for dual_flash connection doc: SPI: Update the dual_flash info sf: Update bank configuration Marek Vasut (3): sf: Squash the malloc+memset combo sf: Fix entries for S25FL256S_256K and S25FL512S_256K sf: Add S25FL128S_256K IDs doc/SPI/README.dual-flash | 5 +- doc/SPI/README.sf-features| 124 ++ drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 1 - drivers/mtd/spi/sf_ops.c | 16 ++-- drivers/mtd/spi/sf_params.c | 171 +- drivers/mtd/spi/sf_probe.c| 104 - include/spi.h | 42 --- include/spi_flash.h | 34 - 9 files changed, 303 insertions(+), 198 deletions(-) create mode 100644 doc/SPI/README.sf-features ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-spi/master
Hi Tom, SF code optimized stuff and few fixes. -- Thanks! Jagan. The following changes since commit b44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b: Prepare v2014.01 (2014-01-20 17:52:59 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to b53c0ea9adb7b72f4e3074d382598b6b3d9c5037: sf: Update bank configuration (2014-01-21 23:08:28 +0530) Jagannadha Sutradharudu Teki (5): sf: ops: Squash the malloc+memset combo sf: Optimize flash features code sf: Use mode_bits for dual_flash connection doc: SPI: Update the dual_flash info sf: Update bank configuration Marek Vasut (3): sf: Squash the malloc+memset combo sf: Fix entries for S25FL256S_256K and S25FL512S_256K sf: Add S25FL128S_256K IDs doc/SPI/README.dual-flash | 5 +- doc/SPI/README.sf-features| 124 ++ drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 1 - drivers/mtd/spi/sf_ops.c | 16 ++-- drivers/mtd/spi/sf_params.c | 171 +- drivers/mtd/spi/sf_probe.c| 104 - include/spi.h | 42 --- include/spi_flash.h | 24 +++--- 9 files changed, 299 insertions(+), 192 deletions(-) create mode 100644 doc/SPI/README.sf-features ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 5/5] sf: Update bank configuration
Updated bank configuration code to more readable.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_probe.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index a5f3046..10d183d 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -217,21 +217,23 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- u8 curr_bank = 0;
+ flash-bank_curr = 0;
if (flash-size SPI_FLASH_16MB_BOUN) {
- flash-bank_read_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
- flash-bank_write_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
+ switch (idcode[0]) {
+ case SPI_FLASH_CFI_MFR_SPANSION:
+ flash-bank_read_cmd = CMD_BANKADDR_BRRD;
+ flash-bank_write_cmd = CMD_BANKADDR_BRWR;
+ break;
+ default:
+ flash-bank_read_cmd = CMD_EXTNADDR_RDEAR;
+ flash-bank_write_cmd = CMD_EXTNADDR_WREAR;
+ }
if (spi_flash_read_common(flash, flash-bank_read_cmd, 1,
- curr_bank, 1)) {
- debug(SF: fail to read bank addr register\n);
+ flash-bank_curr, 1)) {
+ debug(SF: Fail to read bank addr register\n);
return NULL;
}
- flash-bank_curr = curr_bank;
- } else {
- flash-bank_curr = curr_bank;
}
#endif
--
1.8.3
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[U-Boot] [PATCH v2 4/5] doc: SPI: Update the dual_flash info
Updated the dual_flash documentation as it uses
mode_bits from spi drivers to inform the sf framework.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
doc/SPI/README.dual-flash | 5 +++--
doc/SPI/README.sf-features | 3 +++
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
index 6c88d65..05b875f 100644
--- a/doc/SPI/README.dual-flash
+++ b/doc/SPI/README.dual-flash
@@ -9,7 +9,8 @@ to a given controller with single chip select line, but there
are some
hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
connected with a single chip select line from a controller.
-dual_flash from include/spi.h describes these types of connection mode
+dual_flash from include/spi_flash.h describes these types of connection mode
+in spi flash side and mode_bits options for controller driver.
Possible connections:
@@ -54,7 +55,7 @@ SF_DUAL_STACKED_FLASH:
by default, if U_PAGE is unset lower memory should accessible,
once user wants to access upper memory need to set U_PAGE.
-SPI_FLASH_CONN_DUALPARALLEL:
+SF_DUAL_PARALLEL_FLASH:
- dual spi/qspi flash memories are connected with a single chipselect
line and these two memories are operating parallel with separate
buses.
- xilinx zynq qspi controller has implemented this feature [1]
diff --git a/doc/SPI/README.sf-features b/doc/SPI/README.sf-features
index d35f56d..4047e95 100644
--- a/doc/SPI/README.sf-features
+++ b/doc/SPI/README.sf-features
@@ -73,6 +73,9 @@ based on the selected flash features/operations from
spi_slave {} and
spi_flash_params {} - include/spi_flash.h
@dual_flash: flash can be operated in dual flash [3]
+- SF_SINGLE_FLASH: default connection single flash
+- SF_DUAL_STACKED_FLASH: dual flash with dual stacked connection
+- SF_DUAL_PARALLEL_FLASH: dual flash with dual parallel connection
@shift: variable shift operator useful for dual parallel
@poll_cmd: find the read_status or flag_status for polling erase/write
operations
@erase_cmd: discovered erase command
--
1.8.3
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[U-Boot] [PATCH v2 0/5] sf: Optimize spi_flash features code
Shrinked spi_slave and spi_flash code with respect to added flash features. Jagannadha Sutradharudu Teki (5): sf: ops: Squash the malloc+memset combo sf: Optimize flash features code sf: Use mode_bits for dual_flash connection doc: SPI: Update the dual_flash info sf: Update bank configuration doc/SPI/README.dual-flash | 5 +- doc/SPI/README.sf-features| 125 ++ drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 1 - drivers/mtd/spi/sf_ops.c | 15 ++-- drivers/mtd/spi/sf_params.c | 172 +- drivers/mtd/spi/sf_probe.c| 102 - include/spi.h | 42 --- include/spi_flash.h | 24 +++--- 9 files changed, 300 insertions(+), 190 deletions(-) create mode 100644 doc/SPI/README.sf-features -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/5] sf: Use mode_bits for dual_flash connection
SF uses mode_bits from driver side for informing whether flash can operated in single or dual connections. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com Cc: Marek Vasut ma...@denx.de --- drivers/mtd/spi/sf_probe.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index abde69b..a5f3046 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -123,7 +123,6 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, flash-spi = spi; flash-name = params-name; flash-memory_map = spi-memory_map; - flash-dual_flash = flash-spi-option; /* Assign spi_flash ops */ flash-read = spi_flash_cmd_read_ops; @@ -133,7 +132,13 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, if (params-flags SST_WP) flash-write = sst_write_wp; #endif - + /* Get the dual flash connection modes */ +#ifdef CONFIG_SF_DUAL_FLASH + if (flash-spi-mode_bits SPI_SHARED) + flash-dual_flash = SF_DUAL_STACKED_FLASH; + else if (flash-spi-mode_bits SPI_SEPARATED) + flash-dual_flash = SF_DUAL_PARALLEL_FLASH; +#endif /* Compute the flash size */ flash-shift = (flash-dual_flash SF_DUAL_PARALLEL_FLASH) ? 1 : 0; flash-page_size = ((ext_jedec == 0x4d00) ? 512 : 256) flash-shift; -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/5] sf: Optimize flash features code
From: Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
- Shrink spi_slave {}
- Shrink spi_flash_params {}
- Documentation for sf features
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
doc/SPI/README.sf-features| 122 ++
drivers/mtd/spi/sf.c | 4 +-
drivers/mtd/spi/sf_internal.h | 1 -
drivers/mtd/spi/sf_ops.c | 8 +-
drivers/mtd/spi/sf_params.c | 172 +-
drivers/mtd/spi/sf_probe.c| 71 -
include/spi.h | 42 ---
include/spi_flash.h | 24 +++---
8 files changed, 270 insertions(+), 174 deletions(-)
create mode 100644 doc/SPI/README.sf-features
diff --git a/doc/SPI/README.sf-features b/doc/SPI/README.sf-features
new file mode 100644
index 000..d35f56d
--- /dev/null
+++ b/doc/SPI/README.sf-features
@@ -0,0 +1,122 @@
+SPI FLASH feature enhancements:
+==
+
+This document describes how to extend the current data structures in spi
subsystem
+for making use of new flash features/operations w.r.t to controller driver
support.
+
+1. spi_slave:
+
+struct spi_slave {
+..
+u32 mode_bits;
+
+};
+
+@mode_bits can be used to expose the SPI RX/TX operation modes, bus options and
+few flags which are used to extended the flash specific features/operations
+- include/spi.h
+
+mode_bits:
+- SPI_TX_QPP: 4-Wire tx transfer operation quad page program
+- SPI_RX_SLOW: 1-wire rx transfer operation array slow read
+- SPI_RX_DUAL: 2-wire rx transfer operation dual fast read
+- SPI_RX_DUAL_IO: 2-wire rx transfer operation dual io fast read
+- SPI_RX_QUAD: 4-wire rx transfer operation quad fast read
+- SPI_RX_QUAD_IO: 4-wire rx transfer operation quad io fast read
+- SPI_SHARED: dual flash devices are connected in shared bus connection
+- SPI_SEPARATED: dual flash devices are connected in separate bus connection
+- SPI_U_PAGE: select the upper flash in dual flash shared bus connection [1]
+
+2. spi_flash_params:
+
+struct spi_flash_params {
+
+u16 flags;
+..
+};
+
+@flags can be use to verify the flash supported features/operations with
respect
+to controller driven through @mode_bits and also some internal flash specific
+operations - include/spi_flash.h
+
+flags:
+- SST_WP: SST flash write protection
+- SECT_4K: 4K erase sector
+- SECT_32K: 32 erase sector
+- E_FSR: Flag status register for erase/write for micron 256MB flash
+- WR_QPP: Quad page program
+- RD_SLOW: Array slow read
+- RD_DUAL: Dual fast read
+- RD_DUAL_IO: Dual IO read
+- RD_QUAD: Quad fast read
+- RD_QUAD_IO: Quad IO read
+- RD_2WIRE: All 2-wire read commands
+- RD_FULL: All read commands
+- ALL_CMDS: All read and write commands [2]
+
+3. spi_flash:
+
+struct spi_flash {
+...
+ u8 dual_flash;
+u8 shift;
+ u8 poll_cmd;
+u8 erase_cmd;
+u8 read_cmd;
+u8 write_cmd;
+u8 dummy_byte;
+
+};
+
+Few varibles from spi_flash {} can be used to perform the internal operations
+based on the selected flash features/operations from spi_slave {} and
+spi_flash_params {} - include/spi_flash.h
+
+@dual_flash: flash can be operated in dual flash [3]
+@shift: variable shift operator useful for dual parallel
+@poll_cmd: find the read_status or flag_status for polling erase/write
operations
+@erase_cmd: discovered erase command
+@read_cmd: discovered read command
+@write_cmd: discovered write command
+@dummy_byte: read dummy_byte based on read dummy_cycles.
+
+dummy byte is determined based on the dummy cycles of a particular command.
+Fast commands - dummy_byte = dummy_cycles/8
+I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
+For I/O commands except cmd[0] everything goes on no.of lines based on
+particular command but in case of fast commands except data all go on
+single line irrespective of command.
+
+4. Usage:
+
+In drivers/spi/*.c assign spi_slave {} with supported features through
mode_bits.
+Ex: drivers/spi/ti_qspi.c
+
+struct ti_qspi_slave {
+
+ struct spi_slave slave;
+ ..
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ .
+
+ qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
+ if (!qslave) {
+ printf(SPI_error: Fail to allocate ti_qspi_slave\n);
+ return NULL;
+ }
+
+ qslave-slave.mode_bits = SPI_TX_QPP | SPI_RX_QUAD;
+
+}
+
+[1]
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+[2] http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
+[3] doc/SPI/README.dual-flash
+
+--
+Jagannadha Sutradharudu Teki jaga...@xilinx.com
+Sat Jan 18 14:44:28 IST 2014
diff --git a/drivers/mtd
[U-Boot] [PATCH v2 1/5] sf: ops: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
drivers/mtd/spi/sf_ops.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 1f1bb36..abdb0ef 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -381,8 +381,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
}
cmdsz = SPI_FLASH_CMD_LEN + flash-dummy_byte;
- cmd = malloc(cmdsz);
- memset(cmd, 0, cmdsz);
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug(SF: Failed to allocate cmd\n);
+ return ret;
+ }
cmd[0] = flash-read_cmd;
while (len) {
--
1.8.3
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[U-Boot] [PATCH v3] sf: ops: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v3:
- Use errno.h
Changes for v2:
- used debug()
drivers/mtd/spi/sf_ops.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 1f1bb36..ef91b92 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,7 @@
*/
#include common.h
+#include errno.h
#include malloc.h
#include spi.h
#include spi_flash.h
@@ -381,8 +382,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
}
cmdsz = SPI_FLASH_CMD_LEN + flash-dummy_byte;
- cmd = malloc(cmdsz);
- memset(cmd, 0, cmdsz);
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ debug(SF: Failed to allocate cmd\n);
+ return -ENOMEM;
+ }
cmd[0] = flash-read_cmd;
while (len) {
--
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[U-Boot] [PATCH v3] sf: Update bank configuration
Updated bank configuration code to more readable.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
Changes for v3:
- remove bank_curr = 0 for non bank case
Changes for v2:
- none
drivers/mtd/spi/sf_probe.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index a5f3046..53995e4 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -217,21 +217,22 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- u8 curr_bank = 0;
if (flash-size SPI_FLASH_16MB_BOUN) {
- flash-bank_read_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
- flash-bank_write_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
+ switch (idcode[0]) {
+ case SPI_FLASH_CFI_MFR_SPANSION:
+ flash-bank_read_cmd = CMD_BANKADDR_BRRD;
+ flash-bank_write_cmd = CMD_BANKADDR_BRWR;
+ break;
+ default:
+ flash-bank_read_cmd = CMD_EXTNADDR_RDEAR;
+ flash-bank_write_cmd = CMD_EXTNADDR_WREAR;
+ }
if (spi_flash_read_common(flash, flash-bank_read_cmd, 1,
- curr_bank, 1)) {
- debug(SF: fail to read bank addr register\n);
+ flash-bank_curr, 1)) {
+ debug(SF: Fail to read bank addr register\n);
return NULL;
}
- flash-bank_curr = curr_bank;
- } else {
- flash-bank_curr = curr_bank;
}
#endif
--
1.8.3
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[U-Boot] Pull request: u-boot-spi/master
Hi Tom, SF code optimized stuff and few fixes. -- Thanks, Jagan. The following changes since commit 5c9038b6af1a93410af966999638eabb81efcd0f: omap3_beagle: use omap3-beagle.dtb for the C4 revision (2014-01-17 11:03:04 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 83ba605953162443b054d5ad60535468b46558bd: sf: Update bank configuration (2014-01-20 22:30:35 +0530) Jagannadha Sutradharudu Teki (5): sf: ops: Squash the malloc+memset combo sf: Optimize flash features code sf: Use mode_bits for dual_flash connection doc: SPI: Update the dual_flash info sf: Update bank configuration Marek Vasut (3): sf: Squash the malloc+memset combo sf: Fix entries for S25FL256S_256K and S25FL512S_256K sf: Add S25FL128S_256K IDs doc/SPI/README.dual-flash | 5 +- doc/SPI/README.sf-features| 125 ++ drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 1 - drivers/mtd/spi/sf_ops.c | 16 ++-- drivers/mtd/spi/sf_params.c | 171 +- drivers/mtd/spi/sf_probe.c| 104 - include/spi.h | 42 --- include/spi_flash.h | 24 +++--- 9 files changed, 301 insertions(+), 191 deletions(-) create mode 100644 doc/SPI/README.sf-features ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/6] sf: Optimize flash features code
- Shrink spi_slave {}
- Shrink spi_flash_params {}
- Documentation for sf features
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
doc/SPI/README.sf-features| 122 ++
drivers/mtd/spi/sf.c | 4 +-
drivers/mtd/spi/sf_internal.h | 1 -
drivers/mtd/spi/sf_ops.c | 8 +-
drivers/mtd/spi/sf_params.c | 172 +-
drivers/mtd/spi/sf_probe.c| 71 -
include/spi.h | 42 ---
include/spi_flash.h | 24 +++---
8 files changed, 270 insertions(+), 174 deletions(-)
create mode 100644 doc/SPI/README.sf-features
diff --git a/doc/SPI/README.sf-features b/doc/SPI/README.sf-features
new file mode 100644
index 000..d35f56d
--- /dev/null
+++ b/doc/SPI/README.sf-features
@@ -0,0 +1,122 @@
+SPI FLASH feature enhancements:
+==
+
+This document describes how to extend the current data structures in spi
subsystem
+for making use of new flash features/operations w.r.t to controller driver
support.
+
+1. spi_slave:
+
+struct spi_slave {
+..
+u32 mode_bits;
+
+};
+
+@mode_bits can be used to expose the SPI RX/TX operation modes, bus options and
+few flags which are used to extended the flash specific features/operations
+- include/spi.h
+
+mode_bits:
+- SPI_TX_QPP: 4-Wire tx transfer operation quad page program
+- SPI_RX_SLOW: 1-wire rx transfer operation array slow read
+- SPI_RX_DUAL: 2-wire rx transfer operation dual fast read
+- SPI_RX_DUAL_IO: 2-wire rx transfer operation dual io fast read
+- SPI_RX_QUAD: 4-wire rx transfer operation quad fast read
+- SPI_RX_QUAD_IO: 4-wire rx transfer operation quad io fast read
+- SPI_SHARED: dual flash devices are connected in shared bus connection
+- SPI_SEPARATED: dual flash devices are connected in separate bus connection
+- SPI_U_PAGE: select the upper flash in dual flash shared bus connection [1]
+
+2. spi_flash_params:
+
+struct spi_flash_params {
+
+u16 flags;
+..
+};
+
+@flags can be use to verify the flash supported features/operations with
respect
+to controller driven through @mode_bits and also some internal flash specific
+operations - include/spi_flash.h
+
+flags:
+- SST_WP: SST flash write protection
+- SECT_4K: 4K erase sector
+- SECT_32K: 32 erase sector
+- E_FSR: Flag status register for erase/write for micron 256MB flash
+- WR_QPP: Quad page program
+- RD_SLOW: Array slow read
+- RD_DUAL: Dual fast read
+- RD_DUAL_IO: Dual IO read
+- RD_QUAD: Quad fast read
+- RD_QUAD_IO: Quad IO read
+- RD_2WIRE: All 2-wire read commands
+- RD_FULL: All read commands
+- ALL_CMDS: All read and write commands [2]
+
+3. spi_flash:
+
+struct spi_flash {
+...
+ u8 dual_flash;
+u8 shift;
+ u8 poll_cmd;
+u8 erase_cmd;
+u8 read_cmd;
+u8 write_cmd;
+u8 dummy_byte;
+
+};
+
+Few varibles from spi_flash {} can be used to perform the internal operations
+based on the selected flash features/operations from spi_slave {} and
+spi_flash_params {} - include/spi_flash.h
+
+@dual_flash: flash can be operated in dual flash [3]
+@shift: variable shift operator useful for dual parallel
+@poll_cmd: find the read_status or flag_status for polling erase/write
operations
+@erase_cmd: discovered erase command
+@read_cmd: discovered read command
+@write_cmd: discovered write command
+@dummy_byte: read dummy_byte based on read dummy_cycles.
+
+dummy byte is determined based on the dummy cycles of a particular command.
+Fast commands - dummy_byte = dummy_cycles/8
+I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
+For I/O commands except cmd[0] everything goes on no.of lines based on
+particular command but in case of fast commands except data all go on
+single line irrespective of command.
+
+4. Usage:
+
+In drivers/spi/*.c assign spi_slave {} with supported features through
mode_bits.
+Ex: drivers/spi/ti_qspi.c
+
+struct ti_qspi_slave {
+
+ struct spi_slave slave;
+ ..
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ .
+
+ qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
+ if (!qslave) {
+ printf(SPI_error: Fail to allocate ti_qspi_slave\n);
+ return NULL;
+ }
+
+ qslave-slave.mode_bits = SPI_TX_QPP | SPI_RX_QUAD;
+
+}
+
+[1]
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+[2] http://www.spansion.com/Support/Datasheets/S25FL128S_256S_00.pdf
+[3] doc/SPI/README.dual-flash
+
+--
+Jagannadha Sutradharudu Teki jaga...@xilinx.com
+Sat Jan 18 14:44:28 IST 2014
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index 664e860..fb91ac6 100644
--- a/drivers
[U-Boot] [PATCH 3/6] sf: Renames on dual_flash stuff
- Used small names for dual_flash macros
- Updated doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
doc/SPI/README.dual-flash | 9 +
doc/SPI/README.sf-features | 3 +++
drivers/mtd/spi/sf_ops.c | 10 +-
drivers/mtd/spi/sf_probe.c | 18 +++---
include/spi_flash.h| 14 +++---
5 files changed, 31 insertions(+), 23 deletions(-)
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
index 6c88d65..6c4236d 100644
--- a/doc/SPI/README.dual-flash
+++ b/doc/SPI/README.dual-flash
@@ -9,11 +9,12 @@ to a given controller with single chip select line, but there
are some
hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
connected with a single chip select line from a controller.
-dual_flash from include/spi.h describes these types of connection mode
+dual_flash from include/spi_flash.h describes these types of connection mode
+in spi flash side and mode_bits options for controller driver.
Possible connections:
-SF_SINGLE_FLASH:
+SF_SINGLE:
- single spi flash memory connected with single chip select line.
++ CS +---+
@@ -24,7 +25,7 @@ SF_SINGLE_FLASH:
||---| |
+++---+
-SF_DUAL_STACKED_FLASH:
+SF_STACKED:
- dual spi/qspi flash memories are connected with a single chipselect
line and these two memories are operating stacked fasion with shared
buses.
- xilinx zynq qspi controller has implemented this feature [1]
@@ -54,7 +55,7 @@ SF_DUAL_STACKED_FLASH:
by default, if U_PAGE is unset lower memory should accessible,
once user wants to access upper memory need to set U_PAGE.
-SPI_FLASH_CONN_DUALPARALLEL:
+SF_PARALLEL:
- dual spi/qspi flash memories are connected with a single chipselect
line and these two memories are operating parallel with separate
buses.
- xilinx zynq qspi controller has implemented this feature [1]
diff --git a/doc/SPI/README.sf-features b/doc/SPI/README.sf-features
index d35f56d..851dfa8 100644
--- a/doc/SPI/README.sf-features
+++ b/doc/SPI/README.sf-features
@@ -73,6 +73,9 @@ based on the selected flash features/operations from
spi_slave {} and
spi_flash_params {} - include/spi_flash.h
@dual_flash: flash can be operated in dual flash [3]
+- SF_SINGLE: default connection single flash
+- SF_STACKED: dual flash with dual stacked connection
+- SF_PARALLEL: dual flash with dual parallel connection
@shift: variable shift operator useful for dual parallel
@poll_cmd: find the read_status or flag_status for polling erase/write
operations
@erase_cmd: discovered erase command
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 2f3b03a..6cbbfe3 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -135,7 +135,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
{
switch (flash-dual_flash) {
- case SF_DUAL_STACKED_FLASH:
+ case SF_STACKED:
if (*addr = (flash-size 1)) {
*addr -= flash-size 1;
flash-spi-mode_bits |= SPI_U_PAGE;
@@ -143,7 +143,7 @@ static void spi_flash_dual_flash(struct spi_flash *flash,
u32 *addr)
flash-spi-mode_bits = ~SPI_U_PAGE;
}
break;
- case SF_DUAL_PARALLEL_FLASH:
+ case SF_PARALLEL:
*addr = flash-shift;
break;
default:
@@ -261,7 +261,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len)
erase_addr = offset;
#ifdef CONFIG_SF_DUAL_FLASH
- if (flash-dual_flash SF_SINGLE_FLASH)
+ if (flash-dual_flash SF_SINGLE)
spi_flash_dual_flash(flash, erase_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
@@ -303,7 +303,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
write_addr = offset;
#ifdef CONFIG_SF_DUAL_FLASH
- if (flash-dual_flash SF_SINGLE_FLASH)
+ if (flash-dual_flash SF_SINGLE)
spi_flash_dual_flash(flash, write_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
@@ -392,7 +392,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
read_addr = offset;
#ifdef CONFIG_SF_DUAL_FLASH
- if (flash-dual_flash SF_SINGLE_FLASH)
+ if (flash-dual_flash SF_SINGLE)
spi_flash_dual_flash(flash, read_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index d1ebf72..79fbad7 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi
[U-Boot] [PATCH 6/6] sf: Update bank configuration
Updated bank configuration code to more readable.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_probe.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 8f92333..06f99da 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -215,21 +215,23 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
/* Configure the BAR - discover bank cmds and read current bank */
#ifdef CONFIG_SPI_FLASH_BAR
- u8 curr_bank = 0;
+ flash-bank_curr = 0;
if (flash-size SF_16MB_BOUN) {
- flash-bank_read_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
- flash-bank_write_cmd = (idcode[0] == 0x01) ?
- CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
+ switch (idcode[0]) {
+ case SF_CFI_MFR_SPANSION:
+ flash-bank_read_cmd = CMD_BANKADDR_BRRD;
+ flash-bank_write_cmd = CMD_BANKADDR_BRWR;
+ break;
+ default:
+ flash-bank_read_cmd = CMD_EXTNADDR_RDEAR;
+ flash-bank_write_cmd = CMD_EXTNADDR_WREAR;
+ }
if (spi_flash_read_common(flash, flash-bank_read_cmd, 1,
- curr_bank, 1)) {
- debug(SF: fail to read bank addr register\n);
+ flash-bank_curr, 1)) {
+ debug(SF: Fail to read bank addr register\n);
return NULL;
}
- flash-bank_curr = curr_bank;
- } else {
- flash-bank_curr = curr_bank;
}
#endif
--
1.8.3
___
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U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6] sf: Minor macro cleanups
Renamed SPI_FLASH with SF in few places in sf code.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 20 ++--
drivers/mtd/spi/sf_ops.c | 23 +++
drivers/mtd/spi/sf_probe.c| 19 +--
3 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 6b6fa22..fba7218 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,15 +10,15 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
-#define SPI_FLASH_3B_ADDR_LEN 3
-#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
-#define SPI_FLASH_16MB_BOUN0x100
+#define SF_3BYTE_ADDR 3
+#define SF_CMD_LEN (1 + SF_3BYTE_ADDR)
+#define SF_16MB_BOUN 0x100
/* CFI Manufacture ID's */
-#define SPI_FLASH_CFI_MFR_SPANSION 0x01
-#define SPI_FLASH_CFI_MFR_STMICRO 0x20
-#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
-#define SPI_FLASH_CFI_MFR_WINBOND 0xef
+#define SF_CFI_MFR_SPANSION0x01
+#define SF_CFI_MFR_STMICRO 0x20
+#define SF_CFI_MFR_MACRONIX0xc2
+#define SF_CFI_MFR_WINBOND 0xef
/* Erase commands */
#define CMD_ERASE_4K 0x20
@@ -61,9 +61,9 @@
#define STATUS_PEC (1 7)
/* Flash timeout values */
-#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
-#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
+#define SF_PROG_TIMEOUT(2 * CONFIG_SYS_HZ)
+#define SF_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SF_SECTOR_ERASE_TIMEOUT(10 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 6cbbfe3..02b12c1 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -119,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
u8 bank_sel;
int ret;
- bank_sel = offset / (SPI_FLASH_16MB_BOUN flash-shift);
+ bank_sel = offset / (SF_16MB_BOUN flash-shift);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
@@ -207,11 +207,11 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
size_t cmd_len, const void *buf, size_t buf_len)
{
struct spi_slave *spi = flash-spi;
- unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
+ unsigned long timeout = SF_PROG_TIMEOUT;
int ret;
if (buf == NULL)
- timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
+ timeout = SF_PAGE_ERASE_TIMEOUT;
ret = spi_claim_bus(flash-spi);
if (ret) {
@@ -233,9 +233,8 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
ret = spi_flash_cmd_wait_ready(flash, timeout);
if (ret 0) {
- debug(SF: write %s timed out\n,
- timeout == SPI_FLASH_PROG_TIMEOUT ?
- program : page erase);
+ debug(SF: write %s timed out\n, buf == NULL ?
+ page erase : program);
return ret;
}
@@ -247,7 +246,7 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size, erase_addr;
- u8 cmd[SPI_FLASH_CMD_LEN];
+ u8 cmd[SF_CMD_LEN];
int ret = -1;
erase_size = flash-erase_size;
@@ -293,7 +292,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
unsigned long byte_addr, page_size;
u32 write_addr;
size_t chunk_len, actual;
- u8 cmd[SPI_FLASH_CMD_LEN];
+ u8 cmd[SF_CMD_LEN];
int ret = -1;
page_size = flash-page_size;
@@ -380,7 +379,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
return 0;
}
- cmdsz = SPI_FLASH_CMD_LEN + flash-dummy_byte;
+ cmdsz = SF_CMD_LEN + flash-dummy_byte;
cmd = calloc(1, cmdsz);
if (!cmd) {
printf(SF: Failed to allocate cmd\n);
@@ -400,7 +399,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
if (bank_sel 0)
return ret;
#endif
- remain_len = ((SPI_FLASH_16MB_BOUN flash-shift) *
+ remain_len = ((SF_16MB_BOUN flash-shift) *
(bank_sel + 1)) - offset;
if (len remain_len)
read_len = len;
@@ -445,7 +444,7 @@ static int sst_byte_write(struct spi_flash *flash, u32
offset, const void *buf)
if (ret)
return ret;
- return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ return
[U-Boot] [PATCH 1/6] sf: ops: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
drivers/mtd/spi/sf_ops.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 1f1bb36..1fac63a 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -381,8 +381,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
}
cmdsz = SPI_FLASH_CMD_LEN + flash-dummy_byte;
- cmd = malloc(cmdsz);
- memset(cmd, 0, cmdsz);
+ cmd = calloc(1, cmdsz);
+ if (!cmd) {
+ printf(SF: Failed to allocate cmd\n);
+ return ret;
+ }
cmd[0] = flash-read_cmd;
while (len) {
--
1.8.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/6] sf: Update read/write command macros
- Used readable names for read/write command macros
- Added comments for the same
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
Cc: Simon Glass s...@chromium.org
---
drivers/mtd/spi/ramtron.c | 10 --
drivers/mtd/spi/sandbox.c | 12 ++--
drivers/mtd/spi/sf_internal.h | 16
drivers/mtd/spi/sf_probe.c| 20 ++--
4 files changed, 28 insertions(+), 30 deletions(-)
diff --git a/drivers/mtd/spi/ramtron.c b/drivers/mtd/spi/ramtron.c
index d50da37..bdf69f7 100644
--- a/drivers/mtd/spi/ramtron.c
+++ b/drivers/mtd/spi/ramtron.c
@@ -167,7 +167,7 @@ static int ramtron_common(struct spi_flash *flash,
return ret;
}
- if (command == CMD_PAGE_PROGRAM) {
+ if (command == CMD_WR_PAGE) {
/* send WREN */
ret = spi_flash_cmd_write_enable(flash);
if (ret 0) {
@@ -177,7 +177,7 @@ static int ramtron_common(struct spi_flash *flash,
}
/* do the transaction */
- if (command == CMD_PAGE_PROGRAM)
+ if (command == CMD_WR_PAGE)
ret = spi_flash_cmd_write(flash-spi, cmd, cmd_len, buf, len);
else
ret = spi_flash_cmd_read(flash-spi, cmd, cmd_len, buf, len);
@@ -193,15 +193,13 @@ releasebus:
static int ramtron_read(struct spi_flash *flash,
u32 offset, size_t len, void *buf)
{
- return ramtron_common(flash, offset, len, buf,
- CMD_READ_ARRAY_SLOW);
+ return ramtron_common(flash, offset, len, buf, CMD_RD_SLOW);
}
static int ramtron_write(struct spi_flash *flash,
u32 offset, size_t len, const void *buf)
{
- return ramtron_common(flash, offset, len, (void *)buf,
- CMD_PAGE_PROGRAM);
+ return ramtron_common(flash, offset, len, (void *)buf, CMD_WR_PAGE);
}
static int ramtron_erase(struct spi_flash *flash, u32 offset, size_t len)
diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index a62ef4c..bebfb32 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -219,10 +219,10 @@ static int sandbox_sf_process_cmd(struct
sandbox_spi_flash *sbsf, const u8 *rx,
sbsf-state = SF_ID;
sbsf-cmd = SF_ID;
break;
- case CMD_READ_ARRAY_FAST:
+ case CMD_RD_FAST:
sbsf-pad_addr_bytes = 1;
- case CMD_READ_ARRAY_SLOW:
- case CMD_PAGE_PROGRAM:
+ case CMD_RD_SLOW:
+ case CMD_WR_PAGE:
state_addr:
sbsf-state = SF_ADDR;
break;
@@ -339,11 +339,11 @@ static int sandbox_sf_xfer(void *priv, const u8 *rx, u8
*tx,
return 1;
}
switch (sbsf-cmd) {
- case CMD_READ_ARRAY_FAST:
- case CMD_READ_ARRAY_SLOW:
+ case CMD_RD_FAST:
+ case CMD_RD_SLOW:
sbsf-state = SF_READ;
break;
- case CMD_PAGE_PROGRAM:
+ case CMD_WR_PAGE:
sbsf-state = SF_WRITE;
break;
default:
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 47d5ac2..6b6fa22 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -28,22 +28,22 @@
/* Write commands */
#define CMD_WRITE_STATUS 0x01
-#define CMD_PAGE_PROGRAM 0x02
+#define CMD_WR_PAGE0x02/* Page program */
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS0x05
-#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_WR_QUAD0x32/* Quad page program */
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
/* Read commands */
-#define CMD_READ_ARRAY_SLOW0x03
-#define CMD_READ_ARRAY_FAST0x0b
-#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
-#define CMD_READ_DUAL_IO_FAST 0xbb
-#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
-#define CMD_READ_QUAD_IO_FAST 0xeb
+#define CMD_RD_SLOW0x03/* Array slow */
+#define CMD_RD_FAST0x0b/* Array fast */
+#define CMD_RD_DUAL0x3b/* Dual output fast */
+#define CMD_RD_DUAL_IO 0xbb/* Dual IO fast */
+#define CMD_RD_QUAD0x6b/* Quad output fast */
+#define CMD_RD_QUAD_IO 0xeb/* Quad IO fast */
#define CMD_READ_ID0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 79fbad7..7ba0605 100644
--- a/drivers
[U-Boot] [PATCH 0/6] sf: Optimize spi_flash features code
Shrinked spi_slave and spi_flash code with respect to added flash features. Jagannadha Sutradharudu Teki (6): sf: ops: Squash the malloc+memset combo sf: Optimize flash features code sf: Renames on dual_flash stuff sf: Update read/write command macros sf: Minor macro cleanups sf: Update bank configuration doc/SPI/README.dual-flash | 9 ++- doc/SPI/README.sf-features| 125 ++ drivers/mtd/spi/ramtron.c | 10 +-- drivers/mtd/spi/sandbox.c | 12 +-- drivers/mtd/spi/sf.c | 4 +- drivers/mtd/spi/sf_internal.h | 37 + drivers/mtd/spi/sf_ops.c | 48 ++-- drivers/mtd/spi/sf_params.c | 172 +- drivers/mtd/spi/sf_probe.c| 138 - include/spi.h | 42 --- include/spi_flash.h | 38 +- 11 files changed, 370 insertions(+), 265 deletions(-) create mode 100644 doc/SPI/README.sf-features -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] sf: Use shortcut names
- SPI_FLASH - SF
- ARRAY_SLOW - AS
- ARRAY_FAST - AF
- DUAL_OUTPUT_FAST - DOF
- DUAL_IO_FAST - DIOF
- QUAD_OUTPUT_FAST - QOF
- QUAD_IO_FAST - QIOF
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
drivers/mtd/spi/sf_internal.h | 44 +--
drivers/mtd/spi/sf_ops.c | 25
drivers/mtd/spi/sf_probe.c| 44 +--
include/spi_flash.h | 14 +++---
4 files changed, 63 insertions(+), 64 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 6bcd522..f959262 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,15 +10,15 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
-#define SPI_FLASH_3B_ADDR_LEN 3
-#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
-#define SPI_FLASH_16MB_BOUN0x100
+#define SF_INST_3BADDR 3
+#define SF_CMD_LEN (1 + SF_INST_3BADDR)
+#define SF_16MB_BOUN 0x100
/* CFI Manufacture ID's */
-#define SPI_FLASH_CFI_MFR_SPANSION 0x01
-#define SPI_FLASH_CFI_MFR_STMICRO 0x20
-#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
-#define SPI_FLASH_CFI_MFR_WINBOND 0xef
+#define SF_CFI_MFR_SPANSION0x01
+#define SF_CFI_MFR_STMICRO 0x20
+#define SF_CFI_MFR_MACRONIX0xc2
+#define SF_CFI_MFR_WINBOND 0xef
/* Erase commands */
#define CMD_ERASE_4K 0x20
@@ -28,22 +28,22 @@
/* Write commands */
#define CMD_WRITE_STATUS 0x01
-#define CMD_PAGE_PROGRAM 0x02
+#define CMD_WRITE_PP 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS0x05
-#define CMD_QUAD_PAGE_PROGRAM 0x32
+#define CMD_WRITE_QPP 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
/* Read commands */
-#define CMD_READ_ARRAY_SLOW0x03
-#define CMD_READ_ARRAY_FAST0x0b
-#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
-#define CMD_READ_DUAL_IO_FAST 0xbb
-#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
-#define CMD_READ_QUAD_IO_FAST 0xeb
+#define CMD_READ_AS0x03
+#define CMD_READ_AF0x0b
+#define CMD_READ_DOF 0x3b
+#define CMD_READ_DIOF 0xbb
+#define CMD_READ_QOF 0x6b
+#define CMD_READ_QIOF 0xeb
#define CMD_READ_ID0x9f
/* Bank addr access commands */
@@ -55,15 +55,15 @@
#endif
/* Common status */
-#define STATUS_WIP (1 0)
-#define STATUS_QEB_WINSPAN (1 1)
-#define STATUS_QEB_MXIC(1 6)
-#define STATUS_PEC (1 7)
+#define STATUS_WIP 1 0
+#define STATUS_QEB_WINSPAN 1 1
+#define STATUS_QEB_MXIC1 6
+#define STATUS_PEC 1 7
/* Flash timeout values */
-#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
-#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
-#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
+#define SF_PROG_TIMEOUT(2 * CONFIG_SYS_HZ)
+#define SF_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
+#define SF_SECTOR_ERASE_TIMEOUT(10 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 0d87e1b..e8e70bb 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -119,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
u8 bank_sel;
int ret;
- bank_sel = offset / (SPI_FLASH_16MB_BOUN flash-shift);
+ bank_sel = offset / (SF_16MB_BOUN flash-shift);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
@@ -207,11 +207,11 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
size_t cmd_len, const void *buf, size_t buf_len)
{
struct spi_slave *spi = flash-spi;
- unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
+ unsigned long timeout = SF_PROG_TIMEOUT;
int ret;
if (buf == NULL)
- timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
+ timeout = SF_PAGE_ERASE_TIMEOUT;
ret = spi_claim_bus(flash-spi);
if (ret) {
@@ -233,9 +233,8 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
ret = spi_flash_cmd_wait_ready(flash, timeout);
if (ret 0) {
- debug(SF: write %s timed out\n,
- timeout == SPI_FLASH_PROG_TIMEOUT ?
- program
[U-Boot] [PATCH 2/3] sf: Shrink spi_slave {}
Combined spi flash stuff as minimum as possible.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
drivers/mtd/spi/sf.c | 4 ++--
drivers/mtd/spi/sf_ops.c | 18 +-
drivers/mtd/spi/sf_probe.c | 19 ---
include/spi.h | 45 +++--
include/spi_flash.h| 6 +++---
5 files changed, 45 insertions(+), 47 deletions(-)
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index 664e860..fb91ac6 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -19,8 +19,8 @@ static int spi_flash_read_write(struct spi_slave *spi,
int ret;
#ifdef CONFIG_SF_DUAL_FLASH
- if (spi-flags SPI_XFER_U_PAGE)
- flags |= SPI_XFER_U_PAGE;
+ if (spi-mode_bits SPI_U_PAGE)
+ flags |= SPI_U_PAGE;
#endif
if (data_len == 0)
flags |= SPI_XFER_END;
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 9650486..0d87e1b 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -135,15 +135,15 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
{
switch (flash-dual_flash) {
- case SF_DUAL_STACKED_FLASH:
+ case SF_STACKED:
if (*addr = (flash-size 1)) {
*addr -= flash-size 1;
- flash-spi-flags |= SPI_XFER_U_PAGE;
+ flash-spi-mode_bits |= SPI_U_PAGE;
} else {
- flash-spi-flags = ~SPI_XFER_U_PAGE;
+ flash-spi-mode_bits = ~SPI_U_PAGE;
}
break;
- case SF_DUAL_PARALLEL_FLASH:
+ case SF_PARALLEL:
*addr = flash-shift;
break;
default:
@@ -170,8 +170,8 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
}
#ifdef CONFIG_SF_DUAL_FLASH
- if (spi-flags SPI_XFER_U_PAGE)
- flags |= SPI_XFER_U_PAGE;
+ if (spi-mode_bits SPI_U_PAGE)
+ flags |= SPI_U_PAGE;
#endif
ret = spi_xfer(spi, 8, cmd, NULL, flags);
if (ret) {
@@ -261,7 +261,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len)
erase_addr = offset;
#ifdef CONFIG_SF_DUAL_FLASH
- if (flash-dual_flash SF_SINGLE_FLASH)
+ if (flash-dual_flash SF_SINGLE)
spi_flash_dual_flash(flash, erase_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
@@ -303,7 +303,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
write_addr = offset;
#ifdef CONFIG_SF_DUAL_FLASH
- if (flash-dual_flash SF_SINGLE_FLASH)
+ if (flash-dual_flash SF_SINGLE)
spi_flash_dual_flash(flash, write_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
@@ -388,7 +388,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
read_addr = offset;
#ifdef CONFIG_SF_DUAL_FLASH
- if (flash-dual_flash SF_SINGLE_FLASH)
+ if (flash-dual_flash SF_SINGLE)
spi_flash_dual_flash(flash, read_addr);
#endif
#ifdef CONFIG_SPI_FLASH_BAR
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index e84ab13..003f635 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -133,8 +133,13 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
flash-spi = spi;
flash-name = params-name;
flash-memory_map = spi-memory_map;
- flash-dual_flash = flash-spi-option;
+#ifdef CONFIG_SF_DUAL_FLASH
+ if (flash-spi-mode_bits SPI_SHARED)
+ flash-dual_flash = SF_STACKED;
+ else if (flash-spi-mode_bits SPI_SEPARATED)
+ flash-dual_flash = SF_PARALLEL;
+#endif
/* Assign spi_flash ops */
flash-write = spi_flash_cmd_write_ops;
#ifdef CONFIG_SPI_FLASH_SST
@@ -145,12 +150,12 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
flash-read = spi_flash_cmd_read_ops;
/* Compute the flash size */
- flash-shift = (flash-dual_flash SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
+ flash-shift = (flash-dual_flash SF_PARALLEL) ? 1 : 0;
flash-page_size = ((ext_jedec == 0x4d00) ? 512 : 256) flash-shift;
flash-sector_size = params-sector_size flash-shift;
flash-size = flash-sector_size * params-nr_sectors flash-shift;
#ifdef CONFIG_SF_DUAL_FLASH
- if (flash-dual_flash SF_DUAL_STACKED_FLASH)
+ if (flash-dual_flash SF_STACKED)
flash-size = 1;
#endif
@@ -167,7 +172,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
}
/* Look for the fastest read cmd */
- cmd = fls(params
[U-Boot] [PATCH 1/3] sf: ops: Squash the malloc+memset combo
Squash the malloc()+memset() combo in favor of calloc().
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
Cc: Marek Vasut ma...@denx.de
---
drivers/mtd/spi/sf_ops.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 1f1bb36..9650486 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -381,8 +381,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
}
cmdsz = SPI_FLASH_CMD_LEN + flash-dummy_byte;
- cmd = malloc(cmdsz);
- memset(cmd, 0, cmdsz);
+ cmd = calloc(1, cmdsz);
cmd[0] = flash-read_cmd;
while (len) {
--
1.8.3
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[U-Boot] Pull request: u-boot-spi/master
Hi Tom, PR have quad and dual_flash change set also includes few fixes. Tested these changes on spansion, stmicro and sst flash devices. -- Thanks, Jagan. The following changes since commit 7f673c99c2d8d1aa21996c5b914f06d784b080ca: Merge branch 'master' of git://git.denx.de/u-boot-arm (2014-01-10 10:56:00 -0500) are available in the git repository at: git://git.denx.de/u-boot-spi.git master for you to fetch changes up to 35a55fb57fffb615e6b20980fb317e162076adb4: sf: params: Removed flag SECT_4K for Micron N25Q128 (2014-01-12 21:40:23 +0530) Axel Lin (1): spi: sh_spi: Use sh_spi_clear_bit() instead of open-coded Jagannadha Sutradharudu Teki (17): sf: Add extended read commands support sf: Add quad read/write commands support sf: ops: Add configuration register writing support sf: Set quad enable bit support sf: probe: Enable RD_FULL and WR_QPP sf: Separate the flash params table sf: Add QUAD_IO_FAST read support sf: Discover read dummy_byte sf: Add macronix set QEB support sf: probe: Enable macronix quad read/write cmds support sf: Divide flash register ops from QEB code sf: Code cleanups sf: ops: Unify read_ops bank configuration sf: Add dual memories support - DUAL_STACKED sf: Add dual memories support - DUAL_PARALLEL sf: Add CONFIG_SF_DUAL_FLASH doc: SPI: Update status.txt Kuo-Jung Su (1): spi: Add Faraday SPI controller support Simon Glass (1): sandbox: spi: Adjust 'sf test' to work on sandbox Siva Durga Prasad Paladugu (1): sf: params: Removed flag SECT_4K for Micron N25Q128 README | 6 + common/cmd_sf.c | 14 +- doc/SPI/README.dual-flash| 92 +++ doc/SPI/README.ftssp010_spi_test | 41 doc/SPI/status.txt | 11 +- drivers/mtd/spi/Makefile | 4 +- drivers/mtd/spi/sf.c | 4 + drivers/mtd/spi/sf_internal.h| 34 ++- drivers/mtd/spi/sf_ops.c | 157 +--- drivers/mtd/spi/sf_params.c | 130 ++ drivers/mtd/spi/sf_probe.c | 274 +++-- drivers/spi/Makefile | 1 + drivers/spi/ftssp010_spi.c | 508 +++ drivers/spi/sh_spi.c | 10 +- include/spi.h| 26 ++ include/spi_flash.h | 57 + 16 files changed, 1171 insertions(+), 198 deletions(-) create mode 100644 doc/SPI/README.dual-flash create mode 100644 doc/SPI/README.ftssp010_spi_test create mode 100644 drivers/mtd/spi/sf_params.c create mode 100644 drivers/spi/ftssp010_spi.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7 03/17] sf: ops: Add configuration register writing support
This patch provides support to program a flash config register.
Configuration register contains the control bits used to configure
the different configurations and security features of a device.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_ops.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 3d304ce..39e06ec 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -38,6 +38,30 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr)
return 0;
}
+static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
+{
+ u8 data[2];
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, cmd, 1, data[0], 1);
+ if (ret 0) {
+ debug(SF: fail to read status register\n);
+ return ret;
+ }
+
+ cmd = CMD_WRITE_STATUS;
+ data[1] = cr;
+ ret = spi_flash_write_common(flash, cmd, 1, data, 2);
+ if (ret) {
+ debug(SF: fail to write config register\n);
+ return ret;
+ }
+
+ return 0;
+}
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
--
1.8.3
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[U-Boot] [PATCH v7 09/17] sf: Add macronix set QEB support
This patch adds set QEB support for macronix flash devices
which are trying to program/read quad operations.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 5 +
drivers/mtd/spi/sf_ops.c | 26 ++
drivers/mtd/spi/sf_probe.c| 4
3 files changed, 35 insertions(+)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index a9f5a81..c69b53d 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -17,6 +17,7 @@
/* CFI Manufacture ID's */
#define SPI_FLASH_CFI_MFR_SPANSION 0x01
#define SPI_FLASH_CFI_MFR_STMICRO 0x20
+#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
#define SPI_FLASH_CFI_MFR_WINBOND 0xef
/* SECT flags */
@@ -61,6 +62,7 @@
/* Common status */
#define STATUS_WIP 0x01
#define STATUS_QEB_WINSPAN (1 1)
+#define STATUS_QEB_MXIC(1 6)
#define STATUS_PEC 0x80
/* Flash timeout values */
@@ -102,6 +104,9 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len);
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+/* Set quad enbale bit for macronix flashes */
+int spi_flash_set_qeb_mxic(struct spi_flash *flash);
+
/* Set quad enbale bit for winbond and spansion flashes */
int spi_flash_set_qeb_winspan(struct spi_flash *flash);
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 6adee32..05fbcbd 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -39,6 +39,32 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8
sr)
return 0;
}
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, cmd, 1, qeb_status, 1);
+ if (ret 0) {
+ debug(SF: fail to read status register\n);
+ return ret;
+ }
+
+ if (qeb_status STATUS_QEB_MXIC) {
+ debug(SF: Quad enable bit is already set\n);
+ } else {
+ ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
+ if (ret 0)
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
{
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 8bd06ee..88d1d0a 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -31,6 +31,10 @@ static u8 spi_read_cmds_array[] = {
static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
{
switch (idcode0) {
+#ifdef CONFIG_SPI_FLASH_MACRONIX
+ case SPI_FLASH_CFI_MFR_MACRONIX:
+ return spi_flash_set_qeb_mxic(flash);
+#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
--
1.8.3
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[U-Boot] [PATCH v7 17/17] doc: SPI: Update status.txt
Updated current SPI subsyetem status. Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com --- doc/SPI/status.txt | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/doc/SPI/status.txt b/doc/SPI/status.txt index 62c3c85..13889f5 100644 --- a/doc/SPI/status.txt +++ b/doc/SPI/status.txt @@ -11,6 +11,11 @@ SPI FLASH (drivers/mtd/spi): - Bank Address Register (Accessing flashes 16Mbytes in 3-byte addressing) - Added memory_mapped support for read operations. - Common probe support for all supported flash vendors except, ramtron. +- Extended read commands support(dual read, dual IO read) +- Quad Page Program support. +- Quad Read support(quad fast read, quad IO read) +- Dual flash connection topology support(accessing two spi flash memories with single cs) +- Banking support on dual flash connection topology. SPI DRIVERS (drivers/spi): - @@ -18,14 +23,10 @@ SPI DRIVERS (drivers/spi): TODO: - Runtime detection of spi_flash params, SFDP(if possible) - Add support for multibus build/accessing. -- Extended read commands support(dual read, dual IO read) -- Quad Page Program support. -- Quad Read support(quad fast read, quad IO read) -- Dual flash connection topology support(accessing two spi flash memories with single cs) -- Banking support on dual flash connection topology. - Need proper cleanups on spi_flash and drivers. -- Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com 18-09-2013. 07-10-2013. +08-01-2014. -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7 14/17] sf: Add dual memories support - DUAL_STACKED
This patch added support for accessing dual memories in
stacked connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
doc/SPI/README.dual-flash | 65 ++
drivers/mtd/spi/sf.c | 3 +++
drivers/mtd/spi/sf_ops.c | 57 +---
drivers/mtd/spi/sf_probe.c | 8 +-
include/spi.h | 8 ++
include/spi_flash.h| 8 ++
6 files changed, 138 insertions(+), 11 deletions(-)
create mode 100644 doc/SPI/README.dual-flash
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
new file mode 100644
index 000..ba0aa26
--- /dev/null
+++ b/doc/SPI/README.dual-flash
@@ -0,0 +1,65 @@
+SPI/QSPI Dual flash connection modes:
+=
+
+This describes how SPI/QSPI flash memories are connected to a given
+controller in a single chip select line.
+
+Current spi_flash framework supports, single flash memory connected
+to a given controller with single chip select line, but there are some
+hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
+connected with a single chip select line from a controller.
+
+dual_flash from include/spi.h describes these types of connection mode
+
+Possible connections:
+
+SF_SINGLE_FLASH:
+ - single spi flash memory connected with single chip select line.
+
+ ++ CS +---+
+ ||---| |
+ | Controller | I0[3:0]| Flash memory |
+ | SPI/QSPI |==| (SPI/QSPI)|
+ || CLK | |
+ ||---| |
+ +++---+
+
+SF_DUAL_STACKED_FLASH:
+ - dual spi/qspi flash memories are connected with a single chipselect
+ line and these two memories are operating stacked fasion with shared
buses.
+ - xilinx zynq qspi controller has implemented this feature [1]
+
+ ++CS +---+
+ ||--| |
+ || I0[3:0] | Upper Flash |
+ ||+=| memory|
+ ||| CLK | (SPI/QSPI)|
+ |||+| |
+ | Controller |CS || +---+
+ | SPI/QSPI |||| |
+ ||I0[3:0] || | Lower Flash |
+ ||===+|| memory|
+ || CLK| | (SPI/QSPI)|
+ ||-+| |
+ ++ +---+
+
+ - two memory flash devices should has same hw part attributes (like
size,
+ vendor..etc)
+ - Configurations:
+ on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
+ Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
+ Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
+ - Operation:
+ accessing memories serially like one after another.
+ by default, if U_PAGE is unset lower memory should accessible,
+ once user wants to access upper memory need to set U_PAGE.
+
+Note: Technically there is only one CS line from the controller, but
+zynq qspi controller has an internal hw logic to enable additional CS
+when controller is configured for dual memories.
+
+[1]
http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
+
+--
+Jagannadha Sutradharudu Teki jaga...@xilinx.com
+05-01-2014.
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index d5e175c..c780a81 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -18,6 +18,9 @@ static int spi_flash_read_write(struct spi_slave *spi,
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ if (spi-flags SPI_XFER_U_PAGE)
+ flags |= SPI_XFER_U_PAGE;
+
if (data_len == 0)
flags |= SPI_XFER_END;
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 7ae9582..e877858 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -131,10 +131,28 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
}
#endif
+static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
+{
+ switch (flash-dual_flash) {
+ case SF_DUAL_STACKED_FLASH:
+ if (*addr = (flash-size 1)) {
+ *addr -= flash-size 1;
+ flash-spi-flags |= SPI_XFER_U_PAGE;
+ } else {
+ flash-spi-flags = ~SPI_XFER_U_PAGE;
+ }
+ break;
+ default
[U-Boot] [PATCH v7 02/17] sf: Add quad read/write commands support
This patch add quad commands support like
- QUAD_PAGE_PROGRAM = for write program
- QUAD_OUTPUT_FAST - for read program
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 2 +
drivers/mtd/spi/sf_ops.c | 2 +-
drivers/mtd/spi/sf_probe.c| 178 ++
include/spi.h | 9 ++-
include/spi_flash.h | 11 ++-
5 files changed, 113 insertions(+), 89 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 938a78e..dcc9014 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -28,6 +28,7 @@
#define CMD_PAGE_PROGRAM 0x02
#define CMD_WRITE_DISABLE 0x04
#define CMD_READ_STATUS0x05
+#define CMD_QUAD_PAGE_PROGRAM 0x32
#define CMD_READ_STATUS1 0x35
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
@@ -38,6 +39,7 @@
#define CMD_READ_ARRAY_FAST0x0b
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_DUAL_IO_FAST 0xbb
+#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
#define CMD_READ_ID0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 49ceef0..3d304ce 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -210,7 +210,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
page_size = flash-page_size;
- cmd[0] = CMD_PAGE_PROGRAM;
+ cmd[0] = flash-write_cmd;
for (actual = 0; actual len; actual += chunk_len) {
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, offset);
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index c0baac6..3fa7363 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -42,105 +42,105 @@ struct spi_flash_params {
static const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, 0,
SECT_4K},
- {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, 0,
SECT_4K},
- {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, 0,
SECT_4K},
- {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, 0,
SECT_4K},
- {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, 0,
SECT_4K},
- {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, 0,
SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, 0,
SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, 0,
SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, 0,
SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, 0,
SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, 0,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
- {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, 0,
0},
- {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, 0,
0},
- {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, 0,
0},
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, 0,
0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, 0,
0},
+ {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, 0,
0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, 0,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX
[U-Boot] [PATCH v7 08/17] sf: Discover read dummy_byte
Discovered the read dummy_byte based on the
configured read command.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 2 ++
drivers/mtd/spi/sf_ops.c | 16 +---
drivers/mtd/spi/sf_probe.c| 19 +++
include/spi_flash.h | 2 ++
4 files changed, 32 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 7be0292..a9f5a81 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,6 +10,8 @@
#ifndef _SF_INTERNAL_H_
#define _SF_INTERNAL_H_
+#define SPI_FLASH_3B_ADDR_LEN 3
+#define SPI_FLASH_CMD_LEN (1 + SPI_FLASH_3B_ADDR_LEN)
#define SPI_FLASH_16MB_BOUN0x100
/* CFI Manufacture ID's */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 827f719..6adee32 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -9,6 +9,7 @@
*/
#include common.h
+#include malloc.h
#include spi.h
#include spi_flash.h
#include watchdog.h
@@ -216,7 +217,7 @@ int spi_flash_write_common(struct spi_flash *flash, const
u8 *cmd,
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
erase_size = flash-erase_size;
@@ -255,7 +256,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
{
unsigned long byte_addr, page_size;
size_t chunk_len, actual;
- u8 cmd[4];
+ u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
page_size = flash-page_size;
@@ -317,7 +318,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 cmd[5], bank_sel = 0;
+ u8 *cmd, cmdsz, bank_sel = 0;
u32 remain_len, read_len;
int ret = -1;
@@ -335,9 +336,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
return 0;
}
- cmd[0] = flash-read_cmd;
- cmd[4] = 0x00;
+ cmdsz = SPI_FLASH_CMD_LEN + flash-dummy_byte;
+ cmd = malloc(cmdsz);
+ memset(cmd, 0, cmdsz);
+ cmd[0] = flash-read_cmd;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = offset / SPI_FLASH_16MB_BOUN;
@@ -356,8 +359,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
spi_flash_addr(offset, cmd);
- ret = spi_flash_read_common(flash, cmd, sizeof(cmd),
- data, read_len);
+ ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
if (ret 0) {
debug(SF: read failed\n);
break;
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index a049e72..8bd06ee 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -140,6 +140,25 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
}
}
+ /* Read dummy_byte: dummy byte is determined based on the
+* dummy cycles of a particular command.
+* Fast commands - dummy_byte = dummy_cycles/8
+* I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
+* For I/O commands except cmd[0] everything goes on no.of lines
+* based on particular command but incase of fast commands except
+* data all go on single line irrespective of command.
+*/
+ switch (flash-read_cmd) {
+ case CMD_READ_QUAD_IO_FAST:
+ flash-dummy_byte = 2;
+ break;
+ case CMD_READ_ARRAY_SLOW:
+ flash-dummy_byte = 0;
+ break;
+ default:
+ flash-dummy_byte = 1;
+ }
+
/* Poll cmd seclection */
flash-poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 99724a0..437937c 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -72,6 +72,7 @@ extern const struct spi_flash_params spi_flash_params_table[];
* @erase_cmd: Erase cmd 4K, 32K, 64K
* @read_cmd: Read cmd - Array Fast, Extn read and quad read.
* @write_cmd: Write cmd - page and quad program.
+ * @dummy_byte:Dummy cycles for read operation.
* @memory_map:Address of read-only SPI flash access
* @read: Flash read ops: Read len bytes at offset into buf
* Supported cmds: Fast Array Read
@@ -98,6 +99,7 @@ struct spi_flash {
u8 erase_cmd;
u8 read_cmd;
u8 write_cmd;
+ u8 dummy_byte;
void *memory_map;
int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
--
1.8.3
[U-Boot] [PATCH v7 10/17] sf: probe: Enable macronix quad read/write cmds support
Added macronix flash quad read/write commands support and
it's up to the respective controller driver usecase to
configure the respective commands by defining SPI RX/TX
operation modes from include/spi.h on the driver.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_params.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index ad101fb..4cdb4c2 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -40,10 +40,10 @@ const struct spi_flash_params spi_flash_params_table[] = {
{MX25L1605D, 0xc22015, 0x0, 64 * 1024,32, 0,
0},
{MX25L3205D, 0xc22016, 0x0, 64 * 1024,64, 0,
0},
{MX25L6405D, 0xc22017, 0x0, 64 * 1024, 128, 0,
0},
- {MX25L12805, 0xc22018, 0x0, 64 * 1024, 256, 0,
0},
- {MX25L25635F,0xc22019, 0x0, 64 * 1024, 512, 0,
0},
- {MX25L51235F,0xc2201a, 0x0, 64 * 1024, 1024, 0,
0},
- {MX25L12855E,0xc22618, 0x0, 64 * 1024, 256, 0,
0},
+ {MX25L12805, 0xc22018, 0x0, 64 * 1024, 256, RD_FULL,
WR_QPP},
+ {MX25L25635F,0xc22019, 0x0, 64 * 1024, 512, RD_FULL,
WR_QPP},
+ {MX25L51235F,0xc2201a, 0x0, 64 * 1024, 1024, RD_FULL,
WR_QPP},
+ {MX25L12855E,0xc22618, 0x0, 64 * 1024, 256, RD_FULL,
WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
{S25FL008A, 0x010213, 0x0, 64 * 1024,16, 0,
0},
--
1.8.3
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7 06/17] sf: Separate the flash params table
Moved the flash params table from sf_probe.c and
placed on to sf_params.c, hence flash params file will
alter based on new addons.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/Makefile| 4 +-
drivers/mtd/spi/sf_params.c | 130 +++
drivers/mtd/spi/sf_probe.c | 146 +---
include/spi_flash.h | 23 +++
4 files changed, 158 insertions(+), 145 deletions(-)
create mode 100644 drivers/mtd/spi/sf_params.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 26483a2..9e18fb4 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -10,8 +10,8 @@ obj-$(CONFIG_SPL_SPI_LOAD)+= spi_spl_load.o
obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
-obj-$(CONFIG_CMD_SF)+= sf.o
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o sf_ops.o
+obj-$(CONFIG_CMD_SF) += sf.o
+obj-$(CONFIG_SPI_FLASH) += sf_params.o sf_probe.o sf_ops.o
obj-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
new file mode 100644
index 000..ad101fb
--- /dev/null
+++ b/drivers/mtd/spi/sf_params.c
@@ -0,0 +1,130 @@
+/*
+ * SPI flash Params table
+ *
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include spi_flash.h
+
+#include sf_internal.h
+
+/* SPI/QSPI flash device params structure */
+const struct spi_flash_params spi_flash_params_table[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, 0,
SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, 0,
SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, 0,
SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, 0,
SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, 0,
SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, 0,
SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_EON/* EON */
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, 0,
0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, 0,
0},
+ {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, 0,
0},
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, 0,
SECT_4K},
+#endif
+#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
+ {MX25L2006E, 0xc22012, 0x0, 64 * 1024, 4, 0,
0},
+ {MX25L4005, 0xc22013, 0x0, 64 * 1024, 8, 0,
0},
+ {MX25L8005, 0xc22014, 0x0, 64 * 1024,16, 0,
0},
+ {MX25L1605D, 0xc22015, 0x0, 64 * 1024,32, 0,
0},
+ {MX25L3205D, 0xc22016, 0x0, 64 * 1024,64, 0,
0},
+ {MX25L6405D, 0xc22017, 0x0, 64 * 1024, 128, 0,
0},
+ {MX25L12805, 0xc22018, 0x0, 64 * 1024, 256, 0,
0},
+ {MX25L25635F,0xc22019, 0x0, 64 * 1024, 512, 0,
0},
+ {MX25L51235F,0xc2201a, 0x0, 64 * 1024, 1024, 0,
0},
+ {MX25L12855E,0xc22618, 0x0, 64 * 1024, 256, 0,
0},
+#endif
+#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
+ {S25FL008A, 0x010213, 0x0, 64 * 1024,16, 0,
0},
+ {S25FL016A, 0x010214, 0x0, 64 * 1024,32, 0,
0},
+ {S25FL032A, 0x010215, 0x0, 64 * 1024,64, 0,
0},
+ {S25FL064A, 0x010216, 0x0, 64 * 1024, 128, 0,
0},
+ {S25FL128P_256K, 0x012018, 0x0300, 256 * 1024,64, RD_FULL,
WR_QPP},
+ {S25FL128P_64K, 0x012018, 0x0301,64 * 1024, 256, RD_FULL,
WR_QPP},
+ {S25FL032P
[U-Boot] [PATCH v7 16/17] sf: Add CONFIG_SF_DUAL_FLASH
This config will use for defining greater than single flash support.
currently - DUAL_STACKED and DUAL_PARALLEL.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
README | 6 ++
drivers/mtd/spi/sf.c | 3 ++-
drivers/mtd/spi/sf_ops.c | 14 ++
drivers/mtd/spi/sf_probe.c | 2 ++
4 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/README b/README
index a0646c3..aea82be 100644
--- a/README
+++ b/README
@@ -2756,6 +2756,12 @@ CBFS (Coreboot Filesystem) support
Define this option to use the Bank addr/Extended addr
support on SPI flashes which has size 16Mbytes.
+ CONFIG_SF_DUAL_FLASHDual flash memories
+
+ Define this option to use dual flash support where two flash
+ memories can be connected with a given cs line.
+ currently Xilinx Zynq qspi support these type of connections.
+
- SystemACE Support:
CONFIG_SYSTEMACE
diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index c780a81..664e860 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -18,9 +18,10 @@ static int spi_flash_read_write(struct spi_slave *spi,
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+#ifdef CONFIG_SF_DUAL_FLASH
if (spi-flags SPI_XFER_U_PAGE)
flags |= SPI_XFER_U_PAGE;
-
+#endif
if (data_len == 0)
flags |= SPI_XFER_END;
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 843f379..1f1bb36 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -131,6 +131,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
}
#endif
+#ifdef CONFIG_SF_DUAL_FLASH
static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
{
switch (flash-dual_flash) {
@@ -150,6 +151,7 @@ static void spi_flash_dual_flash(struct spi_flash *flash,
u32 *addr)
break;
}
}
+#endif
int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
{
@@ -167,9 +169,10 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
check_status = poll_bit;
}
+#ifdef CONFIG_SF_DUAL_FLASH
if (spi-flags SPI_XFER_U_PAGE)
flags |= SPI_XFER_U_PAGE;
-
+#endif
ret = spi_xfer(spi, 8, cmd, NULL, flags);
if (ret) {
debug(SF: fail to read %s status register\n,
@@ -257,9 +260,10 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len)
while (len) {
erase_addr = offset;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash-dual_flash SF_SINGLE_FLASH)
spi_flash_dual_flash(flash, erase_addr);
-
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, erase_addr);
if (ret 0)
@@ -298,9 +302,10 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
for (actual = 0; actual len; actual += chunk_len) {
write_addr = offset;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash-dual_flash SF_SINGLE_FLASH)
spi_flash_dual_flash(flash, write_addr);
-
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
ret = spi_flash_bank(flash, write_addr);
if (ret 0)
@@ -383,9 +388,10 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
while (len) {
read_addr = offset;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash-dual_flash SF_SINGLE_FLASH)
spi_flash_dual_flash(flash, read_addr);
-
+#endif
#ifdef CONFIG_SPI_FLASH_BAR
bank_sel = spi_flash_bank(flash, read_addr);
if (bank_sel 0)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 48de7c1..bc3cf6c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -150,8 +150,10 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
flash-page_size = ((ext_jedec == 0x4d00) ? 512 : 256) flash-shift;
flash-sector_size = params-sector_size flash-shift;
flash-size = flash-sector_size * params-nr_sectors flash-shift;
+#ifdef CONFIG_SF_DUAL_FLASH
if (flash-dual_flash SF_DUAL_STACKED_FLASH)
flash-size = 1;
+#endif
/* Compute erase sector and command */
if (params-flags SECT_4K) {
--
1.8.3
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[U-Boot] [PATCH v7 04/17] sf: Set quad enable bit support
This patch provides support to set the quad enable bit on flash.
quad enable bit needs to set before performing any quad IO
operations on respective SPI flashes.
Currently added set quad enable bit for winbond and spansion flash
devices. stmicro flash doesn't require to set as qeb is volatile.
remaining flash devices support will add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 10 --
drivers/mtd/spi/sf_ops.c | 26 ++
drivers/mtd/spi/sf_probe.c| 28
3 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index dcc9014..dca34f7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -12,6 +12,11 @@
#define SPI_FLASH_16MB_BOUN0x100
+/* CFI Manufacture ID's */
+#define SPI_FLASH_CFI_MFR_SPANSION 0x01
+#define SPI_FLASH_CFI_MFR_STMICRO 0x20
+#define SPI_FLASH_CFI_MFR_WINBOND 0xef
+
/* SECT flags */
#define SECT_4K(1 1)
#define SECT_32K (1 2)
@@ -52,6 +57,7 @@
/* Common status */
#define STATUS_WIP 0x01
+#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_PEC 0x80
/* Flash timeout values */
@@ -93,8 +99,8 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len);
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-/* Set quad enbale bit */
-int spi_flash_set_qeb(struct spi_flash *flash);
+/* Set quad enbale bit for winbond and spansion flashes */
+int spi_flash_set_qeb_winspan(struct spi_flash *flash);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 39e06ec..827f719 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -38,6 +38,7 @@ int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
return 0;
}
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
{
u8 data[2];
@@ -62,6 +63,31 @@ static int spi_flash_cmd_write_config(struct spi_flash
*flash, u8 cr)
return 0;
}
+int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+{
+ u8 qeb_status;
+ u8 cmd;
+ int ret;
+
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash, cmd, 1, qeb_status, 1);
+ if (ret 0) {
+ debug(SF: fail to read config register\n);
+ return ret;
+ }
+
+ if (qeb_status STATUS_QEB_WINSPAN) {
+ debug(SF: Quad enable bit is already set\n);
+ } else {
+ ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
+ if (ret 0)
+ return ret;
+ }
+
+ return ret;
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 3fa7363..8b2972c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -165,6 +165,25 @@ static u8 spi_read_cmds_array[] = {
CMD_READ_QUAD_OUTPUT_FAST,
};
+static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
+{
+ switch (idcode0) {
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+ case SPI_FLASH_CFI_MFR_SPANSION:
+ case SPI_FLASH_CFI_MFR_WINBOND:
+ return spi_flash_set_qeb_winspan(flash);
+#endif
+#ifdef CONFIG_SPI_FLASH_STMICRO
+ case SPI_FLASH_CFI_MFR_STMICRO:
+ debug(SF: QEB is volatile for %02x flash\n, idcode0);
+ return 0;
+#endif
+ default:
+ printf(SF: Need set QEB func for %02x flash\n, idcode0);
+ return -1;
+ }
+}
+
static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
u8 *idcode)
{
@@ -250,6 +269,15 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
/* Go for default supported write cmd */
flash-write_cmd = CMD_PAGE_PROGRAM;
+ /* Set the quad enable bit - only for quad commands */
+ if ((flash-read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash-write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_set_qeb(flash, idcode[0])) {
+ debug(SF: Fail to set QEB for %02x\n, idcode[0]);
+ return NULL;
+ }
+ }
+
/* Poll cmd seclection */
flash-poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
--
1.8.3
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[U-Boot] [PATCH v7 07/17] sf: Add QUAD_IO_FAST read support
This patch adds support QUAD_IO_FAST read command.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/sf_probe.c| 2 ++
include/spi.h | 4 +++-
include/spi_flash.h | 3 ++-
4 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index dca34f7..7be0292 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -45,6 +45,7 @@
#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
#define CMD_READ_DUAL_IO_FAST 0xbb
#define CMD_READ_QUAD_OUTPUT_FAST 0x6b
+#define CMD_READ_QUAD_IO_FAST 0xeb
#define CMD_READ_ID0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index d95c8b9..a049e72 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -25,6 +25,7 @@ static u8 spi_read_cmds_array[] = {
CMD_READ_DUAL_OUTPUT_FAST,
CMD_READ_DUAL_IO_FAST,
CMD_READ_QUAD_OUTPUT_FAST,
+ CMD_READ_QUAD_IO_FAST,
};
static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
@@ -131,6 +132,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
/* Set the quad enable bit - only for quad commands */
if ((flash-read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash-read_cmd == CMD_READ_QUAD_IO_FAST) ||
(flash-write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
if (spi_flash_set_qeb(flash, idcode[0])) {
debug(SF: Fail to set QEB for %02x\n, idcode[0]);
diff --git a/include/spi.h b/include/spi.h
index 5dd490a..c8a9d87 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -39,8 +39,10 @@
#define SPI_OPM_RX_DOUT1 1
#define SPI_OPM_RX_DIO 1 2
#define SPI_OPM_RX_QOF 1 3
+#define SPI_OPM_RX_QIOF1 4
#define SPI_OPM_RX_EXTNSPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
- SPI_OPM_RX_DIO | SPI_OPM_RX_QOF
+ SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
+ SPI_OPM_RX_QIOF
/* Header byte that marks the start of the message */
#define SPI_PREAMBLE_END_BYTE 0xec
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 8e0bb46..99724a0 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -28,9 +28,10 @@ enum spi_read_cmds {
DUAL_OUTPUT_FAST = 1 1,
DUAL_IO_FAST = 1 2,
QUAD_OUTPUT_FAST = 1 3,
+ QUAD_IO_FAST = 1 4,
};
#define RD_EXTNARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
-#define RD_FULLRD_EXTN | QUAD_OUTPUT_FAST
+#define RD_FULLRD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
/**
* struct spi_flash_params - SPI/QSPI flash device params structure
--
1.8.3
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[U-Boot] [PATCH v7 00/17] sf: Add support for quad and dual_flash
This series is a combo of quad cmds and dual_flash support Refer [1] and [2] for more functional description about this changes. [1] http://u-boot.10912.n7.nabble.com/PATCH-v6-00-12-sf-Add-Extended-read-and-quad-read-write-commands-support-td170645.html [2] http://u-boot.10912.n7.nabble.com/PATCH-v3-0-4-sf-Add-support-to-access-dual-flash-memory-td170760.html Tested on sst, stmicro and spansion flash. Testing branch: $ git clone git://git.denx.de/u-boot-spi.git $ cd u-boot-spi $ git checkout -b master-quad origin/master-quad REQUEST FOR ALL SPI CODE CONTRIBUTORS/USERS, PLEASE TEST THESE CHANGES W.R.T YOUR HW IF POSSIBLE. Please let me know for any issues/concerns/questions. -- Thanks, Jagan. Changes for v7: - cmdsz on read_ops - sf param flags are placed spi_flash.h - code cleanup - updated dual_flash with BAR support Changes for v6: - Divided flash reg ops code - sf_ops.c clean Changes for v5: - Re-implemented write command log - not trying to discover the fastest write - Added SPI RX/TX operation modes - SPI flash parts are moved into sf_params.c file - Added QUAD_IO_FAST read support - Discovred the read dummy_cycles based on configured read cmd - Added set QEB support for macronix flash - Enabled quad read/write cmd support for macronix flash Changes for v4: Changes for v3: Changes for v2: - none Jagannadha Sutradharudu Teki (17): sf: Add extended read commands support sf: Add quad read/write commands support sf: ops: Add configuration register writing support sf: Set quad enable bit support sf: probe: Enable RD_FULL and WR_QPP sf: Separate the flash params table sf: Add QUAD_IO_FAST read support sf: Discover read dummy_byte sf: Add macronix set QEB support sf: probe: Enable macronix quad read/write cmds support sf: Divide flash register ops from QEB code sf: Code cleanups sf: ops: Unify read_ops bank configuration sf: Add dual memories support - DUAL_STACKED sf: Add dual memories support - DUAL_PARALLEL sf: Add CONFIG_SF_DUAL_FLASH doc: SPI: Update status.txt README| 6 + doc/SPI/README.dual-flash | 92 ++ doc/SPI/status.txt| 11 +- drivers/mtd/spi/Makefile | 4 +- drivers/mtd/spi/sf.c | 4 + drivers/mtd/spi/sf_internal.h | 34 -- drivers/mtd/spi/sf_ops.c | 157 +++- drivers/mtd/spi/sf_params.c | 130 drivers/mtd/spi/sf_probe.c| 274 +- include/spi.h | 26 include/spi_flash.h | 57 + 11 files changed, 610 insertions(+), 185 deletions(-) create mode 100644 doc/SPI/README.dual-flash create mode 100644 drivers/mtd/spi/sf_params.c -- 1.8.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7 05/17] sf: probe: Enable RD_FULL and WR_QPP
This patch enabled RD_FULL and WR_QPP for supported flashes
in micron, winbond and spansion.
Remaining parts will be add in future patches.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_probe.c | 60 +++---
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 8b2972c..f24bc1b 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -78,15 +78,15 @@ static const struct spi_flash_params
spi_flash_params_table[] = {
{S25FL016A, 0x010214, 0x0, 64 * 1024,32, 0,
0},
{S25FL032A, 0x010215, 0x0, 64 * 1024,64, 0,
0},
{S25FL064A, 0x010216, 0x0, 64 * 1024, 128, 0,
0},
- {S25FL128P_256K, 0x012018, 0x0300, 256 * 1024,64, 0,
0},
- {S25FL128P_64K, 0x012018, 0x0301,64 * 1024, 256, 0,
0},
- {S25FL032P, 0x010215, 0x4d00,64 * 1024,64, 0,
0},
- {S25FL064P, 0x010216, 0x4d00,64 * 1024, 128, 0,
0},
- {S25FL128S_64K, 0x012018, 0x4d01,64 * 1024, 256, 0,
0},
+ {S25FL128P_256K, 0x012018, 0x0300, 256 * 1024,64, RD_FULL,
WR_QPP},
+ {S25FL128P_64K, 0x012018, 0x0301,64 * 1024, 256, RD_FULL,
WR_QPP},
+ {S25FL032P, 0x010215, 0x4d00,64 * 1024,64, RD_FULL,
WR_QPP},
+ {S25FL064P, 0x010216, 0x4d00,64 * 1024, 128, RD_FULL,
WR_QPP},
+ {S25FL128S_64K, 0x012018, 0x4d01,64 * 1024, 256, RD_FULL,
WR_QPP},
{S25FL256S_256K, 0x010219, 0x4d00,64 * 1024, 512, RD_FULL,
WR_QPP},
{S25FL256S_64K, 0x010219, 0x4d01,64 * 1024, 512, RD_FULL,
WR_QPP},
- {S25FL512S_256K, 0x010220, 0x4d00,64 * 1024, 1024, 0,
0},
- {S25FL512S_64K, 0x010220, 0x4d01,64 * 1024, 1024, 0,
0},
+ {S25FL512S_256K, 0x010220, 0x4d00,64 * 1024, 1024, RD_FULL,
WR_QPP},
+ {S25FL512S_64K, 0x010220, 0x4d01,64 * 1024, 1024, RD_FULL,
WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO/* STMICRO */
{M25P10, 0x202011, 0x0, 32 * 1024, 4, 0,
0},
@@ -97,18 +97,18 @@ static const struct spi_flash_params
spi_flash_params_table[] = {
{M25P32, 0x202016, 0x0, 64 * 1024,64, 0,
0},
{M25P64, 0x202017, 0x0, 64 * 1024, 128, 0,
0},
{M25P128,0x202018, 0x0, 256 * 1024,64, 0,
0},
- {N25Q32, 0x20ba16, 0x0, 64 * 1024,64, 0,
SECT_4K},
- {N25Q32A,0x20bb16, 0x0, 64 * 1024,64, 0,
SECT_4K},
- {N25Q64, 0x20ba17, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {N25Q64A,0x20bb17, 0x0, 64 * 1024, 128, 0,
SECT_4K},
- {N25Q128,0x20ba18, 0x0, 64 * 1024, 256, 0,
SECT_4K},
- {N25Q128A, 0x20bb18, 0x0, 64 * 1024, 256, 0,
SECT_4K},
- {N25Q256,0x20ba19, 0x0, 64 * 1024, 512, 0,
SECT_4K},
- {N25Q256A, 0x20bb19, 0x0, 64 * 1024, 512, 0,
SECT_4K},
- {N25Q512,0x20ba20, 0x0, 64 * 1024, 1024, 0,
E_FSR | SECT_4K},
- {N25Q512A, 0x20bb20, 0x0, 64 * 1024, 1024, 0,
E_FSR | SECT_4K},
- {N25Q1024, 0x20ba21, 0x0, 64 * 1024, 2048, 0,
E_FSR | SECT_4K},
- {N25Q1024A, 0x20bb21, 0x0, 64 * 1024, 2048, 0,
E_FSR | SECT_4K},
+ {N25Q32, 0x20ba16, 0x0, 64 * 1024,64, RD_FULL,
WR_QPP | SECT_4K},
+ {N25Q32A,0x20bb16, 0x0, 64 * 1024,64, RD_FULL,
WR_QPP | SECT_4K},
+ {N25Q64, 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL,
WR_QPP | SECT_4K},
+ {N25Q64A,0x20bb17, 0x0, 64 * 1024, 128, RD_FULL,
WR_QPP | SECT_4K},
+ {N25Q128,0x20ba18, 0x0, 64 * 1024, 256, RD_FULL,
WR_QPP | SECT_4K},
+ {N25Q128A, 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL,
WR_QPP | SECT_4K},
+ {N25Q256,0x20ba19, 0x0, 64 * 1024, 512, RD_FULL,
WR_QPP | SECT_4K
[U-Boot] [PATCH v7 12/17] sf: Code cleanups
- comment typo's
- func args have a proper names
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 11 +++
drivers/mtd/spi/sf_ops.c | 6 +++---
drivers/mtd/spi/sf_probe.c| 4 ++--
include/spi_flash.h | 5 -
4 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index c77961f..6bcd522 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -20,11 +20,6 @@
#define SPI_FLASH_CFI_MFR_MACRONIX 0xc2
#define SPI_FLASH_CFI_MFR_WINBOND 0xef
-/* SECT flags */
-#define SECT_4K(1 1)
-#define SECT_32K (1 2)
-#define E_FSR (1 3)
-
/* Erase commands */
#define CMD_ERASE_4K 0x20
#define CMD_ERASE_32K 0x52
@@ -60,10 +55,10 @@
#endif
/* Common status */
-#define STATUS_WIP 0x01
+#define STATUS_WIP (1 0)
#define STATUS_QEB_WINSPAN (1 1)
#define STATUS_QEB_MXIC(1 6)
-#define STATUS_PEC 0x80
+#define STATUS_PEC (1 7)
/* Flash timeout values */
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
@@ -105,7 +100,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32
offset, size_t len);
int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
/* Program the status register */
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws);
/* Read the config register */
int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 28527fa..bc4a822 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -39,13 +39,13 @@ int spi_flash_cmd_read_status(struct spi_flash *flash, u8
*rs)
return 0;
}
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
{
u8 cmd;
int ret;
cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, cmd, 1, sr, 1);
+ ret = spi_flash_write_common(flash, cmd, 1, ws, 1);
if (ret 0) {
debug(SF: fail to write status register\n);
return ret;
@@ -279,7 +279,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32
offset,
spi_flash_addr(offset, cmd);
- debug(PP: 0x%p = cmd = { 0x%02x 0x%02x%02x%02x } chunk_len =
%zu\n,
+ debug(SF: 0x%p = cmd = { 0x%02x 0x%02x%02x%02x } chunk_len =
%zu\n,
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 6b59f2a..ac42b60 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -167,7 +167,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
cmd = spi_read_cmds_array[cmd - 1];
flash-read_cmd = cmd;
} else {
- /* Go for for default supported read cmd */
+ /* Go for default supported read cmd */
flash-read_cmd = CMD_READ_ARRAY_FAST;
}
@@ -207,7 +207,7 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
flash-dummy_byte = 1;
}
- /* Poll cmd seclection */
+ /* Poll cmd selection */
flash-poll_cmd = CMD_READ_STATUS;
#ifdef CONFIG_SPI_FLASH_STMICRO
if (params-flags E_FSR)
diff --git a/include/spi_flash.h b/include/spi_flash.h
index 437937c..213d659 100644
--- a/include/spi_flash.h
+++ b/include/spi_flash.h
@@ -19,7 +19,10 @@
#include linux/types.h
#include linux/compiler.h
-/* No enum list for write commands only QPP */
+/* sf param flags */
+#define SECT_4K1 1
+#define SECT_32K 1 2
+#define E_FSR 1 3
#define WR_QPP 1 4
/* Enum list - Full read commands */
--
1.8.3
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[U-Boot] [PATCH v7 13/17] sf: ops: Unify read_ops bank configuration
Unified the bar code from read_ops into a spi_flash_bar()
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_ops.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index bc4a822..7ae9582 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -127,7 +127,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
return ret;
}
- return 0;
+ return bank_sel;
}
#endif
@@ -321,8 +321,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data)
{
- u8 *cmd, cmdsz, bank_sel = 0;
+ u8 *cmd, cmdsz;
u32 remain_len, read_len;
+ int bank_sel = 0;
int ret = -1;
/* Handle memory-mapped SPI */
@@ -346,13 +347,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
cmd[0] = flash-read_cmd;
while (len) {
#ifdef CONFIG_SPI_FLASH_BAR
- bank_sel = offset / SPI_FLASH_16MB_BOUN;
-
- ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
- if (ret) {
- debug(SF: fail to set bank%d\n, bank_sel);
+ bank_sel = spi_flash_bank(flash, offset);
+ if (bank_sel 0)
return ret;
- }
#endif
remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
if (len remain_len)
--
1.8.3
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[U-Boot] [PATCH v7 15/17] sf: Add dual memories support - DUAL_PARALLEL
This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.
For more info - see doc/SPI/README.dual-flash
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
doc/SPI/README.dual-flash | 27 +++
drivers/mtd/spi/sf_ops.c | 8 ++--
drivers/mtd/spi/sf_probe.c | 11 ++-
include/spi.h | 3 ++-
include/spi_flash.h| 5 -
5 files changed, 45 insertions(+), 9 deletions(-)
diff --git a/doc/SPI/README.dual-flash b/doc/SPI/README.dual-flash
index ba0aa26..6c88d65 100644
--- a/doc/SPI/README.dual-flash
+++ b/doc/SPI/README.dual-flash
@@ -54,6 +54,33 @@ SF_DUAL_STACKED_FLASH:
by default, if U_PAGE is unset lower memory should accessible,
once user wants to access upper memory need to set U_PAGE.
+SPI_FLASH_CONN_DUALPARALLEL:
+ - dual spi/qspi flash memories are connected with a single chipselect
+ line and these two memories are operating parallel with separate
buses.
+ - xilinx zynq qspi controller has implemented this feature [1]
+
+ +-+ CS +---+
+ ||--| |
+ ||I0[3:0]| Upper Flash |
+ ||=| memory|
+ || CLK | (SPI/QSPI)|
+ ||--| |
+ | Controller | CS +---+
+ | SPI/QSPI |--| |
+ ||I0[3:0]| Lower Flash |
+ ||=| memory|
+ || CLK | (SPI/QSPI)|
+ ||--| |
+ +-+ +---+
+
+ - two memory flash devices should has same hw part attributes (like
size,
+ vendor..etc)
+ - Configurations:
+ Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG
register.
+ - Operation:
+ Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the
lower memory
+ and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in
the upper memory.
+
Note: Technically there is only one CS line from the controller, but
zynq qspi controller has an internal hw logic to enable additional CS
when controller is configured for dual memories.
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index e877858..843f379 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -119,7 +119,7 @@ static int spi_flash_bank(struct spi_flash *flash, u32
offset)
u8 bank_sel;
int ret;
- bank_sel = offset / SPI_FLASH_16MB_BOUN;
+ bank_sel = offset / (SPI_FLASH_16MB_BOUN flash-shift);
ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
if (ret) {
@@ -142,6 +142,9 @@ static void spi_flash_dual_flash(struct spi_flash *flash,
u32 *addr)
flash-spi-flags = ~SPI_XFER_U_PAGE;
}
break;
+ case SF_DUAL_PARALLEL_FLASH:
+ *addr = flash-shift;
+ break;
default:
debug(SF: Unsupported dual_flash=%d\n, flash-dual_flash);
break;
@@ -388,7 +391,8 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
if (bank_sel 0)
return ret;
#endif
- remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
+ remain_len = ((SPI_FLASH_16MB_BOUN flash-shift) *
+ (bank_sel + 1)) - offset;
if (len remain_len)
read_len = len;
else
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index b9e14c5..48de7c1 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -146,19 +146,20 @@ static struct spi_flash *spi_flash_validate_params(struct
spi_slave *spi,
flash-read = spi_flash_cmd_read_ops;
/* Compute the flash size */
- flash-page_size = (ext_jedec == 0x4d00) ? 512 : 256;
- flash-sector_size = params-sector_size;
- flash-size = flash-sector_size * params-nr_sectors;
+ flash-shift = (flash-dual_flash SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
+ flash-page_size = ((ext_jedec == 0x4d00) ? 512 : 256) flash-shift;
+ flash-sector_size = params-sector_size flash-shift;
+ flash-size = flash-sector_size * params-nr_sectors flash-shift;
if (flash-dual_flash SF_DUAL_STACKED_FLASH)
flash-size = 1;
/* Compute erase sector and command */
if (params-flags SECT_4K) {
flash-erase_cmd = CMD_ERASE_4K;
- flash-erase_size = 4096;
+ flash-erase_size = 4096 flash-shift;
} else if (params-flags
[U-Boot] [PATCH v7 11/17] sf: Divide flash register ops from QEB code
QEB code comprises of couple of flash register read/write operations,
this patch moved flash register operations on to sf_op
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 11 ---
drivers/mtd/spi/sf_ops.c | 75 +++
drivers/mtd/spi/sf_probe.c| 44 +
3 files changed, 77 insertions(+), 53 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index c69b53d..c77961f 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -101,14 +101,17 @@ int spi_flash_cmd_write(struct spi_slave *spi, const u8
*cmd, size_t cmd_len,
/* Flash erase(sectors) operation, support all possible erase commands */
int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len);
+/* Read the status register */
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs);
+
/* Program the status register */
int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr);
-/* Set quad enbale bit for macronix flashes */
-int spi_flash_set_qeb_mxic(struct spi_flash *flash);
+/* Read the config register */
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc);
-/* Set quad enbale bit for winbond and spansion flashes */
-int spi_flash_set_qeb_winspan(struct spi_flash *flash);
+/* Program the config register */
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc);
/* Enable writing on the SPI flash */
static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 05fbcbd..28527fa 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -24,94 +24,71 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
cmd[3] = addr 0;
}
-int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
+int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
{
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_WRITE_STATUS;
- ret = spi_flash_write_common(flash, cmd, 1, sr, 1);
+ cmd = CMD_READ_STATUS;
+ ret = spi_flash_read_common(flash, cmd, 1, rs, 1);
if (ret 0) {
- debug(SF: fail to write status register\n);
+ debug(SF: fail to read status register\n);
return ret;
}
return 0;
}
-#ifdef CONFIG_SPI_FLASH_MACRONIX
-int spi_flash_set_qeb_mxic(struct spi_flash *flash)
+int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr)
{
- u8 qeb_status;
u8 cmd;
int ret;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, cmd, 1, qeb_status, 1);
+ cmd = CMD_WRITE_STATUS;
+ ret = spi_flash_write_common(flash, cmd, 1, sr, 1);
if (ret 0) {
- debug(SF: fail to read status register\n);
+ debug(SF: fail to write status register\n);
return ret;
}
- if (qeb_status STATUS_QEB_MXIC) {
- debug(SF: Quad enable bit is already set\n);
- } else {
- ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
- if (ret 0)
- return ret;
- }
-
- return ret;
+ return 0;
}
-#endif
#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
-static int spi_flash_cmd_write_config(struct spi_flash *flash, u8 cr)
+int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
{
- u8 data[2];
- u8 cmd;
int ret;
+ u8 cmd;
- cmd = CMD_READ_STATUS;
- ret = spi_flash_read_common(flash, cmd, 1, data[0], 1);
+ cmd = CMD_READ_CONFIG;
+ ret = spi_flash_read_common(flash, cmd, 1, rc, 1);
if (ret 0) {
- debug(SF: fail to read status register\n);
- return ret;
- }
-
- cmd = CMD_WRITE_STATUS;
- data[1] = cr;
- ret = spi_flash_write_common(flash, cmd, 1, data, 2);
- if (ret) {
- debug(SF: fail to write config register\n);
+ debug(SF: fail to read config register\n);
return ret;
}
return 0;
}
-int spi_flash_set_qeb_winspan(struct spi_flash *flash)
+int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
{
- u8 qeb_status;
+ u8 data[2];
u8 cmd;
int ret;
- cmd = CMD_READ_CONFIG;
- ret = spi_flash_read_common(flash, cmd, 1, qeb_status, 1);
- if (ret 0) {
- debug(SF: fail to read config register\n);
+ ret = spi_flash_cmd_read_status(flash, data[0]);
+ if (ret 0)
return ret;
- }
- if (qeb_status STATUS_QEB_WINSPAN) {
- debug(SF: Quad enable bit is already set\n);
- } else {
- ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
- if (ret 0)
- return ret
[U-Boot] [PATCH v7 01/17] sf: Add extended read commands support
Current sf uses FAST_READ command, this patch adds support to
use the different/extended read command.
This implementation will determine the fastest command by taking
the supported commands from the flash and the controller, controller
is always been a priority.
Signed-off-by: Jagannadha Sutradharudu Teki jaga...@xilinx.com
---
drivers/mtd/spi/sf_internal.h | 2 +
drivers/mtd/spi/sf_ops.c | 2 +-
drivers/mtd/spi/sf_probe.c| 190 +++---
include/spi.h | 8 ++
include/spi_flash.h | 10 +++
5 files changed, 126 insertions(+), 86 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d291746..938a78e 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -36,6 +36,8 @@
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_ARRAY_FAST0x0b
+#define CMD_READ_DUAL_OUTPUT_FAST 0x3b
+#define CMD_READ_DUAL_IO_FAST 0xbb
#define CMD_READ_ID0x9f
/* Bank addr access commands */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index e316a69..49ceef0 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -285,7 +285,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32
offset,
return 0;
}
- cmd[0] = CMD_READ_ARRAY_FAST;
+ cmd[0] = flash-read_cmd;
cmd[4] = 0x00;
while (len) {
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index b863a98..c0baac6 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -27,6 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
* @ext_jedec: Device ext_jedec ID
* @sector_size: Sector size of this device
* @nr_sectors:No.of sectors on this device
+ * @e_rd_cmd: Enum list for read commands
* @flags: Importent param, for flash specific behaviour
*/
struct spi_flash_params {
@@ -35,110 +36,111 @@ struct spi_flash_params {
u16 ext_jedec;
u32 sector_size;
u32 nr_sectors;
+ u8 e_rd_cmd;
u16 flags;
};
static const struct spi_flash_params spi_flash_params_table[] = {
#ifdef CONFIG_SPI_FLASH_ATMEL /* ATMEL */
- {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4,
SECT_4K},
- {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8,
SECT_4K},
- {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8,
SECT_4K},
- {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16,
SECT_4K},
- {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32,
SECT_4K},
- {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64,
SECT_4K},
- {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128,
SECT_4K},
- {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64,
SECT_4K},
+ {AT45DB011D, 0x1f2200, 0x0, 64 * 1024, 4, 0,
SECT_4K},
+ {AT45DB021D, 0x1f2300, 0x0, 64 * 1024, 8, 0,
SECT_4K},
+ {AT45DB041D, 0x1f2400, 0x0, 64 * 1024, 8, 0,
SECT_4K},
+ {AT45DB081D, 0x1f2500, 0x0, 64 * 1024,16, 0,
SECT_4K},
+ {AT45DB161D, 0x1f2600, 0x0, 64 * 1024,32, 0,
SECT_4K},
+ {AT45DB321D, 0x1f2700, 0x0, 64 * 1024,64, 0,
SECT_4K},
+ {AT45DB641D, 0x1f2800, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {AT25DF321, 0x1f4701, 0x0, 64 * 1024,64, 0,
SECT_4K},
#endif
#ifdef CONFIG_SPI_FLASH_EON/* EON */
- {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64,
0},
- {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128,
SECT_4K},
- {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256,
0},
- {EN25S64,0x1c3817, 0x0, 64 * 1024, 128,
0},
+ {EN25Q32B, 0x1c3016, 0x0, 64 * 1024,64, 0,
0},
+ {EN25Q64,0x1c3017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {EN25Q128B, 0x1c3018, 0x0, 64 * 1024, 256, 0,
0},
+ {EN25S64,0x1c3817, 0x0, 64 * 1024, 128, 0,
0},
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
- {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128,
SECT_4K},
- {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64,
SECT_4K},
+ {GD25Q64B, 0xc84017, 0x0, 64 * 1024, 128, 0,
SECT_4K},
+ {GD25LQ32, 0xc86016, 0x0, 64 * 1024,64, 0,
SECT_4K},
#endif
#ifdef
