, Scott Wood wrote:
On Fri, Sep 21, 2012 at 07:47:46PM +0100, José Miguel Gonçalves wrote:
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
On 21-09-2013 16:56, Marek Vasut wrote:
Hi,
Precisely one year after my patch submission to add support to the
MINI2416 board, seems a good time to ask this question, is there any
good reason for not integrating this patch on the u-boot mainline?
Hi Minkyu,
On 25-09-2013 09:55, Minkyu Kang wrote:
Hello,
On 25/09/13 17:06, José Miguel Gonçalves wrote:
On 21-09-2013 16:56, Marek Vasut wrote:
Hi,
Precisely one year after my patch submission to add support to the
MINI2416 board, seems a good time to ask this question, is there any
good
On 25-09-2013 10:30, Minkyu Kang wrote:
On 25/09/13 18:18, José Miguel Gonçalves wrote:
Hi Minkyu,
On 25-09-2013 09:55, Minkyu Kang wrote:
Hello,
On 25/09/13 17:06, José Miguel Gonçalves wrote:
On 21-09-2013 16:56, Marek Vasut wrote:
Hi,
Precisely one year after my patch submission to add
I've added this support for an S3C2416 based board over 2012.10 u-boot
sources.
Please check this patch at:
http://patchwork.ozlabs.org/patch/185885/
José Gonçalves
___
U-Boot mailing list
U-Boot@lists.denx.de
Hi Zoltan,
Did not try this myself on the MINI2416 board, so I can not give you any
hints on that.
But I'm curious, why do you need u-boot's OHCI support for that board?
Best regards,
José Gonçalves
___
U-Boot mailing list
U-Boot@lists.denx.de
Hi,
Precisely one year after my patch submission to add support to the
MINI2416 board, seems a good time to ask this question, is there any
good reason for not integrating this patch on the u-boot mainline?
http://lists.denx.de/pipermail/u-boot/2012-September/134779.html
Best regards,
José
Hi,
Can you tell me if this patch series is going to be included on next u-boot
release?
Do you need anything from my side in order to push this?
Best regards,
José Gonçalves
On 21-09-2012 19:47, José Miguel Gonçalves wrote:
Support for the MINI2416 board based on a Samsung's S3C2416 SoC
Hi Wolfgang,
On 09/21/2012 06:43 AM, Wolfgang Denk wrote:
Dear Tom,
In message 5fbf8e85ca34454794f0f7ecba79798f379f6fd...@hqmail04.nvidia.com you
wrote:
If you flash u-boot-dtb-tegra.bin, you'll get a fully functioning
U-Boot. There's an intermediate file (u-boot-dtb.bin) that I assume
is
On 21-09-2012 17:13, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/21/12 08:52, Wolfgang Denk wrote:
Dear José Miguel Gonçalves,
In message 505c21bb.7000...@inov.pt you wrote:
It is very important to me that we do NOT include any
architectures, SoCs, or board specifc
The values stored in the baud rate divisor register (UBRDIVn) and dividing
slot register (UDIVSLOTn), are used to determine the serial baudrate.
Previously only UBRDIVn was set. This patch initializes also UDIVSLOTn
which allows to obtain a more precise baudrate.
Signed-off-by: José Miguel
rtc_reset() must set the RTC date to the UNIX Epoch.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
Changes for v4:
- None
Changes for v5:
- None
---
drivers/rtc/s3c24x0_rtc.c | 15 +++
1 file
The printf() implementation needs 4~5KB of storage space which may not be
available when building an SPL for SoCs with scarce internal RAM
(8KB or less). This patch adds a new option, CONFIG_SPL_PRINTF_SUPPORT,
to deal with this.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
The loop used to make a delay after baudrate setting is not necessary.
Moreover it is removed by the GCC optimizer (at least with GCC 4.6).
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
Changes for v4:
- None
Changes
This RTC only supports a 100 years range so rtc_set() should not allow setting
years bellow 1970 or above 2069.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
Changes for v4:
- None
Changes for v5:
- None
providers
that can supply it with a selectable NAND chip from 128MB to 1GB.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of Use of clrbits_le32(), setbits_le32() and clrsetbits_le32()
- Use of register bit macros instead of magic
S3C2416 and S3C2450 have 4 UARTs insted of 3 found on older chips.
This patch adds support to the additional UART port and changes the
mapping between CONFIG_SERIAL? and S3C24X0_UART? in order they have
a direct correspondence.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
style cleanup
- Removal of #define CONFIG_SYS_BAUDRATE_TABLE as this in the defaults now
- Checkpatch clean with the exceptions indicated in the v3 changes
José Miguel Gonçalves (11):
Add configuration option to select printf() inclusion on SPL
S3C24XX: Add core support for Samsung's
Samsung's S3C24XX SoCs need this in order to generate a binary image
with a padded SPL concatenated with U-Boot.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- None
Changes for v3:
- Changed new binary target name from u-boot-ubl.bin to u-boot-pad.bin
A better approach to avoid reading the RTC during updates, as sugested in
the S3C2416 User's Manual.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- Removed unneeded parenthesis
Changes for v4:
- None
Changes for v5
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of clrsetbits_le32()
- Use of register bit macros instead of magic numbers
Changes
On 20-09-2012 19:09, Scott Wood wrote:
On 09/20/2012 11:01:42 AM, Tom Warren wrote:
-Original Message-
From: Tom Rini [mailto:tr...@ti.com]
Sent: Wednesday, September 19, 2012 6:29 PM
To: José Miguel Gonçalves
Cc: Scott Wood; u-boot@lists.denx.de; ma...@denx.de; mk7.k
The loop used to make a delay after baudrate setting is not necessary.
Moreover it is removed by the GCC optimizer (at least with GCC 4.6).
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
Changes for v4:
- None
providers
that can supply it with a selectable NAND chip from 128MB to 1GB.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of Use of clrbits_le32(), setbits_le32() and clrsetbits_le32()
- Use of register bit macros instead of magic
rtc_reset() must set the RTC date to the UNIX Epoch.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
Changes for v4:
- None
---
drivers/rtc/s3c24x0_rtc.c | 15 +++
1 file changed, 11 insertions(+), 4
A better approach to avoid reading the RTC during updates, as sugested in
the S3C2416 User's Manual.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- Removed unneeded parenthesis
Changes for v4:
- None
---
drivers/rtc
The printf() implementation needs 4~5KB of storage space which may not be
available when building an SPL for SoCs with scarce internal RAM
(8KB or less). This patch adds a new option, CONFIG_SPL_PRINTF_SUPPORT,
to deal with this.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
The values stored in the baud rate divisor register (UBRDIVn) and dividing
slot register (UDIVSLOTn), are used to determine the serial baudrate.
Previously only UBRDIVn was set. This patch initializes also UDIVSLOTn
which allows to obtain a more precise baudrate.
Signed-off-by: José Miguel
This RTC only supports a 100 years range so rtc_set() should not allow setting
years bellow 1970 or above 2069.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
Changes for v4:
- None
---
drivers/rtc/s3c24x0_rtc.c
Samsung's S3C24XX SoCs need this in order to generate a binary image
with a padded SPL concatenated with U-Boot.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- None
Changes for v3:
- Changed new binary target name from u-boot-ubl.bin to u-boot-pad.bin
S3C2416 and S3C2450 have 4 UARTs insted of 3 found on older chips.
This patch adds support to the additional UART port and changes the
mapping between CONFIG_SERIAL? and S3C24X0_UART? in order they have
a direct correspondence.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of clrsetbits_le32()
- Use of register bit macros instead of magic numbers
Changes
, no spaces at the start of a line
#1716: FILE: include/common.h:631:
+defined(CONFIG_S3C24XX) || \$
Changes for v4:
- NAND Flash driver cleanup and optimization
José Miguel Gonçalves (11):
Add configuration option to select printf() inclusion on SPL
S3C24XX: Add core
On 19-09-2012 17:19, Scott Wood wrote:
On 09/19/2012 06:25:25 AM, José Miguel Gonçalves wrote:
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style
On 19-09-2012 17:10, Scott Wood wrote:
On 09/19/2012 06:25:26 AM, José Miguel Gonçalves wrote:
Samsung's S3C24XX SoCs need this in order to generate a binary image
with a padded SPL concatenated with U-Boot.
I still think pad is a lousy name for this. It refers to a minor
implementation
On 19-09-2012 18:08, Scott Wood wrote:
On 09/19/2012 11:58:06 AM, José Miguel Gonçalves wrote:
On 19-09-2012 17:10, Scott Wood wrote:
On 09/19/2012 06:25:26 AM, José Miguel Gonçalves wrote:
Samsung's S3C24XX SoCs need this in order to generate a binary image
with a padded SPL concatenated
On 19-09-2012 19:19, Tom Rini wrote:
On Wed, Sep 19, 2012 at 11:11:08AM -0600, Stephen Warren wrote:
On 09/19/2012 10:58 AM, Jos? Miguel Gon?alves wrote:
On 19-09-2012 17:10, Scott Wood wrote:
On 09/19/2012 06:25:26 AM, Jos? Miguel Gon?alves wrote:
Samsung's S3C24XX SoCs need this in order
On 09/19/2012 08:18 PM, Tom Rini wrote:
On Wed, Sep 19, 2012 at 12:25:27PM +0100, Jos?? Miguel Gon??alves wrote:
The MINI2416 board is based on a Samsung's S3C2416 SoC and has 64MB DDR2 SDRAM,
256MB NAND Flash, a LAN9220 Ethernet Controller and a WM8731 Audio CODEC.
This U-Boot port was
, José Miguel Gonçalves wrote:
Samsung's S3C24XX SoCs need this in order to generate a
binary image with a padded SPL concatenated with U-Boot.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
--- Changes for v2: - None
Changes for v3: - Changed new binary target name from
u-boot-ubl.bin
Hi Tom,
On 17-09-2012 16:11, Tom Rini wrote:
On Mon, Sep 17, 2012 at 03:47:46PM +0100, Jos? Miguel Gon?alves wrote:
On 17-09-2012 15:39, Tom Rini wrote:
On Sun, Sep 16, 2012 at 10:11:07AM +0100, Jos? Miguel Gon?alves wrote:
On 09/14/2012 07:58 PM, Tom Rini wrote:
On Fri, Sep 14, 2012 at
The printf() implementation needs 4~5KB of storage space which may not be
available when building an SPL for SoCs with scarce internal RAM
(8KB or less). This patch adds a new option, CONFIG_SPL_PRINTF_SUPPORT,
to deal with this.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
The loop used to make a delay after baudrate setting is not necessary.
Moreover it is removed by the GCC optimizer (at least with GCC 4.6).
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
---
drivers/serial/serial_s3c24x0
rtc_reset() must set the RTC date to the UNIX Epoch.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
---
drivers/rtc/s3c24x0_rtc.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git
The values stored in the baud rate divisor register (UBRDIVn) and dividing
slot register (UDIVSLOTn), are used to determine the serial baudrate.
Previously only UBRDIVn was set. This patch initializes also UDIVSLOTn
which allows to obtain a more precise baudrate.
Signed-off-by: José Miguel
, no spaces at the start of a line
#1716: FILE: include/common.h:631:
+defined(CONFIG_S3C24XX) || \$
José Miguel Gonçalves (11):
Add configuration option to select printf() inclusion on SPL
S3C24XX: Add core support for Samsung's S3C24XX SoCs
serial: Add support to 4 ports
This RTC only supports a 100 years range so rtc_set() should not allow setting
years bellow 1970 or above 2069.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- None
---
drivers/rtc/s3c24x0_rtc.c |5 +
1 file changed, 5
A better approach to avoid reading the RTC during updates, as sugested in
the S3C2416 User's Manual.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
Changes for v3:
- Removed unneeded parenthesis
---
drivers/rtc/s3c24x0_rtc.c | 10
S3C2416 and S3C2450 have 4 UARTs insted of 3 found on older chips.
This patch adds support to the additional UART port and changes the
mapping between CONFIG_SERIAL? and S3C24X0_UART? in order they have
a direct correspondence.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
Samsung's S3C24XX SoCs need this in order to generate a binary image
with a padded SPL concatenated with U-Boot.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- None
Changes for v3:
- Changed new binary target name from u-boot-ubl.bin to u-boot-pad.bin
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of clrsetbits_le32()
- Use of register bit macros instead of magic numbers
Changes
providers
that can supply it with a selectable NAND chip from 128MB to 1GB.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of Use of clrbits_le32(), setbits_le32() and clrsetbits_le32()
- Use of register bit macros instead of magic
On 18-09-2012 19:02, Scott Wood wrote:
On 09/18/2012 12:40:36 PM, José Miguel Gonçalves wrote:
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style
On 18-09-2012 19:30, Scott Wood wrote:
On 09/18/2012 01:22:58 PM, José Miguel Gonçalves wrote:
On 18-09-2012 19:02, Scott Wood wrote:
On 09/18/2012 12:40:36 PM, José Miguel Gonçalves wrote:
+#define TACLS_VAL7/* CLE ALE duration setting (0~7) */
+#defineTWRPH0_VAL7
On 09/17/2012 07:47 AM, Christian Riesch wrote:
Hi,
On Sun, Sep 16, 2012 at 11:27 AM, José Miguel Gonçalves
jose.goncal...@inov.pt wrote:
On 09/14/2012 08:08 PM, Tom Rini wrote:
On Fri, Sep 14, 2012 at 06:29:01PM +0100, Jos?? Miguel Gon??alves wrote:
Samsung's S3C24XX SoCs need
On 09/17/2012 07:28 AM, Christian Riesch wrote:
Hi,
On Sun, Sep 16, 2012 at 5:36 PM, Marek Vasut ma...@denx.de wrote:
Dear José Miguel Gonçalves,
On 09/16/2012 11:06 AM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
On 09/15/2012 07:03 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves
Hi Christian,
On 09/17/2012 10:03 AM, Christian Riesch wrote:
Hi,
On Mon, Sep 17, 2012 at 10:34 AM, José Miguel Gonçalves
jose.goncal...@inov.pt wrote:
On 09/17/2012 07:28 AM, Christian Riesch wrote:
Hi,
On Sun, Sep 16, 2012 at 5:36 PM, Marek Vasut ma...@denx.de wrote:
Dear José Miguel
On 09/17/2012 10:10 AM, Christian Riesch wrote:
On Mon, Sep 17, 2012 at 10:30 AM, José Miguel Gonçalves
jose.goncal...@inov.pt wrote:
On 09/17/2012 07:47 AM, Christian Riesch wrote:
Hi,
On Sun, Sep 16, 2012 at 11:27 AM, José Miguel Gonçalves
jose.goncal...@inov.pt wrote:
On 09/14/2012 08:08
Hi Marek,
On 14-09-2012 19:21, Marek Vasut wrote:
Dear José Miguel Gonçalves,
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
[...]
+#include common.h
+#include nand.h
+#include asm
On 17-09-2012 15:39, Tom Rini wrote:
On Sun, Sep 16, 2012 at 10:11:07AM +0100, Jos? Miguel Gon?alves wrote:
On 09/14/2012 07:58 PM, Tom Rini wrote:
On Fri, Sep 14, 2012 at 06:29:02PM +0100, Jos?? Miguel Gon??alves wrote:
The MINI2416 board is based on a Samsung's S3C2416 SoC and has 64MB
On 17-09-2012 17:57, Tom Rini wrote:
On Sun, Sep 16, 2012 at 10:16:47AM +0100, Jos? Miguel Gon?alves wrote:
On 09/14/2012 08:01 PM, Tom Rini wrote:
On Fri, Sep 14, 2012 at 07:45:40PM +0100, Jos? Miguel Gon?alves wrote:
On 14-09-2012 19:21, Marek Vasut wrote:
Dear Jos? Miguel Gon?alves,
On 17-09-2012 18:18, Tom Rini wrote:
On Sun, Sep 16, 2012 at 05:36:47PM +0200, Marek Vasut wrote:
Dear Jos? Miguel Gon?alves,
On 09/16/2012 11:06 AM, Marek Vasut wrote:
Dear Jos? Miguel Gon?alves,
On 09/15/2012 07:03 PM, Marek Vasut wrote:
Dear Jos? Miguel Gon?alves,
Jumping to
On 17-09-2012 18:56, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/17/12 10:08, José Miguel Gonçalves wrote:
On 17-09-2012 17:57, Tom Rini wrote:
On Sun, Sep 16, 2012 at 10:16:47AM +0100, Jos? Miguel Gon?alves
wrote:
On 09/14/2012 08:01 PM, Tom Rini wrote:
On Fri, Sep
On 17-09-2012 19:27, Tom Rini wrote:
On Mon, Sep 17, 2012 at 07:05:48PM +0100, Jos? Miguel Gon?alves wrote:
On 17-09-2012 18:56, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 09/17/12 10:08, Jos? Miguel Gon?alves wrote:
On 17-09-2012 17:57, Tom Rini wrote:
On Sun, Sep 16,
On 09/14/2012 07:58 PM, Tom Rini wrote:
On Fri, Sep 14, 2012 at 06:29:02PM +0100, Jos?? Miguel Gon??alves wrote:
The MINI2416 board is based on a Samsung's S3C2416 SoC and has 64MB DDR2 SDRAM,
256MB NAND Flash, a LAN9220 Ethernet Controller and a WM8731 Audio CODEC.
This U-Boot port was
On 09/14/2012 08:01 PM, Tom Rini wrote:
On Fri, Sep 14, 2012 at 07:45:40PM +0100, Jos? Miguel Gon?alves wrote:
On 14-09-2012 19:21, Marek Vasut wrote:
Dear Jos? Miguel Gon?alves,
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by:
On 09/14/2012 08:08 PM, Tom Rini wrote:
On Fri, Sep 14, 2012 at 06:29:01PM +0100, Jos?? Miguel Gon??alves wrote:
Samsung's S3C24XX SoCs need this in order to generate a binary image
with the SPL and U-Boot concatenated.
Signed-off-by: Jos?? Miguel Gon??alves jose.goncal...@inov.pt
---
Changes
On 09/15/2012 07:03 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Jumping to board_init_r is not performed due to a bug on address
computation.
Is your CONFIG_SYS_TEXT_BASE configured correctly? I don't detect any
misbehavior on my arm926 boards.
Maybe because you are not using
On 09/16/2012 11:06 AM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
On 09/15/2012 07:03 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Jumping to board_init_r is not performed due to a bug on address
computation.
Is your CONFIG_SYS_TEXT_BASE configured correctly? I don't detect any
On 09/16/2012 04:36 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
On 09/16/2012 11:06 AM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
On 09/15/2012 07:03 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Jumping to board_init_r is not performed due to a bug on address
Jumping to board_init_r is not performed due to a bug on address computation.
Relocation offsets are not needed when building SPL.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- None
---
arch/arm/cpu/arm926ejs/start.S |4 +++-
1 file changed, 3
A better approach to avoid reading the RTC during updates, as sugested in
the S3C2416 User's Manual.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
---
drivers/rtc/s3c24x0_rtc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions
The loop used to make a delay after baudrate setting is not necessary.
Moreover it is removed by the GCC optimizer (at least with GCC 4.6).
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
---
drivers/serial/serial_s3c24x0.c |3 ---
1 file
rtc_reset() must set the RTC date to the UNIX Epoch.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
---
drivers/rtc/s3c24x0_rtc.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/rtc/s3c24x0_rtc.c b
Support for the MINI2416 board based on a Samsung's S3C2416 SoC with
64MB DDR2 SDRAM, 256MB NAND Flash, a LAN9220 Ethernet Controller and a
WM8731 Audio CODEC.
Changes for v2:
- Coding style cleanup
- Removed new serial and rtc drivers
- Use of in-tree serial and rtc drivers
José Miguel
Program udivslot register in order to obtain a more precise baudrate.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
---
drivers/serial/serial_s3c24x0.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git
This RTC only supports a 100 years range so rtc_set() should not allow setting
years bellow 1970 or above 2069.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- New patch
---
drivers/rtc/s3c24x0_rtc.c |5 +
1 file changed, 5 insertions(+)
diff --git
S3C2416 and S3C2450 have 4 UARTs insted of 3 found on older chips.
This patch adds support to the additional UART port and changes the
mapping between CONFIG_SERIAL? and S3C24X0_UART? in order they have
a direct correspondence.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
Samsung's S3C24XX SoCs need this in order to generate a binary image
with the SPL and U-Boot concatenated.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- None
---
Makefile |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Makefile
This patch adds the support for Samsung's S3C24XX SoCs that have an ARM926EJS
core.
Currently it supports S3C2412, S3C2413, S3C2416 and S3C2450.
Tested on an S3C2416 platform.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Added register bit macros to avoid
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of clrsetbits_le32()
- Use of register bit macros instead of magic numbers
providers
that can supply it with a selectable NAND chip from 128MB to 1GB.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Changes for v2:
- Coding style cleanup
- Use of Use of clrbits_le32(), setbits_le32() and clrsetbits_le32()
- Use of register bit macros instead of magic
On 14-09-2012 19:21, Marek Vasut wrote:
Dear José Miguel Gonçalves,
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
[...]
+#include common.h
+#include nand.h
+#include asm/io.h
Hi Marek,
On 09/13/2012 10:17 AM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Hi Marek,
On 09/12/2012 10:01 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Serial driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/serial
RTC driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/rtc/Makefile |1 +
drivers/rtc/s3c24xx_rtc.c | 166 +
2 files changed, 167 insertions(+)
create mode 100644 drivers/rtc/s3c24xx_rtc.c
Samsung's S3C24XX SoCs need this in order to generate a binary image with the
SPL and U-Boot concatenated.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
Makefile |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index 058fb53
Jumping to board_init_r is not performed due to a bug on address computation.
Relocation offsets are not needed when building SPL.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
arch/arm/cpu/arm926ejs/start.S |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
Serial driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/serial/Makefile |1 +
drivers/serial/s3c24xx_serial.c | 146 +++
2 files changed, 147 insertions(+)
create mode 100644 drivers/serial
NAND Flash driver with HW ECC for the S3C24XX SoCs.
Currently it only supports SLC NAND chips.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/s3c24xx_nand.c | 269 +++
2 files changed
providers
that can supply it with a selectable NAND chip from 128MB to 1GB.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
MAINTAINERS|4 +
board/boardcon/mini2416/Makefile | 47 +++
board/boardcon/mini2416/config.mk |4 +
board
Support for the MINI2416 board based on a Samsung's S3C2416 SoC with
64MB DDR2 SDRAM, 256MB NAND Flash, a LAN9220 Ethernet Controller and a
WM8731 Audio CODEC.
José Miguel Gonçalves (7):
ARM: fix relocation on ARM926EJS
S3C24XX: Add core support for Samsung's S3C24XX SoCs
S3C24XX: Add
This patch adds the support for Samsung's S3C24XX SoCs that have an ARM926EJS
core.
Currently it supports S3C2412, S3C2413, S3C2416 and S3C2450.
Tested on an S3C2416 platform.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
arch/arm/cpu/arm926ejs/s3c24xx/Makefile | 52
Hi Marek,
On 09/12/2012 10:11 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
+
+/*
+ * Hardware specific access to control-lines function
+ */
+static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int
ctrl) +{
+ s3c24xx_nand *const nand = s3c24xx_get_base_nand
Hi Marek,
On 09/12/2012 10:03 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
+static inline void rtc_access_disable(void)
+{
+ s3c24xx_rtc *const rtc = s3c24xx_get_base_rtc();
+ uchar rtccon;
+
+ rtccon = readb(rtc-rtccon);
+ rtccon = ~0x01;
Magic numbers, fix
On 09/13/2012 12:45 AM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Hi Marek,
On 09/12/2012 10:11 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
+
+/*
+ * Hardware specific access to control-lines function
+ */
+static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned
Hi Scott,
On 09/13/2012 12:20 AM, Scott Wood wrote:
On 09/12/2012 06:16 PM, José Miguel Gonçalves wrote:
Hi Marek,
On 09/12/2012 10:11 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
+
+/*
+ * Hardware specific access to control-lines function
+ */
+static void s3c_nand_hwcontrol(struct
On 09/13/2012 01:24 AM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Hi Scott,
On 09/13/2012 12:20 AM, Scott Wood wrote:
On 09/12/2012 06:16 PM, José Miguel Gonçalves wrote:
Hi Marek,
On 09/12/2012 10:11 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
+
+/*
+ * Hardware specific
Hi Marek,
On 09/12/2012 10:01 PM, Marek Vasut wrote:
Dear José Miguel Gonçalves,
Serial driver for the S3C24XX SoCs.
Signed-off-by: José Miguel Gonçalves jose.goncal...@inov.pt
---
drivers/serial/Makefile |1 +
drivers/serial/s3c24xx_serial.c | 146
Hi,
The end address for memtest set with CONFIG_SYS_MEMTEST_END is supposed to be
included or not in the test?
Checking on the source code I see that the quick implementation does not include
it, but the more extensive implementation enabled with CONFIG_SYS_ALT_MEMTEST does
include the end
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