[PATCH] drivers: mmc: check the return value of mmc_send_if_cond() call
Return value from mmc_send_if_cond() isn't checked if it is a error state
and the result immediately is overwritten with the sd_send_op_cond() call.
Add check for -EOPNOTSUPP to fail early, and trigger a retry for any other
error code.
Fixes: afd5932b2c27 ("Revert "mmc: retry the cmd8 to meet 74 clocks requirement
in the spec")
Signed-off-by: Matt Ranostay
---
drivers/mmc/mmc.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 0b7c0be8cbc..e26a457a74c 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -2862,6 +2862,13 @@ retry:
/* Test for SD version 2 */
err = mmc_send_if_cond(mmc);
+ if (err == -EOPNOTSUPP)
+ return err;
+
+ if (err) {
+ mmc_power_cycle(mmc);
+ goto retry;
+ }
/* Now try to get the SD card's operating condition */
err = sd_send_op_cond(mmc, uhs_en);
--
2.38.GIT
[PATCH] phy: ti: j721e-wiz: add j784s4-wiz-10g module support
Add support for j784s4-wiz-10g device which has two core reference
clocks (e.g core_ref_clk, core_ref1_clk) which requires an additional
mux selection option.
Signed-off-by: Matt Ranostay
---
drivers/phy/ti/phy-j721e-wiz.c | 75 --
1 file changed, 72 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index fb6b6cf3fff..6646b15d410 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -69,14 +69,20 @@ static const struct reg_field por_en =
REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
static const struct reg_field pll1_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 29, 29);
+static const struct reg_field pll1_refclk_mux_sel_2 =
+ REG_FIELD(WIZ_SERDES_RST, 22, 23);
static const struct reg_field pll0_refclk_mux_sel =
REG_FIELD(WIZ_SERDES_RST, 28, 28);
+static const struct reg_field pll0_refclk_mux_sel_2 =
+ REG_FIELD(WIZ_SERDES_RST, 28, 29);
static const struct reg_field refclk_dig_sel_16g =
REG_FIELD(WIZ_SERDES_RST, 24, 25);
static const struct reg_field refclk_dig_sel_10g =
REG_FIELD(WIZ_SERDES_RST, 24, 24);
static const struct reg_field pma_cmn_refclk_int_mode =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
+static const struct reg_field pma_cmn_refclk1_int_mode =
+ REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
static const struct reg_field pma_cmn_refclk_mode =
REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
static const struct reg_field pma_cmn_refclk_dig_div =
@@ -204,6 +210,27 @@ static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
},
};
+static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK
},
+ .table = { 2, 3, 0 },
+ .node_name = "pll0-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK
},
+ .table = { 2, 3, 0 },
+ .node_name = "pll1-refclk",
+ },
+ {
+ .num_parents = 3,
+ .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK
},
+ .table = { 2, 3, 0 },
+ .node_name = "refclk-dig",
+ },
+};
+
static struct wiz_clk_div_sel clk_div_sel[] = {
{
.div_sel = CMN_REFCLK,
@@ -219,6 +246,7 @@ enum wiz_type {
J721E_WIZ_16G,
J721E_WIZ_10G,
AM64_WIZ_10G,
+ J784S4_WIZ_10G,
};
struct wiz_data {
@@ -227,6 +255,7 @@ struct wiz_data {
const struct reg_field *pll1_refclk_mux_sel;
const struct reg_field *refclk_dig_sel;
const struct reg_field *pma_cmn_refclk1_dig_div;
+ const struct reg_field *pma_cmn_refclk1_int_mode;
const struct wiz_clk_mux_sel *clk_mux_sel;
unsigned int clk_div_sel_num;
};
@@ -259,6 +288,16 @@ static struct wiz_data am64_10g_data = {
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
+static struct wiz_data j784s4_wiz_10g = {
+ .type = J784S4_WIZ_10G,
+ .pll0_refclk_mux_sel = _refclk_mux_sel_2,
+ .pll1_refclk_mux_sel = _refclk_mux_sel_2,
+ .refclk_dig_sel = _dig_sel_16g,
+ .pma_cmn_refclk1_int_mode = _cmn_refclk1_int_mode,
+ .clk_mux_sel = clk_mux_sel_10g_2_refclk,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
@@ -279,6 +318,7 @@ struct wiz {
struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
struct regmap_field *pma_cmn_refclk_int_mode;
+ struct regmap_field *pma_cmn_refclk1_int_mode;
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
struct regmap_field *pma_cmn_refclk1_dig_div;
@@ -729,6 +769,15 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
}
+ if (data->pma_cmn_refclk1_int_mode) {
+ wiz->pma_cmn_refclk1_int_mode =
+ devm_regmap_field_alloc(dev, regmap,
*data->pma_cmn_refclk1_int_mode);
+ if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
+ dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init
failed\n");
+ return PTR_ERR(wiz->pma_cmn_re
[PATCH] regmap: add WARN_ONCE when invalid mask is provided to regmap_field_init()
In regmap_field_init() when a invalid mask is provided it still initializes without any warnings of it being incorrect. An example of this is when the LSB is greater than MSB a mask of zero is produced. WARN_ONCE() is not ideal for this but requires less changes to core regmap code. Based on: https://lore.kernel.org/all/20220708013125.313892-1-mranos...@ti.com/ Signed-off-by: Matt Ranostay --- drivers/core/regmap.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 5f98f85cfce..3100a58af2c 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -20,6 +20,7 @@ #include #include #include +#include /* * Internal representation of a regmap field. Instead of storing the MSB and @@ -649,6 +650,8 @@ static void regmap_field_init(struct regmap_field *rm_field, rm_field->reg = reg_field.reg; rm_field->shift = reg_field.lsb; rm_field->mask = GENMASK(reg_field.msb, reg_field.lsb); + + WARN_ONCE(rm_field->mask == 0, "invalid empty mask defined\n"); } struct regmap_field *devm_regmap_field_alloc(struct udevice *dev, -- 2.37.2
[PATCH] armv8: mach-k3: correct define checking for AM625/AM642 memory maps
Using CONFIG_IS_ENABLED breaks accessing memory map structure when doing a A53 SPL build for AM625 and AM642 platforms. This is due to 'abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y'' in which there is no CONFIG_SPL_SOC_K3_AM625/CONFIG_SPL_SOC_K3_AM642 defined in the configuration. For the A53 SPL builds on these platform to access the memory mapping which it will need for enabling the mmu/cache it must use #if defined(X) checks and not CONFIG_IS_ENABLED. Cc: Suman Anna Cc: Neha Francis Signed-off-by: Matt Ranostay --- arch/arm/mach-k3/arm64-mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 12cb89335ad..c43c07ce7fa 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -222,7 +222,7 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ -#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625)) +#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ #define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) -- 2.36.1
[PATCH] phy: ti: j721e-wiz: use OF data for device specific data
Move device specific data into OF data structure so it
is easier to maintain and we can get rid of if statements.
Based on:
https://lore.kernel.org/linux-phy/20220526064121.27625-1-rog...@kernel.org/T/#u
Cc: Roger Quadros
Signed-off-by: Matt Ranostay
---
drivers/phy/ti/phy-j721e-wiz.c | 88 +++---
1 file changed, 60 insertions(+), 28 deletions(-)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 686cdc6f7c..fb6b6cf3ff 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -221,6 +221,44 @@ enum wiz_type {
AM64_WIZ_10G,
};
+struct wiz_data {
+ enum wiz_type type;
+ const struct reg_field *pll0_refclk_mux_sel;
+ const struct reg_field *pll1_refclk_mux_sel;
+ const struct reg_field *refclk_dig_sel;
+ const struct reg_field *pma_cmn_refclk1_dig_div;
+ const struct wiz_clk_mux_sel *clk_mux_sel;
+ unsigned int clk_div_sel_num;
+};
+
+static const struct wiz_data j721e_16g_data = {
+ .type = J721E_WIZ_16G,
+ .pll0_refclk_mux_sel = _refclk_mux_sel,
+ .pll1_refclk_mux_sel = _refclk_mux_sel,
+ .refclk_dig_sel = _dig_sel_16g,
+ .pma_cmn_refclk1_dig_div = _cmn_refclk1_dig_div,
+ .clk_mux_sel = clk_mux_sel_16g,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
+};
+
+static const struct wiz_data j721e_10g_data = {
+ .type = J721E_WIZ_10G,
+ .pll0_refclk_mux_sel = _refclk_mux_sel,
+ .pll1_refclk_mux_sel = _refclk_mux_sel,
+ .refclk_dig_sel = _dig_sel_10g,
+ .clk_mux_sel = clk_mux_sel_10g,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
+static struct wiz_data am64_10g_data = {
+ .type = AM64_WIZ_10G,
+ .pll0_refclk_mux_sel = _refclk_mux_sel,
+ .pll1_refclk_mux_sel = _refclk_mux_sel,
+ .refclk_dig_sel = _dig_sel_10g,
+ .clk_mux_sel = clk_mux_sel_10g,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
@@ -253,6 +291,7 @@ struct wiz {
u32 lane_phy_type[WIZ_MAX_LANES];
struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
unsigned intid;
+ const struct wiz_data *data;
};
struct wiz_div_clk {
@@ -667,7 +706,7 @@ static int wiz_regfield_init(struct wiz *wiz)
struct regmap *regmap = wiz->regmap;
int num_lanes = wiz->num_lanes;
struct udevice *dev = wiz->dev;
- enum wiz_type type;
+ const struct wiz_data *data = wiz->data;
int i;
wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
@@ -704,36 +743,31 @@ static int wiz_regfield_init(struct wiz *wiz)
return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]);
}
- wiz->div_sel_field[CMN_REFCLK1] =
- devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk1_dig_div);
- if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
- dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
- return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
+ if (data->pma_cmn_refclk1_dig_div) {
+ wiz->div_sel_field[CMN_REFCLK1] =
+ devm_regmap_field_alloc(dev, regmap,
*data->pma_cmn_refclk1_dig_div);
+ if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
+ dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init
failed\n");
+ return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
+ }
}
wiz->mux_sel_field[PLL0_REFCLK] =
- devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
+ devm_regmap_field_alloc(dev, regmap,
*data->pll0_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
}
wiz->mux_sel_field[PLL1_REFCLK] =
- devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
+ devm_regmap_field_alloc(dev, regmap,
*data->pll1_refclk_mux_sel);
if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
}
- type = dev_get_driver_data(dev);
- if (type == J721E_WIZ_10G || type == AM64_WIZ_10G)
- wiz->mux_sel_field[REFCLK_DIG] =
- devm_regmap_field_alloc(dev, regmap,
- refclk_dig_sel_10g);
- else
- wiz->mux_sel_field[REFCLK_DIG] =
- devm_regmap_field_alloc(dev, regmap,
- refclk_d
