Re: [PATCH 1/5] mtd/spinand: rework detect procedure for different READ_ID operation
I can try to resend patches (flash drivers synced with linux-6.1). Unfortunately I am not sure I will be able to do it after changes in our mail system. Mikhail Kshevetskiy On 18.04.2023 16:48, Michael Nazzareno Trimarchi wrote: > [External email] > > > > > > Hi Frieder > > On Tue, Apr 18, 2023 at 3:46 PM Frieder Schrempf > wrote: >> Hi Michael, Dario, >> >> On 28.03.23 09:57, Frieder Schrempf wrote: >>> Hi Michael, >>> >>> On 10.02.23 12:57, Michael Nazzareno Trimarchi wrote: >>>> Hi >>>> >>>> I will review >>>> >>>> On Thu, Feb 9, 2023 at 5:52 PM Tom Rini wrote: >>>>> On Thu, Feb 09, 2023 at 10:24:47AM +0100, Frieder Schrempf wrote: >>>>>> Hi, >>>>>> >>>>>> On 10.01.23 12:58, Frieder Schrempf wrote: >>>>>>> From: Mikhail Kshevetskiy >>>>>>> >>>>>>> Currently there are 3 different variants of read_id implementation: >>>>>>> 1. opcode only. Found in GD5FxGQ4xF. >>>>>>> 2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E >>>>>>> 3. opcode + 1 dummy byte. Found in other currently supported chips. >>>>>>> >>>>>>> Original implementation was for variant 1 and let detect function >>>>>>> of chips with variant 2 and 3 to ignore the first byte. This isn't >>>>>>> robust: >>>>>>> >>>>>>> 1. For chips of variant 2, if SPI master doesn't keep MOSI low >>>>>>> during read, chip will get a random id offset, and the entire id >>>>>>> buffer will shift by that offset, causing detect failure. >>>>>>> >>>>>>> 2. For chips of variant 1, if it happens to get a devid that equals >>>>>>> to manufacture id of variant 2 or 3 chips, it'll get incorrectly >>>>>>> detected. >>>>>>> >>>>>>> This patch reworks detect procedure to address problems above. New >>>>>>> logic do detection for all variants separatedly, in 1-2-3 order. >>>>>>> Since all current detect methods do exactly the same id matching >>>>>>> procedure, unify them into core.c and remove detect method from >>>>>>> manufacture_ops. >>>>>>> >>>>>>> This is a rework of Chuanhong Guo patch >>>>>>> submitted to linux kernel >>>>>>> >>>>>>> Signed-off-by: Mikhail Kshevetskiy >>>>>>> Signed-off-by: Frieder Schrempf >>>>>> +Cc: Jagan, Tom >>>>>> >>>>>> Who is supposed to pick up these patches? Some of them have been around >>>>>> for some months (before I resent them). >>>>>> >>>>>> There is no maintainer for drivers/mtd/spinand/ and no maintainer for >>>>>> drivers/mtd/ in general. >>>>>> >>>>>> In Patchwork Jagan got assigned, but the get_maintainer.pl script didn't >>>>>> even add him to Cc, of course. >>>>>> >>>>>> Any ideas how to proceed? >>>>> We don't have anyone dedicated to that area, yes, sadly. I've added >>>>> Michael and Dario as they've also been doing mtd-but-not-spi work of >>>>> late to see if they're interested. Or since you've long been working >>>>> here, would you like to more formally maintain the area? Thanks! >>>> They can come from our tree. I will try to sort out all my duties weeked >>> Any news regarding reviewing/picking these patches? >> Ping! >> >> Can you please apply these patches, that have been waiting for so long? >> >> Thanks >> Frieder > Yes, waiting for Jagan, please way 1 day more > > Michael
Re: [PATCH v3] cmd: mtd: check if a block has to be skipped or erased
On 30.10.2022 17:06, Dario Binacchi wrote:
> [External email]
>
>
>
>
>
> Hi Mikhail,
>
> On Wed, Oct 26, 2022 at 2:56 PM Mikhail Kshevetskiy
> wrote:
>> On 26.10.2022 09:29, Dario Binacchi wrote:
>>
>>> [External email]
>>>
>>>
>>>
>>>
>>>
>>> Hi Mikhail,
>>>
>>> On Mon, Oct 24, 2022 at 1:24 PM Mikhail Kshevetskiy
>>> wrote:
>>>> On 24.10.2022 12:44, Dario Binacchi wrote:
>>>>> [External email]
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>> From: Mikhail Kshevetskiy
>>>>>
>>>>> As reported by patch [1], the `mtd erase' command should not erase bad
>>>>> blocks.
>>>>> To force bad block erasing you have to use the `mtd erase.dontskipbad'
>>>>> command.
>>>>>
>>>>> This patch tries to fix the same issue without modifying code taken
>>>>> from the linux kernel, in order to make further upgrades easier.
>>>>>
>>>>> [1]
>>>>> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fall%2F20221006031501.110290-2-mikhail.kshevetskiy%40iopsys.eu%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7Cfe44aaf264764836295e08daba7ff1f7%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638027355932818989%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=TwMrP%2FpIz5R1Dfd1iXr8u2wZvDj3sdyl%2F8TADkPEDpQ%3Dreserved=0
>>>>> Suggested-by: Michael Trimarchi
>>>>> Co-developed-by: Michael Trimarchi
>>>>> Signed-off-by: Michael Trimarchi
>>>>> Co-developed-by: Dario Binacchi
>>>>> Signed-off-by: Dario Binacchi
>>>>> Tested-by: Mikhail Kshevetskiy
>>>>> Signed-off-by: Mikhail Kshevetskiy
>>>>>
>>>>> ---
>>>>>
>>>>> Changes in v3:
>>>>> - Simplify the code. mtd_erase() can't return a bad block error. Print
>>>>> the messaged where the bad block is found.
>>>>>
>>>>> Changes in v2:
>>>>> - Change the commit author
>>>>> - Do not continue to erase if scrub option is enabled and a bad block
>>>>> was found but return from the function.
>>>>> - Update the patch tags.
>>>>>
>>>>> cmd/mtd.c | 24
>>>>> 1 file changed, 16 insertions(+), 8 deletions(-)
>>>>>
>>>>> diff --git a/cmd/mtd.c b/cmd/mtd.c
>>>>> index ad5cc9827d55..29b2a9c04c0c 100644
>>>>> --- a/cmd/mtd.c
>>>>> +++ b/cmd/mtd.c
>>>>> @@ -434,19 +434,27 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
>>>>> flag, int argc,
>>>>> erase_op.mtd = mtd;
>>>>> erase_op.addr = off;
>>>>> erase_op.len = mtd->erasesize;
>>>>> - erase_op.scrub = scrub;
>>>>>
>>>>> while (len) {
>>>>> - ret = mtd_erase(mtd, _op);
>>>>> -
>>>>> - if (ret) {
>>>>> - /* Abort if its not a bad block error */
>>>>> - if (ret != -EIO)
>>>>> + if (!scrub) {
>>>>> + ret = mtd_block_isbad(mtd, erase_op.addr);
>>>>> + if (ret < 0) {
>>>>> + printf("Failed to get bad block at
>>>>> 0x%08llx\n",
>>>>> + erase_op.addr);
>>>>> + ret = CMD_RET_FAILURE;
>>>>> + goto out_put_mtd;
>>>>> + } else if (ret > 0) {
>>>>> + printf("Skipping bad block at 0x%08llx\n",
>>>>> + erase_op.addr);
>>>>> + ret = -EIO;
>>>>> break;
>>>>> - printf("Skipping bad block at 0x%08llx\n",
>>>>> - erase_op.addr);
>>>>> + }
>>>>> }
>>>>>
>>>>> + ret = mtd_erase(mtd, _op);
>&g
Re: [PATCH v3] cmd: mtd: check if a block has to be skipped or erased
On 26.10.2022 09:29, Dario Binacchi wrote:
> [External email]
>
>
>
>
>
> Hi Mikhail,
>
> On Mon, Oct 24, 2022 at 1:24 PM Mikhail Kshevetskiy
> wrote:
>>
>> On 24.10.2022 12:44, Dario Binacchi wrote:
>>> [External email]
>>>
>>>
>>>
>>>
>>>
>>> From: Mikhail Kshevetskiy
>>>
>>> As reported by patch [1], the `mtd erase' command should not erase bad
>>> blocks.
>>> To force bad block erasing you have to use the `mtd erase.dontskipbad'
>>> command.
>>>
>>> This patch tries to fix the same issue without modifying code taken
>>> from the linux kernel, in order to make further upgrades easier.
>>>
>>> [1]
>>> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fall%2F20221006031501.110290-2-mikhail.kshevetskiy%40iopsys.eu%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C02dff372bf00435cd94208dab71b6aed%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638023625630435867%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=YRmQ5XcWRw8gcy4Hy3nK29J%2FnttlD10lQvH%2B5YnBrxU%3Dreserved=0
>>> Suggested-by: Michael Trimarchi
>>> Co-developed-by: Michael Trimarchi
>>> Signed-off-by: Michael Trimarchi
>>> Co-developed-by: Dario Binacchi
>>> Signed-off-by: Dario Binacchi
>>> Tested-by: Mikhail Kshevetskiy
>>> Signed-off-by: Mikhail Kshevetskiy
>>>
>>> ---
>>>
>>> Changes in v3:
>>> - Simplify the code. mtd_erase() can't return a bad block error. Print
>>> the messaged where the bad block is found.
>>>
>>> Changes in v2:
>>> - Change the commit author
>>> - Do not continue to erase if scrub option is enabled and a bad block
>>> was found but return from the function.
>>> - Update the patch tags.
>>>
>>> cmd/mtd.c | 24
>>> 1 file changed, 16 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/cmd/mtd.c b/cmd/mtd.c
>>> index ad5cc9827d55..29b2a9c04c0c 100644
>>> --- a/cmd/mtd.c
>>> +++ b/cmd/mtd.c
>>> @@ -434,19 +434,27 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
>>> flag, int argc,
>>> erase_op.mtd = mtd;
>>> erase_op.addr = off;
>>> erase_op.len = mtd->erasesize;
>>> - erase_op.scrub = scrub;
>>>
>>> while (len) {
>>> - ret = mtd_erase(mtd, _op);
>>> -
>>> - if (ret) {
>>> - /* Abort if its not a bad block error */
>>> - if (ret != -EIO)
>>> + if (!scrub) {
>>> + ret = mtd_block_isbad(mtd, erase_op.addr);
>>> + if (ret < 0) {
>>> + printf("Failed to get bad block at
>>> 0x%08llx\n",
>>> + erase_op.addr);
>>> + ret = CMD_RET_FAILURE;
>>> + goto out_put_mtd;
>>> + } else if (ret > 0) {
>>> + printf("Skipping bad block at 0x%08llx\n",
>>> + erase_op.addr);
>>> + ret = -EIO;
>>> break;
>>> - printf("Skipping bad block at 0x%08llx\n",
>>> - erase_op.addr);
>>> + }
>>> }
>>>
>>> + ret = mtd_erase(mtd, _op);
>>> + if (ret)
>>> + break;
>>> +
>> mtd_erase() can return -EIO, see drivers/mtd/nand/spi/core.c function
>> spinand_mtd_erase()
> If I compare my original patch [1] with yours [2], I see no difference
> in behavior except for ret checking after calling
> mtd_erase() which, in my case, was wrong.
> Do you agree?
yes
> Further, checking for a bad block inside the do_mtd_erase(), the
> mtd_erase() can return -EIO only in the case of a protected
> block. In case of the scrub option enabled the bad block is erased,
> otherwise the block is jumped in the do_mtd_erase()
> without calling the mtd_erase().
I see -EIO error in the following cases
a) physical bad block
b) hardware failures (ex: some timeout expired)
maybe it also returned for protected block as
Re: [PATCH v3] cmd: mtd: check if a block has to be skipped or erased
On 24.10.2022 12:44, Dario Binacchi wrote:
> [External email]
>
>
>
>
>
> From: Mikhail Kshevetskiy
>
> As reported by patch [1], the `mtd erase' command should not erase bad
> blocks.
> To force bad block erasing you have to use the `mtd erase.dontskipbad'
> command.
>
> This patch tries to fix the same issue without modifying code taken
> from the linux kernel, in order to make further upgrades easier.
>
> [1]
> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fall%2F20221006031501.110290-2-mikhail.kshevetskiy%40iopsys.eu%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C0ce3c4f03458440084dd08dab5a44a0e%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638022014468655016%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=VMQov1%2FRUmymW2G452jlOveOu2tFCE5MtzssuP2Ri3Y%3Dreserved=0
> Suggested-by: Michael Trimarchi
> Co-developed-by: Michael Trimarchi
> Signed-off-by: Michael Trimarchi
> Co-developed-by: Dario Binacchi
> Signed-off-by: Dario Binacchi
> Tested-by: Mikhail Kshevetskiy
> Signed-off-by: Mikhail Kshevetskiy
>
> ---
>
> Changes in v3:
> - Simplify the code. mtd_erase() can't return a bad block error. Print
> the messaged where the bad block is found.
>
> Changes in v2:
> - Change the commit author
> - Do not continue to erase if scrub option is enabled and a bad block
> was found but return from the function.
> - Update the patch tags.
>
> cmd/mtd.c | 24
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/cmd/mtd.c b/cmd/mtd.c
> index ad5cc9827d55..29b2a9c04c0c 100644
> --- a/cmd/mtd.c
> +++ b/cmd/mtd.c
> @@ -434,19 +434,27 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
> flag, int argc,
> erase_op.mtd = mtd;
> erase_op.addr = off;
> erase_op.len = mtd->erasesize;
> - erase_op.scrub = scrub;
>
> while (len) {
> - ret = mtd_erase(mtd, _op);
> -
> - if (ret) {
> - /* Abort if its not a bad block error */
> - if (ret != -EIO)
> + if (!scrub) {
> + ret = mtd_block_isbad(mtd, erase_op.addr);
> + if (ret < 0) {
> + printf("Failed to get bad block at
> 0x%08llx\n",
> + erase_op.addr);
> + ret = CMD_RET_FAILURE;
> + goto out_put_mtd;
> + } else if (ret > 0) {
> + printf("Skipping bad block at 0x%08llx\n",
> + erase_op.addr);
> + ret = -EIO;
> break;
That is bad.//Skipping bad block is an expected behavior. We should not fail on
it.
> - printf("Skipping bad block at 0x%08llx\n",
> - erase_op.addr);
> + }
> }
>
> + ret = mtd_erase(mtd, _op);
> + if (ret)
> + break;
> +
> len -= mtd->erasesize;
> erase_op.addr += mtd->erasesize;
> }
> --
> 2.32.0
>
Re: [PATCH v2] cmd: mtd: check if a block has to be skipped or erased
What patch will be finally applied? I am preparing a patch that will
fix Dario Binacchi issues with non-BBT bad block.
>From my point of view this patch have wrong lines in 'Changes in v2'
- Do not continue to erase if scrub option is enabled and a bad block
was found but return from the function.
Issues of original Dario Binacchi patch:
Non-BBT registered bad block will break 'mtd erase'.
In this case
* mtd_erase() will returns with -EIO
* erasing will be stopped due to error
* 'mtd erase' returns CMD_RET_SUCCESS as -EIO is expected result
Fix this by:
a) return back -EIO check after mtd_erase()
b) simulate bad block behavior and jump to mtd_erase() results
check in the case of BBT registered bad block.
On 24.10.2022 12:35, Dario Binacchi wrote:
> [External email]
>
>
>
>
>
> From: Mikhail Kshevetskiy
>
> As reported by patch [1], the `mtd erase' command should not erase bad
> blocks.
> To force bad block erasing you have to use the `mtd erase.dontskipbad'
> command.
>
> This patch tries to fix the same issue without modifying code taken
> from the linux kernel, in order to make further upgrades easier.
>
> [1]
> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fall%2F20221006031501.110290-2-mikhail.kshevetskiy%40iopsys.eu%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C0b0682eb6b394b7b08dab5a31581%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638022009312464027%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=7Mx%2BHk7KIxaUitavWhTRwtfDL%2FaaOYA9o02oWFiFlw0%3Dreserved=0
> Suggested-by: Michael Trimarchi
> Co-developed-by: Michael Trimarchi
> Signed-off-by: Michael Trimarchi
> Co-developed-by: Dario Binacchi
> Signed-off-by: Dario Binacchi
> Tested-by: Mikhail Kshevetskiy
> Signed-off-by: Mikhail Kshevetskiy
>
> ---
>
> Changes in v2:
> - Change the commit author
> - Do not continue to erase if scrub option is enabled and a bad block
> was found but return from the function.
> - Update the patch tags.
>
> cmd/mtd.c | 17 +++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/cmd/mtd.c b/cmd/mtd.c
> index ad5cc9827d55..a314745e95e1 100644
> --- a/cmd/mtd.c
> +++ b/cmd/mtd.c
> @@ -434,11 +434,24 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
> flag, int argc,
> erase_op.mtd = mtd;
> erase_op.addr = off;
> erase_op.len = mtd->erasesize;
> - erase_op.scrub = scrub;
>
> while (len) {
> - ret = mtd_erase(mtd, _op);
> + if (!scrub) {
> + ret = mtd_block_isbad(mtd, erase_op.addr);
> + if (ret < 0) {
> + printf("Failed to get bad block at
> 0x%08llx\n",
> + erase_op.addr);
> + ret = CMD_RET_FAILURE;
> + goto out_put_mtd;
> + } else if (ret > 0) {
> + /* simulate bad block behavior */
> + ret = -EIO;
> + goto skip_block_erasing;
> + }
> + }
>
> + ret = mtd_erase(mtd, _op);
> +skip_block_erasing:
> if (ret) {
> /* Abort if its not a bad block error */
> if (ret != -EIO)
> --
> 2.32.0
>
Re: [PATCH] cmd: mtd: check if a block has to be skipped or erased
Signed-off-by: Mikhail Kshevetskiy
On 21.10.2022 18:29, Dario Binacchi wrote:
> [External email]
>
>
>
>
>
> As reported by patch [1], the `mtd erase' command should not erase bad
> blocks.
> To force bad block erasing you have to use the `mtd erase.dontskipbad'
> command.
>
> This patch tries to fix the same issue without modifying code taken
> from the linux kernel, in order to make further upgrades easier.
>
> [1]
> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fall%2F20221006031501.110290-2-mikhail.kshevetskiy%40iopsys.eu%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C914960325cd74fb7338208dab37913e4%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638019629853388501%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=6WBTjvbfll%2Boiz5B8q0o%2Bec0bWKCBf5RimWU1hZe61E%3Dreserved=0
> Signed-off-by: Dario Binacchi
> Suggested-by: Michael Trimarchi
> Co-developed-by: Michael Trimarchi
> Signed-off-by: Michael Trimarchi
> Cc: Mikhail Kshevetskiy
>
> ---
>
> cmd/mtd.c | 28
> 1 file changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/cmd/mtd.c b/cmd/mtd.c
> index ad5cc9827d55..3330a428c018 100644
> --- a/cmd/mtd.c
> +++ b/cmd/mtd.c
> @@ -434,19 +434,31 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
> flag, int argc,
> erase_op.mtd = mtd;
> erase_op.addr = off;
> erase_op.len = mtd->erasesize;
> - erase_op.scrub = scrub;
>
> while (len) {
> - ret = mtd_erase(mtd, _op);
> + if (!scrub) {
> + ret = mtd_block_isbad(mtd, erase_op.addr);
> + if (ret < 0) {
> + printf("Failed to get bad block at
> 0x%08llx\n",
> + erase_op.addr);
> + ret = CMD_RET_FAILURE;
> + goto out_put_mtd;
> + }
>
> - if (ret) {
> - /* Abort if its not a bad block error */
> - if (ret != -EIO)
> - break;
> - printf("Skipping bad block at 0x%08llx\n",
> - erase_op.addr);
> + if (ret > 0) {
> + printf("Skipping bad block at 0x%08llx\n",
> + erase_op.addr);
> + ret = 0;
> + len -= mtd->erasesize;
> + erase_op.addr += mtd->erasesize;
> + continue;
> + }
> }
>
> + ret = mtd_erase(mtd, _op);
> + if (ret)
> + break;
> +
> len -= mtd->erasesize;
> erase_op.addr += mtd->erasesize;
> }
> --
> 2.32.0
>
Re: [PATCH v3] cmd: mtd: check if a block has to be skipped or erased
On 24.10.2022 12:44, Dario Binacchi wrote:
> [External email]
>
>
>
>
>
> From: Mikhail Kshevetskiy
>
> As reported by patch [1], the `mtd erase' command should not erase bad
> blocks.
> To force bad block erasing you have to use the `mtd erase.dontskipbad'
> command.
>
> This patch tries to fix the same issue without modifying code taken
> from the linux kernel, in order to make further upgrades easier.
>
> [1]
> https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fall%2F20221006031501.110290-2-mikhail.kshevetskiy%40iopsys.eu%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C0ce3c4f03458440084dd08dab5a44a0e%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638022014468655016%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=VMQov1%2FRUmymW2G452jlOveOu2tFCE5MtzssuP2Ri3Y%3Dreserved=0
> Suggested-by: Michael Trimarchi
> Co-developed-by: Michael Trimarchi
> Signed-off-by: Michael Trimarchi
> Co-developed-by: Dario Binacchi
> Signed-off-by: Dario Binacchi
> Tested-by: Mikhail Kshevetskiy
> Signed-off-by: Mikhail Kshevetskiy
>
> ---
>
> Changes in v3:
> - Simplify the code. mtd_erase() can't return a bad block error. Print
> the messaged where the bad block is found.
>
> Changes in v2:
> - Change the commit author
> - Do not continue to erase if scrub option is enabled and a bad block
> was found but return from the function.
> - Update the patch tags.
>
> cmd/mtd.c | 24
> 1 file changed, 16 insertions(+), 8 deletions(-)
>
> diff --git a/cmd/mtd.c b/cmd/mtd.c
> index ad5cc9827d55..29b2a9c04c0c 100644
> --- a/cmd/mtd.c
> +++ b/cmd/mtd.c
> @@ -434,19 +434,27 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
> flag, int argc,
> erase_op.mtd = mtd;
> erase_op.addr = off;
> erase_op.len = mtd->erasesize;
> - erase_op.scrub = scrub;
>
> while (len) {
> - ret = mtd_erase(mtd, _op);
> -
> - if (ret) {
> - /* Abort if its not a bad block error */
> - if (ret != -EIO)
> + if (!scrub) {
> + ret = mtd_block_isbad(mtd, erase_op.addr);
> + if (ret < 0) {
> + printf("Failed to get bad block at
> 0x%08llx\n",
> + erase_op.addr);
> + ret = CMD_RET_FAILURE;
> + goto out_put_mtd;
> + } else if (ret > 0) {
> + printf("Skipping bad block at 0x%08llx\n",
> + erase_op.addr);
> + ret = -EIO;
> break;
> - printf("Skipping bad block at 0x%08llx\n",
> - erase_op.addr);
> + }
> }
>
> + ret = mtd_erase(mtd, _op);
> + if (ret)
> + break;
> +
mtd_erase() can return -EIO, see drivers/mtd/nand/spi/core.c function
spinand_mtd_erase()
> len -= mtd->erasesize;
> erase_op.addr += mtd->erasesize;
> }
> --
> 2.32.0
>
Re: [PATCH v2] cmd: mtd: try to erase bad blocks only if scrub flag is provided
On 24.10.2022 11:27, Michael Nazzareno Trimarchi wrote:
> [External email]
>
>
>
>
>
> Hi
>
> On Mon, Oct 24, 2022 at 10:20 AM Mikhail Kshevetskiy
> wrote:
>>
>> On 24.10.2022 10:49, Michael Nazzareno Trimarchi wrote:
>>> [External email]
>>>
>>>
>>>
>>>
>>>
>>> Hi Mikhail
>>>
>>> On Mon, Oct 24, 2022 at 9:37 AM Mikhail Kshevetskiy
>>> wrote:
>>>> 'mtd erase' command should not erase bad blocks. To force bad block erasing
>>>> there is 'mtd erase.dontskipbad' command. Unfortunately nand layer erases
>>>> bad blocks unconditionally. This is wrong.
>>>>
>>>> Fix issue by adding bad block checks to do_mtd_erase() function in the case
>>>> srub flag is not provided. We can't simplify code by eliminating -EIO
>>>> result
>>>> check of mtd_erase() as it will terminate erasing with CMD_RET_SUCCESS.
>>>>
>>>> Thanks to Dario Binacchi for his
>>>> patch.
>>>>
>>>> Signed-off-by: Mikhail Kshevetskiy
>>>> ---
>>>> cmd/mtd.c | 17 +++--
>>>> 1 file changed, 15 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/cmd/mtd.c b/cmd/mtd.c
>>>> index ad5cc9827d..a314745e95 100644
>>>> --- a/cmd/mtd.c
>>>> +++ b/cmd/mtd.c
>>>> @@ -434,11 +434,24 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
>>>> flag, int argc,
>>>> erase_op.mtd = mtd;
>>>> erase_op.addr = off;
>>>> erase_op.len = mtd->erasesize;
>>>> - erase_op.scrub = scrub;
>>>>
>>>> while (len) {
>>>> - ret = mtd_erase(mtd, _op);
>>>> + if (!scrub) {
>>>> + ret = mtd_block_isbad(mtd, erase_op.addr);
>>>> + if (ret < 0) {
>>>> + printf("Failed to get bad block at
>>>> 0x%08llx\n",
>>>> + erase_op.addr);
>>>> + ret = CMD_RET_FAILURE;
>>>> + goto out_put_mtd;
>>>> + } else if (ret > 0) {
>>>> + /* simulate bad block behavior */
>>>> + ret = -EIO;
>>>> + goto skip_block_erasing;
>>>> + }
>>>> + }
>>>>
>>>> + ret = mtd_erase(mtd, _op);
>>>> +skip_block_erasing:
>>>> if (ret) {
>>>> /* Abort if its not a bad block error */
>>>> if (ret != -EIO)
>>>> --
>>>> 2.35.1
>>>>
>>> As I stated in a different email. Please re-post with the right sign-off
>>>
>>> Michael
>> There is an issue with Dario Binacchi patch. Please see my comments for
>> his patch.
>>
>> I just suggest a fix. I am sorry if I do it wrong way.
>>
>> Mikhail
> There are two ways I can see:
> Repost the v3 starting from Dario one and improve the commit message
> for him. You can add your signed off and tested by or
> wait Dario to resend with all the suggestion you have made
>
> We think that you rise a correct problem and you help us to
> understand. We just decided to fix on uboot level and not core level.
>
> Michael
Is there a good way to apply Dario patch? It was sent as HTML message.
I can fix message body and apply it, but it will be better if Dario
resend it as normal clear text.
Mikhail
PS: I send patch for a second time because first time it was sent in
HTML format.
>
>>> --
>>> Michael Nazzareno Trimarchi
>>> Co-Founder & Chief Executive Officer
>>> M. +39 347 913 2170
>>> mich...@amarulasolutions.com
>>> __
>>>
>>> Amarula Solutions BV
>>> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
>>> T. +31 (0)85 111 9172
>>> i...@amarulasolutions.com
>>> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C2c68f94e89c247e2886f08dab5999790%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638021968536553670%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=GUYTrPb1VWhNN0EfEgV15jtuZxTldBB4qBpUsl%2Bd8H0%3Dreserved=0
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C2c68f94e89c247e2886f08dab5999790%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638021968536553670%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=GUYTrPb1VWhNN0EfEgV15jtuZxTldBB4qBpUsl%2Bd8H0%3Dreserved=0
Re: [PATCH v2] cmd: mtd: try to erase bad blocks only if scrub flag is provided
On 24.10.2022 10:49, Michael Nazzareno Trimarchi wrote:
> [External email]
>
>
>
>
>
> Hi Mikhail
>
> On Mon, Oct 24, 2022 at 9:37 AM Mikhail Kshevetskiy
> wrote:
>> 'mtd erase' command should not erase bad blocks. To force bad block erasing
>> there is 'mtd erase.dontskipbad' command. Unfortunately nand layer erases
>> bad blocks unconditionally. This is wrong.
>>
>> Fix issue by adding bad block checks to do_mtd_erase() function in the case
>> srub flag is not provided. We can't simplify code by eliminating -EIO result
>> check of mtd_erase() as it will terminate erasing with CMD_RET_SUCCESS.
>>
>> Thanks to Dario Binacchi for his patch.
>>
>> Signed-off-by: Mikhail Kshevetskiy
>> ---
>> cmd/mtd.c | 17 +++--
>> 1 file changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/cmd/mtd.c b/cmd/mtd.c
>> index ad5cc9827d..a314745e95 100644
>> --- a/cmd/mtd.c
>> +++ b/cmd/mtd.c
>> @@ -434,11 +434,24 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
>> flag, int argc,
>> erase_op.mtd = mtd;
>> erase_op.addr = off;
>> erase_op.len = mtd->erasesize;
>> - erase_op.scrub = scrub;
>>
>> while (len) {
>> - ret = mtd_erase(mtd, _op);
>> + if (!scrub) {
>> + ret = mtd_block_isbad(mtd, erase_op.addr);
>> + if (ret < 0) {
>> + printf("Failed to get bad block at
>> 0x%08llx\n",
>> + erase_op.addr);
>> + ret = CMD_RET_FAILURE;
>> + goto out_put_mtd;
>> + } else if (ret > 0) {
>> + /* simulate bad block behavior */
>> + ret = -EIO;
>> + goto skip_block_erasing;
>> + }
>> + }
>>
>> + ret = mtd_erase(mtd, _op);
>> +skip_block_erasing:
>> if (ret) {
>> /* Abort if its not a bad block error */
>> if (ret != -EIO)
>> --
>> 2.35.1
>>
> As I stated in a different email. Please re-post with the right sign-off
>
> Michael
There is an issue with Dario Binacchi patch. Please see my comments for
his patch.
I just suggest a fix. I am sorry if I do it wrong way.
Mikhail
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7Ca0041129e25a4456725708dab594462c%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638021945688614410%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=HASzL7T4QF8Kea8t6Dt7hQYnHGs1poC9gRPZ6N3SPEI%3Dreserved=0
Re: [PATCH] cmd: mtd: try to erase bad blocks only if scrub flag is provided
On 24.10.2022 10:36, Michael Nazzareno Trimarchi wrote:
> [External email]
>
>
>
>
>
> HI Mikhail
>
> On Mon, Oct 24, 2022 at 9:30 AM Mikhail Kshevetskiy
> wrote:
>> 'mtd erase' command should not erase bad blocks. To force bad block erasing
>> there is 'mtd erase.dontskipbad' command. Unfortunately nand layer erases
>> bad blocks unconditionally. This is wrong.
>>
>> Fix issue by adding bad block checks to do_mtd_erase() function in the case
>> srub flag is not provided. We can't simplify code by eliminating -EIO result
>> check of mtd_erase() as it will terminate erasing with CMD_RET_SUCCESS.
>>
>> Thanks to Dario Binacchi for his patch.
>>
>> Signed-off-by: Mikhail Kshevetskiy
>> ---
>> cmd/mtd.c | 17 +++--
>> 1 file changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/cmd/mtd.c b/cmd/mtd.c
>> index ad5cc9827d..a314745e95 100644
>> --- a/cmd/mtd.c
>> +++ b/cmd/mtd.c
>> @@ -434,11 +434,24 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int
>> flag, int argc,
>> erase_op.mtd = mtd;
>> erase_op.addr = off;
>> erase_op.len = mtd->erasesize;
>> - erase_op.scrub = scrub;
>>
>> while (len) {
>> - ret = mtd_erase(mtd, _op);
>> + if (!scrub) {
>> + ret = mtd_block_isbad(mtd, erase_op.addr);
>> + if (ret < 0) {
>> + printf("Failed to get bad block at 0x%08llx\n",
>> + erase_op.addr);
>> + ret = CMD_RET_FAILURE;
>> + goto out_put_mtd;
>> + } else if (ret > 0) {
>> + /* simulate bad block behavior */
>> + ret = -EIO;
>> + goto skip_block_erasing;
>> + }
>> + }
>>
> It's better to review the dario patch and we can resend with your
> signoff and comment too
>
> Michael
I already do it and just suggest a better version of his patch.
Mikhail
>> + ret = mtd_erase(mtd, _op);
>> +skip_block_erasing:
>> if (ret) {
>> /* Abort if its not a bad block error */
>> if (ret != -EIO)
>> --
>> 2.35.1
>>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C934733f81ca541502e1508dab5926d99%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638021937756458878%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=ydvGZ%2BeoO%2FonTzuVg3sStZZHSDFUeKxUhCrdwA48OB0%3Dreserved=0
[PATCH v2] cmd: mtd: try to erase bad blocks only if scrub flag is provided
'mtd erase' command should not erase bad blocks. To force bad block erasing
there is 'mtd erase.dontskipbad' command. Unfortunately nand layer erases
bad blocks unconditionally. This is wrong.
Fix issue by adding bad block checks to do_mtd_erase() function in the case
srub flag is not provided. We can't simplify code by eliminating -EIO result
check of mtd_erase() as it will terminate erasing with CMD_RET_SUCCESS.
Thanks to Dario Binacchi for his patch.
Signed-off-by: Mikhail Kshevetskiy
---
cmd/mtd.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/cmd/mtd.c b/cmd/mtd.c
index ad5cc9827d..a314745e95 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -434,11 +434,24 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag,
int argc,
erase_op.mtd = mtd;
erase_op.addr = off;
erase_op.len = mtd->erasesize;
- erase_op.scrub = scrub;
while (len) {
- ret = mtd_erase(mtd, _op);
+ if (!scrub) {
+ ret = mtd_block_isbad(mtd, erase_op.addr);
+ if (ret < 0) {
+ printf("Failed to get bad block at 0x%08llx\n",
+ erase_op.addr);
+ ret = CMD_RET_FAILURE;
+ goto out_put_mtd;
+ } else if (ret > 0) {
+ /* simulate bad block behavior */
+ ret = -EIO;
+ goto skip_block_erasing;
+ }
+ }
+ ret = mtd_erase(mtd, _op);
+skip_block_erasing:
if (ret) {
/* Abort if its not a bad block error */
if (ret != -EIO)
--
2.35.1
[PATCH] cmd: mtd: try to erase bad blocks only if scrub flag is provided
'mtd erase' command should not erase bad blocks. To force bad block erasing
there is 'mtd erase.dontskipbad' command. Unfortunately nand layer erases
bad blocks unconditionally. This is wrong.
Fix issue by adding bad block checks to do_mtd_erase() function in the case
srub flag is not provided. We can't simplify code by eliminating -EIO result
check of mtd_erase() as it will terminate erasing with CMD_RET_SUCCESS.
Thanks to Dario Binacchi for his patch.
Signed-off-by: Mikhail Kshevetskiy
---
cmd/mtd.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/cmd/mtd.c b/cmd/mtd.c
index ad5cc9827d..a314745e95 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -434,11 +434,24 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag,
int argc,
erase_op.mtd = mtd;
erase_op.addr = off;
erase_op.len = mtd->erasesize;
- erase_op.scrub = scrub;
while (len) {
- ret = mtd_erase(mtd, _op);
+ if (!scrub) {
+ ret = mtd_block_isbad(mtd, erase_op.addr);
+ if (ret < 0) {
+ printf("Failed to get bad block at 0x%08llx\n",
+ erase_op.addr);
+ ret = CMD_RET_FAILURE;
+ goto out_put_mtd;
+ } else if (ret > 0) {
+ /* simulate bad block behavior */
+ ret = -EIO;
+ goto skip_block_erasing;
+ }
+ }
+ ret = mtd_erase(mtd, _op);
+skip_block_erasing:
if (ret) {
/* Abort if its not a bad block error */
if (ret != -EIO)
--
2.35.1
Re: [PATCH] cmd: mtd: check if a block has to be skipped or erased
On 21.10.2022 18:29, Dario Binacchi wrote:
[External email]
As reported by patch [1], the `mtd erase' command should not erase bad
blocks.
To force bad block erasing you have to use the `mtd erase.dontskipbad'
command.
This patch tries to fix the same issue without modifying code taken
from the linux kernel, in order to make further upgrades easier.
[1]
https://eur03.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.kernel.org%2Fall%2F20221006031501.110290-2-mikhail.kshevetskiy%40iopsys.eu%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C914960325cd74fb7338208dab37913e4%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638019629853388501%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=6WBTjvbfll%2Boiz5B8q0o%2Bec0bWKCBf5RimWU1hZe61E%3Dreserved=0
Signed-off-by: Dario Binacchi
Suggested-by: Michael Trimarchi
Co-developed-by: Michael Trimarchi
Signed-off-by: Michael Trimarchi
Cc: Mikhail Kshevetskiy
---
cmd/mtd.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/cmd/mtd.c b/cmd/mtd.c
index ad5cc9827d55..3330a428c018 100644
--- a/cmd/mtd.c
+++ b/cmd/mtd.c
@@ -434,19 +434,31 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag,
int argc,
erase_op.mtd = mtd;
erase_op.addr = off;
erase_op.len = mtd->erasesize;
- erase_op.scrub = scrub;
while (len) {
- ret = mtd_erase(mtd, _op);
+ if (!scrub) {
+ ret = mtd_block_isbad(mtd, erase_op.addr);
+ if (ret < 0) {
+ printf("Failed to get bad block at 0x%08llx\n",
+ erase_op.addr);
+ ret = CMD_RET_FAILURE;
+ goto out_put_mtd;
+ }
- if (ret) {
- /* Abort if its not a bad block error */
- if (ret != -EIO)
- break;
- printf("Skipping bad block at 0x%08llx\n",
- erase_op.addr);
+ if (ret > 0) {
+ printf("Skipping bad block at 0x%08llx\n",
+ erase_op.addr);
+ ret = 0;
+ len -= mtd->erasesize;
+ erase_op.addr += mtd->erasesize;
+ continue;
+ }
}
+ ret = mtd_erase(mtd, _op);
+ if (ret)
+ break;
+
You should check for bad block here, otherwise bad block not marked in
BBT will terminate erasing with CMD_RET_SUCCESS result.
len -= mtd->erasesize;
erase_op.addr += mtd->erasesize;
}
--
2.32.0
Re: [PATCH 2/7] mtd/nand: try to erase bad blocks only if scrub flag is provided
On Thu, 6 Oct 2022 20:09:11 +0200
Michael Nazzareno Trimarchi wrote:
> [External email]
>
>
>
>
>
> Hi Mikhail
>
> On Thu, Oct 6, 2022 at 6:17 PM Mikhail Kshevetskiy
> wrote:
> >
> > On Thu, 6 Oct 2022 18:03:17 +0200
> > Michael Nazzareno Trimarchi wrote:
> >
> > > [External email]
> > >
> > >
> > >
> > >
> > >
> > > On Thu, Oct 6, 2022 at 5:52 PM Mikhail Kshevetskiy
> > > wrote:
> > > >
> > > > On Thu, 6 Oct 2022 08:56:08 +0200
> > > > Michael Nazzareno Trimarchi wrote:
> > > >
> > > > > [External email]
> > > > >
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > Hi
> > > > >
> > > > > On Thu, Oct 6, 2022 at 5:15 AM wrote:
> > > > > >
> > > > > > From: Mikhail Kshevetskiy
> > > > > >
> > > > > > 'mtd erase' command should not erase bad blocks. To force bad block
> > > > > > erasing there is 'mtd erase.dontskipbad' command (this command sets
> > > > > > 'scrub' flag to true in the erase_info structure). Unfortunately
> > > > > > nand layer ignore scrub flag and try to erases bad blocks
> > > > > > unconditionally. This is wrong.
> > > > > >
> > > > > > Add checks to allow bad block erasing only if scrub flag is set.
> > > > > >
> > > > > > Signed-off-by: Mikhail Kshevetskiy
> > > > > > ---
> > > > > > drivers/mtd/nand/core.c | 5 -
> > > > > > 1 file changed, 4 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
> > > > > > index 99c29670c7..a4fb7602c9 100644
> > > > > > --- a/drivers/mtd/nand/core.c
> > > > > > +++ b/drivers/mtd/nand/core.c
> > > > > > @@ -174,7 +174,10 @@ int nanddev_mtd_erase(struct mtd_info *mtd,
> > > > > > struct erase_info *einfo) nanddev_offs_to_pos(nand, einfo->addr +
> > > > > > einfo->len - 1, ); while (nanddev_pos_cmp(, ) <= 0) {
> > > > > > schedule();
> > > > > > - ret = nanddev_erase(nand, );
> > > > > > + if (!einfo->scrub && nanddev_isbad(nand, ))
> > > > >
> > > > > The nandev_erase already check it here:
> > > > >
> > > > > if (nanddev_isbad(nand, pos) || nanddev_isreserved(nand, pos)) {
> > > > >
> > > >
> > > > no it does not work. see nanddev_erase() code
> > > >
> > >
> > > Let me re-formulate it. What execution path are you taking into account?
> > >
> > > The nand are erased using the cmd/nand interface and the erase command
> > > there calls nand_erase_opts that take in account it.
> >
> > spi-nand flash
> >
> > cmd/mtd.c -> do_mtd_erase() -> -> nanddev_mtd_erase() ->
> > nanddev_erase()
> >
>
> Ok now it's clear. I'm thinking and i have create a patch if we can
> use somenthing like this
>
> Not tested
>
>
> @@ -393,7 +394,7 @@ out_put_mtd:
> static int do_mtd_erase(struct cmd_tbl *cmdtp, int flag, int argc,
> char *const argv[])
> {
> - struct erase_info erase_op = {};
> + nand_erase_options_t opts = {};
> struct mtd_info *mtd;
> u64 off, len;
> bool scrub;
> @@ -431,26 +432,11 @@ static int do_mtd_erase(struct cmd_tbl *cmdtp,
> int flag, int argc,
> printf("Erasing 0x%08llx ... 0x%08llx (%d eraseblock(s))\n",
>off, off + len - 1, mtd_div_by_eb(len, mtd));
>
> - erase_op.mtd = mtd;
> - erase_op.addr = off;
> - erase_op.len = mtd->erasesize;
> - erase_op.scrub = scrub;
> -
> - while (len) {
> - ret = mtd_erase(mtd, _op);
> -
> - if (ret) {
> - /* Abort if its not a bad block error */
> - if (ret != -EIO)
> - break;
> - printf("Skipping bad block at 0x%08llx\n",
> - erase_op.addr);
> - }
> -
> - len -= mtd->erasesize;
> - erase_op.addr += mtd->
Re: [PATCH 2/7] mtd/nand: try to erase bad blocks only if scrub flag is provided
On Thu, 6 Oct 2022 18:03:17 +0200
Michael Nazzareno Trimarchi wrote:
> [External email]
>
>
>
>
>
> On Thu, Oct 6, 2022 at 5:52 PM Mikhail Kshevetskiy
> wrote:
> >
> > On Thu, 6 Oct 2022 08:56:08 +0200
> > Michael Nazzareno Trimarchi wrote:
> >
> > > [External email]
> > >
> > >
> > >
> > >
> > >
> > > Hi
> > >
> > > On Thu, Oct 6, 2022 at 5:15 AM wrote:
> > > >
> > > > From: Mikhail Kshevetskiy
> > > >
> > > > 'mtd erase' command should not erase bad blocks. To force bad block
> > > > erasing there is 'mtd erase.dontskipbad' command (this command sets
> > > > 'scrub' flag to true in the erase_info structure). Unfortunately nand
> > > > layer ignore scrub flag and try to erases bad blocks unconditionally.
> > > > This is wrong.
> > > >
> > > > Add checks to allow bad block erasing only if scrub flag is set.
> > > >
> > > > Signed-off-by: Mikhail Kshevetskiy
> > > > ---
> > > > drivers/mtd/nand/core.c | 5 -
> > > > 1 file changed, 4 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
> > > > index 99c29670c7..a4fb7602c9 100644
> > > > --- a/drivers/mtd/nand/core.c
> > > > +++ b/drivers/mtd/nand/core.c
> > > > @@ -174,7 +174,10 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct
> > > > erase_info *einfo) nanddev_offs_to_pos(nand, einfo->addr + einfo->len -
> > > > 1, ); while (nanddev_pos_cmp(, ) <= 0) {
> > > > schedule();
> > > > - ret = nanddev_erase(nand, );
> > > > + if (!einfo->scrub && nanddev_isbad(nand, ))
> > >
> > > The nandev_erase already check it here:
> > >
> > > if (nanddev_isbad(nand, pos) || nanddev_isreserved(nand, pos)) {
> > >
> >
> > no it does not work. see nanddev_erase() code
> >
>
> Let me re-formulate it. What execution path are you taking into account?
>
> The nand are erased using the cmd/nand interface and the erase command
> there calls nand_erase_opts that take in account it.
spi-nand flash
cmd/mtd.c -> do_mtd_erase() -> -> nanddev_mtd_erase() -> nanddev_erase()
>
> Michael
>
>
>
> The nand is erased using the
> > if block is bad or reserverved, than warning is printed, than block is
> > erased.
> >
> >
> > > > + ret = -EIO;
> > > > + else
> > > > + ret = nanddev_erase(nand, );
> > >
> > > erase opt should already take in account scrub.
> > >
> > > Please extend the problem
> > >
> > > Michael
> > > > if (ret) {
> > > > einfo->fail_addr = nanddev_pos_to_offs(nand,
> > > > );
> > > >
> > > > --
> > > > 2.35.1
> > > >
> > >
> > >
> > > --
> > > Michael Nazzareno Trimarchi
> > > Co-Founder & Chief Executive Officer
> > > M. +39 347 913 2170
> > > mich...@amarulasolutions.com
> > > __
> > >
> > > Amarula Solutions BV
> > > Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> > > T. +31 (0)85 111 9172
> > > i...@amarulasolutions.com
> > > https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C220e94cc3ad54f5ccca108daa7b44fe6%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638006690117535825%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=zTEEwU%2BKnLWNDq5xs77MmD6SI%2F31bRf3fEx%2Fyaa65%2FU%3Dreserved=0
>
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C220e94cc3ad54f5ccca108daa7b44fe6%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638006690117535825%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=zTEEwU%2BKnLWNDq5xs77MmD6SI%2F31bRf3fEx%2Fyaa65%2FU%3Dreserved=0
Re: [PATCH 2/7] mtd/nand: try to erase bad blocks only if scrub flag is provided
On Thu, 6 Oct 2022 08:56:08 +0200
Michael Nazzareno Trimarchi wrote:
> [External email]
>
>
>
>
>
> Hi
>
> On Thu, Oct 6, 2022 at 5:15 AM wrote:
> >
> > From: Mikhail Kshevetskiy
> >
> > 'mtd erase' command should not erase bad blocks. To force bad block erasing
> > there is 'mtd erase.dontskipbad' command (this command sets 'scrub' flag
> > to true in the erase_info structure). Unfortunately nand layer ignore
> > scrub flag and try to erases bad blocks unconditionally. This is wrong.
> >
> > Add checks to allow bad block erasing only if scrub flag is set.
> >
> > Signed-off-by: Mikhail Kshevetskiy
> > ---
> > drivers/mtd/nand/core.c | 5 -
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
> > index 99c29670c7..a4fb7602c9 100644
> > --- a/drivers/mtd/nand/core.c
> > +++ b/drivers/mtd/nand/core.c
> > @@ -174,7 +174,10 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct
> > erase_info *einfo) nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1,
> > ); while (nanddev_pos_cmp(, ) <= 0) {
> > schedule();
> > - ret = nanddev_erase(nand, );
> > + if (!einfo->scrub && nanddev_isbad(nand, ))
>
> The nandev_erase already check it here:
>
> if (nanddev_isbad(nand, pos) || nanddev_isreserved(nand, pos)) {
>
no it does not work. see nanddev_erase() code
if block is bad or reserverved, than warning is printed, than block is erased.
> > + ret = -EIO;
> > + else
> > + ret = nanddev_erase(nand, );
>
> erase opt should already take in account scrub.
>
> Please extend the problem
>
> Michael
> > if (ret) {
> > einfo->fail_addr = nanddev_pos_to_offs(nand, );
> >
> > --
> > 2.35.1
> >
>
>
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
>
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> https://eur03.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.amarulasolutions.com%2Fdata=05%7C01%7Cmikhail.kshevetskiy%40iopsys.eu%7C0271cbe11c804a8dfde608daa767e01b%7C7ff78d652de440f586750569e5c7a65d%7C0%7C0%7C638006361837818885%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7Csdata=ZmdqQp%2FXl4XC7yFKmFEYWocIEsqQGYk8b2UI9i2cibo%3Dreserved=0
[PATCH 7/7] net/tftp: make tftpput working with servers that do not use OACK
From: Mikhail Kshevetskiy
Signed-off-by: Mikhail Kshevetskiy
---
net/tftp.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/net/tftp.c b/net/tftp.c
index dea9c25ffd..e120e4d766 100644
--- a/net/tftp.c
+++ b/net/tftp.c
@@ -483,8 +483,15 @@ static void tftp_handler(uchar *pkt, unsigned dest, struct
in_addr sip,
tftp_prev_block = tftp_cur_block;
tftp_cur_block = (unsigned short)(block + 1);
update_block_number();
- if (ack_ok)
+ if (ack_ok) {
+ if (block == 0 &&
+ tftp_state == STATE_SEND_WRQ){
+ /* connection's first ACK */
+ tftp_state = STATE_DATA;
+ tftp_remote_port = src;
+ }
tftp_send(); /* Send next data block */
+ }
}
}
#endif
--
2.35.1
[PATCH 5/7] mtd/spinand: sync supported devices with linux-5.15.43
From: Mikhail Kshevetskiy
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/nand/spi/Makefile | 2 +-
drivers/mtd/nand/spi/core.c | 1 +
drivers/mtd/nand/spi/gigadevice.c | 223 ++
drivers/mtd/nand/spi/macronix.c | 145 +--
drivers/mtd/nand/spi/micron.c | 144 +--
drivers/mtd/nand/spi/paragon.c| 133 ++
drivers/mtd/nand/spi/toshiba.c| 38 ++---
drivers/mtd/nand/spi/winbond.c| 6 +-
include/linux/mtd/nand.h | 5 +-
include/linux/mtd/spinand.h | 31 +
10 files changed, 626 insertions(+), 102 deletions(-)
create mode 100644 drivers/mtd/nand/spi/paragon.c
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index 6c65b187e8..3051de4f7e 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o gigadevice.o macronix.o micron.o toshiba.o winbond.o
+spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o
winbond.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index d0c7d82010..52a15b30ef 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -824,6 +824,7 @@ static const struct spinand_manufacturer
*spinand_manufacturers[] = {
_spinand_manufacturer,
_spinand_manufacturer,
_spinand_manufacturer,
+ _spinand_manufacturer,
_spinand_manufacturer,
_spinand_manufacturer,
};
diff --git a/drivers/mtd/nand/spi/gigadevice.c
b/drivers/mtd/nand/spi/gigadevice.c
index 370ffb765e..0635808715 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -7,13 +7,13 @@
*/
#ifndef __UBOOT__
-#include
#include
#include
#endif
#include
#define SPINAND_MFR_GIGADEVICE 0xC8
+
#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
@@ -22,8 +22,12 @@
#define GD5FXGQXXEXXG_REG_STATUS2 0xf0
-/* Q4 devices, QUADIO: Dummy bytes valid for 1 and 2 GBit variants */
-static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
+#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
+#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
+#define GD5FXGQ4UXFXXG_STATUS_ECC_1_3_BITFLIPS (1 << 4)
+#define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
@@ -31,14 +35,13 @@ static SPINAND_OP_VARIANTS(gd5fxgq4_read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
-/* Q5 devices, QUADIO: Dummy bytes only valid for 1 GBit variants */
-static SPINAND_OP_VARIANTS(gd5f1gq5_read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+static SPINAND_OP_VARIANTS(read_cache_variants_f,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
@@ -48,7 +51,65 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
-static int gd5fxgqxxexxg_ooblayout_ecc(struct mtd_info *mtd, int section,
+static int gd5fxgq4xa_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 8;
+ region->length = 8;
+
+ return 0;
+}
+
+static int gd5fxgq4xa_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ if (section) {
+ region->offset = 16 * section;
+ region->length = 8;
+ } else {
+
[PATCH 6/7] mtd/spinand: add Winbond W25N02KV flash support, fix Winbond flashes identifications
From: Mikhail Kshevetskiy
Winbond uses 3 bytes to identify flash: vendor_id, dev_id_0, dev_id_1,
but current driver uses only first 2 bytes of it for devices
idenfification. As result Winbond W25N02KV flash (id_bytes: EF, AA, 22)
is identified as W25N01GV (id_bytes: EF, AA, 21).
Fix this and add W25N02KV flash support.
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/nand/spi/winbond.c | 80 +-
1 file changed, 78 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index 7f991ed75e..19e5c863e8 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -11,6 +11,7 @@
#include
#include
#endif
+#include
#include
#define SPINAND_MFR_WINBOND0xEF
@@ -76,9 +77,75 @@ static int w25m02gv_select_target(struct spinand_device
*spinand,
return spi_mem_exec_op(spinand->slave, );
}
+static int w25n02kv_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = 64 + (16 * section);
+ region->length = 13;
+
+ return 0;
+}
+
+static int w25n02kv_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 14;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops w25n02kv_ooblayout = {
+ .ecc = w25n02kv_ooblayout_ecc,
+ .free = w25n02kv_ooblayout_free,
+};
+
+static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 mbf = 0;
+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(0x30, );
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ /*
+* Let's try to retrieve the real maximum number of bitflips
+* in order to avoid forcing the wear-leveling layer to move
+* data around if it's not necessary.
+*/
+ if (spi_mem_exec_op(spinand->slave, ))
+ return nand->eccreq.strength;
+
+ mbf >>= 4;
+
+ if (WARN_ON(mbf > nand->eccreq.strength || !mbf))
+ return nand->eccreq.strength;
+
+ return mbf;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
static const struct spinand_info winbond_spinand_table[] = {
SPINAND_INFO("W25M02GV",
-SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab),
+SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 2),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(_cache_variants,
@@ -88,7 +155,7 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ECCINFO(_ooblayout, NULL),
SPINAND_SELECT_TARGET(w25m02gv_select_target)),
SPINAND_INFO("W25N01GV",
-SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa),
+SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x21),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(_cache_variants,
@@ -96,6 +163,15 @@ static const struct spinand_info winbond_spinand_table[] = {
_cache_variants),
0,
SPINAND_ECCINFO(_ooblayout, NULL)),
+ SPINAND_INFO("W25N02KV",
+SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
+NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
+NAND_ECCREQ(8, 512),
+SPINAND_INFO_OP_VARIANTS(_cache_variants,
+ _cache_variants,
+ _cache_variants),
+0,
+SPINAND_ECCINFO(_ooblayout,
w25n02kv_ecc_get_status)),
};
static int winbond_spinand_init(struct spinand_device *spinand)
--
2.35.1
[PATCH 4/7] mtd/spinand: sync core spinand code with linux-5.10.118
From: Mikhail Kshevetskiy
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/nand/spi/core.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index e42c061049..d0c7d82010 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -326,6 +326,13 @@ static int spinand_write_to_cache_op(struct spinand_device
*spinand,
u16 column = 0;
int ret;
+ /*
+* Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
+* the cache content to 0xFF (depends on vendor implementation), so we
+* must fill the page cache entirely even if we only want to program
+* the data portion of the page, otherwise we might corrupt the BBM or
+* user data previously programmed in OOB area.
+*/
memset(spinand->databuf, 0xff,
nanddev_page_size(nand) +
nanddev_per_page_oobsize(nand));
@@ -598,12 +605,12 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t
from,
if (ret == -EBADMSG) {
ecc_failed = true;
mtd->ecc_stats.failed++;
- ret = 0;
} else {
mtd->ecc_stats.corrected += ret;
max_bitflips = max_t(unsigned int, max_bitflips, ret);
}
+ ret = 0;
ops->retlen += iter.req.datalen;
ops->oobretlen += iter.req.ooblen;
}
@@ -669,16 +676,9 @@ static bool spinand_isbad(struct nand_device *nand, const
struct nand_pos *pos)
.oobbuf.in = marker,
.mode = MTD_OPS_RAW,
};
- int ret;
-
- ret = spinand_select_target(spinand, pos->target);
- if (ret)
- return ret;
-
- ret = spinand_read_page(spinand, , false);
- if (ret)
- return ret;
+ spinand_select_target(spinand, pos->target);
+ spinand_read_page(spinand, , false);
if (marker[0] != 0xff || marker[1] != 0xff)
return true;
@@ -722,6 +722,10 @@ static int spinand_markbad(struct nand_device *nand, const
struct nand_pos *pos)
if (ret)
return ret;
+ ret = spinand_write_enable_op(spinand);
+ if (ret)
+ return ret;
+
return spinand_write_page(spinand, );
}
--
2.35.1
[PATCH 3/7] mtd/spinand: rework detect procedure for different READ_ID operation
From: Mikhail Kshevetskiy
Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.
Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:
1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.
2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.
This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.
This is a rework of Chuanhong Guo patch
submitted to linux kernel
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/nand/spi/core.c | 104 +++---
drivers/mtd/nand/spi/gigadevice.c | 30 ++---
drivers/mtd/nand/spi/macronix.c | 45 +
drivers/mtd/nand/spi/micron.c | 50 ++
drivers/mtd/nand/spi/toshiba.c| 66 +--
drivers/mtd/nand/spi/winbond.c| 34 ++
include/linux/mtd/spinand.h | 66 ---
7 files changed, 187 insertions(+), 208 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 4edb7ae952..e42c061049 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#else
@@ -451,9 +452,11 @@ out:
return status & STATUS_BUSY ? -ETIMEDOUT : 0;
}
-static int spinand_read_id_op(struct spinand_device *spinand, u8 *buf)
+static int spinand_read_id_op(struct spinand_device *spinand, u8 naddr,
+ u8 ndummy, u8 *buf)
{
- struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
+ struct spi_mem_op op = SPINAND_READID_OP(naddr, ndummy,
+spinand->scratchbuf,
SPINAND_MAX_ID_LEN);
int ret;
@@ -807,21 +810,6 @@ static int spinand_mtd_block_isreserved(struct mtd_info
*mtd, loff_t offs)
return ret;
}
-const struct spi_mem_op *
-spinand_find_supported_op(struct spinand_device *spinand,
- const struct spi_mem_op *ops,
- unsigned int nops)
-{
- unsigned int i;
-
- for (i = 0; i < nops; i++) {
- if (spi_mem_supports_op(spinand->slave, [i]))
- return [i];
- }
-
- return NULL;
-}
-
static const struct nand_ops spinand_ops = {
.erase = spinand_erase,
.markbad = spinand_markbad,
@@ -836,24 +824,62 @@ static const struct spinand_manufacturer
*spinand_manufacturers[] = {
_spinand_manufacturer,
};
-static int spinand_manufacturer_detect(struct spinand_device *spinand)
+static int spinand_manufacturer_match(struct spinand_device *spinand,
+ enum spinand_readid_method rdid_method)
{
+ u8 *id = spinand->id.data;
unsigned int i;
int ret;
for (i = 0; i < ARRAY_SIZE(spinand_manufacturers); i++) {
- ret = spinand_manufacturers[i]->ops->detect(spinand);
- if (ret > 0) {
- spinand->manufacturer = spinand_manufacturers[i];
- return 0;
- } else if (ret < 0) {
- return ret;
- }
- }
+ const struct spinand_manufacturer *manufacturer =
+ spinand_manufacturers[i];
+ if (id[0] != manufacturer->id)
+ continue;
+
+ ret = spinand_match_and_init(spinand,
+manufacturer->chips,
+manufacturer->nchips,
+rdid_method);
+ if (ret < 0)
+ continue;
+
+ spinand->manufacturer = manufacturer;
+ return 0;
+ }
return -ENOTSUPP;
}
+static int spinand_id_detect(struct spinand_device *spinand)
+{
+ u8 *id = spinand->id.data;
+ int ret;
+
+ ret = spinand_read_id_op(spinand, 0, 0, id);
+ if (ret)
+ return ret;
+ ret = spinand_manufacturer_match(spinand, SPINAND_READID_METHOD_OPCODE);
+ if (!ret)
+ return 0;
+
+ ret = spinand_read_id_op(spinand, 1, 0, id);
+ if (ret)
+ retur
[PATCH 2/7] mtd/nand: try to erase bad blocks only if scrub flag is provided
From: Mikhail Kshevetskiy
'mtd erase' command should not erase bad blocks. To force bad block erasing
there is 'mtd erase.dontskipbad' command (this command sets 'scrub' flag
to true in the erase_info structure). Unfortunately nand layer ignore
scrub flag and try to erases bad blocks unconditionally. This is wrong.
Add checks to allow bad block erasing only if scrub flag is set.
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/nand/core.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 99c29670c7..a4fb7602c9 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -174,7 +174,10 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct
erase_info *einfo)
nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1, );
while (nanddev_pos_cmp(, ) <= 0) {
schedule();
- ret = nanddev_erase(nand, );
+ if (!einfo->scrub && nanddev_isbad(nand, ))
+ ret = -EIO;
+ else
+ ret = nanddev_erase(nand, );
if (ret) {
einfo->fail_addr = nanddev_pos_to_offs(nand, );
--
2.35.1
[PATCH 1/7] mtd: replace name of 'rfree' field with 'free' in struct mtd_ooblayout_ops to better match it's description
From: Mikhail Kshevetskiy
In the description of struct mtd_ooblayout_ops we see:
* @free: function returning a free region in the OOB area.
*Should return -ERANGE if %section exceeds the total number of
*free sections.
but corresponding field of the structure named as 'rfree'. This is
wrong. Fix it the asme way as was done previously in linux kernel.
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/mtdcore.c| 4 ++--
drivers/mtd/nand/raw/denali.c| 2 +-
drivers/mtd/nand/raw/octeontx_nand.c | 2 +-
drivers/mtd/nand/raw/rockchip_nfc.c | 2 +-
drivers/mtd/nand/spi/core.c | 2 +-
drivers/mtd/nand/spi/gigadevice.c| 2 +-
drivers/mtd/nand/spi/macronix.c | 2 +-
drivers/mtd/nand/spi/micron.c| 2 +-
drivers/mtd/nand/spi/toshiba.c | 2 +-
drivers/mtd/nand/spi/winbond.c | 2 +-
include/linux/mtd/mtd.h | 4 ++--
11 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c
index aa78d41a55..df8f3b8284 100644
--- a/drivers/mtd/mtdcore.c
+++ b/drivers/mtd/mtdcore.c
@@ -1208,10 +1208,10 @@ int mtd_ooblayout_free(struct mtd_info *mtd, int
section,
if (!mtd || section < 0)
return -EINVAL;
- if (!mtd->ooblayout || !mtd->ooblayout->rfree)
+ if (!mtd->ooblayout || !mtd->ooblayout->free)
return -ENOTSUPP;
- return mtd->ooblayout->rfree(mtd, section, oobfree);
+ return mtd->ooblayout->free(mtd, section, oobfree);
}
EXPORT_SYMBOL_GPL(mtd_ooblayout_free);
diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
index c827f80281..ed24b84d82 100644
--- a/drivers/mtd/nand/raw/denali.c
+++ b/drivers/mtd/nand/raw/denali.c
@@ -1166,7 +1166,7 @@ static int denali_ooblayout_free(struct mtd_info *mtd,
int section,
static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
.ecc = denali_ooblayout_ecc,
- .rfree = denali_ooblayout_free,
+ .free = denali_ooblayout_free,
};
static int denali_multidev_fixup(struct denali_nand_info *denali)
diff --git a/drivers/mtd/nand/raw/octeontx_nand.c
b/drivers/mtd/nand/raw/octeontx_nand.c
index b338b204f3..4023bbcec6 100644
--- a/drivers/mtd/nand/raw/octeontx_nand.c
+++ b/drivers/mtd/nand/raw/octeontx_nand.c
@@ -435,7 +435,7 @@ static int nand_ooblayout_free_lp(struct mtd_info *mtd, int
section,
static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = {
.ecc = nand_ooblayout_ecc_lp,
- .rfree = nand_ooblayout_free_lp,
+ .free = nand_ooblayout_free_lp,
};
static inline struct octeontx_nand_chip *to_otx_nand(struct nand_chip *nand)
diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c
b/drivers/mtd/nand/raw/rockchip_nfc.c
index d016d25575..1ab429f430 100644
--- a/drivers/mtd/nand/raw/rockchip_nfc.c
+++ b/drivers/mtd/nand/raw/rockchip_nfc.c
@@ -849,7 +849,7 @@ static int rk_nfc_ooblayout_ecc(struct mtd_info *mtd, int
section,
}
static const struct mtd_ooblayout_ops rk_nfc_ooblayout_ops = {
- .rfree = rk_nfc_ooblayout_free,
+ .free = rk_nfc_ooblayout_free,
.ecc = rk_nfc_ooblayout_ecc,
};
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 134bf22c80..4edb7ae952 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1021,7 +1021,7 @@ static int spinand_noecc_ooblayout_free(struct mtd_info
*mtd, int section,
static const struct mtd_ooblayout_ops spinand_noecc_ooblayout = {
.ecc = spinand_noecc_ooblayout_ecc,
- .rfree = spinand_noecc_ooblayout_free,
+ .free = spinand_noecc_ooblayout_free,
};
static int spinand_init(struct spinand_device *spinand)
diff --git a/drivers/mtd/nand/spi/gigadevice.c
b/drivers/mtd/nand/spi/gigadevice.c
index a2c93486f4..25d9f80d26 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -154,7 +154,7 @@ static int gd5fxgq5xexxg_ecc_get_status(struct
spinand_device *spinand,
static const struct mtd_ooblayout_ops gd5fxgqxxexxg_ooblayout = {
.ecc = gd5fxgqxxexxg_ooblayout_ecc,
- .rfree = gd5fxgqxxexxg_ooblayout_free,
+ .free = gd5fxgqxxexxg_ooblayout_free,
};
static const struct spinand_info gigadevice_spinand_table[] = {
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
index 6d643a8000..6a1d6a1793 100644
--- a/drivers/mtd/nand/spi/macronix.c
+++ b/drivers/mtd/nand/spi/macronix.c
@@ -51,7 +51,7 @@ static int mx35lfxge4ab_ooblayout_free(struct mtd_info *mtd,
int section,
static const struct mtd_ooblayout_ops mx35lfxge4ab_ooblayout = {
.ecc = mx35lfxge4ab_ooblayout_ecc,
- .rfree = mx35lfxge4ab_ooblayout_free,
+ .free = mx35lfxge4ab_ooblayout_free,
};
static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 6bacf14aaf..3f5848aacd 100644
--
Re: [PATCH 2/2] mtd: make spinand driver usable without CONFIG_DM
On Sat, 11 Jul 2020 14:16:23 +0530
Jagan Teki wrote:
> On Mon, Jun 22, 2020 at 9:25 PM Mikhail Kshevetskiy
> wrote:
> >
> > From: Mikhail Kshevetskiy
> >
> > Here is an example of spinand driver initialization without CONFIG_DM
> > enabled:
> >
> > void board_nand_init(void)
> > {
> > static struct spinand_devicespinand;
> > static struct mtd_info mtd;
> > static struct spi_slave *slave;
> > int ret;
> >
> > memset(, 0, sizeof(spinand));
> > memset(, 0, sizeof(mtd));
> >
> > slave = spi_setup_slave(BUS, CS, MAX_HZ, MODE);
> > if (!slave) {
> > printf("SPI-NAND: Failed to set up SPI slave\n");
> > return;
> > }
> >
> > slave->mode |= (SPI_TX_BYTE | SPI_RX_SLOW);
> > slave->max_read_size = SPI_MAX_READ_SIZE;
> > slave->max_write_size = SPI_MAX_WRITE_SIZE;
> >
> > ret = spinand_probe_no_dm(, slave, );
> > if (!ret)
> > nand_register(0, );
> > }
> >
> > Using of dual and quad wire transfer modes requires:
> > * dual/quad speed capable hardware (both controller and flash)
> > * physical presence of 4 data wires (quad mode only)
> > * spi controller driver MUST supports slave->mem_ops.exec_op() operations
> > (spi_xfer() interface will suits for single speed data transfer mode
> > only)
> >
> > Signed-off-by: Mikhail Kshevetskiy
> > ---
>
> Now it's time for dm only code, better not come up with nondm anymore
> as possible, please.
>
> Jagan.
I know about it. These patches were in the queue for upstreaming from the new
year :-(
We are using 2010 and 2016 year based u-boot in our projects and due to some
reasons it's not easy to switch it to DM build. This two patches helps us with
backporting of spinand driver from upsteam u-boot. I think we are not an only
users of old u-boot in the world, so it maybe helpful for other people as well.
Just ignore these two patches if you think that NODM era is completely over.
Mikhail.
[PATCH 2/2] mtd: make spinand driver usable without CONFIG_DM
From: Mikhail Kshevetskiy
Here is an example of spinand driver initialization without CONFIG_DM
enabled:
void board_nand_init(void)
{
static struct spinand_devicespinand;
static struct mtd_info mtd;
static struct spi_slave *slave;
int ret;
memset(, 0, sizeof(spinand));
memset(, 0, sizeof(mtd));
slave = spi_setup_slave(BUS, CS, MAX_HZ, MODE);
if (!slave) {
printf("SPI-NAND: Failed to set up SPI slave\n");
return;
}
slave->mode |= (SPI_TX_BYTE | SPI_RX_SLOW);
slave->max_read_size = SPI_MAX_READ_SIZE;
slave->max_write_size = SPI_MAX_WRITE_SIZE;
ret = spinand_probe_no_dm(, slave, );
if (!ret)
nand_register(0, );
}
Using of dual and quad wire transfer modes requires:
* dual/quad speed capable hardware (both controller and flash)
* physical presence of 4 data wires (quad mode only)
* spi controller driver MUST supports slave->mem_ops.exec_op() operations
(spi_xfer() interface will suits for single speed data transfer mode
only)
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/nand/spi/Kconfig | 2 +-
drivers/mtd/nand/spi/core.c | 46
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/Kconfig b/drivers/mtd/nand/spi/Kconfig
index 0777dfdf0a..fd88e2cec9 100644
--- a/drivers/mtd/nand/spi/Kconfig
+++ b/drivers/mtd/nand/spi/Kconfig
@@ -1,6 +1,6 @@
menuconfig MTD_SPI_NAND
bool "SPI NAND device Support"
- depends on DM_MTD && DM_SPI
+ depends on (DM_MTD && DM_SPI) || (MTD && SPI)
select MTD_NAND_CORE
select SPI_MEM
help
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index e0ebd9c04b..a24e2e6677 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -170,14 +170,22 @@ int spinand_select_target(struct spinand_device *spinand,
unsigned int target)
static int spinand_init_cfg_cache(struct spinand_device *spinand)
{
struct nand_device *nand = spinand_to_nand(spinand);
+#ifdef CONFIG_DM
struct udevice *dev = spinand->slave->dev;
+#endif
unsigned int target;
int ret;
+#ifdef CONFIG_DM
spinand->cfg_cache = devm_kzalloc(dev,
sizeof(*spinand->cfg_cache) *
nand->memorg.ntargets,
GFP_KERNEL);
+#else
+ spinand->cfg_cache = kzalloc(sizeof(*spinand->cfg_cache) *
+nand->memorg.ntargets,
+GFP_KERNEL);
+#endif
if (!spinand->cfg_cache)
return -ENOMEM;
@@ -1135,6 +1144,7 @@ static void spinand_cleanup(struct spinand_device
*spinand)
kfree(spinand->scratchbuf);
}
+#ifdef CONFIG_DM
static int spinand_probe(struct udevice *dev)
{
struct spinand_device *spinand = dev_get_priv(dev);
@@ -1187,6 +1197,40 @@ err_spinand_cleanup:
return ret;
}
+#endif /* CONFIG_DM */
+
+#ifdef __UBOOT__
+int spinand_probe_no_dm(struct spinand_device *spinand,
+ struct spi_slave *slave,
+ struct mtd_info *mtd)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ int ret;
+
+ nand->mtd = mtd;
+ mtd->priv = nand;
+ mtd->name = malloc(20);
+ if (!mtd->name)
+ return -ENOMEM;
+ sprintf(mtd->name, "spi-nand%d", spi_nand_idx++);
+ spinand->slave = slave;
+
+ ret = spinand_init(spinand);
+ if (ret)
+ return ret;
+
+ ret = add_mtd_device(mtd);
+ if (ret)
+ goto err_spinand_cleanup;
+
+ return 0;
+
+err_spinand_cleanup:
+ spinand_cleanup(spinand);
+
+ return ret;
+}
+#endif /* __UBOOT__ */
#ifndef __UBOOT__
static int spinand_remove(struct udevice *slave)
@@ -1238,6 +1282,7 @@ MODULE_AUTHOR("Peter Pan");
MODULE_LICENSE("GPL v2");
#endif /* __UBOOT__ */
+#ifdef CONFIG_DM
static const struct udevice_id spinand_ids[] = {
{ .compatible = "spi-nand" },
{ /* sentinel */ },
@@ -1250,3 +1295,4 @@ U_BOOT_DRIVER(spinand) = {
.priv_auto_alloc_size = sizeof(struct spinand_device),
.probe = spinand_probe,
};
+#endif /* CONFIG_DM */
--
2.27.0
[PATCH 1/2] spi: make spi-mem driver usable without CONFIG_DM_SPI, drop NODM variant
From: Ivan Morozko
There is no reason to have a separate and highly restricted version of
spi-mem driver for NODM case, it's quite easily fix DM based driver
version and use it for all cases.
Signed-off-by: Ivan Morozko
Reviewed-by: Mikhail Kshevetskiy
---
drivers/spi/Makefile | 3 +-
drivers/spi/spi-mem-nodm.c | 107 -
drivers/spi/spi-mem.c | 37 -
include/spi.h | 1 +
4 files changed, 26 insertions(+), 122 deletions(-)
delete mode 100644 drivers/spi/spi-mem-nodm.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 54881a7412..6dff4eed83 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -8,12 +8,11 @@ ifdef CONFIG_DM_SPI
obj-y += spi-uclass.o
obj-$(CONFIG_SANDBOX) += spi-emul-uclass.o
obj-$(CONFIG_SOFT_SPI) += soft_spi.o
-obj-$(CONFIG_SPI_MEM) += spi-mem.o
obj-$(CONFIG_TI_QSPI) += ti_qspi.o
else
obj-y += spi.o
-obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o
endif
+obj-$(CONFIG_SPI_MEM) += spi-mem.o
obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c
deleted file mode 100644
index 765f05fe54..00
--- a/drivers/spi/spi-mem-nodm.c
+++ /dev/null
@@ -1,107 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include
-#include
-#include
-#include
-
-int spi_mem_exec_op(struct spi_slave *slave,
- const struct spi_mem_op *op)
-{
- unsigned int pos = 0;
- const u8 *tx_buf = NULL;
- u8 *rx_buf = NULL;
- u8 *op_buf;
- int op_len;
- u32 flag;
- int ret;
- int i;
-
- if (op->data.nbytes) {
- if (op->data.dir == SPI_MEM_DATA_IN)
- rx_buf = op->data.buf.in;
- else
- tx_buf = op->data.buf.out;
- }
-
- op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
- op_buf = calloc(1, op_len);
-
- ret = spi_claim_bus(slave);
- if (ret < 0)
- return ret;
-
- op_buf[pos++] = op->cmd.opcode;
-
- if (op->addr.nbytes) {
- for (i = 0; i < op->addr.nbytes; i++)
- op_buf[pos + i] = op->addr.val >>
- (8 * (op->addr.nbytes - i - 1));
-
- pos += op->addr.nbytes;
- }
-
- if (op->dummy.nbytes)
- memset(op_buf + pos, 0xff, op->dummy.nbytes);
-
- /* 1st transfer: opcode + address + dummy cycles */
- flag = SPI_XFER_BEGIN;
- /* Make sure to set END bit if no tx or rx data messages follow */
- if (!tx_buf && !rx_buf)
- flag |= SPI_XFER_END;
-
- ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag);
- if (ret)
- return ret;
-
- /* 2nd transfer: rx or tx data path */
- if (tx_buf || rx_buf) {
- ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf,
- rx_buf, SPI_XFER_END);
- if (ret)
- return ret;
- }
-
- spi_release_bus(slave);
-
- for (i = 0; i < pos; i++)
- debug("%02x ", op_buf[i]);
- debug("| [%dB %s] ",
- tx_buf || rx_buf ? op->data.nbytes : 0,
- tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-");
- for (i = 0; i < op->data.nbytes; i++)
- debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]);
- debug("[ret %d]\n", ret);
-
- free(op_buf);
-
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-int spi_mem_adjust_op_size(struct spi_slave *slave,
- struct spi_mem_op *op)
-{
- unsigned int len;
-
- len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes;
- if (slave->max_write_size && len > slave->max_write_size)
- return -EINVAL;
-
- if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size)
- op->data.nbytes = min(op->data.nbytes,
- slave->max_read_size);
- else if (slave->max_write_size)
- op->data.nbytes = min(op->data.nbytes,
- slave->max_write_size - len);
-
- if (!op->data.nbytes)
- return -EINVAL;
-
- return 0;
-}
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index d344701aeb..e4544edaad 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -105,6 +105,19 @@ void spi_controller_dma_unmap_mem_op_data(struct
spi_controller *ctlr,
EXPORT_SYMBOL_GPL(spi_controller_dma_unmap_mem_op_data);
#endif /* __UBOOT__ */
+static inline
+s
[PATCH 2/4] mtd: spinand: Explicitly use MTD_OPS_RAW to write the bad block marker to OOB
From: Frieder Schrempf
When writing the bad block marker to the OOB area the access mode
should be set to MTD_OPS_RAW as it is done for reading the marker.
Currently this only works because req.mode is initialized to
MTD_OPS_PLACE_OOB (0) and spinand_write_to_cache_op() checks for
req.mode != MTD_OPS_AUTO_OOB.
Fix this by explicitly setting req.mode to MTD_OPS_RAW.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Signed-off-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200218100432.32433-3-frieder.schre...@kontron.de
---
drivers/mtd/nand/spi/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 410ea2382d..c74a7b5ef3 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -708,6 +708,7 @@ static int spinand_markbad(struct nand_device *nand, const
struct nand_pos *pos)
.ooboffs = 0,
.ooblen = sizeof(marker),
.oobbuf.out = marker,
+ .mode = MTD_OPS_RAW,
};
int ret;
--
2.27.0
[PATCH 3/4] mtd: spinand: Do not erase the block before writing a bad block marker
From: Frieder Schrempf
Currently when marking a block, we use spinand_erase_op() to erase
the block before writing the marker to the OOB area. Doing so without
waiting for the operation to finish can lead to the marking failing
silently and no bad block marker being written to the flash.
In fact we don't need to do an erase at all before writing the BBM.
The ECC is disabled for raw accesses to the OOB data and we don't
need to work around any issues with chips reporting ECC errors as it
is known to be the case for raw NAND.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: sta...@vger.kernel.org
Signed-off-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200218100432.32433-4-frieder.schre...@kontron.de
---
drivers/mtd/nand/spi/core.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index c74a7b5ef3..e0ebd9c04b 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -712,19 +712,10 @@ static int spinand_markbad(struct nand_device *nand,
const struct nand_pos *pos)
};
int ret;
- /* Erase block before marking it bad. */
ret = spinand_select_target(spinand, pos->target);
if (ret)
return ret;
- ret = spinand_write_enable_op(spinand);
- if (ret)
- return ret;
-
- ret = spinand_erase_op(spinand, pos);
- if (ret)
- return ret;
-
return spinand_write_page(spinand, );
}
--
2.27.0
[PATCH 1/4] mtd: spinand: Stop using spinand->oobbuf for buffering bad block markers
From: Frieder Schrempf
For reading and writing the bad block markers, spinand->oobbuf is
currently used as a buffer for the marker bytes. During the
underlying read and write operations to actually get/set the content
of the OOB area, the content of spinand->oobbuf is reused and changed
by accessing it through spinand->oobbuf and/or spinand->databuf.
This is a flaw in the original design of the SPI NAND core and at the
latest from 13c15e07eedf ("mtd: spinand: Handle the case where
PROGRAM LOAD does not reset the cache") on, it results in not having
the bad block marker written at all, as the spinand->oobbuf is
cleared to 0xff after setting the marker bytes to zero.
To fix it, we now just store the two bytes for the marker on the
stack and let the read/write operations copy it from/to the page
buffer later.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: sta...@vger.kernel.org
Signed-off-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
Signed-off-by: Miquel Raynal
Link:
https://lore.kernel.org/linux-mtd/20200218100432.32433-2-frieder.schre...@kontron.de
---
drivers/mtd/nand/spi/core.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 93371fdde0..410ea2382d 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -655,16 +655,16 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t
to,
static bool spinand_isbad(struct nand_device *nand, const struct nand_pos *pos)
{
struct spinand_device *spinand = nand_to_spinand(nand);
+ u8 marker[2] = { };
struct nand_page_io_req req = {
.pos = *pos,
- .ooblen = 2,
+ .ooblen = sizeof(marker),
.ooboffs = 0,
- .oobbuf.in = spinand->oobbuf,
+ .oobbuf.in = marker,
.mode = MTD_OPS_RAW,
};
int ret;
- memset(spinand->oobbuf, 0, 2);
ret = spinand_select_target(spinand, pos->target);
if (ret)
return ret;
@@ -673,7 +673,7 @@ static bool spinand_isbad(struct nand_device *nand, const
struct nand_pos *pos)
if (ret)
return ret;
- if (spinand->oobbuf[0] != 0xff || spinand->oobbuf[1] != 0xff)
+ if (marker[0] != 0xff || marker[1] != 0xff)
return true;
return false;
@@ -702,11 +702,12 @@ static int spinand_mtd_block_isbad(struct mtd_info *mtd,
loff_t offs)
static int spinand_markbad(struct nand_device *nand, const struct nand_pos
*pos)
{
struct spinand_device *spinand = nand_to_spinand(nand);
+ u8 marker[2] = { };
struct nand_page_io_req req = {
.pos = *pos,
.ooboffs = 0,
- .ooblen = 2,
- .oobbuf.out = spinand->oobbuf,
+ .ooblen = sizeof(marker),
+ .oobbuf.out = marker,
};
int ret;
@@ -723,7 +724,6 @@ static int spinand_markbad(struct nand_device *nand, const
struct nand_pos *pos)
if (ret)
return ret;
- memset(spinand->oobbuf, 0, 2);
return spinand_write_page(spinand, );
}
--
2.27.0
[PATCH 4/4] mtd: spinand: enable erasing of bad mtd blocks
U-Boot is able to erase bad mtd blocks on raw nand devices, but this
is not true for spinand flashes. Lets enable this feature for spinand
flashes as well. This is extemelly useful for flash testing.
Signed-off-by: Mikhail Kshevetskiy
---
drivers/mtd/nand/core.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 6fbd24ba74..a39b4c4b30 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -130,10 +130,18 @@ EXPORT_SYMBOL_GPL(nanddev_isreserved);
*/
int nanddev_erase(struct nand_device *nand, const struct nand_pos *pos)
{
+ unsigned int entry;
+
if (nanddev_isbad(nand, pos) || nanddev_isreserved(nand, pos)) {
pr_warn("attempt to erase a bad/reserved block @%llx\n",
nanddev_pos_to_offs(nand, pos));
- return -EIO;
+ if (nanddev_isreserved(nand, pos))
+ return -EIO;
+
+ /* remove bad block from BBT */
+ entry = nanddev_bbt_pos_to_entry(nand, pos);
+ nanddev_bbt_set_block_status(nand, entry,
+NAND_BBT_BLOCK_STATUS_UNKNOWN);
}
return nand->ops->erase(nand, pos);
--
2.27.0
Re: [U-Boot] [PATCH V3 2/3] arm/davinci: spl - boot device selection
On Wed, 11 Jul 2012 00:09:06 +0530
Sughosh Ganu urwithsugh...@gmail.com wrote:
hi Mikhail,
On Mon Jul 09, 2012 at 10:53:39PM +0400, Mikhail Kshevetskiy wrote:
This patch allow us to have a universal spl that detects a boot
device and select a corresponding boot algorithm for main u-boot part
(SOC_DA8XX only)
I have not tested this patch, will do so sometime this week. I had a
couple of questions though.
snip
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c index 74632e5..50b4bbc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
snip
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts(Nand boot...\n);
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
- mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
- CONFIG_SYS_MALLOC_LEN);
+ u32 boot_device;
+ void (*uboot)(void) __noreturn;
+
+ mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+ CONFIG_SYS_SPL_MALLOC_SIZE);
We do not need any heap for the spl on the hawkboard, so can you
please explain why do we need the heap allocation for all spl
images. Can't this be made configurable.
this is needed at least for:
* MMC support
* SPI support
* gunzip support (see next patch)
it can be configurable, but is it reasonable?
gd = gdata;
gd-bd = bdata;
gd-flags |= GD_FLG_RELOC;
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
gd-baudrate = CONFIG_BAUDRATE;
- serial_init(); /* serial communications setup */
+ serial_init();
gd-have_console = 1;
+#endif
This call to serial_init is not needed on the hawkboard -- we
initialise the console needed for spl through NS16550_init for all
da8xx based spl's in arch_cpu_init, which suffices for spl's debug
message requirement. I know this is being used for spi based spl
images, but now that this is being made common, just wanted to
know why we need this. Also, do these changes have any impact on the
size of the spl images.
hm, i'll look on it more carefully. I've just look on spi support in spl.
What about ymodem support? If I am not mistake it require a normal console.
-sughosh
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Re: [U-Boot] [PATCH V2 7/8] arm/davinci: spl - boot device selection
On Mon, 9 Jul 2012 11:39:14 +0530
Prabhakar Lad prabhakar.cse...@gmail.com wrote:
Hi Mikhail,
On Mon, Jul 9, 2012 at 9:01 AM, Mikhail Kshevetskiy
mikhail.kshevets...@gmail.com wrote:
This patch allow us to have a universal spl that detects a boot
device and select a corresponding boot algorithm for main u-boot part
(SOC_DA8XX only)
This patch create copy copy of drivers/mtd/nand/nand_spl_load.c and
drivers/mtd/spi/spi_spl_load.c for the following reasons:
* avoid jump to main u-boot code just after its loading (required
for the next patch: spl - add compressed u-boot image support)
* makes a structure similar to omap3 sources
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v2:
* fix checkpatch warnings
* defines for constants
* use readl() to read a BOOTCFG_REG
* improve patch description
---
arch/arm/cpu/arm926ejs/davinci/Makefile |5 ++
arch/arm/cpu/arm926ejs/davinci/spl.c | 91
+++--- arch/arm/cpu/arm926ejs/davinci/spl_mmc.c |
39 ++ arch/arm/cpu/arm926ejs/davinci/spl_nand.c| 11 +++
arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c | 25 ++
arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c | 42 ++
arch/arm/include/asm/arch-davinci/davinci_boot.h | 50
include/configs/cam_enc_4xx.h| 12 +--
include/configs/da850evm.h | 19 +++--
include/configs/hawkboard.h | 11 +--
10 files changed, 275 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_nand.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c
create mode 100644 arch/arm/include/asm/arch-davinci/davinci_boot.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile
b/arch/arm/cpu/arm926ejs/davinci/Makefile index da7efac..12bd37a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -40,6 +40,11 @@ ifdef CONFIG_SPL_BUILD
COBJS-y+= spl.o
COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
+
+COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += spl_spi_flash.o
+COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+COBJS-$(CONFIG_SPL_MMC_SUPPORT)+= spl_mmc.o
endif
SOBJS = reset.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c index 74632e5..50b4bbc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -25,9 +25,11 @@
#include asm/utils.h
#include nand.h
#include asm/arch/dm365_lowlevel.h
+#include asm/arch/davinci_boot.h
#include ns16550.h
#include malloc.h
#include spi_flash.h
+#include linux/compiler.h
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -72,25 +74,92 @@ void board_init_f(ulong dummy)
relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
}
+u32 davinci_boot_device(void){
+#ifdef CONFIG_SOC_DA8XX
+ u32 bootmode = readl(BOOTCFG_REG) BOOTCFG_REG_DEVICE_MASK;
+ switch (bootmode) {
+ case BOOTCFG_DEVICE_NAND8:
+ case BOOTCFG_DEVICE_NAND16:
+ return BOOT_DEVICE_TYPE_NAND;
+ case BOOTCFG_DEVICE_SPI0_FLASH:
+ case BOOTCFG_DEVICE_SPI1_FLASH:
+ return BOOT_DEVICE_TYPE_SPI_FLASH;
+ case BOOTCFG_DEVICE_UART0:
+ case BOOTCFG_DEVICE_UART1:
+ case BOOTCFG_DEVICE_UART2:
+ return BOOT_DEVICE_TYPE_UART;
+ case BOOTCFG_DEVICE_MMC_OR_SD0:
+ return BOOT_DEVICE_TYPE_MMC;
+ default:
+ return BOOT_DEVICE_TYPE_NONE;
+ }
+#else
+#ifdef
+#endif CONFIG_SPL_NAND_SUPPORT
+ return BOOT_DEVICE_TYPE_NAND;
+#endif
+#ifdef BOOT_DEVICE_SPI_FLASH
+ return BOOT_DEVICE_TYPE_SPI_FLASH;
+#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+ return BOOT_DEVICE_TYPE_UART;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_TYPE_MMC;
+#endif
+}
+
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts(Nand boot...\n);
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
- mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
- CONFIG_SYS_MALLOC_LEN);
+ u32 boot_device;
+ void (*uboot)(void) __noreturn;
+
+ mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+ CONFIG_SYS_SPL_MALLOC_SIZE);
gd = gdata;
gd-bd = bdata;
gd-flags |= GD_FLG_RELOC;
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
[U-Boot] [PATCH V3 1/3] arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
Acked-by: Christian Riesch christian.rie...@omicron.at
Tested-by: Christian Riesch christian.rie...@omicron.at
---
Change for v3:
* split DDR and UART bugfixes to separate patch series (series 1/3)
Change for v2:
* fix checkpatch warnings
---
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 26 +--
arch/arm/include/asm/arch-davinci/hardware.h|1 +
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index df7d6a2..ff2e2e3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -190,13 +190,21 @@ int da850_ddr_setup(void)
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_LOCK);
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_POWERDWN);
-
- setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
}
-
+ setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, dv_ddr2_regs_ctrl-ddrphycr);
- clrbits_le32(davinci_syscfg1_regs-ddr_slew,
- (1 DDR_SLEW_CMOSEN_BIT));
+
+ if (CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT)) {
+ /* DDR2 */
+ clrbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ } else {
+ /* MOBILE DDR */
+ setbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ }
/*
* SDRAM Configuration Register (SDCR):
@@ -216,7 +224,11 @@ int da850_ddr_setup(void)
writel(tmp, dv_ddr2_regs_ctrl-sdbcr);
/* write memory configuration and timing */
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2, dv_ddr2_regs_ctrl-sdbcr2);
+ if (!(CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT))) {
+ /* MOBILE DDR only*/
+ writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+ dv_ddr2_regs_ctrl-sdbcr2);
+ }
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, dv_ddr2_regs_ctrl-sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, dv_ddr2_regs_ctrl-sdtimr2);
@@ -240,7 +252,7 @@ int da850_ddr_setup(void)
/* disable self refresh */
clrbits_le32(dv_ddr2_regs_ctrl-sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+ DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, dv_ddr2_regs_ctrl-pbbpr);
return 0;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..56e5743 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -505,6 +505,7 @@ struct davinci_syscfg1_regs {
((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
#define DDR_SLEW_CMOSEN_BIT4
+#define DDR_SLEW_DDR_PDENA_BIT 5
#define VTP_POWERDWN (1 6)
#define VTP_LOCK (1 7)
--
1.7.10.4
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[U-Boot] [PATCH V3 2/3] arm/davinci/da850: add uart0 pinmux
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v3:
* split DDR and UART bugfixes to separate patch series (series 1/3)
Change for v2:
* fix checkpatch warnings
---
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c |5 +
arch/arm/include/asm/arch-davinci/hardware.h|1 +
arch/arm/include/asm/arch-davinci/pinmux_defs.h |1 +
3 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..dbae5fa 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = {
};
/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+ { pinmux(3), 2, 4 }, /* UART0_RXD */
+ { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
const struct pinmux_config uart1_pins_txrx[] = {
{ pinmux(4), 2, 6 }, /* UART1_RXD */
{ pinmux(4), 2, 7 }, /* UART1_TXD */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 56e5743..76aca24 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -447,6 +447,7 @@ struct davinci_pllc_regs {
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..eddb3f7 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -28,6 +28,7 @@ extern const struct pinmux_config spi1_pins_base[3];
extern const struct pinmux_config spi1_pins_scs0[1];
/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
extern const struct pinmux_config uart1_pins_txrx[2];
extern const struct pinmux_config uart2_pins_txrx[2];
extern const struct pinmux_config uart2_pins_rtscts[2];
--
1.7.10.4
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[U-Boot] [PATCH V3 3/3] serial/ns16550: ns16550 has a different register layout on SOC_DA8XX
also fix NS16550_init() as we need 16x divider
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
Acked-by: Christian Riesch christian.rie...@omicron.at
Tested-by: Christian Riesch christian.rie...@omicron.at
---
Change for v3:
* split DDR and UART bugfixes to separate patch series (series 1/3)
Change for v2:
* fix checkpatch warnings
---
drivers/serial/ns16550.c |2 +-
include/ns16550.h|9 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0c23955..facadd2 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -52,7 +52,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor 8) 0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX)
+ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/include/ns16550.h b/include/ns16550.h
index e9d2eda..51cb5b4 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -46,6 +46,14 @@ struct NS16550 {
UART_REG(lsr); /* 5 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+ UART_REG(reg8); /* 8 */
+ UART_REG(reg9); /* 9 */
+ UART_REG(revid1); /* A */
+ UART_REG(revid2); /* B */
+ UART_REG(pwr_mgmt); /* C */
+ UART_REG(mdr1); /* D */
+#else
UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */
@@ -58,6 +66,7 @@ struct NS16550 {
UART_REG(ssr); /* 11*/
UART_REG(reg12);/* 12*/
UART_REG(osc_12m_sel); /* 13*/
+#endif
};
#define thr rbr
--
1.7.10.4
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[U-Boot] [PATCH V3 1/2] mtd/spi/spi_flash: support CMD_READ_ID=0x90 case
current code does not support spi flashes that have 0x90 read_id command,
so fix this
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v3:
* split SPI flash fixes to separate patch series (series 2/3)
Change for v2:
* fix checkpatch warnings
---
drivers/mtd/spi/spi_flash.c | 66 +++---
drivers/mtd/spi/spi_flash_internal.h |1 +
2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index f689cc4..530b7b3 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -306,13 +306,44 @@ static const struct {
};
#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
+struct spi_flash *spi_analize_flash_probe(struct spi_slave *spi,
+ u8 *idcode, size_t idcode_len, u8 *id)
+{
+ struct spi_flash *flash = NULL;
+ int i, shift;
+ u8 *idp;
+
+#ifdef DEBUG
+ printf(SF: Got idcodes\n);
+ print_buffer(0, idcode, 1, idcode_len, 0);
+#endif
+
+ /* count the number of continuation bytes */
+ for (shift = 0, idp = idcode;
+shift idcode_len *idp == 0x7f;
+++shift, ++idp)
+ continue;
+
+ *id = *idp;
+ /* search the table for matches in shift and id */
+ for (i = 0; i ARRAY_SIZE(flashes); ++i)
+ if (flashes[i].shift == shift flashes[i].idcode == *idp) {
+ /* we have a match, call probe */
+ flash = flashes[i].probe(spi, idp);
+ if (flash)
+ break;
+ }
+
+ return flash;
+}
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
struct spi_flash *flash = NULL;
- int ret, i, shift;
- u8 idcode[IDCODE_LEN], *idp;
+ u8 cmd[4], idcode[IDCODE_LEN], id;
+ int ret;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
@@ -331,28 +362,23 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
if (ret)
goto err_read_id;
-#ifdef DEBUG
- printf(SF: Got idcodes\n);
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
+ flash = spi_analize_flash_probe(spi, idcode, sizeof(idcode), id);
+ if (id == 0xff) {
+ /* try CMD_READ_ID_NEW command */
+ cmd[0] = CMD_READ_ID_NEW;
+ spi_flash_addr(0x00, cmd);
- /* count the number of continuation bytes */
- for (shift = 0, idp = idcode;
-shift IDCODE_CONT_LEN *idp == 0x7f;
-++shift, ++idp)
- continue;
+ ret = spi_flash_cmd_read(spi, cmd, sizeof(cmd),
+ idcode, sizeof(idcode));
+ if (ret)
+ goto err_read_id;
- /* search the table for matches in shift and id */
- for (i = 0; i ARRAY_SIZE(flashes); ++i)
- if (flashes[i].shift == shift flashes[i].idcode == *idp) {
- /* we have a match, call probe */
- flash = flashes[i].probe(spi, idp);
- if (flash)
- break;
- }
+ flash = spi_analize_flash_probe(spi,
+ idcode, sizeof(idcode), id);
+ }
if (!flash) {
- printf(SF: Unsupported manufacturer %02x\n, *idp);
+ printf(SF: Unsupported manufacturer %02x\n, id);
goto err_manufacturer_probe;
}
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 91e036a..b8bd5d5 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -14,6 +14,7 @@
/* Common commands */
#define CMD_READ_ID0x9f
+#define CMD_READ_ID_NEW0x90
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_ARRAY_FAST0x0b
--
1.7.10.4
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[U-Boot] [PATCH V3 2/2] mtd/spi: add sst25l driver
Current SST driver does not support well this types of flash, so
introduce a new one.
This code is a combination of sst.c driver from u-boot and sst25l.c
driver from linux-3.3 release. I try to make a code as close to linux
driver as it was possible.
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v3:
* split SPI flash fixes to separate patch series (series 2/3)
Change for v2:
* fix checkpatch warnings
* improve patch description
---
drivers/mtd/spi/Makefile |3 +-
drivers/mtd/spi/spi_flash.c |3 +
drivers/mtd/spi/spi_flash_internal.h |1 +
drivers/mtd/spi/sst25l.c | 372 ++
4 files changed, 378 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/spi/sst25l.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..9285bf7 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -34,7 +34,8 @@ COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
-COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST25L) += sst25l.o
COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o
COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 530b7b3..d2da542 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -285,6 +285,9 @@ static const struct {
#ifdef CONFIG_SPI_FLASH_SST
{ 0, 0xbf, spi_flash_probe_sst, },
#endif
+#ifdef CONFIG_SPI_FLASH_SST25L
+ { 0, 0xbf, spi_flash_probe_sst25l, },
+#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
{ 0, 0x20, spi_flash_probe_stmicro, },
#endif
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index b8bd5d5..89d9036 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -98,6 +98,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave
*spi, u8 *idcode);
struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_sst25l(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
diff --git a/drivers/mtd/spi/sst25l.c b/drivers/mtd/spi/sst25l.c
new file mode 100644
index 000..9d7be0d
--- /dev/null
+++ b/drivers/mtd/spi/sst25l.c
@@ -0,0 +1,372 @@
+/*
+ * Driver for SST25L SPI Flash chips
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan mcmul...@netapp.com
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include common.h
+#include malloc.h
+#include spi_flash.h
+#include watchdog.h
+
+#include spi_flash_internal.h
+
+#define SST25L_CMD_WRSR0x01/* Write status register */
+#define SST25L_CMD_WRDI0x04/* Write disable */
+#define SST25L_CMD_RDSR0x05/* Read status register */
+#define SST25L_CMD_WREN0x06/* Write enable */
+#define SST25L_CMD_READ0x03/* High speed read */
+
+#define SST25L_CMD_EWSR0x50/* Enable write status register
*/
+#define SST25L_CMD_SECTOR_ERASE0x20/* Erase sector */
+#define SST25L_CMD_READ_ID 0x90/* Read device ID */
+#define SST25L_CMD_AAI_PROGRAM 0xaf/* Auto address increment */
+
+#define SST25L_STATUS_BUSY (1 0)/* Chip is busy */
+#define SST25L_STATUS_WREN (1 1)/* Write enabled */
+#define SST25L_STATUS_BP0 (1 2)/* Block protection 0 */
+#define SST25L_STATUS_BP1 (1 3)/* Block protection 1 */
+
+struct flash_info {
+ const char *name;
+ u16 device_id;
+ u32 page_size;
+ u32 nr_pages;
+ u32 erase_size;
+};
+
+struct sst25l_spi_flash {
+ struct spi_flashflash;
+ const struct flash_info *flash_info;
+};
+
+#define to_sst25l_spi_flash(x) container_of(x, struct sst25l_spi_flash, flash)
+
+static struct flash_info sst25l_flash_info[] = {
+ {sst25vf010a, 0xbf49, 256, 512, 4096},
+ {sst25lf020a, 0xbf43, 256, 1024, 4096},
+ {sst25lf040a, 0xbf44, 256, 2048, 4096
[U-Boot] [PATCH V3 1/3] MMC: u-boot-spl may be compiled without partition support
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- Change for v3: * split MMC+SPL+no partition table support bugfix to separate patch series (series 3/3) Change for v2: * fix checkpatch warnings --- drivers/mmc/mmc.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..69df64a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1253,7 +1253,9 @@ int mmc_startup(struct mmc *mmc) (mmc-cid[1] 8) 0xff, mmc-cid[1] 0xff); sprintf(mmc-block_dev.revision, %d.%d, mmc-cid[2] 28, (mmc-cid[2] 24) 0xf); +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) init_part(mmc-block_dev); +#endif return 0; } -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V3 2/3] arm/davinci: spl - boot device selection
This patch allow us to have a universal spl that detects a boot
device and select a corresponding boot algorithm for main u-boot part
(SOC_DA8XX only)
This patch create copy copy of drivers/mtd/nand/nand_spl_load.c and
drivers/mtd/spi/spi_spl_load.c for the following reasons:
* avoid jump to main u-boot code just after its loading (required
for the next patch: spl - add compressed u-boot image support)
* makes a structure similar to omap3 sources
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v3:
* split MMC+SPL+no partition table support bugfix to separate patch
series (series 3/3)
Change for v2:
* fix checkpatch warnings
* defines for constants
* use readl() to read a BOOTCFG_REG
* improve patch description
---
arch/arm/cpu/arm926ejs/davinci/Makefile |5 ++
arch/arm/cpu/arm926ejs/davinci/spl.c | 91 +++---
arch/arm/cpu/arm926ejs/davinci/spl_mmc.c | 39 ++
arch/arm/cpu/arm926ejs/davinci/spl_nand.c| 11 +++
arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c | 25 ++
arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c | 42 ++
arch/arm/include/asm/arch-davinci/davinci_boot.h | 50
include/configs/cam_enc_4xx.h| 12 +--
include/configs/da850evm.h | 19 +++--
include/configs/hawkboard.h | 11 +--
10 files changed, 275 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_nand.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c
create mode 100644 arch/arm/include/asm/arch-davinci/davinci_boot.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile
b/arch/arm/cpu/arm926ejs/davinci/Makefile
index da7efac..12bd37a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -40,6 +40,11 @@ ifdef CONFIG_SPL_BUILD
COBJS-y+= spl.o
COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
+
+COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += spl_spi_flash.o
+COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+COBJS-$(CONFIG_SPL_MMC_SUPPORT)+= spl_mmc.o
endif
SOBJS = reset.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 74632e5..50b4bbc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -25,9 +25,11 @@
#include asm/utils.h
#include nand.h
#include asm/arch/dm365_lowlevel.h
+#include asm/arch/davinci_boot.h
#include ns16550.h
#include malloc.h
#include spi_flash.h
+#include linux/compiler.h
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -72,25 +74,92 @@ void board_init_f(ulong dummy)
relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
}
+u32 davinci_boot_device(void){
+#ifdef CONFIG_SOC_DA8XX
+ u32 bootmode = readl(BOOTCFG_REG) BOOTCFG_REG_DEVICE_MASK;
+ switch (bootmode) {
+ case BOOTCFG_DEVICE_NAND8:
+ case BOOTCFG_DEVICE_NAND16:
+ return BOOT_DEVICE_TYPE_NAND;
+ case BOOTCFG_DEVICE_SPI0_FLASH:
+ case BOOTCFG_DEVICE_SPI1_FLASH:
+ return BOOT_DEVICE_TYPE_SPI_FLASH;
+ case BOOTCFG_DEVICE_UART0:
+ case BOOTCFG_DEVICE_UART1:
+ case BOOTCFG_DEVICE_UART2:
+ return BOOT_DEVICE_TYPE_UART;
+ case BOOTCFG_DEVICE_MMC_OR_SD0:
+ return BOOT_DEVICE_TYPE_MMC;
+ default:
+ return BOOT_DEVICE_TYPE_NONE;
+ }
+#else
+#ifdef
+#endif CONFIG_SPL_NAND_SUPPORT
+ return BOOT_DEVICE_TYPE_NAND;
+#endif
+#ifdef BOOT_DEVICE_SPI_FLASH
+ return BOOT_DEVICE_TYPE_SPI_FLASH;
+#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+ return BOOT_DEVICE_TYPE_UART;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_TYPE_MMC;
+#endif
+}
+
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts(Nand boot...\n);
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
- mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
- CONFIG_SYS_MALLOC_LEN);
+ u32 boot_device;
+ void (*uboot)(void) __noreturn;
+
+ mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+ CONFIG_SYS_SPL_MALLOC_SIZE);
gd = gdata;
gd-bd = bdata;
gd-flags |= GD_FLG_RELOC;
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
gd-baudrate = CONFIG_BAUDRATE;
- serial_init(); /* serial communications setup */
+ serial_init();
gd-have_console = 1;
+#endif
- puts(SPI boot...\n);
- spi_boot();
+ boot_device = davinci_boot_device();
+ debug(boot device - %d\n, boot_device);
+ switch
[U-Boot] [PATCH V3 3/3] arm/davinci: spl - add compressed u-boot image support
Motivation:
* we have a board with 128 Kb spi flash, so normal u-boot.ais does not
fit on it.
This patch add support of compressed 2-nd u-boot stage. To create a compressed
ais image its required:
* define CONFIG_SPL_GUNZIP_SUPPORT --- enable compressed ais image supports
* define CONFIG_SPL_GUNZIP_MAX_SIZE --- define a maximum size of compressed
u-boot part
* define CONFIG_SPL_GUNZIP_LOAD_ADDR --- memory address to load compressed
u-boot part (CONFIG_SPL_GUNZIP_LOAD_ADDR region should not overlap with
CONFIG_SYS_TEXT_BASE region)
* use: make u-boot-gzip.ais to get a compressed ais image
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v3:
* split MMC+SPL+no partition table support bugfix to separate patch
series (series 3/3)
Change for v2:
* fix checkpatch warnings
* fix merge conflict with upstream u-boot sources
* improve patch description
---
Makefile | 14 ++
arch/arm/cpu/arm926ejs/davinci/spl.c |7 +++
arch/arm/cpu/arm926ejs/davinci/spl_mmc.c |7 ++-
arch/arm/cpu/arm926ejs/davinci/spl_nand.c |7 ++-
arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c |7 ++-
arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c|4
lib/Makefile |1 +
spl/Makefile |1 +
8 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index 85e36ec..cf16824 100644
--- a/Makefile
+++ b/Makefile
@@ -452,6 +452,20 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
$(obj)u-boot.ais
rm $(obj)spl/u-boot-spl{,-pad}.ais
+$(obj)u-boot-gzip.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(obj)tools/mkimage -s -n /dev/null -T aisimage \
+ -e $(CONFIG_SPL_TEXT_BASE) \
+ -d $(obj)spl/u-boot-spl.bin \
+ $(obj)spl/u-boot-spl.ais
+ $(OBJCOPY) ${OBJCFLAGS} -I binary \
+ --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
+ $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
+ cp $(obj)u-boot.bin $(obj)spl/u-boot.bin
+ gzip $(obj)spl/u-boot.bin
+ cat $(obj)spl/u-boot-spl-pad.ais $(obj)spl/u-boot.bin.gz \
+ $(obj)u-boot-gzip.ais
+ rm $(obj)spl/u-boot-spl{,-pad}.ais $(obj)spl/u-boot.bin.gz
+
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 50b4bbc..041df5b 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -111,6 +111,7 @@ u32 davinci_boot_device(void){
void board_init_r(gd_t *id, ulong dummy)
{
+ int size;
u32 boot_device;
void (*uboot)(void) __noreturn;
@@ -159,6 +160,12 @@ void board_init_r(gd_t *id, ulong dummy)
break;
}
+#ifdef CONFIG_SPL_GUNZIP_SUPPORT
+ size = CONFIG_SPL_GUNZIP_MAX_SIZE;
+ gunzip((void *)CONFIG_SYS_TEXT_BASE, 512 * 1024,
+ (void *)CONFIG_SPL_GUNZIP_LOAD_ADDR, size);
+#endif
+
puts(Jump to U-Boot image...\n);
uboot = (void *) CONFIG_SYS_TEXT_BASE;
(*uboot)();
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
b/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
index 1a551e9..fa67f1a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
@@ -28,7 +28,12 @@ void spl_mmc_load_image(void)
ret = mmc-block_dev.block_read(0,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- (void *) CONFIG_SYS_TEXT_BASE);
+#ifndef CONFIG_SPL_GUNZIP_SUPPORT
+ (void *) CONFIG_SYS_TEXT_BASE
+#else
+ (void *) CONFIG_SPL_GUNZIP_LOAD_ADDR
+#endif
+ );
if (ret 0) {
printf(spl: mmc blk read err - %d\n, ret);
hang();
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
index bad1e8f..4bf3e6a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
@@ -6,6 +6,11 @@ void spl_nand_load_image(void)
nand_init();
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *) CONFIG_SYS_TEXT_BASE);
+#ifndef CONFIG_SPL_GUNZIP_SUPPORT
+ (void *) CONFIG_SYS_TEXT_BASE
+#else
+ (void *) CONFIG_SPL_GUNZIP_LOAD_ADDR
+#endif
Re: [U-Boot] [PATCH V3 2/3] arm/davinci: spl - boot device selection
On Mon, 9 Jul 2012 12:41:06 -0700 Tom Rini tr...@ti.com wrote: On 07/09/2012 11:53 AM, Mikhail Kshevetskiy wrote: This patch allow us to have a universal spl that detects a boot device and select a corresponding boot algorithm for main u-boot part (SOC_DA8XX only) This patch create copy copy of drivers/mtd/nand/nand_spl_load.c and drivers/mtd/spi/spi_spl_load.c for the following reasons: * avoid jump to main u-boot code just after its loading (required for the next patch: spl - add compressed u-boot image support) * makes a structure similar to omap3 sources Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com I guess I wasn't clear enough when I asked the series to be split. I want to see this portion turned into: a) Move omap-common spl bits to arch/arm/lib/ b) davinci converted (and as needed, omap3/4/am33xx converted) to be able to use the same code. We shouldn't introduce a new spl_mmc.c for example, we should modify the davinci structure to be able to re-use the same spl_mmc.c code to load/verify and let the next step, as needed happen. I want to see omap be able to re-use SPI (since am33xx can do it too, and I've kludged the davinci stuff before) and potentially be able to re-use for example the gunzip support. This I think is the easy set of steps to being able to reuse this fairly common SPL logic outside of not just TI parts but anyone else that wants it. Ok, I'll take this task. Unfortunately I have no too much free time for this job (summer, parents visit, new job and so on), so it may take a month or so. What about other patches? Mikhail -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V3 2/3] arm/davinci: spl - boot device selection
On Mon, 9 Jul 2012 13:08:07 -0700 Tom Rini tr...@ti.com wrote: On 07/09/2012 12:57 PM, Mikhail Kshevetskiy wrote: On Mon, 9 Jul 2012 12:41:06 -0700 Tom Rini tr...@ti.com wrote: On 07/09/2012 11:53 AM, Mikhail Kshevetskiy wrote: This patch allow us to have a universal spl that detects a boot device and select a corresponding boot algorithm for main u-boot part (SOC_DA8XX only) This patch create copy copy of drivers/mtd/nand/nand_spl_load.c and drivers/mtd/spi/spi_spl_load.c for the following reasons: * avoid jump to main u-boot code just after its loading (required for the next patch: spl - add compressed u-boot image support) * makes a structure similar to omap3 sources Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com I guess I wasn't clear enough when I asked the series to be split. I want to see this portion turned into: a) Move omap-common spl bits to arch/arm/lib/ b) davinci converted (and as needed, omap3/4/am33xx converted) to be able to use the same code. We shouldn't introduce a new spl_mmc.c for example, we should modify the davinci structure to be able to re-use the same spl_mmc.c code to load/verify and let the next step, as needed happen. I want to see omap be able to re-use SPI (since am33xx can do it too, and I've kludged the davinci stuff before) and potentially be able to re-use for example the gunzip support. This I think is the easy set of steps to being able to reuse this fairly common SPL logic outside of not just TI parts but anyone else that wants it. Ok, I'll take this task. Unfortunately I have no too much free time for this job (summer, parents visit, new job and so on), so it may take a month or so. OK, thanks. What about other patches? The ddr/uart ones should make their way in soon and I've assigned the SPI ones to the custodian in patchwork. -- Tom Thanks! Mikhail ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 1/8] arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
Acked-by: Christian Riesch christian.rie...@omicron.at
Tested-by: Christian Riesch christian.rie...@omicron.at
---
Change for v2:
* fix checkpatch warnings
---
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 26 +--
arch/arm/include/asm/arch-davinci/hardware.h|1 +
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index df7d6a2..ff2e2e3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -190,13 +190,21 @@ int da850_ddr_setup(void)
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_LOCK);
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_POWERDWN);
-
- setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
}
-
+ setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, dv_ddr2_regs_ctrl-ddrphycr);
- clrbits_le32(davinci_syscfg1_regs-ddr_slew,
- (1 DDR_SLEW_CMOSEN_BIT));
+
+ if (CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT)) {
+ /* DDR2 */
+ clrbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ } else {
+ /* MOBILE DDR */
+ setbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ }
/*
* SDRAM Configuration Register (SDCR):
@@ -216,7 +224,11 @@ int da850_ddr_setup(void)
writel(tmp, dv_ddr2_regs_ctrl-sdbcr);
/* write memory configuration and timing */
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2, dv_ddr2_regs_ctrl-sdbcr2);
+ if (!(CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT))) {
+ /* MOBILE DDR only*/
+ writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+ dv_ddr2_regs_ctrl-sdbcr2);
+ }
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, dv_ddr2_regs_ctrl-sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, dv_ddr2_regs_ctrl-sdtimr2);
@@ -240,7 +252,7 @@ int da850_ddr_setup(void)
/* disable self refresh */
clrbits_le32(dv_ddr2_regs_ctrl-sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+ DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, dv_ddr2_regs_ctrl-pbbpr);
return 0;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..56e5743 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -505,6 +505,7 @@ struct davinci_syscfg1_regs {
((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
#define DDR_SLEW_CMOSEN_BIT4
+#define DDR_SLEW_DDR_PDENA_BIT 5
#define VTP_POWERDWN (1 6)
#define VTP_LOCK (1 7)
--
1.7.10.4
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[U-Boot] [PATCH V2 3/8] serial/ns16550: ns16550 has a different register layout on SOC_DA8XX
also fix NS16550_init() as we need 16x divider
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
Acked-by: Christian Riesch christian.rie...@omicron.at
Tested-by: Christian Riesch christian.rie...@omicron.at
---
Change for v2:
* fix checkpatch warnings
---
drivers/serial/ns16550.c |2 +-
include/ns16550.h|9 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0c23955..facadd2 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -52,7 +52,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor 8) 0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX)
+ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/include/ns16550.h b/include/ns16550.h
index e9d2eda..51cb5b4 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -46,6 +46,14 @@ struct NS16550 {
UART_REG(lsr); /* 5 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+ UART_REG(reg8); /* 8 */
+ UART_REG(reg9); /* 9 */
+ UART_REG(revid1); /* A */
+ UART_REG(revid2); /* B */
+ UART_REG(pwr_mgmt); /* C */
+ UART_REG(mdr1); /* D */
+#else
UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */
@@ -58,6 +66,7 @@ struct NS16550 {
UART_REG(ssr); /* 11*/
UART_REG(reg12);/* 12*/
UART_REG(osc_12m_sel); /* 13*/
+#endif
};
#define thr rbr
--
1.7.10.4
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[U-Boot] [PATCH V2 2/8] arm/davinci/da850: add uart0 pinmux
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v2:
* fix checkpatch warnings
---
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c |5 +
arch/arm/include/asm/arch-davinci/hardware.h|1 +
arch/arm/include/asm/arch-davinci/pinmux_defs.h |1 +
3 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..dbae5fa 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = {
};
/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+ { pinmux(3), 2, 4 }, /* UART0_RXD */
+ { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
const struct pinmux_config uart1_pins_txrx[] = {
{ pinmux(4), 2, 6 }, /* UART1_RXD */
{ pinmux(4), 2, 7 }, /* UART1_TXD */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 56e5743..76aca24 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -447,6 +447,7 @@ struct davinci_pllc_regs {
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..eddb3f7 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -28,6 +28,7 @@ extern const struct pinmux_config spi1_pins_base[3];
extern const struct pinmux_config spi1_pins_scs0[1];
/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
extern const struct pinmux_config uart1_pins_txrx[2];
extern const struct pinmux_config uart2_pins_txrx[2];
extern const struct pinmux_config uart2_pins_rtscts[2];
--
1.7.10.4
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[U-Boot] [PATCH V2 4/8] mtd/spi/spi_flash: support CMD_READ_ID=0x90 case
current code does not support spi flashes that have 0x90 read_id command,
so fix this
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v2:
* fix checkpatch warnings
---
drivers/mtd/spi/spi_flash.c | 66 +++---
drivers/mtd/spi/spi_flash_internal.h |1 +
2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index f689cc4..530b7b3 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -306,13 +306,44 @@ static const struct {
};
#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
+struct spi_flash *spi_analize_flash_probe(struct spi_slave *spi,
+ u8 *idcode, size_t idcode_len, u8 *id)
+{
+ struct spi_flash *flash = NULL;
+ int i, shift;
+ u8 *idp;
+
+#ifdef DEBUG
+ printf(SF: Got idcodes\n);
+ print_buffer(0, idcode, 1, idcode_len, 0);
+#endif
+
+ /* count the number of continuation bytes */
+ for (shift = 0, idp = idcode;
+shift idcode_len *idp == 0x7f;
+++shift, ++idp)
+ continue;
+
+ *id = *idp;
+ /* search the table for matches in shift and id */
+ for (i = 0; i ARRAY_SIZE(flashes); ++i)
+ if (flashes[i].shift == shift flashes[i].idcode == *idp) {
+ /* we have a match, call probe */
+ flash = flashes[i].probe(spi, idp);
+ if (flash)
+ break;
+ }
+
+ return flash;
+}
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
struct spi_flash *flash = NULL;
- int ret, i, shift;
- u8 idcode[IDCODE_LEN], *idp;
+ u8 cmd[4], idcode[IDCODE_LEN], id;
+ int ret;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
@@ -331,28 +362,23 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
if (ret)
goto err_read_id;
-#ifdef DEBUG
- printf(SF: Got idcodes\n);
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
+ flash = spi_analize_flash_probe(spi, idcode, sizeof(idcode), id);
+ if (id == 0xff) {
+ /* try CMD_READ_ID_NEW command */
+ cmd[0] = CMD_READ_ID_NEW;
+ spi_flash_addr(0x00, cmd);
- /* count the number of continuation bytes */
- for (shift = 0, idp = idcode;
-shift IDCODE_CONT_LEN *idp == 0x7f;
-++shift, ++idp)
- continue;
+ ret = spi_flash_cmd_read(spi, cmd, sizeof(cmd),
+ idcode, sizeof(idcode));
+ if (ret)
+ goto err_read_id;
- /* search the table for matches in shift and id */
- for (i = 0; i ARRAY_SIZE(flashes); ++i)
- if (flashes[i].shift == shift flashes[i].idcode == *idp) {
- /* we have a match, call probe */
- flash = flashes[i].probe(spi, idp);
- if (flash)
- break;
- }
+ flash = spi_analize_flash_probe(spi,
+ idcode, sizeof(idcode), id);
+ }
if (!flash) {
- printf(SF: Unsupported manufacturer %02x\n, *idp);
+ printf(SF: Unsupported manufacturer %02x\n, id);
goto err_manufacturer_probe;
}
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 91e036a..b8bd5d5 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -14,6 +14,7 @@
/* Common commands */
#define CMD_READ_ID0x9f
+#define CMD_READ_ID_NEW0x90
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_ARRAY_FAST0x0b
--
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[U-Boot] [PATCH V2 5/8] mtd/spi: add sst25l driver
Current SST driver does not support well this types of flash, so
introduce a new one.
This code is a combination of sst.c driver from u-boot and sst25l.c
driver from linux-3.3 release. I try to make a code as close to linux
driver as it was possible.
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v2:
* fix checkpatch warnings
* improve patch description
---
drivers/mtd/spi/Makefile |3 +-
drivers/mtd/spi/spi_flash.c |3 +
drivers/mtd/spi/spi_flash_internal.h |1 +
drivers/mtd/spi/sst25l.c | 372 ++
4 files changed, 378 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/spi/sst25l.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..9285bf7 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -34,7 +34,8 @@ COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
-COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST25L) += sst25l.o
COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o
COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 530b7b3..d2da542 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -285,6 +285,9 @@ static const struct {
#ifdef CONFIG_SPI_FLASH_SST
{ 0, 0xbf, spi_flash_probe_sst, },
#endif
+#ifdef CONFIG_SPI_FLASH_SST25L
+ { 0, 0xbf, spi_flash_probe_sst25l, },
+#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
{ 0, 0x20, spi_flash_probe_stmicro, },
#endif
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index b8bd5d5..89d9036 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -98,6 +98,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave
*spi, u8 *idcode);
struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_sst25l(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
diff --git a/drivers/mtd/spi/sst25l.c b/drivers/mtd/spi/sst25l.c
new file mode 100644
index 000..9d7be0d
--- /dev/null
+++ b/drivers/mtd/spi/sst25l.c
@@ -0,0 +1,372 @@
+/*
+ * Driver for SST25L SPI Flash chips
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan mcmul...@netapp.com
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include common.h
+#include malloc.h
+#include spi_flash.h
+#include watchdog.h
+
+#include spi_flash_internal.h
+
+#define SST25L_CMD_WRSR0x01/* Write status register */
+#define SST25L_CMD_WRDI0x04/* Write disable */
+#define SST25L_CMD_RDSR0x05/* Read status register */
+#define SST25L_CMD_WREN0x06/* Write enable */
+#define SST25L_CMD_READ0x03/* High speed read */
+
+#define SST25L_CMD_EWSR0x50/* Enable write status register
*/
+#define SST25L_CMD_SECTOR_ERASE0x20/* Erase sector */
+#define SST25L_CMD_READ_ID 0x90/* Read device ID */
+#define SST25L_CMD_AAI_PROGRAM 0xaf/* Auto address increment */
+
+#define SST25L_STATUS_BUSY (1 0)/* Chip is busy */
+#define SST25L_STATUS_WREN (1 1)/* Write enabled */
+#define SST25L_STATUS_BP0 (1 2)/* Block protection 0 */
+#define SST25L_STATUS_BP1 (1 3)/* Block protection 1 */
+
+struct flash_info {
+ const char *name;
+ u16 device_id;
+ u32 page_size;
+ u32 nr_pages;
+ u32 erase_size;
+};
+
+struct sst25l_spi_flash {
+ struct spi_flashflash;
+ const struct flash_info *flash_info;
+};
+
+#define to_sst25l_spi_flash(x) container_of(x, struct sst25l_spi_flash, flash)
+
+static struct flash_info sst25l_flash_info[] = {
+ {sst25vf010a, 0xbf49, 256, 512, 4096},
+ {sst25lf020a, 0xbf43, 256, 1024, 4096},
+ {sst25lf040a, 0xbf44, 256, 2048, 4096},
+};
+
+static inline int spi_write_sync(struct spi_slave *spi
[U-Boot] [PATCH V2 6/8] MMC: u-boot-spl may be compiled without partition support
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- Change for v2: * fix checkpatch warnings --- drivers/mmc/mmc.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..69df64a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1253,7 +1253,9 @@ int mmc_startup(struct mmc *mmc) (mmc-cid[1] 8) 0xff, mmc-cid[1] 0xff); sprintf(mmc-block_dev.revision, %d.%d, mmc-cid[2] 28, (mmc-cid[2] 24) 0xf); +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) init_part(mmc-block_dev); +#endif return 0; } -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 7/8] arm/davinci: spl - boot device selection
This patch allow us to have a universal spl that detects a boot
device and select a corresponding boot algorithm for main u-boot part
(SOC_DA8XX only)
This patch create copy copy of drivers/mtd/nand/nand_spl_load.c and
drivers/mtd/spi/spi_spl_load.c for the following reasons:
* avoid jump to main u-boot code just after its loading (required
for the next patch: spl - add compressed u-boot image support)
* makes a structure similar to omap3 sources
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v2:
* fix checkpatch warnings
* defines for constants
* use readl() to read a BOOTCFG_REG
* improve patch description
---
arch/arm/cpu/arm926ejs/davinci/Makefile |5 ++
arch/arm/cpu/arm926ejs/davinci/spl.c | 91 +++---
arch/arm/cpu/arm926ejs/davinci/spl_mmc.c | 39 ++
arch/arm/cpu/arm926ejs/davinci/spl_nand.c| 11 +++
arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c | 25 ++
arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c | 42 ++
arch/arm/include/asm/arch-davinci/davinci_boot.h | 50
include/configs/cam_enc_4xx.h| 12 +--
include/configs/da850evm.h | 19 +++--
include/configs/hawkboard.h | 11 +--
10 files changed, 275 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_nand.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c
create mode 100644 arch/arm/include/asm/arch-davinci/davinci_boot.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile
b/arch/arm/cpu/arm926ejs/davinci/Makefile
index da7efac..12bd37a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -40,6 +40,11 @@ ifdef CONFIG_SPL_BUILD
COBJS-y+= spl.o
COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
+
+COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += spl_spi_flash.o
+COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+COBJS-$(CONFIG_SPL_MMC_SUPPORT)+= spl_mmc.o
endif
SOBJS = reset.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 74632e5..50b4bbc 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -25,9 +25,11 @@
#include asm/utils.h
#include nand.h
#include asm/arch/dm365_lowlevel.h
+#include asm/arch/davinci_boot.h
#include ns16550.h
#include malloc.h
#include spi_flash.h
+#include linux/compiler.h
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -72,25 +74,92 @@ void board_init_f(ulong dummy)
relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
}
+u32 davinci_boot_device(void){
+#ifdef CONFIG_SOC_DA8XX
+ u32 bootmode = readl(BOOTCFG_REG) BOOTCFG_REG_DEVICE_MASK;
+ switch (bootmode) {
+ case BOOTCFG_DEVICE_NAND8:
+ case BOOTCFG_DEVICE_NAND16:
+ return BOOT_DEVICE_TYPE_NAND;
+ case BOOTCFG_DEVICE_SPI0_FLASH:
+ case BOOTCFG_DEVICE_SPI1_FLASH:
+ return BOOT_DEVICE_TYPE_SPI_FLASH;
+ case BOOTCFG_DEVICE_UART0:
+ case BOOTCFG_DEVICE_UART1:
+ case BOOTCFG_DEVICE_UART2:
+ return BOOT_DEVICE_TYPE_UART;
+ case BOOTCFG_DEVICE_MMC_OR_SD0:
+ return BOOT_DEVICE_TYPE_MMC;
+ default:
+ return BOOT_DEVICE_TYPE_NONE;
+ }
+#else
+#ifdef
+#endif CONFIG_SPL_NAND_SUPPORT
+ return BOOT_DEVICE_TYPE_NAND;
+#endif
+#ifdef BOOT_DEVICE_SPI_FLASH
+ return BOOT_DEVICE_TYPE_SPI_FLASH;
+#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+ return BOOT_DEVICE_TYPE_UART;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_TYPE_MMC;
+#endif
+}
+
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts(Nand boot...\n);
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
- mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
- CONFIG_SYS_MALLOC_LEN);
+ u32 boot_device;
+ void (*uboot)(void) __noreturn;
+
+ mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+ CONFIG_SYS_SPL_MALLOC_SIZE);
gd = gdata;
gd-bd = bdata;
gd-flags |= GD_FLG_RELOC;
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
gd-baudrate = CONFIG_BAUDRATE;
- serial_init(); /* serial communications setup */
+ serial_init();
gd-have_console = 1;
+#endif
- puts(SPI boot...\n);
- spi_boot();
+ boot_device = davinci_boot_device();
+ debug(boot device - %d\n, boot_device);
+ switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_TYPE_NAND:
+ puts
[U-Boot] [PATCH V2 8/8] arm/davinci: spl - add compressed u-boot image support
Motivation:
* we have a board with 128 Kb spi flash, so normal u-boot.ais does not
fit on it.
This patch add support of compressed 2-nd u-boot stage. To create a compressed
ais image its required:
* define CONFIG_SPL_GUNZIP_SUPPORT --- enable compressed ais image supports
* define CONFIG_SPL_GUNZIP_MAX_SIZE --- define a maximum size of compressed
u-boot part
* define CONFIG_SPL_GUNZIP_LOAD_ADDR --- memory address to load compressed
u-boot part (CONFIG_SPL_GUNZIP_LOAD_ADDR region should not overlap with
CONFIG_SYS_TEXT_BASE region)
* use: make u-boot-gzip.ais to get a compressed ais image
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Change for v2:
* fix checkpatch warnings
* fix merge conflict with upstream u-boot sources
* improve patch description
---
Makefile | 14 ++
arch/arm/cpu/arm926ejs/davinci/spl.c |7 +++
arch/arm/cpu/arm926ejs/davinci/spl_mmc.c |7 ++-
arch/arm/cpu/arm926ejs/davinci/spl_nand.c |7 ++-
arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c |7 ++-
arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c|4
lib/Makefile |1 +
spl/Makefile |1 +
8 files changed, 45 insertions(+), 3 deletions(-)
diff --git a/Makefile b/Makefile
index 85e36ec..cf16824 100644
--- a/Makefile
+++ b/Makefile
@@ -452,6 +452,20 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
$(obj)u-boot.ais
rm $(obj)spl/u-boot-spl{,-pad}.ais
+$(obj)u-boot-gzip.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(obj)tools/mkimage -s -n /dev/null -T aisimage \
+ -e $(CONFIG_SPL_TEXT_BASE) \
+ -d $(obj)spl/u-boot-spl.bin \
+ $(obj)spl/u-boot-spl.ais
+ $(OBJCOPY) ${OBJCFLAGS} -I binary \
+ --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
+ $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
+ cp $(obj)u-boot.bin $(obj)spl/u-boot.bin
+ gzip $(obj)spl/u-boot.bin
+ cat $(obj)spl/u-boot-spl-pad.ais $(obj)spl/u-boot.bin.gz \
+ $(obj)u-boot-gzip.ais
+ rm $(obj)spl/u-boot-spl{,-pad}.ais $(obj)spl/u-boot.bin.gz
+
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 50b4bbc..041df5b 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -111,6 +111,7 @@ u32 davinci_boot_device(void){
void board_init_r(gd_t *id, ulong dummy)
{
+ int size;
u32 boot_device;
void (*uboot)(void) __noreturn;
@@ -159,6 +160,12 @@ void board_init_r(gd_t *id, ulong dummy)
break;
}
+#ifdef CONFIG_SPL_GUNZIP_SUPPORT
+ size = CONFIG_SPL_GUNZIP_MAX_SIZE;
+ gunzip((void *)CONFIG_SYS_TEXT_BASE, 512 * 1024,
+ (void *)CONFIG_SPL_GUNZIP_LOAD_ADDR, size);
+#endif
+
puts(Jump to U-Boot image...\n);
uboot = (void *) CONFIG_SYS_TEXT_BASE;
(*uboot)();
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
b/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
index 1a551e9..fa67f1a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
@@ -28,7 +28,12 @@ void spl_mmc_load_image(void)
ret = mmc-block_dev.block_read(0,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- (void *) CONFIG_SYS_TEXT_BASE);
+#ifndef CONFIG_SPL_GUNZIP_SUPPORT
+ (void *) CONFIG_SYS_TEXT_BASE
+#else
+ (void *) CONFIG_SPL_GUNZIP_LOAD_ADDR
+#endif
+ );
if (ret 0) {
printf(spl: mmc blk read err - %d\n, ret);
hang();
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
index bad1e8f..4bf3e6a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
@@ -6,6 +6,11 @@ void spl_nand_load_image(void)
nand_init();
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *) CONFIG_SYS_TEXT_BASE);
+#ifndef CONFIG_SPL_GUNZIP_SUPPORT
+ (void *) CONFIG_SYS_TEXT_BASE
+#else
+ (void *) CONFIG_SPL_GUNZIP_LOAD_ADDR
+#endif
+ );
debug(Loaded %d bytes from NAND flash\n, CONFIG_SYS_NAND_U_BOOT_SIZE);
}
diff --git a/arch
Re: [U-Boot] [PATCH 1/8] arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
On Thu, 21 Jun 2012 09:37:09 +0200 Christian Riesch christian.rie...@omicron.at wrote: Hi Mikhail, On Tue, Jun 12, 2012 at 11:15 PM, Mikhail Kshevetskiy mikhail.kshevets...@gmail.com wrote: follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of OMAP-L138 DSP+ARM Processor Technical Reference Manual Thanks for fixing this! Just out of curiosity: Did you hit any problem or were you just comparing the code with the reference manual? Hard to say, I faced with memory initialization problem (caused by hardware bug). Before I hit a real problem, I study omap documentation and find disagreements with the code. So i just fix it. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 25 --- arch/arm/include/asm/arch-davinci/hardware.h|1 + 2 files changed, 19 insertions(+), 7 deletions(-) Acked-by: Christian Riesch christian.rie...@omicron.at For the calimain board Tested-by: Christian Riesch christian.rie...@omicron.at Regards, Christian ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/6] arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 26 +--
arch/arm/include/asm/arch-davinci/hardware.h|1 +
2 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index df7d6a2..ff2e2e3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -190,13 +190,21 @@ int da850_ddr_setup(void)
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_LOCK);
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_POWERDWN);
-
- setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
}
-
+ setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, dv_ddr2_regs_ctrl-ddrphycr);
- clrbits_le32(davinci_syscfg1_regs-ddr_slew,
- (1 DDR_SLEW_CMOSEN_BIT));
+
+ if (CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT)) {
+ /* DDR2 */
+ clrbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ } else {
+ /* MOBILE DDR */
+ setbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ }
/*
* SDRAM Configuration Register (SDCR):
@@ -216,7 +224,11 @@ int da850_ddr_setup(void)
writel(tmp, dv_ddr2_regs_ctrl-sdbcr);
/* write memory configuration and timing */
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2, dv_ddr2_regs_ctrl-sdbcr2);
+ if (!(CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT))) {
+ /* MOBILE DDR only*/
+ writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
+ dv_ddr2_regs_ctrl-sdbcr2);
+ }
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, dv_ddr2_regs_ctrl-sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, dv_ddr2_regs_ctrl-sdtimr2);
@@ -240,7 +252,7 @@ int da850_ddr_setup(void)
/* disable self refresh */
clrbits_le32(dv_ddr2_regs_ctrl-sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+ DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, dv_ddr2_regs_ctrl-pbbpr);
return 0;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..56e5743 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -505,6 +505,7 @@ struct davinci_syscfg1_regs {
((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
#define DDR_SLEW_CMOSEN_BIT4
+#define DDR_SLEW_DDR_PDENA_BIT 5
#define VTP_POWERDWN (1 6)
#define VTP_LOCK (1 7)
--
1.7.10
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[U-Boot] [PATCH 3/6] serial/ns16550: ns16550 has a different register layout on SOC_DA8XX
also fix NS16550_init() as we need 16x divider
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
drivers/serial/ns16550.c |2 +-
include/ns16550.h|9 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0c23955..facadd2 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -52,7 +52,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor 8) 0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX)
+ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/include/ns16550.h b/include/ns16550.h
index e9d2eda..51cb5b4 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -46,6 +46,14 @@ struct NS16550 {
UART_REG(lsr); /* 5 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+ UART_REG(reg8); /* 8 */
+ UART_REG(reg9); /* 9 */
+ UART_REG(revid1); /* A */
+ UART_REG(revid2); /* B */
+ UART_REG(pwr_mgmt); /* C */
+ UART_REG(mdr1); /* D */
+#else
UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */
@@ -58,6 +66,7 @@ struct NS16550 {
UART_REG(ssr); /* 11*/
UART_REG(reg12);/* 12*/
UART_REG(osc_12m_sel); /* 13*/
+#endif
};
#define thr rbr
--
1.7.10
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[U-Boot] [PATCH 4/6] mtd/spi/spi_flash: support CMD_READ_ID=0x90 case
current code does not support spi flashes that have 0x90 read_id command,
so fix this
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
drivers/mtd/spi/spi_flash.c | 66 +++---
drivers/mtd/spi/spi_flash_internal.h |1 +
2 files changed, 47 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index f689cc4..530b7b3 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -306,13 +306,44 @@ static const struct {
};
#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
+struct spi_flash *spi_analize_flash_probe(struct spi_slave *spi,
+ u8 *idcode, size_t idcode_len, u8 *id)
+{
+ struct spi_flash *flash = NULL;
+ int i, shift;
+ u8 *idp;
+
+#ifdef DEBUG
+ printf(SF: Got idcodes\n);
+ print_buffer(0, idcode, 1, idcode_len, 0);
+#endif
+
+ /* count the number of continuation bytes */
+ for (shift = 0, idp = idcode;
+shift idcode_len *idp == 0x7f;
+++shift, ++idp)
+ continue;
+
+ *id = *idp;
+ /* search the table for matches in shift and id */
+ for (i = 0; i ARRAY_SIZE(flashes); ++i)
+ if (flashes[i].shift == shift flashes[i].idcode == *idp) {
+ /* we have a match, call probe */
+ flash = flashes[i].probe(spi, idp);
+ if (flash)
+ break;
+ }
+
+ return flash;
+}
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
struct spi_flash *flash = NULL;
- int ret, i, shift;
- u8 idcode[IDCODE_LEN], *idp;
+ u8 cmd[4], idcode[IDCODE_LEN], id;
+ int ret;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
@@ -331,28 +362,23 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
if (ret)
goto err_read_id;
-#ifdef DEBUG
- printf(SF: Got idcodes\n);
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
+ flash = spi_analize_flash_probe(spi, idcode, sizeof(idcode), id);
+ if (id == 0xff) {
+ /* try CMD_READ_ID_NEW command */
+ cmd[0] = CMD_READ_ID_NEW;
+ spi_flash_addr(0x00, cmd);
- /* count the number of continuation bytes */
- for (shift = 0, idp = idcode;
-shift IDCODE_CONT_LEN *idp == 0x7f;
-++shift, ++idp)
- continue;
+ ret = spi_flash_cmd_read(spi, cmd, sizeof(cmd),
+ idcode, sizeof(idcode));
+ if (ret)
+ goto err_read_id;
- /* search the table for matches in shift and id */
- for (i = 0; i ARRAY_SIZE(flashes); ++i)
- if (flashes[i].shift == shift flashes[i].idcode == *idp) {
- /* we have a match, call probe */
- flash = flashes[i].probe(spi, idp);
- if (flash)
- break;
- }
+ flash = spi_analize_flash_probe(spi,
+ idcode, sizeof(idcode), id);
+ }
if (!flash) {
- printf(SF: Unsupported manufacturer %02x\n, *idp);
+ printf(SF: Unsupported manufacturer %02x\n, id);
goto err_manufacturer_probe;
}
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 91e036a..b8bd5d5 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -14,6 +14,7 @@
/* Common commands */
#define CMD_READ_ID0x9f
+#define CMD_READ_ID_NEW0x90
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_ARRAY_FAST0x0b
--
1.7.10
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[U-Boot] [PATCH 2/6] arm/davinci/da850: add uart0 pinmux
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c |5 +
arch/arm/include/asm/arch-davinci/hardware.h|1 +
arch/arm/include/asm/arch-davinci/pinmux_defs.h |1 +
3 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..dbae5fa 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = {
};
/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+ { pinmux(3), 2, 4 }, /* UART0_RXD */
+ { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
const struct pinmux_config uart1_pins_txrx[] = {
{ pinmux(4), 2, 6 }, /* UART1_RXD */
{ pinmux(4), 2, 7 }, /* UART1_TXD */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 56e5743..76aca24 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -447,6 +447,7 @@ struct davinci_pllc_regs {
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..eddb3f7 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -28,6 +28,7 @@ extern const struct pinmux_config spi1_pins_base[3];
extern const struct pinmux_config spi1_pins_scs0[1];
/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
extern const struct pinmux_config uart1_pins_txrx[2];
extern const struct pinmux_config uart2_pins_txrx[2];
extern const struct pinmux_config uart2_pins_rtscts[2];
--
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[U-Boot] [PATCH 6/6] MMC: u-boot-spl may be compiled without partition support
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- drivers/mmc/mmc.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..69df64a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1253,7 +1253,9 @@ int mmc_startup(struct mmc *mmc) (mmc-cid[1] 8) 0xff, mmc-cid[1] 0xff); sprintf(mmc-block_dev.revision, %d.%d, mmc-cid[2] 28, (mmc-cid[2] 24) 0xf); +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) init_part(mmc-block_dev); +#endif return 0; } -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/6] mtd/spi: add sst25l driver
current SST driver does not support well this types of flash, so use
linux-3.3 code as a base.
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
drivers/mtd/spi/Makefile |3 +-
drivers/mtd/spi/spi_flash.c |3 +
drivers/mtd/spi/spi_flash_internal.h |1 +
drivers/mtd/spi/sst25l.c | 372 ++
4 files changed, 378 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/spi/sst25l.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..9285bf7 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -34,7 +34,8 @@ COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
-COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST25L) += sst25l.o
COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o
COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 530b7b3..d2da542 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -285,6 +285,9 @@ static const struct {
#ifdef CONFIG_SPI_FLASH_SST
{ 0, 0xbf, spi_flash_probe_sst, },
#endif
+#ifdef CONFIG_SPI_FLASH_SST25L
+ { 0, 0xbf, spi_flash_probe_sst25l, },
+#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
{ 0, 0x20, spi_flash_probe_stmicro, },
#endif
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index b8bd5d5..89d9036 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -98,6 +98,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave
*spi, u8 *idcode);
struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_sst25l(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
diff --git a/drivers/mtd/spi/sst25l.c b/drivers/mtd/spi/sst25l.c
new file mode 100644
index 000..9d7be0d
--- /dev/null
+++ b/drivers/mtd/spi/sst25l.c
@@ -0,0 +1,372 @@
+/*
+ * Driver for SST25L SPI Flash chips
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan mcmul...@netapp.com
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include common.h
+#include malloc.h
+#include spi_flash.h
+#include watchdog.h
+
+#include spi_flash_internal.h
+
+#define SST25L_CMD_WRSR0x01/* Write status register */
+#define SST25L_CMD_WRDI0x04/* Write disable */
+#define SST25L_CMD_RDSR0x05/* Read status register */
+#define SST25L_CMD_WREN0x06/* Write enable */
+#define SST25L_CMD_READ0x03/* High speed read */
+
+#define SST25L_CMD_EWSR0x50/* Enable write status register
*/
+#define SST25L_CMD_SECTOR_ERASE0x20/* Erase sector */
+#define SST25L_CMD_READ_ID 0x90/* Read device ID */
+#define SST25L_CMD_AAI_PROGRAM 0xaf/* Auto address increment */
+
+#define SST25L_STATUS_BUSY (1 0)/* Chip is busy */
+#define SST25L_STATUS_WREN (1 1)/* Write enabled */
+#define SST25L_STATUS_BP0 (1 2)/* Block protection 0 */
+#define SST25L_STATUS_BP1 (1 3)/* Block protection 1 */
+
+struct flash_info {
+ const char *name;
+ u16 device_id;
+ u32 page_size;
+ u32 nr_pages;
+ u32 erase_size;
+};
+
+struct sst25l_spi_flash {
+ struct spi_flashflash;
+ const struct flash_info *flash_info;
+};
+
+#define to_sst25l_spi_flash(x) container_of(x, struct sst25l_spi_flash, flash)
+
+static struct flash_info sst25l_flash_info[] = {
+ {sst25vf010a, 0xbf49, 256, 512, 4096},
+ {sst25lf020a, 0xbf43, 256, 1024, 4096},
+ {sst25lf040a, 0xbf44, 256, 2048, 4096},
+};
+
+static inline int spi_write_sync(struct spi_slave *spi,
+ const u8 *data, size_t len)
+{
+ return spi_xfer(spi, 8 * len, data,
+ NULL, SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+static int sst25l_status(struct spi_flash *flash, int *status
[U-Boot] [PATCH 1/8] arm/davinci: fix DDR2/mDDR memory controller initialization for Omap L138
follow section 15.2.13.1 (Initializing Following Device Power Up or Reset) of
OMAP-L138 DSP+ARM Processor Technical Reference Manual
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c | 25 ---
arch/arm/include/asm/arch-davinci/hardware.h|1 +
2 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
index df7d6a2..9682407 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c
@@ -190,13 +190,21 @@ int da850_ddr_setup(void)
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_LOCK);
setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_POWERDWN);
-
- setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
}
-
+ setbits_le32(davinci_syscfg1_regs-vtpio_ctl, VTP_IOPWRDWN);
writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, dv_ddr2_regs_ctrl-ddrphycr);
- clrbits_le32(davinci_syscfg1_regs-ddr_slew,
- (1 DDR_SLEW_CMOSEN_BIT));
+
+ if (CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT)){
+ /* DDR2 */
+ clrbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ }else{
+ /* MOBILE DDR */
+ setbits_le32(davinci_syscfg1_regs-ddr_slew,
+ (1 DDR_SLEW_DDR_PDENA_BIT) |
+ (1 DDR_SLEW_CMOSEN_BIT));
+ }
/*
* SDRAM Configuration Register (SDCR):
@@ -216,7 +224,10 @@ int da850_ddr_setup(void)
writel(tmp, dv_ddr2_regs_ctrl-sdbcr);
/* write memory configuration and timing */
- writel(CONFIG_SYS_DA850_DDR2_SDBCR2, dv_ddr2_regs_ctrl-sdbcr2);
+ if (!(CONFIG_SYS_DA850_DDR2_SDBCR (1 DV_DDR_SDCR_DDR2EN_SHIFT))){
+ /* MOBILE DDR only*/
+ writel(CONFIG_SYS_DA850_DDR2_SDBCR2,
dv_ddr2_regs_ctrl-sdbcr2);
+ }
writel(CONFIG_SYS_DA850_DDR2_SDTIMR, dv_ddr2_regs_ctrl-sdtimr);
writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, dv_ddr2_regs_ctrl-sdtimr2);
@@ -240,7 +251,7 @@ int da850_ddr_setup(void)
/* disable self refresh */
clrbits_le32(dv_ddr2_regs_ctrl-sdrcr,
- DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
+ DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_MCLKSTOPEN);
writel(CONFIG_SYS_DA850_DDR2_PBBPR, dv_ddr2_regs_ctrl-pbbpr);
return 0;
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..56e5743 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -505,6 +505,7 @@ struct davinci_syscfg1_regs {
((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
#define DDR_SLEW_CMOSEN_BIT4
+#define DDR_SLEW_DDR_PDENA_BIT 5
#define VTP_POWERDWN (1 6)
#define VTP_LOCK (1 7)
--
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[U-Boot] [PATCH 3/8] serial/ns16550: ns16550 has a different register layout on SOC_DA8XX
also fix NS16550_init() as we need 16x divider
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
drivers/serial/ns16550.c |2 +-
include/ns16550.h|9 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0c23955..e6dec0c 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -52,7 +52,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor 8) 0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX)
+defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/include/ns16550.h b/include/ns16550.h
index e9d2eda..51cb5b4 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -46,6 +46,14 @@ struct NS16550 {
UART_REG(lsr); /* 5 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+ UART_REG(reg8); /* 8 */
+ UART_REG(reg9); /* 9 */
+ UART_REG(revid1); /* A */
+ UART_REG(revid2); /* B */
+ UART_REG(pwr_mgmt); /* C */
+ UART_REG(mdr1); /* D */
+#else
UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */
@@ -58,6 +66,7 @@ struct NS16550 {
UART_REG(ssr); /* 11*/
UART_REG(reg12);/* 12*/
UART_REG(osc_12m_sel); /* 13*/
+#endif
};
#define thr rbr
--
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[U-Boot] [PATCH 2/8] arm/davinci/da850: add uart0 pinmux
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c |5 +
arch/arm/include/asm/arch-davinci/hardware.h|1 +
arch/arm/include/asm/arch-davinci/pinmux_defs.h |1 +
3 files changed, 7 insertions(+)
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..dbae5fa 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = {
};
/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+ { pinmux(3), 2, 4 }, /* UART0_RXD */
+ { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
const struct pinmux_config uart1_pins_txrx[] = {
{ pinmux(4), 2, 6 }, /* UART1_RXD */
{ pinmux(4), 2, 7 }, /* UART1_TXD */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index 56e5743..76aca24 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -447,6 +447,7 @@ struct davinci_pllc_regs {
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..eddb3f7 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -28,6 +28,7 @@ extern const struct pinmux_config spi1_pins_base[3];
extern const struct pinmux_config spi1_pins_scs0[1];
/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
extern const struct pinmux_config uart1_pins_txrx[2];
extern const struct pinmux_config uart2_pins_txrx[2];
extern const struct pinmux_config uart2_pins_rtscts[2];
--
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[U-Boot] [PATCH 4/8] mtd/spi/spi_flash: support CMD_READ_ID=0x90 case
current code does not support spi flashes that have 0x90 read_id command,
so fix this
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
drivers/mtd/spi/spi_flash.c | 64 +++---
drivers/mtd/spi/spi_flash_internal.h |1 +
2 files changed, 45 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index f689cc4..5c931da 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -306,13 +306,44 @@ static const struct {
};
#define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN)
+struct spi_flash *spi_analize_flash_probe(struct spi_slave *spi,
+ u8 *idcode, size_t idcode_len, u8 *id)
+{
+ struct spi_flash *flash = NULL;
+ int i, shift;
+ u8 *idp;
+
+#ifdef DEBUG
+ printf(SF: Got idcodes\n);
+ print_buffer(0, idcode, 1, idcode_len, 0);
+#endif
+
+ /* count the number of continuation bytes */
+ for (shift = 0, idp = idcode;
+shift idcode_len *idp == 0x7f;
+++shift, ++idp)
+ continue;
+
+ *id = *idp;
+ /* search the table for matches in shift and id */
+ for (i = 0; i ARRAY_SIZE(flashes); ++i)
+ if (flashes[i].shift == shift flashes[i].idcode == *idp) {
+ /* we have a match, call probe */
+ flash = flashes[i].probe(spi, idp);
+ if (flash)
+ break;
+ }
+
+ return flash;
+}
+
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
struct spi_flash *flash = NULL;
- int ret, i, shift;
- u8 idcode[IDCODE_LEN], *idp;
+ u8 cmd[4], idcode[IDCODE_LEN], id;
+ int ret;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
@@ -331,28 +362,21 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
if (ret)
goto err_read_id;
-#ifdef DEBUG
- printf(SF: Got idcodes\n);
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
-#endif
+ flash = spi_analize_flash_probe(spi, idcode, sizeof(idcode), id);
+ if (id == 0xff) {
+ /* try CMD_READ_ID_NEW command */
+ cmd[0] = CMD_READ_ID_NEW;
+ spi_flash_addr(0x00, cmd);
- /* count the number of continuation bytes */
- for (shift = 0, idp = idcode;
-shift IDCODE_CONT_LEN *idp == 0x7f;
-++shift, ++idp)
- continue;
+ ret = spi_flash_cmd_read(spi, cmd, sizeof(cmd), idcode,
sizeof(idcode));
+ if (ret)
+ goto err_read_id;
- /* search the table for matches in shift and id */
- for (i = 0; i ARRAY_SIZE(flashes); ++i)
- if (flashes[i].shift == shift flashes[i].idcode == *idp) {
- /* we have a match, call probe */
- flash = flashes[i].probe(spi, idp);
- if (flash)
- break;
- }
+ flash = spi_analize_flash_probe(spi, idcode, sizeof(idcode),
id);
+ }
if (!flash) {
- printf(SF: Unsupported manufacturer %02x\n, *idp);
+ printf(SF: Unsupported manufacturer %02x\n, id);
goto err_manufacturer_probe;
}
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index 91e036a..b8bd5d5 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -14,6 +14,7 @@
/* Common commands */
#define CMD_READ_ID0x9f
+#define CMD_READ_ID_NEW0x90
#define CMD_READ_ARRAY_SLOW0x03
#define CMD_READ_ARRAY_FAST0x0b
--
1.7.10
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/8] mtd/spi: add sst25l driver
current SST driver does not support well this types of flash, so use
linux-3.3 code as a base.
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
drivers/mtd/spi/Makefile |3 +-
drivers/mtd/spi/spi_flash.c |3 +
drivers/mtd/spi/spi_flash_internal.h |1 +
drivers/mtd/spi/sst25l.c | 363 ++
4 files changed, 369 insertions(+), 1 deletion(-)
create mode 100644 drivers/mtd/spi/sst25l.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..9285bf7 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -34,7 +34,8 @@ COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o
COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o
COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o
COBJS-$(CONFIG_SPI_FLASH_SPANSION) += spansion.o
-COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST) += sst.o
+COBJS-$(CONFIG_SPI_FLASH_SST25L) += sst25l.o
COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o
COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o
COBJS-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.o
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 5c931da..846b9b0 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -285,6 +285,9 @@ static const struct {
#ifdef CONFIG_SPI_FLASH_SST
{ 0, 0xbf, spi_flash_probe_sst, },
#endif
+#ifdef CONFIG_SPI_FLASH_SST25L
+ { 0, 0xbf, spi_flash_probe_sst25l, },
+#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
{ 0, 0x20, spi_flash_probe_stmicro, },
#endif
diff --git a/drivers/mtd/spi/spi_flash_internal.h
b/drivers/mtd/spi/spi_flash_internal.h
index b8bd5d5..89d9036 100644
--- a/drivers/mtd/spi/spi_flash_internal.h
+++ b/drivers/mtd/spi/spi_flash_internal.h
@@ -98,6 +98,7 @@ struct spi_flash *spi_flash_probe_atmel(struct spi_slave
*spi, u8 *idcode);
struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_sst25l(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
diff --git a/drivers/mtd/spi/sst25l.c b/drivers/mtd/spi/sst25l.c
new file mode 100644
index 000..6c2cc0f
--- /dev/null
+++ b/drivers/mtd/spi/sst25l.c
@@ -0,0 +1,363 @@
+/*
+ * Driver for SST25L SPI Flash chips
+ *
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan mcmul...@netapp.com
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (tsi-chung.l...@freescale.com)
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include common.h
+#include malloc.h
+#include spi_flash.h
+#include watchdog.h
+
+#include spi_flash_internal.h
+
+#define SST25L_CMD_WRSR0x01/* Write status register */
+#define SST25L_CMD_WRDI0x04/* Write disable */
+#define SST25L_CMD_RDSR0x05/* Read status register */
+#define SST25L_CMD_WREN0x06/* Write enable */
+#define SST25L_CMD_READ0x03/* High speed read */
+
+#define SST25L_CMD_EWSR0x50/* Enable write status register
*/
+#define SST25L_CMD_SECTOR_ERASE0x20/* Erase sector */
+#define SST25L_CMD_READ_ID 0x90/* Read device ID */
+#define SST25L_CMD_AAI_PROGRAM 0xaf/* Auto address increment */
+
+#define SST25L_STATUS_BUSY (1 0)/* Chip is busy */
+#define SST25L_STATUS_WREN (1 1)/* Write enabled */
+#define SST25L_STATUS_BP0 (1 2)/* Block protection 0 */
+#define SST25L_STATUS_BP1 (1 3)/* Block protection 1 */
+
+struct flash_info {
+ const char *name;
+ u16 device_id;
+ u32 page_size;
+ u32 nr_pages;
+ u32 erase_size;
+};
+
+struct sst25l_spi_flash {
+ struct spi_flashflash;
+ const struct flash_info *flash_info;
+};
+
+#define to_sst25l_spi_flash(x) container_of(x, struct sst25l_spi_flash, flash)
+
+static struct flash_info sst25l_flash_info[] = {
+ {sst25vf010a, 0xbf49, 256, 512, 4096},
+ {sst25lf020a, 0xbf43, 256, 1024, 4096},
+ {sst25lf040a, 0xbf44, 256, 2048, 4096},
+};
+
+static inline int spi_write_sync(struct spi_slave *spi, const u8 *data, size_t
len)
+{
+ return spi_xfer(spi, 8 * len, data, NULL, SPI_XFER_BEGIN |
SPI_XFER_END);
+}
+
+static int sst25l_status(struct spi_flash *flash, int *status)
+{
+ unsigned char cmd_resp[2];
+ int err
[U-Boot] [PATCH 6/8] MMC: u-boot-spl may be compiled without partition support
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- drivers/mmc/mmc.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..69df64a 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1253,7 +1253,9 @@ int mmc_startup(struct mmc *mmc) (mmc-cid[1] 8) 0xff, mmc-cid[1] 0xff); sprintf(mmc-block_dev.revision, %d.%d, mmc-cid[2] 28, (mmc-cid[2] 24) 0xf); +#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) init_part(mmc-block_dev); +#endif return 0; } -- 1.7.10 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 8/8] arm/davinci: spl - add compressed u-boot image support
we have a board with 128 Kb spi flash, so normal u-boot.ais does not fit on it.
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
Makefile | 14 ++
arch/arm/cpu/arm926ejs/davinci/spl.c |6 ++
arch/arm/cpu/arm926ejs/davinci/spl_mmc.c |9 +++--
arch/arm/cpu/arm926ejs/davinci/spl_nand.c |9 +++--
arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c |7 ++-
arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c|4
lib/Makefile |2 ++
spl/Makefile |1 +
8 files changed, 47 insertions(+), 5 deletions(-)
diff --git a/Makefile b/Makefile
index 0197239..1cd6f03 100644
--- a/Makefile
+++ b/Makefile
@@ -452,6 +452,20 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin
$(obj)u-boot.bin
$(obj)u-boot.ais
rm $(obj)spl/u-boot-spl{,-pad}.ais
+$(obj)u-boot-gzip.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
+ $(obj)tools/mkimage -s -n /dev/null -T aisimage \
+ -e $(CONFIG_SPL_TEXT_BASE) \
+ -d $(obj)spl/u-boot-spl.bin \
+ $(obj)spl/u-boot-spl.ais
+ $(OBJCOPY) ${OBJCFLAGS} -I binary \
+ --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \
+ $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais
+ cp $(obj)u-boot.bin $(obj)spl/u-boot.bin
+ gzip $(obj)spl/u-boot.bin
+ cat $(obj)spl/u-boot-spl-pad.ais $(obj)spl/u-boot.bin.gz \
+ $(obj)u-boot-gzip.ais
+ rm $(obj)spl/u-boot-spl{,-pad}.ais $(obj)spl/u-boot.bin.gz
+
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
-o $(obj)u-boot.sb
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index a8c318c..f6ddea3 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -111,6 +111,7 @@ u32 davinci_boot_device(void){
void board_init_r(gd_t *id, ulong dummy)
{
+ int size;
u32 boot_device;
void (*uboot)(void) __noreturn;
@@ -159,6 +160,11 @@ void board_init_r(gd_t *id, ulong dummy)
break;
}
+#ifdef CONFIG_SPL_GUNZIP_SUPPORT
+ size = CONFIG_SPL_GUNZIP_MAX_SIZE;
+ gunzip((void*)CONFIG_SYS_TEXT_BASE, 512 * 1024,
(void*)CONFIG_SPL_GUNZIP_LOAD_ADDR, size);
+#endif
+
puts(Jump to U-Boot image...\n);
uboot = (void *) CONFIG_SYS_TEXT_BASE;
(*uboot)();
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
b/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
index 520ecd1..ce8b57b 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
@@ -26,8 +26,13 @@ void spl_mmc_load_image(void)
}
ret = mmc-block_dev.block_read(0,
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR,
- CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
- (void *) CONFIG_SYS_TEXT_BASE);
+ CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS,
+#ifndef CONFIG_SPL_GUNZIP_SUPPORT
+ (void *) CONFIG_SYS_TEXT_BASE
+#else
+ (void *) CONFIG_SPL_GUNZIP_LOAD_ADDR
+#endif
+ );
if (ret 0) {
printf(spl: mmc blk read err - %d\n, ret);
hang();
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
index bad1e8f..da5358c 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_nand.c
@@ -5,7 +5,12 @@ void spl_nand_load_image(void)
{
nand_init();
nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
- CONFIG_SYS_NAND_U_BOOT_SIZE,
- (void *) CONFIG_SYS_TEXT_BASE);
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+#ifndef CONFIG_SPL_GUNZIP_SUPPORT
+ (void *) CONFIG_SYS_TEXT_BASE
+#else
+ (void *) CONFIG_SPL_GUNZIP_LOAD_ADDR
+#endif
+ );
debug(Loaded %d bytes from NAND flash\n, CONFIG_SYS_NAND_U_BOOT_SIZE);
}
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
b/arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
index 2d5b045..710429f 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
@@ -15,7 +15,12 @@ void spl_spi_flash_load_image(void)
ret = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS,
CONFIG_SYS_SPI_U_BOOT_SIZE,
-(void *) CONFIG_SYS_TEXT_BASE);
+#ifndef CONFIG_SPL_GUNZIP_SUPPORT
[U-Boot] [PATCH 7/8] arm/davinci: spl - boot device selection
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
arch/arm/cpu/arm926ejs/davinci/Makefile |5 ++
arch/arm/cpu/arm926ejs/davinci/spl.c | 91 +++---
arch/arm/cpu/arm926ejs/davinci/spl_mmc.c | 37 +
arch/arm/cpu/arm926ejs/davinci/spl_nand.c| 11 +++
arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c | 25 ++
arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c | 41 ++
arch/arm/include/asm/arch-davinci/davinci_boot.h | 25 ++
include/configs/cam_enc_4xx.h| 12 +--
include/configs/da850evm.h | 19 +++--
include/configs/hawkboard.h | 11 +--
10 files changed, 247 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_mmc.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_nand.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_spi_flash.c
create mode 100644 arch/arm/cpu/arm926ejs/davinci/spl_ymodem.c
create mode 100644 arch/arm/include/asm/arch-davinci/davinci_boot.h
diff --git a/arch/arm/cpu/arm926ejs/davinci/Makefile
b/arch/arm/cpu/arm926ejs/davinci/Makefile
index da7efac..12bd37a 100644
--- a/arch/arm/cpu/arm926ejs/davinci/Makefile
+++ b/arch/arm/cpu/arm926ejs/davinci/Makefile
@@ -40,6 +40,11 @@ ifdef CONFIG_SPL_BUILD
COBJS-y+= spl.o
COBJS-$(CONFIG_SOC_DM365) += dm365_lowlevel.o
COBJS-$(CONFIG_SOC_DA8XX) += da850_lowlevel.o
+
+COBJS-$(CONFIG_SPL_NAND_SUPPORT) += spl_nand.o
+COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += spl_spi_flash.o
+COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += spl_ymodem.o
+COBJS-$(CONFIG_SPL_MMC_SUPPORT)+= spl_mmc.o
endif
SOBJS = reset.o
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 74632e5..a8c318c 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -25,9 +25,11 @@
#include asm/utils.h
#include nand.h
#include asm/arch/dm365_lowlevel.h
+#include asm/arch/davinci_boot.h
#include ns16550.h
#include malloc.h
#include spi_flash.h
+#include linux/compiler.h
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -72,25 +74,92 @@ void board_init_f(ulong dummy)
relocate_code(CONFIG_SPL_STACK, NULL, CONFIG_SPL_TEXT_BASE);
}
+u32 davinci_boot_device(void){
+#ifdef CONFIG_SOC_DA8XX
+ u32 bootmode = ((*((vu_long*)0x01C14020)) 0x1F);
+ switch(bootmode){
+ case 0x0E: /* NAND 8 */
+ case 0x10: /* NAND 16 */
+ return BOOT_DEVICE_NAND;
+ case 0x0A:
+ case 0x0C:
+ return BOOT_DEVICE_SPI_FLASH;
+ case 0x16: /* UART0 */
+ case 0x17: /* UART1 */
+ case 0x14: /* UART2 */
+ return BOOT_DEVICE_UART;
+ case 0x1C: /* MMC/SD */
+ return BOOT_DEVICE_MMC;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+#else
+#ifdef
+#endif CONFIG_SPL_NAND_SUPPORT
+ return BOOT_DEVICE_NAND;
+#endif
+#ifdef BOOT_DEVICE_SPI_FLASH
+ return BOOT_DEVICE_SPI_FLASH;
+#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+ return BOOT_DEVICE_UART;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ return BOOT_DEVICE_MMC;
+#endif
+}
+
void board_init_r(gd_t *id, ulong dummy)
{
-#ifdef CONFIG_SPL_NAND_LOAD
- nand_init();
- puts(Nand boot...\n);
- nand_boot();
-#endif
-#ifdef CONFIG_SPL_SPI_LOAD
- mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
- CONFIG_SYS_MALLOC_LEN);
+ u32 boot_device;
+ void (*uboot)(void) __noreturn;
+
+ mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+ CONFIG_SYS_SPL_MALLOC_SIZE);
gd = gdata;
gd-bd = bdata;
gd-flags |= GD_FLG_RELOC;
+#ifdef CONFIG_SPL_SERIAL_SUPPORT
gd-baudrate = CONFIG_BAUDRATE;
- serial_init(); /* serial communications setup */
+ serial_init();
gd-have_console = 1;
+#endif
- puts(SPI boot...\n);
- spi_boot();
+ boot_device = davinci_boot_device();
+ debug(boot device - %d\n, boot_device);
+ switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_NAND:
+ puts(Booting from nand flash ...\n);
+ spl_nand_load_image();
+ break;
+#endif
+#ifdef CONFIG_SPL_SPI_FLASH_SUPPORT
+ case BOOT_DEVICE_SPI_FLASH:
+ puts(Booting from spi flash ...\n);
+ spl_spi_flash_load_image();
+ break;
#endif
+#ifdef CONFIG_SPL_YMODEM_SUPPORT
+ case BOOT_DEVICE_UART:
+ puts(Booting from uart ...\n);
+ spl_ymodem_load_image();
+ break;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+ case BOOT_DEVICE_MMC:
+ puts(Booting from mmc/sd card...\n);
+ spl_mmc_load_image();
+ break;
+#endif
+ default
Re: [U-Boot] [PATCH 1/3] spl: add ymodem support
On Wed, 7 Mar 2012 08:25:39 -0700 Tom Rini tr...@ti.com wrote: On Wed, Mar 07, 2012 at 12:54:05AM +0400, Mikhail Kshevetskiy wrote: We have an omap l138 based board without jtag and empty spi flash. UART is an only way to load something on this board, so we are using uart to load spl image u-boot and then we are using ymodem to load the rest part of u-boot. This conflicts a bit with the SPL ymodem support that's now in u-boot-arm/master and making its way into mainline. Please rebase (and perhaps play some Makefile magic games to get arch/arm/cpu/armv7/omap-common/spl_ymodem.c available to davinci, and yes, we all know we need to unify more of the SPL codebase). Hm, spl_ymodem_load_image() should be arch independent, so I suggest moving it and getcymodem() out from arch/arm/cpu/armv7/omap-common/spl_ymodem.c to common/xyzModem.c (similarly to my patch). any comments, suggestions? Mikhail -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] spl: add ymodem support
We have an omap l138 based board without jtag and empty spi flash.
UART is an only way to load something on this board, so we are using
uart to load spl image u-boot and then we are using ymodem to load
the rest part of u-boot.
---
arch/arm/cpu/arm926ejs/davinci/spl.c | 25 +++
common/Makefile |4 ++-
common/xyzModem.c| 55 ++
include/xyzModem.h |5 +++
lib/Makefile |1 +
5 files changed, 89 insertions(+), 1 deletions(-)
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
diff --git a/arch/arm/cpu/arm926ejs/davinci/spl.c
b/arch/arm/cpu/arm926ejs/davinci/spl.c
index 74632e5..1fedf7d 100644
--- a/arch/arm/cpu/arm926ejs/davinci/spl.c
+++ b/arch/arm/cpu/arm926ejs/davinci/spl.c
@@ -28,6 +28,7 @@
#include ns16550.h
#include malloc.h
#include spi_flash.h
+#include xyzModem.h
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
@@ -93,4 +94,28 @@ void board_init_r(gd_t *id, ulong dummy)
puts(SPI boot...\n);
spi_boot();
#endif
+#ifdef CONFIG_SPL_YMODEM_LOAD
+ mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
+ CONFIG_SYS_MALLOC_LEN);
+
+ gd = gdata;
+ gd-bd = bdata;
+ gd-flags |= GD_FLG_RELOC;
+ gd-baudrate = CONFIG_BAUDRATE;
+ serial_init(); /* serial communications setup */
+ gd-have_console = 1;
+
+ while(1){
+ charch;
+
+ while(!tstc()){
+ puts(Ymodem boot: press Enter to continue...\n);
+ mdelay(1000);
+ }
+ ch = getc();
+ if ((ch == '\r') || (ch == '\n')) break;
+ }
+ puts(Ymodem boot...\n);
+ ymodem_boot();
+#endif
}
diff --git a/common/Makefile b/common/Makefile
index 2a31c62..417a517 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -188,7 +188,9 @@ COBJS-y += console.o
COBJS-y += dlmalloc.o
COBJS-y += memsize.o
COBJS-y += stdio.o
-
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_YMODEM_LOAD) += xyzModem.o
+endif
COBJS := $(sort $(COBJS-y))
XCOBJS := $(sort $(XCOBJS-y))
diff --git a/common/xyzModem.c b/common/xyzModem.c
index a1f955b..8e024d0 100644
--- a/common/xyzModem.c
+++ b/common/xyzModem.c
@@ -847,3 +847,58 @@ GETC_IO_FUNCS (xyzModem_io, xyzModem_stream_open,
xyzModem_stream_close,
RedBoot_load (xmodem, xyzModem_io, false, false, xyzModem_xmodem);
RedBoot_load (ymodem, xyzModem_io, false, false, xyzModem_ymodem);
#endif
+
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_YMODEM_LOAD
+static int getcxmodem(void) {
+ if (tstc())
+ return (getc());
+ return -1;
+}
+
+/*
+ * The main entry for YMODEM booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from serial line into SDRAM and starts it from there.
+ */
+void ymodem_boot(void)
+{
+ int size;
+ int err;
+ int res;
+ connection_info_t info;
+ void (*uboot)(void) __noreturn;
+ ulong store_addr = ~0;
+
+ /*
+* Load U-Boot image from serial line into RAM
+*/
+ size = 0;
+ info.mode = xyzModem_ymodem;
+ res = xyzModem_stream_open (info, err);
+ if (!res) {
+ store_addr = CONFIG_SYS_TEXT_BASE;
+ while ((res =
+ xyzModem_stream_read (store_addr, 1024, err)) 0) {
+ store_addr += res;
+ size += res;
+ }
+ } else {
+ printf (%s\n, xyzModem_error (err));
+ hang();
+ }
+
+ xyzModem_stream_close (err);
+ xyzModem_stream_terminate (false, getcxmodem);
+
+ printf (## Total Size = 0x%08x = %d Bytes\n, size, size);
+
+ /*
+* Jump to U-Boot image
+*/
+ uboot = (void *) CONFIG_SYS_TEXT_BASE;
+ (*uboot)();
+}
+#endif /* CONFIG_SPL_YMODEM_LOAD */
+#endif /* CONFIG_SPL_BUILD */
diff --git a/include/xyzModem.h b/include/xyzModem.h
index f437bbd..275894c 100644
--- a/include/xyzModem.h
+++ b/include/xyzModem.h
@@ -58,6 +58,9 @@
#ifndef _XYZMODEM_H_
#define _XYZMODEM_H_
+#include linux/types.h
+#include linux/compiler.h
+
#define xyzModem_xmodem 1
#define xyzModem_ymodem 2
/* Don't define this until the protocol support is in place */
@@ -114,4 +117,6 @@ void xyzModem_stream_terminate(bool method, int
(*getc)(void));
int xyzModem_stream_read(char *buf, int size, int *err);
char *xyzModem_error(int err);
+void ymodem_boot(void) __noreturn;
+
#endif /* _XYZMODEM_H_ */
diff --git a/lib/Makefile b/lib/Makefile
index e6e6ec6..2983530 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_SHA256) += sha256.o
COBJS-y+= strmhz.o
COBJS-$(CONFIG_RBTREE) += rbtree.o
else
+COBJS-$(CONFIG_SPL_YMODEM_LOAD) += crc16.o
COBJS-$(CONFIG_SPL_SPI_FLASH_SUPPORT
[U-Boot] [PATCH 3/3] arm/davinci/da850: add uart0 pinmux
---
arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c |5 +
arch/arm/include/asm/arch-davinci/hardware.h|1 +
arch/arm/include/asm/arch-davinci/pinmux_defs.h |1 +
3 files changed, 7 insertions(+), 0 deletions(-)
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
diff --git a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
index fa07fb5..dbae5fa 100644
--- a/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
+++ b/arch/arm/cpu/arm926ejs/davinci/da850_pinmux.c
@@ -35,6 +35,11 @@ const struct pinmux_config spi1_pins_scs0[] = {
};
/* UART pin muxer settings */
+const struct pinmux_config uart0_pins_txrx[] = {
+ { pinmux(3), 2, 4 }, /* UART0_RXD */
+ { pinmux(3), 2, 5 }, /* UART0_TXD */
+};
+
const struct pinmux_config uart1_pins_txrx[] = {
{ pinmux(4), 2, 6 }, /* UART1_RXD */
{ pinmux(4), 2, 7 }, /* UART1_TXD */
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h
b/arch/arm/include/asm/arch-davinci/hardware.h
index b145c6e..0a1e2cd 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -447,6 +447,7 @@ struct davinci_pllc_regs {
/* Clock IDs */
enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2,
+ DAVINCI_UART0_CLKID = 2,
DAVINCI_UART2_CLKID = 2,
DAVINCI_MMC_CLKID = 2,
DAVINCI_MDIO_CLKID = 4,
diff --git a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
index 07aceaa..eddb3f7 100644
--- a/arch/arm/include/asm/arch-davinci/pinmux_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pinmux_defs.h
@@ -28,6 +28,7 @@ extern const struct pinmux_config spi1_pins_base[3];
extern const struct pinmux_config spi1_pins_scs0[1];
/* UART pin muxer settings */
+extern const struct pinmux_config uart0_pins_txrx[2];
extern const struct pinmux_config uart1_pins_txrx[2];
extern const struct pinmux_config uart2_pins_txrx[2];
extern const struct pinmux_config uart2_pins_rtscts[2];
--
1.7.9.1
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[U-Boot] [PATCH 2/3] ns16550 has a different register layout on SOC_DA8XX
also fix NS16550_init() as we need 16x divider
---
drivers/serial/ns16550.c |2 +-
include/ns16550.h|9 +
2 files changed, 10 insertions(+), 1 deletions(-)
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 0c23955..e6dec0c 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -52,7 +52,7 @@ void NS16550_init(NS16550_t com_port, int baud_divisor)
serial_out((baud_divisor 8) 0xff, com_port-dlm);
serial_out(UART_LCRVAL, com_port-lcr);
#if (defined(CONFIG_OMAP) !defined(CONFIG_OMAP3_ZOOM2)) || \
- defined(CONFIG_AM33XX)
+defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX)
#if defined(CONFIG_APTIX)
/* /13 mode so Aptix 6MHz can hit 115200 */
diff --git a/include/ns16550.h b/include/ns16550.h
index e9d2eda..51cb5b4 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -46,6 +46,14 @@ struct NS16550 {
UART_REG(lsr); /* 5 */
UART_REG(msr); /* 6 */
UART_REG(spr); /* 7 */
+#ifdef CONFIG_SOC_DA8XX
+ UART_REG(reg8); /* 8 */
+ UART_REG(reg9); /* 9 */
+ UART_REG(revid1); /* A */
+ UART_REG(revid2); /* B */
+ UART_REG(pwr_mgmt); /* C */
+ UART_REG(mdr1); /* D */
+#else
UART_REG(mdr1); /* 8 */
UART_REG(reg9); /* 9 */
UART_REG(regA); /* A */
@@ -58,6 +66,7 @@ struct NS16550 {
UART_REG(ssr); /* 11*/
UART_REG(reg12);/* 12*/
UART_REG(osc_12m_sel); /* 13*/
+#endif
};
#define thr rbr
--
1.7.9.1
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Re: [U-Boot] [PATCH 1/3] spl: add ymodem support
On Tue, 6 Mar 2012 18:34:05 -0300 Fabio Estevam feste...@gmail.com wrote: On Tue, Mar 6, 2012 at 5:54 PM, Mikhail Kshevetskiy mikhail.kshevets...@gmail.com wrote: We have an omap l138 based board without jtag and empty spi flash. UART is an only way to load something on this board, so we are using uart to load spl image u-boot and then we are using ymodem to load the rest part of u-boot. --- arch/arm/cpu/arm926ejs/davinci/spl.c | 25 +++ common/Makefile | 4 ++- common/xyzModem.c | 55 ++ include/xyzModem.h | 5 +++ lib/Makefile | 1 + 5 files changed, 89 insertions(+), 1 deletions(-) Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com Your Signed-off-by line should be placed above the --- line. Same applies for the other patches. fix and resend? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] spl: add ymodem support
On Tue, 6 Mar 2012 22:28:46 + Laurence Withers lwith...@guralp.com wrote: On Wed, Mar 07, 2012 at 12:54:05AM +0400, Mikhail Kshevetskiy wrote: We have an omap l138 based board without jtag and empty spi flash. UART is an only way to load something on this board, so we are using uart to load spl image u-boot and then we are using ymodem to load the rest part of u-boot. Dear Mikhail, I am asking mainly out of curiousity, rather than giving feedback on the patch, but the OMAP-L138 boot ROM has the capability to load both SPL and U-Boot into empty SPI flash using the UART and sfh program or equivalent. (sfh is serial flash host for those following along, a program to talk to the boot ROM over the UART and download some code that the boot ROM can burn into SPI flash). What is the advantage in allowing the SPL to flash U-Boot also? sfh and boot rom does not understand our flash. Many thanks, and bye for now, -- Laurence Withers, lwith...@guralp.comhttp://www.guralp.com/ Direct tel:+447753988197 or tel:+44408643 Software Engineer General support queries: supp...@guralp.com CMG-DCM CMG-EAM CMG-NAM ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm/pxa: remove unused arch-pxa/macro.h
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- arch/arm/cpu/pxa/start.S |1 - arch/arm/include/asm/arch-pxa/macro.h | 328 - onenand_ipl/board/vpac270/Makefile|5 - onenand_ipl/board/vpac270/lowlevel_init.S | 34 --- 4 files changed, 0 insertions(+), 368 deletions(-) delete mode 100644 arch/arm/include/asm/arch-pxa/macro.h delete mode 100644 onenand_ipl/board/vpac270/lowlevel_init.S diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index bf8510e..f15a43a 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -33,7 +33,6 @@ #include config.h #include version.h #include asm/arch/pxa-regs.h -#include asm/arch/macro.h /* takes care the CP15 update has taken place */ .macro CPWAIT reg diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h deleted file mode 100644 index 85958dd..000 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ /dev/null @@ -1,328 +0,0 @@ -/* - * arch/arm/include/asm/arch-pxa/macro.h - * - * Copyright (C) 2010 Marek Vasut marek.va...@gmail.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_PXA_MACRO_H__ -#define __ASM_ARCH_PXA_MACRO_H__ -#ifdef __ASSEMBLY__ - -#include asm/macro.h -#include asm/arch/pxa-regs.h - -/* - * This macro performs a 32bit write to a memory location and makes sure the - * write operation really happened by performing a read back. - * - * Clobbered regs: r4, r5 - */ -.macro write32rb addr, data - ldr r4, =\addr - ldr r5, =\data - str r5, [r4] - ldr r5, [r4] -.endm - -/* - * This macro waits according to OSCR incrementation - * - * Clobbered regs: r4, r5, r6 - */ -.macro pxa_wait_ticks ticks - ldr r4, =OSCR - mov r5, #0 - str r5, [r4] - ldr r5, =\ticks -1: - ldr r6, [r4] - cmp r5, r6 - bgt 1b -.endm - -/* - * This macro sets up the GPIO pins of the PXA2xx/PXA3xx CPU - * - * Clobbered regs: r4, r5 - */ -.macro pxa_gpio_setup - write32 GPSR0, CONFIG_SYS_GPSR0_VAL - write32 GPSR1, CONFIG_SYS_GPSR1_VAL - write32 GPSR2, CONFIG_SYS_GPSR2_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GPSR3, CONFIG_SYS_GPSR3_VAL -#endif - - write32 GPCR0, CONFIG_SYS_GPCR0_VAL - write32 GPCR1, CONFIG_SYS_GPCR1_VAL - write32 GPCR2, CONFIG_SYS_GPCR2_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GPCR3, CONFIG_SYS_GPCR3_VAL -#endif - - write32 GPDR0, CONFIG_SYS_GPDR0_VAL - write32 GPDR1, CONFIG_SYS_GPDR1_VAL - write32 GPDR2, CONFIG_SYS_GPDR2_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GPDR3, CONFIG_SYS_GPDR3_VAL -#endif - - write32 GAFR0_L, CONFIG_SYS_GAFR0_L_VAL - write32 GAFR0_U, CONFIG_SYS_GAFR0_U_VAL - write32 GAFR1_L, CONFIG_SYS_GAFR1_L_VAL - write32 GAFR1_U, CONFIG_SYS_GAFR1_U_VAL - write32 GAFR2_L, CONFIG_SYS_GAFR2_L_VAL - write32 GAFR2_U, CONFIG_SYS_GAFR2_U_VAL -#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) - write32 GAFR3_L, CONFIG_SYS_GAFR3_L_VAL - write32 GAFR3_U, CONFIG_SYS_GAFR3_U_VAL -#endif - - write32 PSSR, CONFIG_SYS_PSSR_VAL -.endm - -/* - * This macro sets up the Memory controller of the PXA2xx CPU - * - * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE - * and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not - * use this regs for other purpose inside this macro. - * - * Clobbered regs: r3, r4, r5, r6, r7 - */ -.macro pxa_mem_setup - /* This comes handy when setting MDREFR */ - ldr r3, =MEMC_BASE - - /* -* 1) Initialize Asynchronous static memory controller -*/ - - /* MSC0: nCS(0,1) */ - write32rb (MEMC_BASE + MSC0_OFFSET), CONFIG_SYS_MSC0_VAL - /* MSC1: nCS(2,3) */ - write32rb (MEMC_BASE + MSC1_OFFSET), CONFIG_SYS_MSC1_VAL - /* MSC2: nCS(4,5) */ - write32rb (MEMC_BASE + MSC2_OFFSET), CONFIG_SYS_MSC2_VAL - - /* -* 2) Initialize Card Interface
[U-Boot] [PATCH 01/11] arm/pxa: remove unused u-boot.lds from board/vpac270
This file is not used, automatically generated u-boot.lds is used instead
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
board/vpac270/u-boot.lds | 55 --
1 files changed, 0 insertions(+), 55 deletions(-)
delete mode 100644 board/vpac270/u-boot.lds
diff --git a/board/vpac270/u-boot.lds b/board/vpac270/u-boot.lds
deleted file mode 100644
index 58c371d..000
--- a/board/vpac270/u-boot.lds
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT(elf32-littlearm, elf32-littlearm, elf32-littlearm)
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- cpu/pxa/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
--
1.7.1
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[U-Boot] [PATCH 04/11] arm/pxa: cleanup vpac270 config and set CONFIG_SYS_HZ to 1000
* CONFIG_SYS_CLKS_IN_HZ is not used anywhere, so removing it * CONFIG_SYS_HZ is set to 1000 on most architectures, so it seems to be the safe default Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index e31b08a..4c162bd 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -151,8 +151,7 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ -#defineCONFIG_SYS_HZ 325 /* Timer @ 325 Hz */ +#defineCONFIG_SYS_HZ 1000/* Timer @ 325 Hz */ #define CONFIG_SYS_CPUSPEED0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ /* -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 03/11] arm/pxa: enable stuart/btuart for vpac270
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
include/configs/vpac270.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index d3e22d9..e31b08a 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -62,7 +62,10 @@
* Serial Console Configuration
*/
#defineCONFIG_PXA_SERIAL
+#defineCONFIG_SERIAL_MULTI
#defineCONFIG_FFUART 1
+#defineCONFIG_STUART 1
+#defineCONFIG_BTUART 1
#defineCONFIG_BAUDRATE 115200
#defineCONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600,
115200 }
--
1.7.1
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[U-Boot] [PATCH 02/11] arm/pxa: fix board/vpac270/vpac270.c compilation if usb support is disabled
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
board/vpac270/vpac270.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c
index 18e47e2..2f29cf4 100644
--- a/board/vpac270/vpac270.c
+++ b/board/vpac270/vpac270.c
@@ -73,6 +73,7 @@ int dram_init (void)
return 0;
}
+#ifdef CONFIG_CMD_USB
int usb_board_init(void)
{
UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL)
@@ -119,6 +120,7 @@ void usb_board_stop(void)
return;
}
+#endif
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
--
1.7.1
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[U-Boot] [PATCH 06/11] arm/pxa: remove CONFIG_ENV_OVERWRITE from vpac270 config
it is not required and not recommended. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index d3e805a..c8663e8 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -40,8 +40,6 @@ #defineCONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) #defineCONFIG_SYS_GBL_DATA_SIZE128 -#defineCONFIG_ENV_OVERWRITE/* override default environment */ - #defineCONFIG_BOOTCOMMAND \ if mmc init fatload mmc 0 0xa400 uImage; then \ bootm 0xa400; \ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 05/11] arm/pxa: fix environment location/length for vpac270 and related bugs.
Define MONITOR_BASE on the base of used flash type. Define ENV_ADDR as MONITOR_BASE + MONITOR_LEN. Fix environment sector size (NOR: 32Kb for first four sectors and 128Kb for other; OneNAND: 128Kb). Last but not least: we have MONITOR_LEN = 0x4, one sector for environment and one sector for its redundancy copy (2 * 0x2 = 256Kb). So the kernel may start from 0x0008 only. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h | 10 ++ 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 4c162bd..d3e805a 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -49,7 +49,7 @@ if usb reset fatload usb 0 0xa400 uImage; then \ bootm 0xa400; \ fi; \ - bootm 0x4; + bootm 0x0008; #defineCONFIG_BOOTARGS console=tty0 console=ttyS0,115200 #defineCONFIG_TIMESTAMP #defineCONFIG_BOOTDELAY2 /* Autoboot delay */ @@ -188,6 +188,7 @@ #ifdefined(CONFIG_CMD_FLASH) /* NOR */ #definePHYS_FLASH_10x /* Flash Bank #1 */ #definePHYS_FLASH_20x0200 /* Flash Bank #2 */ +#defineCONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 #defineCONFIG_SYS_FLASH_CFI #defineCONFIG_FLASH_CFI_DRIVER 1 @@ -207,18 +208,19 @@ #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #defineCONFIG_SYS_NO_FLASH #defineCONFIG_SYS_ONENAND_BASE 0x +#defineCONFIG_SYS_MONITOR_BASE CONFIG_SYS_ONENAND_BASE #defineCONFIG_ENV_IS_IN_ONENAND1 #else /* No flash */ #defineCONFIG_SYS_NO_FLASH #defineCONFIG_SYS_ENV_IS_NOWHERE +#defineCONFIG_SYS_MONITOR_BASE 0x00 #endif -#defineCONFIG_SYS_MONITOR_BASE 0x00 #defineCONFIG_SYS_MONITOR_LEN 0x4 -#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x4 +#define CONFIG_ENV_ADDR(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x2 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 08/11] arm/pxa: increase CONFIG_SYS_MALLOC_LEN to (196Kb + space for environment)
it looks like u-boot allocates a buffer of CONFIG_ENV_SECT_SIZE size when making saveenv command. In our case CONFIG_ENV_SECT_SIZE is 128Kb, so having CONFIG_SYS_MALLOC_LEN = (128Kb + space for environment) is not sufficient. Increase CONFIG_SYS_MALLOC_LEN to (196Kb + space for environment) to resolve a problem. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 98faf9a..ddb3e0e 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -37,7 +37,7 @@ * Environment settings */ #defineCONFIG_ENV_SIZE (4 * 1024) -#defineCONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#defineCONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 196*1024) #defineCONFIG_SYS_GBL_DATA_SIZE128 #defineCONFIG_BOOTCOMMAND \ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 07/11] arm/pxa: decrease environment size and stack size for vpac270
it looks like 4Kb for environment and 64Kb for stack is sufficient Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index c8663e8..98faf9a 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -36,7 +36,7 @@ /* * Environment settings */ -#defineCONFIG_ENV_SIZE 0x4000 +#defineCONFIG_ENV_SIZE (4 * 1024) #defineCONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) #defineCONFIG_SYS_GBL_DATA_SIZE128 @@ -157,7 +157,7 @@ * * The stack sizes are set up in start.S using the settings below */ -#defineCONFIG_STACKSIZE(128*1024) /* regular stack */ +#defineCONFIG_STACKSIZE(64*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ #defineCONFIG_STACKSIZE_IRQ(4*1024)/* IRQ stack */ #defineCONFIG_STACKSIZE_FIQ(4*1024)/* FIQ stack */ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 09/11] arm/pxa: fix number of cfi flashes in vpac270
This board have only one CFI flash actually, so fix it in config.
PS: This patch should not go upstream at this point as it specific
to my revision of voipac
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
include/configs/vpac270.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index ddb3e0e..c92eb40 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -192,8 +192,8 @@
#defineCONFIG_FLASH_CFI_DRIVER 1
#defineCONFIG_SYS_MAX_FLASH_SECT (4 + 255)
-#defineCONFIG_SYS_MAX_FLASH_BANKS 2
-#defineCONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 }
+#defineCONFIG_SYS_MAX_FLASH_BANKS 1
+#defineCONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#defineCONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ)
#defineCONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ)
--
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[U-Boot] [PATCH 10/11] arm/pxa: fix sdram memory layout for vpac270
The board have only 128 Mb of memory and only two first memory banks are used. Also remove unneeded CONFIG_SYS_DRAM_SIZE constant and set default load address to be in sdram. PS: This patch should not go upstream at this point as it specific to my revision of voipac Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h | 17 ++--- 1 files changed, 10 insertions(+), 7 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index c92eb40..b04d1e8 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -166,19 +166,22 @@ /* * DRAM Map */ -#defineCONFIG_NR_DRAM_BANKS2 /* We have 2 banks of DRAM */ -#definePHYS_SDRAM_10xa000 /* SDRAM Bank #1 */ -#definePHYS_SDRAM_1_SIZE 0x0800 /* 128 MB */ -#definePHYS_SDRAM_20x8000 /* SDRAM Bank #2 */ -#definePHYS_SDRAM_2_SIZE 0x0800 /* 128 MB */ +#defineCONFIG_NR_DRAM_BANKS4 /* We have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x0400 /* 64 MB */ +#define PHYS_SDRAM_2 0xa400 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x0400 /* 64 MB */ +#define PHYS_SDRAM_3 0xa800 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x /* 0 MB */ +#define PHYS_SDRAM_4 0xac00 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x /* 0 MB */ #defineCONFIG_SYS_DRAM_BASE0xa000 /* CS0 */ -#defineCONFIG_SYS_DRAM_SIZE0x1000 /* 256 MB DRAM */ #define CONFIG_SYS_MEMTEST_START 0xa040 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa080 /* 4 ... 8 MB in DRAM */ -#defineCONFIG_SYS_LOAD_ADDR(0x5c00) +#defineCONFIG_SYS_LOAD_ADDR0xa000 /* * NOR FLASH -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 11/11] arm/pxa: fix and cleanup of pxa_mem_setup macro v2
WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE, K1RUN, K2RUN and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan to use this macro should check the validity of their MDREFR values. v1: * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks. v2: * rename pxa_mem_setup macro to pxa2xx_mem_setup * setting of MDREFR[K1RUN] and MDREFR[K2RUN] bits may be optional * skip certain configuration steps if SDRAM is not present/configured * improve/fix comments PS: This patch should not go upstream at this point as it require more work. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- arch/arm/include/asm/arch-pxa/macro.h | 78 +--- board/vpac270/lowlevel_init.S |2 +- 2 files changed, 52 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 035a57e..468482a 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,11 +102,15 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_dev_man.pdf */ -.macro pxa_mem_setup +.macro pxa2xx_mem_setup /* This comes handy when setting MDREFR */ ldr r3, =MEMC_BASE + ldr r7, =CONFIG_SYS_MDREFR_VAL /* * 1) Initialize Asynchronous static memory controller @@ -149,51 +153,66 @@ */ /* -* Before accessing MDREFR we need a valid DRI field, so we set -* this to power on defaults + DRI field. +* Before accessing MDREFR we need a valid DRI field. +* Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. +* Optionaly we can set MDREFR[KxFREE] bits. +* So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) +* fields from the config. +* +* WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits +* are usually unset. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ - - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 | \ + MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD - bic r5, #MDREFR_E1PIN + + /* enable them later, if SDRAM is present */ + bic r5, #( MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* Initialize SXCNFG register. Assert the enable bits. -* -* Write SXMRS to cause an MRS command to all enabled banks of -* synchronous static memory. Note that SXLCR need not be written -* at this time. + /* Initialize SXCNFG register to enable synchronous flash memory. +* While the synchronous flash banks are being configured, the SDRAM +* banks must be disabled and MDREFR[APD] must be de-asserted. */ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* -* 6) Initialize SDRAM +* 6) Initialize SDRAM, +*If SDRAM present, then MDREFR[K1RUN] and/or MDREFR[K2RUN] bits +*must be set. Also we must properly configure MDREFR[K1DB2] and +*MDREFR[K2DB2] in this case. +* +*WARNING: K1DB2 and K2DB2 bits are usually set if SDRAM present */ + and r4, r7, #( MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r6, [r3, #MDREFR_OFFSET] + orr r6, r6, r4 + str r6, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] + bic r6, #MDREFR_SLFRSH str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET
[U-Boot] [PATCH 6/8] arm/pxa: increase CONFIG_SYS_MALLOC_LEN to (196Kb + space for environment) (v.2)
it looks like u-boot allocates a buffer of CONFIG_ENV_SECT_SIZE size when making saveenv command. In our case CONFIG_ENV_SECT_SIZE is 128Kb, so having CONFIG_SYS_MALLOC_LEN = 128Kb is not sufficient. Increase CONFIG_SYS_MALLOC_LEN to (196Kb + space for environment) to resolve a problem. v2: rebased against for-wd-master branch Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index bd1b0f6..3ca25bf 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -32,7 +32,7 @@ * Environment settings */ #defineCONFIG_ENV_OVERWRITE -#defineCONFIG_SYS_MALLOC_LEN (128*1024) +#defineCONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 196*1024) #defineCONFIG_SYS_GBL_DATA_SIZE128 #defineCONFIG_BOOTCOMMAND \ -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 4/8] arm/pxa: fix environment sector size, kernel and environment location for vpac270 (v.2)
Define ENV_ADDR as MONITOR_BASE + MONITOR_LEN. Fix environment sector size (NOR: 32Kb for first four sectors and 128Kb for other; OneNAND: 128Kb). Last but not least: we have MONITOR_LEN = 0x4 and one sector for environment (size = 0x2), so the kernel may start from 0x0006 only. v2: rebased against for-wd-master branch Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h | 11 --- 1 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index eb2dc93..c81d567 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -45,7 +45,7 @@ if ide reset fatload ide 0 0xa400 uImage; then \ bootm 0xa400; \ fi; \ - bootm 0x4; + bootm 0x6; #defineCONFIG_BOOTARGS console=tty0 console=ttyS0,115200 #defineCONFIG_TIMESTAMP #defineCONFIG_BOOTDELAY2 /* Autoboot delay */ @@ -214,7 +214,12 @@ #defineCONFIG_SYS_FLASH_PROTECTION 1 #defineCONFIG_ENV_IS_IN_FLASH 1 -#defineCONFIG_ENV_SECT_SIZE0x4000 + +/* + * if (CONFIG_SYS_MONITOR_LEN = 0x18000) CONFIG_ENV_SECT_SIZE = 0x8000; + * else CONFIG_ENV_SECT_SIZE = 0x2 + */ +#defineCONFIG_ENV_SECT_SIZE0x2 #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #defineCONFIG_SYS_NO_FLASH @@ -231,7 +236,7 @@ #defineCONFIG_SYS_MONITOR_BASE 0x0 #defineCONFIG_SYS_MONITOR_LEN 0x4 -#defineCONFIG_ENV_ADDR 0x4 +#defineCONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #defineCONFIG_ENV_SIZE 0x4000 /* -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/8] (RESEND) arm/pxa: enable stuart/btuart for vpac270
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
include/configs/vpac270.h |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index 694a8f9..1e4d4c5 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -58,7 +58,10 @@
* Serial Console Configuration
*/
#defineCONFIG_PXA_SERIAL
+#defineCONFIG_SERIAL_MULTI
#defineCONFIG_FFUART 1
+#defineCONFIG_STUART 1
+#defineCONFIG_BTUART 1
#defineCONFIG_BAUDRATE 115200
#defineCONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600,
115200 }
--
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[U-Boot] [PATCH 7/8] arm/pxa: fix MDREFR[APD] bit setting
pxa_mem_setup macro use r6 to store CONFIG_SYS_MDREFR_VAL during memory initialization. This reg is modified during execution of pxa_wait_ticks. Later we use r6 to setup MDREFR[APD] bit. As result MDREFR[APD] is always zero. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- arch/arm/include/asm/arch-pxa/macro.h | 20 1 files changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 035a57e..5a480fd 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,7 +102,11 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE + * and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not + * use this regs for other purpose inside this macro. + * + * Clobbered regs: r3, r4, r5, r6, r7 */ .macro pxa_mem_setup /* This comes handy when setting MDREFR */ @@ -157,7 +161,7 @@ bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 + mov r7, r4 lsl r4, #20 lsr r4, #20 /* Get a valid DRI field */ @@ -187,12 +191,12 @@ * 6) Initialize SDRAM */ - bic r6, #MDREFR_SLFRSH - str r6, [r3, #MDREFR_OFFSET] + bic r7, #MDREFR_SLFRSH + str r7, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] - orr r6, #MDREFR_E1PIN - str r6, [r3, #MDREFR_OFFSET] + orr r7, #MDREFR_E1PIN + str r7, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] /* @@ -250,8 +254,8 @@ */ ldr r4, [r3, #MDREFR_OFFSET] - and r6, r6, #MDREFR_APD - orr r4, r4, r6 + and r7, r7, #MDREFR_APD + orr r4, r4, r7 str r4, [r3, #MDREFR_OFFSET] ldr r4, [r3, #MDREFR_OFFSET] .endm -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/8] arm/pxa: cleanup vpac270 config and set CONFIG_SYS_HZ to 1000 (v.2)
* CONFIG_SYS_CLKS_IN_HZ is not used anywhere, so removing it * CONFIG_SYS_HZ is set to 1000 on most architectures, so it seems to be the safe default v2: rebased against for-wd-master branch Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 1e4d4c5..eb2dc93 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -149,8 +149,7 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ -#defineCONFIG_SYS_HZ 325 /* Timer @ 325 Hz */ +#defineCONFIG_SYS_HZ 1000/* Timer @ 325 Hz */ #defineCONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ /* -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/8] (RESEND) arm/pxa: remove unused u-boot.lds from board/vpac270
This file is not used, automatically generated u-boot.lds is used instead
Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com
---
board/vpac270/u-boot.lds | 55 --
1 files changed, 0 insertions(+), 55 deletions(-)
delete mode 100644 board/vpac270/u-boot.lds
diff --git a/board/vpac270/u-boot.lds b/board/vpac270/u-boot.lds
deleted file mode 100644
index 58c371d..000
--- a/board/vpac270/u-boot.lds
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_FORMAT(elf32-littlearm, elf32-littlearm, elf32-littlearm)
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
- . = 0x;
-
- . = ALIGN(4);
- .text :
- {
- cpu/pxa/start.o (.text)
- *(.text)
- }
-
- . = ALIGN(4);
- .rodata : { *(.rodata) }
-
- . = ALIGN(4);
- .data : { *(.data) }
-
- . = ALIGN(4);
- .got : { *(.got) }
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
- . = ALIGN(4);
- __bss_start = .;
- .bss : { *(.bss) }
- _end = .;
-}
--
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[U-Boot] [PATCH 5/8] arm/pxa: decrease environment size and stack size for vpac270 (v.2)
it looks like 4Kb for environment and 64Kb for stack is sufficient v2: rebased against for-wd-master branch Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- include/configs/vpac270.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index c81d567..bd1b0f6 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -155,7 +155,7 @@ /* * Stack sizes */ -#defineCONFIG_STACKSIZE(128*1024) /* regular stack */ +#defineCONFIG_STACKSIZE(64*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ #defineCONFIG_STACKSIZE_IRQ(4*1024)/* IRQ stack */ #defineCONFIG_STACKSIZE_FIQ(4*1024)/* FIQ stack */ @@ -237,7 +237,7 @@ #defineCONFIG_SYS_MONITOR_LEN 0x4 #defineCONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#defineCONFIG_ENV_SIZE 0x4000 +#defineCONFIG_ENV_SIZE (4 * 1024) /* * IDE -- 1.7.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 8/8] arm/pxa: fix and cleanup of pxa_mem_setup macro (v.3)
WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE, K1RUN, K2RUN and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan v1: * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks. v2: * rename pxa_mem_setup macro to pxa2xx_mem_setup * setting of MDREFR[K1RUN] and MDREFR[K2RUN] bits may be optional * skip certain configuration steps if SDRAM is not present/configured * improve/fix comments v3: * move fixing of MDREFR[APD] bit setting to separate patch * revert skip certain configuration steps if SDRAM is not present/configured * improve/fix comments PS: This patch is for review only, it should not go upstream at this point. --- arch/arm/include/asm/arch-pxa/macro.h | 84 + 1 files changed, 54 insertions(+), 30 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 5a480fd..410e90b 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -107,10 +107,14 @@ * use this regs for other purpose inside this macro. * * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_dev_man.pdf */ .macro pxa_mem_setup /* This comes handy when setting MDREFR */ ldr r3, =MEMC_BASE + ldr r7, =CONFIG_SYS_MDREFR_VAL /* * 1) Initialize Asynchronous static memory controller @@ -153,51 +157,66 @@ */ /* -* Before accessing MDREFR we need a valid DRI field, so we set -* this to power on defaults + DRI field. +* Before accessing MDREFR we need a valid DRI field. +* Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. +* Optionaly we can set MDREFR[KxFREE] bits. +* So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) +* fields from the config. +* +* WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits +* are usually unset. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r7, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ - - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 | \ + MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD - bic r5, #MDREFR_E1PIN + + /* enable them later, if SDRAM is present */ + bic r5, #( MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* Initialize SXCNFG register. Assert the enable bits. -* -* Write SXMRS to cause an MRS command to all enabled banks of -* synchronous static memory. Note that SXLCR need not be written -* at this time. + /* Initialize SXCNFG register to enable synchronous flash memory. +* While the synchronous flash banks are being configured, the SDRAM +* banks must be disabled and MDREFR[APD] must be de-asserted. */ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* -* 6) Initialize SDRAM +* 6) Initialize SDRAM, +*If SDRAM present, then MDREFR[K1RUN] and/or MDREFR[K2RUN] bits +*must be set. Also we must properly configure MDREFR[K1DB2] and +*MDREFR[K2DB2] in this case. +* +*WARNING: K1DB2 and K2DB2 bits are usually set if SDRAM present */ - bic r7, #MDREFR_SLFRSH - str r7, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + and r4, r7, #( MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r6, [r3, #MDREFR_OFFSET] + orr r6, r6, r4 + str r6, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] - orr r7, #MDREFR_E1PIN - str r7, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + bic
[U-Boot] [PATCH] arm/pxa: fix and cleanup of pxa_mem_setup macro v2
WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE, K1RUN, K2RUN and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan to use this macro should check the validity of their MDREFR values. v1: * strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks. v2: * rename pxa_mem_setup macro to pxa2xx_mem_setup * setting of MDREFR[K1RUN] and MDREFR[K2RUN] bits may be optional * skip certain configuration steps if SDRAM is not present/configured * improve/fix comments Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- arch/arm/include/asm/arch-pxa/macro.h | 82 ++--- board/vpac270/lowlevel_init.S |2 +- 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 1f1759b..e2ddfe9 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,11 +102,15 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_dev_man.pdf */ -.macro pxa_mem_setup +.macro pxa2xx_mem_setup /* This comes handy when setting MDREFR */ ldr r3, =MEMC_BASE + ldr r7, =CONFIG_SYS_MDREFR_VAL /* * 1) Initialize Asynchronous static memory controller @@ -149,51 +153,68 @@ */ /* -* Before accessing MDREFR we need a valid DRI field, so we set -* this to power on defaults + DRI field. +* Before accessing MDREFR we need a valid DRI field. +* Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. +* Optionaly we can set MDREFR[KxFREE] bits. +* So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) +* fields from the config. +* +* WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits +* are usually unset. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ - - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 | \ + MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD - bic r5, #MDREFR_E1PIN + + /* enable them later, if SDRAM is present */ + bic r5, #( MDREFR_E1PIN | MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* Initialize SXCNFG register. Assert the enable bits. -* -* Write SXMRS to cause an MRS command to all enabled banks of -* synchronous static memory. Note that SXLCR need not be written -* at this time. + /* Initialize SXCNFG register to enable synchronous flash memory. +* While the synchronous flash banks are being configured, the SDRAM +* banks must be disabled and MDREFR[APD] must be de-asserted. */ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* -* 6) Initialize SDRAM +* 6) Initialize SDRAM, +*If SDRAM present, then MDREFR[K1RUN] and/or MDREFR[K1RUN] bits +*must be set. Also we must properly configure MDREFR[K1DB2] and +*MDREFR[K2DB2] in this case. +* +*WARNING: K1DB2 and K2DB2 bits are usually set if SDRAM present */ +#if (CONFIG_SYS_MDREFR_VAL (MDREFR_K1RUN | MDREFR_K2RUN)) + and r4, r7, #( MDREFR_K1RUN | MDREFR_K2RUN | \ + MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r6, [r3, #MDREFR_OFFSET] + orr r6, r6, r4 + str r6, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] + bic r6, #MDREFR_SLFRSH str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r6, [r3, #MDREFR_OFFSET] orr r6
[U-Boot] [PATCH] arm/pxa-devel: fix and cleanup of pxa_mem_setup macro
* strict following to section 6.4.10 of Intel PXA27xx Developer's Manual. * use r7 to store CONFIG_SYS_MDREFR_VAL as r6 is used in pxa_wait_ticks WARNING: This macro do not assume the values for K0DB4, KxDB2, KxFREE and APD bits of CONFIG_SYS_MDREFR_VAL as it was done early on many pxa platforms. All pxa developers that plan to use this macro should check the validity of their MDREFR values. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- arch/arm/include/asm/arch-pxa/macro.h | 81 +++-- 1 files changed, 56 insertions(+), 25 deletions(-) diff --git a/arch/arm/include/asm/arch-pxa/macro.h b/arch/arm/include/asm/arch-pxa/macro.h index 1f1759b..26d7a8d 100644 --- a/arch/arm/include/asm/arch-pxa/macro.h +++ b/arch/arm/include/asm/arch-pxa/macro.h @@ -102,7 +102,11 @@ /* * This macro sets up the Memory controller of the PXA2xx CPU * - * Clobbered regs: r3, r4, r5 + * Clobbered regs: r3, r4, r5, r6, r7 + * + * See section 6.4.10 of Intel PXA2xx Processor Developer's Manual + * http://www.marvell.com/products/processors/applications/pxa_family/pxa_27x_dev_man.pdf + * http://www.marvell.com/products/processors/applications/pxa_family/PXA3xx_Developers_Manual.zip */ .macro pxa_mem_setup /* This comes handy when setting MDREFR */ @@ -149,27 +153,38 @@ */ /* -* Before accessing MDREFR we need a valid DRI field, so we set -* this to power on defaults + DRI field. +* Before accessing MDREFR we need a valid DRI field. +* Also we must properly configure MDREFR[K0DB2] and MDREFR[K0DB4]. +* Optionaly we can set MDREFR[KxFREE] bits. +* So we set MDREFR to power on defaults + (DRI, K0DB2, K0DB4, KxFREE) +* fields from the config. +* +* WARNING: K0DB2 and K0DB4 bits are usually set, while KxFREE bits +* are usually unser. */ ldr r5, [r3, #MDREFR_OFFSET] - bic r5, r5, #0x0ff - bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */ - - ldr r4, =CONFIG_SYS_MDREFR_VAL - mov r6, r4 - lsl r4, #20 - lsr r4, #20 /* Get a valid DRI field */ + ldr r4, =( 0xFFF | MDREFR_K0DB4 | MDREFR_K0DB2 ) + orr r4, #( MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE ) + bic r5, r5, r4 /* clear DRI, K0DB2, K0DB4, KxFREE fields */ - orr r5, r5, r4 /* MDREFR user config with correct DRI */ + /* +* r3 is busy with MEMC_BASE, +* r4, r5, r6 used in pxa_wait_ticks and other places, +* so use r7 to store user specified MDREFR_VAL +*/ + ldr r7, =CONFIG_SYS_MDREFR_VAL + and r4, r7, r4 + orr r5, r5, r4 /* use custom DRI, K0DB2, K0DB4, KxFREE */ orr r5, #MDREFR_K0RUN orr r5, #MDREFR_SLFRSH bic r5, #MDREFR_APD bic r5, #MDREFR_E1PIN + bic r5, #MDREFR_K1RUN + bic r5, #MDREFR_K2RUN str r5, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 5) Initialize Synchronous Static Memory (Flash/Peripherals) @@ -184,16 +199,29 @@ write32rb (MEMC_BASE + SXCNFG_OFFSET), CONFIG_SYS_SXCNFG_VAL /* -* 6) Initialize SDRAM +* 6) Initialize SDRAM, +*also we must properly set MDREFR[K1DB2] and MDREFR[K2DB2] +* +*WARNING: K1DB2 and K2DB2 bits are usually set */ - bic r6, #MDREFR_SLFRSH - str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + and r4, r7, #( MDREFR_K1DB2 | MDREFR_K2DB2 ) + ldr r5, [r3, #MDREFR_OFFSET] + bic r5, #( MDREFR_K1DB2 | MDREFR_K2DB2 ) + orr r5, r5, r4 - orr r6, #MDREFR_E1PIN - str r6, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + orr r5, #MDREFR_K1RUN + orr r5, #MDREFR_K2RUN + str r5, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] + + bic r5, #MDREFR_SLFRSH + str r5, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] + + orr r5, #MDREFR_E1PIN + str r5, [r3, #MDREFR_OFFSET] + ldr r5, [r3, #MDREFR_OFFSET] /* * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure @@ -246,14 +274,17 @@ ldr r4, [r3, #MDMRS_OFFSET] /* -* 11) Enable APD +* 11) Optionaly enable MDREFR[APD] +* +* WARNING: APD bit is usually set. */ - ldr r4, [r3, #MDREFR_OFFSET] - and r6, r6, #MDREFR_APD - orr r4, r4, r6 - str r4, [r3, #MDREFR_OFFSET] - ldr r4, [r3, #MDREFR_OFFSET] + and r7, #MDREFR_APD + ldr r5, [r3, #MDREFR_OFFSET] + bic r5
Re: [U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
Dear Wolfgang Denk, Here is my comments to your notices, the updated patch is in the following letter. On Tue, 30 Mar 2010 23:15:45 +0200 Wolfgang Denk w...@denx.de wrote: Dear Mikhail Kshevetskiy, In message 20100329162420.40f54...@laska.campus-ws.pu.ru you wrote: This patch is based on custom u-boot-1.1.2 version produced by voipac (http://www.voipac.com) and board/trizepsiv files from current u-boot. Up to now only PXA270 DIMM module with NOR flash is tested. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- Makefile |3 + board/vpac270/Makefile| 51 +++ board/vpac270/config.mk |3 + board/vpac270/lowlevel_init.S | 740 + board/vpac270/vpac270.c | 101 ++ include/configs/vpac270.h | 329 ++ 6 files changed, 1227 insertions(+), 0 deletions(-) create mode 100644 board/vpac270/Makefile create mode 100644 board/vpac270/config.mk create mode 100644 board/vpac270/lowlevel_init.S create mode 100644 board/vpac270/vpac270.c create mode 100644 include/configs/vpac270.h Entries to MAKEALL and MAINTAINERS missing. fixed diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk new file mode 100644 index 000..4486f6b --- /dev/null +++ b/board/vpac270/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f0 +# 0xa170 +#TEXT_BASE = 0 Please do not add dead code. Remove it. fixed diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S new file mode 100644 index 000..1df381c ... +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm Indentation and vertial alignment by TAB only. Please fix globally. fixed, I try to keep lowlevel_init.S as much close to the same file from board/trizeptiv as it was possible, so initially i keep formatting and comments style from the upstream version of board/trizeptiv/lowlevel_init.S. + /* Set up GPIO pins first - */ + + ldr r0, =GPSR0 + ldr r1, =CONFIG_SYS_GPSR0_VAL + str r1, [r0] One TAB between instruction and arguments should be sufficient. same as above + /* */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps*/ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* */ Incorrect multiline comment style. Please fix globally. same as above ... + /* MECR: Memory Expansion Card Register */ + ldr r2, =CONFIG_SYS_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] Inconsistent indentation - please fix globally. same as above + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CONFIG_SYS_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CONFIG_SYS_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0*/ + ldr r2, =CONFIG_SYS_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1*/ + ldr r2, =CONFIG_SYS_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CONFIG_SYS_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CONFIG_SYS_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* */ + /* Step 2c: Write FLYCNFG FIXME: what's that???*/ + /* */ +@ ldr r2, =CONFIG_SYS_FLYCNFG_VAL +@ str r2, [r1, #FLYCNFG_OFFSET] +@ str r2, [r1, #FLYCNFG_OFFSET] + + /* */ + /* Step 2d: Initialize Timing for Sync Memory
[U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac [rev 2]
This patch is based on custom u-boot-1.1.2 version produced by voipac (http://www.voipac.com) and board/trizepsiv files from current u-boot. Up to now only PXA270 DIMM module with NOR flash is tested. v2: code style was improved Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- MAINTAINERS |4 + MAKEALL |1 + Makefile |3 + board/vpac270/Makefile| 51 +++ board/vpac270/config.mk |1 + board/vpac270/lowlevel_init.S | 735 + board/vpac270/vpac270.c | 103 ++ include/configs/vpac270.h | 408 +++ 8 files changed, 1306 insertions(+), 0 deletions(-) create mode 100644 board/vpac270/Makefile create mode 100644 board/vpac270/config.mk create mode 100644 board/vpac270/lowlevel_init.S create mode 100644 board/vpac270/vpac270.c create mode 100644 include/configs/vpac270.h diff --git a/MAINTAINERS b/MAINTAINERS index 80057ce..f84b6f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -525,6 +525,10 @@ Stefano Babic sba...@denx.de polaris xscale trizepsiv xscale +Mikhail Kshevetskiy mikhail.kshevets...@gmail.com + + vpac270 xscale + Dirk Behme dirk.be...@gmail.com omap3_beagleARM CORTEX-A8 (OMAP3530 SoC) diff --git a/MAKEALL b/MAKEALL index 5c303f9..78ba2af 100755 --- a/MAKEALL +++ b/MAKEALL @@ -692,6 +692,7 @@ LIST_pxa= \ polaris \ pxa255_idp \ trizepsiv \ + vpac270 \ wepep250\ xaeniax \ xm250 \ diff --git a/Makefile b/Makefile index e141cb2..20cceba 100644 --- a/Makefile +++ b/Makefile @@ -3250,6 +3250,9 @@ trizepsiv_config : unconfig fi; @$(MKCONFIG) -a trizepsiv arm pxa trizepsiv +vpac270_config:unconfig + @$(MKCONFIG) $(@:_config=) arm pxa vpac270 + wepep250_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile new file mode 100644 index 000..500e075 --- /dev/null +++ b/board/vpac270/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := vpac270.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk new file mode 100644 index 000..e798bc3 --- /dev/null +++ b/board/vpac270/config.mk @@ -0,0 +1 @@ +TEXT_BASE =0xa1f0 diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S new file mode 100644 index 000..3e8bb5b --- /dev/null +++ b/board/vpac270/lowlevel_init.S @@ -0,0 +1,735 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even
[U-Boot] [PATCH 1/2] improve printf behavior on arm/pxa after enabling 64bit support in printf by default.
commit 4b142febff71eabdb7ddbb125c7b583b24ddc434 (common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL) breaks printf on my arm/pxa270 board. For example, the code int a = 128; printf(a= %d\n, a); will print zero on the console. The problem reproduced on gcc 4.1.1, 4.3.3, 4.4.1 and 4.4.2. This patch fix printf unless you'll need printing 64-bit values. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- cpu/pxa/config.mk |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk index a05d69c..d87b5e0 100644 --- a/cpu/pxa/config.mk +++ b/cpu/pxa/config.mk @@ -24,7 +24,7 @@ PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale +PLATFORM_CPPFLAGS += -march=armv5t -mtune=xscale # = # # Supply options according to compiler version -- 1.7.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] add support of arm/pxa270 board made by voipac
This patch is based on custom u-boot-1.1.2 version produced by voipac (http://www.voipac.com) and board/trizepsiv files from current u-boot. Up to now only PXA270 DIMM module with NOR flash is tested. Signed-off-by: Mikhail Kshevetskiy mikhail.kshevets...@gmail.com --- Makefile |3 + board/vpac270/Makefile| 51 +++ board/vpac270/config.mk |3 + board/vpac270/lowlevel_init.S | 740 + board/vpac270/vpac270.c | 101 ++ include/configs/vpac270.h | 329 ++ 6 files changed, 1227 insertions(+), 0 deletions(-) create mode 100644 board/vpac270/Makefile create mode 100644 board/vpac270/config.mk create mode 100644 board/vpac270/lowlevel_init.S create mode 100644 board/vpac270/vpac270.c create mode 100644 include/configs/vpac270.h diff --git a/Makefile b/Makefile index d801e25..188d618 100644 --- a/Makefile +++ b/Makefile @@ -3253,6 +3253,9 @@ trizepsiv_config : unconfig fi; @$(MKCONFIG) -a trizepsiv arm pxa trizepsiv +vpac270_config:unconfig + @$(MKCONFIG) $(@:_config=) arm pxa vpac270 + wepep250_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile new file mode 100644 index 000..500e075 --- /dev/null +++ b/board/vpac270/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).a + +COBJS := vpac270.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk new file mode 100644 index 000..4486f6b --- /dev/null +++ b/board/vpac270/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f0 +# 0xa170 +#TEXT_BASE = 0 diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S new file mode 100644 index 000..1df381c --- /dev/null +++ b/board/vpac270/lowlevel_init.S @@ -0,0 +1,740 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include config.h +#include version.h +#include asm/arch/pxa-regs.h + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first - */ + + ldr r0, =GPSR0 + ldr
