Re: [U-Boot] [PATCH 1/4] arm64: ls1043ardb: Add sd_bootcmd for distro fallback in case of sdboot
> -Original Message- > From: York Sun > Sent: Tuesday, October 31, 2017 2:45 AM > To: Mingkai Hu > Cc: Shengzhou Liu ; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH 1/4] arm64: ls1043ardb: Add sd_bootcmd for > distro fallback in case of sdboot > > On 10/23/2017 01:53 PM, York Sun wrote: > > On 09/14/2017 02:26 PM, York Sun wrote: > >> On 08/30/2017 03:43 AM, Shengzhou Liu wrote: > >>> Signed-off-by: Shengzhou Liu > >>> --- > >>> include/configs/ls1043a_common.h | 11 ++- > >>> 1 file changed, 10 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/include/configs/ls1043a_common.h > >>> b/include/configs/ls1043a_common.h > >>> index f064d5c24a..976c031574 100644 > >>> --- a/include/configs/ls1043a_common.h > >>> +++ b/include/configs/ls1043a_common.h > >>> @@ -281,6 +281,8 @@ > >>> "fdt_addr_r=0x9000\0" \ > >>> "load_addr=0xa000\0"\ > >>> "kernel_size=0x280\0" \ > >>> + "kernel_addr_sd=0x8000\0" \ > >>> + "kernel_size_sd=0x14000\0" \ > >>> "console=ttyS0,115200\0"\ > >>> "mtdparts=" MTDPARTS_DEFAULT "\0" \ > >>> BOOTENV \ > >>> @@ -318,12 +320,19 @@ > >>> "$kernel_addr $kernel_size && bootm > $load_addr#$board\0" \ > >>> "nor_bootcmd=echo Trying load from nor..;" \ > >>> "cp.b $kernel_addr $load_addr " \ > >>> - "$kernel_size && bootm $load_addr#$board\0" > >>> + "$kernel_size && bootm $load_addr#$board\0" \ > >>> + "sd_bootcmd=echo Trying load from SD ..;" \ > >>> + "mmcinfo; mmc read $load_addr " \ > >>> + "$kernel_addr_sd $kernel_size_sd ;" \ > >>> + " bootm $load_addr#$board\0" > >>> > >> > >> Shouldn't you be using "&&" instead of ";" between commands? > >> > > > > Shengzhou, > > > > Are you going to update the patches? > > Mingkai, > > Do you need this change for LS1043ARDB? Please respond to my comment if > so. Otherwise, I will drop this set. > > York Hi York, This will be needed in order to keep consistent with our LSDK. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Powerpc: Make pcie link state judge more specific
> -Original Message- > From: York Sun > Sent: Tuesday, October 03, 2017 11:32 PM > To: Xiaowei Bao ; Mingkai Hu > > Cc: u-boot@lists.denx.de > Subject: Re: [PATCH] Powerpc: Make pcie link state judge more specific > > On 09/24/2017 08:44 PM, Bao Xiaowei wrote: > > For some special reset times for longer pcie devices, in this case, > > the pcie device may on polling compliance state, the RC considers the > > pcie device is link up, but the pcie device is not link up, only the > > L0 state is link up state. So add the link up status judgement mechanisms. > > > > Signed-off-by: Bao Xiaowei > > --- > > v2: > > - Detailed function module > > - Adjust the code structure > > Mingkai, > > Please ack if you agree with this change. > York, I had discussion with xiaowei and also posted the comments on the patch. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] Powerpc: Make pcie link state judge more specific
> -Original Message-
> From: Bao Xiaowei [mailto:xiaowei@nxp.com]
> Sent: Monday, September 25, 2017 11:27 AM
> To: M.h. Lian ; Z.q. Hou ;
> Mingkai Hu ; York Sun ;
> hamish.mar...@alliedtelesis.co.nz; w...@denx.de;
> tony.obr...@alliedtelesis.co.nz; u-boot@lists.denx.de
> Cc: Xiaowei Bao
> Subject: [PATCH] Powerpc: Make pcie link state judge more specific
>
> For some special reset times for longer pcie devices, in this case, the pcie
> device may on polling compliance state, the RC considers the pcie device is
> link up, but the pcie device is not link up, only the L0 state is link up
> state. So
> add the link up status judgement mechanisms.
>
> Signed-off-by: Bao Xiaowei
> ---
> v2:
> - Detailed function module
> - Adjust the code structure
>
I suggest to split this patch to two patches, one is for format change, another
one is for LTSSM change.
> arch/powerpc/include/asm/fsl_pci.h | 3 +
> drivers/pci/fsl_pci_init.c | 151
> -
> 2 files changed, 86 insertions(+), 68 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/fsl_pci.h
> b/arch/powerpc/include/asm/fsl_pci.h
> index cad341e..9dfbf19 100644
> --- a/arch/powerpc/include/asm/fsl_pci.h
> +++ b/arch/powerpc/include/asm/fsl_pci.h
> @@ -24,6 +24,9 @@
>
> #define PCI_LTSSM0x404 /* PCIe Link Training, Status State Machine */
> #define PCI_LTSSM_L00x16/* L0 state */
It's better to submit a patch to fix the leading space.
> +#define PCIE_GEN3_LTSSM_L0 0x11/* L0 state */
Follow the same name rule as PCI_LTSSM_L0? Like PCI_LTSSM_L0_PEX_REV3?
> +#define LTSSM_PCIE_DETECT_QUIET0x00 /* Detect state */
> +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* Detect state */
>
> int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int
> fsl_is_pci_agent(struct pci_controller *hose); diff --git
> a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index
> af20cf0..5d697bc
> 100644
> --- a/drivers/pci/fsl_pci_init.c
> +++ b/drivers/pci/fsl_pci_init.c
> @@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR; #if
> defined(CONFIG_SYS_PCI_64BIT)
> && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
> #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024) #endif
> +#define PEX_CSR0_LTSSM_MASK 0xFC
> +#define PEX_CSR0_LTSSM_SHIFT 2
>
> /* Setup one inbound ATMU window.
> *
> @@ -290,6 +292,81 @@ static void fsl_pcie_boot_master_release_slave(int
> port) } #endif
>
> +static int is_pcie_gen3(struct fsl_pci_info *pci_info) {
> + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
> + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
> + u32 block_rev;
> +
> + block_rev = in_be32(&pci->block_rev1);
> + if (block_rev >= PEX_IP_BLK_REV_3_0)
> + return 1;
> + else
> + return 0;
> +}
> +
As discussed, it's not related to gen3. It's related to PEX block version.
Please use
The PCIe controller version here.
> +static int get_ltssm_val(struct pci_controller *hose,
> + struct fsl_pci_info *pci_info)
> +{
> + u16 ltssm = 0;
> + pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
> + u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
> + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
> +
> + if (is_pcie_gen3(pci_info))
> + ltssm = (in_be32(&pci->pex_csr0)
> + & PEX_CSR0_LTSSM_MASK) >>
> PEX_CSR0_LTSSM_SHIFT;
> + else
> + pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
> +
> + return ltssm;
> +}
> +
> +static int pci_link_up(struct pci_controller *hose,
> + struct fsl_pci_info *pci_info)
> +{
> + int enabled = 0;
> + u16 ltssm;
> + int i, pcie_ltssm_l0;
> +
> + if (is_pcie_gen3(pci_info))
> + pcie_ltssm_l0 = PCIE_GEN3_LTSSM_L0;
> + else
> + pcie_ltssm_l0 = PCI_LTSSM_L0;
> +
> + ltssm = get_ltssm_val(hose, pci_info);
> + if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
> + ltssm == LTSSM_PCIE_DETECT_ACTIVE)
> + enabled = 0;
> + else if (ltssm == PCIE_GEN3_LTSSM_L0)
> + enabled = 1;
> + else {
> + for (i = 0; i < 100 && ltssm != pcie_ltssm_l0; i++) {
> + ltssm = get_ltssm_val(hose, pci_info);
> + udelay(1000);
> + }
> + enabled = (ltssm == pcie_ltssm_l0) ? 1 : 0;
> + }
> + return enabled;
> +}
> +
> +#if defined(CONFIG_FSL_PCIE_RE
Re: [U-Boot] [PATCH] FSL PCI: Configure PCIe reference ratio
> -Original Message-
> From: York Sun
> Sent: Friday, September 15, 2017 5:15 AM
> To: Joakim Tjernlund ; Mingkai Hu
> ; u-boot @ lists . denx . de ;
> Roy Zang
> Subject: Re: [PATCH] FSL PCI: Configure PCIe reference ratio
>
> On 09/12/2017 10:56 AM, Joakim Tjernlund wrote:
> > Most FSL PCIe controllers expects 333 MHz PCI reference clock.
> > This clock is derived from the CCB but in many cases the ref.
> > clock is not 333 MHz and a divisor needs to be configured.
> >
> > This adds PEX_CCB_DIV #define which can be defined for each type of
> > CPU/platform.
> >
> > Signed-off-by: Joakim Tjernlund
> > ---
> > drivers/pci/fsl_pci_init.c | 6 ++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
> > index 52792dcd59..4d00b3f26c 100644
> > --- a/drivers/pci/fsl_pci_init.c
> > +++ b/drivers/pci/fsl_pci_init.c
> > @@ -322,6 +322,12 @@ void fsl_pci_init(struct pci_controller *hose,
> > struct fsl_pci_info *pci_info)
> >
> > pci_setup_indirect(hose, cfg_addr, cfg_data);
> >
> > +#ifdef PEX_CCB_DIV
> > + /* Configure the PCIE controller core clock ratio */
> > + pci_hose_write_config_dword(hose, dev, 0x440,
> > + ((gd->bus_clk / 100) *
> > +(16 / PEX_CCB_DIV)) / 333);
> > +#endif
> > block_rev = in_be32(&pci->block_rev1);
> > if (PEX_IP_BLK_REV_2_2 <= block_rev) {
> > pi = &pci->pit[2]; /* 0xDC0 */
> >
>
> Mingkai,
>
> Do you ack this change? This presumes the PCIe clock derives from CCB bus
> clock.
>
gd->bus_clk indicates the platform clock while PCIe clock could be CCB or CCB/2.
For example, it's CCB/2 for T1040/T1020, CCB for P2020.
I suggest to add the PCIe clock in gd to handle this difference, just like what
we've done for other IP clocks.
Thanks,
Mingkai
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Re: [U-Boot] FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up
> -Original Message- > From: York Sun > Sent: Wednesday, September 06, 2017 11:37 PM > To: Joakim Tjernlund ; Mingkai Hu > > Cc: Xiaowei Bao ; u-boot@lists.denx.de > Subject: Re: FSL PCIe LTSSM >= PCI_LTSSM_L0 equals link up > > On 09/05/2017 04:08 AM, Joakim Tjernlund wrote: > > On Mon, 2017-08-28 at 17:14 +, York Sun wrote: > >> +Xiaowei > >> > >> On 08/28/2017 10:09 AM, Joakim Tjernlund wrote: > >>> On Mon, 2017-08-28 at 16:55 +, York Sun wrote: > >>>> On 08/28/2017 09:48 AM, Joakim Tjernlund wrote: > >>>>> FSL PCIe controller drivers before REV 3 has this test for link up: > >>>>> enabled = ltssm >= PCI_LTSSM_L0; > >>>>> > >>>>> We have a PCIe dev. that stays in LTSSM=0x51 (Polling Compliance) > >>>>> when non ready for PCI transaktions. When FSL PCIe controller > >>>>> tries to access this device, it hangs forever. > >>>>> > >>>>> Is LTSSM=0x51 really a "legal" state for link up? > >>>>> If not, what is a suitable range(maybe LO <= ltssm <= L0s(0x27)) ? > >>>>> > >>>>> Jocke > >>>>> > >>>>> BTW, the same test is valid in Linux too. > >>>>> > >>>> > >>>> Jocke, > >>>> > >>>> I am not an expert on PCIe. Please if this thread is helpful, > >>> > >>> Me neither .. :) > >>>> > >>>> > https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatc > hwork.ozlabs.org%2Fpatch%2F801519%2F&data=01%7C01%7Cyork.sun%40n > xp.com%7Cf46ff5111ba04e631a9b08d4ee377ecc%7C686ea1d3bc2b4c6fa92cd > 99c5c301635%7C0&sdata=n9%2B2NIjEvsMBCljRLHS6NVVN4ANa3nBGpwUjI4 > Od%2Bhs%3D&reserved=0. > >>> > >>> It mentions polling compliance but this driver already tests for: > >>> if (ltssm < LTSSM_PCIE_L0) > >>> return 0; > >>> return 1; > >>> > >>> It just adds some delay if the device is in Polling Compliance to > >>> see if that changes to L0. > >>> Since both layerscape and fsl >= rev 3 already require ltssm to be > >>> == L0, I suspect the ltssm >= L0 is bogus. > >>> > >> > >> Xiaowei, can you comment? > >> > >> York > > > > Ping? > > Should I just send a patch ? > > > > +Mingkai LTSSM should be L0 state for linkup. Xiaowei have the patch to modify the code for layerscape platform: http://patchwork.ozlabs.org/patch/801519/ He will work out a patch for PowerPC platform also. Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
> -Original Message- > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com] > Sent: Thursday, September 07, 2017 2:55 PM > To: Mingkai Hu ; Roy Zang ; > York Sun > Cc: u-boot@lists.denx.de > Subject: Re: setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ? > > On Thu, 2017-09-07 at 06:45 +, Mingkai Hu wrote: > > > -----Original Message- > > > From: Mingkai Hu > > > Sent: Wednesday, September 06, 2017 5:37 PM > > > To: 'Joakim Tjernlund' ; Roy Zang > > > ; York Sun > > > Cc: u-boot@lists.denx.de > > > Subject: RE: setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ? > > > > > > > > > > > > > -Original Message- > > > > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com] > > > > Sent: Tuesday, September 05, 2017 8:45 PM > > > > To: Mingkai Hu ; Roy Zang > ; > > > > > > York > > > > Sun > > > > Cc: u-boot@lists.denx.de > > > > Subject: Re: setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ? > > > > > > > > On Wed, 2017-08-30 at 15:25 +, York Sun wrote: > > > > > On 08/30/2017 06:05 AM, Joakim Tjernlund wrote: > > > > > > On Tue, 2017-08-29 at 17:33 +, York Sun wrote: > > > > > > > +Roy Zang to comment on PCIe clock source > > > > > > > > > > > > > > On 08/29/2017 10:06 AM, Joakim Tjernlund wrote: > > > > > > > > On Tue, 2017-08-29 at 15:43 +, York Sun wrote: > > > > > > > > > On 08/29/2017 06:21 AM, Joakim Tjernlund wrote: > > > > > > > > > > On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote: > > > > > > > > > > > As we are looking at PCI stuff ATM I would like to > > > > > > > > > > > ask about PEX_GCLK_RATIO in E500 CPUs. I cannot find > > > > > > > > > > > this is setup at all for E500 but I THINK this is > > > > > > > > > > > required. > > > > > > > > > > > > > > > > > > > > > > In 83xx one do: > > > > > > > > > > > get_clocks(); > > > > > > > > > > > /* Configure the PCIE controller core clock ratio */ > > > > > > > > > > > out_le32(hose_cfg_base + PEX_GCLK_RATIO, > > > > > > > > > > > > > > > > > > > > A bit strange with out_le32 instead of out_be32 ? > > > > > > > > > > > > > > > > > > > > > (((bus ? gd->arch.pciexp2_clk : > > > > > > > > > > > gd->arch.pciexp1_clk) / > > > > > > > > > > > 100) * 16) / 333); udelay(100); > > > > > > > > > > > > > > > > > > > > > > Any clues? > > > > > > > > > > > > > > > > > > > > > > Jocke > > > > > > > > > > > > > > > > > > > > Seems like only 83xx is setting this parameter. > > > > > > > > > > > > > > > > > > > > Anyhow, I put together this patch: > > > > > > > > > > > > > > > > > > > > --- a/drivers/pci/fsl_pci_init.c > > > > > > > > > > +++ b/drivers/pci/fsl_pci_init.c > > > > > > > > > > @@ -322,6 +322,10 @@ void fsl_pci_init(struct > > > > > > > > > > pci_controller *hose, struct fsl_pci_info *pci_info) > > > > > > > > > > > > > > > > > > > >pci_setup_indirect(hose, cfg_addr, > > > > > > > > > > cfg_data); > > > > > > > > > > > > > > > > > > > > + /* Configure the PCIE controller core clock ratio */ > > > > > > > > > > + pci_hose_write_config_dword(hose, dev, 0x440, > > > > > > > > > > + (gd- > > > > > > > > > > bus_clk / 3) * 16); > > > > > > > > > > + /* udelay(100) needed here ?*/ > > > > > > > > > > + > > > > > > > > > >block_rev = in_be32(&pci->block_rev1); > > > > > >
Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
> -Original Message-
> From: Mingkai Hu
> Sent: Wednesday, September 06, 2017 5:37 PM
> To: 'Joakim Tjernlund' ; Roy Zang
> ; York Sun
> Cc: u-boot@lists.denx.de
> Subject: RE: setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
>
>
>
> > -Original Message-
> > From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> > Sent: Tuesday, September 05, 2017 8:45 PM
> > To: Mingkai Hu ; Roy Zang ;
> York
> > Sun
> > Cc: u-boot@lists.denx.de
> > Subject: Re: setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
> >
> > On Wed, 2017-08-30 at 15:25 +, York Sun wrote:
> > > On 08/30/2017 06:05 AM, Joakim Tjernlund wrote:
> > > > On Tue, 2017-08-29 at 17:33 +, York Sun wrote:
> > > > > +Roy Zang to comment on PCIe clock source
> > > > >
> > > > > On 08/29/2017 10:06 AM, Joakim Tjernlund wrote:
> > > > > > On Tue, 2017-08-29 at 15:43 +, York Sun wrote:
> > > > > > > On 08/29/2017 06:21 AM, Joakim Tjernlund wrote:
> > > > > > > > On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote:
> > > > > > > > > As we are looking at PCI stuff ATM I would like to ask
> > > > > > > > > about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is
> > > > > > > > > setup at all for E500 but I THINK this is required.
> > > > > > > > >
> > > > > > > > > In 83xx one do:
> > > > > > > > > get_clocks();
> > > > > > > > > /* Configure the PCIE controller core clock ratio */
> > > > > > > > > out_le32(hose_cfg_base + PEX_GCLK_RATIO,
> > > > > > > >
> > > > > > > > A bit strange with out_le32 instead of out_be32 ?
> > > > > > > >
> > > > > > > > > (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk) /
> > > > > > > > > 100) * 16) / 333); udelay(100);
> > > > > > > > >
> > > > > > > > > Any clues?
> > > > > > > > >
> > > > > > > > > Jocke
> > > > > > > >
> > > > > > > > Seems like only 83xx is setting this parameter.
> > > > > > > >
> > > > > > > > Anyhow, I put together this patch:
> > > > > > > >
> > > > > > > > --- a/drivers/pci/fsl_pci_init.c
> > > > > > > > +++ b/drivers/pci/fsl_pci_init.c
> > > > > > > > @@ -322,6 +322,10 @@ void fsl_pci_init(struct
> > > > > > > > pci_controller *hose, struct fsl_pci_info *pci_info)
> > > > > > > >
> > > > > > > >pci_setup_indirect(hose, cfg_addr, cfg_data);
> > > > > > > >
> > > > > > > > + /* Configure the PCIE controller core clock ratio */
> > > > > > > > + pci_hose_write_config_dword(hose, dev, 0x440, (gd-
> > >bus_clk / 3) * 16);
> > > > > > > > + /* udelay(100) needed here ?*/
> > > > > > > > +
> > > > > > > >block_rev = in_be32(&pci->block_rev1);
> > > > > > > >if (PEX_IP_BLK_REV_2_2 <= block_rev) {
> > > > > > > >pi = &pci->pit[2]; /* 0xDC0 */
> > > > > > > >
> > > > > > > > Any chance this will work for all supported FSL PCIe
> > > > > > > > controllers?
> > > > > > > >
> > > > > > >
> > > > > > > Jocke,
> > > > > > >
> > > > > > > You don't need to program this register if the actual PCIe
> > > > > > > clock is the same as default. Since SerDes reference clock
> > > > > > > has to be 100MHz for PCIe protocol, my guess is the PCIe
> > > > > > > clock is always correct. The bus_clk you are referring is
> > > > > > > not the PCIe clock. Again, I am not a PCIe expert, I could
> > > > > > > be wrong. Since PCIe (SerDes) has been working on multiple
> > > > > > > platforms, I guess the
> > clock is correct.
> > > > > >
> > > > > > I don't think so. Here is
Re: [U-Boot] setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
> -Original Message-
> From: Joakim Tjernlund [mailto:joakim.tjernl...@infinera.com]
> Sent: Tuesday, September 05, 2017 8:45 PM
> To: Mingkai Hu ; Roy Zang ;
> York Sun
> Cc: u-boot@lists.denx.de
> Subject: Re: setup of PEX_GCLK_RATIO in E500 CPUs(P2010) missing ?
>
> On Wed, 2017-08-30 at 15:25 +, York Sun wrote:
> > On 08/30/2017 06:05 AM, Joakim Tjernlund wrote:
> > > On Tue, 2017-08-29 at 17:33 +, York Sun wrote:
> > > > +Roy Zang to comment on PCIe clock source
> > > >
> > > > On 08/29/2017 10:06 AM, Joakim Tjernlund wrote:
> > > > > On Tue, 2017-08-29 at 15:43 +, York Sun wrote:
> > > > > > On 08/29/2017 06:21 AM, Joakim Tjernlund wrote:
> > > > > > > On Tue, 2017-08-29 at 12:47 +0200, Joakim Tjernlund wrote:
> > > > > > > > As we are looking at PCI stuff ATM I would like to ask
> > > > > > > > about PEX_GCLK_RATIO in E500 CPUs. I cannot find this is
> > > > > > > > setup at all for E500 but I THINK this is required.
> > > > > > > >
> > > > > > > > In 83xx one do:
> > > > > > > > get_clocks();
> > > > > > > > /* Configure the PCIE controller core clock ratio */
> > > > > > > > out_le32(hose_cfg_base + PEX_GCLK_RATIO,
> > > > > > >
> > > > > > > A bit strange with out_le32 instead of out_be32 ?
> > > > > > >
> > > > > > > > (((bus ? gd->arch.pciexp2_clk : gd->arch.pciexp1_clk) /
> > > > > > > > 100) * 16) / 333); udelay(100);
> > > > > > > >
> > > > > > > > Any clues?
> > > > > > > >
> > > > > > > > Jocke
> > > > > > >
> > > > > > > Seems like only 83xx is setting this parameter.
> > > > > > >
> > > > > > > Anyhow, I put together this patch:
> > > > > > >
> > > > > > > --- a/drivers/pci/fsl_pci_init.c
> > > > > > > +++ b/drivers/pci/fsl_pci_init.c
> > > > > > > @@ -322,6 +322,10 @@ void fsl_pci_init(struct pci_controller
> > > > > > > *hose, struct fsl_pci_info *pci_info)
> > > > > > >
> > > > > > >pci_setup_indirect(hose, cfg_addr, cfg_data);
> > > > > > >
> > > > > > > + /* Configure the PCIE controller core clock ratio */
> > > > > > > + pci_hose_write_config_dword(hose, dev, 0x440, (gd-
> >bus_clk / 3) * 16);
> > > > > > > + /* udelay(100) needed here ?*/
> > > > > > > +
> > > > > > >block_rev = in_be32(&pci->block_rev1);
> > > > > > >if (PEX_IP_BLK_REV_2_2 <= block_rev) {
> > > > > > >pi = &pci->pit[2]; /* 0xDC0 */
> > > > > > >
> > > > > > > Any chance this will work for all supported FSL PCIe controllers?
> > > > > > >
> > > > > >
> > > > > > Jocke,
> > > > > >
> > > > > > You don't need to program this register if the actual PCIe
> > > > > > clock is the same as default. Since SerDes reference clock has
> > > > > > to be 100MHz for PCIe protocol, my guess is the PCIe clock is
> > > > > > always correct. The bus_clk you are referring is not the PCIe
> > > > > > clock. Again, I am not a PCIe expert, I could be wrong. Since
> > > > > > PCIe (SerDes) has been working on multiple platforms, I guess the
> clock is correct.
> > > > >
> > > > > I don't think so. Here is what T1042 says about this:
> > > > >
> > > > > The PCI Express controller clock frequency is one-half the platform
> clock frequency.
> > > > >
> > > > > The PCI Express controller core clock ratio register is used to
> > > > > program the ratio of the actual PCI Express controller clock
> > > > > frequency to the default controller core frequency ( 333 MHz ).
> > > > > This is required only when a PCI Express controller clock frequency
> other than the default 333 MHz has to be used.
> > > > > As an example of programming PEX_GCLK_RATIO, consider the case
> > > > &
Re: [U-Boot] [PATCH 1/2] armv8: ls1046ardb: Make NET independent of FMan
> -Original Message- > From: York Sun [mailto:york@nxp.com] > Sent: Tuesday, April 25, 2017 11:40 PM > To: u-boot@lists.denx.de > Cc: Mingkai Hu ; york sun > Subject: [PATCH 1/2] armv8: ls1046ardb: Make NET independent of FMan > > This allows using PCIe NIC without enabling DPAA FMan. > > Signed-off-by: York Sun > CC: Mingkai Hu > --- > board/freescale/ls1046ardb/Makefile | 2 +- > include/configs/ls1046ardb.h| 15 +-- > 2 files changed, 10 insertions(+), 7 deletions(-) > > diff --git a/board/freescale/ls1046ardb/Makefile > b/board/freescale/ls1046ardb/Makefile > index b92ed0b..4076558 100644 > --- a/board/freescale/ls1046ardb/Makefile > +++ b/board/freescale/ls1046ardb/Makefile > @@ -7,6 +7,6 @@ > obj-y += ddr.o > obj-y += ls1046ardb.o > ifndef CONFIG_SPL_BUILD > -obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o > +obj-$(CONFIG_NET) += eth.o > obj-y += cpld.o > endif > diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h > index 67ee626..40a5635 100644 > --- a/include/configs/ls1046ardb.h > +++ b/include/configs/ls1046ardb.h > @@ -178,18 +178,20 @@ > #define CONFIG_ENV_SECT_SIZE 0x4 /* > 256KB */ > #endif > > +#define AQR105_IRQ_MASK 0x8000 > /* FMan */ > #ifndef SPL_NO_FMAN > -#ifdef CONFIG_SYS_DPAA_FMAN > -#define CONFIG_FMAN_ENET > + > +#ifdef CONFIG_NET > #define CONFIG_PHYLIB > -#define CONFIG_PHYLIB_10G > #define CONFIG_PHY_GIGE /* Include GbE speed/duplex > detection */ > - > #define CONFIG_PHY_REALTEK > -#define CONFIG_PHY_AQUANTIA > -#define AQR105_IRQ_MASK 0x8000 > +#endif > > +#ifdef CONFIG_SYS_DPAA_FMAN > +#define CONFIG_FMAN_ENET > +#define CONFIG_PHY_AQUANTIA > +#define CONFIG_PHYLIB_10G > #define RGMII_PHY1_ADDR 0x1 > #define RGMII_PHY2_ADDR 0x2 > > @@ -200,6 +202,7 @@ > > #define CONFIG_ETHPRIME "FM1@DTSEC3" > #endif > + > #endif > > /* QSPI device */ > -- > 2.7.4 ACK. And Tested-by: Mingkai Hu Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2] armv8: ls1043ardb: Make NET independent of FMan
> -Original Message- > From: York Sun [mailto:york@nxp.com] > Sent: Tuesday, April 25, 2017 11:40 PM > To: u-boot@lists.denx.de > Cc: Mingkai Hu ; york sun > Subject: [PATCH 2/2] armv8: ls1043ardb: Make NET independent of FMan > > This allows using PCIe NIC without enabling DPAA FMan. > > Signed-off-by: York Sun > CC: Mingkai Hu > --- > board/freescale/ls1043ardb/Makefile | 2 +- > include/configs/ls1043ardb.h| 13 - > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/board/freescale/ls1043ardb/Makefile > b/board/freescale/ls1043ardb/Makefile > index 2a4452e..930c690 100644 > --- a/board/freescale/ls1043ardb/Makefile > +++ b/board/freescale/ls1043ardb/Makefile > @@ -7,6 +7,6 @@ > obj-y += ddr.o > obj-y += ls1043ardb.o > ifndef CONFIG_SPL_BUILD > -obj-$(CONFIG_SYS_DPAA_FMAN) += eth.o > +obj-$(CONFIG_NET) += eth.o > obj-y += cpld.o > endif > diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h > index 5e570cd..5e5d1f6 100644 > --- a/include/configs/ls1043ardb.h > +++ b/include/configs/ls1043ardb.h > @@ -250,16 +250,19 @@ > > /* FMan */ > #ifndef SPL_NO_FMAN > -#ifdef CONFIG_SYS_DPAA_FMAN > -#define CONFIG_FMAN_ENET > +#define AQR105_IRQ_MASK 0x4000 > + > +#ifdef CONFIG_NET > #define CONFIG_PHYLIB > -#define CONFIG_PHYLIB_10G > #define CONFIG_PHY_GIGE /* Include GbE speed/duplex > detection */ > - > #define CONFIG_PHY_VITESSE > #define CONFIG_PHY_REALTEK > +#endif > + > +#ifdef CONFIG_SYS_DPAA_FMAN > +#define CONFIG_FMAN_ENET > +#define CONFIG_PHYLIB_10G > #define CONFIG_PHY_AQUANTIA > -#define AQR105_IRQ_MASK 0x4000 > > #define RGMII_PHY1_ADDR 0x1 > #define RGMII_PHY2_ADDR 0x2 > -- > 2.7.4 ACK. And Tested-by: Mingkai Hu Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] Please separated FMan from generate NET config
> > -Original Message- > From: york sun > Sent: Wednesday, March 22, 2017 3:13 AM > To: Mingkai Hu > Cc: Prabhakar Kushwaha ; u- > b...@lists.denx.de > Subject: Please separated FMan from generate NET config > > Mingkai, > > I noticed during recent debug on LS1043ARDB and LS1046ARDB that the > general network feature is combined with DPAA FMan. This is not correct. > The fix is easy. You only need to change the Makefile in board folder to build > eth.o with $(CONFIG_NET) instead of $(CONFIG_SYS_DPAA_FMAN). You > also need to adjust the board config header file to select PHY config with > generate net option vs FMan specific ones. > > Please send patches to fix them. > Sure, will send the patch out to fix it. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase
> -Original Message- > From: Jagan Teki [mailto:jagannadh.t...@gmail.com] > Sent: Tuesday, March 28, 2017 1:57 AM > To: york sun > Cc: Jagan Teki ; u-boot@lists.denx.de; Mingkai Hu > > Subject: Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase > > On Mon, Mar 27, 2017 at 11:05 PM, york sun wrote: > > On 03/15/2017 06:44 PM, york@nxp.com wrote: > >> On 01/27/2017 10:04 AM, Jagan Teki wrote: > >>> On Mon, Jan 23, 2017 at 8:05 PM, york sun wrote: > >>>> On 12/12/2016 09:32 PM, Yao Yuan wrote: > >>>>> Hi Jagan, > >>>>> > >>>>> > >>>>> > >>>>> Do you have any comments? > >>>>> > >>>>> > >>>>> > >>>>> Thanks for your work and you know it’s important for QSPI with > >>>>> S25FS512S. > >>>>> > >>>>> > >>>>> > >>>>> It seems S25FS512S can’t support the SECT_4K, right? > >>>>> > >>>>> And it better to retain the disable_4kb, but we can add a flag in > >>>>> dts to select whether enable it. > >>>>> > >>>>> > >>>> > >>>> Jagan, > >>>> > >>>> This is blocking me from using the board with this specific flash chip. > >>>> Can you take a look? By reverting this single commit 116e005c, my > >>>> board works again. > >>> > >>> I will try to work on this. > >>> > >> > >> Guys, > >> > >> Where are we on this issue? > >> > >> York > >> > > > > Can we revert this patch or have a fix? > > Just wanted to understand more about this, I've attached programming > model in previous mail about this and based on that I've fixed with all 4K. > Waiting for 'Yao Yuan' inputs on this. > +Suresh to follow up this question. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mpc85xx: pci: Implement workaround for Erratum A007815
> -Original Message-
> From: york sun
> Sent: Friday, December 02, 2016 1:24 AM
> To: Mingkai Hu
> Cc: Chris Packham ; Tony O'Brien
> ; u-boot
> Subject: Re: [U-Boot] [PATCH] mpc85xx: pci: Implement workaround for
> Erratum A007815
>
> On 11/30/2016 11:51 PM, Chris Packham wrote:
> > (adding York)
> >
> > On Thu, Dec 1, 2016 at 4:20 PM, Tony O'Brien
> > wrote:
> >> The read-only-write-enable bit is set by default and must be cleared
> >> to prevent overwriting read-only registers. This should be done
> >> immediately after resetting the PCI Express controller.
> >>
> >> Reviewed-by: Hamish Martin
> >>
> >> ---
> >> Note that this does not implement the whole fix for this erratum,
> >> just what is necessary for our implementation. Since we are using a
> >> fixed RC configuration, no support has been added for EP mode or any
> >> consideration of link-up/down events.
> >>
> >> Signed-off-by: Tony O'Brien
> >> ---
> >> arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++
> >> arch/powerpc/include/asm/config_mpc85xx.h | 1 +
> >> arch/powerpc/include/asm/fsl_pci.h| 4 +++-
> >> drivers/pci/fsl_pci_init.c| 7 +++
> >> 4 files changed, 14 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> >> b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> >> index 402a1ff..aabb56b 100644
> >> --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> >> +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
> >> @@ -330,6 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag,
> >> int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
> >> puts("Work-around for Erratum A009663 enabled\n"); #endif
> >> +#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
> >> + puts("Work-around for Erratum A007815 enabled\n"); #endif
> >>
> >> return 0;
> >> }
> >> diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
> >> b/arch/powerpc/include/asm/config_mpc85xx.h
> >> index c92bc1e..c298e44 100644
> >> --- a/arch/powerpc/include/asm/config_mpc85xx.h
> >> +++ b/arch/powerpc/include/asm/config_mpc85xx.h
> >> @@ -785,6 +785,7 @@ defined(CONFIG_PPC_T1014) ||
> >> defined(CONFIG_PPC_T1013) #define
> CONFIG_SYS_FSL_ERRATUM_A006593
> >> #define CONFIG_SYS_FSL_ERRATUM_A007186 #define
> >> CONFIG_SYS_FSL_ERRATUM_A006379
> >> +#define CONFIG_SYS_FSL_ERRATUM_A007815
> >> #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE #define
> >> CONFIG_SYS_FSL_SFP_VER_3_0
> >>
>
> Tony,
>
> The signed-off signature should be above the --- line.
>
> Mingkai,
>
> Please review this implementation. This erratum applies to T4240, T2080,
> LS1021A.
>
Hi York and Tony,
Sorry for delayed response.
I think it's better to add the errata implementation for the layerscape
platform also.
The layerscape driver code is drivers/pci/pcie_layerscape.c. We can help to
test the patch on the layerscape platform if Tony don't have the platform.
There is no link-up/down events used under u-boot, we can leave it out.
Thanks,
Mingkai
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Re: [U-Boot] [PATCH] armv8/ls1043a: Add the OCRAM initialization
> -Original Message- > From: york sun > Sent: Tuesday, October 25, 2016 12:15 AM > To: Prabhakar Kushwaha ; Pratiyush > Srivastava ; u-boot@lists.denx.de; Mingkai > Hu > Cc: Hou Zhiqiang > Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization > > On 10/23/2016 06:59 AM, Prabhakar Kushwaha wrote: > > Hi York, > > > > > >> -Original Message- > >> From: york sun > >> Sent: Saturday, October 22, 2016 1:39 AM > >> To: Prabhakar Kushwaha ; Pratiyush > >> Srivastava ; u-boot@lists.denx.de; > >> Mingkai Hu > >> Cc: Hou Zhiqiang > >> Subject: Re: [PATCH] armv8/ls1043a: Add the OCRAM initialization > >> > >> On 10/16/2016 10:35 PM, Prabhakar Kushwaha wrote: > >>> Hi Mingkai, > >>> > >>>> -Original Message- > >>>> From: Pratiyush Srivastava [mailto:pratiyush.srivast...@nxp.com] > >>>> Sent: Wednesday, October 12, 2016 5:46 PM > >>>> To: u-boot@lists.denx.de > >>>> Cc: york sun ; Prabhakar Kushwaha > >>>> ; Pratiyush Srivastava > >>>> ; Hou Zhiqiang > >> > >>>> Subject: [PATCH] armv8/ls1043a: Add the OCRAM initialization > >>>> > >>>> Clear the content to zero and the ECC error bit of OCRAM1/2. > >>>> > >>>> The OCRAM must be initialized to ZERO by the unit of 8-Byte before > >>>> accessing it, or else it will generate ECC error. And the IBR has > >>>> accessed the OCRAM before this initialization, so the ECC error > >>>> status bit should to be cleared. > >>>> > >>>> Signed-off-by: Pratiyush Srivastava > >>>> Signed-off-by: Hou Zhiqiang > >>>> Signed-off-by: Prabhakar Kushwaha > >>>> --- > >>> > >>> This requirement is for both ls1043 and ls1088a. was this patch > >>> taken care > >> during ls1043a upstreaming > >>> If not, how it is being taken care for ls1043a. Same approach can > >>> be used for > >> ls1088a > >>> > >> > >> I wonder why we don't see ECC errors before this patch. We have > >> LS1043A boots on NAND, SD. > >> > > > > OCRAM has a requirement of initializing before first time "read". > > If user reads OCRAM before **initializing**; ECC error will come. (u-boot > > is > not handling this error for now). > > > > I can only guess the reason of not seeing this error as OCRAM never read > before any write. > > Even in case of Stack, data is first written and then read. > > > > Is there a case you want to read from OCRAM before writing anything to it? > Why don't we need to do so for SPL or LSCH3? > Hi York, For secure boot case, the bootrom uses the OCRAM as workspace but does not Cleare the after the using, which will trigger this issue. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board support
> -Original Message-
> From: york sun
> Sent: Saturday, September 17, 2016 4:14 AM
> To: Q.Y. Gong ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; S.H. Xie ; Z.Q. Hou
> ; Wenbin Song ;
> Shengzhou Liu
> Subject: Re: [Patch v6 8/9] armv8: ls1046ardb: Add LS1046ARDB board
> support
>
> On 09/07/2016 03:08 AM, Gong Qianyu wrote:
> > From: Mingkai Hu
> >
> > LS1046ARDB Specification:
> > -
> > Memory subsystem:
> > * 8GByte DDR4 SDRAM (64bit bus)
> > * 512 Mbyte NAND flash
> > * Two 64 Mbyte high-speed SPI flash
> > * SD connector to interface with the SD memory card
> > * On-board 4G eMMC
> >
> > Ethernet:
> > * Two XFI 10G ports
> > * Two SGMII ports
> > * Two RGMII ports
> >
> > PCIe:
> > * PCIe1 (SerDes2 Lane0) to miniPCIe slot
> > * PCIe2 (SerDes2 Lane1) to x2 PCIe slot
> > * PCIe3 (SerDes2 Lane2) to x4 PCIe slot
>
> Why don't you enable PCIe in the config file?
>
A follow up patch will enable PCIe support which will use the SVR to
differentiate some memory map differences
for different silicon.
>
> > diff --git a/board/freescale/ls1046ardb/ddr.c
> > b/board/freescale/ls1046ardb/ddr.c
> > new file mode 100644
> > index 000..a9b7dbd
> > --- /dev/null
> > +++ b/board/freescale/ls1046ardb/ddr.c
> > @@ -0,0 +1,140 @@
> > +/*
> > + * Copyright 2016 Freescale Semiconductor, Inc.
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include "ddr.h"
> > +#ifdef CONFIG_FSL_DEEP_SLEEP
> > +#include
> > +#endif
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +void fsl_ddr_board_options(memctl_options_t *popts,
> > + dimm_params_t *pdimm,
> > + unsigned int ctrl_num)
> > +{
> > + const struct board_specific_parameters *pbsp, *pbsp_highest =
> NULL;
> > + ulong ddr_freq;
> > +
> > + if (ctrl_num > 1) {
> > + printf("Not supported controller number %d\n", ctrl_num);
> > + return;
> > + }
> > + if (!pdimm->n_ranks)
> > + return;
> > +
> > + pbsp = udimms[0];
> > +
> > + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
> > +* freqency and n_banks specified in board_specific_parameters
> table.
> > +*/
> > + ddr_freq = get_ddr_freq(0) / 100;
> > + while (pbsp->datarate_mhz_high) {
> > + if (pbsp->n_ranks == pdimm->n_ranks) {
> > + if (ddr_freq <= pbsp->datarate_mhz_high) {
> > + popts->clk_adjust = pbsp->clk_adjust;
> > + popts->wrlvl_start = pbsp->wrlvl_start;
> > + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> > + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> > + goto found;
> > + }
> > + pbsp_highest = pbsp;
> > + }
> > + pbsp++;
> > + }
> > +
> > + if (pbsp_highest) {
> > + printf("Error: board specific timing not found for %lu MT/s\n",
> > + ddr_freq);
> > + printf("Trying to use the highest speed (%u) parameters\n",
> > + pbsp_highest->datarate_mhz_high);
> > + popts->clk_adjust = pbsp_highest->clk_adjust;
> > + popts->wrlvl_start = pbsp_highest->wrlvl_start;
> > + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
> > + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
> > + } else {
> > + panic("DIMM is not supported by this board");
> > + }
> > +found:
> > + debug("Found timing match: n_ranks %d, data rate %d,
> rank_gb %d\n",
> > + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
> > +
> > + popts->data_bus_width = 0; /* 64-bit data bus */
> > + popts->otf_burst_chop_en = 0;
> > + popts->burst_length = DDR_BL8;
>
> You don't need to set these options unless you specifically want to disable on
> the fly burst chop. Do you?
>
No, will remove it.
Thanks,
Mingkai
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Re: [U-Boot] [PATCH 1/8] drivers/ddr/fsl: add DEBUG_38
> -Original Message- > From: york sun > Sent: Friday, August 26, 2016 11:00 PM > To: Qianyu Gong ; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha ; Mingkai Hu > ; Shaohui Xie ; Zhiqiang Hou > ; Wenbin Song > Subject: Re: [PATCH 1/8] drivers/ddr/fsl: add DEBUG_38 > > On 08/26/2016 04:40 AM, Gong Qianyu wrote: > > From: Mingkai Hu > > > > DEBUG_38 is needed for rev2 DDR controller. > > > > Signed-off-by: Mingkai Hu > > Signed-off-by: Gong Qianyu > > --- > > drivers/ddr/fsl/ctrl_regs.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c > > index 24fd366..4ae8b80 100644 > > --- a/drivers/ddr/fsl/ctrl_regs.c > > +++ b/drivers/ddr/fsl/ctrl_regs.c > > @@ -2526,5 +2526,7 @@ compute_fsl_memctl_config_regs(const > unsigned int ctrl_num, > > ddr->debug[2] |= 0x0200;/* set bit 22 */ > > #endif > > > > + ddr->debug[37] = 0x8000; > > + > > NAK. You can't simply add a new register without checking if it exists on > older > controllers. > > York Thanks, York. This is not needed and will remove it in next version. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/8] armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency
> -Original Message- > From: york sun > Sent: Friday, August 26, 2016 11:01 PM > To: Qianyu Gong ; u-boot@lists.denx.de > Cc: Prabhakar Kushwaha ; Mingkai Hu > ; Shaohui Xie ; Zhiqiang Hou > ; Wenbin Song > Subject: Re: [PATCH 3/8] armv8: fsl-layerscape: Increase L2 Data RAM latency > and L2 Tag RAM latency > > On 08/26/2016 04:40 AM, Gong Qianyu wrote: > > From: Mingkai Hu > > > > Use 3 cycles. > > Care to explain more here? > Hi York, According to design, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, So increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 8/8] armv8: ls1046ardb: Add LS1046ARDB board support
> -Original Message- > From: Gong Qianyu [mailto:qianyu.g...@nxp.com] > Sent: Friday, August 26, 2016 7:29 PM > To: u-boot@lists.denx.de; york sun > Cc: Prabhakar Kushwaha ; Mingkai Hu > ; Shaohui Xie ; Zhiqiang Hou > ; Wenbin Song ; Mingkai > Hu ; Qianyu Gong > Subject: [PATCH 8/8] armv8: ls1046ardb: Add LS1046ARDB board support > > From: Mingkai Hu > > LS1046ARDB Specification: > - > Memory subsystem: > * 8GByte DDR4 SDRAM (64bit bus) > * 512 Mbyte NAND flash > * Two 64 Mbyte high-speed SPI flash > * SD connector to interface with the SD memory card > * On-board 4G eMMC > > Ethernet: > * Two XFI 10G ports > * Two SGMII ports > * Two RGMII ports > > PCIe: > * PCIe1 (SerDes2 Lane0) to miniPCIe slot > * PCIe2 (SerDes2 Lane1) to x2 PCIe slot > * PCIe3 (SerDes2 Lane2) to x4 PCIe slot > > SATA: > * SerDes2 Lane3 to SATA port > > USB 3.0: one super speed USB 3.0 type A port >one Micro-AB port > > UART: supports two UARTs up to 115200 bps for console > > Signed-off-by: Gong Qianyu > Signed-off-by: Mingkai Hu > --- > arch/arm/Kconfig | 9 + > arch/arm/dts/Makefile | 1 + > arch/arm/dts/fsl-ls1046a-rdb.dts | 44 > arch/arm/dts/fsl-ls1046a.dtsi | 220 +++ > board/freescale/ls1046ardb/Kconfig | 16 ++ > board/freescale/ls1046ardb/MAINTAINERS | 8 + > board/freescale/ls1046ardb/Makefile| 10 + > board/freescale/ls1046ardb/README | 67 ++ > board/freescale/ls1046ardb/cpld.c | 158 ++ > board/freescale/ls1046ardb/cpld.h | 49 + > board/freescale/ls1046ardb/ddr.c | 140 > board/freescale/ls1046ardb/ddr.h | 44 > board/freescale/ls1046ardb/eth.c | 77 +++ > board/freescale/ls1046ardb/ls1046ardb.c| 173 +++ > board/freescale/ls1046ardb/ls1046ardb_pbi.cfg | 22 ++ > board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg | 7 + > board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg | 7 + > .../ls1046ardb/ls1046ardb_rcw_sd_1200.cfg | 7 + > .../ls1046ardb/ls1046ardb_rcw_sd_1400.cfg | 7 + > .../ls1046ardb/ls1046ardb_rcw_sd_5506.cfg | 7 + > configs/ls1046ardb_qspi_defconfig | 25 +++ > configs/ls1046ardb_sdcard_defconfig| 26 +++ > include/configs/ls1046a_common.h | 181 > include/configs/ls1046ardb.h | 237 > + > 24 files changed, 1542 insertions(+) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c..d343995 > 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -811,6 +811,14 @@ config TARGET_LS1043ARDB > help > Support for Freescale LS1043ARDB platform. > > + > +Memory map from core's view > + > +Start AddressEnd Address Description Size > +0x00__ 0x00_000F_ Secure Boot ROM > 1MB > +0x00_0100_ 0x00_0FFF_ CCSRBAR > 240MB > +0x00_1000_ 0x00_1000_ OCRAM0 > 64KB > +0x00_1001_ 0x00_1001_ OCRAM1 > 64KB > +0x00_2000_ 0x00_20FF_ DCSR16MB > +0x00_7E80_ 0x00_7E80_ IFC - NAND Flash64KB > +0x00_7FB0_ 0x00_7FB0_0FFF IFC - FPGA 4KB > +0x00_8000_ 0x00__ DRAM1 2GB > + It's better to add DRAM2 memory map. 0x08 _8000_ 0x09__ DRAM2 6GB > +QSPI flash map: > +Start AddressEnd Address Description Size > +0x0_4000_ - 0x0_400F_RCW + PBI 1MB > +0x0_4010_ - 0x0_401F_U-Boot 1MB > +0x0_4020_ - 0x0_402F_U-Boot Env 1MB > +0x0_4030_ - 0x0_403F_FMan ucode 1MB > +0x0_4040_ - 0x0_404F_UEFI1MB > +0x0_4050_ - 0x0_405F_PPA 1MB > +0x0_4060_ - 0x0_40FF_Reserved10MB > +0x0_4100_ - 0x0_43FF_FIT Image 48MB > + Increase the PPA size to 2M and add memory space for secure boot header as follows: 0x4050 0x406F Primary Protected Application (PPA) 2 M 0x4070 0x408F Secure boot header + bootscript 2 M 0x4090 0x40FF Reserved 7 M Regards, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a
> -Original Message- > From: Shengzhou Liu > Sent: Monday, August 29, 2016 6:53 PM > To: Qianyu Gong ; u-boot@lists.denx.de; york sun > > Cc: Prabhakar Kushwaha ; Mingkai Hu > ; Shaohui Xie ; Zhiqiang Hou > ; Wenbin Song ; Qianyu > Gong > Subject: RE: [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a > > > > -Original Message- > > From: Gong Qianyu [mailto:qianyu.g...@nxp.com] > > Sent: Friday, August 26, 2016 7:29 PM > > To: u-boot@lists.denx.de; york sun > > Cc: Prabhakar Kushwaha ; Mingkai Hu > > ; Shaohui Xie ; Zhiqiang > Hou > > ; Wenbin Song ; > Shengzhou > > Liu ; Qianyu Gong > > Subject: [PATCH 6/8] armv8: ls1046a: Enable DDR erratum for ls1046a > > > > From: Shengzhou Liu > > > > Enable ERRATUM_A009801, ERRATUM_A009803, ERRATUM_A009942, > > ERRATUM_A010165 > > > > Signed-off-by: Shengzhou Liu > > Signed-off-by: Gong Qianyu > > --- > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 + > > 1 file changed, 5 insertions(+) > > > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h > > b/arch/arm/include/asm/arch-fsl-layerscape/config.h > > index c7e374c..3250290 100644 > > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h > > @@ -238,6 +238,11 @@ > > #define GICC_BASE 0x0142 > > > > #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 > > + > > +#define CONFIG_SYS_FSL_ERRATUM_A009801 #define > > +CONFIG_SYS_FSL_ERRATUM_A009803 #define > CONFIG_SYS_FSL_ERRATUM_A009942 > > +#define CONFIG_SYS_FSL_ERRATUM_A010165 > > LS1046 also need to enable ERRATUM_A008511 in this patch. Sure, will add the A008511 as what we have worked out. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR
> -Original Message- > From: Shaohui Xie > Sent: Monday, August 29, 2016 12:45 PM > To: york sun ; Qianyu Gong ; > u-boot@lists.denx.de > Cc: Prabhakar Kushwaha ; Mingkai Hu > ; Zhiqiang Hou ; Wenbin > Song > Subject: RE: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR > > > -Original Message- > > From: york sun > > Sent: Saturday, August 27, 2016 12:08 AM > > To: Qianyu Gong ; u-boot@lists.denx.de > > Cc: Prabhakar Kushwaha ; Mingkai Hu > > ; Shaohui Xie ; Zhiqiang > Hou > > ; Wenbin Song > > Subject: Re: [PATCH 7/8] armv8: ls1046a: disable SATA ECC in DCSR > > > > On 08/26/2016 04:40 AM, Gong Qianyu wrote: > > > From: Shaohui Xie > > > > > > So to fix SATA CRC error. > > > > Does ECC cause the CRC error? Please explain more what you are doing > > in this patch. > [S.H] We only know disable ECC can fix CRC error which provided by > validation team As a workaround, the root cause is not clear. > > Maybe we can drop it for now, there might be a better solution for this issue > in future, or the solution is still the same, but we know exactly what is > going > on. > > Thanks, > Shaohui Maybe we keep this patch and add the description in the git log, and remove the Disabling ECC when the root cause has found. At lease, disabling ECC can make the SATA working. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency
> -Original Message- > From: Edward L Swarthout > Sent: Saturday, July 02, 2016 5:44 AM > To: Prabhakar Kushwaha; york sun; Qianyu Gong; albert.u.b...@aribaud.net; > u-boot@lists.denx.de; s.temerkha...@gmail.com; > yamada.masah...@socionext.com > Cc: Mingkai Hu > Subject: RE: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data > coherency > > From: Prabhakar Kushwaha > > >> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york > >> On 06/30/2016 02:03 AM, Gong Qianyu wrote: > >> > From: Mingkai Hu > >> > > >> > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. > >> > The SMPEN bit should be set before enabling the data cache. > >> > If not enabled, the cache is not coherent with other cores and data > >> > corruption could occur. > >> > > >> > +/* Enalbe SMPEN bit */ > >> > +mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ > >> > +orr x0, x0, #0x40 > >> > +msr S3_1_c15_c2_1, x0 > >> > + > >> > >> I wonder what impact this patch has. Did you find it effective on A53 > core? > >> According to ARM documents, A57 and A72 seem don't care this bit. > > > >I have seen big difference on LS1012A with A53 cores after enabling this > bit. > >If I don't enable this bit many IPs like SATA, SDHC show coherency issue. > > But LS1012A only has a single A53 core. > The multicore part, LS1043A, sets this bit in the bootrom: > > 34: d539f221mrs x1, s3_1_c15_c2_1 > 38: b27a0021orr x1, x1, #0x40 > 3c: d519f221msr s3_1_c15_c2_1, x1 > This bit needs to be set even only one core. And bootrom did not set this bit, so the coherency issue was caused. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency
> -Original Message- > From: Prabhakar Kushwaha > Sent: Friday, July 01, 2016 7:55 AM > To: york sun; Qianyu Gong; albert.u.b...@aribaud.net; u-boot@lists.denx.de; > s.temerkha...@gmail.com; yamada.masah...@socionext.com > Cc: Mingkai Hu > Subject: RE: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency > > Hi York, > > > > -Original Message- > > From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york > > sun > > Sent: Thursday, June 30, 2016 10:32 PM > > To: Qianyu Gong ; albert.u.b...@aribaud.net; u- > > b...@lists.denx.de; s.temerkha...@gmail.com; > > yamada.masah...@socionext.com > > Cc: Mingkai Hu > > Subject: Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data > > coherency > > > > On 06/30/2016 02:03 AM, Gong Qianyu wrote: > > > From: Mingkai Hu > > > > > > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. > > > The SMPEN bit should be set before enabling the data cache. > > > If not enabled, the cache is not coherent with other cores and data > > > corruption could occur. > > > > > > Signed-off-by: Mingkai Hu > > > Signed-off-by: Gong Qianyu > > > > > > diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S > > > index 670e323..735dd67 100644 > > > --- a/arch/arm/cpu/armv8/start.S > > > +++ b/arch/arm/cpu/armv8/start.S > > > @@ -81,6 +81,11 @@ reset: > > > msr cpacr_el1, x0 /* Enable FP/SIMD */ > > > 0: > > > > > > + /* Enalbe SMPEN bit */ > > > + mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ > > > + orr x0, x0, #0x40 > > > + msr S3_1_c15_c2_1, x0 > > > + > > > /* Apply ARM core specific erratas */ > > > bl apply_core_errata > > > > > > > > > > Qianyu, > > > > I wonder what impact this patch has. Did you find it effective on A53 core? > > According to ARM documents, A57 and A72 seem don't care this bit. > > Quote > > > > I have seen big difference on LS1012A with A53 cores after enabling this bit. > If I don't enable this bit many IPs like SATA, SDHC show coherency issue. > Hi York, This bit is used to enable hardware management of data coherency with other cores in the cluster for A53. "Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. You must set the SMPEN bit before enabling the data cache. If you do not, then the cache is not coherent with other cores and data corruption could occur. " For A57/A72, this bit enables the processor to receive instruction cache and TLB maintenance operations broadcast from other processors in the cluster. We will change the commit message and integrate Mark's comments to guard this setting for relevant CPUs. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of CR3V
From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
Sent: Thursday, June 30, 2016 2:50 PM
To: Qianyu Gong
Cc: Mingkai Hu; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
Subject: Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of
CR3V
Hi
On Jun 30, 2016 08:47, "Gong Qianyu"
mailto:qianyu.g...@nxp.com>> wrote:
>
> From: Mingkai Hu mailto:mingkai...@nxp.com>>
>
> Set the flash to Uniform Sector Architecture in the non-volatile
> register. After the power cycle, it's also Uniform Sector Architecture.
>
> Signed-off-by: Mingkai Hu mailto:mingkai...@nxp.com>>
> Signed-off-by: Gong Qianyu mailto:qianyu.g...@nxp.com>>
>
> diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
> index 64d4e0f..366c362 100644
> --- a/drivers/mtd/spi/spi_flash.c
> +++ b/drivers/mtd/spi/spi_flash.c
> @@ -975,7 +975,7 @@ int spi_flash_decode_fdt(const void *blob, struct
> spi_flash *flash)
> static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
> {
> u8 cmd[4];
> - u32 offset = 0x84; /* CR3V register offset */
> + u32 offset = 0x4; /* CR3NV register offset */
> u8 cr3v;
> int ret;
>
I have already tested it and I have in my tree.
What does this mean?
I don't think that should be mandatory in general
The general code doesn’t handle different sector operation, so need to set it
as uniform sector architecture.
Michael
> --
> 2.1.0.27.g96db324
>
> ___
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Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of CR3V
> -Original Message-
> From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
> Sent: Thursday, June 30, 2016 3:47 PM
> To: Mingkai Hu
> Cc: Qianyu Gong; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
> Subject: Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of
> CR3V
>
> Hi
>
> On Thu, Jun 30, 2016 at 9:40 AM, Mingkai Hu wrote:
> >
> >
> >> -Original Message-
> >> From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
> >> Sent: Thursday, June 30, 2016 3:33 PM
> >> To: Mingkai Hu
> >> Cc: Qianyu Gong; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
> >> Subject: Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV
> >> instead of CR3V
> >>
> >> Hi
> >>
> >>
> >> On Thu, Jun 30, 2016 at 9:29 AM, Mingkai Hu wrote:
> >> >
> >> >
> >> >
> >> >
> >> > From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
> >> > Sent: Thursday, June 30, 2016 2:50 PM
> >> > To: Qianyu Gong
> >> > Cc: Mingkai Hu; u-boot@lists.denx.de; Yunhui Cui;
> >> > jt...@openedev.com
> >> > Subject: Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV
> >> > instead of CR3V
> >> >
> >> >
> >> >
> >> > Hi
> >> >
> >> > On Jun 30, 2016 08:47, "Gong Qianyu" wrote:
> >> >>
> >> >> From: Mingkai Hu
> >> >>
> >> >> Set the flash to Uniform Sector Architecture in the non-volatile
> >> >> register. After the power cycle, it's also Uniform Sector Architecture.
> >> >>
> >> >> Signed-off-by: Mingkai Hu
> >> >> Signed-off-by: Gong Qianyu
> >> >>
> >> >> diff --git a/drivers/mtd/spi/spi_flash.c
> >> >> b/drivers/mtd/spi/spi_flash.c index 64d4e0f..366c362 100644
> >> >> --- a/drivers/mtd/spi/spi_flash.c
> >> >> +++ b/drivers/mtd/spi/spi_flash.c
> >> >> @@ -975,7 +975,7 @@ int spi_flash_decode_fdt(const void *blob,
> >> >> struct spi_flash *flash) static int
> >> >> spansion_s25fss_disable_4KB_erase(struct spi_slave *spi) {
> >> >> u8 cmd[4];
> >> >> - u32 offset = 0x84; /* CR3V register offset */
> >> >> + u32 offset = 0x4; /* CR3NV register offset */
> >> >> u8 cr3v;
> >> >> int ret;
> >> >>
> >> >
> >> > I have already tested it and I have in my tree.
> >> >
> >> > What does this mean?
> >> >
> >> > I don't think that should be mandatory in general
> >> >
> >> > The general code doesn’t handle different sector operation, so need
> >> > to set it as uniform sector architecture.
> >> >
> >>
> >> And what about board that does not use the flash in uboot but manage
> >> in some other way. I'm not saying that is wrong but I don't know if
> >> this setting must be no-volatile. Is it something connected from booting on
> QSPI?
> >>
> >
> > If it was not used as uniform sector architecture, the
> > spansion_s25fss_disable_4KB_erase should not be called, correct?
> >
>
> Ok, understand what you mean. You should just probe one time during
> development
> and if you probe means that you want it configured.
>
Yes, and if probed but not using the uniform sector, need to add the code to
handle
different sectors operation and do not call the function
on_s25fss_disable_4KB_erase.
> Anyway as I said I have it in my tree. So I was just asking about permanent
> setting
>
>
> Michael
>
> > Thanks,
> > Mingkai
> >
> >> >
> >> >> --
> >> >> 2.1.0.27.g96db324
> >> >>
> >> >> ___
> >> >> U-Boot mailing list
> >> >> U-Boot@lists.denx.de
> >> >> http://lists.denx.de/mailman/listinfo/u-boot
> >>
> >>
> >>
> >> --
> >> | Michael Nazzareno Trimarchi Amarula Solutions BV |
> >> | COO - Founder Cruquiuskade 47 |
> >> | +31(0)851119172 Amsterdam 1018 AM NL |
> >> | [`as] http://www.amarulasolutions.com |
>
>
>
> --
> | Michael Nazzareno Trimarchi Amarula Solutions BV |
> | COO - Founder Cruquiuskade 47 |
> | +31(0)851119172 Amsterdam 1018 AM NL |
> | [`as] http://www.amarulasolutions.com |
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Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of CR3V
> -Original Message-
> From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
> Sent: Thursday, June 30, 2016 3:33 PM
> To: Mingkai Hu
> Cc: Qianyu Gong; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
> Subject: Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV instead of
> CR3V
>
> Hi
>
>
> On Thu, Jun 30, 2016 at 9:29 AM, Mingkai Hu wrote:
> >
> >
> >
> >
> > From: Michael Trimarchi [mailto:mich...@amarulasolutions.com]
> > Sent: Thursday, June 30, 2016 2:50 PM
> > To: Qianyu Gong
> > Cc: Mingkai Hu; u-boot@lists.denx.de; Yunhui Cui; jt...@openedev.com
> > Subject: Re: [U-Boot] [PATCH] sf: set the Uniform Sector to CR3NV
> > instead of CR3V
> >
> >
> >
> > Hi
> >
> > On Jun 30, 2016 08:47, "Gong Qianyu" wrote:
> >>
> >> From: Mingkai Hu
> >>
> >> Set the flash to Uniform Sector Architecture in the non-volatile
> >> register. After the power cycle, it's also Uniform Sector Architecture.
> >>
> >> Signed-off-by: Mingkai Hu
> >> Signed-off-by: Gong Qianyu
> >>
> >> diff --git a/drivers/mtd/spi/spi_flash.c
> >> b/drivers/mtd/spi/spi_flash.c index 64d4e0f..366c362 100644
> >> --- a/drivers/mtd/spi/spi_flash.c
> >> +++ b/drivers/mtd/spi/spi_flash.c
> >> @@ -975,7 +975,7 @@ int spi_flash_decode_fdt(const void *blob, struct
> >> spi_flash *flash) static int
> >> spansion_s25fss_disable_4KB_erase(struct spi_slave *spi) {
> >> u8 cmd[4];
> >> - u32 offset = 0x84; /* CR3V register offset */
> >> + u32 offset = 0x4; /* CR3NV register offset */
> >> u8 cr3v;
> >> int ret;
> >>
> >
> > I have already tested it and I have in my tree.
> >
> > What does this mean?
> >
> > I don't think that should be mandatory in general
> >
> > The general code doesn’t handle different sector operation, so need to
> > set it as uniform sector architecture.
> >
>
> And what about board that does not use the flash in uboot but manage in some
> other way. I'm not saying that is wrong but I don't know if this setting must
> be
> no-volatile. Is it something connected from booting on QSPI?
>
If it was not used as uniform sector architecture, the
spansion_s25fss_disable_4KB_erase
should not be called, correct?
Thanks,
Mingkai
> >
> >> --
> >> 2.1.0.27.g96db324
> >>
> >> ___
> >> U-Boot mailing list
> >> U-Boot@lists.denx.de
> >> http://lists.denx.de/mailman/listinfo/u-boot
>
>
>
> --
> | Michael Nazzareno Trimarchi Amarula Solutions BV |
> | COO - Founder Cruquiuskade 47 |
> | +31(0)851119172 Amsterdam 1018 AM NL |
> | [`as] http://www.amarulasolutions.com |
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Re: [U-Boot] [Patch v2] fsl-layerscape: fdt: add IFC fixup if no IFC is avaliable in U-Boot
> -Original Message- > From: Gong Qianyu [mailto:qianyu.g...@nxp.com] > Sent: Thursday, April 28, 2016 2:05 PM > To: u-boot@lists.denx.de; york sun; o...@buserror.net > Cc: Mingkai Hu; Qianyu Gong > Subject: [Patch v2] fsl-layerscape: fdt: add IFC fixup if no IFC is avaliable > in > U-Boot > > IFC is considered as a required component in Layerscape platforms' Linux. > But if IFC is not enabled in U-Boot on some boards, accessing IFC memory space > would cause kernel call trace. So disable IFC node in such cases. > > Signed-off-by: Gong Qianyu > --- > V2: > - Revised the title and message. > - Used #ifndef CONFIG_FSL_IFC rather than #ifdef CONFIG_FSL_QSPI. > > arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 5 + > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl- > layerscape/fdt.c > index 1e875c4..96dab56 100644 > --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c > +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c > @@ -98,4 +98,9 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef > CONFIG_SYS_DPAA_FMAN > fdt_fixup_fman_firmware(blob); > #endif > + > +#ifndef CONFIG_FSL_IFC > + do_fixup_by_compat(blob, "fsl,ifc", > +"status", "disabled", 8 + 1, 1); > +#endif > } Reviewed-by: Mingkai Hu Regards, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'
Qianyu,
The reset command is used to boot from the location set in the hardware switch.
Regards,
Mingkai
> -Original Message-
> From: Gong Qianyu [mailto:qianyu.g...@nxp.com]
> Sent: Monday, April 25, 2016 4:39 PM
> To: u-boot@lists.denx.de; york sun; Mingkai Hu
> Cc: Shaohui Xie; Zhiqiang Hou; Wenbin Song; Qianyu Gong
> Subject: [PATCH] armv8/ls1043ardb: fix the limitation of using 'cpld reset'
>
> The current 'cpld reset' will just write global_rst register but couldn't
> switch
> to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw
> source registers for NOR boot as well.
>
> Signed-off-by: Gong Qianyu
> ---
> board/freescale/ls1043ardb/cpld.c | 26 --
> board/freescale/ls1043ardb/cpld.h | 1 +
> 2 files changed, 25 insertions(+), 2 deletions(-)
>
> diff --git a/board/freescale/ls1043ardb/cpld.c
> b/board/freescale/ls1043ardb/cpld.c
> index 78c2824..c645283 100644
> --- a/board/freescale/ls1043ardb/cpld.c
> +++ b/board/freescale/ls1043ardb/cpld.c
> @@ -28,10 +28,18 @@ void cpld_write(unsigned int reg, u8 value)
> /* Set the boot bank to the alternate bank */ void cpld_set_altbank(void) {
> + u16 reg = CPLD_CFG_RCW_SRC_NOR;
> u8 reg4 = CPLD_READ(soft_mux_on);
> + u8 reg5 = (u8)(reg >> 1);
> + u8 reg6 = (u8)(reg & 1);
> u8 reg7 = CPLD_READ(vbank);
>
> - CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL);
> + cpld_rev_bit(®5);
> +
> + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
> +
> + CPLD_WRITE(cfg_rcw_src1, reg5);
> + CPLD_WRITE(cfg_rcw_src2, reg6);
>
> reg7 = (reg7 & ~CPLD_BANK_SEL_MASK) | CPLD_BANK_SEL_ALTBANK;
> CPLD_WRITE(vbank, reg7);
> @@ -42,7 +50,21 @@ void cpld_set_altbank(void)
> /* Set the boot bank to the default bank */ void cpld_set_defbank(void) {
> - CPLD_WRITE(global_rst, 1);
> + u16 reg = CPLD_CFG_RCW_SRC_NOR;
> + u8 reg4 = CPLD_READ(soft_mux_on);
> + u8 reg5 = (u8)(reg >> 1);
> + u8 reg6 = (u8)(reg & 1);
> +
> + cpld_rev_bit(®5);
> +
> + CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1);
> +
> + CPLD_WRITE(cfg_rcw_src1, reg5);
> + CPLD_WRITE(cfg_rcw_src2, reg6);
> +
> + CPLD_WRITE(vbank, 0);
> +
> + CPLD_WRITE(system_rst, 1);
> }
>
> void cpld_set_nand(void)
> diff --git a/board/freescale/ls1043ardb/cpld.h
> b/board/freescale/ls1043ardb/cpld.h
> index bd59c0e..cb175b5 100644
> --- a/board/freescale/ls1043ardb/cpld.h
> +++ b/board/freescale/ls1043ardb/cpld.h
> @@ -40,6 +40,7 @@ void cpld_rev_bit(unsigned char *value);
> #define CPLD_SW_MUX_BANK_SEL 0x40
> #define CPLD_BANK_SEL_MASK 0x07
> #define CPLD_BANK_SEL_ALTBANK0x04
> +#define CPLD_CFG_RCW_SRC_NOR 0x025
> #define CPLD_CFG_RCW_SRC_NAND0x106
> #define CPLD_CFG_RCW_SRC_SD 0x040
> #endif
> --
> 2.1.0.27.g96db324
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[U-Boot] [PATCH v3] armv8/ls1043a: Implement workaround for erratum A009660
From: Mingkai Hu
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu
---
v3:
- Move the macro check to soc.c.
v2:
- Add a check to make sure A009660 and A008514 is are not both enabled.
- Add comment for the offset of eddrtqcr1.
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 19 +++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
2 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7ff0148..213ce3a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -213,6 +213,24 @@ static void erratum_a009929(void)
#endif
}
+/*
+ * This erratum requires setting a value to eddrtqcr1 to optimal
+ * the DDR performance. The eddrtqcr1 register is in SCFG space
+ * of LS1043A and the offset is 0x157_020c.
+ */
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
+ && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+#error A009660 and A008514 can not be both enabled.
+#endif
+
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+ u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -238,6 +256,7 @@ void fsl_lsch2_early_init_f(void)
/* Erratum */
erratum_a009929();
+ erratum_a009660();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index f1b164f..7f8de3d 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -171,6 +171,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
+#define CONFIG_SYS_FSL_ERRATUM_A009660
#else
#error SoC not defined
#endif
--
2.1.0.27.g96db324
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[U-Boot] [PATCH v2] armv8/ls1043a: Implement workaround for erratum A009660
From: Mingkai Hu
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu
---
v2:
- Add a check to make sure A009660 and A008514 is are not both enabled.
- Add comment for the offset of eddrtqcr1.
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 15 +++
arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 +
2 files changed, 20 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7ff0148..8b01fd2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -213,6 +213,20 @@ static void erratum_a009929(void)
#endif
}
+/*
+ * This erratum requires setting a value to eddrtqcr1 to optimal
+ * the DDR performance. The eddrtqcr1 register is in SCFG space
+ * of LS1043A and the offset is 0x157_020c.
+ */
+static void erratum_a009660(void)
+{
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
+ && !defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+ u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -238,6 +252,7 @@ void fsl_lsch2_early_init_f(void)
/* Erratum */
erratum_a009929();
+ erratum_a009660();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index f1b164f..854ed0b 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -171,6 +171,11 @@
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A009929
+#define CONFIG_SYS_FSL_ERRATUM_A009660
+#if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
+ && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
+#error "A009660 and A008514 are both enabed for LS1043A, please check it."
+#endif
#else
#error SoC not defined
#endif
--
2.1.0.27.g96db324
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Re: [U-Boot] [PATCH v4 3/4] ls1043rdb: move USB mux config to config_board_mux
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, January 29, 2016 12:28 PM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v4 3/4] ls1043rdb: move USB mux config to
> config_board_mux
>
> USB pins are muxed with other feature, move USB mux config to
> config_board_mux.
>
> Signed-off-by: Zhao Qiang
> ---
> board/freescale/ls1043ardb/ls1043ardb.c | 30 +++
> ---
> 1 file changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
> b/board/freescale/ls1043ardb/ls1043ardb.c
> index 834fdff..c2d4887 100644
> --- a/board/freescale/ls1043ardb/ls1043ardb.c
> +++ b/board/freescale/ls1043ardb/ls1043ardb.c
> @@ -75,23 +75,8 @@ int dram_init(void)
>
> int board_early_init_f(void)
> {
> - struct ccsr_scfg *scfg = (struct ccsr_scfg
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> - u32 usb_pwrfault;
> -
> fsl_lsch2_early_init_f();
>
> -#ifdef CONFIG_HAS_FSL_XHCI_USB
> - out_be32(&scfg->rcwpmuxcr0, 0x);
> - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB3_SHIFT) |
> - (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB2_SHIFT) |
> - (SCFG_USBPWRFAULT_SHARED <<
> - SCFG_USBPWRFAULT_USB1_SHIFT);
> - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
> -#endif
> -
> return 0;
> }
>
> @@ -126,6 +111,21 @@ int board_init(void)
>
> int config_board_mux(void)
> {
> + struct ccsr_scfg *scfg = (struct ccsr_scfg
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> + u32 usb_pwrfault;
> +
> +#ifdef CONFIG_HAS_FSL_XHCI_USB
> + out_be32(&scfg->rcwpmuxcr0, 0x);
> + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (SCFG_USBPWRFAULT_SHARED <<
> + SCFG_USBPWRFAULT_USB1_SHIFT);
> + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif
> +
> return 0;
> }
>
> --
> 2.1.0.27.g96db324
Reviewed-by: Mingkai Hu
Regards,
Mingkai
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Re: [U-Boot] [PATCH v4 4/4] qe: assgin pins to qe-hdlc
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, January 29, 2016 12:28 PM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v4 4/4] qe: assgin pins to qe-hdlc
>
> qe-hdlc and usb multi-use the pins, when set hwconfig=qe-hdlc, assign the
> pins to qe-hdlc, if not, assgin it to usb
>
> Signed-off-by: Zhao Qiang
> ---
> board/freescale/ls1043ardb/ls1043ardb.c | 53 ++-
> --
> 1 file changed, 43 insertions(+), 10 deletions(-)
>
> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
> b/board/freescale/ls1043ardb/ls1043ardb.c
> index c2d4887..7ba72f8 100644
> --- a/board/freescale/ls1043ardb/ls1043ardb.c
> +++ b/board/freescale/ls1043ardb/ls1043ardb.c
> @@ -114,18 +114,24 @@ int config_board_mux(void)
> struct ccsr_scfg *scfg = (struct ccsr_scfg
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> u32 usb_pwrfault;
>
> + if (hwconfig("qe-hdlc")) {
> + out_be32(&scfg->rcwpmuxcr0,
> + (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
> + printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
> +in_be32(&scfg->rcwpmuxcr0));
> + } else {
> #ifdef CONFIG_HAS_FSL_XHCI_USB
> - out_be32(&scfg->rcwpmuxcr0, 0x);
> - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB3_SHIFT) |
> - (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB2_SHIFT) |
> - (SCFG_USBPWRFAULT_SHARED <<
> - SCFG_USBPWRFAULT_USB1_SHIFT);
> - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
> + out_be32(&scfg->rcwpmuxcr0, 0x);
> + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (SCFG_USBPWRFAULT_SHARED <<
> + SCFG_USBPWRFAULT_USB1_SHIFT);
> + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
> #endif
> -
> + }
> return 0;
> }
>
> @@ -152,6 +158,16 @@ int misc_init_r(void) } #endif
>
> +void fdt_del_qe(void *blob)
> +{
> + int nodeoff = 0;
> +
> + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
> + "fsl,qe")) >= 0) {
> + fdt_del_node(blob, nodeoff);
> + }
> +}
> +
> int ft_board_setup(void *blob, bd_t *bd) {
> u64 base[CONFIG_NR_DRAM_BANKS];
> @@ -169,6 +185,23 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef
> CONFIG_SYS_DPAA_FMAN
> fdt_fixup_fman_ethernet(blob);
> #endif
> +
> + /*
> + * qe-hdlc and usb multi-use the pins,
> + * when set hwconfig to qe-hdlc, delete usb node.
> + */
> + if (hwconfig("qe-hdlc"))
> +#ifdef CONFIG_HAS_FSL_XHCI_USB
> + fdt_del_node_and_alias(blob, "usb1"); #endif
> + /*
> + * qe just support qe-uart and qe-hdlc,
> + * if qe-uart and qe-hdlc are not set in hwconfig,
> + * delete qe node.
> + */
> + if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
> + fdt_del_qe(blob);
> +
> return 0;
> }
>
> --
> 2.1.0.27.g96db324
Reviewed-by: Mingkai Hu
Regards,
Mingkai
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Re: [U-Boot] [PATCH v4 2/4] QE: add QE support on ls1043ardb
> -Original Message- > From: Zhao Qiang [mailto:qiang.z...@nxp.com] > Sent: Friday, January 29, 2016 12:28 PM > To: Mingkai Hu > Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao > Subject: [PATCH v4 2/4] QE: add QE support on ls1043ardb > > Upload qe microcode on ls1043ardb > > Signed-off-by: Zhao Qiang > --- > board/freescale/ls1043ardb/ls1043ardb.c | 8 > drivers/qe/qe.c | 6 ++ > include/configs/ls1043ardb.h| 7 +++ > 3 files changed, 17 insertions(+), 4 deletions(-) > > diff --git a/board/freescale/ls1043ardb/ls1043ardb.c > b/board/freescale/ls1043ardb/ls1043ardb.c > index c8f723a..834fdff 100644 > --- a/board/freescale/ls1043ardb/ls1043ardb.c > +++ b/board/freescale/ls1043ardb/ls1043ardb.c > @@ -21,6 +21,10 @@ > #include > #include > #include "cpld.h" > +#ifdef CONFIG_U_QE > +#include "../../../drivers/qe/qe.h" > +#endif > + > The patch submitted by Qianyu is trying to move qe.h to include/fsl_qe.h, It's better to based on this patch set to avoid the long include statement. http://patchwork.ozlabs.org/patch/572697/ Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8/ls1043a: Implement workaround for erratum A009660
> -Original Message-
> From: york sun
> Sent: Saturday, January 30, 2016 4:40 AM
> To: Mingkai Hu; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/25/2016 10:12 PM, Mingkai Hu wrote:
> >
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: Saturday, January 23, 2016 1:44 AM
> >> To: Mingkai Hu; Mingkai Hu; u-boot@lists.denx.de
> >> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> >> A009660
> >>
> >> On 01/21/2016 11:50 PM, Mingkai Hu wrote:
> >>>
> >>>
> >>>> -Original Message-
> >>>> From: Mingkai Hu
> >>>> Sent: Thursday, January 21, 2016 11:18 AM
> >>>> To: york sun; Mingkai Hu; u-boot@lists.denx.de
> >>>> Subject: RE: [PATCH] armv8/ls1043a: Implement workaround for
> >>>> erratum
> >>>> A009660
> >>>>
> >>>>
> >>>>
> >>>>> -Original Message-
> >>>>> From: york sun
> >>>>> Sent: Thursday, January 21, 2016 12:21 AM
> >>>>> To: Mingkai Hu; u-boot@lists.denx.de
> >>>>> Cc: Mingkai Hu
> >>>>> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for
> >>>>> erratum
> >>>>> A009660
> >>>>>
> >>>>> On 01/19/2016 10:44 PM, Mingkai Hu wrote:
> >>>>>> From: Mingkai Hu
> >>>>>>
> >>>>>> Memory controller performance is not optimal with default
> >>>>>> internal target queue register value, write required value for
> >>>>>> optimal DDR performance.
> >>>>>>
> >>>>>> Signed-off-by: Mingkai Hu
> >>>>>> ---
> >>>>>> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13
> >> +
> >>>>>> arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
> >>>>>> 2 files changed, 14 insertions(+)
> >>>>>>
> >>>>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>>> index 23d6b73..485f5cd 100644
> >>>>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>>>> @@ -210,6 +210,18 @@ static void erratum_a009929(void) #endif }
> >>>>>>
> >>>>>> +/*
> >>>>>> + * This erratum requires setting a value to eddrtqcr1 to
> >>>>>> + * optimal the DDR performance.
> >>>>>> + */
> >>>>>> +static void erratum_a009660(void) { #ifdef
> >>>>>> +CONFIG_SYS_FSL_ERRATUM_A009660
> >>>>>> + u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
> >>>>>> + out_be32(eddrtqcr1, 0x63b20042); #endif }
> >>>>>> +
> >>>>>> void fsl_lsch2_early_init_f(void) {
> >>>>>>struct ccsr_cci400 *cci = (struct ccsr_cci400
> >>>>>> *)CONFIG_SYS_CCI400_ADDR; @@ -232,6 +244,7 @@ void
> >>>>>> fsl_lsch2_early_init_f(void)
> >>>>>>
> >>>>>>/* Erratum */
> >>>>>>erratum_a009929();
> >>>>>> + erratum_a009660();
> >>>>>> }
> >>>>>> #endif
> >>>>>>
> >>>>>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>>>> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>>>> index 49b113d..66399b2 100644
> >>>>>> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>>>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>>>> @@ -167,6 +167,7 @@
> >>>>>> #define GICC_BASE 0x01402000
> >>>>>>
> >>>>>> #define CONFIG_SYS_FSL_ERRATUM_A009929
> >>>>>> +#define CONFIG_SYS_FSL_ERRATUM_A009660
> >>>>>> #else
> >>>>>> #error SoC not defined
> >>>>>> #endif
> >>>>>>
> >>>>>
> >>>>> NACK.
> >>>>>
> >>>>> Erratum A00
Re: [U-Boot] [PATCH v3 4/4] qe: assgin pins to qe-hdlc
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Friday, January 29, 2016 10:51 AM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v3 4/4] qe: assgin pins to qe-hdlc
>
> qe-hdlc and usb multi-use the pins, when set hwconfig=qe-hdlc, assign the
> pins to qe-hdlc, if not, assgin it to usb
>
> Signed-off-by: Zhao Qiang
> ---
> board/freescale/ls1043ardb/ls1043ardb.c | 51 ++-
> --
> 1 file changed, 41 insertions(+), 10 deletions(-)
>
> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
> b/board/freescale/ls1043ardb/ls1043ardb.c
> index c2d4887..a97a09a 100644
> --- a/board/freescale/ls1043ardb/ls1043ardb.c
> +++ b/board/freescale/ls1043ardb/ls1043ardb.c
> @@ -114,18 +114,24 @@ int config_board_mux(void)
> struct ccsr_scfg *scfg = (struct ccsr_scfg
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> u32 usb_pwrfault;
>
> + if (hwconfig("qe-hdlc")) {
> + out_be32(&scfg->rcwpmuxcr0,
> + (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
> + printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
> +in_be32(&scfg->rcwpmuxcr0));
> + } else {
> #ifdef CONFIG_HAS_FSL_XHCI_USB
> - out_be32(&scfg->rcwpmuxcr0, 0x);
> - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB3_SHIFT) |
> - (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB2_SHIFT) |
> - (SCFG_USBPWRFAULT_SHARED <<
> - SCFG_USBPWRFAULT_USB1_SHIFT);
> - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
> + out_be32(&scfg->rcwpmuxcr0, 0x);
> + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (SCFG_USBPWRFAULT_SHARED <<
> + SCFG_USBPWRFAULT_USB1_SHIFT);
> + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
> #endif
> -
> + }
> return 0;
> }
>
> @@ -152,6 +158,16 @@ int misc_init_r(void) } #endif
>
> +void fdt_del_qe(void *blob)
> +{
> + int nodeoff = 0;
> +
> + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
> + "fsl,qe")) >= 0) {
> + fdt_del_node(blob, nodeoff);
> + }
> +}
> +
> int ft_board_setup(void *blob, bd_t *bd) {
> u64 base[CONFIG_NR_DRAM_BANKS];
> @@ -169,6 +185,21 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef
> CONFIG_SYS_DPAA_FMAN
> fdt_fixup_fman_ethernet(blob);
> #endif
> +
> + /* qe-hdlc and usb multi-use the pins,
> + * when set hwconfig to qe-hdlc, delete usb node.
> + */
Use multiple lines comments.
/*
*
*/
> + if (hwconfig("qe-hdlc"))
> +#ifdef CONFIG_HAS_FSL_XHCI_USB
> + fdt_del_node_and_alias(blob, "usb1"); #endif
> + /* qe just support qe-uart and qe-hdlc,
> + * if qe-uart and qe-hdlc are not set in hwconfig,
> + * delete qe node.
> + */
Ditto.
> + if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
> + fdt_del_qe(blob);
> +
> return 0;
> }
>
> --
> 2.1.0.27.g96db324
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Re: [U-Boot] [PATCH] armv8/ls1043a: Implement workaround for erratum A009660
> -Original Message-
> From: york sun
> Sent: Saturday, January 23, 2016 1:44 AM
> To: Mingkai Hu; Mingkai Hu; u-boot@lists.denx.de
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/21/2016 11:50 PM, Mingkai Hu wrote:
> >
> >
> >> -----Original Message-
> >> From: Mingkai Hu
> >> Sent: Thursday, January 21, 2016 11:18 AM
> >> To: york sun; Mingkai Hu; u-boot@lists.denx.de
> >> Subject: RE: [PATCH] armv8/ls1043a: Implement workaround for erratum
> >> A009660
> >>
> >>
> >>
> >>> -Original Message-
> >>> From: york sun
> >>> Sent: Thursday, January 21, 2016 12:21 AM
> >>> To: Mingkai Hu; u-boot@lists.denx.de
> >>> Cc: Mingkai Hu
> >>> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> >>> A009660
> >>>
> >>> On 01/19/2016 10:44 PM, Mingkai Hu wrote:
> >>>> From: Mingkai Hu
> >>>>
> >>>> Memory controller performance is not optimal with default internal
> >>>> target queue register value, write required value for optimal DDR
> >>>> performance.
> >>>>
> >>>> Signed-off-by: Mingkai Hu
> >>>> ---
> >>>> arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13
> +
> >>>> arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
> >>>> 2 files changed, 14 insertions(+)
> >>>>
> >>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>> index 23d6b73..485f5cd 100644
> >>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>>> @@ -210,6 +210,18 @@ static void erratum_a009929(void) #endif }
> >>>>
> >>>> +/*
> >>>> + * This erratum requires setting a value to eddrtqcr1 to
> >>>> + * optimal the DDR performance.
> >>>> + */
> >>>> +static void erratum_a009660(void)
> >>>> +{
> >>>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
> >>>> +u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
> >>>> +out_be32(eddrtqcr1, 0x63b20042);
> >>>> +#endif
> >>>> +}
> >>>> +
> >>>> void fsl_lsch2_early_init_f(void)
> >>>> {
> >>>> struct ccsr_cci400 *cci = (struct ccsr_cci400
> >>>> *)CONFIG_SYS_CCI400_ADDR; @@ -232,6 +244,7 @@ void
> >>>> fsl_lsch2_early_init_f(void)
> >>>>
> >>>> /* Erratum */
> >>>> erratum_a009929();
> >>>> +erratum_a009660();
> >>>> }
> >>>> #endif
> >>>>
> >>>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>> index 49b113d..66399b2 100644
> >>>> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> >>>> @@ -167,6 +167,7 @@
> >>>> #define GICC_BASE 0x01402000
> >>>>
> >>>> #define CONFIG_SYS_FSL_ERRATUM_A009929
> >>>> +#define CONFIG_SYS_FSL_ERRATUM_A009660
> >>>> #else
> >>>> #error SoC not defined
> >>>> #endif
> >>>>
> >>>
> >>> NACK.
> >>>
> >>> Erratum A009660 is cancelled. The workaround is integrated into
> A008514.
> >>> Please revise workaround for A008514. Besides, you are using ARMv7
> >>> offset for ARMv8.
> >>> Please check if this workaround applies to LS2 SoCs. While you are
> >>> on it, please add a comment to LS1 workaround with the word A008514
> >>> so we can grep it.
> >>>
> >>
> >> Hi York,
> >>
> >> I discussed with design team and got the erratum in LS1043A CE before
> >> preparing the patch. The value (0x63b20042) is the same one described
> >> in
> >> A008514 of LS1021A and the register offset of LS1043A is same with
> >> the one used for LS1021A which is in the SCFG space.
> >>
> >> I will double check with the design team about if the erraum number
> >> is still A009660
Re: [U-Boot] [PATCH v2 3/3] QE: assgin pins to QE-HDLC
> -Original Message-
> From: Zhao Qiang [mailto:qiang.z...@nxp.com]
> Sent: Tuesday, January 26, 2016 9:20 AM
> To: Mingkai Hu
> Cc: tr...@konsulko.com; york sun; u-boot@lists.denx.de; Qiang Zhao
> Subject: [PATCH v2 3/3] QE: assgin pins to QE-HDLC
>
> qe-hdlc and usb multi-use the pins, when set hwconfig=qe-hdlc, assign the
> pins to qe-hdlc, if not, assgin it to usb
>
> Signed-off-by: Zhao Qiang
> ---
> Changes for v2:
> - NA
>
> board/freescale/ls1043ardb/ls1043ardb.c | 54 ---
> --
> 1 file changed, 39 insertions(+), 15 deletions(-)
>
> diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
> b/board/freescale/ls1043ardb/ls1043ardb.c
> index 834fdff..042a59f 100644
> --- a/board/freescale/ls1043ardb/ls1043ardb.c
> +++ b/board/freescale/ls1043ardb/ls1043ardb.c
> @@ -75,23 +75,8 @@ int dram_init(void)
>
> int board_early_init_f(void)
> {
> - struct ccsr_scfg *scfg = (struct ccsr_scfg
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> - u32 usb_pwrfault;
> -
> fsl_lsch2_early_init_f();
>
> -#ifdef CONFIG_HAS_FSL_XHCI_USB
> - out_be32(&scfg->rcwpmuxcr0, 0x);
> - out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> - usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB3_SHIFT) |
> - (SCFG_USBPWRFAULT_DEDICATED <<
> - SCFG_USBPWRFAULT_USB2_SHIFT) |
> - (SCFG_USBPWRFAULT_SHARED <<
> - SCFG_USBPWRFAULT_USB1_SHIFT);
> - out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
> -#endif
> -
> return 0;
> }
>
It's better to split this patch to two patches: the first one is to move the
USB config to config_board_mux,
The second patch is to add the qe-hdlc support. this is more clear.
> @@ -126,6 +111,27 @@ int board_init(void)
>
> int config_board_mux(void)
> {
> + struct ccsr_scfg *scfg = (struct ccsr_scfg
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> + u32 usb_pwrfault;
> +
> + if (hwconfig("qe-hdlc")) {
> + out_be32(&scfg->rcwpmuxcr0,
> + (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
> + printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
> +in_be32(&scfg->rcwpmuxcr0));
> + } else {
> +#ifdef CONFIG_HAS_FSL_XHCI_USB
> + out_be32(&scfg->rcwpmuxcr0, 0x);
> + out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
> + usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB3_SHIFT) |
> + (SCFG_USBPWRFAULT_DEDICATED <<
> + SCFG_USBPWRFAULT_USB2_SHIFT) |
> + (SCFG_USBPWRFAULT_SHARED <<
> + SCFG_USBPWRFAULT_USB1_SHIFT);
> + out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif
> + }
> return 0;
> }
>
> @@ -152,6 +158,16 @@ int misc_init_r(void) } #endif
>
> +void fdt_del_qe(void *blob)
> +{
> + int nodeoff = 0;
> +
> + while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
> + "fsl,qe")) >= 0) {
> + fdt_del_node(blob, nodeoff);
> + }
> +}
> +
> int ft_board_setup(void *blob, bd_t *bd) {
> u64 base[CONFIG_NR_DRAM_BANKS];
> @@ -169,6 +185,14 @@ int ft_board_setup(void *blob, bd_t *bd) #ifdef
> CONFIG_SYS_DPAA_FMAN
> fdt_fixup_fman_ethernet(blob);
> #endif
> +
> + if (hwconfig("qe-hdlc"))
> +#ifdef CONFIG_HAS_FSL_XHCI_USB
> + fdt_del_node_and_alias(blob, "usb1"); #endif
> + else if (!hwconfig("qe-uart"))
> + fdt_del_qe(blob);
> +
Can we change it to the following?
+ if (hwconfig("qe-hdlc") || hwconfig("qe-uart"))
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+ fdt_del_node_and_alias(blob, "usb1");
+#endif
+ else
+ fdt_del_qe(blob);
+
Thanks,
Mingkai
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Re: [U-Boot] [PATCH] armv8/ls1043a: Implement workaround for erratum A009660
> -Original Message-
> From: Mingkai Hu
> Sent: Thursday, January 21, 2016 11:18 AM
> To: york sun; Mingkai Hu; u-boot@lists.denx.de
> Subject: RE: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
>
>
> > -Original Message-
> > From: york sun
> > Sent: Thursday, January 21, 2016 12:21 AM
> > To: Mingkai Hu; u-boot@lists.denx.de
> > Cc: Mingkai Hu
> > Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> > A009660
> >
> > On 01/19/2016 10:44 PM, Mingkai Hu wrote:
> > > From: Mingkai Hu
> > >
> > > Memory controller performance is not optimal with default internal
> > > target queue register value, write required value for optimal DDR
> > > performance.
> > >
> > > Signed-off-by: Mingkai Hu
> > > ---
> > > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13 +
> > > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
> > > 2 files changed, 14 insertions(+)
> > >
> > > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > > index 23d6b73..485f5cd 100644
> > > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > > @@ -210,6 +210,18 @@ static void erratum_a009929(void) #endif }
> > >
> > > +/*
> > > + * This erratum requires setting a value to eddrtqcr1 to
> > > + * optimal the DDR performance.
> > > + */
> > > +static void erratum_a009660(void)
> > > +{
> > > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
> > > + u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
> > > + out_be32(eddrtqcr1, 0x63b20042);
> > > +#endif
> > > +}
> > > +
> > > void fsl_lsch2_early_init_f(void)
> > > {
> > > struct ccsr_cci400 *cci = (struct ccsr_cci400
> > > *)CONFIG_SYS_CCI400_ADDR; @@ -232,6 +244,7 @@ void
> > > fsl_lsch2_early_init_f(void)
> > >
> > > /* Erratum */
> > > erratum_a009929();
> > > + erratum_a009660();
> > > }
> > > #endif
> > >
> > > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > > b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > > index 49b113d..66399b2 100644
> > > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > > @@ -167,6 +167,7 @@
> > > #define GICC_BASE0x01402000
> > >
> > > #define CONFIG_SYS_FSL_ERRATUM_A009929
> > > +#define CONFIG_SYS_FSL_ERRATUM_A009660
> > > #else
> > > #error SoC not defined
> > > #endif
> > >
> >
> > NACK.
> >
> > Erratum A009660 is cancelled. The workaround is integrated into A008514.
> > Please revise workaround for A008514. Besides, you are using ARMv7
> > offset for ARMv8.
> > Please check if this workaround applies to LS2 SoCs. While you are on
> > it, please add a comment to LS1 workaround with the word A008514 so we
> > can grep it.
> >
>
> Hi York,
>
> I discussed with design team and got the erratum in LS1043A CE before
> preparing the patch. The value (0x63b20042) is the same one described in
> A008514 of LS1021A and the register offset of LS1043A is same with the
> one used for LS1021A which is in the SCFG space.
>
> I will double check with the design team about if the erraum number is
> still A009660 and keep you in the loop.
>
> For LS2, I got the A008514 in the LS2085A CE, but 1. The value is
> 63b2_0002 which is different from the value used on ls1043 platform.
> 2. The address is in DCFG space.
> 3. I did not get the A008514 in the LS2080A CE (RevD).
>
> So it's better to confirm with design team about the value used and the
> consistence between LS2085A and LS2080A.
>
York,
As discussed with design team, the erratum A009660 is the correct one and the
value/offset is also correct.
Do you prefer to submit a new patch to fix ls2085 or fix it on this patch?
> Thanks,
> Mingkai
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Re: [U-Boot] [PATCH] armv8/ls1043a: Implement workaround for erratum A009660
> -Original Message-
> From: york sun
> Sent: Thursday, January 21, 2016 12:21 AM
> To: Mingkai Hu; u-boot@lists.denx.de
> Cc: Mingkai Hu
> Subject: Re: [PATCH] armv8/ls1043a: Implement workaround for erratum
> A009660
>
> On 01/19/2016 10:44 PM, Mingkai Hu wrote:
> > From: Mingkai Hu
> >
> > Memory controller performance is not optimal with default internal
> > target queue register value, write required value for optimal DDR
> > performance.
> >
> > Signed-off-by: Mingkai Hu
> > ---
> > arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13 +
> > arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 23d6b73..485f5cd 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -210,6 +210,18 @@ static void erratum_a009929(void) #endif }
> >
> > +/*
> > + * This erratum requires setting a value to eddrtqcr1 to
> > + * optimal the DDR performance.
> > + */
> > +static void erratum_a009660(void)
> > +{
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
> > + u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
> > + out_be32(eddrtqcr1, 0x63b20042);
> > +#endif
> > +}
> > +
> > void fsl_lsch2_early_init_f(void)
> > {
> > struct ccsr_cci400 *cci = (struct ccsr_cci400
> > *)CONFIG_SYS_CCI400_ADDR; @@ -232,6 +244,7 @@ void
> > fsl_lsch2_early_init_f(void)
> >
> > /* Erratum */
> > erratum_a009929();
> > + erratum_a009660();
> > }
> > #endif
> >
> > diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > index 49b113d..66399b2 100644
> > --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> > @@ -167,6 +167,7 @@
> > #define GICC_BASE 0x01402000
> >
> > #define CONFIG_SYS_FSL_ERRATUM_A009929
> > +#define CONFIG_SYS_FSL_ERRATUM_A009660
> > #else
> > #error SoC not defined
> > #endif
> >
>
> NACK.
>
> Erratum A009660 is cancelled. The workaround is integrated into A008514.
> Please revise workaround for A008514. Besides, you are using ARMv7 offset
> for ARMv8.
> Please check if this workaround applies to LS2 SoCs. While you are on it,
> please add a comment to LS1 workaround with the word A008514 so we can
> grep it.
>
Hi York,
I discussed with design team and got the erratum in LS1043A CE before preparing
the patch. The value (0x63b20042) is the same one described in A008514 of
LS1021A and the register offset of LS1043A is same with the one used for
LS1021A which is in the SCFG space.
I will double check with the design team about if the erraum number is still
A009660 and keep you in the loop.
For LS2, I got the A008514 in the LS2085A CE, but
1. The value is 63b2_0002 which is different from the value used on ls1043
platform.
2. The address is in DCFG space.
3. I did not get the A008514 in the LS2080A CE (RevD).
So it's better to confirm with design team about the value used and the
consistence between LS2085A and LS2080A.
Thanks,
Mingkai
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[U-Boot] [PATCH] armv8/ls1043a: Implement workaround for erratum A009660
From: Mingkai Hu
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 13 +
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 23d6b73..485f5cd 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -210,6 +210,18 @@ static void erratum_a009929(void)
#endif
}
+/*
+ * This erratum requires setting a value to eddrtqcr1 to
+ * optimal the DDR performance.
+ */
+static void erratum_a009660(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
+ u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ out_be32(eddrtqcr1, 0x63b20042);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -232,6 +244,7 @@ void fsl_lsch2_early_init_f(void)
/* Erratum */
erratum_a009929();
+ erratum_a009660();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 49b113d..66399b2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -167,6 +167,7 @@
#define GICC_BASE 0x01402000
#define CONFIG_SYS_FSL_ERRATUM_A009929
+#define CONFIG_SYS_FSL_ERRATUM_A009660
#else
#error SoC not defined
#endif
--
2.1.0.27.g96db324
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Re: [U-Boot] [PATCH 3/4] armv8/ls1043aqds: Fix CONFIG_LPUART
> -Original Message- > From: Wenbin Song [mailto:wenbin.s...@nxp.com] > Sent: Tuesday, January 19, 2016 2:48 PM > To: york...@freescale.com; Mingkai Hu; Qianyu Gong; Shaohui Xie; Wenbin > Song; u-boot@lists.denx.de > Cc: songwenbin > Subject: [PATCH 3/4] armv8/ls1043aqds: Fix CONFIG_LPUART > > From: songwenbin > > If configured CONFIG_LPUART, should undefine the NS16550 > > Signed-off-by: Wenbin Song > --- > include/configs/ls1043aqds.h | 11 +++ > 1 file changed, 11 insertions(+) > > diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h > index 398f1c3..88f4bc0 100644 > --- a/include/configs/ls1043aqds.h > +++ b/include/configs/ls1043aqds.h > @@ -88,6 +88,17 @@ unsigned long get_board_ddr_clk(void); #define > CONFIG_SYS_FSL_PBL_RCW > board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg > #endif > > +/* > + * LPUART > + */ > +#ifdef CONFIG_LPUART > +#define CONFIG_FSL_LPUART > +#define CONFIG_LPUART_32B_REG > +#undef CONFIG_CONS_INDEX > +#undef CONFIG_SYS_NS16550_SERIAL > +#undef CONFIG_SYS_NS16550_CLK > +#endif > + > /* SATA */ > #define CONFIG_LIBATA > #define CONFIG_SCSI_AHCI > -- > 2.1.0.27.g96db324 It's better to rephrase tile to "armv8/ls1043aqds: add LPUART support"? And give more information about "undefine the NS16550" in commit message. Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] armv8/ls1043aqds: added lpuart support
> -Original Message-
> From: Wenbin Song [mailto:wenbin.s...@nxp.com]
> Sent: Tuesday, January 19, 2016 2:48 PM
> To: york...@freescale.com; Mingkai Hu; Qianyu Gong; Shaohui Xie; Wenbin
> Song; u-boot@lists.denx.de
> Subject: [PATCH 1/4] armv8/ls1043aqds: added lpuart support
>
> From: Shaohui Xie
>
> Signed-off-by: Shaohui Xie
> Signed-off-by: Mingkai Hu
> ---
> board/freescale/ls1043aqds/ls1043aqds.c | 15 +++
> 1 file changed, 15 insertions(+)
>
> diff --git a/board/freescale/ls1043aqds/ls1043aqds.c
> b/board/freescale/ls1043aqds/ls1043aqds.c
> index d6696ca..1da3fe1 100644
> --- a/board/freescale/ls1043aqds/ls1043aqds.c
> +++ b/board/freescale/ls1043aqds/ls1043aqds.c
> @@ -40,6 +40,9 @@ enum {
> #define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
> #define CFG_SD_MUX4_SLOT30x0 /* SLOT3 TX/RX1 */
> #define CFG_SD_MUX4_SLOT10x1 /* SLOT1 TX/RX3 */
> +#define CFG_UART_MUX_MASK0x6
> +#define CFG_UART_MUX_SHIFT 1
> +#define CFG_LPUART_EN0x1
>
> int checkboard(void)
> {
> @@ -218,7 +221,19 @@ void board_retimer_init(void)
>
> int board_early_init_f(void)
> {
> +#ifdef CONFIG_LPUART
> + u8 uart;
> +#endif
> fsl_lsch2_early_init_f();
> +#ifdef CONFIG_LPUART
> + /*FIXME: need to check which lpuart is enabled in rcw, for now
> + * we use lpuart1.
> + */
> + uart = QIXIS_READ(brdcfg[14]);
> + uart &= ~CFG_UART_MUX_MASK;
> + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
> + QIXIS_WRITE(brdcfg[14], uart);
> +#endif
>
Please use the RCW to check which LPUART is enabled.
Thanks,
Mingkai
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[U-Boot] [PATCH 4/5] armv8/ls1043ardb: change core frequency to 1600MHz
For SD boot and NAND boot.
Signed-off-by: Mingkai Hu
---
board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg | 4 ++--
board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
index 935ffc0..d87058b 100644
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
-081f 0c00
-14550002 80004012 e0106000 61002000
+08100010 0a00
+14550002 80004012 e0106000 c1002000
00038800
1100 0096 0001
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
index 28cd958..e2ee34b 100644
--- a/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
-081f 0c00
-14550002 80004012 6004 61002000
+08100010 0a00
+14550002 80004012 6004 c1002000
00038800
1100 0096 0001
--
2.1.0.27.g96db324
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[U-Boot] [PATCH 2/5] armv8/fsl_lsch2: fix DCSR_DCFG address
Signed-off-by: Mingkai Hu --- arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 83caa91..3869177 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -11,7 +11,7 @@ #define CONFIG_SYS_IMMR0x0100 #define CONFIG_SYS_DCSRBAR 0x2000 -#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x0022) +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x0014) #define CONFIG_SYS_FSL_DDR_ADDR(CONFIG_SYS_IMMR + 0x0008) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018) -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] armv8/ls1043a: remove print info
Signed-off-by: Mingkai Hu
---
drivers/net/fm/ls1043.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c
index cf2cc95..93ba318 100644
--- a/drivers/net/fm/ls1043.c
+++ b/drivers/net/fm/ls1043.c
@@ -54,11 +54,8 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
- if (is_device_disabled(port)) {
- printf("%s:%d: port(%d) is disabled\n", __func__,
- __LINE__, port);
+ if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
- }
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9)))
return PHY_INTERFACE_MODE_XGMII;
@@ -69,15 +66,11 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
if (port == FM1_DTSEC3)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) ==
FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) {
- printf("%s:%d: port(FM1_DTSEC3) is OK\n",
- __func__, __LINE__);
return PHY_INTERFACE_MODE_RGMII;
}
if (port == FM1_DTSEC4)
if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) ==
FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) {
- printf("%s:%d: port(FM1_DTSEC4) is OK\n",
- __func__, __LINE__);
return PHY_INTERFACE_MODE_RGMII;
}
--
2.1.0.27.g96db324
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[U-Boot] [PATCH 3/5] armv8/ls1043a: Implement workaround for PEX erratum A009929
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c| 16
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 1 +
3 files changed, 18 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8896b70..b76e5ad 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -121,6 +121,19 @@ void fsl_lsch3_early_init_f(void)
}
#elif defined(CONFIG_LS1043A)
+static void erratum_a009929(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
+ struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+ u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
+ u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
+
+ rstrqmr1 |= 0x0400;
+ gur_out32(&gur->rstrqmr1, rstrqmr1);
+ writel(0x0100, dcsr_cop_ccp);
+#endif
+}
+
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
@@ -135,6 +148,9 @@ void fsl_lsch2_early_init_f(void)
*/
out_le32(&cci->slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
+
+ /* Erratum */
+ erratum_a009929();
}
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index b5a2d28..f744303 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -160,6 +160,7 @@
#define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000
+#define CONFIG_SYS_FSL_ERRATUM_A009929
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 3869177..364485e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -12,6 +12,7 @@
#define CONFIG_SYS_IMMR0x0100
#define CONFIG_SYS_DCSRBAR 0x2000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x0014)
+#define CONFIG_SYS_DCSR_COP_CCP_ADDR (CONFIG_SYS_DCSRBAR + 0x02008040)
#define CONFIG_SYS_FSL_DDR_ADDR(CONFIG_SYS_IMMR +
0x0008)
#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x0018)
--
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[U-Boot] [PATCH 5/5] armv8/ls1043aqds: change core frequency to 1600MHz
For SD boot and NAND boot.
Signed-off-by: Mingkai Hu
---
board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg | 4 ++--
board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
index 935ffc0..d87058b 100644
--- a/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
@@ -1,7 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
-081f 0c00
-14550002 80004012 e0106000 61002000
+08100010 0a00
+14550002 80004012 e0106000 c1002000
00038800
1100 0096 0001
diff --git a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
index 17a5dd0..b6b5e0b 100644
--- a/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
+++ b/board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
@@ -2,7 +2,7 @@
aa55aa55 01ee0100
# RCW
# Enable IFC; disable QSPI
-081f 0c00
-14550002 80004012 6004 61002000
+08100010 0a00
+14550002 80004012 6004 c1002000
00038800
1100 0096 0001
--
2.1.0.27.g96db324
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[U-Boot] [PATCH] armv8/ls1043ardb: Add support for >2GB memory
From: Shaohui Xie
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie
Signed-off-by: Mingkai Hu
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ++--
board/freescale/ls1043ardb/ddr.c | 9 -
board/freescale/ls1043ardb/ls1043ardb.c | 10 ++
include/configs/ls1043a_common.h | 1 +
include/configs/ls1043ardb.h | 2 +-
5 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..aba360e 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -103,8 +103,8 @@
#define CONFIG_SYS_FSL_OCRAM_BASE 0x1000 /* initial RAM */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x20 /* 2 MiB */
#define CONFIG_SYS_FSL_DDR_BE
-#define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
-#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE
+#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
#define CONFIG_SYS_FSL_CCSR_GUR_BE
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c
index b181579..249d056 100644
--- a/board/freescale/ls1043ardb/ddr.c
+++ b/board/freescale/ls1043ardb/ddr.c
@@ -187,5 +187,12 @@ phys_size_t initdram(int board_type)
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
+ if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
+ gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
+ gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+ gd->bd->bi_dram[1].size = gd->ram_size -
+ CONFIG_SYS_DDR_BLOCK1_SIZE;
+ } else {
+ gd->bd->bi_dram[0].size = gd->ram_size;
+ }
}
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c
b/board/freescale/ls1043ardb/ls1043ardb.c
index 9032ed3..c4f2603 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -114,6 +114,16 @@ int misc_init_r(void)
int ft_board_setup(void *blob, bd_t *bd)
{
+ u64 base[CONFIG_NR_DRAM_BANKS];
+ u64 size[CONFIG_NR_DRAM_BANKS];
+
+ /* fixup DT for the two DDR banks */
+ base[0] = gd->bd->bi_dram[0].start;
+ size[0] = gd->bd->bi_dram[0].size;
+ base[1] = gd->bd->bi_dram[1].start;
+ size[1] = gd->bd->bi_dram[1].size;
+
+ fdt_fixup_memory_banks(blob, base, size, 2);
ft_cpu_setup(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 6b9856a..677d281 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -44,6 +44,7 @@
#define CONFIG_SYS_DDR_SDRAM_BASE 0x8000
#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_DDR_BLOCK2_BASE 0x88000ULL
#define CPU_RELEASE_ADDR secondary_boot_func
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 307d947..acffe6e 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -27,7 +27,7 @@
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
/* Physical Memory Map */
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
-#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SPD_BUS_NUM 0
--
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[U-Boot] [PATCH] e1000: support 64bit physical address
Signed-off-by: Mingkai Hu --- drivers/net/e1000.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index d5d48b1..e816410 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -4980,8 +4980,8 @@ e1000_configure_tx(struct e1000_hw *hw) unsigned long tipg, tarc; uint32_t ipgr1, ipgr2; - E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base); - E1000_WRITE_REG(hw, TDBAH, 0); + E1000_WRITE_REG(hw, TDBAL, (unsigned long)tx_base & 0x); + E1000_WRITE_REG(hw, TDBAH, (unsigned long)tx_base >> 32); E1000_WRITE_REG(hw, TDLEN, 128); @@ -5124,8 +5124,8 @@ e1000_configure_rx(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } /* Setup the Base and Length of the Rx Descriptor Ring */ - E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base); - E1000_WRITE_REG(hw, RDBAH, 0); + E1000_WRITE_REG(hw, RDBAL, (unsigned long)rx_base & 0x); + E1000_WRITE_REG(hw, RDBAH, (unsigned long)rx_base >> 32); E1000_WRITE_REG(hw, RDLEN, 128); -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2] powerpc/c29xpcie: Add secure boot support
From: Po Liu Add NOR and SPI flash secure boot target for C29XPCIE board. Signed-off-by: Po Liu Signed-off-by: Mingkai.Hu --- board/freescale/c29xpcie/MAINTAINERS| 2 ++ configs/C29XPCIE_NOR_SECBOOT_defconfig | 4 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 4 include/configs/C29XPCIE.h | 2 ++ 4 files changed, 12 insertions(+) create mode 100644 configs/C29XPCIE_NOR_SECBOOT_defconfig create mode 100644 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig diff --git a/board/freescale/c29xpcie/MAINTAINERS b/board/freescale/c29xpcie/MAINTAINERS index db2e5e3..3308839 100644 --- a/board/freescale/c29xpcie/MAINTAINERS +++ b/board/freescale/c29xpcie/MAINTAINERS @@ -6,3 +6,5 @@ F: include/configs/C29XPCIE.h F: configs/C29XPCIE_defconfig F: configs/C29XPCIE_NAND_defconfig F: configs/C29XPCIE_SPIFLASH_defconfig +F: configs/C29XPCIE_NOR_SECBOOT_defconfig +F: configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig new file mode 100644 index 000..86751cf --- /dev/null +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig new file mode 100644 index 000..d1a42b2 --- /dev/null +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 5d11278..1d8dce8 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -579,4 +579,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + #endif /* __CONFIG_H */ -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/c29xpcie: Add secure boot support
From: Po Liu Add NOR and SPI flash secure boot target for C29XPCIE board. Signed-off-by: Po Liu Signed-off-by: Mingkai.Hu --- configs/C29XPCIE_NOR_SECBOOT_defconfig | 4 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig | 4 include/configs/C29XPCIE.h | 2 ++ 3 files changed, 10 insertions(+) create mode 100644 configs/C29XPCIE_NOR_SECBOOT_defconfig create mode 100644 configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig diff --git a/configs/C29XPCIE_NOR_SECBOOT_defconfig b/configs/C29XPCIE_NOR_SECBOOT_defconfig new file mode 100644 index 000..86751cf --- /dev/null +++ b/configs/C29XPCIE_NOR_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig new file mode 100644 index 000..d1a42b2 --- /dev/null +++ b/configs/C29XPCIE_SPIFLASH_SECBOOT_defconfig @@ -0,0 +1,4 @@ +CONFIG_SYS_EXTRA_OPTIONS="C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT" +CONFIG_PPC=y +CONFIG_MPC85xx=y +CONFIG_TARGET_C29XPCIE=y diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 5d11278..1d8dce8 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -579,4 +579,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + #endif /* __CONFIG_H */ -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/c29xpcie: Add secure boot support
From: Po Liu Add NOR and SPI flash secure boot target for C29XPCIE board. Signed-off-by: Po Liu Signed-off-by: Mingkai.Hu --- boards.cfg | 2 ++ include/configs/C29XPCIE.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/boards.cfg b/boards.cfg index 853446c..b2328ec 100644 --- a/boards.cfg +++ b/boards.cfg @@ -769,6 +769,8 @@ Active powerpc mpc85xx- freescale bsc9132qds Active powerpc mpc85xx- freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu Active powerpc mpc85xx- freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu Active powerpc mpc85xx- freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu +Active powerpc mpc85xx- freescale c29xpcie C29XPCIE_SECBOOT C29XPCIE:C29XPCIE,36BIT,SECURE_BOOT Po Liu +Active powerpc mpc85xx- freescale c29xpcie C29XPCIE_SPIFLASH_SECBOOT C29XPCIE:C29XPCIE,36BIT,SPIFLASH,SECURE_BOOT Po Liu Active powerpc mpc85xx- freescale corenet_ds P3041DS - - Active powerpc mpc85xx- freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF4 - Active powerpc mpc85xx- freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF4 - diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index be91704..dea6e87 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -576,4 +576,6 @@ #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND +#include + #endif /* __CONFIG_H */ -- 2.1.0.27.g96db324 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2] sf: Add support for flag status register on Micron chips
From: Mingkai Hu
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode
after reboot.
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag status register to check some
operations completion.
Signed-off-by: Mingkai.Hu
---
V1:
Based on git://git.denx.de/u-boot.git.
Tested on board T2080QDS and T2080RDB.
V2:
Add the operation of enter 3 Byte address mode in probe.
drivers/mtd/spi/sf_internal.h | 17
drivers/mtd/spi/sf_ops.c | 64 +--
drivers/mtd/spi/sf_probe.c| 5
3 files changed, 78 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 19d4914..49e5a2c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -36,6 +36,11 @@
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_CLEAR_FLAG_STATUS 0x50
+
+/* Used for Macronix and Winbond flashes */
+#defineCMD_ENTER_4B_ADDR 0xB7
+#defineCMD_EXIT_4B_ADDR0xE9
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -59,6 +64,8 @@
#define STATUS_QEB_WINSPAN (1 << 1)
#define STATUS_QEB_MXIC(1 << 6)
#define STATUS_PEC (1 << 7)
+#define STATUS_PROT(1 << 1)
+#define STATUS_ERASE (1 << 5)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
#define STATUS_SRWD(1 << 7) /* SR write protect */
@@ -124,6 +131,12 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash->spi, CMD_CLEAR_FLAG_STATUS, NULL, 0);
+}
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
@@ -160,4 +173,8 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data);
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 85cf22d..8a532b8 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8
wc)
}
#endif
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable)
+{
+ int ret;
+ u8 cmd;
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ return spi_flash_cmd(flash->spi, cmd, NULL, 0);
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
@@ -160,6 +184,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
u8 poll_bit = STATUS_WIP;
@@ -186,22 +211,45 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, &status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status & poll_bit) == check_status)
+ if ((status & poll_bit) == check_status) {
+ out_of_time = 0;
break;
+ }
} while (get_timer(timebase) < timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status & poll_bit) == check_status)
- return 0;
+ if (out_of_time) {
+ /* Timed out */
+ debug("SF: time out!\n");
+ if (cmd == CMD_FLAG_STATUS) {
+ if (spi_flash_cmd_clear_flag_status(flash) < 0)
+ debug("SF: clear flag status failed\n");
+
[U-Boot] [PATCH V2] sf: Add support for flag status register on Micron chips
From: Mingkai Hu
Enter 3 Byte address mode at first, because it may change to 4 Byte
address mode in kernel driver and not reset to 3 Byte address mode
after reboot.
Add clear flag status register operation that some Micron SPI flash
chips required after reading the flag status register to check some
operations completion.
Signed-off-by: Mingkai.Hu
---
V1:
Based on git://git.denx.de/u-boot.git.
Tested on board T2080QDS and T2080RDB.
V2:
Add the operation of enter 3 Byte address mode in probe.
drivers/mtd/spi/sf_internal.h | 17
drivers/mtd/spi/sf_ops.c | 64 +--
drivers/mtd/spi/sf_probe.c| 5
3 files changed, 78 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 19d4914..49e5a2c 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -36,6 +36,11 @@
#define CMD_WRITE_ENABLE 0x06
#define CMD_READ_CONFIG0x35
#define CMD_FLAG_STATUS0x70
+#define CMD_CLEAR_FLAG_STATUS 0x50
+
+/* Used for Macronix and Winbond flashes */
+#defineCMD_ENTER_4B_ADDR 0xB7
+#defineCMD_EXIT_4B_ADDR0xE9
/* Read commands */
#define CMD_READ_ARRAY_SLOW0x03
@@ -59,6 +64,8 @@
#define STATUS_QEB_WINSPAN (1 << 1)
#define STATUS_QEB_MXIC(1 << 6)
#define STATUS_PEC (1 << 7)
+#define STATUS_PROT(1 << 1)
+#define STATUS_ERASE (1 << 5)
#ifdef CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
#define STATUS_SRWD(1 << 7) /* SR write protect */
@@ -124,6 +131,12 @@ static inline int spi_flash_cmd_write_disable(struct
spi_flash *flash)
return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Clear flag status register */
+static inline int spi_flash_cmd_clear_flag_status(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash->spi, CMD_CLEAR_FLAG_STATUS, NULL, 0);
+}
+
/*
* Send the read status command to the device and wait for the wip
* (write-in-progress) bit to clear itself.
@@ -160,4 +173,8 @@ int spi_flash_read_common(struct spi_flash *flash, const u8
*cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data);
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable);
+#endif
+
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 85cf22d..8a532b8 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -93,6 +93,30 @@ int spi_flash_cmd_write_config(struct spi_flash *flash, u8
wc)
}
#endif
+#if defined(CONFIG_SPI_FLASH_STMICRO)
+int spi_flash_cmd_4B_addr_switch(struct spi_flash *flash, int enable)
+{
+ int ret;
+ u8 cmd;
+
+ cmd = enable ? CMD_ENTER_4B_ADDR : CMD_EXIT_4B_ADDR;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ return spi_flash_cmd(flash->spi, cmd, NULL, 0);
+}
+#endif
+
#ifdef CONFIG_SPI_FLASH_BAR
static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
{
@@ -160,6 +184,7 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
unsigned long timebase;
unsigned long flags = SPI_XFER_BEGIN;
int ret;
+ int out_of_time = 1;
u8 status;
u8 check_status = 0x0;
u8 poll_bit = STATUS_WIP;
@@ -186,22 +211,45 @@ int spi_flash_cmd_wait_ready(struct spi_flash *flash,
unsigned long timeout)
WATCHDOG_RESET();
ret = spi_xfer(spi, 8, NULL, &status, 0);
- if (ret)
+ if (ret) {
+ spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
return -1;
+ }
- if ((status & poll_bit) == check_status)
+ if ((status & poll_bit) == check_status) {
+ out_of_time = 0;
break;
+ }
} while (get_timer(timebase) < timeout);
spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
- if ((status & poll_bit) == check_status)
- return 0;
+ if (out_of_time) {
+ /* Timed out */
+ debug("SF: time out!\n");
+ if (cmd == CMD_FLAG_STATUS) {
+ if (spi_flash_cmd_clear_flag_status(flash) < 0)
+ debug("SF: clear flag status failed\n");
+
[U-Boot] [PATCH v2] fsl_ifc: add support for different IFC bank count
From: Mingkai Hu
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. Move ifc bank count to config_mpc85xx.h to support 8 bank count
3. Guard fsl_ifc.h with CONFIG_FSL_IFC macro to eliminate the compile
error on some devices that does not have IFC controller.
Signed-off-by: Mingkai Hu
---
arch/powerpc/cpu/mpc8xxx/fsl_ifc.c| 58 ++-
arch/powerpc/include/asm/config_mpc85xx.h | 7 +++
arch/powerpc/include/asm/fsl_ifc.h| 95 +--
3 files changed, 128 insertions(+), 32 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
index 56b319f..f0da355 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -26,7 +26,7 @@ void print_ifc_regs(void)
int i, j;
printf("IFC Controller Registers\n");
- for (i = 0; i < FSL_IFC_BANK_COUNT; i++) {
+ for (i = 0; i < CONFIG_SYS_FSL_IFC_BANK_COUNT; i++) {
printf("CSPR%d:0x%08X\tAMASK%d:0x%08X\tCSOR%d:0x%08X\n",
i, get_ifc_cspr(i), i, get_ifc_amask(i),
i, get_ifc_csor(i));
@@ -94,4 +94,60 @@ void init_early_memctl_regs(void)
set_ifc_amask(IFC_CS3, CONFIG_SYS_AMASK3);
set_ifc_csor(IFC_CS3, CONFIG_SYS_CSOR3);
#endif
+
+#ifdef CONFIG_SYS_CSPR4_EXT
+ set_ifc_cspr_ext(IFC_CS4, CONFIG_SYS_CSPR4_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR4) && defined(CONFIG_SYS_CSOR4)
+ set_ifc_ftim(IFC_CS4, IFC_FTIM0, CONFIG_SYS_CS4_FTIM0);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM1, CONFIG_SYS_CS4_FTIM1);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM2, CONFIG_SYS_CS4_FTIM2);
+ set_ifc_ftim(IFC_CS4, IFC_FTIM3, CONFIG_SYS_CS4_FTIM3);
+
+ set_ifc_cspr(IFC_CS4, CONFIG_SYS_CSPR4);
+ set_ifc_amask(IFC_CS4, CONFIG_SYS_AMASK4);
+ set_ifc_csor(IFC_CS4, CONFIG_SYS_CSOR4);
+#endif
+
+#ifdef CONFIG_SYS_CSPR5_EXT
+ set_ifc_cspr_ext(IFC_CS5, CONFIG_SYS_CSPR5_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR5) && defined(CONFIG_SYS_CSOR5)
+ set_ifc_ftim(IFC_CS5, IFC_FTIM0, CONFIG_SYS_CS5_FTIM0);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM1, CONFIG_SYS_CS5_FTIM1);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM2, CONFIG_SYS_CS5_FTIM2);
+ set_ifc_ftim(IFC_CS5, IFC_FTIM3, CONFIG_SYS_CS5_FTIM3);
+
+ set_ifc_cspr(IFC_CS5, CONFIG_SYS_CSPR5);
+ set_ifc_amask(IFC_CS5, CONFIG_SYS_AMASK5);
+ set_ifc_csor(IFC_CS5, CONFIG_SYS_CSOR5);
+#endif
+
+#ifdef CONFIG_SYS_CSPR6_EXT
+ set_ifc_cspr_ext(IFC_CS6, CONFIG_SYS_CSPR6_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR6) && defined(CONFIG_SYS_CSOR6)
+ set_ifc_ftim(IFC_CS6, IFC_FTIM0, CONFIG_SYS_CS6_FTIM0);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM1, CONFIG_SYS_CS6_FTIM1);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM2, CONFIG_SYS_CS6_FTIM2);
+ set_ifc_ftim(IFC_CS6, IFC_FTIM3, CONFIG_SYS_CS6_FTIM3);
+
+ set_ifc_cspr(IFC_CS6, CONFIG_SYS_CSPR6);
+ set_ifc_amask(IFC_CS6, CONFIG_SYS_AMASK6);
+ set_ifc_csor(IFC_CS6, CONFIG_SYS_CSOR6);
+#endif
+
+#ifdef CONFIG_SYS_CSPR7_EXT
+ set_ifc_cspr_ext(IFC_CS7, CONFIG_SYS_CSPR7_EXT);
+#endif
+#if defined(CONFIG_SYS_CSPR7) && defined(CONFIG_SYS_CSOR7)
+ set_ifc_ftim(IFC_CS7, IFC_FTIM0, CONFIG_SYS_CS7_FTIM0);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM1, CONFIG_SYS_CS7_FTIM1);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM2, CONFIG_SYS_CS7_FTIM2);
+ set_ifc_ftim(IFC_CS7, IFC_FTIM3, CONFIG_SYS_CS7_FTIM3);
+
+ set_ifc_cspr(IFC_CS7, CONFIG_SYS_CSPR7);
+ set_ifc_amask(IFC_CS7, CONFIG_SYS_AMASK7);
+ set_ifc_csor(IFC_CS7, CONFIG_SYS_CSOR7);
+#endif
}
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 68ca871..1601c72 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -139,6 +139,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
@@ -494,6 +495,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -506,6 +508,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70
#define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
@@ -530,6 +533,7 @@
#define CONFIG_SYS_NUM_FM2_10GEC 2
#define CONFIG_NUM_DDR_CONTROLLERS
[U-Boot] [PATCH] powerpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t
To avoid sign extension problem, use explicit casting to cast the SDRAM size to type phys_size_t, or else, if the SDRAM size is 2G(0x8000), it will be extended to 0x8000 when phys_size_t is type 'unsigned long long'. Signed-off-by: Mingkai Hu --- Based on master branch of git://git.denx.de/u-boot.git Also can apply direcly to git://www.denx.de/git/u-boot-mpc85xx.git arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index df2ab6d..ee6fac3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -339,7 +339,7 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) return fsl_ddr_sdram_size(); #else - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif } #else /* CONFIG_SYS_RAMBOOT */ -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powpc/mpc85xx: explicit cast the SDRAM size to type phys_size_t
To avoid sign extension problem, use explicit casting to cast the SDRAM size to type phys_size_t, or else, if the SDRAM size is 2G(0x8000), it will be extended to 0x8000 when phys_size_t is type 'unsigned long long'. Signed-off-by: Mingkai Hu --- Based on master branch of git://git.denx.de/u-boot.git Also can apply direcly to git://www.denx.de/git/u-boot-mpc85xx.git arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index df2ab6d..ee6fac3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -339,7 +339,7 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) return fsl_ddr_sdram_size(); #else - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; #endif } #else /* CONFIG_SYS_RAMBOOT */ -- 1.8.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][Upstream] cmd_sf: include header file common.h before div64.h
The header file div64.h includes which defines the phys_addr_t according to the macro CONFIG_PHYS_64BIT, while the macro CONFIG_PHYS_64BIT is included in common.h which comes after div64.h, so in order to get consistent type definition for phys_addr_t, common.h should be included before div64.h, Or else, the parameters of phys_addr_t type will be passed wrongly when CONFIG_PHYS_64BIT is defined. Signed-off-by: Mingkai Hu --- Based on master branch of git://git.denx.de/u-boot.git Also can apply direcly to git://www.denx.de/git/u-boot-mpc85xx.git Tested on P2041RDB board. common/cmd_sf.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_sf.c b/common/cmd_sf.c index b175358..bd3c508 100644 --- a/common/cmd_sf.c +++ b/common/cmd_sf.c @@ -5,8 +5,8 @@ * Licensed under the GPL-2 or later. */ -#include #include +#include #include #include -- 1.7.5.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] phylib: Enable SMSC LAN87xx PHY support
LAN8720 PHY is used on Freescale C2X0QDS board. Signed-off-by: Mingkai Hu diff --git a/include/config_phylib_all_drivers.h b/include/config_phylib_all_drivers.h index 1db7cec..12828c6 100644 --- a/include/config_phylib_all_drivers.h +++ b/include/config_phylib_all_drivers.h @@ -23,6 +23,7 @@ #define CONFIG_PHY_NATSEMI #define CONFIG_PHY_LXT #define CONFIG_PHY_ATHEROS +#define CONFIG_PHY_SMSC #ifdef CONFIG_PHYLIB_10G #define CONFIG_PHY_TERANETICS -- 1.7.5.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/p2041rdb: Enable SATA support
Signed-off-by: Mingkai Hu --- include/configs/P2041RDB.h | 20 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 63c8123..918f1b9 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -457,6 +457,26 @@ #define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ +/* SATA */ +#define CONFIG_FSL_SATA_V2 +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 -- 1.7.5.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] powerpc/p2040rdb: Add p2040rdb board support
P2040RDB Specification: --- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu --- v2: - Fix some warning of checkpatch.pl, such as "line over 80 characters". board/freescale/p2040rdb/Makefile | 56 board/freescale/p2040rdb/cpld.c | 171 ++ board/freescale/p2040rdb/cpld.h | 53 +++ board/freescale/p2040rdb/ddr.c | 115 +++ board/freescale/p2040rdb/law.c | 37 ++ board/freescale/p2040rdb/p2040rdb.c | 205 board/freescale/p2040rdb/pci.c | 39 +++ board/freescale/p2040rdb/tlb.c | 119 +++ boards.cfg |3 + doc/README.p2040rdb | 123 +++ include/configs/P2040RDB.h | 624 +++ 11 files changed, 1545 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p2040rdb/Makefile create mode 100644 board/freescale/p2040rdb/cpld.c create mode 100644 board/freescale/p2040rdb/cpld.h create mode 100644 board/freescale/p2040rdb/ddr.c create mode 100644 board/freescale/p2040rdb/law.c create mode 100644 board/freescale/p2040rdb/p2040rdb.c create mode 100644 board/freescale/p2040rdb/pci.c create mode 100644 board/freescale/p2040rdb/tlb.c create mode 100644 doc/README.p2040rdb create mode 100644 include/configs/P2040RDB.h diff --git a/board/freescale/p2040rdb/Makefile b/board/freescale/p2040rdb/Makefile new file mode 100644 index 000..65f348f --- /dev/null +++ b/board/freescale/p2040rdb/Makefile @@ -0,0 +1,56 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y+= $(BOARD).o +COBJS-y += cpld.o +COBJS-y+= ddr.o +COBJS-y+= law.o +COBJS-y+= tlb.o +COBJS-$(CONFIG_PCI) += pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/p2040rdb/cpld.c b/board/freescale/p2040rdb/cpld.c new file mode 100644 index 000..8e1f46e --- /dev/null +++ b/board/freescale/p2040rdb/cpld.c @@ -0,0 +1,171 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CPLD_BASE - The virtual address of the base of the CPLD register map + * + */ + +#include
[U-Boot] [PATCH] powerpc/p2040rdb: Add p2040rdb board support
P2040RDB Specification: --- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu --- Based on http://git.denx.de/?p=u-boot/u-boot-mpc85xx.git;a=shortlog;h=refs/heads/next board/freescale/p2040rdb/Makefile | 56 board/freescale/p2040rdb/cpld.c | 171 ++ board/freescale/p2040rdb/cpld.h | 53 +++ board/freescale/p2040rdb/ddr.c | 115 +++ board/freescale/p2040rdb/law.c | 37 ++ board/freescale/p2040rdb/p2040rdb.c | 204 board/freescale/p2040rdb/pci.c | 39 +++ board/freescale/p2040rdb/tlb.c | 119 +++ boards.cfg |3 + doc/README.p2040rdb | 123 +++ include/configs/P2040RDB.h | 617 +++ 11 files changed, 1537 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p2040rdb/Makefile create mode 100644 board/freescale/p2040rdb/cpld.c create mode 100644 board/freescale/p2040rdb/cpld.h create mode 100644 board/freescale/p2040rdb/ddr.c create mode 100644 board/freescale/p2040rdb/law.c create mode 100644 board/freescale/p2040rdb/p2040rdb.c create mode 100644 board/freescale/p2040rdb/pci.c create mode 100644 board/freescale/p2040rdb/tlb.c create mode 100644 doc/README.p2040rdb create mode 100644 include/configs/P2040RDB.h diff --git a/board/freescale/p2040rdb/Makefile b/board/freescale/p2040rdb/Makefile new file mode 100644 index 000..65f348f --- /dev/null +++ b/board/freescale/p2040rdb/Makefile @@ -0,0 +1,56 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS-y+= $(BOARD).o +COBJS-y += cpld.o +COBJS-y+= ddr.o +COBJS-y+= law.o +COBJS-y+= tlb.o +COBJS-$(CONFIG_PCI) += pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/freescale/p2040rdb/cpld.c b/board/freescale/p2040rdb/cpld.c new file mode 100644 index 000..8e1f46e --- /dev/null +++ b/board/freescale/p2040rdb/cpld.c @@ -0,0 +1,171 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CPLD_BASE - The virtual address of the base of the CPLD register map + * + */ + +#include +#include
[U-Boot] [PATCH 12/14] PHY: add some Broadcom phy support
Port from tsec.c file to add support for bcm5461, bcm5464, bcm5482s.
Signed-off-by: Mingkai Hu
---
drivers/net/fsl_phy.c | 245 +
drivers/net/fsl_phy.h | 22 +
2 files changed, 267 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
index a6ec614..7c22666 100644
--- a/drivers/net/fsl_phy.c
+++ b/drivers/net/fsl_phy.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include "fsl_phy.h"
@@ -242,6 +243,220 @@ static int genphy_shutdown(struct mii_info *phydev)
return 0;
}
+/* Broadcom BCM5461S */
+static int bcm5461_config(struct mii_info *mii_info)
+{
+ unsigned int reg;
+
+ /* reset the PHY */
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_RESET;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ tsec_phy_write(mii_info, 0, MII_CTRL1000, MII_CTRL1000_INIT);
+ tsec_phy_write(mii_info, 0, MII_ADVERTISE, MII_ADVERTISE_INIT);
+
+ /* reset the PHY */
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_RESET;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ return 0;
+}
+
+static int bcm54xx_parse_status(struct mii_info *mii_info)
+{
+ unsigned int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_BCM54xx_AUXSTATUS);
+
+ switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
+ MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
+ case 1:
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_10;
+ break;
+ case 2:
+ mii_info->duplex = DUPLEX_FULL;
+ mii_info->speed = SPEED_10;
+ break;
+ case 3:
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_100;
+ break;
+ case 5:
+ mii_info->duplex = DUPLEX_FULL;
+ mii_info->speed = SPEED_100;
+ break;
+ case 6:
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_1000;
+ break;
+ case 7:
+ mii_info->duplex = DUPLEX_FULL;
+ mii_info->speed = SPEED_1000;
+ break;
+ default:
+ printf("Auto-neg error, defaulting to 10BT/HD\n");
+ mii_info->duplex = DUPLEX_HALF;
+ mii_info->speed = SPEED_10;
+ break;
+ }
+
+ return 0;
+}
+
+static int bcm54xx_startup(struct mii_info *mii_info)
+{
+ /* Read the Status (2x to make sure link is right) */
+ genphy_update_link(mii_info);
+ bcm54xx_parse_status(mii_info);
+
+ return 0;
+}
+
+/* Broadcom BCM5482S */
+/*
+ * "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
+ * circumstances. eg a gigabit TSEC connected to a gigabit switch with
+ * a 4-wire ethernet cable. Both ends advertise gigabit, but can't
+ * link. "Ethernet@Wirespeed" reduces advertised speed until link
+ * can be achieved.
+ */
+static u32 bcm5482_read_wirespeed(struct mii_info *mii_info, u32 reg)
+{
+ return (tsec_phy_read(mii_info, 0, reg) & 0x8FFF) | 0x8010;
+}
+
+static int bcm5482_config(struct mii_info *mii_info)
+{
+ unsigned int reg;
+
+ /* reset the PHY */
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_RESET;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ /* Setup read from auxilary control shadow register 7 */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54xx_AUXCNTL,
+ MIIM_BCM54xx_AUXCNTL_ENCODE(7));
+ /* Read Misc Control register and or in Ethernet@Wirespeed */
+ reg = bcm5482_read_wirespeed(mii_info, MIIM_BCM54xx_AUXCNTL);
+ tsec_phy_write(mii_info, 0, MIIM_BCM54xx_AUXCNTL, reg);
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+ /* Initial config/enable of secondary SerDes interface */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_SHD,
+ MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf));
+ /* Write intial value to secondary SerDes Contol */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_EXP_SEL,
+ MIIM_BCM54XX_EXP_SEL_SSD | 0);
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_EXP_DATA, MII_BMCR_RESTART);
+ /* Enable copper/fiber auto-detect */
+ tsec_phy_write(mii_info, 0, MIIM_BCM54XX_SHD,
+ MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201));
+
+ return 0;
+}
+
+/*
+ * Find out if PHY is in copper or serdes mode by looking at Expansion Reg
+ * 0x42 - "Operating Mode Status Register"
+ */
+static int bcm5482_is_serdes(struct mii_info *m
[U-Boot] [PATCH 11/14] PHY: add some Vitesse phy support
Port from tsec.c file to add support for vsc8221, vsc8211, vsc8601, vsc8641.
Signed-off-by: Mingkai Hu
---
drivers/net/fsl_phy.c | 119 +
drivers/net/fsl_phy.h | 21 +
2 files changed, 140 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
index 1ba0ce1..a6ec614 100644
--- a/drivers/net/fsl_phy.c
+++ b/drivers/net/fsl_phy.c
@@ -242,6 +242,58 @@ static int genphy_shutdown(struct mii_info *phydev)
return 0;
}
+/* Vitesse VSC8211 */
+static int vsc8211_config(struct mii_info *mii_info)
+{
+ /* Override PHY config settings */
+ tsec_phy_write(mii_info, 0, MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT);
+ /* Set up the interface mode */
+ tsec_phy_write(mii_info, 0, MIIM_CIS8201_EXT_CON1,
+ MIIM_CIS8201_EXTCON1_INIT);
+ /* Configure some basic stuff */
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ return 0;
+}
+
+static int vsc8211_parse_status(struct mii_info *mii_info)
+{
+ unsigned int speed;
+ unsigned int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_CIS8201_AUX_CONSTAT);
+
+ if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
+ mii_info->duplex = DUPLEX_FULL;
+ else
+ mii_info->duplex = DUPLEX_HALF;
+
+ speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
+ switch (speed) {
+ case MIIM_CIS8201_AUXCONSTAT_GBIT:
+ mii_info->speed = SPEED_1000;
+ break;
+ case MIIM_CIS8201_AUXCONSTAT_100:
+ mii_info->speed = SPEED_100;
+ break;
+ default:
+ mii_info->speed = SPEED_10;
+ break;
+ }
+
+ return 0;
+}
+
+static int vsc8211_startup(struct mii_info *mii_info)
+{
+ /* Read the Status (2x to make sure link is right) */
+ genphy_update_link(mii_info);
+ vsc8211_parse_status(mii_info);
+
+ return 0;
+}
+
/* Vitesse VSC8244 */
static int vsc8244_parse_status(struct mii_info *mii_info)
{
@@ -280,6 +332,51 @@ static int vsc8244_startup(struct mii_info *mii_info)
return 0;
}
+/* Vitesse VSC8601 */
+int vsc8601_config(struct mii_info *mii_info)
+{
+ unsigned int reg;
+
+ /* Configure some basic stuff */
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+#ifdef CONFIG_SYS_VSC8601_SKEWFIX
+ tsec_phy_write(mii_info, 0, MIIM_VSC8601_EPHY_CON,
+ MIIM_VSC8601_EPHY_CON_INIT_SKEW);
+#if defined(CONFIG_SYS_VSC8601_SKEW_TX) && defined(CONFIG_SYS_VSC8601_SKEW_RX)
+ tsec_phy_write(mii_info, 0, PHY_EXT_PAGE_ACCESS, 1);
+#define VSC8101_SKEW \
+ (CONFIG_SYS_VSC8601_SKEW_TX << 14) | (CONFIG_SYS_VSC8601_SKEW_RX << 12)
+ tsec_phy_write(mii_info, 0, MIIM_VSC8601_SKEW_CTRL, VSC8101_SKEW);
+ tsec_phy_write(mii_info, 0, PHY_EXT_PAGE_ACCESS, 0);
+#endif
+#endif
+ tsec_phy_write(mii_info, 0, MII_ADVERTISE, MII_ADVERTISE_INIT);
+
+ reg = tsec_phy_read(mii_info, 0, MII_BMCR);
+ reg |= BMCR_ANRESTART;
+ tsec_phy_write(mii_info, 0, MII_BMCR, reg);
+
+ return 0;
+}
+
+static struct phy_info phy_info_VSC8211 = {
+ "Vitesse VSC8211",
+ 0xfc4b0,
+ 0x0,
+ &vsc8211_config,
+ &vsc8211_startup,
+ &genphy_shutdown,
+};
+
+static struct phy_info phy_info_VSC8221 = {
+ "Vitesse VSC8221",
+ 0xfc550,
+ 0x0,
+ &genphy_config,
+ &vsc8244_startup,
+ &genphy_shutdown,
+};
+
static struct phy_info phy_info_VSC8244 = {
"Vitesse VSC8244",
0xfc6c0,
@@ -298,6 +395,24 @@ static struct phy_info phy_info_VSC8234 = {
&genphy_shutdown,
};
+static struct phy_info phy_info_VSC8601 = {
+ "Vitesse VSC8601",
+ 0x70420,
+ 0x0,
+ &vsc8601_config,
+ &vsc8244_startup,
+ &genphy_shutdown,
+};
+
+struct phy_info phy_info_VSC8641 = {
+ "Vitesse VSC8641",
+ 0x70430,
+ 0x0,
+ &genphy_config,
+ &vsc8244_startup,
+ &genphy_shutdown,
+};
+
static struct phy_info phy_info_generic = {
"Unknown/Generic PHY",
0x0,
@@ -308,8 +423,12 @@ static struct phy_info phy_info_generic = {
};
static struct phy_info *phy_info[] = {
+ &phy_info_VSC8211,
+ &phy_info_VSC8221,
&phy_info_VSC8244,
&phy_info_VSC8234,
+ &phy_info_VSC8601,
+ &phy_info_VSC8641,
&phy_info_generic
};
diff --git a/drivers/net/fsl_phy.h b/drivers/net/fsl_phy.h
index 8a8b6e8..d18cc58 100644
--- a/drivers/net/fsl_phy.h
+++ b/drivers/net/fsl_phy.h
@@ -34,7 +34,11 @@
#define PORT_MII 0x02
#define PORT_FIBRE 0x03
+/* PHY register offsets */
+#define PHY
[U-Boot] [PATCH 10/14] tsec: refactor the PHY code to make it reuseable
Also remove the PHY code which will be added by the
following patches.
Signed-off-by: Mingkai Hu
---
drivers/net/Makefile |2 +-
drivers/net/tsec.c | 1483 +++---
include/tsec.h | 246 +-
3 files changed, 70 insertions(+), 1661 deletions(-)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 3810665..42fa327 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -79,7 +79,7 @@ COBJS-$(CONFIG_TIGON3) += tigon3.o
COBJS-$(CONFIG_TIGON3) += bcm570x_autoneg.o
COBJS-$(CONFIG_TIGON3) += 5701rls.o
COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
-COBJS-$(CONFIG_TSEC_ENET) += tsec.o
+COBJS-$(CONFIG_TSEC_ENET) += tsec.o fsl_phy.o
COBJS-$(CONFIG_FMAN_ENET) += fsl_phy.o
COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o
COBJS-$(CONFIG_ULI526X) += uli526x.o
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index ac65c43..6ed3e09 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
#include
#include "miiphy.h"
+#include "fsl_phy.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -70,59 +71,6 @@ static struct tsec_info_struct tsec_info[] = {
#endif
};
-/* Writes the given phy's reg with value, using the specified MDIO regs */
-static void tsec_local_mdio_write(tsec_mii_t *phyregs, uint addr,
- uint reg, uint value)
-{
- int timeout = 100;
-
- out_be32(&phyregs->miimadd, (addr << 8) | reg);
- out_be32(&phyregs->miimcon, value);
- asm("sync");
-
- timeout = 100;
- while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--) ;
-}
-
-/* Provide the default behavior of writing the PHY of this ethernet device */
-#define write_phy_reg(priv, regnum, value) \
- tsec_local_mdio_write(priv->phyregs,priv->phyaddr,regnum,value)
-
-/* Reads register regnum on the device's PHY through the
- * specified registers. It lowers and raises the read
- * command, and waits for the data to become valid (miimind
- * notvalid bit cleared), and the bus to cease activity (miimind
- * busy bit cleared), and then returns the value
- */
-static uint tsec_local_mdio_read(tsec_mii_t *phyregs, uint phyid, uint regnum)
-{
- uint value;
-
- /* Put the address of the phy, and the register
-* number into MIIMADD */
- out_be32(&phyregs->miimadd, (phyid << 8) | regnum);
-
- /* Clear the command register, and wait */
- out_be32(&phyregs->miimcom, 0);
- asm("sync");
-
- /* Initiate a read command, and wait */
- out_be32(&phyregs->miimcom, MIIM_READ_COMMAND);
- asm("sync");
-
- /* Wait for the the indication that the read is done */
- while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID |
MIIMIND_BUSY))) ;
-
- /* Grab the value read from the PHY */
- value = in_be32(&phyregs->miimstat);
-
- return value;
-}
-
-/* #define to provide old read_phy_reg functionality without duplicating code
*/
-#define read_phy_reg(priv,regnum) \
- tsec_local_mdio_read(priv->phyregs,priv->phyaddr,regnum)
-
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
| TBIANA_SYMMETRIC_PAUSE \
@@ -144,1332 +92,12 @@ static void tsec_configure_serdes(struct tsec_private
*priv)
{
/* Access TBI PHY registers at given TSEC register offset as opposed
* to the register offset used for external PHY accesses */
- tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_ANA,
- TBIANA_SETTINGS);
- tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa,
TBI_TBICON,
- TBICON_CLK_SELECT);
- tsec_local_mdio_write(priv->phyregs_sgmii, priv->regs->tbipa, TBI_CR,
- CONFIG_TSEC_TBICR_SETTINGS);
-}
-
-/*
- * Returns which value to write to the control register.
- * For 10/100, the value is slightly different
- */
-static uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
-{
- if (priv->flags & TSEC_GIGABIT)
- return MIIM_CONTROL_INIT;
- else
- return MIIM_CR_INIT;
-}
-
-/*
- * Wait for auto-negotiation to complete, then determine link
- */
-static uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
-{
- /*
-* Wait if the link is up, and autonegotiation is in progress
-* (ie - we're capable and it's not done)
-*/
- mii_reg = read_phy_reg(priv, MIIM_STATUS);
- if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
- int i = 0;
-
- puts("Waiting for PHY auto negotiation to complete");
- while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
- /*
-* Timeout reached ?
-
[U-Boot] [PATCH 14/14] PHY: add some misc phy code support
Port from tsec.c file to add support for cis8201, cis8204, dm9161,
dp83865, ksz804, lxt971, rtl8211b.
Signed-off-by: Mingkai Hu
---
drivers/net/fsl_phy.c | 356 -
drivers/net/fsl_phy.h | 57
drivers/net/tsec.c| 24
3 files changed, 436 insertions(+), 1 deletions(-)
diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
index ad9d65e..3a8ebbc 100644
--- a/drivers/net/fsl_phy.c
+++ b/drivers/net/fsl_phy.c
@@ -457,6 +457,211 @@ static int bcm5482_startup(struct mii_info *mii_info)
return 0;
}
+/* CIS8201 */
+static int cis8201_config(struct mii_info *mii_info)
+{
+ /* Override PHY config settings */
+ tsec_phy_write(mii_info, 0, MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT);
+ /* Set up the interface mode */
+ tsec_phy_write(mii_info, 0, MIIM_CIS8201_EXT_CON1,
+ MIIM_CIS8201_EXTCON1_INIT);
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ return 0;
+}
+
+static int cis8201_parse_status(struct mii_info *mii_info)
+{
+ int speed;
+ int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_CIS8201_AUX_CONSTAT);
+
+ if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
+ mii_info->duplex = DUPLEX_FULL;
+ else
+ mii_info->duplex = DUPLEX_HALF;
+
+ speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
+ switch (speed) {
+ case MIIM_CIS8201_AUXCONSTAT_GBIT:
+ mii_info->speed = SPEED_1000;
+ break;
+ case MIIM_CIS8201_AUXCONSTAT_100:
+ mii_info->speed = SPEED_100;
+ break;
+ default:
+ mii_info->speed = SPEED_10;
+ break;
+ }
+
+ return 0;
+}
+
+static int cis8201_startup(struct mii_info *mii_info)
+{
+ genphy_update_link(mii_info);
+ cis8201_parse_status(mii_info);
+
+ return 0;
+}
+
+/* CIS8204 */
+static int __cis8204_fixled(struct mii_info *mii_info)
+{
+ return 0;
+}
+
+int cis8204_fixled(struct mii_info *mii_info)
+ __attribute__((weak, alias("__cis8204_fixled")));
+
+static int cis8204_config(struct mii_info *mii_info)
+{
+ /* Override PHY config settings */
+ tsec_phy_write(mii_info, 0, MIIM_CIS8201_AUX_CONSTAT,
+ MIIM_CIS8201_AUXCONSTAT_INIT);
+ /* Configure some basic stuff */
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ cis8204_fixled(mii_info);
+
+ if (mii_info->flags & TSEC_REDUCED)
+ tsec_phy_write(mii_info, 0, MIIM_CIS8204_EPHY_CON,
+ MIIM_CIS8204_EPHYCON_INIT |
+ MIIM_CIS8204_EPHYCON_RGMII);
+ else
+ tsec_phy_write(mii_info, 0, MIIM_CIS8204_EPHY_CON,
+ MIIM_CIS8204_EPHYCON_INIT);
+
+ return 0;
+}
+
+/* Davicom DM9161E */
+static int dm9161_config(struct mii_info *mii_info)
+{
+ tsec_phy_write(mii_info, 0, MII_BMCR, MIIM_DM9161_CR_STOP);
+ /* Do not bypass the scrambler/descrambler */
+ tsec_phy_write(mii_info, 0, MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT);
+ /* Clear 10BTCSR to default */
+ tsec_phy_write(mii_info, 0, MIIM_DM9161_10BTCSR,
MIIM_DM9161_10BTCSR_INIT);
+
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+ /* Restart Auto Negotiation */
+ tsec_phy_write(mii_info, 0, MII_BMCR, MIIM_DM9161_CR_RSTAN);
+
+ return 0;
+}
+
+static int dm9161_parse_status(struct mii_info *mii_info)
+{
+ int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_DM9161_SCSR);
+
+ if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
+ mii_info->speed = SPEED_100;
+ else
+ mii_info->speed = SPEED_10;
+
+ if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
+ mii_info->duplex = DUPLEX_FULL;
+ else
+ mii_info->duplex = DUPLEX_HALF;
+
+ return 0;
+}
+
+static int dm9161_startup(struct mii_info *mii_info)
+{
+ genphy_update_link(mii_info);
+ dm9161_parse_status(mii_info);
+
+ return 0;
+}
+
+/* NatSemi DP83865 */
+static int dp83865_config(struct mii_info *mii_info)
+{
+ return tsec_phy_write(mii_info, 0, MII_BMCR, MIIM_DP83865_CR_INIT);
+}
+
+static int dp83865_parse_status(struct mii_info *mii_info)
+{
+ int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_DP83865_LANR);
+
+ switch (mii_reg & MIIM_DP83865_SPD_MASK) {
+
+ case MIIM_DP83865_SPD_1000:
+ mii_info->speed = SPEED_1000;
+ break;
+
+ case MIIM_DP83865_SPD_100:
+ mii_info->speed = SPEED_100;
+ break;
+
+ default:
+ mii_info->speed = SPEED_10;
+ break;
+
+ }
+
+ if (mii_re
[U-Boot] [PATCH 13/14] PHY: add some Marvell phy support
Port from tsec.c file to add support for m88e1011s, m88es, m88e1118,
m88e1121r, m88e1145, m88e1149s.
Signed-off-by: Mingkai Hu
---
drivers/net/fsl_phy.c | 299 +
drivers/net/fsl_phy.h | 36 ++
2 files changed, 335 insertions(+), 0 deletions(-)
diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
index 7c22666..ad9d65e 100644
--- a/drivers/net/fsl_phy.c
+++ b/drivers/net/fsl_phy.c
@@ -457,6 +457,245 @@ static int bcm5482_startup(struct mii_info *mii_info)
return 0;
}
+/* Marvell 88E1011S */
+static int m88e1011s_config(struct mii_info *mii_info)
+{
+ /* Reset and configure the PHY */
+ tsec_phy_write(mii_info, 0, MII_BMCR, BMCR_RESET);
+
+ tsec_phy_write(mii_info, 0, 0x1d, 0x1f);
+ tsec_phy_write(mii_info, 0, 0x1e, 0x200c);
+ tsec_phy_write(mii_info, 0, 0x1d, 0x5);
+ tsec_phy_write(mii_info, 0, 0x1e, 0);
+ tsec_phy_write(mii_info, 0, 0x1e, 0x100);
+ tsec_phy_write(mii_info, 0, MII_CTRL1000, MII_CTRL1000_INIT);
+ tsec_phy_write(mii_info, 0, MII_ADVERTISE, MII_ADVERTISE_INIT);
+
+ tsec_phy_write(mii_info, 0, MII_BMCR, BMCR_RESET);
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ return 0;
+}
+
+/* Parse the 88E1011's status register for speed and duplex
+ * information
+ */
+static uint m88e1011s_parse_status(struct mii_info *mii_info)
+{
+ unsigned int speed;
+ unsigned int mii_reg;
+
+ mii_reg = tsec_phy_read(mii_info, 0, MIIM_88E1011_PHY_STATUS);
+
+ if ((mii_reg & MIIM_88E1011_PHYSTAT_LINK) &&
+ !(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
+ int i = 0;
+
+ puts("Waiting for PHY realtime link");
+ while (!(mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE)) {
+ /* Timeout reached ? */
+ if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
+ puts(" TIMEOUT !\n");
+ mii_info->link = 0;
+ break;
+ }
+
+ if ((i++ % 1000) == 0) {
+ putc('.');
+ }
+ udelay(1000);
+ mii_reg = tsec_phy_read(mii_info, 0,
+ MIIM_88E1011_PHY_STATUS);
+ }
+ puts(" done\n");
+ udelay(50); /* another 500 ms (results in faster booting) */
+ } else {
+ if (mii_reg & MIIM_88E1011_PHYSTAT_LINK)
+ mii_info->link = 1;
+ else
+ mii_info->link = 0;
+ }
+
+ if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
+ mii_info->duplex = DUPLEX_FULL;
+ else
+ mii_info->duplex = DUPLEX_HALF;
+
+ speed = mii_reg & MIIM_88E1011_PHYSTAT_SPEED;
+
+ switch (speed) {
+ case MIIM_88E1011_PHYSTAT_GBIT:
+ mii_info->speed = SPEED_1000;
+ break;
+ case MIIM_88E1011_PHYSTAT_100:
+ mii_info->speed = SPEED_100;
+ break;
+ default:
+ mii_info->speed = SPEED_10;
+ break;
+ }
+
+ return 0;
+}
+
+static int m88e1011s_startup(struct mii_info *mii_info)
+{
+ genphy_update_link(mii_info);
+ m88e1011s_parse_status(mii_info);
+
+ return 0;
+}
+
+/* Marvell 88ES */
+static int m88es_config(struct mii_info *mii_info)
+{
+ int reg;
+
+ /* Reset and configure the PHY */
+ tsec_phy_write(mii_info, 0, MII_BMCR, BMCR_RESET);
+
+ if (mii_info->flags & TSEC_REDUCED) {
+ reg = tsec_phy_read(mii_info, 0, 0x1b);
+ reg = (reg & 0xfff0) | 0xb;
+ tsec_phy_write(mii_info, 0, 0x1b, reg);
+ } else {
+ tsec_phy_write(mii_info, 0, 0x1b, 0x1f);
+ }
+
+ tsec_phy_write(mii_info, 0, 0x14, 0x0cd2);
+ tsec_phy_write(mii_info, 0, MII_CTRL1000, MII_CTRL1000_INIT);
+ tsec_phy_write(mii_info, 0, MII_ADVERTISE, MII_ADVERTISE_INIT);
+ tsec_phy_write(mii_info, 0, MII_BMCR, BMCR_RESET);
+ tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+
+ return 0;
+}
+
+/* Marvell 88E1118 */
+static int m88e1118_config(struct mii_info *mii_info)
+{
+ /* Reset and configure the PHY */
+ tsec_phy_write(mii_info, 0, MII_BMCR, BMCR_RESET);
+ /* Change Page Number */
+ tsec_phy_write(mii_info, 0, 0x16, 0x0002);
+ /* Delay RGMII TX and RX */
+ tsec_phy_write(mii_info, 0, 0x15, 0x1070);
+ /* Change Page Number */
+ tsec_phy_write(mii_info, 0, 0x16, 0x0003);
+ /* Adjust LED control */
+ tsec_phy_write(mii_info, 0, 0x10, 0x021e);
+ /* Change Page Number */
+ tsec_phy_write(mii_info, 0, 0x16,
[U-Boot] [PATCH 09/14] tsec: use general ethernet MII register struct(tsec_mii_t)
This will pave the way to move the PHY code to fsl_phy.c which
will be reused by all other code.
Signed-off-by: Mingkai Hu
---
drivers/net/tsec.c | 10 +-
include/tsec.h | 35 +++
2 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 40f1c76..ac65c43 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -56,7 +56,7 @@ static struct tsec_info_struct tsec_info[] = {
#ifdef CONFIG_MPC85XX_FEC
{
.regs = (tsec_t *)(TSEC_BASE_ADDR + 0x2000),
- .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR),
+ .miiregs = (tsec_mii_t *)(MDIO_BASE_ADDR + 0x520),
.devname = CONFIG_MPC85XX_FEC_NAME,
.phyaddr = FEC_PHY_ADDR,
.flags = FEC_FLAGS
@@ -71,7 +71,7 @@ static struct tsec_info_struct tsec_info[] = {
};
/* Writes the given phy's reg with value, using the specified MDIO regs */
-static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
+static void tsec_local_mdio_write(tsec_mii_t *phyregs, uint addr,
uint reg, uint value)
{
int timeout = 100;
@@ -94,7 +94,7 @@ static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint
addr,
* notvalid bit cleared), and the bus to cease activity (miimind
* busy bit cleared), and then returns the value
*/
-static uint tsec_local_mdio_read(tsec_mdio_t *phyregs, uint phyid, uint regnum)
+static uint tsec_local_mdio_read(tsec_mii_t *phyregs, uint phyid, uint regnum)
{
uint value;
@@ -635,7 +635,7 @@ static uint mii_parse_dm9161_scsr(uint mii_reg, struct
tsec_private * priv)
static uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
{
uint phyid;
- tsec_mdio_t *regbase = priv->phyregs;
+ tsec_mii_t *regbase = priv->phyregs;
int timeout = 100;
for (phyid = 0; phyid < 4; phyid++) {
@@ -1444,7 +1444,7 @@ static void phy_run_commands(struct tsec_private *priv,
struct phy_cmd *cmd)
{
int i;
uint result;
- tsec_mdio_t *phyregs = priv->phyregs;
+ tsec_mii_t *phyregs = priv->phyregs;
out_be32(&phyregs->miimcfg, MIIMCFG_RESET);
diff --git a/include/tsec.h b/include/tsec.h
index 6971b47..054e5cf 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -19,15 +19,18 @@
#include
#include
+#include
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#define CONFIG_SYS_MDIO_BASE_ADDR (TSEC_BASE_ADDR + 0x520)
+
#define STD_TSEC_INFO(num) \
{ \
.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \
- .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \
- .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ .miiregs = (tsec_mii_t *)(CONFIG_SYS_MDIO_BASE_ADDR), \
+ .miiregs_sgmii = (tsec_mii_t *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET), \
.devname = CONFIG_TSEC##num##_NAME, \
.phyaddr = TSEC##num##_PHY_ADDR, \
@@ -37,8 +40,8 @@
#define SET_STD_TSEC_INFO(x, num) \
{ \
x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \
- x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \
- x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \
+ x.miiregs = (tsec_mii_t *)(CONFIG_SYS_MDIO_BASE_ADDR); \
+ x.miiregs_sgmii = (tsec_mii_t *)(CONFIG_SYS_MDIO_BASE_ADDR \
+ (num - 1) * TSEC_MDIO_OFFSET); \
x.devname = CONFIG_TSEC##num##_NAME; \
x.phyaddr = TSEC##num##_PHY_ADDR; \
@@ -467,22 +470,6 @@ typedef struct tsec_hash_regs
uintres2[24];
} tsec_hash_t;
-typedef struct tsec_mdio {
- uintres1[4];
- uintieventm;
- uintimaskm;
- uintres2;
- uintemapm;
- uintres3[320];
- uintmiimcfg;/* MII Management: Configuration */
- uintmiimcom;/* MII Management: Command */
- uintmiimadd;/* MII Management: Address */
- uintmiimcon;/* MII Management: Control */
- uintmiimstat; /* MII Management: Status */
- uintmiimind;/* MII Management: Indicators */
- uintres4[690];
-} tsec_mdio_t;
-
typedef struct tsec
{
/* General Control and Status Registers (0x2_n000) */
@@ -588,8 +575,8 @@ typedef struct tsec
struct tsec_private {
tsec_t *regs;
- tsec_mdio_t *phyregs;
- tsec_mdio_t *phyregs_sgmii;
+ tsec_mii_t *phyregs;
+ tsec_mii_t *phyregs_sgmii;
struct phy_info *phyinfo;
uint phyaddr;
u32 flags;
@@ -648,8 +635,8 @@ struct phy_info {
struct tsec_info_struct {
tsec_t *regs;
- tsec_mdio_t *miiregs;
- tsec_mdio_t *miiregs_sgmii;
+ tsec_mii_t *miiregs;
+ tsec_mii_t *miiregs_sgmii;
char *devname;
[U-Boot] [PATCH 08/14] tsec: arrange the code to avoid useless function declaration
Signed-off-by: Mingkai Hu
---
drivers/net/tsec.c | 857 +---
1 files changed, 416 insertions(+), 441 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 910cf9e..40f1c76 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -44,31 +44,6 @@ static RTXBD rtx __attribute__ ((aligned(8)));
#error "rtx must be 64-bit aligned"
#endif
-static int tsec_send(struct eth_device *dev,
-volatile void *packet, int length);
-static int tsec_recv(struct eth_device *dev);
-static int tsec_init(struct eth_device *dev, bd_t * bd);
-static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
-static void tsec_halt(struct eth_device *dev);
-static void init_registers(tsec_t * regs);
-static void startup_tsec(struct eth_device *dev);
-static int init_phy(struct eth_device *dev);
-void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
-uint read_phy_reg(struct tsec_private *priv, uint regnum);
-static struct phy_info *get_phy_info(struct eth_device *dev);
-static void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
-static void adjust_link(struct eth_device *dev);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
-static int tsec_miiphy_write(const char *devname, unsigned char addr,
-unsigned char reg, unsigned short value);
-static int tsec_miiphy_read(const char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-#endif
-#ifdef CONFIG_MCAST_TFTP
-static int tsec_mcast_addr (struct eth_device *dev, u8 mcast_mac, u8 set);
-#endif
-
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
@@ -95,140 +70,6 @@ static struct tsec_info_struct tsec_info[] = {
#endif
};
-/*
- * Initialize all the TSEC devices
- *
- * Returns the number of TSEC devices that were initialized
- */
-int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsecs, int num)
-{
- int i;
- int ret, count = 0;
-
- for (i = 0; i < num; i++) {
- ret = tsec_initialize(bis, &tsecs[i]);
- if (ret > 0)
- count += ret;
- }
-
- return count;
-}
-
-int tsec_standard_init(bd_t *bis)
-{
- return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
-}
-
-/* Initialize device structure. Returns success if PHY
- * initialization succeeded (i.e. if it recognizes the PHY)
- */
-static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info)
-{
- struct eth_device *dev;
- int i;
- struct tsec_private *priv;
-
- dev = (struct eth_device *)malloc(sizeof *dev);
-
- if (NULL == dev)
- return 0;
-
- memset(dev, 0, sizeof *dev);
-
- priv = (struct tsec_private *)malloc(sizeof(*priv));
-
- if (NULL == priv)
- return 0;
-
- privlist[num_tsecs++] = priv;
- priv->regs = tsec_info->regs;
- priv->phyregs = tsec_info->miiregs;
- priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
-
- priv->phyaddr = tsec_info->phyaddr;
- priv->flags = tsec_info->flags;
-
- sprintf(dev->name, tsec_info->devname);
- dev->iobase = 0;
- dev->priv = priv;
- dev->init = tsec_init;
- dev->halt = tsec_halt;
- dev->send = tsec_send;
- dev->recv = tsec_recv;
-#ifdef CONFIG_MCAST_TFTP
- dev->mcast = tsec_mcast_addr;
-#endif
-
- /* Tell u-boot to get the addr from the env */
- for (i = 0; i < 6; i++)
- dev->enetaddr[i] = 0;
-
- eth_register(dev);
-
- /* Reset the MAC */
- setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
- udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
- clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
- && !defined(BITBANGMII)
- miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
-#endif
-
- /* Try to initialize PHY here, and return */
- return init_phy(dev);
-}
-
-/* Initializes data structures and registers for the controller,
- * and brings the interface up. Returns the link status, meaning
- * that it returns success if the link is up, failure otherwise.
- * This allows u-boot to find the first active controller.
- */
-static int tsec_init(struct eth_device *dev, bd_t * bd)
-{
- uint tempval;
- char tmpbuf[MAC_ADDR_LEN];
- int i;
- struct tsec_private *priv = (struct tsec_private *)dev->priv;
- tsec_t *regs = priv->regs;
-
- /* Make sure the controller is stopped */
- tsec_halt(dev);
-
- /* Init MACCFG2. Defaults to GMII */
- out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
-
-
[U-Boot] [PATCH 07/14] tsec: use IO accessories to access the register
Signed-off-by: Mingkai Hu
---
drivers/net/tsec.c | 232 ++-
include/tsec.h |6 +-
2 files changed, 121 insertions(+), 117 deletions(-)
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index 9c8fe62..910cf9e 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -50,7 +50,7 @@ static int tsec_recv(struct eth_device *dev);
static int tsec_init(struct eth_device *dev, bd_t * bd);
static int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info);
static void tsec_halt(struct eth_device *dev);
-static void init_registers(volatile tsec_t * regs);
+static void init_registers(tsec_t * regs);
static void startup_tsec(struct eth_device *dev);
static int init_phy(struct eth_device *dev);
void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
@@ -166,9 +166,9 @@ static int tsec_initialize(bd_t * bis, struct
tsec_info_struct *tsec_info)
eth_register(dev);
/* Reset the MAC */
- priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
+ setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
- priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
+ clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
&& !defined(BITBANGMII)
@@ -190,16 +190,16 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
char tmpbuf[MAC_ADDR_LEN];
int i;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
- volatile tsec_t *regs = priv->regs;
+ tsec_t *regs = priv->regs;
/* Make sure the controller is stopped */
tsec_halt(dev);
/* Init MACCFG2. Defaults to GMII */
- regs->maccfg2 = MACCFG2_INIT_SETTINGS;
+ out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
/* Init ECNTRL */
- regs->ecntrl = ECNTRL_INIT_SETTINGS;
+ out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
/* Copy the station address into the address registers.
* Backwards, because little endian MACS are dumb */
@@ -209,11 +209,11 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
tmpbuf[3];
- regs->macstnaddr1 = tempval;
+ out_be32(®s->macstnaddr1, tempval);
tempval = *((uint *) (tmpbuf + 4));
- regs->macstnaddr2 = tempval;
+ out_be32(®s->macstnaddr2, tempval);
/* reset the indices to zero */
rxIdx = 0;
@@ -230,17 +230,17 @@ static int tsec_init(struct eth_device *dev, bd_t * bd)
}
/* Writes the given phy's reg with value, using the specified MDIO regs */
-static void tsec_local_mdio_write(volatile tsec_mdio_t *phyregs, uint addr,
+static void tsec_local_mdio_write(tsec_mdio_t *phyregs, uint addr,
uint reg, uint value)
{
int timeout = 100;
- phyregs->miimadd = (addr << 8) | reg;
- phyregs->miimcon = value;
+ out_be32(&phyregs->miimadd, (addr << 8) | reg);
+ out_be32(&phyregs->miimcon, value);
asm("sync");
timeout = 100;
- while ((phyregs->miimind & MIIMIND_BUSY) && timeout--) ;
+ while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--) ;
}
@@ -254,28 +254,27 @@ static void tsec_local_mdio_write(volatile tsec_mdio_t
*phyregs, uint addr,
* notvalid bit cleared), and the bus to cease activity (miimind
* busy bit cleared), and then returns the value
*/
-static uint tsec_local_mdio_read(volatile tsec_mdio_t *phyregs,
- uint phyid, uint regnum)
+static uint tsec_local_mdio_read(tsec_mdio_t *phyregs, uint phyid, uint regnum)
{
uint value;
/* Put the address of the phy, and the register
* number into MIIMADD */
- phyregs->miimadd = (phyid << 8) | regnum;
+ out_be32(&phyregs->miimadd, (phyid << 8) | regnum);
/* Clear the command register, and wait */
- phyregs->miimcom = 0;
+ out_be32(&phyregs->miimcom, 0);
asm("sync");
/* Initiate a read command, and wait */
- phyregs->miimcom = MIIM_READ_COMMAND;
+ out_be32(&phyregs->miimcom, MIIM_READ_COMMAND);
asm("sync");
/* Wait for the the indication that the read is done */
- while ((phyregs->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
+ while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID |
MIIMIND_BUSY))) ;
/* Grab the value read from the PHY */
- value = phyregs->miimstat;
+ value = in_be32(&phyregs->miimstat);
return value;
}
@@ -321,18 +320,18 @@ static int i
[U-Boot] [PATCH 02/14] powerpc/fman: add PHY support for dTSEC
From: Kumar Gala
Add VSC8244 and VSC8234 phy support, this will be reused
by etsec code.
Signed-off-by: Kumar Gala
Signed-off-by: Mingkai Hu
---
arch/powerpc/include/asm/fsl_enet.h | 10 +
drivers/net/fsl_phy.c | 353 +++
drivers/net/fsl_phy.h | 176 +
3 files changed, 539 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/fsl_phy.c
create mode 100644 drivers/net/fsl_phy.h
diff --git a/arch/powerpc/include/asm/fsl_enet.h
b/arch/powerpc/include/asm/fsl_enet.h
index 4fb2857..9475249 100644
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ b/arch/powerpc/include/asm/fsl_enet.h
@@ -28,6 +28,16 @@ enum fsl_phy_enet_if {
FSL_ETH_IF_NONE,
};
+typedef struct tsec_mii_mng {
+ u32 miimcfg;/* MII management configuration reg */
+ u32 miimcom;/* MII management command reg */
+ u32 miimadd;/* MII management address reg */
+ u32 miimcon;/* MII management control reg */
+ u32 miimstat; /* MII management status reg */
+ u32 miimind;/* MII management indication reg */
+ u32 ifstat; /* Interface Status Register */
+} __attribute__ ((packed))tsec_mii_t;
+
int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if
phyc);
#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/drivers/net/fsl_phy.c b/drivers/net/fsl_phy.c
new file mode 100644
index 000..1ba0ce1
--- /dev/null
+++ b/drivers/net/fsl_phy.c
@@ -0,0 +1,353 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Jun-jie Zhang
+ * Mingkai Hu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+#include
+
+#include "fsl_phy.h"
+
+void tsec_local_mdio_write(tsec_mii_t *phyregs, int port_addr,
+ int dev_addr, int regnum, int value)
+{
+ int timeout = 100;
+
+ out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
+ out_be32(&phyregs->miimcon, value);
+ asm("sync");
+
+ while ((in_be32(&phyregs->miimind) & MIIMIND_BUSY) && timeout--);
+}
+
+int tsec_local_mdio_read(tsec_mii_t *phyregs, int port_addr,
+ int dev_addr, int regnum)
+{
+ int value;
+ int timeout = 100;
+
+ /* Put the address of the phy, and the register
+* number into MIIMADD */
+ out_be32(&phyregs->miimadd, (port_addr << 8) | (regnum & 0x1f));
+
+ /* Clear the command register, and wait */
+ out_be32(&phyregs->miimcom, 0);
+ asm("sync");
+
+ /* Initiate a read command, and wait */
+ out_be32(&phyregs->miimcom, MIIMCOM_READ_CYCLE);
+ asm("sync");
+
+ /* Wait for the the indication that the read is done */
+ while ((in_be32(&phyregs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
+ && timeout--);
+
+ /* Grab the value read from the PHY */
+ value = in_be32(&phyregs->miimstat);
+
+ return value;
+}
+
+int tsec_phy_read(struct mii_info *mii_info, int dev_addr, int regnum)
+{
+ tsec_mii_t *phyregs = mii_info->phyregs;
+
+ return tsec_local_mdio_read(phyregs, mii_info->mii_id, dev_addr,
+ regnum);
+}
+
+int tsec_phy_write(struct mii_info *mii_info, int dev_addr, int regnum,
+ int value)
+{
+ tsec_mii_t *phyregs = mii_info->phyregs;
+
+ tsec_local_mdio_write(phyregs, mii_info->mii_id, dev_addr, regnum,
+ value);
+
+ return 0;
+}
+
+static int genphy_config(struct mii_info *mii_info)
+{
+ return tsec_phy_write(mii_info, 0, MII_BMCR, MII_BMCR_INIT);
+}
+
+/**
+ * genphy_update_link - update link status in @phydev
+ * @phydev: target phy_device struct
+ *
+ * Description: Update the value in phydev->link to reflect the
+ * current link value. In order to do this, we need to read
+ * the status register twice, keeping the second value.
+ */
+static int genphy_update_link(struct mii_info *phydev)
+{
+ unsigned int mii_reg;
+
+ /*
+* Wait if the link is up, and autonegotiation is in progress
+* (ie
[U-Boot] [PATCH 06/14] powerpc/corenet_ds: Add fman support
From: Kumar Gala
Signed-off-by: Kumar Gala
Signed-off-by: Mingkai Hu
---
board/freescale/corenet_ds/Makefile |1 +
board/freescale/corenet_ds/corenet_ds.c | 11 +-
board/freescale/corenet_ds/eth_p4080.c | 352 +++
3 files changed, 359 insertions(+), 5 deletions(-)
create mode 100644 board/freescale/corenet_ds/eth_p4080.c
diff --git a/board/freescale/corenet_ds/Makefile
b/board/freescale/corenet_ds/Makefile
index 1047d78..a6872ac 100644
--- a/board/freescale/corenet_ds/Makefile
+++ b/board/freescale/corenet_ds/Makefile
@@ -28,6 +28,7 @@ LIB = $(obj)lib$(BOARD).o
COBJS-y+= $(BOARD).o
COBJS-y+= ddr.o
+COBJS-$(CONFIG_P4080DS)+= eth_p4080.o
COBJS-$(CONFIG_P4080DS)+= p4080ds_ddr.o
COBJS-$(CONFIG_PCI)+= pci.o
COBJS-y+= law.o
diff --git a/board/freescale/corenet_ds/corenet_ds.c
b/board/freescale/corenet_ds/corenet_ds.c
index 232dc72..2eadf99 100644
--- a/board/freescale/corenet_ds/corenet_ds.c
+++ b/board/freescale/corenet_ds/corenet_ds.c
@@ -32,10 +32,12 @@
#include
#include
#include
+#include
extern void pci_of_setup(void *blob, bd_t *bd);
#include "../common/ngpixis.h"
+#include "../../../drivers/net/fm/dtsec.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -193,6 +195,8 @@ void board_lmb_reserve(struct lmb *lmb)
}
#endif
+extern void fdt_fixup_p4080ds_enet(void * blob);
+
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@@ -210,9 +214,6 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
fdt_fixup_liodn(blob);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_p4080ds_enet(blob);
}
diff --git a/board/freescale/corenet_ds/eth_p4080.c
b/board/freescale/corenet_ds/eth_p4080.c
new file mode 100644
index 000..465b07c
--- /dev/null
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../common/ngpixis.h"
+#include "../../../drivers/net/fm/dtsec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define EMI_NONE 0x
+#define EMI_MASK 0xf000
+#define EMI1_RGMII 0x0
+#define EMI1_SLOT3 0x8000 /* bank1 EFGH */
+#define EMI1_SLOT4 0x4000 /* bank2 ABCD */
+#define EMI1_SLOT5 0xc000 /* bank3 ABCD */
+#define EMI2_SLOT4 0x1000 /* bank2 ABCD */
+#define EMI2_SLOT5 0x3000 /* bank3 ABCD */
+#define EMI1_MASK 0xc000
+#define EMI2_MASK 0x3000
+
+static int mdio_mux[NUM_FM_PORTS];
+
+void mux_mdio_for_fm(enum fm_port port, int fm, int num)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ uint gpioval = in_be32(&pgpio->gpdat) & ~(EMI_MASK);
+ gpioval |= mdio_mux[port];
+
+ out_be32(&pgpio->gpdat, gpioval);
+}
+
+static u32 find_or_alloc_phandle(void * blob, const char * path, u32 phandle)
+{
+ int off;
+ u32 ph = 0;
+
+ path = fdt_get_alias(blob, path);
+ if (path) {
+ off = fdt_path_offset(blob, path);
+ if (off) {
+ ph = fdt_get_phandle(blob, off);
+ if ((ph == 0) || (ph == -1)) {
+ ph = phandle++;
+ fdt_setprop_cell(blob, off, "linux,phandle",
ph);
+ }
+ }
+ }
+
+ return ph;
+}
+
+static void fdt_set_phy_handle(void *fdt, char * prop, phys_addr_t pa,
+ const char *alias)
+{
+ int offset;
+ u32 ph = find_or_alloc_phandle(fdt, alias, fdt_alloc_phandle(fdt));
+
+ offset = fdt_node_offset_by_compat_reg(fdt, prop, pa);
+ fdt_setprop(fdt, offset, "phy-handle", &ph, sizeof(ph));
+}
+
+/*
+ * Sets the specified node's status to the value contained in "status"
+ * If the first character of the specified path i
[U-Boot] [PATCH 04/14] powerpc/fman: add 10GEC controller and PHY support
From: Kumar Gala
Signed-off-by: Kumar Gala
Signed-off-by: Mingkai Hu
---
drivers/net/fm/tgec.c | 104
drivers/net/fm/tgec.h | 230 +
drivers/net/fm/tgec_phy.c | 155 ++
3 files changed, 489 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/fm/tgec.c
create mode 100644 drivers/net/fm/tgec.h
create mode 100644 drivers/net/fm/tgec_phy.c
diff --git a/drivers/net/fm/tgec.c b/drivers/net/fm/tgec.c
new file mode 100644
index 000..02a2476
--- /dev/null
+++ b/drivers/net/fm/tgec.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Dave Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#include "tgec.h"
+
+static void tgec_init_mac(struct fsl_enet_mac *mac)
+{
+ struct tgec *regs = mac->base;
+
+ /* mask all interrupt */
+ out_be32(®s->imask, IMASK_MASK_ALL);
+
+ /* clear all events */
+ out_be32(®s->ievent, IEVENT_CLEAR_ALL);
+
+ /* set the max receive length */
+ out_be32(®s->maxfrm, mac->max_rx_len);
+
+ /* 1588 disable, insert second mac disable
+* payload length check disable, normal operation,
+* any rx error frame is discarded, clear counters,
+* pause frame ignore, no promiscuous, LAN mode
+* Rx CRC no strip, Tx CRC append, Rx disable and Tx disable
+*/
+ out_be32(®s->command_config, TGEC_CMD_CFG_INIT);
+ udelay(1000);
+ out_be32(®s->command_config, TGEC_CMD_CFG_FINAL);
+
+ /* multicast frame reception for the hash entry disable */
+ out_be32(®s->hashtable_ctrl, 0);
+}
+
+static void tgec_enable_mac(struct fsl_enet_mac *mac)
+{
+ struct tgec *regs = mac->base;
+
+ setbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN);
+}
+
+static void tgec_disable_mac(struct fsl_enet_mac *mac)
+{
+ struct tgec *regs = mac->base;
+
+ clrbits_be32(®s->command_config, TGEC_CMD_CFG_RXTX_EN);
+}
+
+static void tgec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
+{
+ struct tgec *regs = mac->base;
+ u32 mac_addr0, mac_addr1;
+
+ /* if a station address of 0x12345678ABCD, perform a write to
+ MAC_ADDR0 of 0x78563412,
+ MAC_ADDR1 of 0xCDAB */
+
+ mac_addr0 = (mac_addr[3] << 24) | (mac_addr[2] << 16) | \
+ (mac_addr[1] << 8) | (mac_addr[0]);
+ out_be32(®s->mac_addr_0, mac_addr0);
+
+ mac_addr1 = ((mac_addr[5] << 8) | mac_addr[4]) & 0x;
+ out_be32(®s->mac_addr_1, mac_addr1);
+}
+
+static void tgec_set_interface_mode(struct fsl_enet_mac *mac,
+ enum fsl_phy_enet_if type, int speed)
+{
+ /* nothing right now */
+ return;
+}
+
+void init_tgec(struct fsl_enet_mac *mac, void *base,
+ void *phyregs, int max_rx_len)
+{
+ mac->base = base;
+ mac->phyregs = phyregs;
+ mac->max_rx_len = max_rx_len;
+ mac->init_mac = tgec_init_mac;
+ mac->enable_mac = tgec_enable_mac;
+ mac->disable_mac = tgec_disable_mac;
+ mac->set_mac_addr = tgec_set_mac_addr;
+ mac->set_if_mode = tgec_set_interface_mode;
+}
diff --git a/drivers/net/fm/tgec.h b/drivers/net/fm/tgec.h
new file mode 100644
index 000..8d64db2
--- /dev/null
+++ b/drivers/net/fm/tgec.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Dave Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple
[U-Boot] [PATCH 03/14] powerpc/fman: add dTSEC controller support
From: Kumar Gala
Signed-off-by: Kumar Gala
Signed-off-by: Mingkai Hu
---
arch/powerpc/include/asm/fsl_enet.h | 12 ++
drivers/net/fm/dtsec.c | 168 +++
drivers/net/fm/dtsec.h | 251 +++
3 files changed, 431 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/fm/dtsec.c
create mode 100644 drivers/net/fm/dtsec.h
diff --git a/arch/powerpc/include/asm/fsl_enet.h
b/arch/powerpc/include/asm/fsl_enet.h
index 9475249..f94482d 100644
--- a/arch/powerpc/include/asm/fsl_enet.h
+++ b/arch/powerpc/include/asm/fsl_enet.h
@@ -38,6 +38,18 @@ typedef struct tsec_mii_mng {
u32 ifstat; /* Interface Status Register */
} __attribute__ ((packed))tsec_mii_t;
+struct fsl_enet_mac {
+ void *base; /* MAC controller registers base address */
+ void *phyregs;
+ int max_rx_len;
+ void (*init_mac)(struct fsl_enet_mac *mac);
+ void (*enable_mac)(struct fsl_enet_mac *mac);
+ void (*disable_mac)(struct fsl_enet_mac *mac);
+ void (*set_mac_addr)(struct fsl_enet_mac *mac, u8 *mac_addr);
+ void (*set_if_mode)(struct fsl_enet_mac *mac, enum fsl_phy_enet_if type,
+ int speed);
+};
+
int fdt_fixup_phy_connection(void *blob, int offset, enum fsl_phy_enet_if
phyc);
#endif /* __ASM_PPC_FSL_ENET_H */
diff --git a/drivers/net/fm/dtsec.c b/drivers/net/fm/dtsec.c
new file mode 100644
index 000..7c28217
--- /dev/null
+++ b/drivers/net/fm/dtsec.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright 2009-2010 Freescale Semiconductor, Inc.
+ * Dave Liu
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#include "dtsec.h"
+#include "../fsl_phy.h"
+
+static void dtsec_init_mac(struct fsl_enet_mac *mac)
+{
+ struct dtsec *regs = mac->base;
+
+ /* soft reset */
+ out_be32(®s->maccfg1, MACCFG1_SOFT_RST);
+ udelay(1000);
+
+ /* clear soft reset, Rx/Tx MAC disable */
+ out_be32(®s->maccfg1, 0);
+
+ /* graceful stop rx */
+ out_be32(®s->rctrl, RCTRL_INIT);
+ udelay(1000);
+
+ /* graceful stop tx */
+ out_be32(®s->tctrl, TCTRL_INIT);
+ udelay(1000);
+
+ /* disable all interrupts */
+ out_be32(®s->imask, IMASK_MASK_ALL);
+
+ /* clear all events */
+ out_be32(®s->ievent, IEVENT_CLEAR_ALL);
+
+ /* set the max Rx length */
+ out_be32(®s->maxfrm, mac->max_rx_len);
+
+ /* set the ecntrl to reset value */
+ out_be32(®s->ecntrl, ECNTRL_DEFAULT);
+
+ /* Rx length check, no strip CRC for Rx,
+* pad and append CRC for Tx, full duplex
+*/
+ out_be32(®s->maccfg2, MACCFG2_INIT);
+}
+
+static void dtsec_enable_mac(struct fsl_enet_mac *mac)
+{
+ struct dtsec *regs = mac->base;
+
+ /* enable Rx/Tx MAC */
+ setbits_be32(®s->maccfg1, MACCFG1_RXTX_EN);
+
+ /* clear the graceful Rx stop */
+ clrbits_be32(®s->rctrl, RCTRL_GRS);
+
+ /* clear the graceful Tx stop */
+ clrbits_be32(®s->tctrl, TCTRL_GTS);
+}
+
+static void dtsec_disable_mac(struct fsl_enet_mac *mac)
+{
+ struct dtsec *regs = mac->base;
+
+ /* graceful Rx stop */
+ setbits_be32(®s->rctrl, RCTRL_GRS);
+
+ /* graceful Tx stop */
+ setbits_be32(®s->tctrl, TCTRL_GTS);
+
+ /* disable Rx/Tx MAC */
+ clrbits_be32(®s->maccfg1, MACCFG1_RXTX_EN);
+}
+
+static void dtsec_set_mac_addr(struct fsl_enet_mac *mac, u8 *mac_addr)
+{
+ struct dtsec *regs = mac->base;
+ u32 mac_addr1, mac_addr2;
+
+ /* if a station address of 0x12345678ABCD, perform a write to
+ MACSTNADDR1 of 0xCDAB7856,
+ MACSTNADDR2 of 0x3412 */
+
+ mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
+ (mac_addr[3] << 8) | (mac_addr[2]);
+ out_be32(®s->macstnaddr1, mac_addr1);
+
+ mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0x;
+ out_be32(®s->macstnaddr2, mac_addr2);
+}
+
+static void dtsec_set_interface_mode(struct fsl_enet_mac *mac, enum
fsl_phy_enet_if type,
+
[U-Boot] [PATCH 01/14] powerpc/p4080: Add function to report which lane is used for a prtcl
From: Kumar Gala
Also rename serdes_get_bank() to serdes_get_bank_by_lane().
Signed-off-by: Emil Medve
Signed-off-by: Kumar Gala
Signed-off-by: Mingkai Hu
---
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 33 +++-
arch/powerpc/include/asm/fsl_serdes.h |4 +++
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 7fc00d8..c4c595e 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "fsl_corenet_serdes.h"
static u32 serdes_prtcl_map;
@@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane)
return lanes[lane].idx;
}
-int serdes_get_bank(int lane)
+int serdes_get_bank_by_lane(int lane)
{
return lanes[lane].bank;
}
@@ -263,6 +264,34 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs,
ccsr_gur_t *gur,
}
#endif
+static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device)
+{
+ int i;
+
+ for (i = 0; i < SRDS_MAX_LANES; i++) {
+ if (serdes_get_prtcl(prtcl, i) == device)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int serdes_get_first_lane(enum srds_prtcl device)
+{
+ u32 prtcl;
+ const ccsr_gur_t *gur;
+
+ gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ /* Is serdes enabled at all? */
+ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
+ return -ENODEV;
+
+ prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
+
+ return __serdes_get_first_lane(prtcl, device);
+}
+
void fsl_serdes_init(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -318,7 +347,7 @@ void fsl_serdes_init(void)
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane);
if (serdes_lane_enabled(lane)) {
- have_bank[serdes_get_bank(lane)] = 1;
+ have_bank[serdes_get_bank_by_lane(lane)] = 1;
serdes_prtcl_map |= (1 << lane_prtcl);
}
}
diff --git a/arch/powerpc/include/asm/fsl_serdes.h
b/arch/powerpc/include/asm/fsl_serdes.h
index 85518eb..9d9f2e4 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -53,4 +53,8 @@ enum srds_prtcl {
int is_serdes_configured(enum srds_prtcl device);
void fsl_serdes_init(void);
+#ifdef CONFIG_FSL_CORENET
+int serdes_get_first_lane(enum srds_prtcl device);
+#endif
+
#endif /* __FSL_SERDES_H */
--
1.6.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 00/14] powerpc/p4080: add support for FMan ethernet in Independent mode
This patchset add support for the P4080's datapath accelation architecture in independent mode, and do some code refactor of the file tsec.c. 1. Add the releated MAC controller support, includeing dTSEC and 10GEC 2. Add support for FMan ethernet in Independent mode 3. Add PHY support (VSC8244 and VSC8234) to a new file fsl_phy.c which can be reused by other code, such tsec and uec code. 4. tsec code cleanup 5. Move all the PHY code in tsec.c to fsl_phy.c to make it reuseable. Based on the latest WD's U-Boot tree. Tested on P4080DS and MPC8536DS board with SGMII card. [PATCH 01/14] powerpc/p4080: Add function to report which lane is used for a prtcl [PATCH 02/14] powerpc/fman: add PHY support for dTSEC [PATCH 03/14] powerpc/fman: add dTSEC controller support [PATCH 04/14] powerpc/fman: add 10GEC controller and PHY support [PATCH 05/14] powerpc/qoirq: Add support for FMan ethernet in Independent mode [PATCH 06/14] powerpc/corenet_ds: Add fman support [PATCH 07/14] tsec: use IO accessories to access the register [PATCH 08/14] tsec: arrange the code to avoid useless function declaration [PATCH 09/14] tsec: use general ethernet MII register struct(tsec_mii_t) [PATCH 10/14] tsec: refactor the PHY code to make it reuseable [PATCH 11/14] PHY: add some Vitesse phy support [PATCH 12/14] PHY: add some Broadcom phy support [PATCH 13/14] PHY: add some Marvell phy support [PATCH 14/14] PHY: add some misc phy code support Thanks, Mingkai ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] 85xx/eSDHC: fix eSDHC clock frequency mask
The default value of the prescaler of eSDHC clock frequency is 0x80, so we need to mask the MSB to set a different clock, or else it maybe make the behavior of this prescaler undefined. Signed-off-by: Mingkai Hu --- include/fsl_esdhc.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 89b8304..eac6a2b 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -32,7 +32,7 @@ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x0800 #define SYSCTL_TIMEOUT_MASK0x000f -#define SYSCTL_CLOCK_MASK 0x0fff +#define SYSCTL_CLOCK_MASK 0xfff0 #define SYSCTL_PEREN 0x0004 #define SYSCTL_HCKEN 0x0002 #define SYSCTL_IPGEN 0x0001 -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ppc/85xx: Clean up mpc8536DS PCI setup code
Use new fsl_pci_init_port() that reduces amount of duplicated code in the
board ports, use IO accessors and clean up printing of status info.
Signed-off-by: Mingkai Hu
---
board/freescale/mpc8536ds/mpc8536ds.c | 252 +
1 files changed, 64 insertions(+), 188 deletions(-)
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c
b/board/freescale/mpc8536ds/mpc8536ds.c
index 9d617df..84f3c30 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -195,17 +195,24 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
-int first_free_busno=0;
-
-void
-pci_init_board(void)
+#ifdef CONFIG_PCI
+void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- uint devdisr = gur->devdisr;
- uint sdrs2_io_sel =
- (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info[4];
+ u32 devdisr, pordevsr, io_sel, sdrs2_io_sel, host_agent;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
+ int num = 0;
+
+ int pcie_ep, pcie_configured;
+
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
+ host_agent = (in_be32(&gur->porbmsr) & MPC85xx_PORBMSR_HA) >> 16;
debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
@@ -218,228 +225,97 @@ pci_init_board(void)
} else if (sdrs2_io_sel == 6)
printf("eTSEC1 is in sgmii mode.\n");
+ puts("\n");
#ifdef CONFIG_PCIE3
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
- struct pci_controller *hose = &pcie3_hose;
- int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
- int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
- struct pci_region *r = hose->regions;
+ pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent);
+ pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\nPCIE3 connected to Slot3 as %s (base address
%x)",
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ SET_STD_PCIE_INFO(pci_info[num], 3);
+ printf ("PCIE3 connected to Slot3 as %s (base address
%lx)\n",
pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0x;
- debug (" with errors. Clearing. Now
0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* outbound memory */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_MEM_BUS,
- CONFIG_SYS_PCIE3_MEM_PHYS,
- CONFIG_SYS_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(r++,
- CONFIG_SYS_PCIE3_IO_BUS,
- CONFIG_SYS_PCIE3_IO_PHYS,
- CONFIG_SYS_PCIE3_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = r - hose->regions;
-
- hose->first_busno=first_free_busno;
-
- fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
-
- first_free_busno=hose->last_busno+1;
- printf ("PCIE3 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ pci_info[num].regs);
+ first_free_busno = fsl_pci_init_port(&pci_info[num++],
+ &pcie3_hose, first_free_busno, pcie_ep);
} else {
printf ("PCIE3: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE1
[U-Boot] [PATCH] ppc/85xx: make boot from NAND full relocation to RAM
Take advantage of the latest full relocation commit of PPC platform
for boot from NAND.
Signed-off-by: Mingkai Hu
---
Changelog:
- according to Scott's comments to seperate this patch.
cpu/mpc85xx/u-boot-nand.lds |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/u-boot-nand.lds b/cpu/mpc85xx/u-boot-nand.lds
index a0fc8f1..b4c63e2 100644
--- a/cpu/mpc85xx/u-boot-nand.lds
+++ b/cpu/mpc85xx/u-boot-nand.lds
@@ -58,7 +58,6 @@ SECTIONS
.text :
{
*(.text)
-*(.fixup)
*(.got1)
} :text
_etext = .;
--
1.6.4
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[U-Boot] [PATCH] fsl_elbc_nand: remove the bbt descriptors relocation fixup
The commit 66372fe2 manually relocated the bbt pattern pointer,
which can be removed by using full relocation.
Signed-off-by: Mingkai Hu
---
drivers/mtd/nand/fsl_elbc_nand.c |4
1 files changed, 0 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 50cb4aa..146e9bf 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -766,9 +766,6 @@ int board_nand_init(struct nand_chip *nand)
nand->waitfunc = fsl_elbc_wait;
/* set up nand options */
- /* redirect the pointer of bbt pattern to RAM */
- bbt_main_descr.pattern = bbt_pattern;
- bbt_mirror_descr.pattern = mirror_pattern;
nand->bbt_td = &bbt_main_descr;
nand->bbt_md = &bbt_mirror_descr;
@@ -815,7 +812,6 @@ int board_nand_init(struct nand_chip *nand)
/* Large-page-specific setup */
if (or & OR_FCM_PGS) {
priv->page_size = 1;
- largepage_memorybased.pattern = scan_ff_pattern;
nand->badblock_pattern = &largepage_memorybased;
/* adjust ecc setup if needed */
--
1.6.4
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[U-Boot] [PATCH v4 3/3] Add README.mpc8536ds
Add boot from NAND/eSDHC/eSPI description Signed-off-by: Mingkai Hu --- No change over v3. doc/README.mpc8536ds | 127 ++ 1 files changed, 127 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc8536ds diff --git a/doc/README.mpc8536ds b/doc/README.mpc8536ds new file mode 100644 index 000..4d0bee0 --- /dev/null +++ b/doc/README.mpc8536ds @@ -0,0 +1,127 @@ +Overview: += + +The MPC8536E integrates a PowerPC processor core with system logic +required for imaging, networking, and communications applications. + +Boot from NAND: +=== + +The MPC8536E is capable of booting from NAND flash which uses the image +u-boot-nand.bin. This image contains two parts: a first stage image(also +call 4K NAND loader and a second stage image. The former is appended to +the latter to produce u-boot-nand.bin. + +The bootup process can be divided into two stages: the first stage will +configure the L2SRAM, then copy the second stage image to L2SRAM and jump +to it. The second stage image is to configure all the hardware and boot up +to U-Boot command line. + +The 4K NAND loader's code comes from the corresponding nand_spl directory, +along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL +is mainly used to shrink the code size to the 4K size limitation. + +The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the +second stage image. It's set in the board config file when boot from NAND +is selected. + +Build and boot steps + + +1. Building image + make MPC8536DS_NAND_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 1011 + SW9[1-3] = 101 + Note: 1 stands for 'on', 0 stands for 'off' + +3. Flash image + tftp 100 u-boot-nand.bin + nand erase 0 a + nand write 100 0 a + +Boot from On-chip ROM: +== + +The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC +and boot from eSPI. When power on, the porcessor excutes the ROM code to +initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from +the memory device that interfaced to the controller, such as the SDCard or +SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. + +The memory device should contain a specific data structure with control word +and config word at the fixed address. The config word direct the process how +to config the memory device, and the control word direct the processor where +to find the image on the memory device, or where copy the main image to. The +user can use any method to store the data structure to the memory device, only +if store it on the assigned address. + +Build and boot steps + + +For boot from eSDHC: +1. Build image + make MPC8536DS_SDCARD_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0111 + SW3[1] = 0 + SW8[7] = 0 - The on-board SD/MMC slot is active + SW8[7] = 1 - The externel SD/MMC slot is active + +3. Put image to SDCard + Put the follwing info at the assigned address on the SDCard: + + Offset | Data | Description + + | 0x40-0x43 | 0x424F4F54 | BOOT signature | + + | 0x48-0x4B | 0x0008 | u-boot.bin's size | + + | 0x50-0x53 | 0x | u-boot.bin's Addr on SDCard | + + | 0x58-0x5B | 0xF8F8 | Target Address | + --- + | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address | + + | 0x68-0x6B | 0x6| Number of Config Addr/Data | + + | 0x80-0x83 | 0xFF720100 | Config Addr 1 | + | 0x84-0x87 | 0xF8F8 | Config Data 1 | + + | 0x88-0x8b | 0xFF720e44 | Config Addr 2 | + | 0x8c-0x8f | 0x000C | Config Data 2 | + + | 0x90-0x93 | 0xFF72 | Config Addr 3 | + | 0x94-0x97 | 0x8001 | Config Data 3 | + + | 0x98-0x9b | 0xFF72e40e | Config Addr 4 | + | 0x9c-0x9f | 0x0040 | Config Data 4 | + + | 0xa0-0xa3 | 0x4001 | Conf
[U-Boot] [PATCH v4 2/3] On-chip ROM boot: MPC8536DS support
The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu --- Change over v3: - Aligned owing to the modificatoin of the board config file. MAKEALL |2 ++ Makefile|2 ++ board/freescale/mpc8536ds/config.mk | 12 include/configs/MPC8536DS.h | 17 - 4 files changed, 32 insertions(+), 1 deletions(-) diff --git a/MAKEALL b/MAKEALL index b7aadd3..0a54d75 100755 --- a/MAKEALL +++ b/MAKEALL @@ -379,6 +379,8 @@ LIST_85xx=" \ ATUM8548\ MPC8536DS \ MPC8536DS_NAND \ + MPC8536DS_SDCARD\ + MPC8536DS_SPIFLASH \ MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ diff --git a/Makefile b/Makefile index 781db22..c8a883c 100644 --- a/Makefile +++ b/Makefile @@ -2447,6 +2447,8 @@ ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548 MPC8536DS_NAND_config \ +MPC8536DS_SDCARD_config \ +MPC8536DS_SPIFLASH_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index d6490b5..e38af73 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -30,8 +30,20 @@ LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds endif endif +ifeq ($(CONFIG_MK_SDCARD), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fc +endif + +ifeq ($(CONFIG_MK_SPIFLASH), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fc +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff8 endif +ifndef RESET_VECTOR_ADDRESS RESET_VECTOR_ADDRESS = 0xeffc +endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index af36986..a847275 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,6 +37,16 @@ #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 #endif +#ifdef CONFIG_MK_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f8 +#endif + +#ifdef CONFIG_MK_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f8 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E5001 /* BOOKE e500 family */ @@ -236,7 +246,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASETEXT_BASE /* start of monitor */ -#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ + || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT @@ -635,6 +646,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/3] NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu
---
Change over v3:
- Intergrated Scott's comments.
- Intergrated Wolfgang's comments.
MAKEALL|1 +
Makefile |1 +
board/freescale/mpc8536ds/config.mk|7 ++
board/freescale/mpc8536ds/tlb.c| 11 ++
include/configs/MPC8536DS.h| 95 +++
nand_spl/board/freescale/mpc8536ds/Makefile| 123
nand_spl/board/freescale/mpc8536ds/nand_boot.c | 83
7 files changed, 303 insertions(+), 18 deletions(-)
create mode 100644 nand_spl/board/freescale/mpc8536ds/Makefile
create mode 100644 nand_spl/board/freescale/mpc8536ds/nand_boot.c
diff --git a/MAKEALL b/MAKEALL
index b394adb..b7aadd3 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -378,6 +378,7 @@ LIST_83xx=" \
LIST_85xx="\
ATUM8548\
MPC8536DS \
+ MPC8536DS_NAND \
MPC8540ADS \
MPC8540EVAL \
MPC8541CDS \
diff --git a/Makefile b/Makefile
index 9c5b2a5..781db22 100644
--- a/Makefile
+++ b/Makefile
@@ -2446,6 +2446,7 @@ vme8349_config: unconfig
ATUM8548_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+MPC8536DS_NAND_config \
MPC8536DS_36BIT_config \
MPC8536DS_config: unconfig
@$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
diff --git a/board/freescale/mpc8536ds/config.mk
b/board/freescale/mpc8536ds/config.mk
index c1d0525..d6490b5 100644
--- a/board/freescale/mpc8536ds/config.mk
+++ b/board/freescale/mpc8536ds/config.mk
@@ -23,6 +23,13 @@
#
# mpc8536ds board
#
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
ifndef TEXT_BASE
TEXT_BASE = 0xeff8
endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 35a13d4..dc52d7f 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x4,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 9d45648..af36986 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -31,6 +31,12 @@
#define CONFIG_PHYS_64BIT 1
#endif
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT 1
+#define CONFIG_RAMBOOT_NAND1
+#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E5001 /* BOOKE e500 family */
@@ -91,10 +97,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_PANIC_HANG /* do not reset board on panic */
[U-Boot] [PATCH] mpc8536: fix board config file line length
Signed-off-by: Mingkai Hu
---
Changelog:
According to Woflgang's comments, fixed the line length of
the board config file.
include/configs/MPC8536DS.h | 147 +++
1 files changed, 79 insertions(+), 68 deletions(-)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index faca805..9d45648 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -86,8 +86,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_NUM_ADDR_MAP16 /* number of TLB1
entries */
#endif
-#define CONFIG_SYS_MEMTEST_START 0x0001 /* skip exception
vectors */
-#define CONFIG_SYS_MEMTEST_END 0x1f00 /* skip u-boot at top
of RAM */
+#define CONFIG_SYS_MEMTEST_START 0x0001/* skip exception vectors */
+#define CONFIG_SYS_MEMTEST_END 0x1f00/* skip u-boot at top of RAM */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
@@ -97,16 +97,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xffe0 /* relocated CCSRBAR */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_CCSRBAR_PHYS0xfffe0ull /* physical
addr of CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS0xfffe0ull /* physical addr of
CCSRBAR */
#else
-#define CONFIG_SYS_CCSRBAR_PHYSCONFIG_SYS_CCSRBAR /* physical
addr of CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYSCONFIG_SYS_CCSRBAR
#endif
-#define CONFIG_SYS_IMMRCONFIG_SYS_CCSRBAR /* PQII uses
CONFIG_SYS_IMMR */
+#define CONFIG_SYS_IMMRCONFIG_SYS_CCSRBAR /* PQII uses
CONFIG_SYS_IMMR */
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
-#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
+#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
+#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000)
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
@@ -131,9 +131,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_SPD_BUS_NUM 1
/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
+#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
#define CONFIG_SYS_DDR_CS0_BNDS0x001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no
interleaving */
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
#define CONFIG_SYS_DDR_TIMING_30x
#define CONFIG_SYS_DDR_TIMING_00x00260802
#define CONFIG_SYS_DDR_TIMING_10x3935d322
@@ -145,7 +145,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_DDR_CLK_CTRL0x0380
#define CONFIG_SYS_DDR_OCD_CTRL0x
#define CONFIG_SYS_DDR_OCD_STATUS 0x
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
#define CONFIG_SYS_DDR_CONTROL20x04400010
#define CONFIG_SYS_DDR_ERR_INT_EN 0x000d
@@ -190,21 +190,26 @@ extern unsigned long get_board_ddr_clk(unsigned long
dummy);
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
-#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS +
0x800)) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR0_PRELIM \
+ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800)) \
+| BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) |
BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
+| BR_PS_16 | BR_V)
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
-#define CONFIG_SYS_FLASH_BANKS_LIST{CONFIG_SYS_FLASH_BASE_PHYS +
0x800, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x800, \
+ CONFIG_SYS_FLASH_BASE_PHYS }
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 1024/* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT 1024/* sectors per device
[U-Boot] [PATCH] immap_85xx: add porpllsr's plat ratio definition
Signed-off-by: Mingkai Hu
---
include/asm-ppc/immap_85xx.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e7d412d..39fdb8e 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1542,6 +1542,8 @@ typedef struct ccsr_gur {
#endif
#define MPC85xx_PORPLLSR_QE_RATIO 0x3e00
#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT25
+#define MPC85xx_PORPLLSR_PLAT_RATIO0x003e
+#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
uintporbmsr;/* 0xe0004 - POR boot mode status register */
#define MPC85xx_PORBMSR_HA 0x0007
#define MPC85xx_PORBMSR_HA_SHIFT 16
--
1.6.4
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[U-Boot] [PATCH] ppc/85xx: add cpu init config file for boot from NAND
When boot from NAND, the NAND flash must be connected to br/or0.
Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to
it.
Signed-off-by: Mingkai Hu
---
ChangeLog:
- move the board specific config for br/or to board init file, i.e.
nand_spl/board/freescale/mpc8536ds/nand_boot.c, which make it common
for 85xx platform.
cpu/mpc85xx/cpu_init_nand.c | 63 +++
1 files changed, 63 insertions(+), 0 deletions(-)
create mode 100644 cpu/mpc85xx/cpu_init_nand.c
diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c
new file mode 100644
index 000..184cca4
--- /dev/null
+++ b/cpu/mpc85xx/cpu_init_nand.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include
+#include
+
+void cpu_init_f(void)
+{
+ ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+
+ /*
+* LCRR - Clock Ratio Register - set up local bus timing
+* when needed
+*/
+ out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
+
+#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
+ out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
+ out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+#else
+#error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
+#endif
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
+ char *l2srbar;
+ int i;
+
+ out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
+
+ /* set MBECCDIS=1, SBECCDIS=1 */
+ out_be32(&l2cache->l2errdis,
+ (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
+
+ /* set L2E=1 & L2SRAM=001 */
+ out_be32(&l2cache->l2ctl,
+ (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
+
+ /* Initialize L2 SRAM to zero */
+ l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR;
+ for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
+ l2srbar[i] = 0;
+#endif
+}
--
1.6.4
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[U-Boot] [PATCH] ppc/85xx: add ld script file for boot from NAND
The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.
Signed-off-by: Mingkai Hu
---
ChangeLog:
- move from board specific directory to cpu/mpc85xx/*,
make it avalible for 85xx platform.
cpu/mpc85xx/u-boot-nand_spl.lds | 67 +++
1 files changed, 67 insertions(+), 0 deletions(-)
create mode 100644 cpu/mpc85xx/u-boot-nand_spl.lds
diff --git a/cpu/mpc85xx/u-boot-nand_spl.lds b/cpu/mpc85xx/u-boot-nand_spl.lds
new file mode 100644
index 000..fef3e42
--- /dev/null
+++ b/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ *
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+ . = 0xfff0;
+ .text : {
+ *(.text)
+ }
+ _etext = .;
+
+ .reloc : {
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ . = ALIGN(8);
+ .data : {
+ *(.rodata*)
+ *(.data*)
+ *(.sdata*)
+ }
+ _edata = .;
+
+ . = ALIGN(8);
+ __init_begin = .;
+ __init_end = .;
+
+ .resetvec ADDR(.text) + 0xffc : {
+ *(.resetvec)
+ } = 0x
+
+ __bss_start = .;
+ .bss : {
+ *(.sbss)
+ *(.bss)
+ }
+ _end = .;
+}
+ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
--
1.6.4
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[U-Boot] [PATCH] ppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds
Signed-off-by: Mingkai Hu --- Sorry for the spam, ingnor the [PATCH] mpc8536: simplify the top makefile for 36-bit config, this is the new version. Makefile|4 +--- include/configs/MPC8536DS.h |2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 0b61d05..99837a3 100644 --- a/Makefile +++ b/Makefile @@ -2448,9 +2448,7 @@ ATUM8548_config: unconfig MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale MPC8540ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 4746e2e..faca805 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_MPC8536DS_36BIT +#ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT 1 #endif -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mpc8536: simplify the top makefile for 36-bit config
Signed-off-by: Mingkai Hu --- Makefile|4 +--- include/configs/MPC8536DS.h |2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index 0b61d05..99837a3 100644 --- a/Makefile +++ b/Makefile @@ -2448,9 +2448,7 @@ ATUM8548_config: unconfig MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig - @mkdir -p $(obj)include - @echo "#define CONFIG_$(@:_config=) 1" >$(obj)include/config.h - @$(MKCONFIG) -a MPC8536DS ppc mpc85xx mpc8536ds freescale + @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale MPC8540ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8540ads freescale diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 4746e2e..faca805 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_MPC8536DS_36BIT +#ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT 1 #endif -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/3] Add README.mpc8536ds
Add boot from NAND/eSDHC/eSPI description Signed-off-by: Mingkai Hu --- No change over v2, it comes here for the pick up convience. doc/README.mpc8536ds | 127 ++ 1 files changed, 127 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc8536ds diff --git a/doc/README.mpc8536ds b/doc/README.mpc8536ds new file mode 100644 index 000..4d0bee0 --- /dev/null +++ b/doc/README.mpc8536ds @@ -0,0 +1,127 @@ +Overview: += + +The MPC8536E integrates a PowerPC processor core with system logic +required for imaging, networking, and communications applications. + +Boot from NAND: +=== + +The MPC8536E is capable of booting from NAND flash which uses the image +u-boot-nand.bin. This image contains two parts: a first stage image(also +call 4K NAND loader and a second stage image. The former is appended to +the latter to produce u-boot-nand.bin. + +The bootup process can be divided into two stages: the first stage will +configure the L2SRAM, then copy the second stage image to L2SRAM and jump +to it. The second stage image is to configure all the hardware and boot up +to U-Boot command line. + +The 4K NAND loader's code comes from the corresponding nand_spl directory, +along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL +is mainly used to shrink the code size to the 4K size limitation. + +The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the +second stage image. It's set in the board config file when boot from NAND +is selected. + +Build and boot steps + + +1. Building image + make MPC8536DS_NAND_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 1011 + SW9[1-3] = 101 + Note: 1 stands for 'on', 0 stands for 'off' + +3. Flash image + tftp 100 u-boot-nand.bin + nand erase 0 a + nand write 100 0 a + +Boot from On-chip ROM: +== + +The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC +and boot from eSPI. When power on, the porcessor excutes the ROM code to +initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from +the memory device that interfaced to the controller, such as the SDCard or +SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. + +The memory device should contain a specific data structure with control word +and config word at the fixed address. The config word direct the process how +to config the memory device, and the control word direct the processor where +to find the image on the memory device, or where copy the main image to. The +user can use any method to store the data structure to the memory device, only +if store it on the assigned address. + +Build and boot steps + + +For boot from eSDHC: +1. Build image + make MPC8536DS_SDCARD_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0111 + SW3[1] = 0 + SW8[7] = 0 - The on-board SD/MMC slot is active + SW8[7] = 1 - The externel SD/MMC slot is active + +3. Put image to SDCard + Put the follwing info at the assigned address on the SDCard: + + Offset | Data | Description + + | 0x40-0x43 | 0x424F4F54 | BOOT signature | + + | 0x48-0x4B | 0x0008 | u-boot.bin's size | + + | 0x50-0x53 | 0x | u-boot.bin's Addr on SDCard | + + | 0x58-0x5B | 0xF8F8 | Target Address | + --- + | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address | + + | 0x68-0x6B | 0x6| Number of Config Addr/Data | + + | 0x80-0x83 | 0xFF720100 | Config Addr 1 | + | 0x84-0x87 | 0xF8F8 | Config Data 1 | + + | 0x88-0x8b | 0xFF720e44 | Config Addr 2 | + | 0x8c-0x8f | 0x000C | Config Data 2 | + + | 0x90-0x93 | 0xFF72 | Config Addr 3 | + | 0x94-0x97 | 0x8001 | Config Data 3 | + + | 0x98-0x9b | 0xFF72e40e | Config Addr 4 | + | 0x9c-0x9f | 0x0040 | Config Data 4 | + -
[U-Boot] [PATCH v3 1/3] NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu
---
Change over v2:
- Intergrated Kumar's comments.
- Aligned to the leatest git tree
MAKEALL|1 +
Makefile |1 +
board/freescale/mpc8536ds/config.mk|7 ++
board/freescale/mpc8536ds/tlb.c| 11 ++
cpu/mpc85xx/cpu_init_nand.c| 69 +
include/configs/MPC8536DS.h| 96 +++
nand_spl/board/freescale/mpc8536ds/Makefile| 123
nand_spl/board/freescale/mpc8536ds/nand_boot.c | 99 +++
nand_spl/board/freescale/mpc8536ds/u-boot.lds | 67 +
9 files changed, 454 insertions(+), 20 deletions(-)
create mode 100644 cpu/mpc85xx/cpu_init_nand.c
create mode 100644 nand_spl/board/freescale/mpc8536ds/Makefile
create mode 100644 nand_spl/board/freescale/mpc8536ds/nand_boot.c
create mode 100644 nand_spl/board/freescale/mpc8536ds/u-boot.lds
diff --git a/MAKEALL b/MAKEALL
index 1d50c34..283add0 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -378,6 +378,7 @@ LIST_83xx=" \
LIST_85xx="\
ATUM8548\
MPC8536DS \
+ MPC8536DS_NAND \
MPC8540ADS \
MPC8540EVAL \
MPC8541CDS \
diff --git a/Makefile b/Makefile
index 99837a3..4d18a9f 100644
--- a/Makefile
+++ b/Makefile
@@ -2446,6 +2446,7 @@ vme8349_config: unconfig
ATUM8548_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+MPC8536DS_NAND_config \
MPC8536DS_36BIT_config \
MPC8536DS_config: unconfig
@$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
diff --git a/board/freescale/mpc8536ds/config.mk
b/board/freescale/mpc8536ds/config.mk
index c1d0525..d6490b5 100644
--- a/board/freescale/mpc8536ds/config.mk
+++ b/board/freescale/mpc8536ds/config.mk
@@ -23,6 +23,13 @@
#
# mpc8536ds board
#
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
ifndef TEXT_BASE
TEXT_BASE = 0xeff8
endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 35a13d4..dc52d7f 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x4,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/cpu/mpc85xx/cpu_init_nand.c b/cpu/mpc85xx/cpu_init_nand.c
new file mode 100644
index 000..e62f8d3
--- /dev/null
+++ b/cpu/mpc85xx/cpu_init_nand.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
[U-Boot] [PATCH v3 2/3] On-chip ROM boot: MPC8536DS support
The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu --- Change over v2: - Intergrated Kumar's comments. - Aligned to the leatest git tree MAKEALL |2 ++ Makefile|2 ++ board/freescale/mpc8536ds/config.mk | 12 include/configs/MPC8536DS.h | 17 - 4 files changed, 32 insertions(+), 1 deletions(-) diff --git a/MAKEALL b/MAKEALL index 283add0..97600f2 100755 --- a/MAKEALL +++ b/MAKEALL @@ -379,6 +379,8 @@ LIST_85xx=" \ ATUM8548\ MPC8536DS \ MPC8536DS_NAND \ + MPC8536DS_SDCARD\ + MPC8536DS_SPIFLASH \ MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ diff --git a/Makefile b/Makefile index 4d18a9f..8f7f7c3 100644 --- a/Makefile +++ b/Makefile @@ -2447,6 +2447,8 @@ ATUM8548_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548 MPC8536DS_NAND_config \ +MPC8536DS_SDCARD_config \ +MPC8536DS_SPIFLASH_config \ MPC8536DS_36BIT_config \ MPC8536DS_config: unconfig @$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk index d6490b5..e38af73 100644 --- a/board/freescale/mpc8536ds/config.mk +++ b/board/freescale/mpc8536ds/config.mk @@ -30,8 +30,20 @@ LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds endif endif +ifeq ($(CONFIG_MK_SDCARD), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fc +endif + +ifeq ($(CONFIG_MK_SPIFLASH), y) +TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE) +RESET_VECTOR_ADDRESS = 0xf8fc +endif + ifndef TEXT_BASE TEXT_BASE = 0xeff8 endif +ifndef RESET_VECTOR_ADDRESS RESET_VECTOR_ADDRESS = 0xeffc +endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index b6f1e60..97091d4 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,6 +37,16 @@ #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 #endif +#ifdef CONFIG_MK_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f8 +#endif + +#ifdef CONFIG_MK_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f8 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E5001 /* BOOKE e500 family */ @@ -231,7 +241,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASETEXT_BASE /* start of monitor */ -#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ + || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT @@ -622,6 +633,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 -- 1.6.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/5] NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu
---
Makefile |1 +
board/freescale/mpc8536ds/config.mk|7 ++
board/freescale/mpc8536ds/tlb.c| 11 ++
cpu/mpc85xx/nand_init.c| 109 ++
cpu/mpc85xx/u-boot-nand.lds|4 +-
include/configs/MPC8536DS.h| 96 +++
nand_spl/board/freescale/mpc8536ds/Makefile| 119
nand_spl/board/freescale/mpc8536ds/nand_boot.c | 99
nand_spl/board/freescale/mpc8536ds/u-boot.lds | 67 +
9 files changed, 490 insertions(+), 23 deletions(-)
create mode 100644 cpu/mpc85xx/nand_init.c
create mode 100644 nand_spl/board/freescale/mpc8536ds/Makefile
create mode 100644 nand_spl/board/freescale/mpc8536ds/nand_boot.c
create mode 100644 nand_spl/board/freescale/mpc8536ds/u-boot.lds
diff --git a/Makefile b/Makefile
index 8fd9979..681242e 100644
--- a/Makefile
+++ b/Makefile
@@ -2442,6 +2442,7 @@ vme8349_config: unconfig
ATUM8548_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+MPC8536DS_NAND_config \
MPC8536DS_36BIT_config \
MPC8536DS_config: unconfig
@$(MKCONFIG) -n $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
diff --git a/board/freescale/mpc8536ds/config.mk
b/board/freescale/mpc8536ds/config.mk
index f030876..bf8dd76 100644
--- a/board/freescale/mpc8536ds/config.mk
+++ b/board/freescale/mpc8536ds/config.mk
@@ -23,6 +23,13 @@
#
# mpc8536ds board
#
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_MPC8536DS_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
ifndef TEXT_BASE
TEXT_BASE = 0xeff8
endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 35a13d4..dc52d7f 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x4,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/cpu/mpc85xx/nand_init.c b/cpu/mpc85xx/nand_init.c
new file mode 100644
index 000..c29b22d
--- /dev/null
+++ b/cpu/mpc85xx/nand_init.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have recei
[U-Boot] [PATCH v3 1/5] 85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NADN loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu
---
- Move u-boot-nand.lds from board directory to cpu/mpc85xx, which make it
avalible for 85xx platform
- Some modification on u-boot-nand.lds accoring to u-boot.lds
cpu/mpc85xx/cpu_init.c | 19 ++
cpu/mpc85xx/start.S | 23 +++-
cpu/mpc85xx/tlb.c |6 ++
cpu/mpc85xx/u-boot-nand.lds | 140 +++
drivers/misc/fsl_law.c |2 +
5 files changed, 189 insertions(+), 1 deletions(-)
create mode 100644 cpu/mpc85xx/u-boot-nand.lds
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a54cf5d..5f66511 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -291,6 +291,25 @@ int cpu_init_r(void)
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ if (cache_ctl & MPC85xx_L2CTL_L2E) {
+ /* Clear L2 SRAM memory-mapped base address */
+ out_be32(&l2cache->l2srbar0, 0x0);
+ out_be32(&l2cache->l2srbar1, 0x0);
+
+ /* set MBECCDIS=0, SBECCDIS=0 */
+ clrbits_be32(&l2cache->l2errdis,
+ (MPC85xx_L2ERRDIS_MBECC |
+MPC85xx_L2ERRDIS_SBECC));
+
+ /* set L2E=0, L2SRAM=0 */
+ clrbits_be32(&l2cache->l2ctl,
+ (MPC85xx_L2CTL_L2E |
+MPC85xx_L2CTL_L2SRAM_ENTIRE));
+ }
+#endif
+
l2siz_field = (cache_ctl >> 28) & 0x3;
switch (l2siz_field) {
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e21a4eb..c5b6bd9 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -57,10 +57,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
+#ifndef CONFIG_NAND_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
+#endif
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -235,10 +237,11 @@ _start_e500:
#endif /* CONFIG_MPC8569 */
- /* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
+#ifndef CONFIG_SYS_RAMBOOT
+ /* create a temp mapping in AS=1 to the 4M boot window */
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
@@ -248,6 +251,20 @@ _start_e500:
/* The 85xx has the default boot window 0xff80 - 0x */
lis r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+ /*
+* create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
+* image has been relocated to TEXT_BASE on the second stage.
+*/
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+ lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+ lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS
[U-Boot] [PATCH v1 1/3] Make mmc init come before env_relocate
If the environment variables are saved on the MMC/SD card,
env_relocat can't relocate env from MMC/SD card without mmc init.
Signed-off-by: Mingkai Hu
---
lib_ppc/board.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index e8509ee..d5329b7 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -824,6 +824,12 @@ void board_init_r (gd_t *id, ulong dest_addr)
nand_init();/* go init the NAND */
#endif
+#ifdef CONFIG_GENERIC_MMC
+ WATCHDOG_RESET ();
+ puts ("MMC: ");
+ mmc_initialize (bd);
+#endif
+
/* relocate environment function pointers etc. */
env_relocate ();
@@ -990,12 +996,6 @@ void board_init_r (gd_t *id, ulong dest_addr)
scsi_init ();
#endif
-#ifdef CONFIG_GENERIC_MMC
- WATCHDOG_RESET ();
- puts ("MMC: ");
- mmc_initialize (bd);
-#endif
-
#if defined(CONFIG_CMD_DOC)
WATCHDOG_RESET ();
puts ("DOC: ");
--
1.6.4
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[U-Boot] [PATCH v1 2/3] Add support for save environment variable to MMC/SD card
Whether booting from MMC/SD card or not, the environment variables
can be saved on it, this patch add the operation support.
Signed-off-by: Mingkai Hu
---
common/Makefile |1 +
common/cmd_nvedit.c |3 +-
common/env_sdcard.c | 135 +++
3 files changed, 138 insertions(+), 1 deletions(-)
create mode 100644 common/env_sdcard.c
diff --git a/common/Makefile b/common/Makefile
index 3781738..ce6a7da 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -61,6 +61,7 @@ COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_nvram.o
COBJS-$(CONFIG_ENV_IS_IN_ONENAND) += env_onenand.o
COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_SDCARD) += env_sdcard.o
COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
# command
diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c
index 2186205..83969ef 100644
--- a/common/cmd_nvedit.c
+++ b/common/cmd_nvedit.c
@@ -60,9 +60,10 @@ DECLARE_GLOBAL_DATA_PTR;
!defined(CONFIG_ENV_IS_IN_NVRAM) && \
!defined(CONFIG_ENV_IS_IN_ONENAND) && \
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
+!defined(CONFIG_ENV_IS_IN_SDCARD) && \
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|\
-SPI_FLASH|MG_DISK|NVRAM|NOWHERE}
+SPI_FLASH|MG_DISK|NVRAM|SDCARD|NOWHERE}
#endif
#define XMK_STR(x) #x
diff --git a/common/env_sdcard.c b/common/env_sdcard.c
new file mode 100644
index 000..ce73358
--- /dev/null
+++ b/common/env_sdcard.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
+ *
+ * Changelog:
+ * July 2008, Intial version.
+ * June 2009, align to the MMC framework.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include
+#include
+
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* references to names in env_common.c */
+extern uchar default_environment[];
+extern int mmc_get_env_addr(int dev, u32 *env_addr);
+
+char *env_name_spec = "SD CARD";
+env_t *env_ptr;
+
+uchar env_get_char_spec(int index)
+{
+ return *((uchar *)(gd->env_addr + index));
+}
+
+static int readenv(int dev, size_t offset, u_char *buf)
+{
+ int ret;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ mmc_init(mmc);
+
+ ret = mmc_read(mmc, offset, buf, CONFIG_ENV_SIZE);
+ if (ret)
+ return 1;
+
+ return 0;
+}
+
+static int writeenv(int dev, size_t offset, u_char *buf)
+{
+ int env_blknr, env_blkcnt, n;
+ uint blklen;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ mmc_init(mmc);
+
+ blklen = mmc->write_bl_len;
+ env_blknr = offset / blklen;
+ env_blkcnt = CONFIG_ENV_SIZE / blklen;
+
+ n = mmc->block_dev.block_write(dev, env_blknr, env_blkcnt, buf);
+ if (n != env_blkcnt)
+ return 1;
+
+ return 0;
+}
+
+int saveenv(void)
+{
+ int ret;
+ int dev = 0;
+ u32 env_addr;
+
+ ret = mmc_get_env_addr(dev, &env_addr);
+ if (ret) {
+ puts("FAILED!\n");
+ return 1;
+ }
+
+ ret = writeenv(dev, env_addr, (u_char *) env_ptr);
+ if (ret)
+ return 1;
+
+ puts("done\n");
+ gd->env_valid = 1;
+
+ return ret;
+}
+
+void env_relocate_spec(void)
+{
+ int ret;
+ int dev = 0;
+ u32 env_addr;
+
+ ret = mmc_get_env_addr(dev, &env_addr);
+ if (ret)
+ goto err_read;
+
+ ret = readenv(dev, env_addr, (u_char *) env_ptr);
+ if (ret)
+ goto err_read;
+
+ if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc)
+ goto err_crc;
+
+ gd->env_valid = 1;
+
+ return;
+
+err_read:
+err_crc:
+ puts("*** Warning - bad CRC, using default environment\n\n");
+
+ set_default_env();
+}
+
+int env_init(void)
+{
+ /* eSDHC isn't usable before relocation */
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+
+ return 0;
+}
--
1.6.4
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[U-Boot] [PATCH v1 0/3] Add support for saveing env variable to SDCard
[PATCH v1 1/3] Make mmc init come before env_relocate [PATCH v1 2/3] Add support for save environment variable to MMC/SD card [PATCH v1 3/3] mpc8536: Get the address of env on the SDCard ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 3/3] mpc8536: Get the address of env on the SDCard
Both the save env and load env operation will call this function
to get the address of env on the SDCard, so the user can control
where to put the env freely.
Also enable the functionlity of saving env variable to SDCard on
mpc8536
Signed-off-by: Mingkai Hu
---
board/freescale/mpc8536ds/mpc8536ds.c | 46 +
include/configs/MPC8536DS.h |5 +++-
2 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c
b/board/freescale/mpc8536ds/mpc8536ds.c
index da72916..85a3dc3 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -38,6 +38,8 @@
#include
#include
#include
+#include
+#include
#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
@@ -681,3 +683,47 @@ void ft_board_setup(void *blob, bd_t *bd)
#endif
}
#endif
+
+#if defined(CONFIG_MMC)
+/*
+ * The environment variables are written to just after the u-boot image
+ * on SDCard, so we must read the MBR to get the start address and code
+ * length of the u-boot image, then calculate the address of the env.
+ */
+#define ESDHC_BOOT_IMAGE_SIZE 0x48
+#define ESDHC_BOOT_IMAGE_ADDR 0x50
+
+int mmc_get_env_addr(int dev, u32 *env_addr)
+{
+ int ret;
+ u8 *tmp_buf;
+ u32 blklen, code_offset, code_len;
+ struct mmc *mmc = find_mmc_device(dev);
+
+ mmc_init(mmc);
+
+ blklen = mmc->read_bl_len;
+ tmp_buf = malloc(blklen);
+ if (!tmp_buf)
+ return 1;
+
+ /* read out the first block, get the config data information */
+ ret = mmc_read(mmc, 0, tmp_buf, blklen);
+ if (ret) {
+ free(tmp_buf);
+ return 1;
+ }
+
+ /* Get the Source Address, from offset 0x50 */
+ code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
+
+ /* Get the code size from offset 0x48 */
+ code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
+
+ *env_addr = code_offset + code_len;
+
+ free(tmp_buf);
+
+ return 0;
+}
+#endif
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 580d66f..6ffa894 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -633,7 +633,10 @@ extern unsigned long get_board_ddr_clk(unsigned long
dummy);
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024) +
CONFIG_SYS_NAND_BLOCK_SIZE)
-#elif defined(CONFIG_RAMBOOT_SPIFLASH) || defined(CONFIG_RAMBOOT_SDCARD)
+#elif defined(CONFIG_RAMBOOT_SDCARD)
+#define CONFIG_ENV_IS_IN_SDCARD 1
+#define CONFIG_ENV_SIZE 0x2000
+#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
--
1.6.4
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[U-Boot] [PATCH v2 1/5] 85xx: add boot from NAND/eSDHC/eSPI support
The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch
implements these three bootup methods in a unified way - all of these
use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM
which lets us use the SPD to initialize the SDRAM.
For all three bootup methods, the bootup process can be divided into two
stages: the first stage will initialize the corresponding controller,
configure the L2SRAM, then copy the second stage image to L2SRAM and
jump to it. The second stage image is just like the general U-Boot image
to configure all the hardware and boot up to U-Boot command line.
When boot from NAND, the eLBC controller will first load the first stage
image to internal 4K RAM buffer because it's also stored on the NAND
flash. The first stage image, also call 4K NADN loader, will initialize
the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K
NAND loader's code comes from the corresponding nand_spl directory, along
with the code twisted by CONFIG_NAND_SPL.
When boot from eSDHC/eSPI, there's no such a first stage image because
the CPU ROM code does the same work. It will initialize the L2SRAM
according to the config addr/word pairs on the fixed address and
initialize the eSDHC/eSPI controller, then load the second stage image
to L2SRAM and jump to it.
The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
second stage image for all different bootup methods. It's set in the
board config file when one of the bootup methods above is selected.
Signed-off-by: Mingkai Hu
---
cpu/mpc85xx/cpu_init.c | 19 +++
cpu/mpc85xx/start.S| 23 ++-
cpu/mpc85xx/tlb.c |6 ++
drivers/misc/fsl_law.c |2 ++
4 files changed, 49 insertions(+), 1 deletions(-)
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index a54cf5d..5f66511 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -291,6 +291,25 @@ int cpu_init_r(void)
asm("msync;isync");
cache_ctl = l2cache->l2ctl;
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ if (cache_ctl & MPC85xx_L2CTL_L2E) {
+ /* Clear L2 SRAM memory-mapped base address */
+ out_be32(&l2cache->l2srbar0, 0x0);
+ out_be32(&l2cache->l2srbar1, 0x0);
+
+ /* set MBECCDIS=0, SBECCDIS=0 */
+ clrbits_be32(&l2cache->l2errdis,
+ (MPC85xx_L2ERRDIS_MBECC |
+MPC85xx_L2ERRDIS_SBECC));
+
+ /* set L2E=0, L2SRAM=0 */
+ clrbits_be32(&l2cache->l2ctl,
+ (MPC85xx_L2CTL_L2E |
+MPC85xx_L2CTL_L2SRAM_ENTIRE));
+ }
+#endif
+
l2siz_field = (cache_ctl >> 28) & 0x3;
switch (l2siz_field) {
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e21a4eb..c5b6bd9 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -57,10 +57,12 @@
GOT_ENTRY(_GOT2_TABLE_)
GOT_ENTRY(_FIXUP_TABLE_)
+#ifndef CONFIG_NAND_SPL
GOT_ENTRY(_start)
GOT_ENTRY(_start_of_vectors)
GOT_ENTRY(_end_of_vectors)
GOT_ENTRY(transfer_to_handler)
+#endif
GOT_ENTRY(__init_end)
GOT_ENTRY(_end)
@@ -235,10 +237,11 @@ _start_e500:
#endif /* CONFIG_MPC8569 */
- /* create a temp mapping in AS=1 to the 4M boot window */
lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
+#ifndef CONFIG_SYS_RAMBOOT
+ /* create a temp mapping in AS=1 to the 4M boot window */
lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
@@ -248,6 +251,20 @@ _start_e500:
/* The 85xx has the default boot window 0xff80 - 0x */
lis r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
ori r9,r9,FSL_BOOKE_MAS3(0xffc0, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#else
+ /*
+* create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
+* image has been relocated to TEXT_BASE on the second stage.
+*/
+ lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
+ ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
+
+ lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
+ ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
+
+ lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
+ ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+#endif
mtspr MAS0,r6
mtspr MAS1,r7
@@ -359,6 +376,7 @@ _start_cont:
bl board_init_f
isync
+#ifndef CONFIG_NAND_SPL
. = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
@@ -813,6 +831,7
[U-Boot] [PATCH v2 5/5] Add README.mpc8536ds
Add boot from NAND/eSDHC/eSPI description Signed-off-by: Mingkai Hu --- doc/README.mpc8536ds | 127 ++ 1 files changed, 127 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc8536ds diff --git a/doc/README.mpc8536ds b/doc/README.mpc8536ds new file mode 100644 index 000..4d0bee0 --- /dev/null +++ b/doc/README.mpc8536ds @@ -0,0 +1,127 @@ +Overview: += + +The MPC8536E integrates a PowerPC processor core with system logic +required for imaging, networking, and communications applications. + +Boot from NAND: +=== + +The MPC8536E is capable of booting from NAND flash which uses the image +u-boot-nand.bin. This image contains two parts: a first stage image(also +call 4K NAND loader and a second stage image. The former is appended to +the latter to produce u-boot-nand.bin. + +The bootup process can be divided into two stages: the first stage will +configure the L2SRAM, then copy the second stage image to L2SRAM and jump +to it. The second stage image is to configure all the hardware and boot up +to U-Boot command line. + +The 4K NAND loader's code comes from the corresponding nand_spl directory, +along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL +is mainly used to shrink the code size to the 4K size limitation. + +The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the +second stage image. It's set in the board config file when boot from NAND +is selected. + +Build and boot steps + + +1. Building image + make MPC8536DS_NAND_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 1011 + SW9[1-3] = 101 + Note: 1 stands for 'on', 0 stands for 'off' + +3. Flash image + tftp 100 u-boot-nand.bin + nand erase 0 a + nand write 100 0 a + +Boot from On-chip ROM: +== + +The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC +and boot from eSPI. When power on, the porcessor excutes the ROM code to +initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from +the memory device that interfaced to the controller, such as the SDCard or +SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. + +The memory device should contain a specific data structure with control word +and config word at the fixed address. The config word direct the process how +to config the memory device, and the control word direct the processor where +to find the image on the memory device, or where copy the main image to. The +user can use any method to store the data structure to the memory device, only +if store it on the assigned address. + +Build and boot steps + + +For boot from eSDHC: +1. Build image + make MPC8536DS_SDCARD_config + make CROSS_COMPILE=powerpc-none-linux-gnuspe- all + +2. Change dip-switch + SW2[5-8] = 0111 + SW3[1] = 0 + SW8[7] = 0 - The on-board SD/MMC slot is active + SW8[7] = 1 - The externel SD/MMC slot is active + +3. Put image to SDCard + Put the follwing info at the assigned address on the SDCard: + + Offset | Data | Description + + | 0x40-0x43 | 0x424F4F54 | BOOT signature | + + | 0x48-0x4B | 0x0008 | u-boot.bin's size | + + | 0x50-0x53 | 0x | u-boot.bin's Addr on SDCard | + + | 0x58-0x5B | 0xF8F8 | Target Address | + --- + | 0x60-0x63 | 0xF8FFF000 | Execution Starting Address | + + | 0x68-0x6B | 0x6| Number of Config Addr/Data | + + | 0x80-0x83 | 0xFF720100 | Config Addr 1 | + | 0x84-0x87 | 0xF8F8 | Config Data 1 | + + | 0x88-0x8b | 0xFF720e44 | Config Addr 2 | + | 0x8c-0x8f | 0x000C | Config Data 2 | + + | 0x90-0x93 | 0xFF72 | Config Addr 3 | + | 0x94-0x97 | 0x8001 | Config Data 3 | + + | 0x98-0x9b | 0xFF72e40e | Config Addr 4 | + | 0x9c-0x9f | 0x0040 | Config Data 4 | + + | 0xa0-0xa3 | 0x4001 | Config Addr 5
[U-Boot] [PATCH v2 3/5] NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu
---
Makefile |1 +
board/freescale/mpc8536ds/config.mk|7 +
board/freescale/mpc8536ds/tlb.c| 11 ++
board/freescale/mpc8536ds/u-boot-nand.lds | 140
cpu/mpc85xx/nand_init.c| 109 ++
include/configs/MPC8536DS.h| 96 +
nand_spl/board/freescale/mpc8536ds/Makefile| 119
nand_spl/board/freescale/mpc8536ds/nand_boot.c | 99 +
nand_spl/board/freescale/mpc8536ds/u-boot.lds | 67 +++
9 files changed, 629 insertions(+), 20 deletions(-)
create mode 100644 board/freescale/mpc8536ds/u-boot-nand.lds
create mode 100644 cpu/mpc85xx/nand_init.c
create mode 100644 nand_spl/board/freescale/mpc8536ds/Makefile
create mode 100644 nand_spl/board/freescale/mpc8536ds/nand_boot.c
create mode 100644 nand_spl/board/freescale/mpc8536ds/u-boot.lds
diff --git a/Makefile b/Makefile
index 8fd9979..681242e 100644
--- a/Makefile
+++ b/Makefile
@@ -2442,6 +2442,7 @@ vme8349_config: unconfig
ATUM8548_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
+MPC8536DS_NAND_config \
MPC8536DS_36BIT_config \
MPC8536DS_config: unconfig
@$(MKCONFIG) -n $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
diff --git a/board/freescale/mpc8536ds/config.mk
b/board/freescale/mpc8536ds/config.mk
index f030876..b4bc33c 100644
--- a/board/freescale/mpc8536ds/config.mk
+++ b/board/freescale/mpc8536ds/config.mk
@@ -23,6 +23,13 @@
#
# mpc8536ds board
#
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_MPC8536DS_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
+endif
+endif
+
ifndef TEXT_BASE
TEXT_BASE = 0xeff8
endif
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 35a13d4..dc52d7f 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+ /* *I*G - L2SRAM */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x4,
+ CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256K, 1),
+#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8536ds/u-boot-nand.lds
b/board/freescale/mpc8536ds/u-boot-nand.lds
new file mode 100644
index 000..c14e946
--- /dev/null
+++ b/board/freescale/mpc8536ds/u-boot-nand.lds
@@ -0,0 +1,140 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY o
