[PATCH v3 1/5] i2c: mediatek: add basic driver support
From: Mingming Lee
Add MediaTek I2C basic driver
Reviewed-by: Heiko Schocher
Signed-off-by: Mingming Lee
---
Changes for v3:
- fixed code veriew note in v2
- optimize the dma read/write flow in mtk_i2c_do_transfer()
Changes for v2:
- using error number defined in include/linux/errno.h
---
drivers/i2c/Kconfig | 8 +
drivers/i2c/Makefile | 1 +
drivers/i2c/mt_i2c.c | 713 +++
3 files changed, 722 insertions(+)
create mode 100644 drivers/i2c/mt_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index dec6dc9..e217673 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -159,6 +159,14 @@ config SYS_I2C_MESON
internal buffer holding up to 8 bytes for transfers and supports
both 7-bit and 10-bit addresses.
+config SYS_I2C_MTK
+ bool "MediaTek I2C driver"
+ help
+ This selects the MediaTek Integrated Inter Circuit bus driver.
+ The I2C bus adapter is the base for some other I2C client, eg: touch,
sensors.
+ If you want to use MediaTek I2C interface, say Y here.
+ If unsure, say N.
+
config SYS_I2C_MXC
bool "NXP MXC I2C driver"
help
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e851ec4..7227742 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_MTK) += mt_i2c.o
obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/mt_i2c.c b/drivers/i2c/mt_i2c.c
new file mode 100644
index 000..e1de933
--- /dev/null
+++ b/drivers/i2c/mt_i2c.c
@@ -0,0 +1,713 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek I2C Interface driver
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define I2C_RS_TRANSFERBIT(4)
+#define I2C_HS_NACKERR BIT(2)
+#define I2C_ACKERR BIT(1)
+#define I2C_TRANSAC_COMP BIT(0)
+#define I2C_TRANSAC_START BIT(0)
+#define I2C_RS_MUL_CNFGBIT(15)
+#define I2C_RS_MUL_TRIGBIT(14)
+#define I2C_DCM_DISABLE0x
+#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
+#define I2C_IO_CONFIG_PUSH_PULL0x
+#define I2C_SOFT_RST 0x0001
+#define I2C_FIFO_ADDR_CLR 0x0001
+#define I2C_DELAY_LEN 0x0002
+#define I2C_ST_START_CON 0x8001
+#define I2C_FS_START_CON 0x1800
+#define I2C_TIME_CLR_VALUE 0x
+#define I2C_TIME_DEFAULT_VALUE 0x0003
+#define I2C_WRRD_TRANAC_VALUE 0x0002
+#define I2C_RD_TRANAC_VALUE0x0001
+
+#define I2C_DMA_CON_TX 0x
+#define I2C_DMA_CON_RX 0x0001
+#define I2C_DMA_START_EN 0x0001
+#define I2C_DMA_INT_FLAG_NONE 0x
+#define I2C_DMA_CLR_FLAG 0x
+#define I2C_DMA_TX_RX 0x
+#define I2C_DMA_HARD_RST 0x0002
+
+#define MAX_ST_MODE_SPEED 10
+#define MAX_FS_MODE_SPEED 40
+#define MAX_HS_MODE_SPEED 340
+#define MAX_SAMPLE_CNT_DIV 8
+#define MAX_STEP_CNT_DIV 64
+#define MAX_HS_STEP_CNT_DIV8
+#define I2C_DEFAULT_CLK_DIV4
+
+#define MAX_I2C_ADDR 0x7f
+#define MAX_I2C_LEN0xff
+#define TRANS_ADDR_ONLYBIT(8)
+#define TRANSFER_TIMEOUT 5 /* us */
+#define I2C_FIFO_STAT1_MASK0x001f
+#define TIMING_SAMPLE_OFFSET 8
+#define HS_SAMPLE_OFFSET 12
+#define HS_STEP_OFFSET 8
+
+#define I2C_CONTROL_WRAPPERBIT(0)
+#define I2C_CONTROL_RS BIT(1)
+#define I2C_CONTROL_DMA_EN BIT(2)
+#define I2C_CONTROL_CLK_EXT_EN BIT(3)
+#define I2C_CONTROL_DIR_CHANGE BIT(4)
+#define I2C_CONTROL_ACKERR_DET_EN BIT(5)
+#define I2C_CONTROL_TRANSFER_LEN_CHANGE BIT(6)
+#define I2C_CONTROL_DMAACK BIT(8)
+#define I2C_CONTROL_ASYNC BIT(9)
+
+enum I2C_REGS_OFFSET {
+ REG_PORT = 0x0,
+ REG_SLAVE_ADDR = 0x04,
+ REG_INTR_MASK = 0x08,
+ REG_INTR_STAT = 0x0c,
+ REG_CONTROL = 0x10,
+ REG_TRANSFER_LEN = 0x14,
+ REG_TRANSAC_LEN = 0x18,
+ REG_DELAY_LEN = 0x1c,
+ REG_TIMING = 0x20,
+ REG_START = 0x24,
+ REG_EXT_CONF = 0x28,
+ REG_FIFO_STAT1 = 0x2c,
+ REG_FIFO_STAT = 0x30,
+ REG_FIFO_THRESH = 0x34,
+
[PATCH v3 0/5] Add i2c support for MediaTek mt8512
From: Mingming Lee This patch series adds basic i2c support for MediaTek MT8512 EMMC boards. --- Changes for v3: - fixed code veriew note in v2. - optimize the dma read/write flow in mtk_i2c_do_transfer(). - add Reviewed-by info. Changes for v2: - using error number defined in include/linux/errno.h. - add Mediatek i2c controller driver to ARM MEDIATEK in MAINTAINERS. - add bindings for mediatek i2c driver. Mingming Lee (5): i2c: mediatek: add basic driver support ARM: dts: Mediatek: add i2c node support for mt8512 configs: mt8512: Enable I2C related configs dt-binding: i2c: add bindings for mediatek i2c driver MAINTAINERS: add i2c driver to ARM MEDIATEK MAINTAINERS | 2 + arch/arm/dts/mt8512-bm1-emmc.dts | 12 + arch/arm/dts/mt8512.dtsi | 38 +- configs/mt8512_bm1_emmc_defconfig| 8 +- doc/device-tree-bindings/i2c/i2c-mtk.txt | 39 ++ drivers/i2c/Kconfig | 8 + drivers/i2c/Makefile | 1 + drivers/i2c/mt_i2c.c | 713 +++ 8 files changed, 819 insertions(+), 2 deletions(-) create mode 100644 doc/device-tree-bindings/i2c/i2c-mtk.txt create mode 100644 drivers/i2c/mt_i2c.c -- 1.8.1.1.dirty
[PATCH v3 5/5] MAINTAINERS: add i2c driver to ARM MEDIATEK
From: Mingming Lee add Mediatek i2c controller driver to ARM MEDIATEK. Reviewed-by: Simon Glass Signed-off-by: Mingming Lee --- Changes for v3: - just add Reviewed-by info --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 889a73f..cc78561 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -254,10 +254,12 @@ S:Maintained F: arch/arm/mach-mediatek/ F: arch/arm/include/asm/arch-mediatek/ F: board/mediatek/ +F: doc/device-tree-bindings/i2c/i2c-mtk.txt F: doc/device-tree-bindings/phy/phy-mtk-* F: doc/device-tree-bindings/usb/mediatek,* F: doc/README.mediatek F: drivers/clk/mediatek/ +F: drivers/i2c/mt_i2c.c F: drivers/mmc/mtk-sd.c F: drivers/phy/phy-mtk-* F: drivers/pinctrl/mediatek/ -- 1.8.1.1.dirty
[PATCH v3 2/5] ARM: dts: Mediatek: add i2c node support for mt8512
From: Mingming Lee
add i2c dts node support for mt8512
Reviewed-by: Heiko Schocher
Reviewed-by: Simon Glass
Signed-off-by: Mingming Lee
---
Changes for v3:
- just add Reviewed-by info.
---
arch/arm/dts/mt8512-bm1-emmc.dts | 12
arch/arm/dts/mt8512.dtsi | 38 +-
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts
index 296ed93..7c02539 100644
--- a/arch/arm/dts/mt8512-bm1-emmc.dts
+++ b/arch/arm/dts/mt8512-bm1-emmc.dts
@@ -45,6 +45,18 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_default>;
diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi
index 01a02a7..39e9499 100644
--- a/arch/arm/dts/mt8512.dtsi
+++ b/arch/arm/dts/mt8512.dtsi
@@ -90,6 +90,42 @@
reg = <0x10200a80 0x50>;
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x11007000 0x1000>,
+ <0x1180 0x80>;
+ clocks = < CLK_INFRA_I2C0_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10019000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x10019000 0x1000>,
+ <0x11000100 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1001e000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x1001e000 0x1000>,
+ <0x11000180 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,hsuart";
reg = <0x11002000 0x1000>;
@@ -112,4 +148,4 @@
status = "disabled";
};
-};
\ No newline at end of file
+};
--
1.8.1.1.dirty
[PATCH v3 4/5] dt-binding: i2c: add bindings for mediatek i2c driver
From: Mingming Lee
add bindings for mediatek i2c driver
Reviewed-by: Simon Glass
Signed-off-by: Mingming Lee
---
Changes for v3:
- just add Reviewed-by info
---
doc/device-tree-bindings/i2c/i2c-mtk.txt | 39
1 file changed, 39 insertions(+)
create mode 100644 doc/device-tree-bindings/i2c/i2c-mtk.txt
diff --git a/doc/device-tree-bindings/i2c/i2c-mtk.txt
b/doc/device-tree-bindings/i2c/i2c-mtk.txt
new file mode 100644
index 000..10a3f29
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/i2c-mtk.txt
@@ -0,0 +1,39 @@
+I2C for Mediatek platforms
+
+Required properties :
+- compatible : Must be "mediatek,mt8512-i2c"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks: phandles to input clocks.
+- clock-names : Contains the names of the clocks:
+ "main", the clock used for normal mode I2C.
+ "dma", the clock used for apdma mode I2C.
+- status : enable in requried dts or not.
+
+Examples :
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x11007000 0x1000>,
+ <0x1180 0x80>;
+ clocks = < CLK_INFRA_I2C0_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10019000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x10019000 0x1000>,
+ <0x11000100 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
\ No newline at end of file
--
1.8.1.1.dirty
[PATCH v3 3/5] configs: mt8512: Enable I2C related configs
From: Mingming Lee Enable MTK I2C Enable I2C basic command Reviewed-by: Heiko Schocher Reviewed-by: Simon Glass Signed-off-by: Mingming Lee --- Changes for v3: - fixed the config order - add Reviewed-by info --- configs/mt8512_bm1_emmc_defconfig | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index 10a2083..a509cfe 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -3,21 +3,24 @@ CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x44e0 CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x1000 CONFIG_DM_GPIO=y CONFIG_TARGET_MT8512=y -CONFIG_NR_DRAM_BANKS=1 CONFIG_DEFAULT_DEVICE_TREE="mt8512-bm1-emmc" CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_DEFAULT_FDT_FILE="mt8512-bm1-emmc.dtb" CONFIG_SYS_PROMPT="MT8512> " CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_ENV_OVERWRITE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y CONFIG_DM_MMC=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y @@ -33,3 +36,6 @@ CONFIG_MTK_TIMER=y CONFIG_WDT=y CONFIG_WDT_MTK=y CONFIG_LZO=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y -- 1.8.1.1.dirty
Re: [PATCH v2 4/5] dt-binding: i2c: add bindings for mediatek i2c driver
hello Simon, On Sun, 2020-10-11 at 21:34 -0600, Simon Glass wrote: > On Wed, 30 Sep 2020 at 02:22, mingming lee wrote: > > > > From: Mingming Lee > > > > add bindings for mediatek i2c driver > > Should indicate which version of linux this file comes from. > we just send it in u-boot, do not sync with kernel yet. > > > > Signed-off-by: Mingming Lee > > --- > > doc/device-tree-bindings/i2c/i2c-mtk.txt | 39 > > 1 file changed, 39 insertions(+) > > create mode 100644 doc/device-tree-bindings/i2c/i2c-mtk.txt > > Reviewed-by: Simon Glass
Re: [PATCH v2 3/5] configs: mt8512: Enable I2C related configs
hello Simon,
thank you for your review
I have re-order it and would send it in next version.
On Sun, 2020-10-11 at 21:34 -0600, Simon Glass wrote:
> On Wed, 30 Sep 2020 at 02:22, mingming lee wrote:
> >
> > From: Mingming Lee
> >
> > Enable MTK I2C
> > Enable I2C basic command
> >
> > Signed-off-by: Mingming Lee
> > ---
> > configs/mt8512_bm1_emmc_defconfig | 3 +++
> > 1 file changed, 3 insertions(+)
>
> Reviewed-by: Simon Glass
>
> Please check that the sorting is correct.
>
> Something like this bash function may help:
>
> # $1 is config name
> function fix_kconfig()
> {
> make O=/tmp/b/$1_defconfig cfg && \
> make O=/tmp/b/$1 savedefconfig && \
> meld /tmp/b/$1/defconfig configs/$1_defconfig
> }
>
> Regards,
> Simon
Re: [PATCH v2 1/5] i2c: mediatek: add basic driver support
hi Simon, Thank you for your carefully reveiw, and I think I would modify all of them in next version. On Mon, 2020-10-05 at 18:02 -0600, Simon Glass wrote: > Hi Mingming, > > On Wed, 30 Sep 2020 at 02:22, mingming lee wrote: > > > > From: Mingming Lee > > > > Add MediaTek I2C basic driver > > > > Signed-off-by: Mingming Lee > > > > --- > > Changes for v2: > >- using error number defined in include/linux/errno.h > > --- > > drivers/i2c/Kconfig | 9 + > > drivers/i2c/Makefile | 1 + > > drivers/i2c/mt_i2c.c | 617 +++ > > 3 files changed, 627 insertions(+) > > create mode 100644 drivers/i2c/mt_i2c.c > > This looks good to me. Some nits below. > > > > > diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig > > index dec6dc9dfa..103688ed36 100644 > > --- a/drivers/i2c/Kconfig > > +++ b/drivers/i2c/Kconfig > > @@ -159,6 +159,15 @@ config SYS_I2C_MESON > > internal buffer holding up to 8 bytes for transfers and supports > > both 7-bit and 10-bit addresses. > > > > +config SYS_I2C_MTK > > + bool "MediaTek I2C driver" > > + default n > > Not needed I would remove it. > > > + help > > + This selects the MediaTek Integrated Inter Circuit bus driver. > > + The I2C bus adapter is the base for some other I2C client, eg: > > touch, sensors. > > + If you want to use MediaTek I2C interface, say Y here. > > + If unsure, say N. > > + > > config SYS_I2C_MXC > > bool "NXP MXC I2C driver" > > help > > diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile > > index e851ec462e..7227742f8d 100644 > > --- a/drivers/i2c/Makefile > > +++ b/drivers/i2c/Makefile > > @@ -28,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o > > obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o > > obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o > > obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o > > +obj-$(CONFIG_SYS_I2C_MTK) += mt_i2c.o > > obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o > > obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o > > obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o > > diff --git a/drivers/i2c/mt_i2c.c b/drivers/i2c/mt_i2c.c > > new file mode 100644 > > index 00..be6262d3d2 > > --- /dev/null > > +++ b/drivers/i2c/mt_i2c.c > > @@ -0,0 +1,617 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * MediaTek I2C Interface driver > > + * > > + * Copyright (C) 2020 MediaTek Inc. > > + * Author: Mingming Lee > > + */ > > + > > +#include > > +#include > > Check the include-file ordering here: > > https://www.denx.de/wiki/U-Boot/CodingStyle > I would modify the order. > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define I2C_OK 0 > > Drop this and just use 0 > I would drop this. > > + > > +#define I2C_RS_TRANSFERBIT(4) > > +#define I2C_HS_NACKERR BIT(2) > > +#define I2C_ACKERR BIT(1) > > +#define I2C_TRANSAC_COMP BIT(0) > > +#define I2C_TRANSAC_START BIT(0) > > +#define I2C_RS_MUL_CNFGBIT(15) > > +#define I2C_RS_MUL_TRIGBIT(14) > > +#define I2C_DCM_DISABLE0x > > +#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003 > > +#define I2C_IO_CONFIG_PUSH_PULL0x > > +#define I2C_SOFT_RST 0x0001 > > +#define I2C_FIFO_ADDR_CLR 0x0001 > > +#define I2C_DELAY_LEN 0x0002 > > +#define I2C_ST_START_CON 0x8001 > > +#define I2C_FS_START_CON 0x1800 > > +#define I2C_TIME_CLR_VALUE 0x > > +#define I2C_TIME_DEFAULT_VALUE 0x0003 > > +#define I2C_WRRD_TRANAC_VALUE 0x0002 > > +#define I2C_RD_TRANAC_VALUE0x0001 > > + > > +#define I2C_DMA_CON_TX 0x > > +#define I2C_DMA_CON_RX 0x0001 > > +#define I2C_DMA_START_EN 0x0001 > > +#define I2C_DMA_INT_FLAG_NONE 0x > > +#define I2C_DMA_CLR_FLAG 0x > > +#define I2C_DMA_HARD_RST 0x0002 > > + > > +#define MAX_ST_MODE_SPEED 10 > > +#define MAX_FS_MODE_SPEED 40 > > +#define MAX_HS_MODE_SPEED 340 > > +#define MAX_SAM
[PATCH v2 2/5] ARM: dts: Mediatek: add i2c node support for mt8512
From: Mingming Lee
add i2c dts node support for mt8512
Signed-off-by: Mingming Lee
---
arch/arm/dts/mt8512-bm1-emmc.dts | 12 ++
arch/arm/dts/mt8512.dtsi | 38 +++-
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts
index 296ed93b9e..7c02539fca 100644
--- a/arch/arm/dts/mt8512-bm1-emmc.dts
+++ b/arch/arm/dts/mt8512-bm1-emmc.dts
@@ -45,6 +45,18 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_default>;
diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi
index 01a02a7ebf..39e94993c1 100644
--- a/arch/arm/dts/mt8512.dtsi
+++ b/arch/arm/dts/mt8512.dtsi
@@ -90,6 +90,42 @@
reg = <0x10200a80 0x50>;
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x11007000 0x1000>,
+ <0x1180 0x80>;
+ clocks = < CLK_INFRA_I2C0_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10019000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x10019000 0x1000>,
+ <0x11000100 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1001e000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x1001e000 0x1000>,
+ <0x11000180 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,hsuart";
reg = <0x11002000 0x1000>;
@@ -112,4 +148,4 @@
status = "disabled";
};
-};
\ No newline at end of file
+};
--
2.18.0
[PATCH v2 0/5] Add i2c support for MediaTek mt8512
From: Mingming Lee This patch series adds basic i2c support for MediaTek MT8512 EMMC boards. --- Changes for v2: - using error number defined in include/linux/errno.h. - add Mediatek i2c controller driver to ARM MEDIATEK in MAINTAINERS. - add bindings for mediatek i2c driver. Mingming Lee (5): i2c: mediatek: add basic driver support ARM: dts: Mediatek: add i2c node support for mt8512 configs: mt8512: Enable I2C related configs dt-binding: i2c: add bindings for mediatek i2c driver MAINTAINERS: add i2c driver to ARM MEDIATEK MAINTAINERS | 2 + arch/arm/dts/mt8512-bm1-emmc.dts | 12 + arch/arm/dts/mt8512.dtsi | 38 +- configs/mt8512_bm1_emmc_defconfig| 3 + doc/device-tree-bindings/i2c/i2c-mtk.txt | 39 ++ drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/mt_i2c.c | 617 +++ 8 files changed, 720 insertions(+), 1 deletion(-) create mode 100644 doc/device-tree-bindings/i2c/i2c-mtk.txt create mode 100644 drivers/i2c/mt_i2c.c -- 2.18.0
[PATCH v2 5/5] MAINTAINERS: add i2c driver to ARM MEDIATEK
From: Mingming Lee add Mediatek i2c controller driver to ARM MEDIATEK. Signed-off-by: Mingming Lee --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 889a73f15f..cc78561818 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -254,10 +254,12 @@ S:Maintained F: arch/arm/mach-mediatek/ F: arch/arm/include/asm/arch-mediatek/ F: board/mediatek/ +F: doc/device-tree-bindings/i2c/i2c-mtk.txt F: doc/device-tree-bindings/phy/phy-mtk-* F: doc/device-tree-bindings/usb/mediatek,* F: doc/README.mediatek F: drivers/clk/mediatek/ +F: drivers/i2c/mt_i2c.c F: drivers/mmc/mtk-sd.c F: drivers/phy/phy-mtk-* F: drivers/pinctrl/mediatek/ -- 2.18.0
[PATCH v2 1/5] i2c: mediatek: add basic driver support
From: Mingming Lee
Add MediaTek I2C basic driver
Signed-off-by: Mingming Lee
---
Changes for v2:
- using error number defined in include/linux/errno.h
---
drivers/i2c/Kconfig | 9 +
drivers/i2c/Makefile | 1 +
drivers/i2c/mt_i2c.c | 617 +++
3 files changed, 627 insertions(+)
create mode 100644 drivers/i2c/mt_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index dec6dc9dfa..103688ed36 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -159,6 +159,15 @@ config SYS_I2C_MESON
internal buffer holding up to 8 bytes for transfers and supports
both 7-bit and 10-bit addresses.
+config SYS_I2C_MTK
+ bool "MediaTek I2C driver"
+ default n
+ help
+ This selects the MediaTek Integrated Inter Circuit bus driver.
+ The I2C bus adapter is the base for some other I2C client, eg: touch,
sensors.
+ If you want to use MediaTek I2C interface, say Y here.
+ If unsure, say N.
+
config SYS_I2C_MXC
bool "NXP MXC I2C driver"
help
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e851ec462e..7227742f8d 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_MTK) += mt_i2c.o
obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/mt_i2c.c b/drivers/i2c/mt_i2c.c
new file mode 100644
index 00..be6262d3d2
--- /dev/null
+++ b/drivers/i2c/mt_i2c.c
@@ -0,0 +1,617 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek I2C Interface driver
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define I2C_OK 0
+
+#define I2C_RS_TRANSFERBIT(4)
+#define I2C_HS_NACKERR BIT(2)
+#define I2C_ACKERR BIT(1)
+#define I2C_TRANSAC_COMP BIT(0)
+#define I2C_TRANSAC_START BIT(0)
+#define I2C_RS_MUL_CNFGBIT(15)
+#define I2C_RS_MUL_TRIGBIT(14)
+#define I2C_DCM_DISABLE0x
+#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
+#define I2C_IO_CONFIG_PUSH_PULL0x
+#define I2C_SOFT_RST 0x0001
+#define I2C_FIFO_ADDR_CLR 0x0001
+#define I2C_DELAY_LEN 0x0002
+#define I2C_ST_START_CON 0x8001
+#define I2C_FS_START_CON 0x1800
+#define I2C_TIME_CLR_VALUE 0x
+#define I2C_TIME_DEFAULT_VALUE 0x0003
+#define I2C_WRRD_TRANAC_VALUE 0x0002
+#define I2C_RD_TRANAC_VALUE0x0001
+
+#define I2C_DMA_CON_TX 0x
+#define I2C_DMA_CON_RX 0x0001
+#define I2C_DMA_START_EN 0x0001
+#define I2C_DMA_INT_FLAG_NONE 0x
+#define I2C_DMA_CLR_FLAG 0x
+#define I2C_DMA_HARD_RST 0x0002
+
+#define MAX_ST_MODE_SPEED 10
+#define MAX_FS_MODE_SPEED 40
+#define MAX_HS_MODE_SPEED 340
+#define MAX_SAMPLE_CNT_DIV 8
+#define MAX_STEP_CNT_DIV 64
+#define MAX_HS_STEP_CNT_DIV8
+#define I2C_DEFAULT_CLK_DIV4
+
+#define MAX_I2C_ADDR 0x7F
+#define MAX_I2C_LEN0xFF
+#define TRANS_ADDR_ONLYBIT(8)
+#define TRANSFER_TIMEOUT 5 /* us */
+#define I2C_FIFO_STAT1_MASK0x001F
+#define TIMING_SAMPLE_OFFSET 8
+#define HS_SAMPLE_OFFSET 12
+#define HS_STEP_OFFSET 8
+
+#define I2C_CONTROL_WRAPPERBIT(0)
+#define I2C_CONTROL_RS BIT(1)
+#define I2C_CONTROL_DMA_EN BIT(2)
+#define I2C_CONTROL_CLK_EXT_EN BIT(3)
+#define I2C_CONTROL_DIR_CHANGE BIT(4)
+#define I2C_CONTROL_ACKERR_DET_EN BIT(5)
+#define I2C_CONTROL_TRANSFER_LEN_CHANGE BIT(6)
+#define I2C_CONTROL_DMAACK BIT(8)
+#define I2C_CONTROL_ASYNC BIT(9)
+
+enum I2C_REGS_OFFSET {
+ OFFSET_PORT = 0x0,
+ OFFSET_SLAVE_ADDR = 0x04,
+ OFFSET_INTR_MASK = 0x08,
+ OFFSET_INTR_STAT = 0x0C,
+ OFFSET_CONTROL = 0x10,
+ OFFSET_TRANSFER_LEN = 0x14,
+ OFFSET_TRANSAC_LEN = 0x18,
+ OFFSET_DELAY_LEN = 0x1C,
+ OFFSET_TIMING = 0x20,
+ OFFSET_START = 0x24,
+ OFFSET_EXT_CONF = 0x28,
+ OFFSET_FIFO_STAT1 = 0x2C,
+ OFFSET_FIFO_STAT = 0x30,
+ OFFSET_FIFO_THRESH = 0x34,
+ OFFSET_FIFO_ADDR_CLR = 0x38,
+ OFFSET_IO_CONFIG = 0x40,
+ OFFSET_RSV_DEBUG = 0x44,
+ OFFSET_HS = 0x48,
+ OFFSET_SOFTRESET = 0x50,
+ OFFSET_DCM_EN = 0x54,
+ OFF
[PATCH v2 4/5] dt-binding: i2c: add bindings for mediatek i2c driver
From: Mingming Lee
add bindings for mediatek i2c driver
Signed-off-by: Mingming Lee
---
doc/device-tree-bindings/i2c/i2c-mtk.txt | 39
1 file changed, 39 insertions(+)
create mode 100644 doc/device-tree-bindings/i2c/i2c-mtk.txt
diff --git a/doc/device-tree-bindings/i2c/i2c-mtk.txt
b/doc/device-tree-bindings/i2c/i2c-mtk.txt
new file mode 100644
index 00..10a3f29a1e
--- /dev/null
+++ b/doc/device-tree-bindings/i2c/i2c-mtk.txt
@@ -0,0 +1,39 @@
+I2C for Mediatek platforms
+
+Required properties :
+- compatible : Must be "mediatek,mt8512-i2c"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #address-cells = <1>;
+- #size-cells = <0>;
+- clocks: phandles to input clocks.
+- clock-names : Contains the names of the clocks:
+ "main", the clock used for normal mode I2C.
+ "dma", the clock used for apdma mode I2C.
+- status : enable in requried dts or not.
+
+Examples :
+
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x11007000 0x1000>,
+ <0x1180 0x80>;
+ clocks = < CLK_INFRA_I2C0_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10019000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x10019000 0x1000>,
+ <0x11000100 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
\ No newline at end of file
--
2.18.0
[PATCH v2 3/5] configs: mt8512: Enable I2C related configs
From: Mingming Lee Enable MTK I2C Enable I2C basic command Signed-off-by: Mingming Lee --- configs/mt8512_bm1_emmc_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index 10a2083134..6b3d9a4e9b 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -33,3 +33,6 @@ CONFIG_MTK_TIMER=y CONFIG_WDT=y CONFIG_WDT_MTK=y CONFIG_LZO=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y -- 2.18.0
Re: [PATCH 1/3] i2c: mediatek: add basic driver support
On Wed, 2020-09-30 at 07:38 +0200, Heiko Schocher wrote: > Hello mingming, > > Am 09.09.2020 um 08:07 schrieb mingming lee: > > From: Mingming Lee > > > > Add MediaTek I2C basic driver > > > > Signed-off-by: Mingming Lee > > --- > > drivers/i2c/Kconfig | 9 + > > drivers/i2c/Makefile | 1 + > > drivers/i2c/mt_i2c.c | 619 > > +++ > > 3 files changed, 629 insertions(+) > > create mode 100644 drivers/i2c/mt_i2c.c > > Nitpicks only: > > As you introduce here new DTS bindings, can you please document them > in u-boot:/doc/device-tree-bindings/ > ->thank you for for advice, I would add the new DTS bingding in next version. > Thanks! > > > [snip] > > diff --git a/drivers/i2c/mt_i2c.c b/drivers/i2c/mt_i2c.c > > new file mode 100644 > > index 000..5badde9 > > --- /dev/null > > +++ b/drivers/i2c/mt_i2c.c > > @@ -0,0 +1,619 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * MediaTek I2C Interface driver > > + * > > + * Copyright (C) 2020 MediaTek Inc. > > + * Author: Mingming Lee > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define I2C_OK 0 > > +#define EINVAL_I2C 22 /* invalid argument */ > > +#define ETIMEDOUT_I2C 110 /* connection timed out */ > > +#define EACK_I2C 6 /* remote I/O error */ > > You could use defines from include/linux/errno.h ? > --->I think it is better to use the define from include/linux/errno.h, and I would modify it in next version today. > [snip] > > > Reviewed-by: Heiko Schocher > > Thanks! > > bye, > Heiko
[PATCH 2/3] ARM: dts: Mediatek: add i2c node support for mt8512
From: Mingming Lee
add i2c dts node support for mt8512
Signed-off-by: Mingming Lee
---
arch/arm/dts/mt8512-bm1-emmc.dts | 12
arch/arm/dts/mt8512.dtsi | 38 +-
2 files changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts
index 296ed93..7c02539 100644
--- a/arch/arm/dts/mt8512-bm1-emmc.dts
+++ b/arch/arm/dts/mt8512-bm1-emmc.dts
@@ -45,6 +45,18 @@
};
};
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_pins_default>;
diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi
index 01a02a7..39e9499 100644
--- a/arch/arm/dts/mt8512.dtsi
+++ b/arch/arm/dts/mt8512.dtsi
@@ -90,6 +90,42 @@
reg = <0x10200a80 0x50>;
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x11007000 0x1000>,
+ <0x1180 0x80>;
+ clocks = < CLK_INFRA_I2C0_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10019000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x10019000 0x1000>,
+ <0x11000100 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1001e000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x1001e000 0x1000>,
+ <0x11000180 0x80>;
+ clocks = < CLK_INFRA_I2C1_AXI>,
+ < CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,hsuart";
reg = <0x11002000 0x1000>;
@@ -112,4 +148,4 @@
status = "disabled";
};
-};
\ No newline at end of file
+};
--
1.9.1
[PATCH 1/3] i2c: mediatek: add basic driver support
From: Mingming Lee
Add MediaTek I2C basic driver
Signed-off-by: Mingming Lee
---
drivers/i2c/Kconfig | 9 +
drivers/i2c/Makefile | 1 +
drivers/i2c/mt_i2c.c | 619 +++
3 files changed, 629 insertions(+)
create mode 100644 drivers/i2c/mt_i2c.c
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index dec6dc9..103688e 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -159,6 +159,15 @@ config SYS_I2C_MESON
internal buffer holding up to 8 bytes for transfers and supports
both 7-bit and 10-bit addresses.
+config SYS_I2C_MTK
+ bool "MediaTek I2C driver"
+ default n
+ help
+ This selects the MediaTek Integrated Inter Circuit bus driver.
+ The I2C bus adapter is the base for some other I2C client, eg: touch,
sensors.
+ If you want to use MediaTek I2C interface, say Y here.
+ If unsure, say N.
+
config SYS_I2C_MXC
bool "NXP MXC I2C driver"
help
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e851ec4..7227742 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
+obj-$(CONFIG_SYS_I2C_MTK) += mt_i2c.o
obj-$(CONFIG_SYS_I2C_NEXELL) += nx_i2c.o
obj-$(CONFIG_SYS_I2C_OCTEON) += octeon_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
diff --git a/drivers/i2c/mt_i2c.c b/drivers/i2c/mt_i2c.c
new file mode 100644
index 000..5badde9
--- /dev/null
+++ b/drivers/i2c/mt_i2c.c
@@ -0,0 +1,619 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek I2C Interface driver
+ *
+ * Copyright (C) 2020 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define I2C_OK 0
+#define EINVAL_I2C 22 /* invalid argument */
+#define ETIMEDOUT_I2C 110 /* connection timed out */
+#define EACK_I2C 6 /* remote I/O error */
+
+#define I2C_RS_TRANSFERBIT(4)
+#define I2C_HS_NACKERR BIT(2)
+#define I2C_ACKERR BIT(1)
+#define I2C_TRANSAC_COMP BIT(0)
+#define I2C_TRANSAC_START BIT(0)
+#define I2C_RS_MUL_CNFGBIT(15)
+#define I2C_RS_MUL_TRIGBIT(14)
+#define I2C_DCM_DISABLE0x
+#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
+#define I2C_IO_CONFIG_PUSH_PULL0x
+#define I2C_SOFT_RST 0x0001
+#define I2C_FIFO_ADDR_CLR 0x0001
+#define I2C_DELAY_LEN 0x0002
+#define I2C_ST_START_CON 0x8001
+#define I2C_FS_START_CON 0x1800
+#define I2C_TIME_CLR_VALUE 0x
+#define I2C_TIME_DEFAULT_VALUE 0x0003
+#define I2C_WRRD_TRANAC_VALUE 0x0002
+#define I2C_RD_TRANAC_VALUE0x0001
+
+#define I2C_DMA_CON_TX 0x
+#define I2C_DMA_CON_RX 0x0001
+#define I2C_DMA_START_EN 0x0001
+#define I2C_DMA_INT_FLAG_NONE 0x
+#define I2C_DMA_CLR_FLAG 0x
+#define I2C_DMA_HARD_RST 0x0002
+
+#define MAX_ST_MODE_SPEED 10
+#define MAX_FS_MODE_SPEED 40
+#define MAX_HS_MODE_SPEED 340
+#define MAX_SAMPLE_CNT_DIV 8
+#define MAX_STEP_CNT_DIV 64
+#define MAX_HS_STEP_CNT_DIV8
+#define I2C_DEFAULT_CLK_DIV4
+
+#define MAX_I2C_ADDR 0x7F
+#define MAX_I2C_LEN0xFF
+#define TRANS_ADDR_ONLYBIT(8)
+#define TRANSFER_TIMEOUT 5 /* us */
+#define I2C_FIFO_STAT1_MASK0x001F
+#define TIMING_SAMPLE_OFFSET 8
+#define HS_SAMPLE_OFFSET 12
+#define HS_STEP_OFFSET 8
+
+#define I2C_CONTROL_WRAPPERBIT(0)
+#define I2C_CONTROL_RS BIT(1)
+#define I2C_CONTROL_DMA_EN BIT(2)
+#define I2C_CONTROL_CLK_EXT_EN BIT(3)
+#define I2C_CONTROL_DIR_CHANGE BIT(4)
+#define I2C_CONTROL_ACKERR_DET_EN BIT(5)
+#define I2C_CONTROL_TRANSFER_LEN_CHANGE BIT(6)
+#define I2C_CONTROL_DMAACK BIT(8)
+#define I2C_CONTROL_ASYNC BIT(9)
+
+enum I2C_REGS_OFFSET {
+ OFFSET_PORT = 0x0,
+ OFFSET_SLAVE_ADDR = 0x04,
+ OFFSET_INTR_MASK = 0x08,
+ OFFSET_INTR_STAT = 0x0C,
+ OFFSET_CONTROL = 0x10,
+ OFFSET_TRANSFER_LEN = 0x14,
+ OFFSET_TRANSAC_LEN = 0x18,
+ OFFSET_DELAY_LEN = 0x1C,
+ OFFSET_TIMING = 0x20,
+ OFFSET_START = 0x24,
+ OFFSET_EXT_CONF = 0x28,
+ OFFSET_FIFO_STAT1 = 0x2C,
+ OFFSET_FIFO_STAT = 0x30,
+ OFFSET_FIFO_THRESH = 0x34,
+ OFFSET_FIFO_ADDR_CLR = 0x38,
+ OFFSET_IO_CONFIG = 0x40,
+ OFFSET_RSV_DEBUG = 0x44,
+ OFFSET_HS = 0x48,
+
[PATCH 0/3] Add i2c support for MediaTek mt8512
From: Mingming Lee This patch series adds basic i2c support for MediaTek MT8512 EMMC boards. Mingming Lee (3): i2c: mediatek: add basic driver support ARM: dts: Mediatek: add i2c node support for mt8512 configs: mt8512: Enable I2C related configs arch/arm/dts/mt8512-bm1-emmc.dts | 12 + arch/arm/dts/mt8512.dtsi | 38 ++- configs/mt8512_bm1_emmc_defconfig | 3 + drivers/i2c/Kconfig | 9 + drivers/i2c/Makefile | 1 + drivers/i2c/mt_i2c.c | 619 ++ 6 files changed, 681 insertions(+), 1 deletion(-) create mode 100644 drivers/i2c/mt_i2c.c -- 1.9.1
[PATCH 3/3] configs: mt8512: Enable I2C related configs
From: Mingming Lee Enable MTK I2C Enable I2C basic command Signed-off-by: Mingming Lee --- configs/mt8512_bm1_emmc_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index 10a2083..6b3d9a4 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -33,3 +33,6 @@ CONFIG_MTK_TIMER=y CONFIG_WDT=y CONFIG_WDT_MTK=y CONFIG_LZO=y +CONFIG_CMD_I2C=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y -- 1.9.1
[PATCH] ARM: MediaTek: amend IC description for MediaTek MT8512
From: Mingming Lee The description for MT8512 has some mistake, so correct it. Signed-off-by: Mingming Lee --- arch/arm/mach-mediatek/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 0042e57017..7f40ba9319 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -47,10 +47,10 @@ config TARGET_MT8512 select ARM64 select MT8512 help - The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53. + The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, - Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo - chip and several DDR3 and DDR4 options. + IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital + and several LPDDR3 and LPDDR4 options. config TARGET_MT8516 bool "MediaTek MT8516 SoC" -- 2.18.0
Re: [PATCH] pinctrl: mediatek: mt8512: fix the wrong start address of ranges
On Fri, 2020-08-07 at 17:32 +0800, Chunfeng Yun wrote:
> The start address of dout, pullen and pullsel ragnes are wrong,
> so fix up them.
>
> Signed-off-by: Chunfeng Yun
> ---
> drivers/pinctrl/mediatek/pinctrl-mt8512.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
> b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
> index af43754..bf2a8dd9 100644
> --- a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
> +++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
> @@ -31,15 +31,15 @@ static const struct mtk_pin_field_calc
> mt8512_pin_di_range[] = {
> };
>
> static const struct mtk_pin_field_calc mt8512_pin_do_range[] = {
> - PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
> + PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
> };
>
> static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = {
> - PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
> + PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
> };
>
> static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = {
> - PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
> + PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
> };
>
> static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = {
Reviewed-by: Mingming Lee
[PATCH v2 6/6] fastboot: mt85xx: add command to flash/erase emmc hwpart
This patch includes the following:
1. Add fastboot command to erase the whole EMMC_USER
2. Add fastboot command to flash image at EMMC_BOOT1
3. Add fastboot command to erase the whole EMMC_BOOT1
4. Enale CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT for mt8518
Signed-off-by: mingming lee
---
Changes for v2:
- Limit the config in this patch depends on ARCH_MEDIATEK
- config include all the added function,avoid affect other IC config
---
configs/mt8518_ap1_emmc_defconfig | 1 +
drivers/fastboot/Kconfig | 30 +
drivers/fastboot/fb_mmc.c | 102 ++
3 files changed, 133 insertions(+)
diff --git a/configs/mt8518_ap1_emmc_defconfig
b/configs/mt8518_ap1_emmc_defconfig
index 714fd8e087..e929d40d75 100644
--- a/configs/mt8518_ap1_emmc_defconfig
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -60,3 +60,4 @@ CONFIG_FASTBOOT_FLASH_MMC=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_BUF_ADDR=0x5600
CONFIG_FASTBOOT_BUF_SIZE=0x1E0
+CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
\ No newline at end of file
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index 433ea0dc3b..aab8288930 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -104,6 +104,36 @@ config FASTBOOT_FLASH_NAND_TRIMFFS
When flashing NAND enable the DROP_FFS flag to drop trailing all-0xff
pages.
+config FASTBOOT_MMC_BOOT1_SUPPORT
+ bool "Enable EMMC_BOOT1 flash/erase"
+ depends on FASTBOOT_FLASH_MMC && EFI_PARTITION && ARCH_MEDIATEK
+ help
+ The fastboot "flash" and "erase" commands normally does operations
+ on EMMC userdata. Define this to enable the special commands to
+ flash/erase EMMC_BOOT1.
+ The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+
+config FASTBOOT_MMC_BOOT1_NAME
+ string "Target name for updating EMMC_BOOT1"
+ depends on FASTBOOT_MMC_BOOT1_SUPPORT
+ default "mmc0boot0"
+ help
+ The fastboot "flash" and "erase" commands support operations on
+ EMMC_BOOT1. This occurs when the specified "EMMC_BOOT1 name" on
+ the "fastboot flash" and "fastboot erase" commands match the value
+ defined here.
+ The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+
+config FASTBOOT_MMC_USER_NAME
+ string "Target name for erasing EMMC_USER"
+ depends on FASTBOOT_FLASH_MMC && EFI_PARTITION && ARCH_MEDIATEK
+ default "mmc0"
+ help
+ The fastboot "erase" command supports erasing EMMC_USER. This occurs
+ when the specified "EMMC_USER name" on the "fastboot erase" commands
+ match the value defined here.
+ The default target name for erasing EMMC_USER is "mmc0".
+
config FASTBOOT_GPT_NAME
string "Target name for updating GPT"
depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index b0b19c5762..d7cf9f4aac 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -129,6 +129,76 @@ static void write_raw_image(struct blk_desc *dev_desc,
disk_partition_t *info,
fastboot_okay(NULL, response);
}
+#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT
+static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc)
+{
+ lbaint_t blks;
+
+ debug("Start Erasing mmc hwpart[%u]...\n", dev_desc->hwpart);
+
+ blks = fb_mmc_blk_write(dev_desc, 0, dev_desc->lba, NULL);
+
+ if (blks != dev_desc->lba) {
+ pr_err("Failed to erase mmc hwpart[%u]\n", dev_desc->hwpart);
+ return 1;
+ }
+
+ printf(" erased %lu bytes from mmc hwpart[%u]\n",
+ dev_desc->lba * dev_desc->blksz, dev_desc->hwpart);
+
+ return 0;
+}
+
+static void fb_mmc_boot1_ops(struct blk_desc *dev_desc, void *buffer,
+u32 buff_sz, char *response)
+{
+ lbaint_t blkcnt;
+ lbaint_t blks;
+ unsigned long blksz;
+
+ // To operate on EMMC_BOOT1 (mmc0boot0), we first change the hwpart
+ if (blk_dselect_hwpart(dev_desc, 1)) {
+ pr_err("Failed to select hwpart\n");
+ fastboot_fail("Failed to select hwpart", response);
+ return;
+ }
+
+ if (buffer) { /* flash */
+
+ /* determine number of blocks to write */
+ blksz = dev_desc->blksz;
+ blkcnt = ((buff_sz + (blksz - 1)) & ~(blksz - 1));
+ blkcnt = lldiv(blkcnt, blksz);
+
+ if (blkcnt > dev_desc->lba) {
+ pr_err("Image size too large\n");
+ fastboot_fail(&
[PATCH v2 2/6] ARM: Mediatek: Add board_late_init to init usb gadget driver
Add board_late_init function to init usb gadget driver for mt8518
Signed-off-by: mingming lee
---
board/mediatek/mt8518/mt8518_ap1.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/board/mediatek/mt8518/mt8518_ap1.c
b/board/mediatek/mt8518/mt8518_ap1.c
index 9710907fe2..2ac7c6cd18 100644
--- a/board/mediatek/mt8518/mt8518_ap1.c
+++ b/board/mediatek/mt8518/mt8518_ap1.c
@@ -16,3 +16,21 @@ int board_init(void)
debug("gd->fdt_blob is %p\n", gd->fdt_blob);
return 0;
}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_USB_GADGET
+ struct udevice *dev;
+ int ret;
+#endif
+
+#ifdef CONFIG_USB_GADGET
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, );
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
--
2.24.1
[PATCH v2 1/6] usb: musb-new: mt85xx: add musb-new gadget driver.
Using musb-new structure for mt85xx gadget driver.
Add gadget driver dts for mt8518 SoCs.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 13 ++
drivers/usb/musb-new/Kconfig | 11 +-
drivers/usb/musb-new/Makefile | 1 +
drivers/usb/musb-new/mt85xx.c | 417 ++
4 files changed, 441 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/musb-new/mt85xx.c
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
index c2d17fda4a..56da91a9fe 100644
--- a/arch/arm/dts/mt8518.dtsi
+++ b/arch/arm/dts/mt8518.dtsi
@@ -74,6 +74,19 @@
};
};
+ usb0: usb@1110 {
+ compatible = "mediatek,mt8518-musb";
+ reg = <0x1110 0x1000>;
+ reg-names = "control";
+ clocks = < CLK_TOP_USB20_48M>,
+< CLK_TOP_USBIF>,
+< CLK_TOP_USB>;
+ clock-names = "usbpll", "usbmcu", "usb";
+ interrupts = ;
+ interrupt-names = "mc";
+ status = "okay";
+ };
+
mmc0: mmc@1112 {
compatible = "mediatek,mt8516-mmc";
reg = <0x1112 0x1000>;
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 79ad14ef66..6cf8a2b60b 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -47,6 +47,15 @@ config USB_MUSB_DSPS
bool "TI DSPS platforms"
if USB_MUSB_HOST || USB_MUSB_GADGET
+config USB_MUSB_MT85XX
+ bool "Enable Mediatek MT85XX DRC USB controller"
+ depends on DM_USB && ARCH_MEDIATEK
+ default n
+ help
+ Say y to enable Mediatek MT85XX USB DRC controller support
+ if it is available on your Mediatek MUSB IP based platform.
+ DMA controllers are ignored. This driver follow musb-new
+ driver and usb gadget framework.
config USB_MUSB_PIC32
bool "Enable Microchip PIC32 DRC USB controller"
@@ -76,7 +85,7 @@ endif
config USB_MUSB_PIO_ONLY
bool "Disable DMA (always use PIO)"
- default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS ||
USB_MUSB_DSPS || USB_MUSB_SUNXI
+ default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS ||
USB_MUSB_DSPS || USB_MUSB_SUNXI || USB_MUSB_MT85XX
help
All data is copied between memory and FIFO by the CPU.
DMA controllers are ignored.
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index ec7852ce94..6355eb12dd 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o
musb_uboot.o
obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
+obj-$(CONFIG_USB_MUSB_MT85XX) += mt85xx.o
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
diff --git a/drivers/usb/musb-new/mt85xx.c b/drivers/usb/musb-new/mt85xx.c
new file mode 100644
index 00..131fd7dd79
--- /dev/null
+++ b/drivers/usb/musb-new/mt85xx.c
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek "glue layer"
+ *
+ * Copyright (C) 2019-2021 by Mediatek
+ * Based on the AllWinner SUNXI "glue layer" code.
+ * Copyright (C) 2015 Hans de Goede
+ * Copyright (C) 2013 Jussi Kivilinna
+ *
+ * This file is part of the Inventra Controller Driver for Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+#define DBG_I(fmt, ...) \
+ pr_info(fmt, ##__VA_ARGS__)
+
+struct mtk_musb_config {
+ struct musb_hdrc_config *config;
+};
+
+struct mtk_musb_glue {
+ struct musb_host_data mdata;
+ struct clk usbpllclk;
+ struct clk usbmcuclk;
+ struct clk usbclk;
+ struct mtk_musb_config *cfg;
+ struct device dev;
+};
+
+#define to_mtk_musb_glue(d)container_of(d, struct mtk_musb_glue, dev)
+
+/**
+ * phy settings
+
**/
+#define USB20_PHY_BASE 0x0800
+#define USBPHY_READ8(offset)\
+ readb((void *)(USB20_PHY_BASE + (offset)))
+#define USBPHY_WRITE8(offset, value) \
+ writeb(value, (void *)(USB20_PHY_BASE + (offset)))
+#define USBPHY_SET8(offset, mask) \
+ USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) | (mask))
+#define USBPHY_CLR8(offset, mask) \
+ USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) & (~(mask)))
+
+static void mt_usb_phy_po
[PATCH v2 0/6] Add fastboot support for MediaTek mt8518
This patch series adds basic fastboot support for MediaTek MT8518 EMMC boards, including musb-new structure for gadget driver and fastboot related configs. --- Changes for v2: - Limit the config in this patch depends on ARCH_MEDIATEK. - config all the added function,avoid affect other IC config. - fixed the build error for other defconfig,such as dra7xx_evm_defconfig. mingming lee (6): usb: musb-new: mt85xx: add musb-new gadget driver. ARM: Mediatek: Add board_late_init to init usb gadget driver configs: mt8518: set global variables for fastboot configs: mt8518: enable usb gadget driver configs: mt8518: Enable fastboot related configs fastboot: mt85xx: add command to flash/erase emmc hwpart arch/arm/dts/mt8518.dtsi | 13 + board/mediatek/mt8518/mt8518_ap1.c | 18 ++ configs/mt8518_ap1_emmc_defconfig | 22 ++ drivers/fastboot/Kconfig | 30 +++ drivers/fastboot/fb_mmc.c | 102 +++ drivers/usb/musb-new/Kconfig | 11 +- drivers/usb/musb-new/Makefile | 1 + drivers/usb/musb-new/mt85xx.c | 417 + include/configs/mt8518.h | 10 +- 9 files changed, 619 insertions(+), 5 deletions(-) create mode 100644 drivers/usb/musb-new/mt85xx.c -- 2.24.1
[PATCH v2 5/6] configs: mt8518: Enable fastboot related configs
Enable EFI module. Enable fastboot. Signed-off-by: mingming lee --- configs/mt8518_ap1_emmc_defconfig | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index 9857b7b776..714fd8e087 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -34,6 +34,7 @@ CONFIG_WDT_MTK=y CONFIG_CLK=y CONFIG_TIMER=y CONFIG_MTK_TIMER=y +CONFIG_MMC=y CONFIG_CMD_MMC=y CONFIG_DM_MMC=y CONFIG_MMC_MTK=y @@ -48,4 +49,14 @@ CONFIG_USB_MUSB_MT85XX=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 CONFIG_USB_GADGET_PRODUCT_NUM=0x0c01 -CONFIG_USB_GADGET_MANUFACTURER="Mediatek." \ No newline at end of file +CONFIG_USB_GADGET_MANUFACTURER="Mediatek." +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_GPT_NAME=GPT +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_BUF_ADDR=0x5600 +CONFIG_FASTBOOT_BUF_SIZE=0x1E0 -- 2.24.1
[PATCH v2 3/6] configs: mt8518: set global variables for fastboot
set common fastboot variables for mt8518 Signed-off-by: mingming lee --- include/configs/mt8518.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 8906245a62..9bc9c04e66 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -11,9 +11,6 @@ #include -#define CONFIG_ENV_SIZESZ_4K - -/* Machine ID */ #define CONFIG_SYS_NONCACHED_MEMORYSZ_1M #define CONFIG_CPU_ARMV8 @@ -39,7 +36,7 @@ /* ENV Setting */ #if defined(CONFIG_MMC_MTK) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET 0x4E6 + #define CONFIG_ENV_OVERWRITE /* MMC offset in block unit,and block size is 0x200 */ @@ -58,10 +55,15 @@ #define ENV_BOOT_CMD \ "mtk_boot=run boot_rd_img;bootm;\0" +#define ENV_FASTBOOT \ + "serial#=1234567890ABCDEF\0" \ + "board=mt8518\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6c00\0" \ ENV_DEVICE_SETTINGS \ ENV_BOOT_READ_IMAGE \ + ENV_FASTBOOT \ ENV_BOOT_CMD \ "bootcmd=run mtk_boot;\0" \ -- 2.24.1
[PATCH v2 4/6] configs: mt8518: enable usb gadget driver
Enable board_late_init and usb gadget for mt8518 Signed-off-by: mingming lee --- configs/mt8518_ap1_emmc_defconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index dd42076f4d..9857b7b776 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -39,3 +39,13 @@ CONFIG_DM_MMC=y CONFIG_MMC_MTK=y CONFIG_MMC_HS200_SUPPORT=y # CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOARD_LATE_INIT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_MT85XX=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0c01 +CONFIG_USB_GADGET_MANUFACTURER="Mediatek." \ No newline at end of file -- 2.24.1
Re: [PATCH 6/6] fastboot: mt85xx: add command to flash/erase emmc hwpart
On Wed, 2020-01-15 at 15:48 -0500, Tom Rini wrote: > On Mon, Jan 06, 2020 at 02:26:49PM +0800, mingming lee wrote: > > > This patch includes the following: > > 1. Add fastboot command to erase the whole EMMC_USER > > 2. Add fastboot command to flash image at EMMC_BOOT1 > > 3. Add fastboot command to erase the whole EMMC_BOOT1 > > 4. Enale CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT for mt8518 > > > > Signed-off-by: mingming lee > > This breaks building of dra7xx_evm and possibly others, thanks. > hi Tom, Thank you very much for the review, I would fixed it in the next version. By The way, I wonder could U pls share your way for check? Then in the futher I could check it all on my local before submit.
[PATCH 0/6] Add fastboot support for MediaTek mt8518
This patch series adds basic fastboot support for MediaTek MT8518 EMMC boards, including musb-new structure for gadget driver and fastboot related configs. mingming lee (6): usb: musb-new: mt85xx: add musb-new gadget driver. ARM: Mediatek: Add board_late_init to init usb gadget driver configs: mt8518: set global variables for fastboot configs: mt8518: enable usb gadget driver configs: mt8518: Enable fastboot related configs fastboot: mt85xx: add command to flash/erase emmc hwpart arch/arm/dts/mt8518.dtsi | 13 + board/mediatek/mt8518/mt8518_ap1.c | 18 ++ configs/mt8518_ap1_emmc_defconfig | 22 ++ drivers/fastboot/Kconfig | 30 +++ drivers/fastboot/fb_mmc.c | 98 ++- drivers/usb/musb-new/Kconfig | 11 +- drivers/usb/musb-new/Makefile | 1 + drivers/usb/musb-new/mt85xx.c | 417 + include/configs/mt8518.h | 10 +- 9 files changed, 614 insertions(+), 6 deletions(-) create mode 100644 drivers/usb/musb-new/mt85xx.c -- 2.24.1
[PATCH 1/6] usb: musb-new: mt85xx: add musb-new gadget driver.
Using musb-new structure for mt85xx gadget driver.
Add gadget driver dts for mt8518 SoCs.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 13 ++
drivers/usb/musb-new/Kconfig | 11 +-
drivers/usb/musb-new/Makefile | 1 +
drivers/usb/musb-new/mt85xx.c | 417 ++
4 files changed, 441 insertions(+), 1 deletion(-)
create mode 100644 drivers/usb/musb-new/mt85xx.c
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
index c2d17fda4a..56da91a9fe 100644
--- a/arch/arm/dts/mt8518.dtsi
+++ b/arch/arm/dts/mt8518.dtsi
@@ -74,6 +74,19 @@
};
};
+ usb0: usb@1110 {
+ compatible = "mediatek,mt8518-musb";
+ reg = <0x1110 0x1000>;
+ reg-names = "control";
+ clocks = < CLK_TOP_USB20_48M>,
+< CLK_TOP_USBIF>,
+< CLK_TOP_USB>;
+ clock-names = "usbpll", "usbmcu", "usb";
+ interrupts = ;
+ interrupt-names = "mc";
+ status = "okay";
+ };
+
mmc0: mmc@1112 {
compatible = "mediatek,mt8516-mmc";
reg = <0x1112 0x1000>;
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 79ad14ef66..6cf8a2b60b 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -47,6 +47,15 @@ config USB_MUSB_DSPS
bool "TI DSPS platforms"
if USB_MUSB_HOST || USB_MUSB_GADGET
+config USB_MUSB_MT85XX
+ bool "Enable Mediatek MT85XX DRC USB controller"
+ depends on DM_USB && ARCH_MEDIATEK
+ default n
+ help
+ Say y to enable Mediatek MT85XX USB DRC controller support
+ if it is available on your Mediatek MUSB IP based platform.
+ DMA controllers are ignored. This driver follow musb-new
+ driver and usb gadget framework.
config USB_MUSB_PIC32
bool "Enable Microchip PIC32 DRC USB controller"
@@ -76,7 +85,7 @@ endif
config USB_MUSB_PIO_ONLY
bool "Disable DMA (always use PIO)"
- default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS ||
USB_MUSB_DSPS || USB_MUSB_SUNXI
+ default y if USB_MUSB_AM35X || USB_MUSB_PIC32 || USB_MUSB_OMAP2PLUS ||
USB_MUSB_DSPS || USB_MUSB_SUNXI || USB_MUSB_MT85XX
help
All data is copied between memory and FIFO by the CPU.
DMA controllers are ignored.
diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile
index ec7852ce94..6355eb12dd 100644
--- a/drivers/usb/musb-new/Makefile
+++ b/drivers/usb/musb-new/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_USB_MUSB_HOST) += musb_host.o musb_core.o
musb_uboot.o
obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o
obj-$(CONFIG_USB_MUSB_DA8XX) += da8xx.o
obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o
+obj-$(CONFIG_USB_MUSB_MT85XX) += mt85xx.o
obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o
obj-$(CONFIG_USB_MUSB_PIC32) += pic32.o
obj-$(CONFIG_USB_MUSB_SUNXI) += sunxi.o
diff --git a/drivers/usb/musb-new/mt85xx.c b/drivers/usb/musb-new/mt85xx.c
new file mode 100644
index 00..131fd7dd79
--- /dev/null
+++ b/drivers/usb/musb-new/mt85xx.c
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Mediatek "glue layer"
+ *
+ * Copyright (C) 2019-2021 by Mediatek
+ * Based on the AllWinner SUNXI "glue layer" code.
+ * Copyright (C) 2015 Hans de Goede
+ * Copyright (C) 2013 Jussi Kivilinna
+ *
+ * This file is part of the Inventra Controller Driver for Linux.
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "linux-compat.h"
+#include "musb_core.h"
+#include "musb_uboot.h"
+
+#define DBG_I(fmt, ...) \
+ pr_info(fmt, ##__VA_ARGS__)
+
+struct mtk_musb_config {
+ struct musb_hdrc_config *config;
+};
+
+struct mtk_musb_glue {
+ struct musb_host_data mdata;
+ struct clk usbpllclk;
+ struct clk usbmcuclk;
+ struct clk usbclk;
+ struct mtk_musb_config *cfg;
+ struct device dev;
+};
+
+#define to_mtk_musb_glue(d)container_of(d, struct mtk_musb_glue, dev)
+
+/**
+ * phy settings
+
**/
+#define USB20_PHY_BASE 0x0800
+#define USBPHY_READ8(offset)\
+ readb((void *)(USB20_PHY_BASE + (offset)))
+#define USBPHY_WRITE8(offset, value) \
+ writeb(value, (void *)(USB20_PHY_BASE + (offset)))
+#define USBPHY_SET8(offset, mask) \
+ USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) | (mask))
+#define USBPHY_CLR8(offset, mask) \
+ USBPHY_WRITE8(offset, (USBPHY_READ8(offset)) & (~(mask)))
+
+static void mt_usb_phy_po
[PATCH 3/6] configs: mt8518: set global variables for fastboot
set common fastboot variables for mt8518 Signed-off-by: mingming lee --- include/configs/mt8518.h | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 8906245a62..9bc9c04e66 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -11,9 +11,6 @@ #include -#define CONFIG_ENV_SIZESZ_4K - -/* Machine ID */ #define CONFIG_SYS_NONCACHED_MEMORYSZ_1M #define CONFIG_CPU_ARMV8 @@ -39,7 +36,7 @@ /* ENV Setting */ #if defined(CONFIG_MMC_MTK) #define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET 0x4E6 + #define CONFIG_ENV_OVERWRITE /* MMC offset in block unit,and block size is 0x200 */ @@ -58,10 +55,15 @@ #define ENV_BOOT_CMD \ "mtk_boot=run boot_rd_img;bootm;\0" +#define ENV_FASTBOOT \ + "serial#=1234567890ABCDEF\0" \ + "board=mt8518\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0x6c00\0" \ ENV_DEVICE_SETTINGS \ ENV_BOOT_READ_IMAGE \ + ENV_FASTBOOT \ ENV_BOOT_CMD \ "bootcmd=run mtk_boot;\0" \ -- 2.24.1
[PATCH 6/6] fastboot: mt85xx: add command to flash/erase emmc hwpart
This patch includes the following:
1. Add fastboot command to erase the whole EMMC_USER
2. Add fastboot command to flash image at EMMC_BOOT1
3. Add fastboot command to erase the whole EMMC_BOOT1
4. Enale CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT for mt8518
Signed-off-by: mingming lee
---
configs/mt8518_ap1_emmc_defconfig | 1 +
drivers/fastboot/Kconfig | 30 ++
drivers/fastboot/fb_mmc.c | 98 ++-
3 files changed, 128 insertions(+), 1 deletion(-)
diff --git a/configs/mt8518_ap1_emmc_defconfig
b/configs/mt8518_ap1_emmc_defconfig
index 714fd8e087..e929d40d75 100644
--- a/configs/mt8518_ap1_emmc_defconfig
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -60,3 +60,4 @@ CONFIG_FASTBOOT_FLASH_MMC=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_BUF_ADDR=0x5600
CONFIG_FASTBOOT_BUF_SIZE=0x1E0
+CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
\ No newline at end of file
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index 433ea0dc3b..a4cf52dc9a 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -104,6 +104,36 @@ config FASTBOOT_FLASH_NAND_TRIMFFS
When flashing NAND enable the DROP_FFS flag to drop trailing all-0xff
pages.
+config FASTBOOT_MMC_BOOT1_SUPPORT
+ bool "Enable EMMC_BOOT1 flash/erase"
+ depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
+ help
+ The fastboot "flash" and "erase" commands normally does operations
+ on EMMC userdata. Define this to enable the special commands to
+ flash/erase EMMC_BOOT1.
+ The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+
+config FASTBOOT_MMC_BOOT1_NAME
+ string "Target name for updating EMMC_BOOT1"
+ depends on FASTBOOT_MMC_BOOT1_SUPPORT
+ default "mmc0boot0"
+ help
+ The fastboot "flash" and "erase" commands support operations on
+ EMMC_BOOT1. This occurs when the specified "EMMC_BOOT1 name" on
+ the "fastboot flash" and "fastboot erase" commands match the value
+ defined here.
+ The default target name for updating EMMC_BOOT1 is "mmc0boot0".
+
+config FASTBOOT_MMC_USER_NAME
+ string "Target name for erasing EMMC_USER"
+ depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
+ default "mmc0"
+ help
+ The fastboot "erase" command supports erasing EMMC_USER. This occurs
+ when the specified "EMMC_USER name" on the "fastboot erase" commands
+ match the value defined here.
+ The default target name for erasing EMMC_USER is "mmc0".
+
config FASTBOOT_GPT_NAME
string "Target name for updating GPT"
depends on FASTBOOT_FLASH_MMC && EFI_PARTITION
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index b0b19c5762..4eabbfdf3d 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -129,6 +129,76 @@ static void write_raw_image(struct blk_desc *dev_desc,
disk_partition_t *info,
fastboot_okay(NULL, response);
}
+#ifdef CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT
+static int fb_mmc_erase_mmc_hwpart(struct blk_desc *dev_desc)
+{
+ lbaint_t blks;
+
+ debug("Start Erasing mmc hwpart[%u]...\n", dev_desc->hwpart);
+
+ blks = fb_mmc_blk_write(dev_desc, 0, dev_desc->lba, NULL);
+
+ if (blks != dev_desc->lba) {
+ pr_err("Failed to erase mmc hwpart[%u]\n", dev_desc->hwpart);
+ return 1;
+ }
+
+ printf(" erased %lu bytes from mmc hwpart[%u]\n",
+ dev_desc->lba * dev_desc->blksz, dev_desc->hwpart);
+
+ return 0;
+}
+
+static void fb_mmc_boot1_ops(struct blk_desc *dev_desc, void *buffer,
+u32 buff_sz, char *response)
+{
+ lbaint_t blkcnt;
+ lbaint_t blks;
+ unsigned long blksz;
+
+ // To operate on EMMC_BOOT1 (mmc0boot0), we first change the hwpart
+ if (blk_dselect_hwpart(dev_desc, 1)) {
+ pr_err("Failed to select hwpart\n");
+ fastboot_fail("Failed to select hwpart", response);
+ return;
+ }
+
+ if (buffer) { /* flash */
+
+ /* determine number of blocks to write */
+ blksz = dev_desc->blksz;
+ blkcnt = ((buff_sz + (blksz - 1)) & ~(blksz - 1));
+ blkcnt = lldiv(blkcnt, blksz);
+
+ if (blkcnt > dev_desc->lba) {
+ pr_err("Image size too large\n");
+ fastboot_fail("Image size too large", response);
+ return;
+ }
+
+ debug("Start Flashing Image to EMMC_BOOT1...\n");
+
+ blks = fb
[PATCH 4/6] configs: mt8518: enable usb gadget driver
Enable board_late_init and usb gadget for mt8518 Signed-off-by: mingming lee --- configs/mt8518_ap1_emmc_defconfig | 10 ++ 1 file changed, 10 insertions(+) diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index dd42076f4d..9857b7b776 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -39,3 +39,13 @@ CONFIG_DM_MMC=y CONFIG_MMC_MTK=y CONFIG_MMC_HS200_SUPPORT=y # CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOARD_LATE_INIT=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_USB_MUSB_GADGET=y +CONFIG_USB_MUSB_MT85XX=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0c01 +CONFIG_USB_GADGET_MANUFACTURER="Mediatek." \ No newline at end of file -- 2.24.1
[PATCH 5/6] configs: mt8518: Enable fastboot related configs
Enable EFI module. Enable fastboot. Signed-off-by: mingming lee --- configs/mt8518_ap1_emmc_defconfig | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index 9857b7b776..714fd8e087 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -34,6 +34,7 @@ CONFIG_WDT_MTK=y CONFIG_CLK=y CONFIG_TIMER=y CONFIG_MTK_TIMER=y +CONFIG_MMC=y CONFIG_CMD_MMC=y CONFIG_DM_MMC=y CONFIG_MMC_MTK=y @@ -48,4 +49,14 @@ CONFIG_USB_MUSB_MT85XX=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_GADGET_VENDOR_NUM=0x0bb4 CONFIG_USB_GADGET_PRODUCT_NUM=0x0c01 -CONFIG_USB_GADGET_MANUFACTURER="Mediatek." \ No newline at end of file +CONFIG_USB_GADGET_MANUFACTURER="Mediatek." +CONFIG_EFI_PARTITION=y +CONFIG_FASTBOOT_GPT_NAME=GPT +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_BUF_ADDR=0x5600 +CONFIG_FASTBOOT_BUF_SIZE=0x1E0 -- 2.24.1
[PATCH 2/6] ARM: Mediatek: Add board_late_init to init usb gadget driver
Add board_late_init function to init usb gadget driver for mt8518
Signed-off-by: mingming lee
---
board/mediatek/mt8518/mt8518_ap1.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/board/mediatek/mt8518/mt8518_ap1.c
b/board/mediatek/mt8518/mt8518_ap1.c
index 9710907fe2..2ac7c6cd18 100644
--- a/board/mediatek/mt8518/mt8518_ap1.c
+++ b/board/mediatek/mt8518/mt8518_ap1.c
@@ -16,3 +16,21 @@ int board_init(void)
debug("gd->fdt_blob is %p\n", gd->fdt_blob);
return 0;
}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_USB_GADGET
+ struct udevice *dev;
+ int ret;
+#endif
+
+#ifdef CONFIG_USB_GADGET
+ ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, );
+ if (ret) {
+ pr_err("%s: Cannot find USB device\n", __func__);
+ return ret;
+ }
+#endif
+
+ return 0;
+}
--
2.24.1
[PATCH v2 3/8] clk: mediatek: add set_clr_upd mux type flow
Add new set_clr_upd mux type and related operation to
mtk common clock driver to support mt8512
---
drivers/clk/mediatek/clk-mtk.c | 43 +-
drivers/clk/mediatek/clk-mtk.h | 23 ++
2 files changed, 55 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 6c6b500d9b..450de981e9 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32
parent,
if (++index == mux->num_parents)
return -EINVAL;
- /* switch mux to a select parent */
- val = readl(base + mux->mux_reg);
- val &= ~(mux->mux_mask << mux->mux_shift);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = (mux->mux_mask << mux->mux_shift);
+ writel(val, base + mux->mux_clr_reg);
- val |= index << mux->mux_shift;
- writel(val, base + mux->mux_reg);
+ val = (index << mux->mux_shift);
+ writel(val, base + mux->mux_set_reg);
+
+ if (mux->upd_shift >= 0)
+ writel(BIT(mux->upd_shift), base + mux->upd_reg);
+ } else {
+ /* switch mux to a select parent */
+ val = readl(base + mux->mux_reg);
+ val &= ~(mux->mux_mask << mux->mux_shift);
+
+ val |= index << mux->mux_shift;
+ writel(val, base + mux->mux_reg);
+ }
return 0;
}
@@ -332,9 +343,14 @@ static int mtk_topckgen_enable(struct clk *clk)
return 0;
/* enable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val &= ~BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_clr_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val &= ~BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
if (mux->flags & CLK_DOMAIN_SCPSYS) {
/* enable scpsys clock off control */
@@ -360,9 +376,14 @@ static int mtk_topckgen_disable(struct clk *clk)
return 0;
/* disable clock gate */
- val = readl(priv->base + mux->gate_reg);
- val |= BIT(mux->gate_shift);
- writel(val, priv->base + mux->gate_reg);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = BIT(mux->gate_shift);
+ writel(val, priv->base + mux->mux_set_reg);
+ } else {
+ val = readl(priv->base + mux->gate_reg);
+ val |= BIT(mux->gate_shift);
+ writel(val, priv->base + mux->gate_reg);
+ }
return 0;
}
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index dce93253ad..7ea0042500 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -12,6 +12,7 @@
#define HAVE_RST_BAR BIT(0)
#define CLK_DOMAIN_SCPSYS BIT(0)
+#define CLK_MUX_SETCLR_UPD BIT(1)
#define CLK_GATE_SETCLRBIT(0)
#define CLK_GATE_SETCLR_INVBIT(1)
@@ -102,9 +103,13 @@ struct mtk_composite {
const int id;
const int *parent;
u32 mux_reg;
+ u32 mux_set_reg;
+ u32 mux_clr_reg;
+ u32 upd_reg;
u32 gate_reg;
u32 mux_mask;
signed char mux_shift;
+ signed char upd_shift;
signed char gate_shift;
signed char num_parents;
u16 flags;
@@ -137,6 +142,24 @@ struct mtk_composite {
.flags = 0, \
}
+#define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
+ _mux_clr_ofs, _shift, _width, _gate,\
+ _upd_ofs, _upd, _flags) { \
+ .id = _id, \
+ .mux_reg = _mux_ofs,\
+ .mux_set_reg = _mux_set_ofs,\
+ .mux_clr_reg = _mux_clr_ofs,\
+ .upd_reg = _upd_ofs,\
+ .upd_shift = _upd, \
+ .mux_shift = _shift,\
+ .mux_mask = BIT(_width) - 1,\
+ .gate_reg = _mux_ofs, \
+ .gate_shift = _gate,\
+ .parent = _parents, \
+ .num_parents = ARRAY_SIZE(_parents),\
+ .flags = _flags,
[PATCH v2 8/8] ARM: MediaTek: add basic support for MT8512 boards
This adds a general board file based on MT8512 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8512 eMMC board.
Signed-off-by: mingming lee
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8512-bm1-emmc.dts | 106 ++
board/mediatek/mt8512/Kconfig | 14
board/mediatek/mt8512/MAINTAINERS | 6 ++
board/mediatek/mt8512/Makefile| 3 +
board/mediatek/mt8512/mt8512.c| 19 ++
configs/mt8512_bm1_emmc_defconfig | 44 +
include/configs/mt8512.h | 60 +
8 files changed, 253 insertions(+)
create mode 100644 arch/arm/dts/mt8512-bm1-emmc.dts
create mode 100644 board/mediatek/mt8512/Kconfig
create mode 100644 board/mediatek/mt8512/MAINTAINERS
create mode 100644 board/mediatek/mt8512/Makefile
create mode 100644 board/mediatek/mt8512/mt8512.c
create mode 100644 configs/mt8512_bm1_emmc_defconfig
create mode 100644 include/configs/mt8512.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c..57cae40d83 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -835,6 +835,7 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
+ mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts
new file mode 100644
index 00..296ed93b9e
--- /dev/null
+++ b/arch/arm/dts/mt8512-bm1-emmc.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8512.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8512 BM1 EMMC";
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x2000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ bus-width = <8>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/board/mediatek/mt8512/Kconfig b/board/mediatek/mt8512/Kconfig
new file mode 100644
index 00..87bd1fbe69
--- /dev/null
+++ b/board/mediatek/mt8512/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MT8
[PATCH v2 5/8] pinctrl: mediatek: add driver for MT8512
Add Pinctrl driver for MediaTek MT8512 SoC.
Signed-off-by: mingming lee
---
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8512.c | 387 ++
3 files changed, 392 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8512.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 22ee62362b..9c6b580fde 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -12,6 +12,10 @@ config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8512
+ bool "MT8512 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index 0ab7b1595b..ba955575cf 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -5,5 +5,6 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
new file mode 100644
index 00..af43754a4d
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, true)
+#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 30, false)
+
+static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = {
+ PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = {
+ PIN_FIELD(0, 115, 0x140, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_di_range[] = {
+ PIN_FIELD(0, 115, 0x000, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_do_range[] = {
+ PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = {
+ PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = {
+ PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = {
+ PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1),
+ PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1),
+ PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1),
+ PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1),
+ PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1),
+ PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1),
+ PIN_FIELD(20, 20, 0x410, 0x10, 6, 1),
+ PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1),
+ PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1),
+ PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1),
+ PIN_FIELD(32, 32, 0x410, 0x10, 10, 1),
+ PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1),
+ PIN_FIELD(40, 40, 0x410, 0x10, 12, 1),
+ PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1),
+ PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1),
+ PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1),
+ PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1),
+ PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1),
+ PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1),
+ PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1),
+ PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1),
+ PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1),
+ PIN_FIELD(70, 70, 0x410, 0x10, 22, 1),
+ PIN_FIELD(71, 71, 0x410, 0x10, 23, 1),
+ PIN_FIELD(72, 72, 0x410, 0x10, 24, 1),
+ PIN_FIELD(73, 73, 0x410, 0x10, 25, 1),
+ PIN_FIELD(74, 74, 0x410, 0x10, 26, 1),
+ PIN_FIELD(75, 75, 0x410, 0x10, 27, 1),
+ PIN_FIELD(76, 76, 0x410, 0x10, 28, 1),
+ PIN_FIELD(77, 77, 0x410, 0x10, 29, 1),
+ PIN_FIELD(78, 78, 0x410, 0x10, 30, 1),
+ PIN_FIELD(79, 79, 0x410, 0x10, 31, 1),
+ PIN_FIELD(80, 80, 0x420, 0x10, 0, 1),
+ PIN_FIELD(81, 81, 0x420, 0x10, 1, 1),
+ PIN_FIELD(82, 82, 0x420, 0x10, 2, 1),
+ PIN_FIELD(83, 83, 0x420, 0x10, 3, 1),
+ PIN_FIELD(84, 84, 0x420, 0x10, 4, 1),
+ PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1),
+ PIN_FIELD(87, 87, 0x420, 0x10,
[PATCH v2 2/8] clk: mediatek: add driver support for MT8512
Add clock driver for MediaTek MT8512 SoC, include topckgen,
apmixedsys and infracfg support.
Signed-off-by: mingming lee
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8512.c | 873 +
include/dt-bindings/clock/mt8512-clk.h | 197 ++
3 files changed, 1071 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8512.c
create mode 100644 include/dt-bindings/clock/mt8512-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e92bcd4efe..b82243885c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,6 +3,7 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8512.c
b/drivers/clk/mediatek/clk-mt8512.c
new file mode 100644
index 00..cb168f146b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -0,0 +1,873 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8512 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT8512_PLL_FMAX(3800UL * MHZ)
+#define MT8512_PLL_FMIN(1500UL * MHZ)
+#define MT8512_CON0_RST_BARBIT(23)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) {\
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT8512_CON0_RST_BAR,\
+ .fmax = MT8512_PLL_FMAX,\
+ .fmin = MT8512_PLL_FMIN,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pcwibits = 8, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ .pcw_chg_reg = _pcw_chg_reg,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x0001,
+ 0, 22, 0x0310, 24, 0x0310, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x0001,
+ HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
+ PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x0001,
+ HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x0001,
+ 0, 22, 0x0354, 24, 0x0354, 0, 0),
+ PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x0001,
+ 0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
+ PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x0001,
+ 0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
+ PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x0001,
+ 0, 22, 0x0378, 24, 0x0378, 0, 0),
+ PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x0001,
+ 0, 22, 0x0394, 24, 0x0394, 0, 0),
+ PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x0001,
+ 0, 22, 0x03A4, 24, 0x03A4, 0, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 2600),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
+ FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+ FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAIN
[PATCH v2 0/8] Add support for MediaTek MT8512 Soc
This patch series adds basic boot support on eMMC for the MediaTek MT8512 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. --- Changes for v2: - Sort device nodes reg address order and alphabetically. - Split the changes in mtk clk for 8512 into two patchs. - Delete fix patch for clock-rate overflow in mtk clk since have been included in changelist 1207053 mingming lee (8): ARM: MediaTek: Add support for MediaTek MT8512 SoC clk: mediatek: add driver support for MT8512 clk: mediatek: add set_clr_upd mux type flow clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll pinctrl: mediatek: add driver for MT8512 mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs mmc: mtk-sd: fix hang when data read quickly ARM: MediaTek: add basic support for MT8512 boards arch/arm/dts/Makefile | 1 + arch/arm/dts/mt8512-bm1-emmc.dts | 106 +++ arch/arm/dts/mt8512.dtsi | 115 +++ arch/arm/mach-mediatek/Kconfig| 15 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8512/Makefile| 4 + arch/arm/mach-mediatek/mt8512/init.c | 78 ++ arch/arm/mach-mediatek/mt8512/lowlevel_init.S | 32 + board/mediatek/mt8512/Kconfig | 14 + board/mediatek/mt8512/MAINTAINERS | 6 + board/mediatek/mt8512/Makefile| 3 + board/mediatek/mt8512/mt8512.c| 19 + configs/mt8512_bm1_emmc_defconfig | 44 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8512.c | 873 ++ drivers/clk/mediatek/clk-mtk.c| 68 +- drivers/clk/mediatek/clk-mtk.h| 26 + drivers/mmc/mtk-sd.c | 140 ++- drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8512.c | 387 include/configs/mt8512.h | 60 ++ include/dt-bindings/clock/mt8512-clk.h| 197 23 files changed, 2138 insertions(+), 57 deletions(-) create mode 100644 arch/arm/dts/mt8512-bm1-emmc.dts create mode 100644 arch/arm/dts/mt8512.dtsi create mode 100644 arch/arm/mach-mediatek/mt8512/Makefile create mode 100644 arch/arm/mach-mediatek/mt8512/init.c create mode 100644 arch/arm/mach-mediatek/mt8512/lowlevel_init.S create mode 100644 board/mediatek/mt8512/Kconfig create mode 100644 board/mediatek/mt8512/MAINTAINERS create mode 100644 board/mediatek/mt8512/Makefile create mode 100644 board/mediatek/mt8512/mt8512.c create mode 100644 configs/mt8512_bm1_emmc_defconfig create mode 100644 drivers/clk/mediatek/clk-mt8512.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8512.c create mode 100644 include/configs/mt8512.h create mode 100644 include/dt-bindings/clock/mt8512-clk.h -- 2.24.1
[PATCH v2 7/8] mmc: mtk-sd: fix hang when data read quickly
For CMD21 tuning data, the 128/64 bytes data may coming in very short time, before msdc_start_data(), the read data has already come, in this case, clear MSDC_INT will cause the interrupt disappear and lead to the thread hang. the solution is just clear all interrupts before command was sent. Signed-off-by: mingming lee --- drivers/mmc/mtk-sd.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 23413731dc..b0365877d7 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -531,6 +530,7 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd, blocks = data->blocks; writel(CMD_INTS_MASK, >base->msdc_int); + writel(DATA_INTS_MASK, >base->msdc_int); writel(blocks, >base->sdc_blk_num); writel(cmd->cmdarg, >base->sdc_arg); writel(rawcmd, >base->sdc_cmd); @@ -677,13 +677,9 @@ static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) u32 size; int ret; - WATCHDOG_RESET(); - if (data->flags == MMC_DATA_WRITE) host->last_data_write = 1; - writel(DATA_INTS_MASK, >base->msdc_int); - size = data->blocks * data->blocksize; if (data->flags == MMC_DATA_WRITE) -- 2.24.1
[PATCH v2 6/8] mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs.
MT8512/MT8110 SoCs puts the tune register at top layer, so
need add new code to support it.
Signed-off-by: mingming lee
---
drivers/mmc/mtk-sd.c | 134 ---
1 file changed, 101 insertions(+), 33 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index eaa584a4df..23413731dc 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -135,6 +136,25 @@
#define SDC_FIFO_CFG_WRVALIDSELBIT(24)
#define SDC_FIFO_CFG_RDVALIDSELBIT(25)
+/* EMMC_TOP_CONTROL mask */
+#define PAD_RXDLY_SEL BIT(0)
+#define DELAY_EN BIT(1)
+#define PAD_DAT_RD_RXDLY2 (0x1f << 2)
+#define PAD_DAT_RD_RXDLY (0x1f << 7)
+#define PAD_DAT_RD_RXDLY_S 7
+#define PAD_DAT_RD_RXDLY2_SEL BIT(12)
+#define PAD_DAT_RD_RXDLY_SEL BIT(13)
+#define DATA_K_VALUE_SEL BIT(14)
+#define SDC_RX_ENH_EN BIT(15)
+
+/* EMMC_TOP_CMD mask */
+#define PAD_CMD_RXDLY2 (0x1f << 0)
+#define PAD_CMD_RXDLY (0x1f << 5)
+#define PAD_CMD_RXDLY_S5
+#define PAD_CMD_RD_RXDLY2_SEL BIT(10)
+#define PAD_CMD_RD_RXDLY_SEL BIT(11)
+#define PAD_CMD_TX_DLY (0x1f << 12)
+
/* SDC_CFG_BUSWIDTH */
#define MSDC_BUS_1BITS 0x0
#define MSDC_BUS_4BITS 0x1
@@ -219,6 +239,21 @@ struct mtk_sd_regs {
u32 sdc_fifo_cfg;
};
+struct msdc_top_regs {
+ u32 emmc_top_control;
+ u32 emmc_top_cmd;
+ u32 emmc50_pad_ctl0;
+ u32 emmc50_pad_ds_tune;
+ u32 emmc50_pad_dat0_tune;
+ u32 emmc50_pad_dat1_tune;
+ u32 emmc50_pad_dat2_tune;
+ u32 emmc50_pad_dat3_tune;
+ u32 emmc50_pad_dat4_tune;
+ u32 emmc50_pad_dat5_tune;
+ u32 emmc50_pad_dat6_tune;
+ u32 emmc50_pad_dat7_tune;
+};
+
struct msdc_compatible {
u8 clk_div_bits;
u8 sclk_cycle_shift;
@@ -249,6 +284,7 @@ struct msdc_tune_para {
struct msdc_host {
struct mtk_sd_regs *base;
+ struct msdc_top_regs *top_base;
struct mmc *mmc;
struct msdc_compatible *dev_comp;
@@ -964,6 +1000,36 @@ static struct msdc_delay_phase get_best_delay(struct
msdc_host *host, u32 delay)
return delay_phase;
}
+static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = >base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = >base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(>top_base->emmc_top_cmd, PAD_CMD_RXDLY,
+ value << PAD_CMD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ value << MSDC_PAD_TUNE_CMDRDLY_S);
+}
+
+static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = >base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = >base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(>top_base->emmc_top_control,
+ PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ value << MSDC_PAD_TUNE_DATRRDLY_S);
+}
+
static int hs400_tune_response(struct udevice *dev, u32 opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
@@ -1010,7 +1076,7 @@ static int hs400_tune_response(struct udevice *dev, u32
opcode)
PAD_CMD_TUNE_RX_DLY3_S);
final_delay = final_cmd_delay.final_phase;
- dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+ dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
@@ -1217,21 +1283,14 @@ static int msdc_tune_together(struct udevice *dev, u32
opcode)
u32 rise_delay = 0, fall_delay = 0;
struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
u8 final_delay, final_maxlen;
- void __iomem *tune_reg = >base->pad_tune;
int i, ret;
- if (host->dev_comp->pad_tune0)
- tune_reg = >base->pad_tune0;
-
clrbits_le32(>base->msdc_iocon, MSDC_IOCON_DSPL);
clrbits_le32(>base->msdc_iocon, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- i << MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE
[PATCH v2 1/8] ARM: MediaTek: Add support for MediaTek MT8512 SoC
Add support for MediaTek MT8512 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee
---
Changes for v2:
-Sort device nodes reg address order and alphabetically.
---
arch/arm/dts/mt8512.dtsi | 115 ++
arch/arm/mach-mediatek/Kconfig| 15 +++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8512/Makefile| 4 +
arch/arm/mach-mediatek/mt8512/init.c | 78
arch/arm/mach-mediatek/mt8512/lowlevel_init.S | 32 +
6 files changed, 245 insertions(+)
create mode 100644 arch/arm/dts/mt8512.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8512/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8512/init.c
create mode 100644 arch/arm/mach-mediatek/mt8512/lowlevel_init.S
diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi
new file mode 100644
index 00..01a02a7ebf
--- /dev/null
+++ b/arch/arm/dts/mt8512.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8512";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ gic: interrupt-controller@c00 {
+compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ reg = <0xc00 0x4>, /* GICD */
+ <0xc08 0x20>; /* GICR */
+ interrupts = ;
+ };
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt8512-topckgen";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: clock-controller-cg@1000 {
+ compatible = "mediatek,mt8512-topckgen-cg";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: clock-controller@10001000 {
+ compatible = "mediatek,mt8512-infracfg";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8512-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ watchdog0: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = ;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+ timer0: apxgpt@10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_SYS_26M_D2>,
+< CLK_TOP_CLK32K>,
+< CLK_INFRA_APXGPT>;
+ clock-names = "clk13m",
+"clk32k",
+"bus";
+ };
+
+ apmixedsys: clock-controller@1000c000 {
+ compatible = "mediatek,mt8512-apmixedsys";
+ reg = <0x1000c000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_CLK26M>,
+ < CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ mmc0: mmc@1123 {
+ compatible = "mediatek,mt8512-mmc";
+ reg = <0x1123 0x1000>,
+ <0x11cd 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_MSDC50_0_SEL>,
+< CLK_INFRA_MSDC0>,
+< CLK_INFRA_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "dis
[PATCH v2 4/8] clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
---
drivers/clk/mediatek/clk-mtk.c | 25 +
drivers/clk/mediatek/clk-mtk.h | 3 +++
2 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 450de981e9..334559161e 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -95,11 +95,13 @@ static unsigned long __mtk_pll_recalc_rate(const struct
mtk_pll_data *pll,
{
int pcwbits = pll->pcwbits;
int pcwfbits;
+ int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
- pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
vco = (u64)fin * pcw;
@@ -124,7 +126,7 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw,
int postdiv)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = >tree->plls[clk->id];
- u32 val;
+ u32 val, chg;
/* set postdiv */
val = readl(priv->base + pll->pd_reg);
@@ -140,11 +142,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32
pcw, int postdiv)
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
- val &= ~CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
- val |= CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
+ if (pll->pcw_chg_reg) {
+ chg = readl(priv->base + pll->pcw_chg_reg);
+ chg |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ writel(chg, priv->base + pll->pcw_chg_reg);
+ } else {
+ val |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ }
udelay(20);
}
@@ -161,8 +168,9 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw,
u32 *postdiv,
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = >tree->plls[clk->id];
- unsigned long fmin = 1000 * MHZ;
+ unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
u64 _pcw;
+ int ibits;
u32 val;
if (freq > pll->fmax)
@@ -175,7 +183,8 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw,
u32 *postdiv,
}
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
- _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
do_div(_pcw, priv->tree->xtal2_rate);
*pcw = (u32)_pcw;
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 7ea0042500..c7dc980861 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -37,9 +37,12 @@ struct mtk_pll_data {
u32 flags;
u32 rst_bar_mask;
u64 fmax;
+ u64 fmin;
int pcwbits;
+ int pcwibits;
u32 pcw_reg;
int pcw_shift;
+ u32 pcw_chg_reg;
};
/**
--
2.24.1
Re: [PATCH 2/7] clk: mediatek: adjust common driver for mt8512
On Tue, 2019-12-24 at 03:50 +0800, Ryder Lee wrote:
> On Mon, 2019-12-23 at 17:28 +0800, mingming lee wrote:
> > Update mtk common clock driver to support mt8512
> > 1. add new set_clr_upd mux type and related operation
> > 2. add configurable pcw_chg_reg/ibits/fmin to mtk_pll
> > 3. fix mtk_clk_find_parent_rate data overflow.
>
> I think these should be split into different patches. Also, Sam has sent a
> fixup for overflow problem
>
> > Signed-off-by: mingming lee
> > ---
> > drivers/clk/mediatek/clk-mtk.c | 72 --
> > drivers/clk/mediatek/clk-mtk.h | 26
> > 2 files changed, 77 insertions(+), 21 deletions(-)
>
> > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> > index 6c6b500d9b..5a2b77e4ae 100644
> > --- a/drivers/clk/mediatek/clk-mtk.c
> > +++ b/drivers/clk/mediatek/clk-mtk.c
> > @@ -39,8 +39,8 @@
> > * this function is recursively called to find the parent to calculate
> > * the accurate frequency.
> > */
> > -static int mtk_clk_find_parent_rate(struct clk *clk, int id,
> > - const struct driver *drv)
> > +static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
> > + const struct driver *drv)
> > {
> > struct clk parent = { .id = id, };
> >
> > @@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base,
> > u32 parent,
> > if (++index == mux->num_parents)
> > return -EINVAL;
> >
> > - /* switch mux to a select parent */
> > - val = readl(base + mux->mux_reg);
> > - val &= ~(mux->mux_mask << mux->mux_shift);
> > + if (mux->flags & CLK_MUX_SETCLR_UPD) {
> > + val = (mux->mux_mask << mux->mux_shift);
> > + writel(val, base + mux->mux_clr_reg);
> >
> > - val |= index << mux->mux_shift;
> > - writel(val, base + mux->mux_reg);
> > + val = (index << mux->mux_shift);
> > + writel(val, base + mux->mux_set_reg);
> > +
> > + if (mux->upd_shift >= 0)
> > + writel(BIT(mux->upd_shift), base + mux->upd_reg);
> > + } else {
> > + /* switch mux to a select parent */
> > + val = readl(base + mux->mux_reg);
> > + val &= ~(mux->mux_mask << mux->mux_shift);
> > +
> > + val |= index << mux->mux_shift;
> > + writel(val, base + mux->mux_reg);
> > + }
> >
> > return 0;
> > }
> > @@ -84,11 +95,13 @@ static unsigned long __mtk_pll_recalc_rate(const struct
> > mtk_pll_data *pll,
> > {
> > int pcwbits = pll->pcwbits;
> > int pcwfbits;
> > + int ibits;
> > u64 vco;
> > u8 c = 0;
> >
> > /* The fractional part of the PLL divider. */
> > - pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
> > + ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
> > + pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
> >
> > vco = (u64)fin * pcw;
> >
> > @@ -113,7 +126,7 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32
> > pcw, int postdiv)
> > {
> > struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
> > const struct mtk_pll_data *pll = >tree->plls[clk->id];
> > - u32 val;
> > + u32 val, chg;
> >
> > /* set postdiv */
> > val = readl(priv->base + pll->pd_reg);
> > @@ -129,11 +142,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk,
> > u32 pcw, int postdiv)
> > /* set pcw */
> > val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
> > val |= pcw << pll->pcw_shift;
> > - val &= ~CON1_PCW_CHG;
> > - writel(val, priv->base + pll->pcw_reg);
> >
> > - val |= CON1_PCW_CHG;
> > - writel(val, priv->base + pll->pcw_reg);
> > + if (pll->pcw_chg_reg) {
> > + chg = readl(priv->base + pll->pcw_chg_reg);
> > + chg |= CON1_PCW_CHG;
> > + writel(val, priv->base + pll->pcw_reg);
> > + writel(chg, priv->base + pll->pcw_chg_reg);
> > + } else {
> > + val |= CON1_PCW_CHG;
> > + writel(val, priv->base + pll->pcw_reg);
> > + }
> >
> > udelay(20);
> > }
> > @@ -150,8 +168,9 @@ stati
[PATCH 3/7] clk: mediatek: add driver support for MT8512
Add clock driver for MediaTek MT8512 SoC, include topckgen,
apmixedsys and infracfg support.
Signed-off-by: mingming lee
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8512.c | 873 +
include/dt-bindings/clock/mt8512-clk.h | 197 ++
3 files changed, 1071 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8512.c
create mode 100644 include/dt-bindings/clock/mt8512-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e92bcd4efe..b82243885c 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -3,6 +3,7 @@
obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
+obj-$(CONFIG_MT8512) += clk-mt8512.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
diff --git a/drivers/clk/mediatek/clk-mt8512.c
b/drivers/clk/mediatek/clk-mt8512.c
new file mode 100644
index 00..cb168f146b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -0,0 +1,873 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8512 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT8512_PLL_FMAX(3800UL * MHZ)
+#define MT8512_PLL_FMIN(1500UL * MHZ)
+#define MT8512_CON0_RST_BARBIT(23)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) {\
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT8512_CON0_RST_BAR,\
+ .fmax = MT8512_PLL_FMAX,\
+ .fmin = MT8512_PLL_FMIN,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pcwibits = 8, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ .pcw_chg_reg = _pcw_chg_reg,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x0001,
+ 0, 22, 0x0310, 24, 0x0310, 0, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x0001,
+ HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
+ PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x0001,
+ HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
+ PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x0001,
+ 0, 22, 0x0354, 24, 0x0354, 0, 0),
+ PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x0001,
+ 0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
+ PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x0001,
+ 0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
+ PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x0001,
+ 0, 22, 0x0378, 24, 0x0378, 0, 0),
+ PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x0001,
+ 0, 22, 0x0394, 24, 0x0394, 0, 0),
+ PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x0001,
+ 0, 22, 0x03A4, 24, 0x03A4, 0, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 2600),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
+ FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+ FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAIN
[PATCH 4/7] pinctrl: mediatek: add driver for MT8512
Add Pinctrl driver for MediaTek MT8512 SoC.
Signed-off-by: mingming lee
---
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8512.c | 387 ++
3 files changed, 392 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8512.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 22ee62362b..9c6b580fde 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -12,6 +12,10 @@ config PINCTRL_MT7629
bool "MT7629 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8512
+ bool "MT8512 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index 0ab7b1595b..ba955575cf 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -5,5 +5,6 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
+obj-$(CONFIG_PINCTRL_MT8512) += pinctrl-mt8512.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8512.c
b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
new file mode 100644
index 00..af43754a4d
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8512.c
@@ -0,0 +1,387 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, false)
+#define PIN_FIELDS(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, true)
+#define PIN_FIELD30(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits)
\
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 30, false)
+
+static const struct mtk_pin_field_calc mt8512_pin_mode_range[] = {
+ PIN_FIELD30(0, 115, 0x1E0, 0x10, 0, 3),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_dir_range[] = {
+ PIN_FIELD(0, 115, 0x140, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_di_range[] = {
+ PIN_FIELD(0, 115, 0x000, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_do_range[] = {
+ PIN_FIELD(0, 115, 0x860, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullen_range[] = {
+ PIN_FIELD(0, 115, 0x900, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_pullsel_range[] = {
+ PIN_FIELD(0, 115, 0x0A0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8512_pin_ies_range[] = {
+ PIN_FIELDS(0, 2, 0x410, 0x10, 0, 1),
+ PIN_FIELDS(3, 5, 0x410, 0x10, 1, 1),
+ PIN_FIELDS(6, 7, 0x410, 0x10, 2, 1),
+ PIN_FIELDS(8, 11, 0x410, 0x10, 3, 1),
+ PIN_FIELDS(12, 15, 0x410, 0x10, 4, 1),
+ PIN_FIELDS(16, 19, 0x410, 0x10, 5, 1),
+ PIN_FIELD(20, 20, 0x410, 0x10, 6, 1),
+ PIN_FIELDS(21, 25, 0x410, 0x10, 7, 1),
+ PIN_FIELDS(26, 27, 0x410, 0x10, 8, 1),
+ PIN_FIELDS(28, 31, 0x410, 0x10, 9, 1),
+ PIN_FIELD(32, 32, 0x410, 0x10, 10, 1),
+ PIN_FIELDS(33, 39, 0x410, 0x10, 11, 1),
+ PIN_FIELD(40, 40, 0x410, 0x10, 12, 1),
+ PIN_FIELDS(41, 43, 0x410, 0x10, 13, 1),
+ PIN_FIELDS(44, 47, 0x410, 0x10, 14, 1),
+ PIN_FIELDS(48, 51, 0x410, 0x10, 15, 1),
+ PIN_FIELDS(52, 53, 0x410, 0x10, 16, 1),
+ PIN_FIELDS(54, 57, 0x410, 0x10, 17, 1),
+ PIN_FIELDS(58, 63, 0x410, 0x10, 18, 1),
+ PIN_FIELDS(64, 65, 0x410, 0x10, 19, 1),
+ PIN_FIELDS(66, 67, 0x410, 0x10, 20, 1),
+ PIN_FIELDS(68, 69, 0x410, 0x10, 21, 1),
+ PIN_FIELD(70, 70, 0x410, 0x10, 22, 1),
+ PIN_FIELD(71, 71, 0x410, 0x10, 23, 1),
+ PIN_FIELD(72, 72, 0x410, 0x10, 24, 1),
+ PIN_FIELD(73, 73, 0x410, 0x10, 25, 1),
+ PIN_FIELD(74, 74, 0x410, 0x10, 26, 1),
+ PIN_FIELD(75, 75, 0x410, 0x10, 27, 1),
+ PIN_FIELD(76, 76, 0x410, 0x10, 28, 1),
+ PIN_FIELD(77, 77, 0x410, 0x10, 29, 1),
+ PIN_FIELD(78, 78, 0x410, 0x10, 30, 1),
+ PIN_FIELD(79, 79, 0x410, 0x10, 31, 1),
+ PIN_FIELD(80, 80, 0x420, 0x10, 0, 1),
+ PIN_FIELD(81, 81, 0x420, 0x10, 1, 1),
+ PIN_FIELD(82, 82, 0x420, 0x10, 2, 1),
+ PIN_FIELD(83, 83, 0x420, 0x10, 3, 1),
+ PIN_FIELD(84, 84, 0x420, 0x10, 4, 1),
+ PIN_FIELDS(85, 86, 0x420, 0x10, 5, 1),
+ PIN_FIELD(87, 87, 0x420, 0x10,
[PATCH 7/7] ARM: MediaTek: add basic support for MT8512 boards
This adds a general board file based on MT8512 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8512 eMMC board.
Signed-off-by: mingming lee
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8512-bm1-emmc.dts | 106 ++
board/mediatek/mt8512/Kconfig | 14
board/mediatek/mt8512/MAINTAINERS | 6 ++
board/mediatek/mt8512/Makefile| 3 +
board/mediatek/mt8512/mt8512.c| 19 ++
configs/mt8512_bm1_emmc_defconfig | 44 +
include/configs/mt8512.h | 60 +
8 files changed, 253 insertions(+)
create mode 100644 arch/arm/dts/mt8512-bm1-emmc.dts
create mode 100644 board/mediatek/mt8512/Kconfig
create mode 100644 board/mediatek/mt8512/MAINTAINERS
create mode 100644 board/mediatek/mt8512/Makefile
create mode 100644 board/mediatek/mt8512/mt8512.c
create mode 100644 configs/mt8512_bm1_emmc_defconfig
create mode 100644 include/configs/mt8512.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c..57cae40d83 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -835,6 +835,7 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
+ mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8512-bm1-emmc.dts b/arch/arm/dts/mt8512-bm1-emmc.dts
new file mode 100644
index 00..296ed93b9e
--- /dev/null
+++ b/arch/arm/dts/mt8512-bm1-emmc.dts
@@ -0,0 +1,106 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8512.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8512 BM1 EMMC";
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x2000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ bus-width = <8>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ drive-strength = <6>;
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/board/mediatek/mt8512/Kconfig b/board/mediatek/mt8512/Kconfig
new file mode 100644
index 00..87bd1fbe69
--- /dev/null
+++ b/board/mediatek/mt8512/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_MT8
[PATCH 1/7] ARM: MediaTek: Add support for MediaTek MT8512 SoC
Add support for MediaTek MT8512 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8512.dtsi | 115 ++
arch/arm/mach-mediatek/Kconfig| 15 +++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8512/Makefile| 4 +
arch/arm/mach-mediatek/mt8512/init.c | 78
arch/arm/mach-mediatek/mt8512/lowlevel_init.S | 32 +
6 files changed, 245 insertions(+)
create mode 100644 arch/arm/dts/mt8512.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8512/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8512/init.c
create mode 100644 arch/arm/mach-mediatek/mt8512/lowlevel_init.S
diff --git a/arch/arm/dts/mt8512.dtsi b/arch/arm/dts/mt8512.dtsi
new file mode 100644
index 00..543f068cb8
--- /dev/null
+++ b/arch/arm/dts/mt8512.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8512";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt8512-topckgen";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: clock-controller-cg@1000 {
+ compatible = "mediatek,mt8512-topckgen-cg";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: clock-controller@10001000 {
+ compatible = "mediatek,mt8512-infracfg";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@0c00 {
+compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ reg = <0xc00 0x4>, /* GICD */
+ <0xc08 0x20>; /* GICR */
+ interrupts = ;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ timer0: apxgpt@10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_SYS_26M_D2>,
+< CLK_TOP_CLK32K>,
+< CLK_INFRA_APXGPT>;
+ clock-names = "clk13m",
+"clk32k",
+"bus";
+ };
+
+ watchdog0: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = ;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8512-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ apmixedsys: clock-controller@1000c000 {
+ compatible = "mediatek,mt8512-apmixedsys";
+ reg = <0x1000c000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mmc0: mmc@1123 {
+ compatible = "mediatek,mt8512-mmc";
+ reg = <0x1123 0x1000>,
+ <0x11cd 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_MSDC50_0_SEL>,
+< CLK_INFRA_MSDC0>,
+< CLK_INFRA_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ uart0: serial@11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_CLK26M>,
+ < CLK_INFRA_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/a
[PATCH 2/7] clk: mediatek: adjust common driver for mt8512
Update mtk common clock driver to support mt8512
1. add new set_clr_upd mux type and related operation
2. add configurable pcw_chg_reg/ibits/fmin to mtk_pll
3. fix mtk_clk_find_parent_rate data overflow
Signed-off-by: mingming lee
---
drivers/clk/mediatek/clk-mtk.c | 72 --
drivers/clk/mediatek/clk-mtk.h | 26
2 files changed, 77 insertions(+), 21 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 6c6b500d9b..5a2b77e4ae 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -39,8 +39,8 @@
* this function is recursively called to find the parent to calculate
* the accurate frequency.
*/
-static int mtk_clk_find_parent_rate(struct clk *clk, int id,
- const struct driver *drv)
+static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
+ const struct driver *drv)
{
struct clk parent = { .id = id, };
@@ -67,12 +67,23 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32
parent,
if (++index == mux->num_parents)
return -EINVAL;
- /* switch mux to a select parent */
- val = readl(base + mux->mux_reg);
- val &= ~(mux->mux_mask << mux->mux_shift);
+ if (mux->flags & CLK_MUX_SETCLR_UPD) {
+ val = (mux->mux_mask << mux->mux_shift);
+ writel(val, base + mux->mux_clr_reg);
- val |= index << mux->mux_shift;
- writel(val, base + mux->mux_reg);
+ val = (index << mux->mux_shift);
+ writel(val, base + mux->mux_set_reg);
+
+ if (mux->upd_shift >= 0)
+ writel(BIT(mux->upd_shift), base + mux->upd_reg);
+ } else {
+ /* switch mux to a select parent */
+ val = readl(base + mux->mux_reg);
+ val &= ~(mux->mux_mask << mux->mux_shift);
+
+ val |= index << mux->mux_shift;
+ writel(val, base + mux->mux_reg);
+ }
return 0;
}
@@ -84,11 +95,13 @@ static unsigned long __mtk_pll_recalc_rate(const struct
mtk_pll_data *pll,
{
int pcwbits = pll->pcwbits;
int pcwfbits;
+ int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
- pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
vco = (u64)fin * pcw;
@@ -113,7 +126,7 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw,
int postdiv)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = >tree->plls[clk->id];
- u32 val;
+ u32 val, chg;
/* set postdiv */
val = readl(priv->base + pll->pd_reg);
@@ -129,11 +142,16 @@ static void mtk_pll_set_rate_regs(struct clk *clk, u32
pcw, int postdiv)
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
- val &= ~CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
- val |= CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
+ if (pll->pcw_chg_reg) {
+ chg = readl(priv->base + pll->pcw_chg_reg);
+ chg |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ writel(chg, priv->base + pll->pcw_chg_reg);
+ } else {
+ val |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ }
udelay(20);
}
@@ -150,8 +168,9 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw,
u32 *postdiv,
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = >tree->plls[clk->id];
- unsigned long fmin = 1000 * MHZ;
+ unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
u64 _pcw;
+ int ibits;
u32 val;
if (freq > pll->fmax)
@@ -164,7 +183,8 @@ static void mtk_pll_calc_values(struct clk *clk, u32 *pcw,
u32 *postdiv,
}
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
- _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
do_div(_pcw, priv->tree->xtal2_rate);
*pcw = (u32)_pcw;
@@ -332,9 +352,14 @@ static int mtk_topckgen_enable(struct clk *clk)
return 0;
/* enable clock gate */
- val = readl(priv-&
[PATCH 6/7] mmc: mtk-sd: fix hang when data read quickly
For CMD21 tuning data, the 128/64 bytes data may coming in very short time, before msdc_start_data(), the read data has already come, in this case, clear MSDC_INT will cause the interrupt disappear and lead to the thread hang. the solution is just clear all interrupts before command was sent. Signed-off-by: mingming lee --- drivers/mmc/mtk-sd.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 23413731dc..b0365877d7 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -531,6 +530,7 @@ static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd, blocks = data->blocks; writel(CMD_INTS_MASK, >base->msdc_int); + writel(DATA_INTS_MASK, >base->msdc_int); writel(blocks, >base->sdc_blk_num); writel(cmd->cmdarg, >base->sdc_arg); writel(rawcmd, >base->sdc_cmd); @@ -677,13 +677,9 @@ static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) u32 size; int ret; - WATCHDOG_RESET(); - if (data->flags == MMC_DATA_WRITE) host->last_data_write = 1; - writel(DATA_INTS_MASK, >base->msdc_int); - size = data->blocks * data->blocksize; if (data->flags == MMC_DATA_WRITE) -- 2.18.0
[PATCH 5/7] mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs
This patch adds mmc support for MediaTek MT8512/MT8110 SoCs.
MT8512/MT8110 SoCs puts the tune register at top layer, so
need add new code to support it.
Signed-off-by: mingming lee
---
drivers/mmc/mtk-sd.c | 134 ---
1 file changed, 101 insertions(+), 33 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index eaa584a4df..23413731dc 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -135,6 +136,25 @@
#define SDC_FIFO_CFG_WRVALIDSELBIT(24)
#define SDC_FIFO_CFG_RDVALIDSELBIT(25)
+/* EMMC_TOP_CONTROL mask */
+#define PAD_RXDLY_SEL BIT(0)
+#define DELAY_EN BIT(1)
+#define PAD_DAT_RD_RXDLY2 (0x1f << 2)
+#define PAD_DAT_RD_RXDLY (0x1f << 7)
+#define PAD_DAT_RD_RXDLY_S 7
+#define PAD_DAT_RD_RXDLY2_SEL BIT(12)
+#define PAD_DAT_RD_RXDLY_SEL BIT(13)
+#define DATA_K_VALUE_SEL BIT(14)
+#define SDC_RX_ENH_EN BIT(15)
+
+/* EMMC_TOP_CMD mask */
+#define PAD_CMD_RXDLY2 (0x1f << 0)
+#define PAD_CMD_RXDLY (0x1f << 5)
+#define PAD_CMD_RXDLY_S5
+#define PAD_CMD_RD_RXDLY2_SEL BIT(10)
+#define PAD_CMD_RD_RXDLY_SEL BIT(11)
+#define PAD_CMD_TX_DLY (0x1f << 12)
+
/* SDC_CFG_BUSWIDTH */
#define MSDC_BUS_1BITS 0x0
#define MSDC_BUS_4BITS 0x1
@@ -219,6 +239,21 @@ struct mtk_sd_regs {
u32 sdc_fifo_cfg;
};
+struct msdc_top_regs {
+ u32 emmc_top_control;
+ u32 emmc_top_cmd;
+ u32 emmc50_pad_ctl0;
+ u32 emmc50_pad_ds_tune;
+ u32 emmc50_pad_dat0_tune;
+ u32 emmc50_pad_dat1_tune;
+ u32 emmc50_pad_dat2_tune;
+ u32 emmc50_pad_dat3_tune;
+ u32 emmc50_pad_dat4_tune;
+ u32 emmc50_pad_dat5_tune;
+ u32 emmc50_pad_dat6_tune;
+ u32 emmc50_pad_dat7_tune;
+};
+
struct msdc_compatible {
u8 clk_div_bits;
u8 sclk_cycle_shift;
@@ -249,6 +284,7 @@ struct msdc_tune_para {
struct msdc_host {
struct mtk_sd_regs *base;
+ struct msdc_top_regs *top_base;
struct mmc *mmc;
struct msdc_compatible *dev_comp;
@@ -964,6 +1000,36 @@ static struct msdc_delay_phase get_best_delay(struct
msdc_host *host, u32 delay)
return delay_phase;
}
+static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = >base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = >base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(>top_base->emmc_top_cmd, PAD_CMD_RXDLY,
+ value << PAD_CMD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
+ value << MSDC_PAD_TUNE_CMDRDLY_S);
+}
+
+static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
+{
+ void __iomem *tune_reg = >base->pad_tune;
+
+ if (host->dev_comp->pad_tune0)
+ tune_reg = >base->pad_tune0;
+
+ if (host->top_base)
+ clrsetbits_le32(>top_base->emmc_top_control,
+ PAD_DAT_RD_RXDLY, value << PAD_DAT_RD_RXDLY_S);
+ else
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
+ value << MSDC_PAD_TUNE_DATRRDLY_S);
+}
+
static int hs400_tune_response(struct udevice *dev, u32 opcode)
{
struct msdc_plat *plat = dev_get_platdata(dev);
@@ -1010,7 +1076,7 @@ static int hs400_tune_response(struct udevice *dev, u32
opcode)
PAD_CMD_TUNE_RX_DLY3_S);
final_delay = final_cmd_delay.final_phase;
- dev_err(dev, "Final cmd pad delay: %x\n", final_delay);
+ dev_info(dev, "Final cmd pad delay: %x\n", final_delay);
return final_delay == 0xff ? -EIO : 0;
}
@@ -1217,21 +1283,14 @@ static int msdc_tune_together(struct udevice *dev, u32
opcode)
u32 rise_delay = 0, fall_delay = 0;
struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
u8 final_delay, final_maxlen;
- void __iomem *tune_reg = >base->pad_tune;
int i, ret;
- if (host->dev_comp->pad_tune0)
- tune_reg = >base->pad_tune0;
-
clrbits_le32(>base->msdc_iocon, MSDC_IOCON_DSPL);
clrbits_le32(>base->msdc_iocon, MSDC_IOCON_W_DSPL);
for (i = 0; i < PAD_DELAY_MAX; i++) {
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M,
- i << MSDC_PAD_TUNE_CMDRDLY_S);
- clrsetbits_le32(tune_reg, MSDC_PAD_TUNE
[PATCH 0/7] Add support for MediaTek MT8512 Soc
This patch series adds basic boot support on eMMC for the MediaTek MT8512 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. mingming lee (7): ARM: MediaTek: Add support for MediaTek MT8512 SoC clk: mediatek: adjust common driver for mt8512 clk: mediatek: add driver support for MT8512 pinctrl: mediatek: add driver for MT8512 mmc: mtk-sd: add support for MediaTek MT8512/MT8110 SoCs mmc: mtk-sd: fix hang when data read quickly ARM: MediaTek: add basic support for MT8512 boards arch/arm/dts/Makefile | 1 + arch/arm/dts/mt8512-bm1-emmc.dts | 106 +++ arch/arm/dts/mt8512.dtsi | 115 +++ arch/arm/mach-mediatek/Kconfig| 15 + arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8512/Makefile| 4 + arch/arm/mach-mediatek/mt8512/init.c | 78 ++ arch/arm/mach-mediatek/mt8512/lowlevel_init.S | 32 + board/mediatek/mt8512/Kconfig | 14 + board/mediatek/mt8512/MAINTAINERS | 6 + board/mediatek/mt8512/Makefile| 3 + board/mediatek/mt8512/mt8512.c| 19 + configs/mt8512_bm1_emmc_defconfig | 44 + drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8512.c | 873 ++ drivers/clk/mediatek/clk-mtk.c| 72 +- drivers/clk/mediatek/clk-mtk.h| 26 + drivers/mmc/mtk-sd.c | 140 ++- drivers/pinctrl/mediatek/Kconfig | 4 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8512.c | 387 include/configs/mt8512.h | 60 ++ include/dt-bindings/clock/mt8512-clk.h| 197 23 files changed, 2140 insertions(+), 59 deletions(-) create mode 100644 arch/arm/dts/mt8512-bm1-emmc.dts create mode 100644 arch/arm/dts/mt8512.dtsi create mode 100644 arch/arm/mach-mediatek/mt8512/Makefile create mode 100644 arch/arm/mach-mediatek/mt8512/init.c create mode 100644 arch/arm/mach-mediatek/mt8512/lowlevel_init.S create mode 100644 board/mediatek/mt8512/Kconfig create mode 100644 board/mediatek/mt8512/MAINTAINERS create mode 100644 board/mediatek/mt8512/Makefile create mode 100644 board/mediatek/mt8512/mt8512.c create mode 100644 configs/mt8512_bm1_emmc_defconfig create mode 100644 drivers/clk/mediatek/clk-mt8512.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8512.c create mode 100644 include/configs/mt8512.h create mode 100644 include/dt-bindings/clock/mt8512-clk.h -- 2.18.0
[U-Boot] [PATCH v3 2/5] clk: mediatek: add driver for MT8518
Add clock driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
Changes for v3:
-fix top clock register definition which cause unused warning.
---
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-mt8518.c | 1558
include/dt-bindings/clock/mt8518-clk.h | 249
3 files changed, 1808 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8518.c
create mode 100644 include/dt-bindings/clock/mt8518-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a47a5bdbc2..e92bcd4efe 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8518.c
b/drivers/clk/mediatek/clk-mt8518.c
new file mode 100644
index 00..76f7b3b361
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8518 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT8518_PLL_FMAX(3000UL * MHZ)
+#define MT8518_CON0_RST_BARBIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT8518_CON0_RST_BAR,\
+ .fmax = MT8518_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x0001,
+ 0, 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x0001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x3001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x0001,
+ 0, 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x0001,
+ 0, 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x0001,
+ 0, 31, 0x01A0, 1, 0x01A4, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x0001,
+ 0, 21, 0x01C4, 24, 0x01C4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 2600),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 5),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 5),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+
[U-Boot] [PATCH v3 5/5] ARM: MediaTek: add basic support for MT8518 boards
This adds a general board file based on MT8518 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8518 eMMC board.
Signed-off-by: mingming lee
---
Changes for v3:
- change hs400 to hs200 since the dts is hs200
- disable ENV in emmc
Changes for v2:
- print debug log using debug() api
- delete unnecessary configs and code
- change emmc hs200 to hs400 to speed up boot time
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/mt8518-ap1-emmc.dts | 104 +
arch/arm/mach-mediatek/Kconfig | 1 +
board/mediatek/mt8518/Kconfig | 14
board/mediatek/mt8518/MAINTAINERS | 6 ++
board/mediatek/mt8518/Makefile | 3 +
board/mediatek/mt8518/mt8518_ap1.c | 18 +
configs/mt8518_ap1_emmc_defconfig | 41
include/configs/mt8518.h | 68 +++
9 files changed, 257 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts
create mode 100644 board/mediatek/mt8518/Kconfig
create mode 100644 board/mediatek/mt8518/MAINTAINERS
create mode 100644 board/mediatek/mt8518/Makefile
create mode 100644 board/mediatek/mt8518/mt8518_ap1.c
create mode 100644 configs/mt8518_ap1_emmc_defconfig
create mode 100644 include/configs/mt8518.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 251d32ca62..7071a7c1b9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -825,7 +825,8 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
- mt8516-pumpkin.dtb
+ mt8516-pumpkin.dtb \
+ mt8518-ap1-emmc.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
diff --git a/arch/arm/dts/mt8518-ap1-emmc.dts b/arch/arm/dts/mt8518-ap1-emmc.dts
new file mode 100644
index 00..f017ee4431
--- /dev/null
+++ b/arch/arm/dts/mt8518-ap1-emmc.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8518.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8518 AP1 EMMC";
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x1000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ bus-width = <8>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_p
[U-Boot] [PATCH v3 0/5] Add support for MediaTek MT8518 Soc
This patch series adds basic boot support on eMMC for the MediaTek MT8518 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. --- Changes for v3: - Fix top clock register definition which cause unused warning. - Change hs400 to hs200 since the dts is hs200 - Fixed all build warnings using gcc version 740 Changes for v2: - Fixed issues in v1: drop unused 'devices',delete no need code and print debug log using debug() - Delete unnecessary configs in defconfig - Adjust the mmc tuning flow to support HS400 mingming lee (5): ARM: MediaTek: Add support for MediaTek MT8518 SoC clk: mediatek: add driver for MT8518 mmc: mtk-sd: Adjust the mmc tuning flow pinctrl: add driver for MT8518 ARM: MediaTek: add basic support for MT8518 boards arch/arm/dts/Makefile |3 +- arch/arm/dts/mt8518-ap1-emmc.dts | 104 ++ arch/arm/dts/mt8518.dtsi | 98 ++ arch/arm/mach-mediatek/Kconfig| 10 + arch/arm/mach-mediatek/Makefile |1 + arch/arm/mach-mediatek/mt8518/Makefile|4 + arch/arm/mach-mediatek/mt8518/init.c | 71 + arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 32 + board/mediatek/mt8518/Kconfig | 14 + board/mediatek/mt8518/MAINTAINERS |6 + board/mediatek/mt8518/Makefile|3 + board/mediatek/mt8518/mt8518_ap1.c| 18 + configs/mt8518_ap1_emmc_defconfig | 41 + drivers/clk/mediatek/Makefile |1 + drivers/clk/mediatek/clk-mt8518.c | 1558 + drivers/mmc/mtk-sd.c | 209 ++- drivers/pinctrl/mediatek/Kconfig |4 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 + include/configs/mt8518.h | 68 + include/dt-bindings/clock/mt8518-clk.h| 249 +++ 21 files changed, 2889 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts create mode 100644 arch/arm/dts/mt8518.dtsi create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile create mode 100644 arch/arm/mach-mediatek/mt8518/init.c create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S create mode 100644 board/mediatek/mt8518/Kconfig create mode 100644 board/mediatek/mt8518/MAINTAINERS create mode 100644 board/mediatek/mt8518/Makefile create mode 100644 board/mediatek/mt8518/mt8518_ap1.c create mode 100644 configs/mt8518_ap1_emmc_defconfig create mode 100644 drivers/clk/mediatek/clk-mt8518.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c create mode 100644 include/configs/mt8518.h create mode 100644 include/dt-bindings/clock/mt8518-clk.h -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee
---
Changes for v3:
-drop unused api to keep it simple
Changes for v2:
-drop unused 'device' in dtsi to keep it simple
---
arch/arm/dts/mt8518.dtsi | 91 +++
arch/arm/mach-mediatek/Kconfig| 9 ++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8518/Makefile| 4 +
arch/arm/mach-mediatek/mt8518/init.c | 71 +++
arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 32 +++
6 files changed, 208 insertions(+)
create mode 100644 arch/arm/dts/mt8518.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644
index 00..9f56122319
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8518";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt8518-topckgen";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@0c00 {
+compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ reg = <0xc00 0x4>, /* GICD */
+ <0xc10 0x20>; /* GICR */
+ interrupts = ;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ timer0: apxgpt@10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_CLK26M_D2>,
+< CLK_TOP_CLK32K>,
+< CLK_TOP_APXGPT>;
+ clock-names = "clk13m",
+"clk32k",
+"bus";
+ };
+
+ watchdog0: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = ;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+
+
+ mmc0: mmc@1112 {
+ compatible = "mediatek,mt8516-mmc";
+ reg = <0x1112 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_MSDC0>,
+ < CLK_TOP_MSDC0>,
+ < CLK_TOP_MSDC0_B>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ uart0: serial@11005000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11005000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_UART0_SEL>,
+ < CLK_TOP_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25ef7651f0..8e343c3182 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -38,6 +38,15 @@ config TARGET_MT8516
Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth
combo
chip and several DDR3 and DDR4 options.
+config TARGET_MT8518
+ bool "MediaTek MT8518 SoC"
+ select ARM64
+ help
+ The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+ Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth
combo
+ chip and several DDR3 and DDR4 options.
+
endchoice
source "board/mediatek/mt7623/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index ea414dc407..b9b2355e03 100644
--- a/arch/arm/mach-m
[U-Boot] [PATCH v3 4/5] pinctrl: add driver for MT8518
Add Pinctrl driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 9 +-
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 ++
4 files changed, 424 insertions(+), 1 deletion(-)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
index 9f56122319..c2d17fda4a 100644
--- a/arch/arm/dts/mt8518.dtsi
+++ b/arch/arm/dts/mt8518.dtsi
@@ -65,7 +65,14 @@
reset-on-timeout;
};
-
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8518-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
mmc0: mmc@1112 {
compatible = "mediatek,mt8516-mmc";
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 9930ca1faf..22ee62362b 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -16,4 +16,8 @@ config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8518
+bool "MT8518 SoC pinctrl driver"
+ select PINCTRL_MTK
+
endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index c4f29088d2..0ab7b1595b 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
+obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
new file mode 100644
index 00..8d2cd948f6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = {
+ PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = {
+ PIN_FIELD(0, 119, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_di_range[] = {
+ PIN_FIELD(0, 119, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_do_range[] = {
+ PIN_FIELD(0, 119, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = {
+ PIN_FIELD(0, 2, 0x900, 0x10, 0, 1),
+ PIN_FIELD(3, 3, 0x920, 0x10, 9, 1),
+ PIN_FIELD(4, 4, 0x920, 0x10, 8, 1),
+ PIN_FIELD(5, 5, 0x920, 0x10, 7, 1),
+ PIN_FIELD(6, 6, 0x920, 0x10, 6, 1),
+ PIN_FIELD(7, 7, 0x920, 0x10, 10, 1),
+ PIN_FIELD(8, 8, 0x920, 0x10, 1, 1),
+ PIN_FIELD(9, 9, 0x920, 0x10, 0, 1),
+ PIN_FIELD(10, 10, 0x920, 0x10, 5, 1),
+ PIN_FIELD(11, 11, 0x920, 0x10, 4, 1),
+ PIN_FIELD(12, 12, 0x920, 0x10, 3, 1),
+ PIN_FIELD(13, 13, 0x920, 0x10, 2, 1),
+ PIN_FIELD(14, 14, 0x900, 0x10, 1, 1),
+ PIN_FIELD(15, 15, 0x900, 0x10, 2, 1),
+ PIN_FIELD(16, 16, 0x900, 0x10, 3, 1),
+ PIN_FIELD(17, 20, 0x900, 0x10, 4, 1),
+ PIN_FIELD(21, 22, 0x900, 0x10, 5, 1),
+ PIN_FIELD(23, 27, 0x910, 0x10, 15, 1),
+ PIN_FIELD(28, 28, 0x900, 0x10, 6, 1),
+ PIN_FIELD(29, 29, 0x930, 0x10, 2, 1),
+ PIN_FIELD(30, 30, 0x930, 0x10, 1, 1),
+ PIN_FIELD(31, 31, 0x930, 0x10, 6, 1),
+ PIN_FIELD(32, 32, 0x930, 0x10, 5, 1),
+ PIN_FIELD(33, 33, 0x930, 0x10, 4, 1),
+ PIN_FIELD(34, 35, 0x930, 0x10, 3, 1),
+ PIN_FIELD(36, 39, 0x900, 0x10, 7, 1),
+ PIN_FIELD(40, 41, 0x900, 0x10, 8, 1),
+ PIN_FIELD(42, 44, 0x900, 0x10, 9, 1),
+ PIN_FIELD(45, 47, 0x900, 0x10, 10, 1),
+ PIN_FIELD(48, 51, 0x900, 0x10, 11, 1),
+ PIN_FIELD(52, 55, 0x900, 0x10, 12, 1),
+ PIN_FIELD(56, 56, 0x900, 0x10, 13, 1),
+ PIN_FIELD(57, 57, 0x900, 0x10, 14, 1),
+ PIN_FIELD(58, 58, 0x900, 0x10, 15, 1),
+ PIN_FIELD(59, 60, 0x910, 0x10, 0, 1),
+
+ PIN_FIELD(61, 61, 0x910, 0x10, 1, 1),
+ PIN_FIELD(62, 62, 0x910, 0x10, 2, 1),
+ PIN_FIELD(63, 69, 0x910, 0x10, 3, 1),
+ PIN_FIELD(70, 70, 0x910, 0x10, 4, 1),
+ PIN_FIELD(71, 76, 0x910, 0x10, 5, 1),
+ PIN_FIELD(77, 80, 0x910, 0x10, 6, 1),
+ PIN_FIELD(81, 87
[U-Boot] [PATCH v3 3/5] mmc: mtk-sd: Adjust the mmc tuning flow
1.Support cmd response and data tuning together.
2.Support hs400 cmd responese tuning.
Signed-off-by: mingming lee
---
Changes for v2:
- add hs400 support
---
drivers/mmc/mtk-sd.c | 209 +++
1 file changed, 193 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index ffd647fac7..eaa584a4df 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -125,6 +125,9 @@
#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
#define MSDC_PAD_TUNE_DATWRDLY_S 0
+#define PAD_CMD_TUNE_RX_DLY3 0x3E
+#define PAD_CMD_TUNE_RX_DLY3_S 1
+
/* EMMC50_CFG0 */
#define EMMC50_CFG_CFCSTS_SEL BIT(4)
@@ -209,7 +212,8 @@ struct mtk_sd_regs {
u32 eco_ver;
u32 reserved6[27];
u32 pad_ds_tune;
- u32 reserved7[31];
+ u32 pad_cmd_tune;
+ u32 reserved7[30];
u32 emmc50_cfg0;
u32 reserved8[7];
u32 sdc_fifo_cfg;
@@ -240,6 +244,7 @@ struct msdc_plat {
struct msdc_tune_para {
u32 iocon;
u32 pad_tune;
+ u32 pad_cmd_tune;
};
struct msdc_host {
@@ -364,6 +369,8 @@ static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
case MMC_CMD_WRITE_SINGLE_BLOCK:
case MMC_CMD_READ_SINGLE_BLOCK:
case SD_CMD_APP_SEND_SCR:
+ case MMC_CMD_SEND_TUNING_BLOCK:
+ case MMC_CMD_SEND_TUNING_BLOCK_HS200:
dtype = 1;
break;
case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
@@ -469,6 +476,14 @@ static int msdc_start_command(struct msdc_host *host,
struct mmc_cmd *cmd,
if (!msdc_cmd_is_ready(host))
return -EIO;
+ if ((readl(>base->msdc_fifocs) &
+ MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
+ (readl(>base->msdc_fifocs) &
+ MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
+ pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
+ msdc_reset_hw(host);
+ }
+
msdc_fifo_clr(host);
host->last_resp_type = cmd->resp_type;
@@ -652,14 +667,22 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct
mmc_cmd *cmd,
struct mmc_data *data)
{
struct msdc_host *host = dev_get_priv(dev);
- int ret;
+ int cmd_ret, data_ret;
- ret = msdc_start_command(host, cmd, data);
- if (ret)
- return ret;
+ cmd_ret = msdc_start_command(host, cmd, data);
+ if (cmd_ret &&
+ !(cmd_ret == -EIO &&
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
+ return cmd_ret;
- if (data)
- return msdc_start_data(host, data);
+ if (data) {
+ data_ret = msdc_start_data(host, data);
+ if (cmd_ret)
+ return cmd_ret;
+ else
+ return data_ret;
+ }
return 0;
}
@@ -941,6 +964,56 @@ static struct msdc_delay_phase get_best_delay(struct
msdc_host *host, u32 delay)
return delay_phase;
}
+static int hs400_tune_response(struct udevice *dev, u32 opcode)
+{
+ struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_host *host = dev_get_priv(dev);
+ struct mmc *mmc = >mmc;
+ u32 cmd_delay = 0;
+ struct msdc_delay_phase final_cmd_delay = { 0, };
+ u8 final_delay;
+ void __iomem *tune_reg = >base->pad_cmd_tune;
+ int cmd_err;
+ int i, j;
+
+ setbits_le32(>base->pad_cmd_tune, BIT(0));
+
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == UHS_SDR104)
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
+ host->hs200_cmd_int_delay <<
+ MSDC_PAD_TUNE_CMDRRDLY_S);
+
+ if (host->r_smpl)
+ clrbits_le32(>base->msdc_iocon, MSDC_IOCON_RSPL);
+ else
+ setbits_le32(>base->msdc_iocon, MSDC_IOCON_RSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ i << PAD_CMD_TUNE_RX_DLY3_S);
+
+ for (j = 0; j < 3; j++) {
+ mmc_send_tuning(mmc, opcode, _err);
+ if (!cmd_err) {
+ cmd_delay |= (1 << i);
+ } else {
+ cmd_delay &= ~(1 << i);
+ break;
+ }
+ }
+ }
+
+ final_cmd_delay = get_best_delay(host, cmd_delay);
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ final_cmd_delay.final_phase <<
+ PAD_CMD_TUNE_RX_DLY3_S);
+
Re: [U-Boot] [PATCH v2 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
On Wed, 2019-10-30 at 23:09 -0400, Tom Rini wrote:
> On Mon, Oct 21, 2019 at 02:59:04PM +0800, mingming lee wrote:
>
> > Add support for MediaTek MT8518 SoC. This include the file
> > that will initialize the SoC after boot and its device tree.
> >
> > Signed-off-by: mingming lee
> > ---
> > Changes for v2:
> >-drop unused 'device' in dtsi to keep it simple
>
> Please fix problems such as:
> +drivers/clk/mediatek/clk-mt8518.c:1294:35: error: 'top7_cg_regs'
> defined but not used [-Werror=unused-const-variable=]
> + static const struct mtk_gate_regs top7_cg_regs = {
> + ^~~~
> +drivers/clk/mediatek/clk-mt8518.c:1288:35: error: 'top6_cg_regs'
> defined but not used [-Werror=unused-const-variable=]
> + static const struct mtk_gate_regs top6_cg_regs = {
> +cc1: all warnings being treated as errors
> +make[4]: *** [drivers/clk/mediatek/clk-mt8518.o] Error 1
> +make[3]: *** [drivers/clk/mediatek] Error 2
> +make[2]: *** [drivers/clk] Error 2
> +make[1]: *** [drivers] Error 2
>
> and ensure everything builds without warning, thanks!
>
Thank you for your review.
Sorry for forgetting build with -Werror flag, and I would check it
again.
___
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[U-Boot] [PATCH v2 2/5] clk: mediatek: add driver for MT8518
Add clock driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-mt8518.c | 1558
include/dt-bindings/clock/mt8518-clk.h | 249
3 files changed, 1808 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8518.c
create mode 100644 include/dt-bindings/clock/mt8518-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a47a5bdbc2..e92bcd4efe 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8518.c
b/drivers/clk/mediatek/clk-mt8518.c
new file mode 100644
index 00..35b3db28e6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8518 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT8518_PLL_FMAX(3000UL * MHZ)
+#define MT8518_CON0_RST_BARBIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT8518_CON0_RST_BAR,\
+ .fmax = MT8518_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x0001,
+ 0, 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x0001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x3001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x0001,
+ 0, 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x0001,
+ 0, 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x0001,
+ 0, 31, 0x01A0, 1, 0x01A4, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x0001,
+ 0, 21, 0x01C4, 24, 0x01C4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 2600),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 5),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 5),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_
[U-Boot] [PATCH v2 5/5] ARM: MediaTek: add basic support for MT8518 boards
This adds a general board file based on MT8518 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8518 eMMC board.
Signed-off-by: mingming lee
---
Changes for v2:
- print debug log using debug() api
- delete unnecessary configs and code
- change emmc hs200 to hs400 to speed up boot time
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/mt8518-ap1-emmc.dts | 104 +
arch/arm/mach-mediatek/Kconfig | 1 +
board/mediatek/mt8518/Kconfig | 14
board/mediatek/mt8518/MAINTAINERS | 6 ++
board/mediatek/mt8518/Makefile | 3 +
board/mediatek/mt8518/mt8518_ap1.c | 18 +
configs/mt8518_ap1_emmc_defconfig | 41
include/configs/mt8518.h | 68 +++
9 files changed, 257 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts
create mode 100644 board/mediatek/mt8518/Kconfig
create mode 100644 board/mediatek/mt8518/MAINTAINERS
create mode 100644 board/mediatek/mt8518/Makefile
create mode 100644 board/mediatek/mt8518/mt8518_ap1.c
create mode 100644 configs/mt8518_ap1_emmc_defconfig
create mode 100644 include/configs/mt8518.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aac1b83d49..54ca31c995 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -788,7 +788,8 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
- mt8516-pumpkin.dtb
+ mt8516-pumpkin.dtb \
+ mt8518-ap1-emmc.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
diff --git a/arch/arm/dts/mt8518-ap1-emmc.dts b/arch/arm/dts/mt8518-ap1-emmc.dts
new file mode 100644
index 00..f017ee4431
--- /dev/null
+++ b/arch/arm/dts/mt8518-ap1-emmc.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8518.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8518 AP1 EMMC";
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x1000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ bus-width = <8>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
[U-Boot] [PATCH v2 3/5] mmc: mtk-sd: Adjust the mmc tuning flow
1.Support cmd response and data tuning together.
2.Support hs400 cmd responese tuning.
Signed-off-by: mingming lee
---
Changes for v2:
- add hs400 support
---
drivers/mmc/mtk-sd.c | 209 +++
1 file changed, 193 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index f555357af2..0b3eeeaa20 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -125,6 +125,9 @@
#define MSDC_PAD_TUNE_DATWRDLY_M 0x1f
#define MSDC_PAD_TUNE_DATWRDLY_S 0
+#define PAD_CMD_TUNE_RX_DLY3 0x3E
+#define PAD_CMD_TUNE_RX_DLY3_S 1
+
/* EMMC50_CFG0 */
#define EMMC50_CFG_CFCSTS_SEL BIT(4)
@@ -209,7 +212,8 @@ struct mtk_sd_regs {
u32 eco_ver;
u32 reserved6[27];
u32 pad_ds_tune;
- u32 reserved7[31];
+ u32 pad_cmd_tune;
+ u32 reserved7[30];
u32 emmc50_cfg0;
u32 reserved8[7];
u32 sdc_fifo_cfg;
@@ -239,6 +243,7 @@ struct msdc_plat {
struct msdc_tune_para {
u32 iocon;
u32 pad_tune;
+ u32 pad_cmd_tune;
};
struct msdc_host {
@@ -362,6 +367,8 @@ static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
case MMC_CMD_WRITE_SINGLE_BLOCK:
case MMC_CMD_READ_SINGLE_BLOCK:
case SD_CMD_APP_SEND_SCR:
+ case MMC_CMD_SEND_TUNING_BLOCK:
+ case MMC_CMD_SEND_TUNING_BLOCK_HS200:
dtype = 1;
break;
case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
@@ -467,6 +474,14 @@ static int msdc_start_command(struct msdc_host *host,
struct mmc_cmd *cmd,
if (!msdc_cmd_is_ready(host))
return -EIO;
+ if ((readl(>base->msdc_fifocs) &
+ MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
+ (readl(>base->msdc_fifocs) &
+ MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
+ pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
+ msdc_reset_hw(host);
+ }
+
msdc_fifo_clr(host);
host->last_resp_type = cmd->resp_type;
@@ -650,14 +665,22 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct
mmc_cmd *cmd,
struct mmc_data *data)
{
struct msdc_host *host = dev_get_priv(dev);
- int ret;
+ int cmd_ret, data_ret;
- ret = msdc_start_command(host, cmd, data);
- if (ret)
- return ret;
+ cmd_ret = msdc_start_command(host, cmd, data);
+ if (cmd_ret &&
+ !(cmd_ret == -EIO &&
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
+ return cmd_ret;
- if (data)
- return msdc_start_data(host, data);
+ if (data) {
+ data_ret = msdc_start_data(host, data);
+ if (cmd_ret)
+ return cmd_ret;
+ else
+ return data_ret;
+ }
return 0;
}
@@ -936,6 +959,56 @@ static struct msdc_delay_phase get_best_delay(struct
msdc_host *host, u32 delay)
return delay_phase;
}
+static int hs400_tune_response(struct udevice *dev, u32 opcode)
+{
+ struct msdc_plat *plat = dev_get_platdata(dev);
+ struct msdc_host *host = dev_get_priv(dev);
+ struct mmc *mmc = >mmc;
+ u32 cmd_delay = 0;
+ struct msdc_delay_phase final_cmd_delay = { 0, };
+ u8 final_delay;
+ void __iomem *tune_reg = >base->pad_cmd_tune;
+ int cmd_err;
+ int i, j;
+
+ setbits_le32(>base->pad_cmd_tune, BIT(0));
+
+ if (mmc->selected_mode == MMC_HS_200 ||
+ mmc->selected_mode == UHS_SDR104)
+ clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
+ host->hs200_cmd_int_delay <<
+ MSDC_PAD_TUNE_CMDRRDLY_S);
+
+ if (host->r_smpl)
+ clrbits_le32(>base->msdc_iocon, MSDC_IOCON_RSPL);
+ else
+ setbits_le32(>base->msdc_iocon, MSDC_IOCON_RSPL);
+
+ for (i = 0; i < PAD_DELAY_MAX; i++) {
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ i << PAD_CMD_TUNE_RX_DLY3_S);
+
+ for (j = 0; j < 3; j++) {
+ mmc_send_tuning(mmc, opcode, _err);
+ if (!cmd_err) {
+ cmd_delay |= (1 << i);
+ } else {
+ cmd_delay &= ~(1 << i);
+ break;
+ }
+ }
+ }
+
+ final_cmd_delay = get_best_delay(host, cmd_delay);
+ clrsetbits_le32(tune_reg, PAD_CMD_TUNE_RX_DLY3,
+ final_cmd_delay.final_phase <<
+ PAD_CMD_TUNE_RX_DLY3_S);
+
[U-Boot] [PATCH v2 4/5] pinctrl: add driver for MT8518
Add Pinctrl driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 9 +-
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 ++
4 files changed, 424 insertions(+), 1 deletion(-)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
index 9f56122319..c2d17fda4a 100644
--- a/arch/arm/dts/mt8518.dtsi
+++ b/arch/arm/dts/mt8518.dtsi
@@ -65,7 +65,14 @@
reset-on-timeout;
};
-
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8518-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
mmc0: mmc@1112 {
compatible = "mediatek,mt8516-mmc";
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 9930ca1faf..22ee62362b 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -16,4 +16,8 @@ config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8518
+bool "MT8518 SoC pinctrl driver"
+ select PINCTRL_MTK
+
endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index c4f29088d2..0ab7b1595b 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
+obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
new file mode 100644
index 00..8d2cd948f6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = {
+ PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = {
+ PIN_FIELD(0, 119, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_di_range[] = {
+ PIN_FIELD(0, 119, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_do_range[] = {
+ PIN_FIELD(0, 119, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = {
+ PIN_FIELD(0, 2, 0x900, 0x10, 0, 1),
+ PIN_FIELD(3, 3, 0x920, 0x10, 9, 1),
+ PIN_FIELD(4, 4, 0x920, 0x10, 8, 1),
+ PIN_FIELD(5, 5, 0x920, 0x10, 7, 1),
+ PIN_FIELD(6, 6, 0x920, 0x10, 6, 1),
+ PIN_FIELD(7, 7, 0x920, 0x10, 10, 1),
+ PIN_FIELD(8, 8, 0x920, 0x10, 1, 1),
+ PIN_FIELD(9, 9, 0x920, 0x10, 0, 1),
+ PIN_FIELD(10, 10, 0x920, 0x10, 5, 1),
+ PIN_FIELD(11, 11, 0x920, 0x10, 4, 1),
+ PIN_FIELD(12, 12, 0x920, 0x10, 3, 1),
+ PIN_FIELD(13, 13, 0x920, 0x10, 2, 1),
+ PIN_FIELD(14, 14, 0x900, 0x10, 1, 1),
+ PIN_FIELD(15, 15, 0x900, 0x10, 2, 1),
+ PIN_FIELD(16, 16, 0x900, 0x10, 3, 1),
+ PIN_FIELD(17, 20, 0x900, 0x10, 4, 1),
+ PIN_FIELD(21, 22, 0x900, 0x10, 5, 1),
+ PIN_FIELD(23, 27, 0x910, 0x10, 15, 1),
+ PIN_FIELD(28, 28, 0x900, 0x10, 6, 1),
+ PIN_FIELD(29, 29, 0x930, 0x10, 2, 1),
+ PIN_FIELD(30, 30, 0x930, 0x10, 1, 1),
+ PIN_FIELD(31, 31, 0x930, 0x10, 6, 1),
+ PIN_FIELD(32, 32, 0x930, 0x10, 5, 1),
+ PIN_FIELD(33, 33, 0x930, 0x10, 4, 1),
+ PIN_FIELD(34, 35, 0x930, 0x10, 3, 1),
+ PIN_FIELD(36, 39, 0x900, 0x10, 7, 1),
+ PIN_FIELD(40, 41, 0x900, 0x10, 8, 1),
+ PIN_FIELD(42, 44, 0x900, 0x10, 9, 1),
+ PIN_FIELD(45, 47, 0x900, 0x10, 10, 1),
+ PIN_FIELD(48, 51, 0x900, 0x10, 11, 1),
+ PIN_FIELD(52, 55, 0x900, 0x10, 12, 1),
+ PIN_FIELD(56, 56, 0x900, 0x10, 13, 1),
+ PIN_FIELD(57, 57, 0x900, 0x10, 14, 1),
+ PIN_FIELD(58, 58, 0x900, 0x10, 15, 1),
+ PIN_FIELD(59, 60, 0x910, 0x10, 0, 1),
+
+ PIN_FIELD(61, 61, 0x910, 0x10, 1, 1),
+ PIN_FIELD(62, 62, 0x910, 0x10, 2, 1),
+ PIN_FIELD(63, 69, 0x910, 0x10, 3, 1),
+ PIN_FIELD(70, 70, 0x910, 0x10, 4, 1),
+ PIN_FIELD(71, 76, 0x910, 0x10, 5, 1),
+ PIN_FIELD(77, 80, 0x910, 0x10, 6, 1),
+ PIN_FIELD(81, 87
[U-Boot] [PATCH v2 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee
---
Changes for v2:
-drop unused 'device' in dtsi to keep it simple
---
arch/arm/dts/mt8518.dtsi | 91 ++
arch/arm/mach-mediatek/Kconfig| 9 ++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8518/Makefile| 4 +
arch/arm/mach-mediatek/mt8518/init.c | 116 ++
arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +
6 files changed, 280 insertions(+)
create mode 100644 arch/arm/dts/mt8518.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644
index 00..9f56122319
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8518";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt8518-topckgen";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@0c00 {
+compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ reg = <0xc00 0x4>, /* GICD */
+ <0xc10 0x20>; /* GICR */
+ interrupts = ;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ timer0: apxgpt@10008000 {
+ compatible = "mediatek,timer";
+ reg = <0x10008000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_CLK26M_D2>,
+< CLK_TOP_CLK32K>,
+< CLK_TOP_APXGPT>;
+ clock-names = "clk13m",
+"clk32k",
+"bus";
+ };
+
+ watchdog0: watchdog@10007000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10007000 0x1000>;
+ interrupts = ;
+ #reset-cells = <1>;
+ status = "disabled";
+ timeout-sec = <60>;
+ reset-on-timeout;
+ };
+
+
+
+ mmc0: mmc@1112 {
+ compatible = "mediatek,mt8516-mmc";
+ reg = <0x1112 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_MSDC0>,
+ < CLK_TOP_MSDC0>,
+ < CLK_TOP_MSDC0_B>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ uart0: serial@11005000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11005000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_TOP_UART0_SEL>,
+ < CLK_TOP_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 25ef7651f0..8e343c3182 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -38,6 +38,15 @@ config TARGET_MT8516
Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth
combo
chip and several DDR3 and DDR4 options.
+config TARGET_MT8518
+ bool "MediaTek MT8518 SoC"
+ select ARM64
+ help
+ The MediaTek MT8518 is a ARM64-based SoC with a quad-core Cortex-A53.
+ including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
+ Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth
combo
+ chip and several DDR3 and DDR4 options.
+
endchoice
source "board/mediatek/mt7623/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index ea414dc407..b9b2355e03 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Make
[U-Boot] [PATCH v2 0/5] Add support for MediaTek MT8518 Soc
This patch series add basic boot support on eMMC for the MediaTek MT8518 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. --- Changes for v2: - fixed issues in v1: drop unused 'devices',delete no need code and print debug log using debug() - delete unnecessary configs in defconfig - adjust the mmc tuning flow to support HS400 mingming lee (5): ARM: MediaTek: Add support for MediaTek MT8518 SoC clk: mediatek: add driver for MT8518 mmc: mtk-sd: Adjust the mmc tuning flow pinctrl: add driver for MT8518 ARM: MediaTek: add basic support for MT8518 boards arch/arm/dts/Makefile |3 +- arch/arm/dts/mt8518-ap1-emmc.dts | 104 ++ arch/arm/dts/mt8518.dtsi | 98 ++ arch/arm/mach-mediatek/Kconfig| 10 + arch/arm/mach-mediatek/Makefile |1 + arch/arm/mach-mediatek/mt8518/Makefile|4 + arch/arm/mach-mediatek/mt8518/init.c | 116 ++ arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 + board/mediatek/mt8518/Kconfig | 14 + board/mediatek/mt8518/MAINTAINERS |6 + board/mediatek/mt8518/Makefile|3 + board/mediatek/mt8518/mt8518_ap1.c| 18 + configs/mt8518_ap1_emmc_defconfig | 41 + drivers/clk/mediatek/Makefile |1 + drivers/clk/mediatek/clk-mt8518.c | 1558 + drivers/mmc/mtk-sd.c | 209 ++- drivers/pinctrl/mediatek/Kconfig |4 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 + include/configs/mt8518.h | 68 + include/dt-bindings/clock/mt8518-clk.h| 249 +++ 21 files changed, 2961 insertions(+), 17 deletions(-) create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts create mode 100644 arch/arm/dts/mt8518.dtsi create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile create mode 100644 arch/arm/mach-mediatek/mt8518/init.c create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S create mode 100644 board/mediatek/mt8518/Kconfig create mode 100644 board/mediatek/mt8518/MAINTAINERS create mode 100644 board/mediatek/mt8518/Makefile create mode 100644 board/mediatek/mt8518/mt8518_ap1.c create mode 100644 configs/mt8518_ap1_emmc_defconfig create mode 100644 drivers/clk/mediatek/clk-mt8518.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c create mode 100644 include/configs/mt8518.h create mode 100644 include/dt-bindings/clock/mt8518-clk.h -- 2.23.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 5/5] ARM: MediaTek: add basic support for MT8518 boards
On Sat, 2019-10-12 at 01:28 +0800, Tom Rini wrote:
> On Wed, Sep 11, 2019 at 07:14:59PM +0800, mingming lee wrote:
>
> > This adds a general board file based on MT8518 SoCs from MediaTek.
> >
> > Apart from the generic parts (cpu) we add some low level init codes
> > and initialize the early clocks.
> >
> > This commit is adding the basic boot support for the MT8518 eMMC board.
> >
> > Signed-off-by: mingming lee
>
> OK, there's a few problems here:
>
> [snip]
> > +int board_init(void)
> > +{
> > + /* address of boot parameters */
> > + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> > +
> > + printf("gd->fdt_blob is %p\n", gd->fdt_blob);
>
> Please remove this (and audit the series for other) bring-up debug
> printfs that we shouldn't need anymore.
>
> > + return 0;
> > +}
> > +
> > +int board_late_init(void)
> > +{
> > + /*to load environment variable from persistent store*/
> > + gd->env_valid = 1;
> > + env_relocate();
> > +
> > + return 0;
> > +}
>
> Er, do you really need this?
>
> [snip]
> > +/* Machine ID */
> > +#define CONFIG_MACH_TYPE 8518
> > +#define CONFIG_SYS_NONCACHED_MEMORYBIT(20)
>
> CONFIG_MACH_TYPE is not relevant to aarch64 platforms (it's for
> pre-device tree boards) and 'BIT(20)' isn't a valid value for
> CONFIG_SYS_NONCACHED_MEMORY (and leads to a warning a build).
>
> Thanks!
>
Thank you for your advice.I would modify those issues in the next
Version.
For the debug info using API printf,I would modify it to the API
debug()
For the API board_late_init and define CONFIG_MACH_TYPE,I would delete
it.
For BIT(20), I used to use SZ_1M,it also have warning.I think I would
modify it to 0x10.
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Re: [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote:
>
> On 11/09/2019 13:14, mingming lee wrote:
> > Add support for MediaTek MT8518 SoC. This include the file
> > that will initialize the SoC after boot and its device tree.
> >
> > Signed-off-by: mingming lee
> > ---
> > arch/arm/dts/mt8518.dtsi | 201 ++
> > arch/arm/mach-mediatek/Kconfig| 9 +
> > arch/arm/mach-mediatek/Makefile | 1 +
> > arch/arm/mach-mediatek/mt8518/Makefile| 4 +
> > arch/arm/mach-mediatek/mt8518/init.c | 116 ++
> > arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +
> > 6 files changed, 390 insertions(+)
> > create mode 100644 arch/arm/dts/mt8518.dtsi
> > create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
> > create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
> > create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
> >
> > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
> > new file mode 100644
> > index 00..39d001884f
> > --- /dev/null
> > +++ b/arch/arm/dts/mt8518.dtsi
> > @@ -0,0 +1,201 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Mingming Lee
> > + *
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/ {
> > + compatible = "mediatek,mt8518";
> > + interrupt-parent = <>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + enable-method = "mediatek,mt8518-smp";
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x1>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu2: cpu@2 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x2>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu3: cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x3>;
> > + clock-frequency = <13>;
> > + };
> > + };
> > +
> > + chipid: chipid@0800 {
> > + compatible = "mediatek,chipid";
> > + reg = <0x0800 0x0004>,
> > + <0x0804 0x0004>,
> > + <0x0808 0x0004>,
> > + <0x080c 0x0004>;
> > + };
>
> I couldn't find any driver using this compatible.
> You may want to drop this 'device'.
>
> Regards,
> Matthias
Thank you for review.
I will drop it and also drop other unused 'device'.
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Re: [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote:
>
> On 11/09/2019 13:14, mingming lee wrote:
> > Add support for MediaTek MT8518 SoC. This include the file
> > that will initialize the SoC after boot and its device tree.
> >
> > Signed-off-by: mingming lee
> > ---
> > arch/arm/dts/mt8518.dtsi | 201 ++
> > arch/arm/mach-mediatek/Kconfig| 9 +
> > arch/arm/mach-mediatek/Makefile | 1 +
> > arch/arm/mach-mediatek/mt8518/Makefile| 4 +
> > arch/arm/mach-mediatek/mt8518/init.c | 116 ++
> > arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +
> > 6 files changed, 390 insertions(+)
> > create mode 100644 arch/arm/dts/mt8518.dtsi
> > create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
> > create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
> > create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
> >
> > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
> > new file mode 100644
> > index 00..39d001884f
> > --- /dev/null
> > +++ b/arch/arm/dts/mt8518.dtsi
> > @@ -0,0 +1,201 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Mingming Lee
> > + *
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/ {
> > + compatible = "mediatek,mt8518";
> > + interrupt-parent = <>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + enable-method = "mediatek,mt8518-smp";
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x1>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu2: cpu@2 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x2>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu3: cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x3>;
> > + clock-frequency = <13>;
> > + };
> > + };
> > +
> > + chipid: chipid@0800 {
> > + compatible = "mediatek,chipid";
> > + reg = <0x0800 0x0004>,
> > + <0x0804 0x0004>,
> > + <0x0808 0x0004>,
> > + <0x080c 0x0004>;
> > + };
>
> I couldn't find any driver using this compatible.
> You may want to drop this 'device'.
>
> Regards,
> Matthias
Thank you for review.
I will drop this 'device' and also drop other unused 'device'.
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Re: [U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
On Sun, 2019-10-13 at 18:55 +0800, Matthias Brugger wrote:
>
> On 11/09/2019 13:14, mingming lee wrote:
> > Add support for MediaTek MT8518 SoC. This include the file
> > that will initialize the SoC after boot and its device tree.
> >
> > Signed-off-by: mingming lee
> > ---
> > arch/arm/dts/mt8518.dtsi | 201 ++
> > arch/arm/mach-mediatek/Kconfig| 9 +
> > arch/arm/mach-mediatek/Makefile | 1 +
> > arch/arm/mach-mediatek/mt8518/Makefile| 4 +
> > arch/arm/mach-mediatek/mt8518/init.c | 116 ++
> > arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +
> > 6 files changed, 390 insertions(+)
> > create mode 100644 arch/arm/dts/mt8518.dtsi
> > create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
> > create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
> > create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
> >
> > diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
> > new file mode 100644
> > index 00..39d001884f
> > --- /dev/null
> > +++ b/arch/arm/dts/mt8518.dtsi
> > @@ -0,0 +1,201 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2019 MediaTek Inc.
> > + * Author: Mingming Lee
> > + *
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +/ {
> > + compatible = "mediatek,mt8518";
> > + interrupt-parent = <>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + enable-method = "mediatek,mt8518-smp";
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu1: cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x1>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu2: cpu@2 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x2>;
> > + clock-frequency = <13>;
> > + };
> > +
> > + cpu3: cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x3>;
> > + clock-frequency = <13>;
> > + };
> > + };
> > +
> > + chipid: chipid@0800 {
> > + compatible = "mediatek,chipid";
> > + reg = <0x0800 0x0004>,
> > + <0x0804 0x0004>,
> > + <0x0808 0x0004>,
> > + <0x080c 0x0004>;
> > + };
>
> I couldn't find any driver using this compatible.
> You may want to drop this 'device'.
>
> Regards,
> Matthias
Thank you for review.
I will drop it and also drop other unused 'device'.
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[U-Boot] [PATCH 5/5] ARM: MediaTek: add basic support for MT8518 boards
This adds a general board file based on MT8518 SoCs from MediaTek.
Apart from the generic parts (cpu) we add some low level init codes
and initialize the early clocks.
This commit is adding the basic boot support for the MT8518 eMMC board.
Signed-off-by: mingming lee
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/mt8518-ap1-emmc.dts | 104 +
arch/arm/mach-mediatek/Kconfig | 1 +
board/mediatek/mt8518/Kconfig | 14
board/mediatek/mt8518/MAINTAINERS | 6 ++
board/mediatek/mt8518/Makefile | 3 +
board/mediatek/mt8518/mt8518_ap1.c | 27
configs/mt8518_ap1_emmc_defconfig | 54 +++
include/configs/mt8518.h | 73
9 files changed, 284 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts
create mode 100644 board/mediatek/mt8518/Kconfig
create mode 100644 board/mediatek/mt8518/MAINTAINERS
create mode 100644 board/mediatek/mt8518/Makefile
create mode 100644 board/mediatek/mt8518/mt8518_ap1.c
create mode 100644 configs/mt8518_ap1_emmc_defconfig
create mode 100644 include/configs/mt8518.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aac1b83d49..54ca31c995 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -788,7 +788,8 @@ dtb-$(CONFIG_SOC_K3_J721E) +=
k3-j721e-common-proc-board.dtb \
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
- mt8516-pumpkin.dtb
+ mt8516-pumpkin.dtb \
+ mt8518-ap1-emmc.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
diff --git a/arch/arm/dts/mt8518-ap1-emmc.dts b/arch/arm/dts/mt8518-ap1-emmc.dts
new file mode 100644
index 00..a542d65f59
--- /dev/null
+++ b/arch/arm/dts/mt8518-ap1-emmc.dts
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8518.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ model = "MT8518 AP1 EMMC";
+
+ chosen {
+ stdout-path =
+ tick-timer =
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0x1000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins_default>;
+ bus-width = <8>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <_3p3v>;
+ vqmmc-supply = <_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+ {
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "msdc";
+ groups = "msdc0";
+ };
+
+ conf-cmd-data {
+ pins = "MSDC0_CMD", "MSDC0_DAT0", "MSDC0_DAT1",
+ "MSDC0_DAT2", "MSDC0_DAT3", "MSDC0_DAT4",
+ "MSDC0_DAT5", "MSDC0_DAT6", "MSDC0_DAT7";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "MSDC0_CLK";
+ bias-pull-down;
+ };
+
+ conf-rst {
+ pins = "MSDC0_RSTB";
+ bias-pull-up;
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_rxd_txd";
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_pins>;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index 8e343c3182..a5808bd343 100644
--- a/arch/arm/mach-media
[U-Boot] [PATCH 4/5] pinctrl: add driver for MT8518
Add Pinctrl driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 9 +
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 ++
4 files changed, 425 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
index 39d001884f..d924944c2a 100644
--- a/arch/arm/dts/mt8518.dtsi
+++ b/arch/arm/dts/mt8518.dtsi
@@ -151,6 +151,15 @@
status = "disabled";
};
+ pinctrl: pinctrl@10005000 {
+ compatible = "mediatek,mt8518-pinctrl";
+ reg = <0x10005000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
mmc0: mmc@1112 {
compatible = "mediatek,mt8516-mmc";
reg = <0x1112 0x1000>;
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 9930ca1faf..22ee62362b 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -16,4 +16,8 @@ config PINCTRL_MT8516
bool "MT8516 SoC pinctrl driver"
select PINCTRL_MTK
+config PINCTRL_MT8518
+bool "MT8518 SoC pinctrl driver"
+ select PINCTRL_MTK
+
endif
diff --git a/drivers/pinctrl/mediatek/Makefile
b/drivers/pinctrl/mediatek/Makefile
index c4f29088d2..0ab7b1595b 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
+obj-$(CONFIG_PINCTRL_MT8518) += pinctrl-mt8518.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
new file mode 100644
index 00..8d2cd948f6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ */
+
+#include
+
+#include "pinctrl-mtk-common.h"
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 16, false)
+
+static const struct mtk_pin_field_calc mt8518_pin_mode_range[] = {
+ PIN_FIELD_CALC(0, 119, 0x300, 0x10, 0, 3, 15, false),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_dir_range[] = {
+ PIN_FIELD(0, 119, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_di_range[] = {
+ PIN_FIELD(0, 119, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_do_range[] = {
+ PIN_FIELD(0, 119, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt8518_pin_ies_range[] = {
+ PIN_FIELD(0, 2, 0x900, 0x10, 0, 1),
+ PIN_FIELD(3, 3, 0x920, 0x10, 9, 1),
+ PIN_FIELD(4, 4, 0x920, 0x10, 8, 1),
+ PIN_FIELD(5, 5, 0x920, 0x10, 7, 1),
+ PIN_FIELD(6, 6, 0x920, 0x10, 6, 1),
+ PIN_FIELD(7, 7, 0x920, 0x10, 10, 1),
+ PIN_FIELD(8, 8, 0x920, 0x10, 1, 1),
+ PIN_FIELD(9, 9, 0x920, 0x10, 0, 1),
+ PIN_FIELD(10, 10, 0x920, 0x10, 5, 1),
+ PIN_FIELD(11, 11, 0x920, 0x10, 4, 1),
+ PIN_FIELD(12, 12, 0x920, 0x10, 3, 1),
+ PIN_FIELD(13, 13, 0x920, 0x10, 2, 1),
+ PIN_FIELD(14, 14, 0x900, 0x10, 1, 1),
+ PIN_FIELD(15, 15, 0x900, 0x10, 2, 1),
+ PIN_FIELD(16, 16, 0x900, 0x10, 3, 1),
+ PIN_FIELD(17, 20, 0x900, 0x10, 4, 1),
+ PIN_FIELD(21, 22, 0x900, 0x10, 5, 1),
+ PIN_FIELD(23, 27, 0x910, 0x10, 15, 1),
+ PIN_FIELD(28, 28, 0x900, 0x10, 6, 1),
+ PIN_FIELD(29, 29, 0x930, 0x10, 2, 1),
+ PIN_FIELD(30, 30, 0x930, 0x10, 1, 1),
+ PIN_FIELD(31, 31, 0x930, 0x10, 6, 1),
+ PIN_FIELD(32, 32, 0x930, 0x10, 5, 1),
+ PIN_FIELD(33, 33, 0x930, 0x10, 4, 1),
+ PIN_FIELD(34, 35, 0x930, 0x10, 3, 1),
+ PIN_FIELD(36, 39, 0x900, 0x10, 7, 1),
+ PIN_FIELD(40, 41, 0x900, 0x10, 8, 1),
+ PIN_FIELD(42, 44, 0x900, 0x10, 9, 1),
+ PIN_FIELD(45, 47, 0x900, 0x10, 10, 1),
+ PIN_FIELD(48, 51, 0x900, 0x10, 11, 1),
+ PIN_FIELD(52, 55, 0x900, 0x10, 12, 1),
+ PIN_FIELD(56, 56, 0x900, 0x10, 13, 1),
+ PIN_FIELD(57, 57, 0x900, 0x10, 14, 1),
+ PIN_FIELD(58, 58, 0x900, 0x10, 15, 1),
+ PIN_FIELD(59, 60, 0x910, 0x10, 0, 1),
+
+ PIN_FIELD(61, 61, 0x910, 0x10, 1, 1),
+ PIN_FIELD(62, 62, 0x910, 0x10, 2, 1),
+ PIN_FIELD(63, 69, 0x910, 0x10, 3, 1),
+ PIN_FIELD(70, 70, 0x910, 0x10, 4, 1),
+ PIN_FIELD(71, 76, 0x910, 0x10, 5, 1),
+ PIN
[U-Boot] [PATCH 3/5] mmc: mtk-sd: add HS200 support
add HS200 mode and tune support
Signed-off-by: mingming lee
---
drivers/mmc/mtk-sd.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index f555357af2..bede4153b3 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -362,6 +362,8 @@ static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
case MMC_CMD_WRITE_SINGLE_BLOCK:
case MMC_CMD_READ_SINGLE_BLOCK:
case SD_CMD_APP_SEND_SCR:
+ case MMC_CMD_SEND_TUNING_BLOCK:
+ case MMC_CMD_SEND_TUNING_BLOCK_HS200:
dtype = 1;
break;
case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */
@@ -467,6 +469,14 @@ static int msdc_start_command(struct msdc_host *host,
struct mmc_cmd *cmd,
if (!msdc_cmd_is_ready(host))
return -EIO;
+ if ((readl(>base->msdc_fifocs) &
+ MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S ||
+ (readl(>base->msdc_fifocs) &
+ MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S) {
+ pr_err("TX/RX FIFO non-empty before start of IO. Reset\n");
+ msdc_reset_hw(host);
+ }
+
msdc_fifo_clr(host);
host->last_resp_type = cmd->resp_type;
@@ -650,14 +660,22 @@ static int msdc_ops_send_cmd(struct udevice *dev, struct
mmc_cmd *cmd,
struct mmc_data *data)
{
struct msdc_host *host = dev_get_priv(dev);
- int ret;
+ int cmd_ret, data_ret;
- ret = msdc_start_command(host, cmd, data);
- if (ret)
- return ret;
+ cmd_ret = msdc_start_command(host, cmd, data);
+ if (cmd_ret &&
+ !(cmd_ret == -EIO &&
+ (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
+ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)))
+ return cmd_ret;
- if (data)
- return msdc_start_data(host, data);
+ if (data) {
+ data_ret = msdc_start_data(host, data);
+ if (cmd_ret)
+ return cmd_ret;
+ else
+ return data_ret;
+ }
return 0;
}
--
2.18.0
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[U-Boot] [PATCH 2/5] clk: mediatek: add driver for MT8518
Add clock driver for MediaTek MT8518 SoC.
Signed-off-by: mingming lee
---
drivers/clk/mediatek/Makefile |1 +
drivers/clk/mediatek/clk-mt8518.c | 1558
include/dt-bindings/clock/mt8518-clk.h | 249
3 files changed, 1808 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt8518.c
create mode 100644 include/dt-bindings/clock/mt8518-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a47a5bdbc2..e92bcd4efe 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
+obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt8518.c
b/drivers/clk/mediatek/clk-mt8518.c
new file mode 100644
index 00..35b3db28e6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -0,0 +1,1558 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT8518 SoC
+ *
+ * Copyright (C) 2019 BayLibre, SAS
+ * Author: Chen Zhong
+ */
+
+#include
+#include
+#include
+#include
+
+#include "clk-mtk.h"
+
+#define MT8518_PLL_FMAX(3000UL * MHZ)
+#define MT8518_CON0_RST_BARBIT(27)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg,\
+ .pwr_reg = _pwr_reg,\
+ .en_mask = _en_mask,\
+ .rst_bar_mask = MT8518_CON0_RST_BAR,\
+ .fmax = MT8518_PLL_FMAX,\
+ .flags = _flags,\
+ .pcwbits = _pcwbits,\
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg,\
+ .pcw_shift = _pcw_shift,\
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x0001,
+ 0, 21, 0x0104, 24, 0x0104, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x0001,
+ HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
+ PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x3001,
+ HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
+ PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x0001,
+ 0, 21, 0x0164, 24, 0x0164, 0),
+ PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x0001,
+ 0, 31, 0x0180, 1, 0x0184, 0),
+ PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x0001,
+ 0, 31, 0x01A0, 1, 0x01A4, 0),
+ PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x0001,
+ 0, 21, 0x01C4, 24, 0x01C4, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 2600),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 5),
+ FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 5),
+ FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
+ FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
+ FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
+ FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
+ FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
+ FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
+ FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
+ FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
+ FACTOR0(CLK_TOP_
[U-Boot] [PATCH 0/5] Add support for MediaTek MT8518 Soc
This patch series adds basic boot support on eMMC for the MediaTek MT8518 SoC based boards. This series add the clock, pinctrl drivers and the SoC initializaton code. mingming lee (5): ARM: MediaTek: Add support for MediaTek MT8518 SoC clk: mediatek: add driver for MT8518 mmc: mtk-sd: add HS200 support pinctrl: add driver for MT8518 ARM: MediaTek: add basic support for MT8518 boards arch/arm/dts/Makefile |3 +- arch/arm/dts/mt8518-ap1-emmc.dts | 104 ++ arch/arm/dts/mt8518.dtsi | 210 +++ arch/arm/mach-mediatek/Kconfig| 10 + arch/arm/mach-mediatek/Makefile |1 + arch/arm/mach-mediatek/mt8518/Makefile|4 + arch/arm/mach-mediatek/mt8518/init.c | 116 ++ arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 + board/mediatek/mt8518/Kconfig | 14 + board/mediatek/mt8518/MAINTAINERS |6 + board/mediatek/mt8518/Makefile|3 + board/mediatek/mt8518/mt8518_ap1.c| 27 + configs/mt8518_ap1_emmc_defconfig | 54 + drivers/clk/mediatek/Makefile |1 + drivers/clk/mediatek/clk-mt8518.c | 1558 + drivers/mmc/mtk-sd.c | 30 +- drivers/pinctrl/mediatek/Kconfig |4 + drivers/pinctrl/mediatek/Makefile |1 + drivers/pinctrl/mediatek/pinctrl-mt8518.c | 411 + include/configs/mt8518.h | 73 + include/dt-bindings/clock/mt8518-clk.h| 249 +++ 21 files changed, 2931 insertions(+), 7 deletions(-) create mode 100644 arch/arm/dts/mt8518-ap1-emmc.dts create mode 100644 arch/arm/dts/mt8518.dtsi create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile create mode 100644 arch/arm/mach-mediatek/mt8518/init.c create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S create mode 100644 board/mediatek/mt8518/Kconfig create mode 100644 board/mediatek/mt8518/MAINTAINERS create mode 100644 board/mediatek/mt8518/Makefile create mode 100644 board/mediatek/mt8518/mt8518_ap1.c create mode 100644 configs/mt8518_ap1_emmc_defconfig create mode 100644 drivers/clk/mediatek/clk-mt8518.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8518.c create mode 100644 include/configs/mt8518.h create mode 100644 include/dt-bindings/clock/mt8518-clk.h -- 2.18.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 201 ++
arch/arm/mach-mediatek/Kconfig| 9 +
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8518/Makefile| 4 +
arch/arm/mach-mediatek/mt8518/init.c | 116 ++
arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +
6 files changed, 390 insertions(+)
create mode 100644 arch/arm/dts/mt8518.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644
index 00..39d001884f
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8518";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt8518-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-frequency = <13>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-frequency = <13>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-frequency = <13>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-frequency = <13>;
+ };
+ };
+
+ chipid: chipid@0800 {
+ compatible = "mediatek,chipid";
+ reg = <0x0800 0x0004>,
+ <0x0804 0x0004>,
+ <0x0808 0x0004>,
+ <0x080c 0x0004>;
+ };
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt8518-topckgen";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: clock-controller-cg@1000 {
+ compatible = "mediatek,mt8518-topckgen-cg";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: clock-controller@10018000 {
+ compatible = "mediatek,mt8518-apmixedsys";
+ reg = <0x10018000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@0c00 {
+compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ reg = <0xc00 0x4>, /* GICD */
+ <0xc10 0x20>; /* GICR */
+ interrupts = ;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ apdma: dma-controller@11000480 {
+ compatible = "mediatek,mt8518-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0x11000480 0x80>,
+ <0x11000500 0x80>,
+ <0x11000580 0x80>,
+ <0x11000600 0x80>,
+ <0x11000980 0x80>,
+ <0x11000a00 0x80>;
+ interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ clocks = < CLK_TOP_APDMA>;
+ clock-names = "apdma";
+
[U-Boot] [PATCH 1/5] ARM: MediaTek: Add support for MediaTek MT8518 SoC
Add support for MediaTek MT8518 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: mingming lee
---
arch/arm/dts/mt8518.dtsi | 201 ++
arch/arm/mach-mediatek/Kconfig| 9 +
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8518/Makefile| 4 +
arch/arm/mach-mediatek/mt8518/init.c | 116 ++
arch/arm/mach-mediatek/mt8518/lowlevel_init.S | 59 +
6 files changed, 390 insertions(+)
create mode 100644 arch/arm/dts/mt8518.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8518/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8518/init.c
create mode 100644 arch/arm/mach-mediatek/mt8518/lowlevel_init.S
diff --git a/arch/arm/dts/mt8518.dtsi b/arch/arm/dts/mt8518.dtsi
new file mode 100644
index 00..39d001884f
--- /dev/null
+++ b/arch/arm/dts/mt8518.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Mingming Lee
+ *
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8518";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt8518-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-frequency = <13>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-frequency = <13>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ clock-frequency = <13>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ clock-frequency = <13>;
+ };
+ };
+
+ chipid: chipid@0800 {
+ compatible = "mediatek,chipid";
+ reg = <0x0800 0x0004>,
+ <0x0804 0x0004>,
+ <0x0808 0x0004>,
+ <0x080c 0x0004>;
+ };
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt8518-topckgen";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen_cg: clock-controller-cg@1000 {
+ compatible = "mediatek,mt8518-topckgen-cg";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apmixedsys: clock-controller@10018000 {
+ compatible = "mediatek,mt8518-apmixedsys";
+ reg = <0x10018000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ gic: interrupt-controller@0c00 {
+compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ interrupt-controller;
+ reg = <0xc00 0x4>, /* GICD */
+ <0xc10 0x20>; /* GICR */
+ interrupts = ;
+ };
+
+ sysirq: interrupt-controller@10200a80 {
+ compatible = "mediatek,sysirq";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <>;
+ reg = <0x10200a80 0x50>;
+ };
+
+ apdma: dma-controller@11000480 {
+ compatible = "mediatek,mt8518-uart-dma",
+ "mediatek,mt6577-uart-dma";
+ reg = <0x11000480 0x80>,
+ <0x11000500 0x80>,
+ <0x11000580 0x80>,
+ <0x11000600 0x80>,
+ <0x11000980 0x80>,
+ <0x11000a00 0x80>;
+ interrupts = ,
+ ,
+ ,
+ ,
+ ,
+ ;
+ clocks = < CLK_TOP_APDMA>;
+ clock-names = "apdma";
+
