This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip QSPI driver and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for
the HSS to use.
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
board/microchip/mpfs_icicle/Kconfig
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli
Signed-off-by: Naga Sureshkumar Relli
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
drivers/spi/Kconfig
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree.
The Winbond NAND flash memory can be connected to the
Icicle Kit by using the Mikroe Flash 5 click board and
the Pi 3 Click shield.
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
arch/riscv/dts
.
Co-developed-by: Conor Dooley
Signed-off-by: Conor Dooley
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 75 +---
1 file changed, 17 insertions(+), 58 deletions(-)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle
:
- Add Co-developed-by with patch
- Replace spi-nand with flash in device node
- Add board details for QSPI NAND
- Rename QSPI driver file with microchip-coreqspi
- Add microchip,coreqspi-rtl-v2 to the compatible list
- Use MICROCHIP_COREQSPI instead of MICROCHIP_QSPI in kconfig
Padmarao Begari (4
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip QSPI driver and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for
the HSS to use.
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
board/microchip/mpfs_icicle/Kconfig
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli
Signed-off-by: Naga Sureshkumar Relli
Signed-off-by: Padmarao Begari
---
drivers/spi/Kconfig | 6 +
drivers/spi
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree.
The Winbond NAND flash memory can be connected to the
Icicle Kit by using the Mikroe Flash 5 click board and
the Pi 3 Click shield.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
context.
Co-developed-by: Conor Dooley
Signed-off-by: Conor Dooley
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70
1 file changed, 14 insertions(+), 56 deletions(-)
diff --git a/arch/riscv/dts/microchip-mpfs
with microchip-coreqspi
- Add microchip,coreqspi-rtl-v2 to the compatible list
- Use MICROCHIP_COREQSPI instead of MICROCHIP_QSPI in kconfig
Padmarao Begari (4):
riscv: dts: Update memory configuration
riscv: dts: Add QSPI NAND device node
spi: Add Microchip PolarFire SoC QSPI driver
riscv
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the qspi standard, dual and quad
mode interfaces.
Signed-off-by: Padmarao Begari
Signed-off-by: Naga Sureshkumar Relli
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip QSPI driver and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for
the HSS to use.
Signed-off-by: Padmarao Begari
---
board/microchip/mpfs_icicle/Kconfig | 7 +++
configs
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts
context.
Signed-off-by: Padmarao Begari
Signed-off-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70
1 file changed, 14 insertions(+), 56 deletions(-)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle
FPGA reference design and a small 4MB reservation is
made at the end of 32-bit DDR to provide some memory for the HSS
to use, add Microchip QSPI driver.
Padmarao Begari (4):
riscv: dts: update memory configuration
riscv: dts: Add QSPI NAND device node
riscv: Update Microchip MPFS Icicle Kit
Hi Bin,
On Fri, Nov 12, 2021 at 6:58 AM Bin Meng wrote:
> On Thu, Nov 11, 2021 at 9:17 PM wrote:
> >
> > > I agree with Bin here. You shouldn't introduce a new compatible just
> for
> > > u-boot. If you need one, please to it first in linux and get an ACK
> there.
> > > Or at least there
Hi Bin,
On Thu, Nov 11, 2021 at 1:37 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Nov 11, 2021 at 2:11 PM wrote:
> >
> > Hi Bin,
> >
> >
> >
> > Do we need to upstream Linux kernel bindings for Microchip MACB
> compatible if there is no change in Linux MACB driver?
> >
> > Are the Linux
Hi Bin,
On Wed, Nov 3, 2021 at 5:17 PM Padmarao Begari wrote:
> Hi Bin,
>
> On Tue, Nov 2, 2021 at 6:16 PM Bin Meng wrote:
>
>> Hi Padmarao,
>>
>> On Tue, Nov 2, 2021 at 7:03 PM Padmarao Begari
>> wrote:
>> >
>> > Hi Bin,
&g
Hi Bin,
On Tue, Nov 2, 2021 at 6:16 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Tue, Nov 2, 2021 at 7:03 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, Nov 1, 2021 at 2:15 PM Bin Meng wrote:
> >>
> >> On Fri, Oct 22, 2021 at 4:5
Hi Bin,
On Mon, Nov 1, 2021 at 2:16 PM Bin Meng wrote:
> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
> wrote:
> >
> > UART1 uses for U-BOOT and Linux console instead of UART0 and
>
> nits: s/U-BOOT/U-Boot
>
>
ok
> > UART0 is reserved for Hart Softwa
Hi Bin,
On Mon, Nov 1, 2021 at 2:15 PM Bin Meng wrote:
> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
> wrote:
> >
> > Update compatible as per Microchip PolarFire SoC ethernet
> > device node.
> >
> > Signed-off-by: Padmarao Begari
> > ---
On Mon, Nov 1, 2021 at 2:13 PM Bin Meng wrote:
> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
> wrote:
> >
> > This patch updates Microchip MPFS Icicle Kit support. For now,
> > add Microchip I2C driver, set environment variables for
> > mac addesses
Hi Bin,
On Mon, Nov 1, 2021 at 2:11 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
> wrote:
> >
> > The device tree split into .dtsi and .dts files, common
> > device node for eMMC/SD, enable I2C1, UART1 for console
> &
Add I2C driver code for the Microchip PolarFire SoC.
This driver supports I2C data transfer and probe for I2C
slave addresses.
Signed-off-by: Padmarao Begari
---
drivers/i2c/Kconfig | 6 +
drivers/i2c/Makefile| 1 +
drivers/i2c/i2c-microchip.c | 482
The device tree split into .dtsi and .dts files, common
device node for eMMC/SD, enable I2C1, UART1 for console
instead of UART0, enable the DDR 2GB memory and in
that 288MB memory is reserved for fabric buffer.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
Update compatible as per Microchip PolarFire SoC ethernet
device node.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8c6461e717..1b867bd5c2 100644
--- a/drivers/net/macb.c
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip I2C driver, set environment variables for
mac addesses and default build for SBI_V02.
Signed-off-by: Padmarao Begari
---
board/microchip/mpfs_icicle/Kconfig | 5 +
board/microchip/mpfs_icicle/mpfs_icicle.c
UART1 uses for U-BOOT and Linux console instead of UART0 and
UART0 is reserved for Hart Software Services(HSS).
Signed-off-by: Padmarao Begari
---
doc/board/microchip/mpfs_icicle.rst | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/doc/board/microchip
instead of UART0, UART0 is reserved for Hart
Software Services, common device node for eMMC/SD, add Microchip
I2C driver and default build for SBI_V02.
Padmarao Begari (5):
riscv: dts: Split Microchip device tree
riscv: Update Microchip MPFS Icicle Kit support
i2c: Add Microchip PolarFire SoC
;okay";
> };
> @@ -316,7 +313,6 @@
> reg-shift = <2>;
> interrupt-parent = <>;
> interrupts = <93>;
> - clock-frequency = <15000>;
> clocks = < CLK_MMUART3>;
> status = "okay";
> };
> --
> 2.25.1
>
>
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
.probe = mpfs_clk_probe,
> .priv_auto = sizeof(struct clk),
> + .flags = DM_FLAG_PRE_RELOC,
> };
> --
> 2.25.1
>
>
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
+++ b/configs/microchip_mpfs_icicle_defconfig
> @@ -1,4 +1,5 @@
> CONFIG_RISCV=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> CONFIG_ENV_SIZE=0x2000
> CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
> CONFIG_TARGET_MICROCHIP_ICICLE=y
> --
> 2.25.1
>
>
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
Hi Sean,
On Tue, Mar 16, 2021 at 9:52 AM Sean Anderson wrote:
> On 3/16/21 12:05 AM, Padmarao Begari wrote:
> > Hi Sean,
> >
> > On Thu, Mar 11, 2021 at 7:18 AM Sean Anderson <mailto:sean...@gmail.com>> wrote:
> >
> > The HSS source uses a
Hi Sean,
On Thu, Mar 11, 2021 at 7:18 AM Sean Anderson wrote:
> The HSS source uses an "mpfs" prefix with the icicle board name. Change our
> documentation to match.
>
Signed-off-by: Sean Anderson
> ---
>
> doc/board/microchip/mpfs_icicle.rst | 6 +++---
> 1 file changed, 3 insertions(+), 3
Hi Eugen,
On Fri, Jan 15, 2021 at 1:34 PM wrote:
> On 15.01.2021 06:02, Padmarao Begari wrote:
> > Hi Eugen,
> >
> > On Thu, Jan 14, 2021 at 4:50 PM > <mailto:eugen.hris...@microchip.com>> wrote:
> >
> > On 17.12.2020 07:22, Padmar
+ OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
---
arch/riscv/Kconfig | 4
arch/riscv/include
s are on UART0
- Move clock and reset index source into patch4
- Remove "dma_addr_r" type in the macb driver
- Add lower_32_bits() for 32-bit address in the macb driver
- Add set_rate() returns the new clock rate in the clock driver
Padmarao Begari (7):
riscv: Add DMA 64-bit address suppor
Hi Eugen,
On Thu, Jan 14, 2021 at 4:50 PM wrote:
> On 17.12.2020 07:22, Padmarao Begari - I30397 wrote:
> > Hi Eugen,
> >
> > This series of patches break my side of work(patches) so you need to
> > create patches after my patches are going into master branch because
Hi Tom,
On Thu, Jan 14, 2021 at 1:31 AM Tom Rini wrote:
> On Wed, Jan 13, 2021 at 01:34:55PM +0800, ub...@andestech.com wrote:
>
> > Hi Tom,
> >
> > Please pull some riscv updates:
> >
> > - Update qemu-riscv.rst build instructions.
> > - Add support for SPI on Kendryte K210.
> > - Add
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+ OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17
r 32-bit address in the macb driver
- Add set_rate() returns the new clock rate in the clock driver
Padmarao Begari (7):
riscv: Add DMA 64-bit address support
net: macb: Add DMA 64-bit address support for macb
net: macb: Add phy address to read it from device tree
clk: Add Microchip PolarFire
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Rick Chen
---
arch/riscv/Kconfig | 4
arch/riscv/include
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions
Hi Rick,
On Mon, Jan 11, 2021 at 8:26 AM Rick Chen wrote:
> Hi Padmarao
>
> > From: Padmarao Begari [mailto:padmarao.beg...@microchip.com]
> > Sent: Tuesday, December 22, 2020 9:12 PM
> > To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志);
>
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+ OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
doc for the U-Boot logs are on UART0
- Move clock and reset index source into patch4
- Remove "dma_addr_r" type in the macb driver
- Add lower_32_bits() for 32-bit address in the macb driver
- Add set_rate() returns the new clock rate in the clock driver
Padmarao Begari (7):
riscv: Add DM
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/Kconfig | 4
arch/riscv/include/asm/types.h | 4
2
Hi Simon,
On Sat, Dec 19, 2020 at 7:58 AM Simon Glass wrote:
> Hi Padmarao,
>
> On Mon, 14 Dec 2020 at 04:09, Padmarao Begari
> wrote:
> >
> > Add clock driver code for the Microchip PolarFire SoC. This driver
> > handles reset and clock control of the
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst
+ OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17 deletions(-)
diff --git
_bits() for 32-bit address in the macb driver
- Add set_rate() returns the new clock rate in the clock driver
Padmarao Begari (7):
riscv: Add DMA 64-bit address support
net: macb: Add DMA 64-bit address support for macb
net: macb: Add phy address to read it from device tree
clk: Add Microc
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig | 4
arch/riscv/include/asm/types.h | 4
2 files changed, 8
Hi Bin,
On Fri, Dec 11, 2020 at 2:57 PM Bin Meng wrote:
> HI Padmarao,
>
> On Fri, Dec 11, 2020 at 4:23 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Fri, Dec 11, 2020 at 1:22 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
> >>
Hi Bin,
On Fri, Dec 11, 2020 at 2:59 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 4:49 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
>
Hi Bin,
On Fri, Dec 11, 2020 at 2:55 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 4:32 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
&g
Hi Bin,
On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >
> > Hi Padmarao,
> >
> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> > wrote:
> > >
> > > Enable
Hi Bin,
On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >
> > Hi Padmarao,
> >
> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> > wrote:
> > >
> > > Enable
Hi Bin,
On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed
Hi Bin,
On Fri, Dec 11, 2020 at 1:22 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 3:10 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
&g
Hi Bin,
On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:43 AM Padmarao Begari
> wrote:
> >
> > dma_addr_t holds any valid DMA address. If the DMA API only uses
> 32/64-bit
> > addresses, dma_addr_t need only be 32
Hi Bin,
On Thu, Dec 10, 2020 at 4:25 PM Bin Meng wrote:
> On Thu, Dec 10, 2020 at 6:04 PM Bin Meng wrote:
> >
> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> > wrote:
> > >
> > > Add clock driver code for the Microchip PolarFire SoC. This drive
Hi Bin,
On Thu, Dec 10, 2020 at 3:54 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > This patch adds Microchip MPFS Icicle Kit support. For now, only
> > NS16550 Serial, Microchip clock, Cadence eMMC and MAC
Hi Bin,
On Thu, Dec 10, 2020 at 6:48 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-b
Hi Bin,
On Thu, Dec 10, 2020 at 12:08 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > This doc describes the procedure to build, flash and
> > boot Linux using U-boot on Microchip MPFS Icicle Kit.
> >
Hi Rick,
On Thu, Dec 10, 2020 at 8:33 AM Rick Chen wrote:
> Hi Padmarao
>
> > From: Padmarao Begari [mailto:padmarao.beg...@microchip.com]
> > Sent: Thursday, December 03, 2020 4:32 AM
> > To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志);
>
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421
+ OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
board/microchip/mpfs_icicle/Kconfig | 24 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 97 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
compatible string of the device tree node.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig | 4
arch/riscv/include/asm/types.h | 4
2 files changed, 8
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
the macb driver
- Add set_rate() returns the new clock rate in the clock driver
Padmarao Begari (7):
riscv: Add DMA 64-bit address support
net: macb: Add DMA 64-bit address support for macb
net: macb: Add phy address to read it from device tree
clk: Add Microchip PolarFire SoC clock d
Hi Cyril,
On Fri, Nov 27, 2020 at 10:05 PM wrote:
> Hi Padmarao,
>
> On 11/27/20 12:04 PM, Padmarao Begari wrote:
> > This doc describes the procedure to build, flash and
> > boot Linux using U-boot on Microchip MPFS Icicle Kit.
> >
> > Signed-off-by: Padma
Hi Cyril,
On Fri, Nov 27, 2020 at 9:47 PM wrote:
> Hi Padmarao,
>
> On 11/27/20 12:04 PM, Padmarao Begari wrote:
> > This patch set adds Microchip PolarFire SoC Icicle Kit support
> > to RISC-V U-Boot.
> >
> > The patches are based upon latest U-Boot tree
>
Hi Cyril,
On Fri, Nov 27, 2020 at 9:45 PM wrote:
> On 11/27/20 1:43 PM, Bin Meng wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> the content is safe
> >
> > Hi Padmarao,
> >
> > On Fri, Nov 27, 2020 at 8:18 PM Padmarao Beg
Hi Bin,
On Fri, Nov 27, 2020 at 7:13 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Nov 27, 2020 at 8:18 PM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-b
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers
+ OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
board/microchip/mpfs_icicle/Kconfig | 24 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 97 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421
1 - 100 of 149 matches
Mail list logo
