[PATCH v3 4/4] riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now, add Microchip QSPI driver and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use. Signed-off-by: Padmarao Begari Reviewed-by: Conor Dooley --- board/microchip/mpfs_icicle/Kconfig | 7 +++ configs/microchip_mpfs_icicle_defconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 092e411215..332f03f0da 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -50,5 +50,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_I2C imply DM_I2C imply SYS_I2C_MICROCHIP + imply SPI + imply DM_SPI + imply MICROCHIP_COREQSPI + imply MTD_SPI_NAND + imply CMD_MTD + imply MTD_PARTITIONS + imply CMD_MTDPARTS endif diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 6113c5be80..c295b9bad3 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -17,6 +17,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_SYS_MEM_TOP_HIDE=0x40 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y -- 2.25.1
[PATCH v3 3/4] spi: Add Microchip PolarFire SoC QSPI driver
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli
Signed-off-by: Naga Sureshkumar Relli
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/microchip_coreqspi.c | 505 +++
3 files changed, 512 insertions(+)
create mode 100644 drivers/spi/microchip_coreqspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2f12081f88..994bfd563e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -237,6 +237,12 @@ config MESON_SPIFC
This driver can be used to access the SPI NOR flash chips on
Amlogic Meson SoCs.
+config MICROCHIP_COREQSPI
+ bool "Microchip FPGA QSPI Controller driver"
+ help
+ Enable the QSPI driver for Microchip FPGA QSPI controllers.
+ This driver can be used on Polarfire SoC.
+
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
depends on MPC8xx
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 50ba43550b..6d1154b902 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
+obj-$(CONFIG_MICROCHIP_COREQSPI) += microchip_coreqspi.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c
new file mode 100644
index 00..5fe0c8e123
--- /dev/null
+++ b/drivers/spi/microchip_coreqspi.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Microchip Technology Inc.
+ * Padmarao Begari
+ * Naga Sureshkumar Relli
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * QSPI Control register mask defines
+ */
+#define CONTROL_ENABLE BIT(0)
+#define CONTROL_MASTER BIT(1)
+#define CONTROL_XIPBIT(2)
+#define CONTROL_XIPADDRBIT(3)
+#define CONTROL_CLKIDLEBIT(10)
+#define CONTROL_SAMPLE_MASKGENMASK(12, 11)
+#define CONTROL_MODE0 BIT(13)
+#define CONTROL_MODE12_MASKGENMASK(15, 14)
+#define CONTROL_MODE12_EX_RO BIT(14)
+#define CONTROL_MODE12_EX_RW BIT(15)
+#define CONTROL_MODE12_FULLGENMASK(15, 14)
+#define CONTROL_FLAGSX4BIT(16)
+#define CONTROL_CLKRATE_MASK GENMASK(27, 24)
+#define CONTROL_CLKRATE_SHIFT 24
+
+/*
+ * QSPI Frames register mask defines
+ */
+#define FRAMES_TOTALBYTES_MASK GENMASK(15, 0)
+#define FRAMES_CMDBYTES_MASK GENMASK(24, 16)
+#define FRAMES_CMDBYTES_SHIFT 16
+#define FRAMES_SHIFT 25
+#define FRAMES_IDLE_MASK GENMASK(29, 26)
+#define FRAMES_IDLE_SHIFT 26
+#define FRAMES_FLAGBYTEBIT(30)
+#define FRAMES_FLAGWORDBIT(31)
+
+/*
+ * QSPI Interrupt Enable register mask defines
+ */
+#define IEN_TXDONE BIT(0)
+#define IEN_RXDONE BIT(1)
+#define IEN_RXAVAILABLEBIT(2)
+#define IEN_TXAVAILABLEBIT(3)
+#define IEN_RXFIFOEMPTYBIT(4)
+#define IEN_TXFIFOFULL BIT(5)
+
+/*
+ * QSPI Status register mask defines
+ */
+#define STATUS_TXDONE BIT(0)
+#define STATUS_RXDONE BIT(1)
+#define STATUS_RXAVAILABLE BIT(2)
+#define STATUS_TXAVAILABLE BIT(3)
+#define STATUS_RXFIFOEMPTY BIT(4)
+#define STATUS_TXFIFOFULL BIT(5)
+#define STATUS_READY BIT(7)
+#define STATUS_FLAGSX4 BIT(8)
+#define STATUS_MASKGENMASK(8, 0)
+
+#define BYTESUPPER_MASKGENMASK(31, 16)
+#define BYTESLOWER_MASKGENMASK(15, 0)
+
+#define MAX_DIVIDER16
+#define MIN_DIVIDER0
+#define MAX_DATA_CMD_LEN 256
+
+/* QSPI ready time out value */
+#define TIMEOUT_MS (1000 * 500)
+
+/*
+ * QSPI Register offsets.
+ */
+#define REG_CONTROL(0x00)
+#define REG_FRAMES (0x04)
+#define REG_IEN(0x0c)
+#define REG_STATUS (0x10)
+#define REG_DIRECT_ACCESS (0x14)
+#define REG_UPPER_ACCESS (0x18)
+#define REG_RX_DATA(0x40)
+#define REG_TX_DATA(0x44)
+#define REG_X4_RX_DATA (0x48)
+#define REG_X4_TX_DATA (0x4c)
+#define REG_FRAMESUP (0x50)
+
+/**
+ * struct mchp_coreqspi - Defines qspi driver instance
+ * @regs: Address of the QSPI controller registers
+ * @freq: QSPI Input frequency
+ * @txbuf: TX buffer
+ * @rxbuf: RX buffer
+ * @tx_len:Number of bytes left to transfer
+ * @rx_len:Number of bytes left to receive
+ */
+struct mchp_coreqspi {
+
[PATCH v3 2/4] riscv: dts: Add QSPI NAND device node
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree.
The Winbond NAND flash memory can be connected to the
Icicle Kit by using the Mikroe Flash 5 click board and
the Pi 3 Click shield.
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 48fc2bf06a..762dcfc694 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -19,6 +19,7 @@
aliases {
serial1 =
ethernet0 =
+ spi0 =
};
chosen {
@@ -114,3 +115,18 @@
ti,fifo-depth = <0x1>;
};
};
+
+ {
+ status = "okay";
+ num-cs = <1>;
+
+ flash0: flash@0 {
+ compatible = "spi-nand";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <2000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
--
2.25.1
[PATCH v3 1/4] riscv: dts: Update memory configuration
In the v2022.10 Icicle reference design, the seg registers have been
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific context.
Co-developed-by: Conor Dooley
Signed-off-by: Conor Dooley
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 75 +---
1 file changed, 17 insertions(+), 58 deletions(-)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 287ef3d23b..48fc2bf06a 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2021 Microchip Technology Inc.
+ * Copyright (C) 2021-2022 Microchip Technology Inc.
* Padmarao Begari
*/
@@ -13,7 +13,8 @@
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
+ compatible = "microchip,mpfs-icicle-reference-rtlv2210",
+"microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
serial1 =
@@ -28,70 +29,28 @@
timebase-frequency = ;
};
- reserved-memory {
- ranges;
- #size-cells = <2>;
- #address-cells = <2>;
-
- fabricbuf0: fabricbuf@0 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xae00 0x0 0x200>;
- label = "fabricbuf0-ddr-c";
- };
-
- fabricbuf1: fabricbuf@1 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xc000 0x0 0x800>;
- label = "fabricbuf1-ddr-nc";
- };
-
- fabricbuf2: fabricbuf@2 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xd800 0x0 0x800>;
- label = "fabricbuf2-ddr-nc-wcb";
- };
- };
-
- udmabuf0 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-c0";
- minor-number = <0>;
- size = <0x0 0x200>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
- udmabuf1 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc0";
- minor-number = <1>;
- size = <0x0 0x800>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
- udmabuf2 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc-wcb0";
- minor-number = <2>;
- size = <0x0 0x800>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
ddrc_cache_lo: memory@8000 {
device_type = "memory";
- reg = <0x0 0x8000 0x0 0x2e00>;
- clocks = < CLK_DDRC>;
+ reg = <0x0 0x8000 0x0 0x4000>;
status = "okay";
};
- ddrc_cache_hi: memory@10 {
+ ddrc_cache_hi: memory@104000 {
device_type = "memory";
- reg = <0x10 0x0 0x0 0x4000>;
- clocks = < CLK_DDRC>;
+ reg = <0x10 0x4000 0x0 0x4000>;
status = "okay";
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss_payload: region@BFC0 {
+ reg = <0x0 0xBFC0 0x0 0x40>;
+ no-map;
+ };
+ };
};
{
--
2.25.1
[PATCH v3 0/4] Update Microchip PolarFire SoC
This patch set updates Microchip PolarFire SoC Icicle Kit support of RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://source.denx.de/u-boot/u-boot) at commit id 8bc87a4c55a1723728374a5643f13bced37dad6b The memory device node is updated based on the latest FPGA reference design v2022.10 and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, add Microchip QSPI driver. Changes in v3: - Add reference design campatible in the device tree - Change QSPI time out value to 500ms(as per Linux) - Fix some typos Changes in v2: - Add Co-developed-by with patch - Replace spi-nand with flash in device node - Add board details for QSPI NAND - Rename QSPI driver file with microchip-coreqspi - Add microchip,coreqspi-rtl-v2 to the compatible list - Use MICROCHIP_COREQSPI instead of MICROCHIP_QSPI in kconfig Padmarao Begari (4): riscv: dts: Update memory configuration riscv: dts: Add QSPI NAND device node spi: Add Microchip PolarFire SoC QSPI driver riscv: Update Microchip MPFS Icicle Kit support arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 91 ++-- board/microchip/mpfs_icicle/Kconfig | 7 + configs/microchip_mpfs_icicle_defconfig | 1 + drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/microchip_coreqspi.c | 505 +++ 6 files changed, 553 insertions(+), 58 deletions(-) create mode 100644 drivers/spi/microchip_coreqspi.c -- 2.25.1
[PATCH v2 4/4] riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now, add Microchip QSPI driver and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use. Signed-off-by: Padmarao Begari Reviewed-by: Conor Dooley --- board/microchip/mpfs_icicle/Kconfig | 7 +++ configs/microchip_mpfs_icicle_defconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 092e411215..332f03f0da 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -50,5 +50,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_I2C imply DM_I2C imply SYS_I2C_MICROCHIP + imply SPI + imply DM_SPI + imply MICROCHIP_COREQSPI + imply MTD_SPI_NAND + imply CMD_MTD + imply MTD_PARTITIONS + imply CMD_MTDPARTS endif diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 6113c5be80..c295b9bad3 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -17,6 +17,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_SYS_MEM_TOP_HIDE=0x40 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y -- 2.25.1
[PATCH v2 3/4] spi: Add Microchip PolarFire SoC QSPI driver
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the QSPI standard, dual and quad
mode interfaces.
Co-developed-by: Naga Sureshkumar Relli
Signed-off-by: Naga Sureshkumar Relli
Signed-off-by: Padmarao Begari
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/microchip_coreqspi.c | 505 +++
3 files changed, 512 insertions(+)
create mode 100644 drivers/spi/microchip_coreqspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2f12081f88..994bfd563e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -237,6 +237,12 @@ config MESON_SPIFC
This driver can be used to access the SPI NOR flash chips on
Amlogic Meson SoCs.
+config MICROCHIP_COREQSPI
+ bool "Microchip FPGA QSPI Controller driver"
+ help
+ Enable the QSPI driver for Microchip FPGA QSPI controllers.
+ This driver can be used on Polarfire SoC.
+
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
depends on MPC8xx
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 50ba43550b..6d1154b902 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
+obj-$(CONFIG_MICROCHIP_COREQSPI) += microchip_coreqspi.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c
new file mode 100644
index 00..ea81ddd03c
--- /dev/null
+++ b/drivers/spi/microchip_coreqspi.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Microchip Technology Inc.
+ * Padmarao Begari
+ * Naga Sureshkumar Relli
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * QSPI Control register mask defines
+ */
+#define CONTROL_ENABLE BIT(0)
+#define CONTROL_MASTER BIT(1)
+#define CONTROL_XIPBIT(2)
+#define CONTROL_XIPADDRBIT(3)
+#define CONTROL_CLKIDLEBIT(10)
+#define CONTROL_SAMPLE_MASKGENMASK(12, 11)
+#define CONTROL_MODE0 BIT(13)
+#define CONTROL_MODE12_MASKGENMASK(15, 14)
+#define CONTROL_MODE12_EX_RO BIT(14)
+#define CONTROL_MODE12_EX_RW BIT(15)
+#define CONTROL_MODE12_FULLGENMASK(15, 14)
+#define CONTROL_FLAGSX4BIT(16)
+#define CONTROL_CLKRATE_MASK GENMASK(27, 24)
+#define CONTROL_CLKRATE_SHIFT 24
+
+/*
+ * QSPI Frames register mask defines
+ */
+#define FRAMES_TOTALBYTES_MASK GENMASK(15, 0)
+#define FRAMES_CMDBYTES_MASK GENMASK(24, 16)
+#define FRAMES_CMDBYTES_SHIFT 16
+#define FRAMES_SHIFT 25
+#define FRAMES_IDLE_MASK GENMASK(29, 26)
+#define FRAMES_IDLE_SHIFT 26
+#define FRAMES_FLAGBYTEBIT(30)
+#define FRAMES_FLAGWORDBIT(31)
+
+/*
+ * QSPI Interrupt Enable register mask defines
+ */
+#define IEN_TXDONE BIT(0)
+#define IEN_RXDONE BIT(1)
+#define IEN_RXAVAILABLEBIT(2)
+#define IEN_TXAVAILABLEBIT(3)
+#define IEN_RXFIFOEMPTYBIT(4)
+#define IEN_TXFIFOFULL BIT(5)
+
+/*
+ * QSPI Status register mask defines
+ */
+#define STATUS_TXDONE BIT(0)
+#define STATUS_RXDONE BIT(1)
+#define STATUS_RXAVAILABLE BIT(2)
+#define STATUS_TXAVAILABLE BIT(3)
+#define STATUS_RXFIFOEMPTY BIT(4)
+#define STATUS_TXFIFOFULL BIT(5)
+#define STATUS_READY BIT(7)
+#define STATUS_FLAGSX4 BIT(8)
+#define STATUS_MASKGENMASK(8, 0)
+
+#define BYTESUPPER_MASKGENMASK(31, 16)
+#define BYTESLOWER_MASKGENMASK(15, 0)
+
+#define MAX_DIVIDER16
+#define MIN_DIVIDER0
+#define MAX_DATA_CMD_LEN 256
+
+/* QSPI ready time out value */
+#define TIMEOUT_MS (1000 * 60)
+
+/*
+ * QSPI Register offsets.
+ */
+#define REG_CONTROL(0x00)
+#define REG_FRAMES (0x04)
+#define REG_IEN(0x0c)
+#define REG_STATUS (0x10)
+#define REG_DIRECT_ACCESS (0x14)
+#define REG_UPPER_ACCESS (0x18)
+#define REG_RX_DATA(0x40)
+#define REG_TX_DATA(0x44)
+#define REG_X4_RX_DATA (0x48)
+#define REG_X4_TX_DATA (0x4c)
+#define REG_FRAMESUP (0x50)
+
+/**
+ * struct mchp_coreqspi - Defines qspi driver instance
+ * @regs: Address of the QSPI controller registers
+ * @freq: QSPI Input frequency
+ * @txbuf: TX buffer
+ * @rxbuf: RX buffer
+ * @tx_len:Number of bytes left to transfer
+ * @rx_len:Number of bytes left to receive
+ */
+struct mchp_coreqspi {
+ void __iomem *regs;
+
[PATCH v2 2/4] riscv: dts: Add QSPI NAND device node
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree.
The Winbond NAND flash memory can be connected to the
Icicle Kit by using the Mikroe Flash 5 click board and
the Pi 3 Click shield.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 876c475069..e1fbedc507 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -18,6 +18,7 @@
aliases {
serial1 =
ethernet0 =
+ spi0 =
};
chosen {
@@ -113,3 +114,17 @@
ti,fifo-depth = <0x1>;
};
};
+
+ {
+ status = "okay";
+ num-cs = <1>;
+ flash0: flash@0 {
+ compatible = "spi-nand";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <2000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
--
2.25.1
[PATCH v2 1/4] riscv: dts: Update memory configuration
In the v2022.10 Icicle reference design, the seg registers are going to be
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific context.
Co-developed-by: Conor Dooley
Signed-off-by: Conor Dooley
Signed-off-by: Padmarao Begari
Reviewed-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70
1 file changed, 14 insertions(+), 56 deletions(-)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 287ef3d23b..876c475069 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2021 Microchip Technology Inc.
+ * Copyright (C) 2021-2022 Microchip Technology Inc.
* Padmarao Begari
*/
@@ -28,70 +28,28 @@
timebase-frequency = ;
};
- reserved-memory {
- ranges;
- #size-cells = <2>;
- #address-cells = <2>;
-
- fabricbuf0: fabricbuf@0 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xae00 0x0 0x200>;
- label = "fabricbuf0-ddr-c";
- };
-
- fabricbuf1: fabricbuf@1 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xc000 0x0 0x800>;
- label = "fabricbuf1-ddr-nc";
- };
-
- fabricbuf2: fabricbuf@2 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xd800 0x0 0x800>;
- label = "fabricbuf2-ddr-nc-wcb";
- };
- };
-
- udmabuf0 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-c0";
- minor-number = <0>;
- size = <0x0 0x200>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
- udmabuf1 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc0";
- minor-number = <1>;
- size = <0x0 0x800>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
- udmabuf2 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc-wcb0";
- minor-number = <2>;
- size = <0x0 0x800>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
ddrc_cache_lo: memory@8000 {
device_type = "memory";
- reg = <0x0 0x8000 0x0 0x2e00>;
- clocks = < CLK_DDRC>;
+ reg = <0x0 0x8000 0x0 0x4000>;
status = "okay";
};
ddrc_cache_hi: memory@10 {
device_type = "memory";
- reg = <0x10 0x0 0x0 0x4000>;
- clocks = < CLK_DDRC>;
+ reg = <0x10 0x4000 0x0 0x4000>;
status = "okay";
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss_payload: region@BFC0 {
+ reg = <0x0 0xBFC0 0x0 0x40>;
+ no-map;
+ };
+ };
};
{
--
2.25.1
[PATCH v2 0/4] Update Microchip PolarFire SoC
This patch set updates Microchip PolarFire SoC Icicle Kit support of RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://source.denx.de/u-boot/u-boot) at commit id d843273a8022e70ccbdb6ad446b3335c3753e84f The memory device node is updated based on the latest FPGA reference design v2022.10 and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, add Microchip QSPI driver. Changes in v2: - Add Co-developed-by with patch - Replace spi-nand with flash in device node - Add board details for QSPI NAND - Rename QSPI driver file with microchip-coreqspi - Add microchip,coreqspi-rtl-v2 to the compatible list - Use MICROCHIP_COREQSPI instead of MICROCHIP_QSPI in kconfig Padmarao Begari (4): riscv: dts: Update memory configuration riscv: dts: Add QSPI NAND device node spi: Add Microchip PolarFire SoC QSPI driver riscv: Update Microchip MPFS Icicle Kit support arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 85 ++-- board/microchip/mpfs_icicle/Kconfig | 7 + configs/microchip_mpfs_icicle_defconfig | 1 + drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/microchip_coreqspi.c | 505 +++ 6 files changed, 549 insertions(+), 56 deletions(-) create mode 100644 drivers/spi/microchip_coreqspi.c -- 2.25.1
[PATCH 4/4] spi: Add Microchip PolarFire SoC QSPI driver
Add QSPI driver code for the Microchip PolarFire SoC.
This driver supports the qspi standard, dual and quad
mode interfaces.
Signed-off-by: Padmarao Begari
Signed-off-by: Naga Sureshkumar Relli
---
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/microchip_qspi.c | 504 +++
3 files changed, 511 insertions(+)
create mode 100644 drivers/spi/microchip_qspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2f12081f88..690306309a 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -237,6 +237,12 @@ config MESON_SPIFC
This driver can be used to access the SPI NOR flash chips on
Amlogic Meson SoCs.
+config MICROCHIP_QSPI
+ bool "Microchip Quad SPI driver"
+ help
+ Enable the Microchip Quad SPI controller driver. This driver can be
+ used on Polarfire SoCs.
+
config MPC8XX_SPI
bool "MPC8XX SPI Driver"
depends on MPC8xx
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 50ba43550b..010855ae1d 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -40,6 +40,7 @@ obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
+obj-$(CONFIG_MICROCHIP_QSPI) += microchip_qspi.o
obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MTK_SNFI_SPI) += mtk_snfi_spi.o
diff --git a/drivers/spi/microchip_qspi.c b/drivers/spi/microchip_qspi.c
new file mode 100644
index 00..2c803f6d2f
--- /dev/null
+++ b/drivers/spi/microchip_qspi.c
@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Microchip Technology Inc.
+ * Padmarao Begari
+ * Naga Sureshkumar Relli
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * QSPI Control register mask defines
+ */
+#define CONTROL_ENABLE BIT(0)
+#define CONTROL_MASTER BIT(1)
+#define CONTROL_XIPBIT(2)
+#define CONTROL_XIPADDRBIT(3)
+#define CONTROL_CLKIDLEBIT(10)
+#define CONTROL_SAMPLE_MASKGENMASK(12, 11)
+#define CONTROL_MODE0 BIT(13)
+#define CONTROL_MODE12_MASKGENMASK(15, 14)
+#define CONTROL_MODE12_EX_RO BIT(14)
+#define CONTROL_MODE12_EX_RW BIT(15)
+#define CONTROL_MODE12_FULLGENMASK(15, 14)
+#define CONTROL_FLAGSX4BIT(16)
+#define CONTROL_CLKRATE_MASK GENMASK(27, 24)
+#define CONTROL_CLKRATE_SHIFT 24
+
+/*
+ * QSPI Frames register mask defines
+ */
+#define FRAMES_TOTALBYTES_MASK GENMASK(15, 0)
+#define FRAMES_CMDBYTES_MASK GENMASK(24, 16)
+#define FRAMES_CMDBYTES_SHIFT 16
+#define FRAMES_SHIFT 25
+#define FRAMES_IDLE_MASK GENMASK(29, 26)
+#define FRAMES_IDLE_SHIFT 26
+#define FRAMES_FLAGBYTEBIT(30)
+#define FRAMES_FLAGWORDBIT(31)
+
+/*
+ * QSPI Interrupt Enable register mask defines
+ */
+#define IEN_TXDONE BIT(0)
+#define IEN_RXDONE BIT(1)
+#define IEN_RXAVAILABLEBIT(2)
+#define IEN_TXAVAILABLEBIT(3)
+#define IEN_RXFIFOEMPTYBIT(4)
+#define IEN_TXFIFOFULL BIT(5)
+
+/*
+ * QSPI Status register mask defines
+ */
+#define STATUS_TXDONE BIT(0)
+#define STATUS_RXDONE BIT(1)
+#define STATUS_RXAVAILABLE BIT(2)
+#define STATUS_TXAVAILABLE BIT(3)
+#define STATUS_RXFIFOEMPTY BIT(4)
+#define STATUS_TXFIFOFULL BIT(5)
+#define STATUS_READY BIT(7)
+#define STATUS_FLAGSX4 BIT(8)
+#define STATUS_MASKGENMASK(8, 0)
+
+#define BYTESUPPER_MASKGENMASK(31, 16)
+#define BYTESLOWER_MASKGENMASK(15, 0)
+
+#define MAX_DIVIDER16
+#define MIN_DIVIDER0
+#define MAX_DATA_CMD_LEN 256
+
+/* QSPI ready time out value */
+#define TIMEOUT_MS (1000 * 60)
+
+/*
+ * QSPI Register offsets.
+ */
+#define REG_CONTROL(0x00)
+#define REG_FRAMES (0x04)
+#define REG_IEN(0x0c)
+#define REG_STATUS (0x10)
+#define REG_DIRECT_ACCESS (0x14)
+#define REG_UPPER_ACCESS (0x18)
+#define REG_RX_DATA(0x40)
+#define REG_TX_DATA(0x44)
+#define REG_X4_RX_DATA (0x48)
+#define REG_X4_TX_DATA (0x4c)
+#define REG_FRAMESUP (0x50)
+
+/**
+ * struct mchp_coreqspi - Defines qspi driver instance
+ * @regs: Address of the QSPI controller registers
+ * @freq: QSPI Input frequency
+ * @txbuf: TX buffer
+ * @rxbuf: RX buffer
+ * @tx_len:Number of bytes left to transfer
+ * @rx_len:Number of bytes left to receive
+ */
+struct mchp_coreqspi {
+ void __iomem *regs;
+ u32 freq;
+ u8 *txbuf;
+ u8 *rxbuf;
+ int tx_len;
+ int rx_len
[PATCH 3/4] riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now, add Microchip QSPI driver and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use. Signed-off-by: Padmarao Begari --- board/microchip/mpfs_icicle/Kconfig | 7 +++ configs/microchip_mpfs_icicle_defconfig | 1 + 2 files changed, 8 insertions(+) diff --git a/board/microchip/mpfs_icicle/Kconfig b/board/microchip/mpfs_icicle/Kconfig index 092e411215..230f96b033 100644 --- a/board/microchip/mpfs_icicle/Kconfig +++ b/board/microchip/mpfs_icicle/Kconfig @@ -50,5 +50,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_I2C imply DM_I2C imply SYS_I2C_MICROCHIP + imply SPI + imply DM_SPI + imply MICROCHIP_QSPI + imply MTD_SPI_NAND + imply CMD_MTD + imply MTD_PARTITIONS + imply CMD_MTDPARTS endif diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index 6113c5be80..c295b9bad3 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -17,6 +17,7 @@ CONFIG_DISPLAY_BOARDINFO=y CONFIG_SYS_CBSIZE=256 CONFIG_SYS_PBSIZE=282 CONFIG_SYS_BOOTM_LEN=0x400 +CONFIG_SYS_MEM_TOP_HIDE=0x40 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DM_MTD=y -- 2.25.1
[PATCH 2/4] riscv: dts: Add QSPI NAND device node
Add QSPI NAND device node to the Microchip PolarFire SoC
Icicle kit device tree
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 876c475069..679221e13f 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -18,6 +18,7 @@
aliases {
serial1 =
ethernet0 =
+ spi0 =
};
chosen {
@@ -113,3 +114,17 @@
ti,fifo-depth = <0x1>;
};
};
+
+ {
+ status = "okay";
+ num-cs = <1>;
+ flash0: spi-nand@0 {
+ compatible = "spi-nand";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <2000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
--
2.25.1
[PATCH 1/4] riscv: dts: update memory configuration
In the v2022.10 Icicle reference design, the seg registers are going to be
changed, resulting in a required change to the memory map.
A small 4MB reservation is made at the end of 32-bit DDR to provide some
memory for the HSS to use, so that it can cache its payload between
reboots of a specific context.
Signed-off-by: Padmarao Begari
Signed-off-by: Conor Dooley
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70
1 file changed, 14 insertions(+), 56 deletions(-)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 287ef3d23b..876c475069 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2021 Microchip Technology Inc.
+ * Copyright (C) 2021-2022 Microchip Technology Inc.
* Padmarao Begari
*/
@@ -28,70 +28,28 @@
timebase-frequency = ;
};
- reserved-memory {
- ranges;
- #size-cells = <2>;
- #address-cells = <2>;
-
- fabricbuf0: fabricbuf@0 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xae00 0x0 0x200>;
- label = "fabricbuf0-ddr-c";
- };
-
- fabricbuf1: fabricbuf@1 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xc000 0x0 0x800>;
- label = "fabricbuf1-ddr-nc";
- };
-
- fabricbuf2: fabricbuf@2 {
- compatible = "shared-dma-pool";
- reg = <0x0 0xd800 0x0 0x800>;
- label = "fabricbuf2-ddr-nc-wcb";
- };
- };
-
- udmabuf0 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-c0";
- minor-number = <0>;
- size = <0x0 0x200>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
- udmabuf1 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc0";
- minor-number = <1>;
- size = <0x0 0x800>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
- udmabuf2 {
- compatible = "ikwzm,u-dma-buf";
- device-name = "udmabuf-ddr-nc-wcb0";
- minor-number = <2>;
- size = <0x0 0x800>;
- memory-region = <>;
- sync-mode = <3>;
- };
-
ddrc_cache_lo: memory@8000 {
device_type = "memory";
- reg = <0x0 0x8000 0x0 0x2e00>;
- clocks = < CLK_DDRC>;
+ reg = <0x0 0x8000 0x0 0x4000>;
status = "okay";
};
ddrc_cache_hi: memory@10 {
device_type = "memory";
- reg = <0x10 0x0 0x0 0x4000>;
- clocks = < CLK_DDRC>;
+ reg = <0x10 0x4000 0x0 0x4000>;
status = "okay";
};
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hss_payload: region@BFC0 {
+ reg = <0x0 0xBFC0 0x0 0x40>;
+ no-map;
+ };
+ };
};
{
--
2.25.1
[PATCH 0/4] Update Microchip PolarFire SoC
This patch set updates Microchip PolarFire SoC Icicle Kit support of RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://source.denx.de/u-boot/u-boot) at commit id 3724ddf157aab3bd009c1da234b9a1af1621b544 The memory device node is updated in the device tree based on the latest FPGA reference design and a small 4MB reservation is made at the end of 32-bit DDR to provide some memory for the HSS to use, add Microchip QSPI driver. Padmarao Begari (4): riscv: dts: update memory configuration riscv: dts: Add QSPI NAND device node riscv: Update Microchip MPFS Icicle Kit support spi: Add Microchip PolarFire SoC QSPI driver arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 85 ++-- board/microchip/mpfs_icicle/Kconfig | 7 + configs/microchip_mpfs_icicle_defconfig | 1 + drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/microchip_qspi.c | 504 +++ 6 files changed, 548 insertions(+), 56 deletions(-) create mode 100644 drivers/spi/microchip_qspi.c -- 2.25.1
Re: [PATCH v1 4/5] net: macb: Compatible as per device tree
Hi Bin, On Fri, Nov 12, 2021 at 6:58 AM Bin Meng wrote: > On Thu, Nov 11, 2021 at 9:17 PM wrote: > > > > > I agree with Bin here. You shouldn't introduce a new compatible just > for > > > u-boot. If you need one, please to it first in linux and get an ACK > there. > > > Or at least there should be patches for it pending in linux and it > should > > > be likely, that they will be accepted. > > > > > > Please work towards having one binding for u-boot and linux. > > > > > > -michael > > > > I think both Michael and Bin are right, but that maybe this has gone > circular. > > > > IIRC, Linux *doesn't need* any extra bindings because its driver already > > supports 64-bit DMA. > > > > Padmarao's original patch added equivalent 64-bit functionality to the > > driver in U-Boot, but this was rejected. > > > > I am not sure why it was rejected. Is that because it breaks some > other platforms? > > No > > Instead I think the suggestion was to add a device-tree binding to > choose 32 or > > 64-bit DMA... however, there is no reasonably way of upstreaming this > into > > the Linux device-tree, as Linux doesn't need it... so he is left in a > Catch-22. > > > > A way forward may be to go back to his original approach and get the > U-Boot > > driver functionality updated so that it works similarly to the Linux > driver > > (and thus can use the same device-tree stanza)? > > Let's go back to the original approach and see what happens. > > Ok, I will do that and submit it in Patch v2. Regards Padmarao > Regards, > Bin >
Re: [PATCH v1 4/5] net: macb: Compatible as per device tree
Hi Bin, On Thu, Nov 11, 2021 at 1:37 PM Bin Meng wrote: > Hi Padmarao, > > On Thu, Nov 11, 2021 at 2:11 PM wrote: > > > > Hi Bin, > > > > > > > > Do we need to upstream Linux kernel bindings for Microchip MACB > compatible if there is no change in Linux MACB driver? > > > > Are the Linux maintainers can approve this? Because the changes only in > U-Boot not Linux. > > > > If Linux driver does not need to be updated to support MPFS macb using > existing compatible string but U-Boot driver has to, something is > wrong on the U-Boot macb driver side. > > Would you please reconsider the whole changes? > > We submitted patches(v1, v2) last year for the U-Boot MACB update for 64-bit DMA access same like Linux MACB driver using "#ifdef CONFIG_DMA_ADDR_T_64BIT" but one of the reviewer wanted to check 64-bit DMA support at runtime instead of #ifdef and we updated the macb driver based on the design config debug6 register of MACB hardware which supports 32-bit or 64-bit DMA in patch(v3) but the SiFive FU540 MACB didn't work then the reviewer suggested use compatible string instead of design config register and updated same in patch(v4), these changes were tested and acknowledged them at Patch v6. Below links for patch submitted for "net: macb: Add DMA 64-bit address support for macb" https://www.mail-archive.com/u-boot@lists.denx.de/msg387528.html - Patch v2 https://www.mail-archive.com/u-boot@lists.denx.de/msg389490.html - Patch v3 https://www.mail-archive.com/u-boot@lists.denx.de/msg390611.html - Patch v4 https://www.mail-archive.com/u-boot@lists.denx.de/msg391001.html - Patch v5 https://www.mail-archive.com/u-boot@lists.denx.de/msg391850.html - Patch v6 Regards Padmarao Regards, > Bin >
Re: [PATCH v1 4/5] net: macb: Compatible as per device tree
Hi Bin,
On Wed, Nov 3, 2021 at 5:17 PM Padmarao Begari wrote:
> Hi Bin,
>
> On Tue, Nov 2, 2021 at 6:16 PM Bin Meng wrote:
>
>> Hi Padmarao,
>>
>> On Tue, Nov 2, 2021 at 7:03 PM Padmarao Begari
>> wrote:
>> >
>> > Hi Bin,
>> >
>> > On Mon, Nov 1, 2021 at 2:15 PM Bin Meng wrote:
>> >>
>> >> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
>> >> wrote:
>> >> >
>> >> > Update compatible as per Microchip PolarFire SoC ethernet
>> >> > device node.
>> >> >
>> >> > Signed-off-by: Padmarao Begari
>> >> > ---
>> >> > drivers/net/macb.c | 2 +-
>> >> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >> >
>> >> > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
>> >> > index 8c6461e717..1b867bd5c2 100644
>> >> > --- a/drivers/net/macb.c
>> >> > +++ b/drivers/net/macb.c
>> >> > @@ -1502,7 +1502,7 @@ static const struct udevice_id macb_eth_ids[]
>> = {
>> >> > { .compatible = "cdns,zynq-gem" },
>> >> > { .compatible = "sifive,fu540-c000-gem",
>> >> > .data = (ulong)_config },
>> >> > - { .compatible = "microchip,mpfs-mss-gem",
>> >> > + { .compatible = "microchip,mpfs-gem",
>> >>
>> >> Could you please provide the upstream Linux kernel binding reference?
>> >> I can't find such string in the Linux kernel.
>> >>
>> >
>> > We are not upstreamed Linux bindings yet, soon we will do.
>> >
>> > The compatible "cdns,macb" is used in Linux for 32-bit and 64-bit DMA
>> transfer and U-Boot for 32-bit DMA transfer.
>> > We added this string to support 64-bit DMA transfer of the GEM.
>> >
>>
>> I suggest we upstream the new compatible string binding first, then
>> update U-Boot. Otherwise U-Boot might be updated again if the
>> compatible string is changed during the upstream review process.
>>
>>
> We are going to use the same compatible strings in the U-Boot and Linux
> for PolarFire SoC peripherals like "microchip,mpfs-xxx" (xxx means
> peripheral name, ex. "microchip,mpfs-i2c", "microchip,mpfs-rtc"etc).
> Here, we are updating compatible(existing) "microchip,mpfs-mss-gem" with
> "microchip,mpfs-gem".
>
>
The U-Boot MACB driver code updated to support 64-bit DMA access using the
compatible string "microchip,mpfs-mss-gem" last time and the compatible
string "microchip,mpfs-mss-gem" is only for U-Boot for 64-bit DMA access of
MACB not for Linux, the Linux works fine with compatible string
"cdns,macb" and there is no change in the driver code.
Still do we need to upstream Linux kernel bindings for this?
Regards
Padmarao
> Regards,
>> Bin
>>
>
Re: [PATCH v1 4/5] net: macb: Compatible as per device tree
Hi Bin,
On Tue, Nov 2, 2021 at 6:16 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Tue, Nov 2, 2021 at 7:03 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Mon, Nov 1, 2021 at 2:15 PM Bin Meng wrote:
> >>
> >> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
> >> wrote:
> >> >
> >> > Update compatible as per Microchip PolarFire SoC ethernet
> >> > device node.
> >> >
> >> > Signed-off-by: Padmarao Begari
> >> > ---
> >> > drivers/net/macb.c | 2 +-
> >> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >> >
> >> > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> >> > index 8c6461e717..1b867bd5c2 100644
> >> > --- a/drivers/net/macb.c
> >> > +++ b/drivers/net/macb.c
> >> > @@ -1502,7 +1502,7 @@ static const struct udevice_id macb_eth_ids[] =
> {
> >> > { .compatible = "cdns,zynq-gem" },
> >> > { .compatible = "sifive,fu540-c000-gem",
> >> > .data = (ulong)_config },
> >> > - { .compatible = "microchip,mpfs-mss-gem",
> >> > + { .compatible = "microchip,mpfs-gem",
> >>
> >> Could you please provide the upstream Linux kernel binding reference?
> >> I can't find such string in the Linux kernel.
> >>
> >
> > We are not upstreamed Linux bindings yet, soon we will do.
> >
> > The compatible "cdns,macb" is used in Linux for 32-bit and 64-bit DMA
> transfer and U-Boot for 32-bit DMA transfer.
> > We added this string to support 64-bit DMA transfer of the GEM.
> >
>
> I suggest we upstream the new compatible string binding first, then
> update U-Boot. Otherwise U-Boot might be updated again if the
> compatible string is changed during the upstream review process.
>
>
We are going to use the same compatible strings in the U-Boot and Linux for
PolarFire SoC peripherals like "microchip,mpfs-xxx" (xxx means peripheral
name, ex. "microchip,mpfs-i2c", "microchip,mpfs-rtc"etc).
Here, we are updating compatible(existing) "microchip,mpfs-mss-gem" with
"microchip,mpfs-gem".
Regards,
> Bin
>
Re: [PATCH v1 5/5] doc: board: Update Microchip MPFS Icicle Kit doc
Hi Bin, On Mon, Nov 1, 2021 at 2:16 PM Bin Meng wrote: > On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari > wrote: > > > > UART1 uses for U-BOOT and Linux console instead of UART0 and > > nits: s/U-BOOT/U-Boot > > ok > > UART0 is reserved for Hart Software Services(HSS). > > > > Signed-off-by: Padmarao Begari > > --- > > doc/board/microchip/mpfs_icicle.rst | 11 +++ > > 1 file changed, 7 insertions(+), 4 deletions(-) > > > > diff --git a/doc/board/microchip/mpfs_icicle.rst > b/doc/board/microchip/mpfs_icicle.rst > > index c71c2f3cab..d7af542c0e 100644 > > --- a/doc/board/microchip/mpfs_icicle.rst > > +++ b/doc/board/microchip/mpfs_icicle.rst > > @@ -18,8 +18,9 @@ The support for following drivers are already enabled: > > > > 1. NS16550 UART Driver. > > 2. Microchip Clock Driver. > > -3. Cadence MACB ethernet driver for networking support. > > -4. Cadence MMC Driver for eMMC/SD support. > > +3. Microchip I2C Driver. > > nits: can we just insert this after the existing entries? > > ok Regards Padmarao > > +4. Cadence MACB ethernet driver for networking support. > > +5. Cadence MMC Driver for eMMC/SD support. > > > > Booting from eMMC using HSS > > --- > > @@ -214,7 +215,8 @@ GPT partition. > > Booting > > ~~~ > > > > -You should see the U-Boot prompt on UART0. > > +You should see the U-Boot prompt on UART1. > > +(Note: UART0 is reserved for HSS) > > > > Sample boot log from MPFS Icicle Kit > > > > @@ -451,7 +453,8 @@ copied payload and Linux image. > > > > sudo dd if= of=/dev/sdX2 bs=512 > > > > -You should see the U-Boot prompt on UART0. > > +You should see the U-Boot prompt on UART1. > > +(Note: UART0 is reserved for HSS) > > > > GUID type > > ~ > > Otherwise, > Reviewed-by: Bin Meng > > Regards, > Bin >
Re: [PATCH v1 4/5] net: macb: Compatible as per device tree
Hi Bin,
On Mon, Nov 1, 2021 at 2:15 PM Bin Meng wrote:
> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
> wrote:
> >
> > Update compatible as per Microchip PolarFire SoC ethernet
> > device node.
> >
> > Signed-off-by: Padmarao Begari
> > ---
> > drivers/net/macb.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> > index 8c6461e717..1b867bd5c2 100644
> > --- a/drivers/net/macb.c
> > +++ b/drivers/net/macb.c
> > @@ -1502,7 +1502,7 @@ static const struct udevice_id macb_eth_ids[] = {
> > { .compatible = "cdns,zynq-gem" },
> > { .compatible = "sifive,fu540-c000-gem",
> > .data = (ulong)_config },
> > - { .compatible = "microchip,mpfs-mss-gem",
> > + { .compatible = "microchip,mpfs-gem",
>
> Could you please provide the upstream Linux kernel binding reference?
> I can't find such string in the Linux kernel.
>
>
We are not upstreamed Linux bindings yet, soon we will do.
The compatible "cdns,macb" is used in Linux for 32-bit and 64-bit DMA
transfer and U-Boot for 32-bit DMA transfer.
We added this string to support 64-bit DMA transfer of the GEM.
Regards
Padmarao
> > .data = (ulong)_config },
> > { }
> > };
>
> Regards,
> Bin
>
Re: [PATCH v1 2/5] riscv: Update Microchip MPFS Icicle Kit support
On Mon, Nov 1, 2021 at 2:13 PM Bin Meng wrote:
> On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari
> wrote:
> >
> > This patch updates Microchip MPFS Icicle Kit support. For now,
> > add Microchip I2C driver, set environment variables for
> > mac addesses and default build for SBI_V02.
> >
> > Signed-off-by: Padmarao Begari
> > ---
> > board/microchip/mpfs_icicle/Kconfig | 5 +
> > board/microchip/mpfs_icicle/mpfs_icicle.c | 17 -
> > configs/microchip_mpfs_icicle_defconfig | 1 -
> > 3 files changed, 21 insertions(+), 2 deletions(-)
> >
> > diff --git a/board/microchip/mpfs_icicle/Kconfig
> b/board/microchip/mpfs_icicle/Kconfig
> > index 4678462378..092e411215 100644
> > --- a/board/microchip/mpfs_icicle/Kconfig
> > +++ b/board/microchip/mpfs_icicle/Kconfig
> > @@ -45,5 +45,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > imply MMC_WRITE
> > imply MMC_SDHCI
> > imply MMC_SDHCI_CADENCE
> > + imply MMC_SDHCI_ADMA
> > + imply MMC_HS200_SUPPORT
> > + imply CMD_I2C
> > + imply DM_I2C
> > + imply SYS_I2C_MICROCHIP
> >
> > endif
> > diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
> b/board/microchip/mpfs_icicle/mpfs_icicle.c
> > index afef719dff..e74c9fb03c 100644
> > --- a/board/microchip/mpfs_icicle/mpfs_icicle.c
> > +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
> > @@ -119,7 +119,22 @@ int board_late_init(void)
> > if (icicle_mac_addr[idx] == ':')
> > icicle_mac_addr[idx] = ' ';
> > }
> > - env_set("icicle_mac_addr", icicle_mac_addr);
> > + env_set("icicle_mac_addr0", icicle_mac_addr);
>
> What's this environment for? Shouldn't the U-Boot standard environment
> variable "ethaddr" be set here?
>
>
The "icicle_mac_addr0" and "icicle_mac_addr1" environment variables are
used for updating the mac
addresses(mac0 and mac1) in the FIT image using fdt overlays like below.
fdt addr ${fdt_addr_r}
fdt set /soc/ethernet@20112000 local-mac-address ${icicle_mac_addr0}
fdt set /soc/ethernet@2011 local-mac-address ${icicle_mac_addr1}
The "ethaddr" variable comes in the U-Boot like "00:04:a3:d6:45:94" but we
want "[00 04 a3 d6 45 94]" to update the mac address in the FIT Image.
>
> > +
> > + mac_addr[5] = device_serial_number[0] + 1;
> > +
> > + icicle_mac_addr[0] = '[';
> > +
> > + sprintf(_mac_addr[1], "%pM", mac_addr);
>
> "eth1addr"?
>
>
No, a second mac address environment variable "icicle_mac_addr1".
only one MAC address is used in the U-Boot and two MAC's in the Linux.
> > +
> > + icicle_mac_addr[18] = ']';
> > + icicle_mac_addr[19] = '\0';
> > +
> > + for (idx = 0; idx < 20; idx++) {
> > + if (icicle_mac_addr[idx] == ':')
> > + icicle_mac_addr[idx] = ' ';
> > + }
> > + env_set("icicle_mac_addr1", icicle_mac_addr);
> >
> > return 0;
> > }
> > diff --git a/configs/microchip_mpfs_icicle_defconfig
> b/configs/microchip_mpfs_icicle_defconfig
> > index 90ae76cc12..b3c7e6db8f 100644
> > --- a/configs/microchip_mpfs_icicle_defconfig
> > +++ b/configs/microchip_mpfs_icicle_defconfig
> > @@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
> > CONFIG_TARGET_MICROCHIP_ICICLE=y
> > CONFIG_ARCH_RV64I=y
> > CONFIG_RISCV_SMODE=y
> > -CONFIG_SBI_V01=y
> > CONFIG_DISTRO_DEFAULTS=y
> > CONFIG_SYS_LOAD_ADDR=0x8020
> > CONFIG_FIT=y
> > --
>
> Regards,
> Bin
>
Re: [PATCH v1 1/5] riscv: dts: Split Microchip device tree
Hi Bin, On Mon, Nov 1, 2021 at 2:11 PM Bin Meng wrote: > Hi Padmarao, > > On Fri, Oct 22, 2021 at 4:58 PM Padmarao Begari > wrote: > > > > The device tree split into .dtsi and .dts files, common > > device node for eMMC/SD, enable I2C1, UART1 for console > > instead of UART0, enable the DDR 2GB memory and in > > that 288MB memory is reserved for fabric buffer. > > > > Signed-off-by: Padmarao Begari > > --- > > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 > > arch/riscv/dts/microchip-mpfs.dtsi| 571 ++ > > .../microchip-mpfs-plic.h | 195 ++ > > .../interrupt-controller/riscv-hart.h | 18 + > > 4 files changed, 913 insertions(+), 389 deletions(-) > > create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi > > create mode 100644 > include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h > > create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h > > Are these files sync'ed from upstream Linux kernel? > > No, We are going to submit these files to the upstream Linux kernel very soon. Regards Padmarao > > > > [snip] > > Regards, > Bin >
[PATCH v1 3/5] i2c: Add Microchip PolarFire SoC I2C driver
Add I2C driver code for the Microchip PolarFire SoC. This driver supports I2C data transfer and probe for I2C slave addresses. Signed-off-by: Padmarao Begari --- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile| 1 + drivers/i2c/i2c-microchip.c | 482 3 files changed, 489 insertions(+) create mode 100644 drivers/i2c/i2c-microchip.c diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 7c447a8aa0..5482a4a470 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -250,6 +250,12 @@ config SYS_I2C_MESON internal buffer holding up to 8 bytes for transfers and supports both 7-bit and 10-bit addresses. +config SYS_I2C_MICROCHIP + bool "Microchip I2C driver" + help + Add support for the Microchip I2C driver. This is operating on + standard mode up to 100 kbits/s and fast mode up to 400 kbits/s. + config SYS_I2C_MXC bool "NXP MXC I2C driver" help diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index fca6b157f8..9d41f379bb 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o obj-$(CONFIG_SYS_I2C_MESON) += meson_i2c.o +obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o obj-$(CONFIG_SYS_I2C_MV) += mv_i2c.o obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o diff --git a/drivers/i2c/i2c-microchip.c b/drivers/i2c/i2c-microchip.c new file mode 100644 index 00..12f65d0af7 --- /dev/null +++ b/drivers/i2c/i2c-microchip.c @@ -0,0 +1,482 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Microchip I2C controller driver + * + * Copyright (C) 2021 Microchip Technology Inc. + * Padmarao Begari + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#defineMICROCHIP_I2C_TIMEOUT (1000 * 60) + +#define MPFS_I2C_CTRL (0x00) +#defineCTRL_CR0(0x00) +#defineCTRL_CR1(0x01) +#defineCTRL_AA BIT(2) +#defineCTRL_SI BIT(3) +#defineCTRL_STOBIT(4) +#defineCTRL_STABIT(5) +#defineCTRL_ENS1 BIT(6) +#defineCTRL_CR2(0x07) +#define MPFS_I2C_STATUS (0x04) +#defineSTATUS_BUS_ERROR (0x00) +#defineSTATUS_M_START_SENT (0x08) +#defineSTATUS_M_REPEATED_START_SENT(0x10) +#defineSTATUS_M_SLAW_ACK (0x18) +#defineSTATUS_M_SLAW_NACK (0x20) +#defineSTATUS_M_TX_DATA_ACK(0x28) +#defineSTATUS_M_TX_DATA_NACK (0x30) +#defineSTATUS_M_ARB_LOST (0x38) +#defineSTATUS_M_SLAR_ACK (0x40) +#defineSTATUS_M_SLAR_NACK (0x48) +#defineSTATUS_M_RX_DATA_ACKED (0x50) +#defineSTATUS_M_RX_DATA_NACKED (0x58) +#defineSTATUS_S_SLAW_ACKED (0x60) +#defineSTATUS_S_ARB_LOST_SLAW_ACKED(0x68) +#defineSTATUS_S_GENERAL_CALL_ACKED (0x70) +#defineSTATUS_S_ARB_LOST_GENERAL_CALL_ACKED(0x78) +#defineSTATUS_S_RX_DATA_ACKED (0x80) +#defineSTATUS_S_RX_DATA_NACKED (0x88) +#defineSTATUS_S_GENERAL_CALL_RX_DATA_ACKED (0x90) +#defineSTATUS_S_GENERAL_CALL_RX_DATA_NACKED(0x98) +#defineSTATUS_S_RX_STOP (0xA0) +#defineSTATUS_S_SLAR_ACKED (0xA8) +#defineSTATUS_S_ARB_LOST_SLAR_ACKED(0xB0) +#defineSTATUS_S_TX_DATA_ACK(0xb8) +#defineSTATUS_S_TX_DATA_NACK (0xC0) +#defineSTATUS_LAST_DATA_ACK(0xC8) +#defineSTATUS_M_SMB_MASTER_RESET (0xD0) +#defineSTATUS_S_SCL_LOW_TIMEOUT(0xD8) +#defineSTATUS_NO_STATE_INFO(0xF8) +#define MPFS_I2C_DATA (0x08) +#define MPFS_I2C_SLAVE0_ADDR (0x0c) +#define MPFS_I2C_SMBUS (0x10) +#define MPFS_I2C_FREQ
[PATCH v1 1/5] riscv: dts: Split Microchip device tree
The device tree split into .dtsi and .dts files, common
device node for eMMC/SD, enable I2C1, UART1 for console
instead of UART0, enable the DDR 2GB memory and in
that 288MB memory is reserved for fabric buffer.
Signed-off-by: Padmarao Begari
---
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518
arch/riscv/dts/microchip-mpfs.dtsi| 571 ++
.../microchip-mpfs-plic.h | 195 ++
.../interrupt-controller/riscv-hart.h | 18 +
4 files changed, 913 insertions(+), 389 deletions(-)
create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi
create mode 100644
include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index 89c4cf5fb2..287ef3d23b 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -1,417 +1,157 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Microchip Technology Inc.
+ * Padmarao Begari
+ */
/dts-v1/;
-#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+#include "microchip-mpfs.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ100
/ {
- #address-cells = <2>;
- #size-cells = <2>;
- model = "Microchip MPFS Icicle Kit";
- compatible = "microchip,mpfs-icicle-kit";
+ model = "Microchip PolarFire-SoC Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- serial0 =
- ethernet0 =
+ serial1 =
+ ethernet0 =
};
chosen {
- stdout-path = "serial0";
+ stdout-path = "serial1";
};
- cpucomplex: cpus {
- #address-cells = <1>;
- #size-cells = <0>;
+ cpus {
timebase-frequency = ;
- cpu0: cpu@0 {
- clocks = < CLK_CPU>;
- compatible = "sifive,e51", "sifive,rocket0", "riscv";
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <128>;
- i-cache-size = <16384>;
- reg = <0>;
- riscv,isa = "rv64imac";
- status = "disabled";
- operating-points = <
- /* kHz uV */
- 60 110
- 30 95
- 15 75
- >;
- cpu0intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu1: cpu@1 {
- clocks = < CLK_CPU>;
- compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- reg = <1>;
- riscv,isa = "rv64imafdc";
- tlb-split;
- status = "okay";
- operating-points = <
- /* kHz uV */
- 60 110
- 30 95
- 15 75
- >;
- cpu1intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu2: cpu@2 {
-
[PATCH v1 4/5] net: macb: Compatible as per device tree
Update compatible as per Microchip PolarFire SoC ethernet
device node.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 8c6461e717..1b867bd5c2 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -1502,7 +1502,7 @@ static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,zynq-gem" },
{ .compatible = "sifive,fu540-c000-gem",
.data = (ulong)_config },
- { .compatible = "microchip,mpfs-mss-gem",
+ { .compatible = "microchip,mpfs-gem",
.data = (ulong)_config },
{ }
};
--
2.25.1
[PATCH v1 2/5] riscv: Update Microchip MPFS Icicle Kit support
This patch updates Microchip MPFS Icicle Kit support. For now,
add Microchip I2C driver, set environment variables for
mac addesses and default build for SBI_V02.
Signed-off-by: Padmarao Begari
---
board/microchip/mpfs_icicle/Kconfig | 5 +
board/microchip/mpfs_icicle/mpfs_icicle.c | 17 -
configs/microchip_mpfs_icicle_defconfig | 1 -
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index 4678462378..092e411215 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -45,5 +45,10 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply MMC_WRITE
imply MMC_SDHCI
imply MMC_SDHCI_CADENCE
+ imply MMC_SDHCI_ADMA
+ imply MMC_HS200_SUPPORT
+ imply CMD_I2C
+ imply DM_I2C
+ imply SYS_I2C_MICROCHIP
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index afef719dff..e74c9fb03c 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -119,7 +119,22 @@ int board_late_init(void)
if (icicle_mac_addr[idx] == ':')
icicle_mac_addr[idx] = ' ';
}
- env_set("icicle_mac_addr", icicle_mac_addr);
+ env_set("icicle_mac_addr0", icicle_mac_addr);
+
+ mac_addr[5] = device_serial_number[0] + 1;
+
+ icicle_mac_addr[0] = '[';
+
+ sprintf(_mac_addr[1], "%pM", mac_addr);
+
+ icicle_mac_addr[18] = ']';
+ icicle_mac_addr[19] = '\0';
+
+ for (idx = 0; idx < 20; idx++) {
+ if (icicle_mac_addr[idx] == ':')
+ icicle_mac_addr[idx] = ' ';
+ }
+ env_set("icicle_mac_addr1", icicle_mac_addr);
return 0;
}
diff --git a/configs/microchip_mpfs_icicle_defconfig
b/configs/microchip_mpfs_icicle_defconfig
index 90ae76cc12..b3c7e6db8f 100644
--- a/configs/microchip_mpfs_icicle_defconfig
+++ b/configs/microchip_mpfs_icicle_defconfig
@@ -6,7 +6,6 @@ CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
CONFIG_TARGET_MICROCHIP_ICICLE=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
-CONFIG_SBI_V01=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x8020
CONFIG_FIT=y
--
2.25.1
[PATCH v1 5/5] doc: board: Update Microchip MPFS Icicle Kit doc
UART1 uses for U-BOOT and Linux console instead of UART0 and UART0 is reserved for Hart Software Services(HSS). Signed-off-by: Padmarao Begari --- doc/board/microchip/mpfs_icicle.rst | 11 +++ 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/doc/board/microchip/mpfs_icicle.rst b/doc/board/microchip/mpfs_icicle.rst index c71c2f3cab..d7af542c0e 100644 --- a/doc/board/microchip/mpfs_icicle.rst +++ b/doc/board/microchip/mpfs_icicle.rst @@ -18,8 +18,9 @@ The support for following drivers are already enabled: 1. NS16550 UART Driver. 2. Microchip Clock Driver. -3. Cadence MACB ethernet driver for networking support. -4. Cadence MMC Driver for eMMC/SD support. +3. Microchip I2C Driver. +4. Cadence MACB ethernet driver for networking support. +5. Cadence MMC Driver for eMMC/SD support. Booting from eMMC using HSS --- @@ -214,7 +215,8 @@ GPT partition. Booting ~~~ -You should see the U-Boot prompt on UART0. +You should see the U-Boot prompt on UART1. +(Note: UART0 is reserved for HSS) Sample boot log from MPFS Icicle Kit @@ -451,7 +453,8 @@ copied payload and Linux image. sudo dd if= of=/dev/sdX2 bs=512 -You should see the U-Boot prompt on UART0. +You should see the U-Boot prompt on UART1. +(Note: UART0 is reserved for HSS) GUID type ~ -- 2.25.1
[PATCH v1 0/5] Update Microchip PolarFire SoC support
This patch set updates Microchip PolarFire SoC Icicle Kit support of RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://source.denx.de/u-boot/u-boot) at commit id f200a4bcecf1be6d8b546f0eb6af6403c93d80dd The device tree split into .dtsi and .dts files, UART1 uses for console instead of UART0, UART0 is reserved for Hart Software Services, common device node for eMMC/SD, add Microchip I2C driver and default build for SBI_V02. Padmarao Begari (5): riscv: dts: Split Microchip device tree riscv: Update Microchip MPFS Icicle Kit support i2c: Add Microchip PolarFire SoC I2C driver net: macb: Compatible as per device tree doc: board: Update Microchip MPFS Icicle Kit doc arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 arch/riscv/dts/microchip-mpfs.dtsi| 571 ++ board/microchip/mpfs_icicle/Kconfig | 5 + board/microchip/mpfs_icicle/mpfs_icicle.c | 17 +- configs/microchip_mpfs_icicle_defconfig | 1 - doc/board/microchip/mpfs_icicle.rst | 11 +- drivers/i2c/Kconfig | 6 + drivers/i2c/Makefile | 1 + drivers/i2c/i2c-microchip.c | 482 +++ drivers/net/macb.c| 2 +- .../microchip-mpfs-plic.h | 195 ++ .../interrupt-controller/riscv-hart.h | 18 + 12 files changed, 1431 insertions(+), 396 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi create mode 100644 drivers/i2c/i2c-microchip.c create mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h -- 2.25.1
Re: [PATCH 3/3] riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes
On Wed, Mar 31, 2021 at 12:55 PM Bin Meng wrote: > The uart nodes already provide property for the driver to > dynamically calculate the correct clock frequency. There is no need > to keep the hard-coded property. > > Signed-off-by: Bin Meng > --- > > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 > 1 file changed, 4 deletions(-) > > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts > b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts > index e2b9decc94..89c4cf5fb2 100644 > --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts > @@ -232,7 +232,6 @@ > reg-shift = <2>; > interrupt-parent = <>; > interrupts = <90>; > - clock-frequency = <15000>; > clocks = < CLK_MMUART0>; > status = "okay"; > }; > @@ -294,7 +293,6 @@ > reg-shift = <2>; > interrupt-parent = <>; > interrupts = <91>; > - clock-frequency = <15000>; > clocks = < CLK_MMUART1>; > status = "okay"; > }; > @@ -305,7 +303,6 @@ > reg-shift = <2>; > interrupt-parent = <>; > interrupts = <92>; > - clock-frequency = <15000>; > clocks = < CLK_MMUART2>; > status = "okay"; > }; > @@ -316,7 +313,6 @@ > reg-shift = <2>; > interrupt-parent = <>; > interrupts = <93>; > - clock-frequency = <15000>; > clocks = < CLK_MMUART3>; > status = "okay"; > }; > -- > 2.25.1 > > Reviewed-by: Padmarao Begari Tested-by: Padmarao Begari
Re: [PATCH 2/3] clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag
On Wed, Mar 31, 2021 at 12:55 PM Bin Meng wrote:
> This driver is needed in the pre-relocation phase as the serial
> driver depends on it.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/clk/microchip/mpfs_clk.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/microchip/mpfs_clk.c
> b/drivers/clk/microchip/mpfs_clk.c
> index 722c79b7c0..05d7647206 100644
> --- a/drivers/clk/microchip/mpfs_clk.c
> +++ b/drivers/clk/microchip/mpfs_clk.c
> @@ -120,4 +120,5 @@ U_BOOT_DRIVER(mpfs_clk) = {
> .ops = _clk_ops,
> .probe = mpfs_clk_probe,
> .priv_auto = sizeof(struct clk),
> + .flags = DM_FLAG_PRE_RELOC,
> };
> --
> 2.25.1
>
>
Reviewed-by: Padmarao Begari
Tested-by: Padmarao Begari
Re: [PATCH 1/3] riscv: mpfs-icicle-kit: Increase SYS_MALLOC_F_LEN
On Wed, Mar 31, 2021 at 12:55 PM Bin Meng wrote: > The RISC-V architecture default value of CONFIG_SYS_MALLOC_F_LEN > (0x1000) would not provide enough memory for devices like mpfs > clock and ns16550 serial to bind well before relocation. > > Signed-off-by: Bin Meng > --- > > configs/microchip_mpfs_icicle_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/microchip_mpfs_icicle_defconfig > b/configs/microchip_mpfs_icicle_defconfig > index 0c15c3bd38..1cb29201b4 100644 > --- a/configs/microchip_mpfs_icicle_defconfig > +++ b/configs/microchip_mpfs_icicle_defconfig > @@ -1,4 +1,5 @@ > CONFIG_RISCV=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > CONFIG_ENV_SIZE=0x2000 > CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit" > CONFIG_TARGET_MICROCHIP_ICICLE=y > -- > 2.25.1 > > Reviewed-by: Padmarao Begari Tested-by: Padmarao Begari
Re: [PATCH] doc: icicle: Fix incorrect board name in HSS docs
Hi Sean, On Tue, Mar 16, 2021 at 9:52 AM Sean Anderson wrote: > On 3/16/21 12:05 AM, Padmarao Begari wrote: > > Hi Sean, > > > > On Thu, Mar 11, 2021 at 7:18 AM Sean Anderson <mailto:sean...@gmail.com>> wrote: > > > > The HSS source uses an "mpfs" prefix with the icicle board name. > Change our > > documentation to match. > > > > Signed-off-by: Sean Anderson sean...@gmail.com>> > > --- > > > > doc/board/microchip/mpfs_icicle.rst | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/doc/board/microchip/mpfs_icicle.rst > b/doc/board/microchip/mpfs_icicle.rst > > index c71c2f3cab..cd18472542 100644 > > --- a/doc/board/microchip/mpfs_icicle.rst > > +++ b/doc/board/microchip/mpfs_icicle.rst > > @@ -63,15 +63,15 @@ Build the HSS (Hart Software Services) - > Microchip boot-flow > > > > .. code-block:: none > > > > - make BOARD=icicle-kit-es config > > + make BOARD=mpfs-icicle-kit-es config > > > > Alternatively, copy the default config for Microchip boot-flow. > > > > .. code-block:: none > > > > - cp boards/icicle-kit-es/def_config .config > > + cp boards/mpfs-icicle-kit-es/def_config .config > > > > -2. make BOARD=icicle-kit-es > > +2. make BOARD=mpfs-icicle-kit-es > > 3. In the Default subdirectory, the standard build will create > hss.elf and > > various binary formats (hss.hex and hss.bin). > > > > > > The "mpfs" prefix added only for Microchip boot flow of the HSS but not > Custom boot flow of the HSS. > > Do you mean that > > * The "mpfs" prefix should be used for both microchip boot flow and >custom boot flow, this patch adds it only to the microchip boot flow, >and this patch should be modified to add it to both. > The "mpfs" prefix should be used for both microchip boot flow and custom boot flow, this patch adds it only to the microchip boot flow, and this patch should be modified to add it to both. Regards Padmarao > * The "mpfs" prefix should be used only for the microchip boot flow >and not be used for the custom boot flow, this patch adds it to both >the microchip boot flow and the custom boot flow, and this patch >should be modified to only add it to the custom boot flow. > > Or something else entirely? > > Thanks, > > --Sean > > > > > Regards > > Padmarao > > > > -- > > 2.30.1 > > > >
Re: [PATCH] doc: icicle: Fix incorrect board name in HSS docs
Hi Sean, On Thu, Mar 11, 2021 at 7:18 AM Sean Anderson wrote: > The HSS source uses an "mpfs" prefix with the icicle board name. Change our > documentation to match. > Signed-off-by: Sean Anderson > --- > > doc/board/microchip/mpfs_icicle.rst | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/doc/board/microchip/mpfs_icicle.rst > b/doc/board/microchip/mpfs_icicle.rst > index c71c2f3cab..cd18472542 100644 > --- a/doc/board/microchip/mpfs_icicle.rst > +++ b/doc/board/microchip/mpfs_icicle.rst > @@ -63,15 +63,15 @@ Build the HSS (Hart Software Services) - Microchip > boot-flow > > .. code-block:: none > > - make BOARD=icicle-kit-es config > + make BOARD=mpfs-icicle-kit-es config > > Alternatively, copy the default config for Microchip boot-flow. > > .. code-block:: none > > - cp boards/icicle-kit-es/def_config .config > + cp boards/mpfs-icicle-kit-es/def_config .config > > -2. make BOARD=icicle-kit-es > +2. make BOARD=mpfs-icicle-kit-es > 3. In the Default subdirectory, the standard build will create hss.elf and > various binary formats (hss.hex and hss.bin). > > The "mpfs" prefix added only for Microchip boot flow of the HSS but not Custom boot flow of the HSS. Regards Padmarao > -- > 2.30.1 > >
Re: [PATCH 1/6] net: macb: use dummy descriptor for RBQP
Hi Eugen, On Fri, Jan 15, 2021 at 1:34 PM wrote: > On 15.01.2021 06:02, Padmarao Begari wrote: > > Hi Eugen, > > > > On Thu, Jan 14, 2021 at 4:50 PM > <mailto:eugen.hris...@microchip.com>> wrote: > > > > On 17.12.2020 07:22, Padmarao Begari - I30397 wrote: > > > Hi Eugen, > > > > > > This series of patches break my side of work(patches) so you need > to > > > create patches after my patches are going into master branch > > because my > > > patches are already reviewed and tested. > > > > Hi, > > > > Could you please detail the breakage ? > > > > > > The breakage is the fdt relocation disabled in the board environment > > variables so I have removed it and enabled fdt relocation in PATCH v9. > > Maybe you misunderstand my question. I was asking about the sama7g5 macb > series, which you claimed that breaks your current patch set. > This is a link to the series : > https://patchwork.ozlabs.org/project/uboot/list/?series=218367 > > Since you claimed that this series breaks your series, I am asking what > exactly is the breakage. How does the fdt relocation in your board > environment has anything to do with macb and these patches which are not > applied ? > > My mistake, misunderstood your question, Yes the fdt relocation has nothing to do with the macb. We both are adding a member into struct mac_config, a dummy descriptor for RBQP and my changes are both 32-bit and 64-bit DMA. Regards Padmarao > Thanks, > Eugen > > > > > Regards > > Padmarao > > > > I saw a pull request with your patches that was NAK-ed, if your two > > macb > > patches are tested and reviewed I could apply them to the atmel tree > as > > well and send them, if your PR is delayed. But we are interested to > > have > > our sama7g5 series pushed as well, so we need to know if it's ok on > > your > > side, and what is wrong with the sama7g5 series. > > > > Thanks! > > Eugen > > > > > > Regards > > > Padmarao > > > > > > > > > *From:* Eugen Hristev - M18282 > <mailto:eugen.hris...@microchip.com>> > > > *Sent:* Wednesday, December 16, 2020 12:24 PM > > > *To:* anup.pa...@wdc.com <mailto:anup.pa...@wdc.com> > > mailto:anup.pa...@wdc.com>>; > > bin.m...@windriver.com <mailto:bin.m...@windriver.com> > > > mailto:bin.m...@windriver.com>>; > > Padmarao Begari - I30397 > > > > <mailto:padmarao.beg...@microchip.com>> > > > *Cc:* Claudiu Beznea - M18063 > <mailto:claudiu.bez...@microchip.com>>; > > > joe.hershber...@ni.com <mailto:joe.hershber...@ni.com> > > mailto:joe.hershber...@ni.com>>; > > u-boot@lists.denx.de <mailto:u-boot@lists.denx.de> > > > mailto:u-boot@lists.denx.de>> > > > *Subject:* Re: [PATCH 1/6] net: macb: use dummy descriptor for > RBQP > > > On 03.12.2020 11:25, Claudiu Beznea wrote: > > >> In case of multiple queues on RX side the queue scheduler > > >> will try to use all the available configured queues (with > > >> descriptors having TX_USED bit cleared). If at least one RBQP > > >> points to a descriptor with a valid used bit configuration then > > >> the reception may block as this may point to any memory. To avoid > > >> this scenario all the queues (except queue zero) were disabled by > > >> setting DMA descriptors with used bit set on proper RBQP. The > driver > > >> anyway uses only queue 0 for TX/RX. > > >> > > >> Signed-off-by: Claudiu Beznea > <mailto:claudiu.bez...@microchip.com>> > > >> --- > > > > > > Hi Anup, Bin, Padmarao, > > > > > > I noticed on the mailing list that you have been actively working > and > > > testing the Macb driver on various platforms, we have this series > > > outstanding and I want to make sure that it does not break > > anything on > > > your side, so it would be appreciated if you could have a look or > > test > > > it before it goes into master branch. > > > > > > Thanks ! > > > Eugen > > > > >
[PATCH v9 6/7] riscv: Add Microchip MPFS Icicle Kit support
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 59 +-
4 files changed, 145 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..4678462378 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,30 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..0e34409067 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -6,10 +6,49 @@
#include
#include
+#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+ /*
+* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /*
+* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +61,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr,
6);
+ if (ret) {
+ printf("No local-mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property\n");
+
[PATCH v9 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 810
3 files changed, 820 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 915f1be8a5..08c167b6b5 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -17,6 +17,7 @@ Board-specific doc
google/index
intel/index
kontron/index
+ microchip/index
renesas/index
rockchip/index
sifive/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..affc5a9e01
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+=
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..7489761501
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,810 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building U-Boot
+---
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware (Microchip
+boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin
embedded)
+as HSS payload (Custom boot-flow)
+
+Microchip boot-flow
+---
+HSS with OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode)
+
+Build the HSS (Hart Software Services) - Microchip boot-flow
+
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+ make BOARD=icicle-kit-es config
+
+Alternatively, copy the default config for Microchip boot-flow.
+
+.. code-block:: none
+
+ cp boards/icicle-kit-es/def_config .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+ various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+Creating the HSS payload - Microchip boot-flow
+--
+1. You will be creating a payload from `u-boot-dtb.bin`.
+ Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+ cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the
binary file.
+
+ hart-entry-points: {u54_1: '0x8020', u54_2: '0x8020', u54_3:
'0x8020', u54_4: '0x8020'}
+
+ payloads:
+ test/u-boot-dtb.bin: {exec-addr: '0x8020', owner-hart: u54_1,
secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode:
prv_s}
+
+4. Generate payload
+
+.. code-block:: none
+
+ ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md)
+
+Custom boot-flow
+
+HSS without OpenSBI (M-Mode) -> OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux
(S-Mode)
+
+Build OpenSBI
+-
+
+1. Get the OpenSB
[PATCH v9 4/7] clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/microchip/Kconfig | 5 +
drivers/clk/microchip/Makefile| 1 +
drivers/clk/microchip/mpfs_clk.c | 123
drivers/clk/microchip/mpfs_clk.h | 44 +
drivers/clk/microchip/mpfs_clk_cfg.c | 152 ++
drivers/clk/microchip/mpfs_clk_periph.c | 187 ++
.../dt-bindings/clock/microchip-mpfs-clock.h | 45 +
9 files changed, 559 insertions(+)
create mode 100644 drivers/clk/microchip/Kconfig
create mode 100644 drivers/clk/microchip/Makefile
create mode 100644 drivers/clk/microchip/mpfs_clk.c
create mode 100644 drivers/clk/microchip/mpfs_clk.h
create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c
create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c
create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index db06f276ec..4aeaa0cd58 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -165,6 +165,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
+source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f8383e523d..645709b855 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
+obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
new file mode 100644
index 00..b70241559d
--- /dev/null
+++ b/drivers/clk/microchip/Kconfig
@@ -0,0 +1,5 @@
+config CLK_MPFS
+ bool "Clock support for Microchip PolarFire SoC"
+ depends on CLK && CLK_CCF
+ help
+ This enables support clock driver for Microchip PolarFire SoC
platform.
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 00..904b345d75
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1 @@
+obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
new file mode 100644
index 00..722c79b7c0
--- /dev/null
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mpfs_clk.h"
+
+/* All methods are delegated to CCF clocks */
+
+static ulong mpfs_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, );
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int mpfs_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int mpfs_clk_enable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, true);
+}
+
+static int mpfs_clk_disable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, false);
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+ int ret;
+ void __iomem *base;
+ u32 clk_rate;
+ const char *parent_clk_name;
+ struct clk *clk = dev_get_priv(dev);
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, clk);
+ if (ret)
+ return ret;
+
+ dev_read_u32
[PATCH v9 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
3 files changed, 436 insertions(+)
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..01331b0aa1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
new file mode 100644
index 00..f60283fb6b
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+
+/ {
+ aliases {
+ cpu1 =
+ cpu2 =
+ cpu3 =
+ cpu4 =
+ };
+};
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 00..e2b9decc94
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip MPFS Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells
[PATCH v9 3/7] net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0c2ac811fb..2225b33ff6 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -531,6 +531,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1311,6 +1317,7 @@ static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct macb_device *macb = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
int ret;
@@ -1323,6 +1330,12 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Read phyaddr from DT */
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args))
+ macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
+"reg", -1);
+
macb->regs = (void *)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
--
2.17.1
[PATCH v9 2/7] net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.
The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e287c29e69..0c2ac811fb 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -83,7 +83,16 @@ struct macb_dma_desc {
u32 ctrl;
};
-#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
+struct macb_dma_desc_64 {
+ u32 addrh;
+ u32 unused;
+};
+
+#define HW_DMA_CAP_32B 0
+#define HW_DMA_CAP_64B 1
+
+#define DMA_DESC_SIZE 16
+#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
@@ -137,6 +146,7 @@ struct macb_device {
struct macb_config {
unsigned intdma_burst_length;
+ unsigned inthw_dma_cap;
int (*clk_init)(struct udevice *dev, ulong rate);
};
@@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct
macb_device *macb)
#if defined(CONFIG_CMD_NET)
+static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
+{
+ return (struct macb_dma_desc_64 *)((void *)desc
+ + sizeof(struct macb_dma_desc));
+}
+
+static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
+ ulong addr)
+{
+ struct macb_dma_desc_64 *desc_64;
+
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ desc_64 = macb_64b_desc(desc);
+ desc_64->addrh = upper_32_bits(addr);
+ }
+ desc->addr = lower_32_bits(addr);
+}
+
static int _macb_send(struct macb_device *macb, const char *name, void *packet,
int length)
{
@@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
macb->tx_head++;
}
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ tx_head = tx_head * 2;
+
macb->tx_ring[tx_head].ctrl = ctrl;
- macb->tx_ring[tx_head].addr = paddr;
+ macb_set_addr(macb, >tx_ring[tx_head], paddr);
+
barrier();
macb_flush_ring_desc(macb, TX);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
@@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device *macb,
unsigned int new_tail)
{
unsigned int i;
+ unsigned int count;
i = macb->rx_tail;
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
void *buffer;
int length;
u32 status;
+ u8 flag = false;
macb->wrapped = false;
for (;;) {
macb_invalidate_ring_desc(macb, RX);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ next_rx_tail = next_rx_tail * 2;
+
if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
if (status & MACB_BIT(RX_SOF)) {
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ next_rx_tail = next_rx_tail / 2;
+ flag = true;
+ }
+
if (next_rx_tail != macb->rx_tail)
[PATCH v9 1/7] riscv: Add DMA 64-bit address support
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 4 arch/riscv/include/asm/types.h | 4 2 files changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 30b05408b1..55eaee2da6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,10 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + default y if 64BIT + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1
[PATCH v9 0/7] Microchip PolarFire SoC support
This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id ab1a425524a79eeca61e7b67fdf382c7a499346f All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Changes in v9: - Remove fdt_high=0x, initrd_high=0x - Add bootm_size=0x1000 in the environment variables Changes in v8: - Use 'priv_auto' instead of 'priv_auto_alloc_size' in the clock driver - Remove the doc warnings to build the htmldocs Changes in v7: - Allocate memory using auto-alloc feature in the clock driver - Re-order header files in the clock driver - Add comments in the clock driver Changes in v6: - Update MACB driver for 32-bit/64-bit DMA based on struct mac_config - Rename microchip,mpfs-clock.h to microchip-mpfs-clock.h - Add dual-license GPL or MIT in the clock dt-binding - Move refclk device tree node under / device tree node - Remove the dtc warnings - Fix some typos in device tree and doc Changes in v5: - Replace compatible string "microchip,polarfire-soc" with "microchip,mpfs-icicle-kit" in the device tree - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" - Fix some typos in doc - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* - Rename pfsoc-clock.h to mpfs-clock.h Changes in v4: - Add dual-license GPL or MIT in the device tree - Replace microsemi compatible strings with microchip - Add MACB compatible string for Microchip PolarFire SoC ethernet - Update MACB driver for 32-bit/64-bit DMA based on compatible string Changes in v3: - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT - Update MACB driver for 32-bit/64-bit DMA based on design config register - Add phy-handle in MACB driver to read the phy address from device tree - Fix checkpatch warnings in the clock driver - Remove fu540 related compatible strings from soc device tree node - Move refclk device tree node under /soc device tree node - Use local-mac-address instead of mac-address in the device tree - Rename device tree to microchip-mpfs-icicle-kit.dts - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file - Drop the imply DMA_ADDR_T_64BIT from board config - Fix some typos - Update doc with Microchip and Custom boot-flow Changes in v2: - Add clock frequency for the clint device tree node - Move peripheral device tree nodes under /soc device tree node - Device tree nodes are in order based on the address - Enable UART0 for U-Boot logs - Update doc for the U-Boot logs are on UART0 - Move clock and reset index source into patch4 - Remove "dma_addr_r" type in the macb driver - Add lower_32_bits() for 32-bit address in the macb driver - Add set_rate() returns the new clock rate in the clock driver Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig| 4 + arch/riscv/dts/Makefile | 1 + .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 + arch/riscv/include/asm/types.h| 4 + board/microchip/mpfs_icicle/Kconfig | 23 + board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 810 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile| 1 + drivers/clk/microchip/mpfs_clk.c | 123 +++ drivers/clk/microchip/mpfs_clk.h | 44 + drivers/clk/microchip/mpfs_clk_cfg.c | 152 drivers/clk/microchip/mpfs_clk_periph.c | 187 drivers/net/macb.c| 144 +++- drivers/net/macb.h| 6 + include/configs/microchip_mpfs_icicle.h | 59 +- .../dt-bindings/clock/microchip-mpfs-clock.h | 45 + 23 files changed, 2101 insertions(+), 62 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/
Re: [PATCH 1/6] net: macb: use dummy descriptor for RBQP
Hi Eugen,
On Thu, Jan 14, 2021 at 4:50 PM wrote:
> On 17.12.2020 07:22, Padmarao Begari - I30397 wrote:
> > Hi Eugen,
> >
> > This series of patches break my side of work(patches) so you need to
> > create patches after my patches are going into master branch because my
> > patches are already reviewed and tested.
>
> Hi,
>
> Could you please detail the breakage ?
>
The breakage is the fdt relocation disabled in the board environment
variables so I have removed it and enabled fdt relocation in PATCH v9.
Regards
Padmarao
> I saw a pull request with your patches that was NAK-ed, if your two macb
> patches are tested and reviewed I could apply them to the atmel tree as
> well and send them, if your PR is delayed. But we are interested to have
> our sama7g5 series pushed as well, so we need to know if it's ok on your
> side, and what is wrong with the sama7g5 series.
>
> Thanks!
> Eugen
> >
> > Regards
> > Padmarao
> >
> > *From:* Eugen Hristev - M18282
> > *Sent:* Wednesday, December 16, 2020 12:24 PM
> > *To:* anup.pa...@wdc.com ; bin.m...@windriver.com
> > ; Padmarao Begari - I30397
> >
> > *Cc:* Claudiu Beznea - M18063 ;
> > joe.hershber...@ni.com ; u-boot@lists.denx.de
> >
> > *Subject:* Re: [PATCH 1/6] net: macb: use dummy descriptor for RBQP
> > On 03.12.2020 11:25, Claudiu Beznea wrote:
> >> In case of multiple queues on RX side the queue scheduler
> >> will try to use all the available configured queues (with
> >> descriptors having TX_USED bit cleared). If at least one RBQP
> >> points to a descriptor with a valid used bit configuration then
> >> the reception may block as this may point to any memory. To avoid
> >> this scenario all the queues (except queue zero) were disabled by
> >> setting DMA descriptors with used bit set on proper RBQP. The driver
> >> anyway uses only queue 0 for TX/RX.
> >>
> >> Signed-off-by: Claudiu Beznea
> >> ---
> >
> > Hi Anup, Bin, Padmarao,
> >
> > I noticed on the mailing list that you have been actively working and
> > testing the Macb driver on various platforms, we have this series
> > outstanding and I want to make sure that it does not break anything on
> > your side, so it would be appreciated if you could have a look or test
> > it before it goes into master branch.
> >
> > Thanks !
> > Eugen
> >
> >
> >> drivers/net/macb.c | 4 +++-
> >> drivers/net/macb.h | 2 ++
> >> 2 files changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> >> index b80a259ff757..836eb85ec96a 100644
> >> --- a/drivers/net/macb.c
> >> +++ b/drivers/net/macb.c
> >> @@ -732,8 +732,10 @@ static int gmac_init_multi_queues(struct
> macb_device *macb)
> >>flush_dcache_range(macb->dummy_desc_dma, macb->dummy_desc_dma +
> >>ALIGN(MACB_TX_DUMMY_DMA_DESC_SIZE, PKTALIGN));
> >>
> >> - for (i = 1; i < num_queues; i++)
> >> + for (i = 1; i < num_queues; i++) {
> >>gem_writel_queue_TBQP(macb, macb->dummy_desc_dma, i - 1);
> >> + gem_writel_queue_RBQP(macb, macb->dummy_desc_dma, i - 1);
> >> + }
> >>
> >>return 0;
> >> }
> >> diff --git a/drivers/net/macb.h b/drivers/net/macb.h
> >> index 9b16383eba46..28c7fe306883 100644
> >> --- a/drivers/net/macb.h
> >> +++ b/drivers/net/macb.h
> >> @@ -768,5 +768,7 @@
> >> #define GEM_RX_CSUM_CHECKED_MASK2
> >> #define gem_writel_queue_TBQP(port, value, queue_num) \
> >>writel((value), (port)->regs + GEM_TBQP(queue_num))
> >> +#define gem_writel_queue_RBQP(port, value, queue_num)\
> >> + writel((value), (port)->regs + GEM_RBQP(queue_num))
> >>
> >> #endif /* __DRIVERS_MACB_H__ */
> >>
> >
>
>
Re: Pull request: u-boot-riscv/master
Hi Tom, On Thu, Jan 14, 2021 at 1:31 AM Tom Rini wrote: > On Wed, Jan 13, 2021 at 01:34:55PM +0800, ub...@andestech.com wrote: > > > Hi Tom, > > > > Please pull some riscv updates: > > > > - Update qemu-riscv.rst build instructions. > > - Add support for SPI on Kendryte K210. > > - Add Microchip PolarFire SoC Icicle Kit support. > > > > Thanks > > Rick > > > > CI: passed > > https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/5853 > > > > The following changes since commit > ee6726be4f0dccb612f0193c62ca149164c8a5af: > > > > Merge tag 'ti-v2021.04-rc1' of > https://gitlab.denx.de/u-boot/custodians/u-boot-ti (2021-01-12 09:32:48 > -0500) > > > > are available in the Git repository at: > > > > g...@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to 477b035bd200fbef3045902f3ea2fe26cd831a5c: > > > > doc: board: Add Microchip MPFS Icicle Kit doc (2021-01-13 08:51:55 > +0800) > > NAK: > ERROR: fdt or initrd relocation disabled at boot time > #272: FILE: include/configs/microchip_mpfs_icicle.h:32: > + "fdt_high=0x\0" \ > > It also disables initrd relocation, which I don't like, but isn't fatal. > But you cannot disable fdt relocation as that leads to run time problems > all too often. > > Ok I will enable fdt relocation in PATCH v9 and remove "fdt_high=0x\0", "initrd_high=0x\0 from the board ENV. Thanks Padmarao > -- > Tom >
[PATCH v8 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
3 files changed, 436 insertions(+)
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..01331b0aa1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
new file mode 100644
index 00..f60283fb6b
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+
+/ {
+ aliases {
+ cpu1 =
+ cpu2 =
+ cpu3 =
+ cpu4 =
+ };
+};
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 00..e2b9decc94
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip MPFS Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells
[PATCH v8 6/7] riscv: Add Microchip MPFS Icicle Kit support
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60 +-
4 files changed, 146 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..4678462378 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,30 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..0e34409067 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -6,10 +6,49 @@
#include
#include
+#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+ /*
+* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /*
+* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +61,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr,
6);
+ if (ret) {
+ printf("No local-mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property\n");
+
[PATCH v8 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 810
3 files changed, 820 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 915f1be8a5..08c167b6b5 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -17,6 +17,7 @@ Board-specific doc
google/index
intel/index
kontron/index
+ microchip/index
renesas/index
rockchip/index
sifive/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..affc5a9e01
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+=
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..161277478a
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,810 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building U-Boot
+---
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware (Microchip
+boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin
embedded)
+as HSS payload (Custom boot-flow)
+
+Microchip boot-flow
+---
+HSS with OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode)
+
+Build the HSS (Hart Software Services) - Microchip boot-flow
+
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+ make BOARD=icicle-kit-es config
+
+Alternatively, copy the default config for Microchip boot-flow.
+
+.. code-block:: none
+
+ cp boards/icicle-kit-es/def_config .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+ various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+Creating the HSS payload - Microchip boot-flow
+--
+1. You will be creating a payload from `u-boot-dtb.bin`.
+ Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+ cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the
binary file.
+
+ hart-entry-points: {u54_1: '0x8020', u54_2: '0x8020', u54_3:
'0x8020', u54_4: '0x8020'}
+
+ payloads:
+ test/u-boot-dtb.bin: {exec-addr: '0x8020', owner-hart: u54_1,
secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart: u54_4, priv-mode:
prv_s}
+
+4. Generate payload
+
+.. code-block:: none
+
+ ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md)
+
+Custom boot-flow
+
+HSS without OpenSBI (M-Mode) -> OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux
(S-Mode)
+
+Build OpenSBI
+-
+
+1. Get the OpenSB
[PATCH v8 4/7] clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/microchip/Kconfig | 5 +
drivers/clk/microchip/Makefile| 1 +
drivers/clk/microchip/mpfs_clk.c | 123
drivers/clk/microchip/mpfs_clk.h | 44 +
drivers/clk/microchip/mpfs_clk_cfg.c | 152 ++
drivers/clk/microchip/mpfs_clk_periph.c | 187 ++
.../dt-bindings/clock/microchip-mpfs-clock.h | 45 +
9 files changed, 559 insertions(+)
create mode 100644 drivers/clk/microchip/Kconfig
create mode 100644 drivers/clk/microchip/Makefile
create mode 100644 drivers/clk/microchip/mpfs_clk.c
create mode 100644 drivers/clk/microchip/mpfs_clk.h
create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c
create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c
create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..1161fe7b5a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
+source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..dbf28c4e81 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
+obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
new file mode 100644
index 00..b70241559d
--- /dev/null
+++ b/drivers/clk/microchip/Kconfig
@@ -0,0 +1,5 @@
+config CLK_MPFS
+ bool "Clock support for Microchip PolarFire SoC"
+ depends on CLK && CLK_CCF
+ help
+ This enables support clock driver for Microchip PolarFire SoC
platform.
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 00..904b345d75
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1 @@
+obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
new file mode 100644
index 00..722c79b7c0
--- /dev/null
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mpfs_clk.h"
+
+/* All methods are delegated to CCF clocks */
+
+static ulong mpfs_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, );
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int mpfs_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int mpfs_clk_enable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, true);
+}
+
+static int mpfs_clk_disable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, false);
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+ int ret;
+ void __iomem *base;
+ u32 clk_rate;
+ const char *parent_clk_name;
+ struct clk *clk = dev_get_priv(dev);
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, clk);
+ if (ret)
+ return ret;
+
+ dev_read_u32
[PATCH v8 2/7] net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.
The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e287c29e69..0c2ac811fb 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -83,7 +83,16 @@ struct macb_dma_desc {
u32 ctrl;
};
-#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
+struct macb_dma_desc_64 {
+ u32 addrh;
+ u32 unused;
+};
+
+#define HW_DMA_CAP_32B 0
+#define HW_DMA_CAP_64B 1
+
+#define DMA_DESC_SIZE 16
+#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
@@ -137,6 +146,7 @@ struct macb_device {
struct macb_config {
unsigned intdma_burst_length;
+ unsigned inthw_dma_cap;
int (*clk_init)(struct udevice *dev, ulong rate);
};
@@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct
macb_device *macb)
#if defined(CONFIG_CMD_NET)
+static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
+{
+ return (struct macb_dma_desc_64 *)((void *)desc
+ + sizeof(struct macb_dma_desc));
+}
+
+static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
+ ulong addr)
+{
+ struct macb_dma_desc_64 *desc_64;
+
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ desc_64 = macb_64b_desc(desc);
+ desc_64->addrh = upper_32_bits(addr);
+ }
+ desc->addr = lower_32_bits(addr);
+}
+
static int _macb_send(struct macb_device *macb, const char *name, void *packet,
int length)
{
@@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
macb->tx_head++;
}
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ tx_head = tx_head * 2;
+
macb->tx_ring[tx_head].ctrl = ctrl;
- macb->tx_ring[tx_head].addr = paddr;
+ macb_set_addr(macb, >tx_ring[tx_head], paddr);
+
barrier();
macb_flush_ring_desc(macb, TX);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
@@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device *macb,
unsigned int new_tail)
{
unsigned int i;
+ unsigned int count;
i = macb->rx_tail;
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
void *buffer;
int length;
u32 status;
+ u8 flag = false;
macb->wrapped = false;
for (;;) {
macb_invalidate_ring_desc(macb, RX);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ next_rx_tail = next_rx_tail * 2;
+
if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
if (status & MACB_BIT(RX_SOF)) {
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ next_rx_tail = next_rx_tail / 2;
+ flag = true;
+ }
+
if (next_rx_tail != macb->rx_tail)
[PATCH v8 0/7] Microchip PolarFire SoC support
This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id d71be1990218957b9f05dbf13a72859a2abe06d7 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Changes in v8: - Use 'priv_auto' instead of 'priv_auto_alloc_size' in the clock driver - Remove the doc warnings to build the htmldocs Changes in v7: - Allocate memory using auto-alloc feature in the clock driver - Re-order header files in the clock driver - Add comments in the clock driver Changes in v6: - Update MACB driver for 32-bit/64-bit DMA based on struct mac_config - Rename microchip,mpfs-clock.h to microchip-mpfs-clock.h - Add dual-license GPL or MIT in the clock dt-binding - Move refclk device tree node under / device tree node - Remove the dtc warnings - Fix some typos in device tree and doc Changes in v5: - Replace compatible string "microchip,polarfire-soc" with "microchip,mpfs-icicle-kit" in the device tree - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" - Fix some typos in doc - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* - Rename pfsoc-clock.h to mpfs-clock.h Changes in v4: - Add dual-license GPL or MIT in the device tree - Replace microsemi compatible strings with microchip - Add MACB compatible string for Microchip PolarFire SoC ethernet - Update MACB driver for 32-bit/64-bit DMA based on compatible string Changes in v3: - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT - Update MACB driver for 32-bit/64-bit DMA based on design config register - Add phy-handle in MACB driver to read the phy address from device tree - Fix checkpatch warnings in the clock driver - Remove fu540 related compatible strings from soc device tree node - Move refclk device tree node under /soc device tree node - Use local-mac-address instead of mac-address in the device tree - Rename device tree to microchip-mpfs-icicle-kit.dts - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file - Drop the imply DMA_ADDR_T_64BIT from board config - Fix some typos - Update doc with Microchip and Custom boot-flow Changes in v2: - Add clock frequency for the clint device tree node - Move peripheral device tree nodes under /soc device tree node - Device tree nodes are in order based on the address - Enable UART0 for U-Boot logs - Update doc for the U-Boot logs are on UART0 - Move clock and reset index source into patch4 - Remove "dma_addr_r" type in the macb driver - Add lower_32_bits() for 32-bit address in the macb driver - Add set_rate() returns the new clock rate in the clock driver Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig| 4 + arch/riscv/dts/Makefile | 1 + .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 + arch/riscv/include/asm/types.h| 4 + board/microchip/mpfs_icicle/Kconfig | 23 + board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 810 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile| 1 + drivers/clk/microchip/mpfs_clk.c | 123 +++ drivers/clk/microchip/mpfs_clk.h | 44 + drivers/clk/microchip/mpfs_clk_cfg.c | 152 drivers/clk/microchip/mpfs_clk_periph.c | 187 drivers/net/macb.c| 144 +++- drivers/net/macb.h| 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip-mpfs-clock.h | 45 + 23 files changed, 2102 insertions(+), 62 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100
[PATCH v8 1/7] riscv: Add DMA 64-bit address support
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/Kconfig | 4 arch/riscv/include/asm/types.h | 4 2 files changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 30b05408b1..55eaee2da6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,10 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + default y if 64BIT + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1
[PATCH v8 3/7] net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0c2ac811fb..2225b33ff6 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -531,6 +531,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1311,6 +1317,7 @@ static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct macb_device *macb = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
int ret;
@@ -1323,6 +1330,12 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Read phyaddr from DT */
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args))
+ macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
+"reg", -1);
+
macb->regs = (void *)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
--
2.17.1
Re: [PATCH v7 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
Hi Rick, On Mon, Jan 11, 2021 at 8:26 AM Rick Chen wrote: > Hi Padmarao > > > From: Padmarao Begari [mailto:padmarao.beg...@microchip.com] > > Sent: Tuesday, December 22, 2020 9:12 PM > > To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志); > anup.pa...@wdc.com; lukas.a...@aisec.fraunhofer.de; joe.hershber...@ni.com; > lu...@denx.de; atish.pa...@wdc.com > > Cc: cyril.j...@microchip.com; lewis.ha...@microchip.com; > ivan.grif...@emdalo.com; daire.mcnam...@emdalo.com; > conor.doo...@microchip.com; Padmarao Begari > > Subject: [PATCH v7 7/7] doc: board: Add Microchip MPFS Icicle Kit doc > > > > This doc describes the procedure to build, flash and > > boot Linux using U-boot on Microchip MPFS Icicle Kit. > > > > Signed-off-by: Padmarao Begari > > Reviewed-by: Anup Patel > > Reviewed-by: Bin Meng > > --- > > doc/board/index.rst | 1 + > > doc/board/microchip/index.rst | 9 + > > doc/board/microchip/mpfs_icicle.rst | 816 > > 3 files changed, 826 insertions(+) > > create mode 100644 doc/board/microchip/index.rst > > create mode 100644 doc/board/microchip/mpfs_icicle.rst > > Please check the CI failure item as below: > https://gitlab.denx.de/u-boot/custodians/u-boot-riscv/-/jobs/199014 > > > /builds/u-boot/custodians/u-boot-riscv/doc/board/microchip/mpfs_icicle.rst:99:Unexpected > indentation. > 199make[1]: *** [htmldocs] Error 1 > 200make: *** [htmldocs] Error 2 > 201doc/Makefile:69: recipe for target 'htmldocs' failed > 202Makefile:2167: recipe for target 'htmldocs' failed > > The error is the line broken into more lines at mpfs_icicle.rst:99, I will make it a single line. Regards Padmarao > Thanks, > Rick >
[PATCH v7 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 816
3 files changed, 826 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 915f1be8a5..08c167b6b5 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -17,6 +17,7 @@ Board-specific doc
google/index
intel/index
kontron/index
+ microchip/index
renesas/index
rockchip/index
sifive/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..affc5a9e01
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+=
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..d0d0edef91
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,816 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building U-Boot
+---
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware (Microchip
+boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin
embedded)
+as HSS payload (Custom boot-flow)
+
+Microchip boot-flow
+---
+HSS with OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode)
+
+Build the HSS (Hart Software Services) - Microchip boot-flow
+
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+ make BOARD=icicle-kit-es config
+
+Alternatively, copy the default config for Microchip boot-flow.
+
+.. code-block:: none
+
+ cp boards/icicle-kit-es/def_config .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+ various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+Creating the HSS payload - Microchip boot-flow
+--
+1. You will be creating a payload from `u-boot-dtb.bin`.
+ Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+ cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the
binary file.
+
+ hart-entry-points: {u54_1: '0x8020', u54_2: '0x8020',
+ u54_3: '0x8020', u54_4: '0x8020'}
+
+ payloads:
+ test/u-boot-dtb.bin: {exec-addr: '0x8020', owner-hart: u54_1,
+ secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart:
u54_4,
+ priv-mode: prv_s}
+
+4. Generate payload
+
+.. code-block:: none
+
+ ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md)
+
+Custom boot-flow
+
+HSS without OpenSBI (M-Mode) -> OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux
(S-Mod
[PATCH v7 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
3 files changed, 436 insertions(+)
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..01331b0aa1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
new file mode 100644
index 00..f60283fb6b
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+
+/ {
+ aliases {
+ cpu1 =
+ cpu2 =
+ cpu3 =
+ cpu4 =
+ };
+};
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 00..e2b9decc94
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip MPFS Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells
[PATCH v7 6/7] riscv: Add Microchip MPFS Icicle Kit support
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60 +-
4 files changed, 146 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..4678462378 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,30 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..0e34409067 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -6,10 +6,49 @@
#include
#include
+#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+ /*
+* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /*
+* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +61,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr,
6);
+ if (ret) {
+ printf("No local-mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property\n");
+
[PATCH v7 3/7] net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 626ee49227..9b45187e5a 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -531,6 +531,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1311,6 +1317,7 @@ static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
int ret;
@@ -1323,6 +1330,12 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Read phyaddr from DT */
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args))
+ macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
+"reg", -1);
+
macb->regs = (void *)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
--
2.17.1
[PATCH v7 2/7] net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.
The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index b80a259ff7..626ee49227 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -83,7 +83,16 @@ struct macb_dma_desc {
u32 ctrl;
};
-#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
+struct macb_dma_desc_64 {
+ u32 addrh;
+ u32 unused;
+};
+
+#define HW_DMA_CAP_32B 0
+#define HW_DMA_CAP_64B 1
+
+#define DMA_DESC_SIZE 16
+#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
@@ -137,6 +146,7 @@ struct macb_device {
struct macb_config {
unsigned intdma_burst_length;
+ unsigned inthw_dma_cap;
int (*clk_init)(struct udevice *dev, ulong rate);
};
@@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct
macb_device *macb)
#if defined(CONFIG_CMD_NET)
+static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
+{
+ return (struct macb_dma_desc_64 *)((void *)desc
+ + sizeof(struct macb_dma_desc));
+}
+
+static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
+ ulong addr)
+{
+ struct macb_dma_desc_64 *desc_64;
+
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ desc_64 = macb_64b_desc(desc);
+ desc_64->addrh = upper_32_bits(addr);
+ }
+ desc->addr = lower_32_bits(addr);
+}
+
static int _macb_send(struct macb_device *macb, const char *name, void *packet,
int length)
{
@@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
macb->tx_head++;
}
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ tx_head = tx_head * 2;
+
macb->tx_ring[tx_head].ctrl = ctrl;
- macb->tx_ring[tx_head].addr = paddr;
+ macb_set_addr(macb, >tx_ring[tx_head], paddr);
+
barrier();
macb_flush_ring_desc(macb, TX);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
@@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device *macb,
unsigned int new_tail)
{
unsigned int i;
+ unsigned int count;
i = macb->rx_tail;
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
void *buffer;
int length;
u32 status;
+ u8 flag = false;
macb->wrapped = false;
for (;;) {
macb_invalidate_ring_desc(macb, RX);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ next_rx_tail = next_rx_tail * 2;
+
if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
if (status & MACB_BIT(RX_SOF)) {
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ next_rx_tail = next_rx_tail / 2;
+ flag = true;
+ }
+
if (next_rx_tail != macb->rx_tail)
[PATCH v7 4/7] clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Tested-by: Bin Meng
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/microchip/Kconfig | 5 +
drivers/clk/microchip/Makefile| 1 +
drivers/clk/microchip/mpfs_clk.c | 123
drivers/clk/microchip/mpfs_clk.h | 44 +
drivers/clk/microchip/mpfs_clk_cfg.c | 152 ++
drivers/clk/microchip/mpfs_clk_periph.c | 187 ++
.../dt-bindings/clock/microchip-mpfs-clock.h | 45 +
9 files changed, 559 insertions(+)
create mode 100644 drivers/clk/microchip/Kconfig
create mode 100644 drivers/clk/microchip/Makefile
create mode 100644 drivers/clk/microchip/mpfs_clk.c
create mode 100644 drivers/clk/microchip/mpfs_clk.h
create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c
create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c
create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..1161fe7b5a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
+source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..bd8a6eed88 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
+obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
new file mode 100644
index 00..b70241559d
--- /dev/null
+++ b/drivers/clk/microchip/Kconfig
@@ -0,0 +1,5 @@
+config CLK_MPFS
+ bool "Clock support for Microchip PolarFire SoC"
+ depends on CLK && CLK_CCF
+ help
+ This enables support clock driver for Microchip PolarFire SoC
platform.
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 00..904b345d75
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1 @@
+obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
new file mode 100644
index 00..2dd55ee557
--- /dev/null
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mpfs_clk.h"
+
+/* All methods are delegated to CCF clocks */
+
+static ulong mpfs_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, );
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int mpfs_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int mpfs_clk_enable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, true);
+}
+
+static int mpfs_clk_disable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, false);
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+ int ret;
+ void __iomem *base;
+ u32 clk_rate;
+ const char *parent_clk_name;
+ struct clk *clk = dev_get_priv(dev);
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, clk);
+ if (ret)
+ return ret;
+
+ dev_read_u32
[PATCH v7 0/7] Microchip PolarFire SoC support
This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id c15f44acf9d473f4682bfdc63b8aebd313492b15 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Changes in v7: - Allocate memory using auto-alloc feature in the clock driver - Re-order header files in the clock driver - Add comments in the clock driver Changes in v6: - Update MACB driver for 32-bit/64-bit DMA based on struct mac_config - Rename microchip,mpfs-clock.h to microchip-mpfs-clock.h - Add dual-license GPL or MIT in the clock dt-binding - Move refclk device tree node under / device tree node - Remove the dtc warnings - Fix some typos in device tree and doc Changes in v5: - Replace compatible string "microchip,polarfire-soc" with "microchip,mpfs-icicle-kit" in the device tree - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" - Fix some typos in doc - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* - Rename pfsoc-clock.h to mpfs-clock.h Changes in v4: - Add dual-license GPL or MIT in the device tree - Replace microsemi compatible strings with microchip - Add MACB compatible string for Microchip PolarFire SoC ethernet - Update MACB driver for 32-bit/64-bit DMA based on compatible string Changes in v3: - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT - Update MACB driver for 32-bit/64-bit DMA based on design config register - Add phy-handle in MACB driver to read the phy address from device tree - Fix checkpatch warnings in the clock driver - Remove fu540 related compatible strings from soc device tree node - Move refclk device tree node under /soc device tree node - Use local-mac-address instead of mac-address in the device tree - Rename device tree to microchip-mpfs-icicle-kit.dts - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file - Drop the imply DMA_ADDR_T_64BIT from board config - Fix some typos - Update doc with Microchip and Custom boot-flow Changes in v2: - Add clock frequency for the clint device tree node - Move peripheral device tree nodes under /soc device tree node - Device tree nodes are in order based on the address - Enable UART0 for U-Boot logs - Update doc for the U-Boot logs are on UART0 - Move clock and reset index source into patch4 - Remove "dma_addr_r" type in the macb driver - Add lower_32_bits() for 32-bit address in the macb driver - Add set_rate() returns the new clock rate in the clock driver Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig| 4 + arch/riscv/dts/Makefile | 1 + .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 + arch/riscv/include/asm/types.h| 4 + board/microchip/mpfs_icicle/Kconfig | 23 + board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 816 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile| 1 + drivers/clk/microchip/mpfs_clk.c | 123 +++ drivers/clk/microchip/mpfs_clk.h | 44 + drivers/clk/microchip/mpfs_clk_cfg.c | 152 drivers/clk/microchip/mpfs_clk_periph.c | 187 drivers/net/macb.c| 144 +++- drivers/net/macb.h| 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip-mpfs-clock.h | 45 + 23 files changed, 2108 insertions(+), 62 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h -- 2.17.1
[PATCH v7 1/7] riscv: Add DMA 64-bit address support
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel Reviewed-by: Bin Meng --- arch/riscv/Kconfig | 4 arch/riscv/include/asm/types.h | 4 2 files changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 30b05408b1..55eaee2da6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,10 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + default y if 64BIT + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1
Re: [PATCH v6 4/7] clk: Add Microchip PolarFire SoC clock driver
Hi Simon,
On Sat, Dec 19, 2020 at 7:58 AM Simon Glass wrote:
> Hi Padmarao,
>
> On Mon, 14 Dec 2020 at 04:09, Padmarao Begari
> wrote:
> >
> > Add clock driver code for the Microchip PolarFire SoC. This driver
> > handles reset and clock control of the Microchip PolarFire SoC device.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-by: Anup Patel
> > ---
> > drivers/clk/Kconfig | 1 +
> > drivers/clk/Makefile | 1 +
> > drivers/clk/microchip/Kconfig | 5 +
> > drivers/clk/microchip/Makefile| 1 +
> > drivers/clk/microchip/mpfs_clk.c | 127 +
> > drivers/clk/microchip/mpfs_clk.h | 19 ++
> > drivers/clk/microchip/mpfs_clk_cfg.c | 134 ++
> > drivers/clk/microchip/mpfs_clk_periph.c | 173 ++
> > .../dt-bindings/clock/microchip-mpfs-clock.h | 45 +
> > 9 files changed, 506 insertions(+)
> > create mode 100644 drivers/clk/microchip/Kconfig
> > create mode 100644 drivers/clk/microchip/Makefile
> > create mode 100644 drivers/clk/microchip/mpfs_clk.c
> > create mode 100644 drivers/clk/microchip/mpfs_clk.h
> > create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c
> > create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c
> > create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h
>
> Rather than allocating memory in your driver should use driver model's
> auto-alloc feature.
>
>
ok
> >
> > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > index 4dfbad7986..1161fe7b5a 100644
> > --- a/drivers/clk/Kconfig
> > +++ b/drivers/clk/Kconfig
> > @@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig"
> > source "drivers/clk/imx/Kconfig"
> > source "drivers/clk/kendryte/Kconfig"
> > source "drivers/clk/meson/Kconfig"
> > +source "drivers/clk/microchip/Kconfig"
> > source "drivers/clk/mvebu/Kconfig"
> > source "drivers/clk/owl/Kconfig"
> > source "drivers/clk/renesas/Kconfig"
> > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> > index d1e295ac7c..bd8a6eed88 100644
> > --- a/drivers/clk/Makefile
> > +++ b/drivers/clk/Makefile
> > @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
> > obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
> > obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
> > obj-$(CONFIG_CLK_K210) += kendryte/
> > +obj-$(CONFIG_CLK_MPFS) += microchip/
> > obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
> > obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
> > obj-$(CONFIG_CLK_OWL) += owl/
> > diff --git a/drivers/clk/microchip/Kconfig
> b/drivers/clk/microchip/Kconfig
> > new file mode 100644
> > index 00..b70241559d
> > --- /dev/null
> > +++ b/drivers/clk/microchip/Kconfig
> > @@ -0,0 +1,5 @@
> > +config CLK_MPFS
> > + bool "Clock support for Microchip PolarFire SoC"
> > + depends on CLK && CLK_CCF
> > + help
> > + This enables support clock driver for Microchip PolarFire SoC
> platform.
> > diff --git a/drivers/clk/microchip/Makefile
> b/drivers/clk/microchip/Makefile
> > new file mode 100644
> > index 00..904b345d75
> > --- /dev/null
> > +++ b/drivers/clk/microchip/Makefile
> > @@ -0,0 +1 @@
> > +obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
> > diff --git a/drivers/clk/microchip/mpfs_clk.c
> b/drivers/clk/microchip/mpfs_clk.c
> > new file mode 100644
> > index 00..1b1b66ef64
> > --- /dev/null
> > +++ b/drivers/clk/microchip/mpfs_clk.c
> > @@ -0,0 +1,127 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2020 Microchip Technology Inc.
> > + * Padmarao Begari
> > + */
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include "mpfs_clk.h"
> > +
> > +/* All methods are delegated to CCF clocks */
> > +
> > +static ulong mpfs_clk_get_rate(struct clk *clk)
> > +{
> > + struct clk *c;
> > + int err = clk_get_by_id(clk->id, );
> > +
> > + if (err)
> > + return err;
> > + return clk_get_rate(c);
> > +}
> > +
> > +static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate)
> > +{
> > +
[PATCH v6 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 816
3 files changed, 826 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 915f1be8a5..08c167b6b5 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -17,6 +17,7 @@ Board-specific doc
google/index
intel/index
kontron/index
+ microchip/index
renesas/index
rockchip/index
sifive/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..affc5a9e01
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+=
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..fe1c8d45c9
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,816 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building U-Boot
+---
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware (Microchip
+boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin
embedded)
+as HSS payload (Custom boot-flow)
+
+Microchip boot-flow
+---
+HSS with OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux (S-Mode)
+
+Build the HSS (Hart Software Services) - Microchip boot-flow
+
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+ make BOARD=icicle-kit-es config
+
+Alternatively, copy the default config for Microchip boot-flow.
+
+.. code-block:: none
+
+ cp boards/icicle-kit-es/def_config .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+ various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+Creating the HSS payload - Microchip boot-flow
+--
+1. You will be creating a payload from `u-boot-dtb.bin`.
+ Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+ cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the
binary file.
+
+ hart-entry-points: {u54_1: '0x8020', u54_2: '0x8020',
+ u54_3: '0x8020', u54_4: '0x8020'}
+
+ payloads:
+ test/u-boot-dtb.bin: {exec-addr: '0x8020', owner-hart: u54_1,
+ secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart:
u54_4,
+ priv-mode: prv_s}
+
+4. Generate payload
+
+.. code-block:: none
+
+ ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at
https://github.com/polarfire-soc/hart-software-services/blob/master/tools/hss-payload-generator/README.md)
+
+Custom boot-flow
+
+HSS without OpenSBI (M-Mode) -> OpenSBI (M-Mode) -> U-Boot (S-Mode) -> Linux
(S-Mode)
+
+Build OpenSBI
+
[PATCH v6 6/7] riscv: Add Microchip MPFS Icicle Kit support
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
board/microchip/mpfs_icicle/Kconfig | 23 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60 +-
4 files changed, 146 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..4678462378 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,30 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..0e34409067 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -6,10 +6,49 @@
#include
#include
+#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+ /*
+* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /*
+* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +61,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr,
6);
+ if (ret) {
+ printf("No local-mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property\n");
+ return -ENODEV;
+ }
+
+ icicle_mac_ad
[PATCH v6 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
3 files changed, 436 insertions(+)
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..01331b0aa1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
new file mode 100644
index 00..f60283fb6b
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+
+/ {
+ aliases {
+ cpu1 =
+ cpu2 =
+ cpu3 =
+ cpu4 =
+ };
+};
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 00..e2b9decc94
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip-mpfs-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip MPFS Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells
[PATCH v6 3/7] net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 626ee49227..9b45187e5a 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -531,6 +531,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1311,6 +1317,7 @@ static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
int ret;
@@ -1323,6 +1330,12 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Read phyaddr from DT */
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args))
+ macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
+"reg", -1);
+
macb->regs = (void *)pdata->iobase;
macb->is_big_endian = (cpu_to_be32(0x12345678) == 0x12345678);
--
2.17.1
[PATCH v6 4/7] clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/microchip/Kconfig | 5 +
drivers/clk/microchip/Makefile| 1 +
drivers/clk/microchip/mpfs_clk.c | 127 +
drivers/clk/microchip/mpfs_clk.h | 19 ++
drivers/clk/microchip/mpfs_clk_cfg.c | 134 ++
drivers/clk/microchip/mpfs_clk_periph.c | 173 ++
.../dt-bindings/clock/microchip-mpfs-clock.h | 45 +
9 files changed, 506 insertions(+)
create mode 100644 drivers/clk/microchip/Kconfig
create mode 100644 drivers/clk/microchip/Makefile
create mode 100644 drivers/clk/microchip/mpfs_clk.c
create mode 100644 drivers/clk/microchip/mpfs_clk.h
create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c
create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c
create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..1161fe7b5a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
+source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..bd8a6eed88 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
+obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
new file mode 100644
index 00..b70241559d
--- /dev/null
+++ b/drivers/clk/microchip/Kconfig
@@ -0,0 +1,5 @@
+config CLK_MPFS
+ bool "Clock support for Microchip PolarFire SoC"
+ depends on CLK && CLK_CCF
+ help
+ This enables support clock driver for Microchip PolarFire SoC
platform.
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 00..904b345d75
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1 @@
+obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
new file mode 100644
index 00..1b1b66ef64
--- /dev/null
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mpfs_clk.h"
+
+/* All methods are delegated to CCF clocks */
+
+static ulong mpfs_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, );
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int mpfs_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int mpfs_clk_enable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, true);
+}
+
+static int mpfs_clk_disable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, false);
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+ int ret;
+ void __iomem *base;
+ u32 clk_rate;
+ struct clk *clk;
+ const char *parent_clk_name;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -ENODEV;
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 0, clk);
+
[PATCH v6 2/7] net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
hardware compatibility and it is configured with structure macb_config
in the driver.
The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit
DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit
not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index b80a259ff7..626ee49227 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -83,7 +83,16 @@ struct macb_dma_desc {
u32 ctrl;
};
-#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
+struct macb_dma_desc_64 {
+ u32 addrh;
+ u32 unused;
+};
+
+#define HW_DMA_CAP_32B 0
+#define HW_DMA_CAP_64B 1
+
+#define DMA_DESC_SIZE 16
+#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
@@ -137,6 +146,7 @@ struct macb_device {
struct macb_config {
unsigned intdma_burst_length;
+ unsigned inthw_dma_cap;
int (*clk_init)(struct udevice *dev, ulong rate);
};
@@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct
macb_device *macb)
#if defined(CONFIG_CMD_NET)
+static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
+{
+ return (struct macb_dma_desc_64 *)((void *)desc
+ + sizeof(struct macb_dma_desc));
+}
+
+static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
+ ulong addr)
+{
+ struct macb_dma_desc_64 *desc_64;
+
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ desc_64 = macb_64b_desc(desc);
+ desc_64->addrh = upper_32_bits(addr);
+ }
+ desc->addr = lower_32_bits(addr);
+}
+
static int _macb_send(struct macb_device *macb, const char *name, void *packet,
int length)
{
@@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
macb->tx_head++;
}
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ tx_head = tx_head * 2;
+
macb->tx_ring[tx_head].ctrl = ctrl;
- macb->tx_ring[tx_head].addr = paddr;
+ macb_set_addr(macb, >tx_ring[tx_head], paddr);
+
barrier();
macb_flush_ring_desc(macb, TX);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
@@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device *macb,
unsigned int new_tail)
{
unsigned int i;
+ unsigned int count;
i = macb->rx_tail;
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
void *buffer;
int length;
u32 status;
+ u8 flag = false;
macb->wrapped = false;
for (;;) {
macb_invalidate_ring_desc(macb, RX);
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B)
+ next_rx_tail = next_rx_tail * 2;
+
if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
if (status & MACB_BIT(RX_SOF)) {
+ if (macb->config->hw_dma_cap & HW_DMA_CAP_64B) {
+ next_rx_tail = next_rx_tail / 2;
+ flag = true;
+ }
+
if (next_rx_tail != macb->rx_tail)
reclaim_rx_buffer
[PATCH v6 0/7] Microchip PolarFire SoC support
This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id 5a1a8a63be8f7262a300eddafb18020926b12fb6 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Changes in v6: - Update MACB driver for 32-bit/64-bit DMA based on struct mac_config - Rename microchip,mpfs-clock.h to microchip-mpfs-clock.h - Add dual-license GPL or MIT in the clock dt-binding - Move refclk device tree node under / device tree node - Remove the dtc warnings - Fix some typos in device tree and doc Changes in v5: - Replace compatible string "microchip,polarfire-soc" with "microchip,mpfs-icicle-kit" in the device tree - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" - Fix some typos in doc - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* - Rename pfsoc-clock.h to mpfs-clock.h Changes in v4: - Add dual-license GPL or MIT in the device tree - Replace microsemi compatible strings with microchip - Add MACB compatible string for Microchip PolarFire SoC ethernet - Update MACB driver for 32-bit/64-bit DMA based on compatible string Changes in v3: - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT - Update MACB driver for 32-bit/64-bit DMA based on design config register - Add phy-handle in MACB driver to read the phy address from device tree - Fix checkpatch warnings in the clock driver - Remove fu540 related compatible strings from soc device tree node - Move refclk device tree node under /soc device tree node - Use local-mac-address instead of mac-address in the device tree - Rename device tree to microchip-mpfs-icicle-kit.dts - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file - Drop the imply DMA_ADDR_T_64BIT from board config - Fix some typos - Update doc with Microchip and Custom boot-flow Changes in v2: - Add clock frequency for the clint device tree node - Move peripheral device tree nodes under /soc device tree node - Device tree nodes are in order based on the address - Enable UART0 for U-Boot logs - Update doc for the U-Boot logs are on UART0 - Move clock and reset index source into patch4 - Remove "dma_addr_r" type in the macb driver - Add lower_32_bits() for 32-bit address in the macb driver - Add set_rate() returns the new clock rate in the clock driver Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig| 4 + arch/riscv/dts/Makefile | 1 + .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 + arch/riscv/include/asm/types.h| 4 + board/microchip/mpfs_icicle/Kconfig | 23 + board/microchip/mpfs_icicle/mpfs_icicle.c | 99 ++- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 816 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile| 1 + drivers/clk/microchip/mpfs_clk.c | 127 +++ drivers/clk/microchip/mpfs_clk.h | 19 + drivers/clk/microchip/mpfs_clk_cfg.c | 134 +++ drivers/clk/microchip/mpfs_clk_periph.c | 173 drivers/net/macb.c| 144 +++- drivers/net/macb.h| 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip-mpfs-clock.h | 45 + 23 files changed, 2055 insertions(+), 62 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c create mode 100644 include/dt-bindings/clock/microchip-mpfs-clock.h -- 2.17.1
[PATCH v6 1/7] riscv: Add DMA 64-bit address support
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel --- arch/riscv/Kconfig | 4 arch/riscv/include/asm/types.h | 4 2 files changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 30b05408b1..55eaee2da6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,10 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + default y if 64BIT + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1
Re: [PATCH v5 1/7] riscv: Add DMA 64-bit address support
Hi Bin, On Fri, Dec 11, 2020 at 2:57 PM Bin Meng wrote: > HI Padmarao, > > On Fri, Dec 11, 2020 at 4:23 PM Padmarao Begari > wrote: > > > > Hi Bin, > > > > On Fri, Dec 11, 2020 at 1:22 PM Bin Meng wrote: > >> > >> Hi Padmarao, > >> > >> On Fri, Dec 11, 2020 at 3:10 PM Padmarao Begari > wrote: > >> > > >> > Hi Bin, > >> > > >> > On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote: > >> >> > >> >> Hi Padmarao, > >> >> > >> >> On Thu, Dec 3, 2020 at 4:43 AM Padmarao Begari > >> >> wrote: > >> >> > > >> >> > dma_addr_t holds any valid DMA address. If the DMA API only uses > 32/64-bit > >> >> > addresses, dma_addr_t need only be 32/64 bits wide. > >> >> > > >> >> > Signed-off-by: Padmarao Begari > >> >> > Reviewed-by: Anup Patel > >> >> > --- > >> >> > arch/riscv/Kconfig | 4 > >> >> > arch/riscv/include/asm/types.h | 4 > >> >> > 2 files changed, 8 insertions(+) > >> >> > > >> >> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > >> >> > index 30b05408b1..55eaee2da6 100644 > >> >> > --- a/arch/riscv/Kconfig > >> >> > +++ b/arch/riscv/Kconfig > >> >> > @@ -152,6 +152,10 @@ config 32BIT > >> >> > config 64BIT > >> >> > bool > >> >> > > >> >> > +config DMA_ADDR_T_64BIT > >> >> > + bool > >> >> > + default y if 64BIT > >> >> > + > >> >> > config SIFIVE_CLINT > >> >> > bool > >> >> > depends on RISCV_MMODE || SPL_RISCV_MMODE > >> >> > diff --git a/arch/riscv/include/asm/types.h > b/arch/riscv/include/asm/types.h > >> >> > index 403cf9a48f..b800b2d221 100644 > >> >> > --- a/arch/riscv/include/asm/types.h > >> >> > +++ b/arch/riscv/include/asm/types.h > >> >> > @@ -29,7 +29,11 @@ typedef unsigned short umode_t; > >> >> > > >> >> > #include > >> >> > > >> >> > +#ifdef CONFIG_DMA_ADDR_T_64BIT > >> >> > +typedef u64 dma_addr_t; > >> >> > +#else > >> >> > typedef u32 dma_addr_t; > >> >> > +#endif > >> >> > >> >> Why is this patch needed for U-Boot? > >> >> > >> > > >> > Initially this patch was created for the MACB driver dependency and > now the MACB driver is not dependent on CONFIG_DMA_ADDR_T_64BIT. > >> > But We created this patch the same as the ARM 64-bit kconfig and the > 'CONFIG_DMA_ADDR_T_64BIT' is used when the MMC driver is configured with > DMA. > >> > > >> > >> But in U-Boot there is no 64-bit address. The DMA address should be > >> under 4G. Both MACB and MMC driver should work with the 32-bit DMA > >> addresses, no? > >> > > > > We will use 64-bit addresses in the future. > > But U-Boot does not generate 64-bit addresses for DMA at present. > > PolarFire SoC GEM uses 64-bit DMA not 32-bit DMA Regards Padmarao > > Both MACB and MMC drivers work with 64-bit DMA addresses in the > PolarFire SoC. > > So I think the patch to enable 64-bit DMA in U-Boot is not necessary. > > Regards, > Bin >
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Bin,
On Fri, Dec 11, 2020 at 2:59 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 4:49 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
> >>
> >> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >> >
> >> > Hi Padmarao,
> >> >
> >> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> >> > wrote:
> >> > >
> >> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
> >> > > compatible string of the device tree node.
> >> > >
> >> > > Signed-off-by: Padmarao Begari
> >> > > Reviewed-by: Anup Patel
> >> > > ---
> >> > > drivers/net/macb.c | 131
> +++--
> >> > > drivers/net/macb.h | 6 +++
> >> > > 2 files changed, 120 insertions(+), 17 deletions(-)
> >> > >
> >> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> >> > > index b80a259ff7..e7c93d4747 100644
> >> > > --- a/drivers/net/macb.c
> >> > > +++ b/drivers/net/macb.c
> >> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
> >> > > u32 ctrl;
> >> > > };
> >> > >
> >> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
> >> > > +struct macb_dma_desc_64 {
> >> > > + u32 addrh;
> >> > > + u32 unused;
> >> > > +};
> >> > > +
> >> > > +#define HW_DMA_CAP_32B 0
> >> > > +#define HW_DMA_CAP_64B 1
> >> > > +
> >> > > +#define DMA_DESC_SIZE 16
> >> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
> >> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
> >> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
> >> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
> >> > > @@ -133,6 +142,7 @@ struct macb_device {
> >> > > #endif
> >> > > phy_interface_t phy_interface;
> >> > > #endif
> >> > > + unsigned short hw_dma_cap;
> >> > > };
> >> > >
> >> > > struct macb_config {
> >> > > @@ -307,6 +317,24 @@ static inline void
> macb_invalidate_rx_buffer(struct macb_device *macb)
> >> > >
> >> > > #if defined(CONFIG_CMD_NET)
> >> > >
> >> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
> *desc)
> >> > > +{
> >> > > + return (struct macb_dma_desc_64 *)((void *)desc
> >> > > + + sizeof(struct macb_dma_desc));
> >> > > +}
> >> > > +
> >> > > +static void macb_set_addr(struct macb_device *macb, struct
> macb_dma_desc *desc,
> >> > > + ulong addr)
> >> > > +{
> >> > > + struct macb_dma_desc_64 *desc_64;
> >> > > +
> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
> >> > > + desc_64 = macb_64b_desc(desc);
> >> > > + desc_64->addrh = upper_32_bits(addr);
> >> > > + }
> >> > > + desc->addr = lower_32_bits(addr);
> >> > > +}
> >> > > +
> >> > > static int _macb_send(struct macb_device *macb, const char *name,
> void *packet,
> >> > > int length)
> >> > > {
> >> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device
> *macb, const char *name, void *packet,
> >> > > macb->tx_head++;
> >> > > }
> >> > >
> >> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> >> > > + tx_head = tx_head * 2;
> >> > > +
> >> > > macb->tx_ring[tx_head].ctrl = ctrl;
> >> > > - macb->tx_ring[tx_head].addr = paddr;
> >> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
> >> > > +
> >> > > barrier();
> >> > > macb_flush_ring_desc(macb, TX);
> >> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB
Re: [PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Bin,
On Fri, Dec 11, 2020 at 2:55 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Dec 11, 2020 at 4:32 PM Padmarao Begari
> wrote:
> >
> > Hi Bin,
> >
> > On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
> >>
> >> Hi Padmarao,
> >>
> >> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> >> wrote:
> >> >
> >> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >> >
> >> > Signed-off-by: Padmarao Begari
> >> > Reviewed-by: Anup Patel
> >>
> >> Sorry 2 more warnings, please check below:
> >>
> >> > ---
> >> > arch/riscv/dts/Makefile | 1 +
> >> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
> >> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421
> ++
> >> > 3 files changed, 436 insertions(+)
> >> > create mode 100644
> arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> >> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >> >
> >> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> >> > index 3a6f96c67d..01331b0aa1 100644
> >> > --- a/arch/riscv/dts/Makefile
> >> > +++ b/arch/riscv/dts/Makefile
> >> > @@ -3,6 +3,7 @@
> >> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> >> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> >> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> >> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) +=
> microchip-mpfs-icicle-kit.dtb
> >> >
> >> > targets += $(dtb-y)
> >> >
> >> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> >> > new file mode 100644
> >> > index 00..f60283fb6b
> >> > --- /dev/null
> >> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> >> > @@ -0,0 +1,14 @@
> >> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> > +/*
> >> > + * Copyright (C) 2020 Microchip Technology Inc.
> >> > + * Padmarao Begari
> >> > + */
> >> > +
> >> > +/ {
> >> > + aliases {
> >> > + cpu1 =
> >> > + cpu2 =
> >> > + cpu3 =
> >> > + cpu4 =
> >> > + };
> >> > +};
> >> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >> > new file mode 100644
> >> > index 00..f5478bf201
> >> > --- /dev/null
> >> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >> > @@ -0,0 +1,421 @@
> >> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> > +/* Copyright (c) 2020 Microchip Technology Inc */
> >> > +
> >> > +/dts-v1/;
> >> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
> >> > +
> >> > +/* Clock frequency (in Hz) of the rtcclk */
> >> > +#define RTCCLK_FREQ100
> >> > +
> >> > +/ {
> >> > + #address-cells = <2>;
> >> > + #size-cells = <2>;
> >> > + model = "Microchip MPFS Icicle Kit";
> >> > + compatible = "microchip,mpfs-icicle-kit";
> >> > +
> >> > + aliases {
> >> > + serial0 =
> >> > + ethernet0 =
> >> > + };
> >> > +
> >> > + chosen {
> >> > + stdout-path = "serial0";
> >> > + };
> >> > +
> >> > + cpucomplex: cpus {
> >> > + #address-cells = <1>;
> >> > + #size-cells = <0>;
> >> > + timebase-frequency = ;
> >> > + cpu0: cpu@0 {
> >> > + clocks = < CLK_CPU>;
> >> > + compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> >> > + device_type = "cpu";
> >> > + i-cache-block-size = <64>;
> >> > + i-cache-sets = <128>;
> >> > + i-cache
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Bin,
On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >
> > Hi Padmarao,
> >
> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> > wrote:
> > >
> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
> > > compatible string of the device tree node.
> > >
> > > Signed-off-by: Padmarao Begari
> > > Reviewed-by: Anup Patel
> > > ---
> > > drivers/net/macb.c | 131 +++--
> > > drivers/net/macb.h | 6 +++
> > > 2 files changed, 120 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> > > index b80a259ff7..e7c93d4747 100644
> > > --- a/drivers/net/macb.c
> > > +++ b/drivers/net/macb.c
> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
> > > u32 ctrl;
> > > };
> > >
> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
> > > +struct macb_dma_desc_64 {
> > > + u32 addrh;
> > > + u32 unused;
> > > +};
> > > +
> > > +#define HW_DMA_CAP_32B 0
> > > +#define HW_DMA_CAP_64B 1
> > > +
> > > +#define DMA_DESC_SIZE 16
> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
> > > @@ -133,6 +142,7 @@ struct macb_device {
> > > #endif
> > > phy_interface_t phy_interface;
> > > #endif
> > > + unsigned short hw_dma_cap;
> > > };
> > >
> > > struct macb_config {
> > > @@ -307,6 +317,24 @@ static inline void
> macb_invalidate_rx_buffer(struct macb_device *macb)
> > >
> > > #if defined(CONFIG_CMD_NET)
> > >
> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
> *desc)
> > > +{
> > > + return (struct macb_dma_desc_64 *)((void *)desc
> > > + + sizeof(struct macb_dma_desc));
> > > +}
> > > +
> > > +static void macb_set_addr(struct macb_device *macb, struct
> macb_dma_desc *desc,
> > > + ulong addr)
> > > +{
> > > + struct macb_dma_desc_64 *desc_64;
> > > +
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
> > > + desc_64 = macb_64b_desc(desc);
> > > + desc_64->addrh = upper_32_bits(addr);
> > > + }
> > > + desc->addr = lower_32_bits(addr);
> > > +}
> > > +
> > > static int _macb_send(struct macb_device *macb, const char *name,
> void *packet,
> > > int length)
> > > {
> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb,
> const char *name, void *packet,
> > > macb->tx_head++;
> > > }
> > >
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + tx_head = tx_head * 2;
> > > +
> > > macb->tx_ring[tx_head].ctrl = ctrl;
> > > - macb->tx_ring[tx_head].addr = paddr;
> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
> > > +
> > > barrier();
> > > macb_flush_ring_desc(macb, TX);
> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) |
> MACB_BIT(TSTART));
> > > @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct
> macb_device *macb,
> > >unsigned int new_tail)
> > > {
> > > unsigned int i;
> > > + unsigned int count;
> > >
> > > i = macb->rx_tail;
> > >
> > > macb_invalidate_ring_desc(macb, RX);
> > > while (i > new_tail) {
> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + count = i * 2;
> > > + else
> > > + count = i;
> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> > > i++;
> > > if (i > MACB_RX_RING_SIZE)
>
Re: [PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Hi Bin,
On Thu, Dec 10, 2020 at 4:08 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 10, 2020 at 6:33 PM Bin Meng wrote:
> >
> > Hi Padmarao,
> >
> > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> > wrote:
> > >
> > > Enable 32-bit or 64-bit DMA in the macb driver based on the macb
> > > compatible string of the device tree node.
> > >
> > > Signed-off-by: Padmarao Begari
> > > Reviewed-by: Anup Patel
> > > ---
> > > drivers/net/macb.c | 131 +++--
> > > drivers/net/macb.h | 6 +++
> > > 2 files changed, 120 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> > > index b80a259ff7..e7c93d4747 100644
> > > --- a/drivers/net/macb.c
> > > +++ b/drivers/net/macb.c
> > > @@ -83,7 +83,16 @@ struct macb_dma_desc {
> > > u32 ctrl;
> > > };
> > >
> > > -#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
> > > +struct macb_dma_desc_64 {
> > > + u32 addrh;
> > > + u32 unused;
> > > +};
> > > +
> > > +#define HW_DMA_CAP_32B 0
> > > +#define HW_DMA_CAP_64B 1
> > > +
> > > +#define DMA_DESC_SIZE 16
> > > +#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
> > > #define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
> > > #define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
> > > #define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
> > > @@ -133,6 +142,7 @@ struct macb_device {
> > > #endif
> > > phy_interface_t phy_interface;
> > > #endif
> > > + unsigned short hw_dma_cap;
> > > };
> > >
> > > struct macb_config {
> > > @@ -307,6 +317,24 @@ static inline void
> macb_invalidate_rx_buffer(struct macb_device *macb)
> > >
> > > #if defined(CONFIG_CMD_NET)
> > >
> > > +static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc
> *desc)
> > > +{
> > > + return (struct macb_dma_desc_64 *)((void *)desc
> > > + + sizeof(struct macb_dma_desc));
> > > +}
> > > +
> > > +static void macb_set_addr(struct macb_device *macb, struct
> macb_dma_desc *desc,
> > > + ulong addr)
> > > +{
> > > + struct macb_dma_desc_64 *desc_64;
> > > +
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
> > > + desc_64 = macb_64b_desc(desc);
> > > + desc_64->addrh = upper_32_bits(addr);
> > > + }
> > > + desc->addr = lower_32_bits(addr);
> > > +}
> > > +
> > > static int _macb_send(struct macb_device *macb, const char *name,
> void *packet,
> > > int length)
> > > {
> > > @@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb,
> const char *name, void *packet,
> > > macb->tx_head++;
> > > }
> > >
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + tx_head = tx_head * 2;
> > > +
> > > macb->tx_ring[tx_head].ctrl = ctrl;
> > > - macb->tx_ring[tx_head].addr = paddr;
> > > + macb_set_addr(macb, >tx_ring[tx_head], paddr);
> > > +
> > > barrier();
> > > macb_flush_ring_desc(macb, TX);
> > > macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) |
> MACB_BIT(TSTART));
> > > @@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct
> macb_device *macb,
> > >unsigned int new_tail)
> > > {
> > > unsigned int i;
> > > + unsigned int count;
> > >
> > > i = macb->rx_tail;
> > >
> > > macb_invalidate_ring_desc(macb, RX);
> > > while (i > new_tail) {
> > > - macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
> > > + if (macb->hw_dma_cap & HW_DMA_CAP_64B)
> > > + count = i * 2;
> > > + else
> > > + count = i;
> > > + macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
> > > i++;
> > > if (i > MACB_RX_RING_SIZE)
>
Re: [PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Bin,
On Fri, Dec 11, 2020 at 1:31 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-by: Anup Patel
>
> Sorry 2 more warnings, please check below:
>
> > ---
> > arch/riscv/dts/Makefile | 1 +
> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
> > 3 files changed, 436 insertions(+)
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..01331b0aa1 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
> >
> > targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > new file mode 100644
> > index 00..f60283fb6b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2020 Microchip Technology Inc.
> > + * Padmarao Begari
> > + */
> > +
> > +/ {
> > + aliases {
> > + cpu1 =
> > + cpu2 =
> > + cpu3 =
> > + cpu4 =
> > + };
> > +};
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > new file mode 100644
> > index 00..f5478bf201
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,421 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip MPFS Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + aliases {
> > + serial0 =
> > + ethernet0 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0";
> > + };
> > +
> > + cpucomplex: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = ;
> > + cpu0: cpu@0 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > + operating-points = <
> > + /* kHz uV */
> > + 60 110
> > + 30 95
> > + 15 75
> > + >;
> > + cpu0intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu1: cpu@1 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,u54-mc", &quo
Re: [PATCH v5 1/7] riscv: Add DMA 64-bit address support
Hi Bin, On Fri, Dec 11, 2020 at 1:22 PM Bin Meng wrote: > Hi Padmarao, > > On Fri, Dec 11, 2020 at 3:10 PM Padmarao Begari > wrote: > > > > Hi Bin, > > > > On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote: > >> > >> Hi Padmarao, > >> > >> On Thu, Dec 3, 2020 at 4:43 AM Padmarao Begari > >> wrote: > >> > > >> > dma_addr_t holds any valid DMA address. If the DMA API only uses > 32/64-bit > >> > addresses, dma_addr_t need only be 32/64 bits wide. > >> > > >> > Signed-off-by: Padmarao Begari > >> > Reviewed-by: Anup Patel > >> > --- > >> > arch/riscv/Kconfig | 4 > >> > arch/riscv/include/asm/types.h | 4 > >> > 2 files changed, 8 insertions(+) > >> > > >> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > >> > index 30b05408b1..55eaee2da6 100644 > >> > --- a/arch/riscv/Kconfig > >> > +++ b/arch/riscv/Kconfig > >> > @@ -152,6 +152,10 @@ config 32BIT > >> > config 64BIT > >> > bool > >> > > >> > +config DMA_ADDR_T_64BIT > >> > + bool > >> > + default y if 64BIT > >> > + > >> > config SIFIVE_CLINT > >> > bool > >> > depends on RISCV_MMODE || SPL_RISCV_MMODE > >> > diff --git a/arch/riscv/include/asm/types.h > b/arch/riscv/include/asm/types.h > >> > index 403cf9a48f..b800b2d221 100644 > >> > --- a/arch/riscv/include/asm/types.h > >> > +++ b/arch/riscv/include/asm/types.h > >> > @@ -29,7 +29,11 @@ typedef unsigned short umode_t; > >> > > >> > #include > >> > > >> > +#ifdef CONFIG_DMA_ADDR_T_64BIT > >> > +typedef u64 dma_addr_t; > >> > +#else > >> > typedef u32 dma_addr_t; > >> > +#endif > >> > >> Why is this patch needed for U-Boot? > >> > > > > Initially this patch was created for the MACB driver dependency and now > the MACB driver is not dependent on CONFIG_DMA_ADDR_T_64BIT. > > But We created this patch the same as the ARM 64-bit kconfig and the > 'CONFIG_DMA_ADDR_T_64BIT' is used when the MMC driver is configured with > DMA. > > > > But in U-Boot there is no 64-bit address. The DMA address should be > under 4G. Both MACB and MMC driver should work with the 32-bit DMA > addresses, no? > > We will use 64-bit addresses in the future. Both MACB and MMC drivers work with 64-bit DMA addresses in the PolarFire SoC. Regards Padmarao > Regards, > Bin >
Re: [PATCH v5 1/7] riscv: Add DMA 64-bit address support
Hi Bin, On Thu, Dec 10, 2020 at 4:11 PM Bin Meng wrote: > Hi Padmarao, > > On Thu, Dec 3, 2020 at 4:43 AM Padmarao Begari > wrote: > > > > dma_addr_t holds any valid DMA address. If the DMA API only uses > 32/64-bit > > addresses, dma_addr_t need only be 32/64 bits wide. > > > > Signed-off-by: Padmarao Begari > > Reviewed-by: Anup Patel > > --- > > arch/riscv/Kconfig | 4 > > arch/riscv/include/asm/types.h | 4 > > 2 files changed, 8 insertions(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 30b05408b1..55eaee2da6 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -152,6 +152,10 @@ config 32BIT > > config 64BIT > > bool > > > > +config DMA_ADDR_T_64BIT > > + bool > > + default y if 64BIT > > + > > config SIFIVE_CLINT > > bool > > depends on RISCV_MMODE || SPL_RISCV_MMODE > > diff --git a/arch/riscv/include/asm/types.h > b/arch/riscv/include/asm/types.h > > index 403cf9a48f..b800b2d221 100644 > > --- a/arch/riscv/include/asm/types.h > > +++ b/arch/riscv/include/asm/types.h > > @@ -29,7 +29,11 @@ typedef unsigned short umode_t; > > > > #include > > > > +#ifdef CONFIG_DMA_ADDR_T_64BIT > > +typedef u64 dma_addr_t; > > +#else > > typedef u32 dma_addr_t; > > +#endif > > Why is this patch needed for U-Boot? > > Initially this patch was created for the MACB driver dependency and now the MACB driver is not dependent on CONFIG_DMA_ADDR_T_64BIT. But We created this patch the same as the ARM 64-bit kconfig and the 'CONFIG_DMA_ADDR_T_64BIT' is used when the MMC driver is configured with DMA. Regards Padmarao > Regards, > Bin >
Re: [PATCH v5 4/7] clk: Add Microchip PolarFire SoC clock driver
Hi Bin, On Thu, Dec 10, 2020 at 4:25 PM Bin Meng wrote: > On Thu, Dec 10, 2020 at 6:04 PM Bin Meng wrote: > > > > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari > > wrote: > > > > > > Add clock driver code for the Microchip PolarFire SoC. This driver > > > handles reset and clock control of the Microchip PolarFire SoC device. > > > > > > Signed-off-by: Padmarao Begari > > > Reviewed-by: Anup Patel > > > --- > > > drivers/clk/Kconfig | 1 + > > > drivers/clk/Makefile | 1 + > > > drivers/clk/microchip/Kconfig | 5 + > > > drivers/clk/microchip/Makefile| 1 + > > > drivers/clk/microchip/mpfs_clk.c | 127 + > > > drivers/clk/microchip/mpfs_clk.h | 19 ++ > > > drivers/clk/microchip/mpfs_clk_cfg.c | 134 ++ > > > drivers/clk/microchip/mpfs_clk_periph.c | 173 ++ > > > .../dt-bindings/clock/microchip,mpfs-clock.h | 45 + > > > 9 files changed, 506 insertions(+) > > > create mode 100644 drivers/clk/microchip/Kconfig > > > create mode 100644 drivers/clk/microchip/Makefile > > > create mode 100644 drivers/clk/microchip/mpfs_clk.c > > > create mode 100644 drivers/clk/microchip/mpfs_clk.h > > > create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c > > > create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c > > > create mode 100644 include/dt-bindings/clock/microchip,mpfs-clock.h > > > > > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig > > > index 4dfbad7986..1161fe7b5a 100644 > > > --- a/drivers/clk/Kconfig > > > +++ b/drivers/clk/Kconfig > > > @@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig" > > > source "drivers/clk/imx/Kconfig" > > > source "drivers/clk/kendryte/Kconfig" > > > source "drivers/clk/meson/Kconfig" > > > +source "drivers/clk/microchip/Kconfig" > > > source "drivers/clk/mvebu/Kconfig" > > > source "drivers/clk/owl/Kconfig" > > > source "drivers/clk/renesas/Kconfig" > > > diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile > > > index d1e295ac7c..bd8a6eed88 100644 > > > --- a/drivers/clk/Makefile > > > +++ b/drivers/clk/Makefile > > > @@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/ > > > obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/ > > > obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o > > > obj-$(CONFIG_CLK_K210) += kendryte/ > > > +obj-$(CONFIG_CLK_MPFS) += microchip/ > > > obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o > > > obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o > > > obj-$(CONFIG_CLK_OWL) += owl/ > > > diff --git a/drivers/clk/microchip/Kconfig > b/drivers/clk/microchip/Kconfig > > > new file mode 100644 > > > index 00..b70241559d > > > --- /dev/null > > > +++ b/drivers/clk/microchip/Kconfig > > > @@ -0,0 +1,5 @@ > > > +config CLK_MPFS > > > + bool "Clock support for Microchip PolarFire SoC" > > > + depends on CLK && CLK_CCF > > > + help > > > + This enables support clock driver for Microchip PolarFire > SoC platform. > > > diff --git a/drivers/clk/microchip/Makefile > b/drivers/clk/microchip/Makefile > > > new file mode 100644 > > > index 00..904b345d75 > > > --- /dev/null > > > +++ b/drivers/clk/microchip/Makefile > > > @@ -0,0 +1 @@ > > > +obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o > > > diff --git a/drivers/clk/microchip/mpfs_clk.c > b/drivers/clk/microchip/mpfs_clk.c > > > new file mode 100644 > > > index 00..1b1b66ef64 > > > --- /dev/null > > > +++ b/drivers/clk/microchip/mpfs_clk.c > > > @@ -0,0 +1,127 @@ > > > +// SPDX-License-Identifier: GPL-2.0+ > > > +/* > > > + * Copyright (C) 2020 Microchip Technology Inc. > > > + * Padmarao Begari > > > + */ > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > +#include > > > + > > > +#include "mpfs_clk.h" > > > + > > > +/* All methods are delegated to CCF clocks */ > > > + > > > +static u
Re: [PATCH v5 6/7] riscv: Add Microchip MPFS Icicle Kit support
Hi Bin,
On Thu, Dec 10, 2020 at 3:54 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > This patch adds Microchip MPFS Icicle Kit support. For now, only
> > NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
> > only enabled. The Microchip MPFS Icicle defconfig by default builds
>
> remove "only" because it was already said at the beginning of this sentence
>
>
Ok
> > U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
> > in S-Mode as payload of HSS + OpenSBI.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-by: Anup Patel
> > ---
> > board/microchip/mpfs_icicle/Kconfig | 24 ++
> > board/microchip/mpfs_icicle/mpfs_icicle.c | 97 ++-
> > configs/microchip_mpfs_icicle_defconfig | 9 ++-
> > include/configs/microchip_mpfs_icicle.h | 60 +-
> > 4 files changed, 145 insertions(+), 45 deletions(-)
> >
> > diff --git a/board/microchip/mpfs_icicle/Kconfig
> b/board/microchip/mpfs_icicle/Kconfig
> > index bf8e1a13ec..f4e705a07b 100644
> > --- a/board/microchip/mpfs_icicle/Kconfig
> > +++ b/board/microchip/mpfs_icicle/Kconfig
> > @@ -20,7 +20,31 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> > def_bool y
> > select GENERIC_RISCV
> > select BOARD_EARLY_INIT_F
> > + select BOARD_LATE_INIT
> > imply SMP
> > + imply CLK_CCF
> > + imply CLK_MPFS
> > imply SYS_NS16550
> > + imply CMD_DHCP
> > + imply CMD_EXT2
> > + imply CMD_EXT4
> > + imply CMD_FAT
> > + imply CMD_FS_GENERIC
> > + imply CMD_NET
> > + imply CMD_PING
> > + imply CMD_MMC
> > + imply DOS_PARTITION
> > + imply EFI_PARTITION
> > + imply IP_DYN
> > + imply ISO_PARTITION
> > + imply MACB
> > + imply MII
> > + imply NET_RANDOM_ETHADDR
>
> This should not be used since we are reading mac address from SoC.
>
> Ok, I will remove imply NET_RANDOM_ETHADDR
> + imply PHY_LIB
> > + imply PHY_VITESSE
> > + imply MMC
> > + imply MMC_WRITE
> > + imply MMC_SDHCI
> > + imply MMC_SDHCI_CADENCE
> >
> > endif
> > diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
> b/board/microchip/mpfs_icicle/mpfs_icicle.c
> > index 8381361ec3..420ea25ac2 100644
> > --- a/board/microchip/mpfs_icicle/mpfs_icicle.c
> > +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
> > @@ -6,10 +6,47 @@
> >
> > #include
> > #include
> > +#include
> > #include
> > #include
> >
> > -#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
> > +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
> > +#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
> > +#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
> > +#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
> > +
> > +#define PERIPH_RESET_VALUE 0x1e8u
> > +#define SERVICE_CR_REQ 0x1u
> > +#define SERVICE_SR_BUSY0x2u
> > +
> > +static void read_device_serial_number(u8 *response, u8 response_size)
> > +{
> > + u8 idx;
> > + u8 *response_buf;
> > + unsigned int val;
> > +
> > + response_buf = (u8 *)response;
> > +
> > + writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
> > + /*
> > +* REQ bit will remain set till the system controller starts
> > +* processing.
> > +*/
> > + do {
> > + val = readl(MPFS_SYS_SERVICE_CR);
> > + } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
> > +
> > + /*
> > +* Once system controller starts processing the busy bit will
> > +* go high and service is completed when busy bit is gone low
> > +*/
> > + do {
> > + val = readl(MPFS_SYS_SERVICE_SR);
> > + } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
> > +
> > + for (idx = 0; idx < response_size; idx++)
> > + response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX +
> idx);
> > +}
> >
> > int board_init(void)
> > {
> > @@ -22,10 +59,64 @@ int board_early_init_f(void)
> > {
> > unsigned int val;
> >
> > - /* Reset uart peripheral */
> > +
Re: [PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Bin,
On Thu, Dec 10, 2020 at 6:48 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-by: Anup Patel
> > ---
> > arch/riscv/dts/Makefile | 1 +
> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
> > 3 files changed, 436 insertions(+)
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..01331b0aa1 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
> >
> > targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > new file mode 100644
> > index 00..f60283fb6b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2020 Microchip Technology Inc.
> > + * Padmarao Begari
> > + */
> > +
> > +/ {
> > + aliases {
> > + cpu1 =
> > + cpu2 =
> > + cpu3 =
> > + cpu4 =
> > + };
> > +};
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > new file mode 100644
> > index 00..f5478bf201
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,421 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,mpfs-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip MPFS Icicle Kit";
> > + compatible = "microchip,mpfs-icicle-kit";
> > +
> > + aliases {
> > + serial0 =
> > + ethernet0 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0";
> > + };
> > +
> > + cpucomplex: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = ;
> > + cpu0: cpu@0 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > + operating-points = <
> > + /* kHz uV */
> > + 60 110
> > + 30 95
> > + 15 75
> > + >;
> > + cpu0intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu1: cpu@1 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > +
Re: [PATCH v5 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
Hi Bin, On Thu, Dec 10, 2020 at 12:08 PM Bin Meng wrote: > Hi Padmarao, > > On Thu, Dec 3, 2020 at 4:44 AM Padmarao Begari > wrote: > > > > This doc describes the procedure to build, flash and > > boot Linux using U-boot on Microchip MPFS Icicle Kit. > > > > Signed-off-by: Padmarao Begari > > Reviewed-by: Anup Patel > > --- > > doc/board/index.rst | 1 + > > doc/board/microchip/index.rst | 9 + > > doc/board/microchip/mpfs_icicle.rst | 830 > > 3 files changed, 840 insertions(+) > > create mode 100644 doc/board/microchip/index.rst > > create mode 100644 doc/board/microchip/mpfs_icicle.rst > > > > diff --git a/doc/board/index.rst b/doc/board/index.rst > > index 4b6a996eb1..e329e2744c 100644 > > --- a/doc/board/index.rst > > +++ b/doc/board/index.rst > > @@ -15,6 +15,7 @@ Board-specific doc > > freescale/index > > google/index > > intel/index > > + microchip/index > > nits: this should be inserted after kontron/index > > > kontron/index > > renesas/index > > rockchip/index > > diff --git a/doc/board/microchip/index.rst > b/doc/board/microchip/index.rst > > new file mode 100644 > > index 00..b09e6788af > > --- /dev/null > > +++ b/doc/board/microchip/index.rst > > @@ -0,0 +1,9 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Microchip > > +== > > nits: please make sure the delimiter has the same width as the sub-titles > > please fix similar issue globally in this file > > ok > > + > > +.. toctree:: > > + :maxdepth: 2 > > + > > + mpfs_icicle > > diff --git a/doc/board/microchip/mpfs_icicle.rst > b/doc/board/microchip/mpfs_icicle.rst > > new file mode 100644 > > index 00..d37b9bcb92 > > --- /dev/null > > +++ b/doc/board/microchip/mpfs_icicle.rst > > @@ -0,0 +1,830 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Microchip PolarFire SoC Icicle Kit > > +== > > + > > +RISC-V PolarFire SoC > > +- > > +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip. > > + > > +The Icicle Kit development platform is based on PolarFire SoC and > capable > > +of running Linux. > > + > > +Mainline support > > + > > +The support for following drivers are already enabled: > > + > > +1. NS16550 UART Driver. > > +2. Microchip Clock Driver. > > +3. Cadence MACB ethernet driver for networking support. > > +4. Cadence MMC Driver for eMMC/SD support. > > + > > +Booting from eMMC using HSS > > +--- > > + > > +Building U-Boot > > +--- > > + > > +1. Add the RISC-V toolchain to your PATH. > > +2. Setup ARCH & cross compilation environment variable: > > + > > +.. code-block:: none > > + > > + export CROSS_COMPILE= > > + > > +3. make microchip_mpfs_icicle_defconfig > > +4. make > > + > > +Flashing > > + > > + > > +The current U-Boot port is supported in S-mode only and loaded from > DRAM. > > + > > +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is > required to > > +boot the u-boot.bin in S-mode. > > + > > +Currently, the u-boot.bin is used as a payload of the HSS > firmware(Microchip > > nits: needs a space before ( and after ) > Please fix this globally in this file. > > ok > > +boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin > embedded) > > +as HSS payload(Custom boot-flow) > > + > > +Microchip boot-flow > > +--- > > +HSS with OpenSBI(M-Mode) -> U-Boot(S-Mode) -> Linux(S-Mode) > > + > > +Build the HSS((Hart Software Services) - Microchip boot-flow > > redundant ( > > ok > > + > > +(Note: HSS git repo is at > > +https://github.com/polarfire-soc/hart-software-services) > > + > > +1. Configure > > + > > +.. code-block:: none > > + > > + make BOARD=icicle-kit-es config > > + > > +Alternatively, copy the default config for Microchip boot-flow. > > + > > +.. code-block:: none > > + > > + cp boards/icicle-kit-es/def_config .config > > + > > +2. make BOARD=icicle-kit-es > > +3. In the Default subdirectory, the standard build will create hss.elf > and > > + various
Re: [PATCH v5 0/7] Microchip PolarFire SoC support
Hi Rick, On Thu, Dec 10, 2020 at 8:33 AM Rick Chen wrote: > Hi Padmarao > > > From: Padmarao Begari [mailto:padmarao.beg...@microchip.com] > > Sent: Thursday, December 03, 2020 4:32 AM > > To: u-boot@lists.denx.de; bmeng...@gmail.com; Rick Jian-Zhi Chen(陳建志); > anup.pa...@wdc.com; lukas.a...@aisec.fraunhofer.de; joe.hershber...@ni.com; > lu...@denx.de; atish.pa...@wdc.com > > Cc: cyril.j...@microchip.com; lewis.ha...@microchip.com; > ivan.grif...@emdalo.com; daire.mcnam...@emdalo.com; > conor.doo...@microchip.com; Padmarao Begari > > Subject: [PATCH v5 0/7] Microchip PolarFire SoC support > > > > This patch set adds Microchip PolarFire SoC Icicle Kit support > > to RISC-V U-Boot. > > > > The patches are based upon latest U-Boot tree > > (https://gitlab.denx.de/u-boot/u-boot.git) at commit id > > 80cbd731df50b9ab646940ea862b70bcaff37225 > > > > All drivers namely: NS16550 Serial, Microchip clock, > > Cadence eMMC and Cadence MACB Ethernet work fine on actual > > Microchip PolarFire SoC Icicle Kit. > > > > Changes in v5: > > - Replace compatible string "microchip,polarfire-soc" with > > "microchip,mpfs-icicle-kit" in the device tree > > - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" > > - Fix some typos in doc > > - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* > > - Rename pfsoc-clock.h to mpfs-clock.h > > > > Changes in v4: > > - Add dual-license GPL or MIT in the device tree > > - Replace microsemi compatible strings with microchip > > - Add MACB compatible string for Microchip PolarFire SoC ethernet > > - Update MACB driver for 32-bit/64-bit DMA based on compatible string > > > > Changes in v3: > > - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT > > - Update MACB driver for 32-bit/64-bit DMA based on design config > register > > - Add phy-handle in MACB driver to read the phy address from device tree > > - Fix checkpatch warnings in the clock driver > > - Remove fu540 related compatible strings from soc device tree node > > - Move refclk device tree node under /soc device tree node > > - Use local-mac-address instead of mac-address in the device tree > > - Rename device tree to microchip-mpfs-icicle-kit.dts > > - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file > > - Drop the imply DMA_ADDR_T_64BIT from board config > > - Fix some typos > > - Update doc with Microchip and Custom boot-flow > > > > Changes in v2: > > - Add clock frequency for the clint device tree node > > - Move peripheral device tree nodes under /soc device tree node > > - Device tree nodes are in order based on the address > > - Enable UART0 for U-Boot logs > > - Update doc for the U-Boot logs are on UART0 > > - Move clock and reset index source into patch4 > > - Remove "dma_addr_r" type in the macb driver > > - Add lower_32_bits() for 32-bit address in the macb driver > > - Add set_rate() returns the new clock rate in the clock driver > > > > Padmarao Begari (7): > > riscv: Add DMA 64-bit address support > > net: macb: Add DMA 64-bit address support for macb > > net: macb: Add phy address to read it from device tree > > clk: Add Microchip PolarFire SoC clock driver > > riscv: dts: Add device tree for Microchip Icicle Kit > > riscv: Add Microchip MPFS Icicle Kit support > > doc: board: Add Microchip MPFS Icicle Kit doc > > > > Please check about the CI failure item Job #95.59 > https://travis-ci.org/github/rickchen36/u-boot-riscv/jobs/748298546 > > ok, the underline is too short for Microchip name in the index.rst file. I will fix it in PATCH v6 Regards Padmarao > Thanks, > Rick > > > arch/riscv/Kconfig| 4 + > > arch/riscv/dts/Makefile | 1 + > > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + > > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 + > > arch/riscv/include/asm/types.h| 4 + > > board/microchip/mpfs_icicle/Kconfig | 24 + > > board/microchip/mpfs_icicle/mpfs_icicle.c | 97 +- > > configs/microchip_mpfs_icicle_defconfig | 9 +- > > doc/board/index.rst | 1 + > > doc/board/microchip/index.rst | 9 + > > doc/board/microchip/mpfs_icicle.rst | 830 ++ > > drivers/clk/Kconfig | 1 + > > drivers/clk/Makefile | 1 + > > drivers/clk/microchip/Kconfig
[PATCH v5 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 830
3 files changed, 840 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 4b6a996eb1..e329e2744c 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,6 +15,7 @@ Board-specific doc
freescale/index
google/index
intel/index
+ microchip/index
kontron/index
renesas/index
rockchip/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..b09e6788af
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+==
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..d37b9bcb92
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,830 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+-
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building U-Boot
+---
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware(Microchip
+boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin
embedded)
+as HSS payload(Custom boot-flow)
+
+Microchip boot-flow
+---
+HSS with OpenSBI(M-Mode) -> U-Boot(S-Mode) -> Linux(S-Mode)
+
+Build the HSS((Hart Software Services) - Microchip boot-flow
+
+(Note: HSS git repo is at
+https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+ make BOARD=icicle-kit-es config
+
+Alternatively, copy the default config for Microchip boot-flow.
+
+.. code-block:: none
+
+ cp boards/icicle-kit-es/def_config .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+ various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+Creating the HSS payload - Microchip boot-flow
+--
+1. You will be creating a payload from `u-boot-dtb.bin`.
+ Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+ cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the
binary file.
+
+ hart-entry-points: {u54_1: '0x8020', u54_2: '0x8020',
+ u54_3: '0x8020', u54_4: '0x8020'}
+
+ payloads:
+ test/u-boot-dtb.bin: {exec-addr: '0x8020', owner-hart: u54_1,
+ secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart:
u54_4,
+ priv-mode: prv_s}
+
+4. Generate payload
+
+.. code-block:: none
+
+ ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at
+https://github.com/polarfire-soc/hart-software-services/blob/master
+/tools/hss-payload-generator/README.md)
+
+Custom boot-flow
+
+HSS without OpenSBI(M-Mode) -> OpenSBI(M-Mode) -> U-Boot(S-Mode) ->
Linux(S-Mode)
+
+Build OpenSBI
+
[PATCH v5 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
3 files changed, 436 insertions(+)
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..01331b0aa1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
new file mode 100644
index 00..f60283fb6b
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+
+/ {
+ aliases {
+ cpu1 =
+ cpu2 =
+ cpu3 =
+ cpu4 =
+ };
+};
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 00..f5478bf201
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip MPFS Icicle Kit";
+ compatible = "microchip,mpfs-icicle-kit";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells = <1>;
+
[PATCH v5 6/7] riscv: Add Microchip MPFS Icicle Kit support
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
only enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
board/microchip/mpfs_icicle/Kconfig | 24 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 97 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60 +-
4 files changed, 145 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..f4e705a07b 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,31 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply NET_RANDOM_ETHADDR
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..420ea25ac2 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -6,10 +6,47 @@
#include
#include
+#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+ /*
+* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /*
+* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +59,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr,
6);
+ if (ret) {
+ printf("No local-mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property\n");
+ return -ENODEV;
+
[PATCH v5 2/7] net: macb: Add DMA 64-bit address support for macb
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
compatible string of the device tree node.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 insertions(+), 17 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index b80a259ff7..e7c93d4747 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -83,7 +83,16 @@ struct macb_dma_desc {
u32 ctrl;
};
-#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
+struct macb_dma_desc_64 {
+ u32 addrh;
+ u32 unused;
+};
+
+#define HW_DMA_CAP_32B 0
+#define HW_DMA_CAP_64B 1
+
+#define DMA_DESC_SIZE 16
+#define DMA_DESC_BYTES(n) ((n) * DMA_DESC_SIZE)
#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
#define MACB_TX_DUMMY_DMA_DESC_SIZE(DMA_DESC_BYTES(1))
@@ -133,6 +142,7 @@ struct macb_device {
#endif
phy_interface_t phy_interface;
#endif
+ unsigned short hw_dma_cap;
};
struct macb_config {
@@ -307,6 +317,24 @@ static inline void macb_invalidate_rx_buffer(struct
macb_device *macb)
#if defined(CONFIG_CMD_NET)
+static struct macb_dma_desc_64 *macb_64b_desc(struct macb_dma_desc *desc)
+{
+ return (struct macb_dma_desc_64 *)((void *)desc
+ + sizeof(struct macb_dma_desc));
+}
+
+static void macb_set_addr(struct macb_device *macb, struct macb_dma_desc *desc,
+ ulong addr)
+{
+ struct macb_dma_desc_64 *desc_64;
+
+ if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
+ desc_64 = macb_64b_desc(desc);
+ desc_64->addrh = upper_32_bits(addr);
+ }
+ desc->addr = lower_32_bits(addr);
+}
+
static int _macb_send(struct macb_device *macb, const char *name, void *packet,
int length)
{
@@ -325,8 +353,12 @@ static int _macb_send(struct macb_device *macb, const char
*name, void *packet,
macb->tx_head++;
}
+ if (macb->hw_dma_cap & HW_DMA_CAP_64B)
+ tx_head = tx_head * 2;
+
macb->tx_ring[tx_head].ctrl = ctrl;
- macb->tx_ring[tx_head].addr = paddr;
+ macb_set_addr(macb, >tx_ring[tx_head], paddr);
+
barrier();
macb_flush_ring_desc(macb, TX);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
@@ -363,19 +395,28 @@ static void reclaim_rx_buffers(struct macb_device *macb,
unsigned int new_tail)
{
unsigned int i;
+ unsigned int count;
i = macb->rx_tail;
macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
if (i > MACB_RX_RING_SIZE)
i = 0;
}
while (i < new_tail) {
- macb->rx_ring[i].addr &= ~MACB_BIT(RX_USED);
+ if (macb->hw_dma_cap & HW_DMA_CAP_64B)
+ count = i * 2;
+ else
+ count = i;
+ macb->rx_ring[count].addr &= ~MACB_BIT(RX_USED);
i++;
}
@@ -390,16 +431,25 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
void *buffer;
int length;
u32 status;
+ u8 flag = false;
macb->wrapped = false;
for (;;) {
macb_invalidate_ring_desc(macb, RX);
+ if (macb->hw_dma_cap & HW_DMA_CAP_64B)
+ next_rx_tail = next_rx_tail * 2;
+
if (!(macb->rx_ring[next_rx_tail].addr & MACB_BIT(RX_USED)))
return -EAGAIN;
status = macb->rx_ring[next_rx_tail].ctrl;
if (status & MACB_BIT(RX_SOF)) {
+ if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
+ next_rx_tail = next_rx_tail / 2;
+ flag = true;
+ }
+
if (next_rx_tail != macb->rx_tail)
reclaim_rx_buffers(macb, next_rx_tail);
macb->wrapped = false;
@@ -426,11 +476,22 @@ static int _macb_recv(struct macb_device *macb, uchar
**packetp)
*packetp = buffer;
}
+ if (macb->hw_dma_cap & HW_DMA_CAP_64B) {
+ if (!flag)
+
[PATCH v5 3/7] net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e7c93d4747..16d1597b10 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -531,6 +531,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1310,6 +1316,7 @@ static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
const char *compatible;
int ret;
@@ -1323,6 +1330,12 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Read phyaddr from DT */
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args))
+ macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
+ "reg", -1);
+
compatible = dev_read_prop(dev, "compatible", NULL);
if (compatible) {
--
2.17.1
[PATCH v5 1/7] riscv: Add DMA 64-bit address support
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit addresses, dma_addr_t need only be 32/64 bits wide. Signed-off-by: Padmarao Begari Reviewed-by: Anup Patel --- arch/riscv/Kconfig | 4 arch/riscv/include/asm/types.h | 4 2 files changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 30b05408b1..55eaee2da6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -152,6 +152,10 @@ config 32BIT config 64BIT bool +config DMA_ADDR_T_64BIT + bool + default y if 64BIT + config SIFIVE_CLINT bool depends on RISCV_MMODE || SPL_RISCV_MMODE diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h index 403cf9a48f..b800b2d221 100644 --- a/arch/riscv/include/asm/types.h +++ b/arch/riscv/include/asm/types.h @@ -29,7 +29,11 @@ typedef unsigned short umode_t; #include +#ifdef CONFIG_DMA_ADDR_T_64BIT +typedef u64 dma_addr_t; +#else typedef u32 dma_addr_t; +#endif typedef unsigned long phys_addr_t; typedef unsigned long phys_size_t; -- 2.17.1
[PATCH v5 4/7] clk: Add Microchip PolarFire SoC clock driver
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/microchip/Kconfig | 5 +
drivers/clk/microchip/Makefile| 1 +
drivers/clk/microchip/mpfs_clk.c | 127 +
drivers/clk/microchip/mpfs_clk.h | 19 ++
drivers/clk/microchip/mpfs_clk_cfg.c | 134 ++
drivers/clk/microchip/mpfs_clk_periph.c | 173 ++
.../dt-bindings/clock/microchip,mpfs-clock.h | 45 +
9 files changed, 506 insertions(+)
create mode 100644 drivers/clk/microchip/Kconfig
create mode 100644 drivers/clk/microchip/Makefile
create mode 100644 drivers/clk/microchip/mpfs_clk.c
create mode 100644 drivers/clk/microchip/mpfs_clk.h
create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c
create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c
create mode 100644 include/dt-bindings/clock/microchip,mpfs-clock.h
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4dfbad7986..1161fe7b5a 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -173,6 +173,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
+source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
source "drivers/clk/owl/Kconfig"
source "drivers/clk/renesas/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d1e295ac7c..bd8a6eed88 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
obj-$(CONFIG_CLK_K210) += kendryte/
+obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
obj-$(CONFIG_CLK_OWL) += owl/
diff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig
new file mode 100644
index 00..b70241559d
--- /dev/null
+++ b/drivers/clk/microchip/Kconfig
@@ -0,0 +1,5 @@
+config CLK_MPFS
+ bool "Clock support for Microchip PolarFire SoC"
+ depends on CLK && CLK_CCF
+ help
+ This enables support clock driver for Microchip PolarFire SoC
platform.
diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
new file mode 100644
index 00..904b345d75
--- /dev/null
+++ b/drivers/clk/microchip/Makefile
@@ -0,0 +1 @@
+obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
new file mode 100644
index 00..1b1b66ef64
--- /dev/null
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "mpfs_clk.h"
+
+/* All methods are delegated to CCF clocks */
+
+static ulong mpfs_clk_get_rate(struct clk *clk)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_get_rate(c);
+}
+
+static ulong mpfs_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return clk_set_rate(c, rate);
+}
+
+static int mpfs_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct clk *c, *p;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+
+ err = clk_get_by_id(parent->id, );
+ if (err)
+ return err;
+
+ return clk_set_parent(c, p);
+}
+
+static int mpfs_clk_endisable(struct clk *clk, bool enable)
+{
+ struct clk *c;
+ int err = clk_get_by_id(clk->id, );
+
+ if (err)
+ return err;
+ return enable ? clk_enable(c) : clk_disable(c);
+}
+
+static int mpfs_clk_enable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, true);
+}
+
+static int mpfs_clk_disable(struct clk *clk)
+{
+ return mpfs_clk_endisable(clk, false);
+}
+
+static int mpfs_clk_probe(struct udevice *dev)
+{
+ int ret;
+ void __iomem *base;
+ u32 clk_rate;
+ struct clk *clk;
+ const char *parent_clk_name;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -ENODEV;
+
+ clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+ if (!clk)
+ return -ENOMEM;
+
+ ret = clk_get_by_index(dev, 0, clk);
+
[PATCH v5 0/7] Microchip PolarFire SoC support
This patch set adds Microchip PolarFire SoC Icicle Kit support to RISC-V U-Boot. The patches are based upon latest U-Boot tree (https://gitlab.denx.de/u-boot/u-boot.git) at commit id 80cbd731df50b9ab646940ea862b70bcaff37225 All drivers namely: NS16550 Serial, Microchip clock, Cadence eMMC and Cadence MACB Ethernet work fine on actual Microchip PolarFire SoC Icicle Kit. Changes in v5: - Replace compatible string "microchip,polarfire-soc" with "microchip,mpfs-icicle-kit" in the device tree - Use "mpfs" as identifier in place of "polarfire-soc", "pfsoc" - Fix some typos in doc - Rename the clock driver files clk_pfsoc_* to mpfs_clk_* - Rename pfsoc-clock.h to mpfs-clock.h Changes in v4: - Add dual-license GPL or MIT in the device tree - Replace microsemi compatible strings with microchip - Add MACB compatible string for Microchip PolarFire SoC ethernet - Update MACB driver for 32-bit/64-bit DMA based on compatible string Changes in v3: - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT - Update MACB driver for 32-bit/64-bit DMA based on design config register - Add phy-handle in MACB driver to read the phy address from device tree - Fix checkpatch warnings in the clock driver - Remove fu540 related compatible strings from soc device tree node - Move refclk device tree node under /soc device tree node - Use local-mac-address instead of mac-address in the device tree - Rename device tree to microchip-mpfs-icicle-kit.dts - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file - Drop the imply DMA_ADDR_T_64BIT from board config - Fix some typos - Update doc with Microchip and Custom boot-flow Changes in v2: - Add clock frequency for the clint device tree node - Move peripheral device tree nodes under /soc device tree node - Device tree nodes are in order based on the address - Enable UART0 for U-Boot logs - Update doc for the U-Boot logs are on UART0 - Move clock and reset index source into patch4 - Remove "dma_addr_r" type in the macb driver - Add lower_32_bits() for 32-bit address in the macb driver - Add set_rate() returns the new clock rate in the clock driver Padmarao Begari (7): riscv: Add DMA 64-bit address support net: macb: Add DMA 64-bit address support for macb net: macb: Add phy address to read it from device tree clk: Add Microchip PolarFire SoC clock driver riscv: dts: Add device tree for Microchip Icicle Kit riscv: Add Microchip MPFS Icicle Kit support doc: board: Add Microchip MPFS Icicle Kit doc arch/riscv/Kconfig| 4 + arch/riscv/dts/Makefile | 1 + .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 + arch/riscv/include/asm/types.h| 4 + board/microchip/mpfs_icicle/Kconfig | 24 + board/microchip/mpfs_icicle/mpfs_icicle.c | 97 +- configs/microchip_mpfs_icicle_defconfig | 9 +- doc/board/index.rst | 1 + doc/board/microchip/index.rst | 9 + doc/board/microchip/mpfs_icicle.rst | 830 ++ drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/microchip/Kconfig | 5 + drivers/clk/microchip/Makefile| 1 + drivers/clk/microchip/mpfs_clk.c | 127 +++ drivers/clk/microchip/mpfs_clk.h | 19 + drivers/clk/microchip/mpfs_clk_cfg.c | 134 +++ drivers/clk/microchip/mpfs_clk_periph.c | 173 drivers/net/macb.c| 144 ++- drivers/net/macb.h| 6 + include/configs/microchip_mpfs_icicle.h | 60 +- .../dt-bindings/clock/microchip,mpfs-clock.h | 45 + 23 files changed, 2068 insertions(+), 62 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts create mode 100644 doc/board/microchip/index.rst create mode 100644 doc/board/microchip/mpfs_icicle.rst create mode 100644 drivers/clk/microchip/Kconfig create mode 100644 drivers/clk/microchip/Makefile create mode 100644 drivers/clk/microchip/mpfs_clk.c create mode 100644 drivers/clk/microchip/mpfs_clk.h create mode 100644 drivers/clk/microchip/mpfs_clk_cfg.c create mode 100644 drivers/clk/microchip/mpfs_clk_periph.c create mode 100644 include/dt-bindings/clock/microchip,mpfs-clock.h -- 2.17.1
Re: [PATCH v4 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
Hi Cyril, On Fri, Nov 27, 2020 at 10:05 PM wrote: > Hi Padmarao, > > On 11/27/20 12:04 PM, Padmarao Begari wrote: > > This doc describes the procedure to build, flash and > > boot Linux using U-boot on Microchip MPFS Icicle Kit. > > > > Signed-off-by: Padmarao Begari > > Reviewed-by: Anup Patel > > --- > > doc/board/index.rst | 1 + > > doc/board/microchip/index.rst | 9 + > > doc/board/microchip/mpfs_icicle.rst | 827 > > 3 files changed, 837 insertions(+) > > create mode 100644 doc/board/microchip/index.rst > > create mode 100644 doc/board/microchip/mpfs_icicle.rst > > > > diff --git a/doc/board/index.rst b/doc/board/index.rst > > index 4b6a996eb1..e329e2744c 100644 > > --- a/doc/board/index.rst > > +++ b/doc/board/index.rst > > @@ -15,6 +15,7 @@ Board-specific doc > > freescale/index > > google/index > > intel/index > > + microchip/index > > kontron/index > > renesas/index > > rockchip/index > > diff --git a/doc/board/microchip/index.rst > b/doc/board/microchip/index.rst > > new file mode 100644 > > index 00..b09e6788af > > --- /dev/null > > +++ b/doc/board/microchip/index.rst > > @@ -0,0 +1,9 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Microchip > > +== > > + > > +.. toctree:: > > + :maxdepth: 2 > > + > > + mpfs_icicle > > diff --git a/doc/board/microchip/mpfs_icicle.rst > b/doc/board/microchip/mpfs_icicle.rst > > new file mode 100644 > > index 00..fb3f895ca3 > > --- /dev/null > > +++ b/doc/board/microchip/mpfs_icicle.rst > > @@ -0,0 +1,827 @@ > > +.. SPDX-License-Identifier: GPL-2.0+ > > + > > +Microchip PolarFire SoC Icicle Kit > > +== > > + > > +RISC-V PolarFire SoC > > +- > > +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip. > > + > > +The Icicle Kit development platform is based on PolarFire SoC and > capable > > +of running Linux. > > + > > +Mainline support > > + > > +The support for following drivers are already enabled: > > + > > +1. NS16550 UART Driver. > > +2. Microchip Clock Driver. > > +3. Cadence MACB ethernet driver for networking support. > > +4. Cadence MMC Driver for eMMC/SD support. > > + > > +Booting from eMMC using HSS > > +--- > > + > > +Building U-Boot > > +--- > > + > > +1. Add the RISC-V toolchain to your PATH. > > +2. Setup ARCH & cross compilation environment variable: > > + > > +.. code-block:: none > > + > > + export CROSS_COMPILE= > > + > > +3. make microchip_mpfs_icicle_defconfig > > +4. make > > + > > +Flashing > > + > > + > > +The current U-Boot port is supported in S-mode only and loaded from > DRAM. > > + > > +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is > required to > > +boot the u-boot.bin in S-mode. > > + > > +Currently, the u-boot.bin is used as a payload of the HSS > firmware(Microchip > > +boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin > embedded) > > +as HSS payload(Custom boot-flow) > > + > > +Microchip boot-flow > > +--- > > +HSS with OpenSBI(M-Mode) -> U-Boot(S-Mode) -> Linux(S-Mode) > > + > > +Build the HSS((Hart Software Services) - Microchip boot-flow > > + > > +(Note: HSS git repo is at > > +https://github.com/polarfire-soc/hart-software-services) > > + > > +1. Configure > > + > > +.. code-block:: none > > + > > + make BOARD=icicle-kit-es config > > + > > +Alternatively, copy the default config for Microchip boot-flow. > > + > > +.. code-block:: none > > + > > + cp boards/icicle-kit-es/def_config .config > > + > > +2. make BOARD=icicle-kit-es > > +3. In the Default subdirectory, the standard build will create hss.elf > and > > + various binary formats (hss.hex and hss.bin). > > + > > +The FPGA design will use the hss.hex or hss.bin. > > + > > +FPGA design with HSS programming file > > +- > > + > https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards > > > +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit
Re: [PATCH v4 0/7] Microchip PolarFire SoC support
Hi Cyril, On Fri, Nov 27, 2020 at 9:47 PM wrote: > Hi Padmarao, > > On 11/27/20 12:04 PM, Padmarao Begari wrote: > > This patch set adds Microchip PolarFire SoC Icicle Kit support > > to RISC-V U-Boot. > > > > The patches are based upon latest U-Boot tree > > (https://gitlab.denx.de/u-boot/u-boot.git) at commit id > > 7889951d0f56eab746a7c8fde350a022ba0361ca > > > > All drivers namely: NS16550 Serial, Microchip clock, > > Cadence eMMC and Cadence MACB Ethernet work fine on actual > > Microchip PolarFire SoC Icicle Kit. > > > > Changes in v4: > > - Add dual-license GPL or MIT in the device tree > > - Replace microsemi compatible strings with microchip > > - Add MACB compatible string for Microchip PolarFire SoC ethernet > > - Update MACB driver for 32-bit/64-bit DMA based on compatible string > > > > Changes in v3: > > - Add 'default y if 64BIT' for config DMA_ADDR_T_64BIT > > - Update MACB driver for 32-bit/64-bit DMA based on design config > register > > - Add phy-handle in MACB driver to read the phy address from device tree > > - Fix checkpatch warnings in the clock driver > > - Remove fu540 related compatible strings from soc device tree node > > - Move refclk device tree node under /soc device tree node > > - Use local-mac-address instead of mac-address in the device tree > > - Rename device tree to microchip-mpfs-icicle-kit.dts > > - Add U-Boot specific dts microchip-mpfs-icicle-kit-u-boot.dtsi file > > - Drop the imply DMA_ADDR_T_64BIT from board config > > - Fix some typos > > - Update doc with Microchip and Custom boot-flow > > > > Changes in v2: > > - Add clock frequency for the clint device tree node > > - Move peripheral device tree nodes under /soc device tree node > > - Device tree nodes are in order based on the address > > - Enable UART0 for U-Boot logs > > - Update doc for the U-Boot logs are on UART0 > > - Move clock and reset index source into patch4 > > - Remove "dma_addr_r" type in the macb driver > > - Add lower_32_bits() for 32-bit address in the macb driver > > - Add set_rate() returns the new clock rate in the clock driver > > > > Padmarao Begari (7): > >riscv: Add DMA 64-bit address support > >net: macb: Add DMA 64-bit address support for macb > >net: macb: Add phy address to read it from device tree > >clk: Add Microchip PolarFire SoC clock driver > >riscv: dts: Add device tree for Microchip Icicle Kit > >riscv: Add Microchip MPFS Icicle Kit support > >doc: board: Add Microchip MPFS Icicle Kit doc > > > > arch/riscv/Kconfig| 4 + > > arch/riscv/dts/Makefile | 1 + > > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 + > > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 + > > arch/riscv/include/asm/types.h| 4 + > > board/microchip/mpfs_icicle/Kconfig | 24 + > > board/microchip/mpfs_icicle/mpfs_icicle.c | 97 +- > > configs/microchip_mpfs_icicle_defconfig | 9 +- > > doc/board/index.rst | 1 + > > doc/board/microchip/index.rst | 9 + > > doc/board/microchip/mpfs_icicle.rst | 827 ++ > > drivers/clk/Kconfig | 1 + > > drivers/clk/Makefile | 1 + > > drivers/clk/microchip/Kconfig | 5 + > > drivers/clk/microchip/Makefile| 1 + > > drivers/clk/microchip/clk_pfsoc.c | 127 +++ > > drivers/clk/microchip/clk_pfsoc.h | 19 + > > drivers/clk/microchip/clk_pfsoc_cfg.c | 134 +++ > > drivers/clk/microchip/clk_pfsoc_periph.c | 173 > > drivers/net/macb.c| 144 ++- > > drivers/net/macb.h| 6 + > > include/configs/microchip_mpfs_icicle.h | 60 +- > > .../dt-bindings/clock/microchip,pfsoc-clock.h | 45 + > > 23 files changed, 2065 insertions(+), 62 deletions(-) > > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi > > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts > > create mode 100644 doc/board/microchip/index.rst > > create mode 100644 doc/board/microchip/mpfs_icicle.rst > > create mode 100644 drivers/clk/microchip/Kconfig > > create mode 100644 drivers/clk/microchip/Makefile > > create mode 100644 drivers/clk/microchip/clk_pfsoc.c > > create mode 100644 drivers/clk/microchip/clk_pfsoc.h > > create mode 100644 drivers/clk/microchip/clk_pfsoc_cfg.c > > create mode 100644 drivers/clk/microchip/clk_pfsoc_periph.c > > create mode 100644 include/dt-bindings/clock/microchip,pfsoc-clock.h > > > Can you please rename the files clk_pfsoc_* to mpfs_clk_*? I know this > naming is inconsistent but we need to start somewhere. Also > pfsoc-clock.h to mpfs-clock.h. > > > Ok Regards Padmarao > Regards, > > Cyril. > >
Re: [PATCH v4 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Cyril,
On Fri, Nov 27, 2020 at 9:45 PM wrote:
> On 11/27/20 1:43 PM, Bin Meng wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> the content is safe
> >
> > Hi Padmarao,
> >
> > On Fri, Nov 27, 2020 at 8:18 PM Padmarao Begari
> > wrote:
> >> Add device tree for Microchip PolarFire SoC Icicle Kit.
> snip
> >> --- /dev/null
> >> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >> @@ -0,0 +1,421 @@
> >> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> >> +/* Copyright (c) 2020 Microchip Technology Inc */
> >> +
> >> +/dts-v1/;
> >> +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> >> +
> >> +/* Clock frequency (in Hz) of the rtcclk */
> >> +#define RTCCLK_FREQ100
> >> +
> >> +/ {
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >> + model = "Microchip PolarFire-SoC";
> >> + compatible = "microchip,polarfire-soc";
> > Should this be: "microchip,polarfire-soc-icicle-kit"?
>
> My preference for this would go to: "microchip,mpfs-icicle-kit". This is
> the name used to order the board and what is written on the box.
>
>
ok
> As a rule please use "mpfs" as identifier in place of "polarfire-soc",
> "pfsoc", "pse", "g5soc" or whatever other variation on the theme when
> not using the marketing name of the device.
>
>
ok
Regards
Padmarao
> Regards,
>
> Cyril.
>
>
>
Re: [PATCH v4 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Hi Bin,
On Fri, Nov 27, 2020 at 7:13 PM Bin Meng wrote:
> Hi Padmarao,
>
> On Fri, Nov 27, 2020 at 8:18 PM Padmarao Begari
> wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari
> > Reviewed-by: Anup Patel
> > ---
> > arch/riscv/dts/Makefile | 1 +
> > .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
> > arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
> > 3 files changed, 436 insertions(+)
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..01331b0aa1 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> > dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> > dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
> >
> > targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > new file mode 100644
> > index 00..f60283fb6b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
> > @@ -0,0 +1,14 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2020 Microchip Technology Inc.
> > + * Padmarao Begari
> > + */
> > +
> > +/ {
> > + aliases {
> > + cpu1 =
> > + cpu2 =
> > + cpu3 =
> > + cpu4 =
> > + };
> > +};
> > diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > new file mode 100644
> > index 00..bf5d65740a
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
> > @@ -0,0 +1,421 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + model = "Microchip PolarFire-SoC";
> > + compatible = "microchip,polarfire-soc";
>
> Should this be: "microchip,polarfire-soc-icicle-kit"?
>
> > +
> > + aliases {
> > + serial0 =
> > + ethernet0 =
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0";
> > + };
> > +
> > + cpucomplex: cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + timebase-frequency = ;
> > + cpu0: cpu@0 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > + device_type = "cpu";
> > + i-cache-block-size = <64>;
> > + i-cache-sets = <128>;
> > + i-cache-size = <16384>;
> > + reg = <0>;
> > + riscv,isa = "rv64imac";
> > + status = "disabled";
> > + operating-points = <
> > + /* kHz uV */
> > + 60 110
> > + 30 95
> > + 15 75
> > + >;
> > + cpu0intc: interrupt-controller {
> > + #interrupt-cells = <1>;
> > + compatible = "riscv,cpu-intc";
> > + interrupt-controller;
> > + };
> > + };
> > + cpu1: cpu@1 {
> > + clocks = < CLK_CPU>;
> > + compatible = "sifive,u54-mc&q
[PATCH v4 7/7] doc: board: Add Microchip MPFS Icicle Kit doc
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 827
3 files changed, 837 insertions(+)
create mode 100644 doc/board/microchip/index.rst
create mode 100644 doc/board/microchip/mpfs_icicle.rst
diff --git a/doc/board/index.rst b/doc/board/index.rst
index 4b6a996eb1..e329e2744c 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,6 +15,7 @@ Board-specific doc
freescale/index
google/index
intel/index
+ microchip/index
kontron/index
renesas/index
rockchip/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..b09e6788af
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+==
+
+.. toctree::
+ :maxdepth: 2
+
+ mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..fb3f895ca3
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,827 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+-
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building U-Boot
+---
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+ export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware(Microchip
+boot-flow) and OpenSBI generic platform fw_payload.bin (with u-boot.bin
embedded)
+as HSS payload(Custom boot-flow)
+
+Microchip boot-flow
+---
+HSS with OpenSBI(M-Mode) -> U-Boot(S-Mode) -> Linux(S-Mode)
+
+Build the HSS((Hart Software Services) - Microchip boot-flow
+
+(Note: HSS git repo is at
+https://github.com/polarfire-soc/hart-software-services)
+
+1. Configure
+
+.. code-block:: none
+
+ make BOARD=icicle-kit-es config
+
+Alternatively, copy the default config for Microchip boot-flow.
+
+.. code-block:: none
+
+ cp boards/icicle-kit-es/def_config .config
+
+2. make BOARD=icicle-kit-es
+3. In the Default subdirectory, the standard build will create hss.elf and
+ various binary formats (hss.hex and hss.bin).
+
+The FPGA design will use the hss.hex or hss.bin.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+Creating the HSS payload - Microchip boot-flow
+--
+1. You will be creating a payload from `u-boot-dtb.bin`.
+ Copy this file to the HSS/tools/hss-payload-generator/test directory.
+2. Go to hss-payload-generator source directory.
+
+.. code-block:: none
+
+ cd hart-software-services/tools/hss-payload-generator
+
+3. Edit test/uboot.yaml file for hart entry points and correct name of the
binary file.
+
+ hart-entry-points: {u54_1: '0x8020', u54_2: '0x8020',
+ u54_3: '0x8020', u54_4: '0x8020'}
+
+ payloads:
+ test/u-boot-dtb.bin: {exec-addr: '0x8020', owner-hart: u54_1,
+ secondary-hart: u54_2, secondary-hart: u54_3, secondary-hart:
u54_4,
+ priv-mode: prv_s}
+
+4. Generate payload
+
+.. code-block:: none
+
+ ./hss-payload-generator -c test/uboot.yaml payload.bin
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+Please refer to HSS documenation to build the HSS firmware for payload.
+(Note: HSS git repo is at
+https://github.com/polarfire-soc/hart-software-services/blob/master
+/tools/hss-payload-generator/README.md)
+
+Custom boot-flow
+
+HSS without OpenSBI(M-Mode) -> OpenSBI(M-Mode) -> U-Boot(S-Mode) ->
Linux(S-Mode)
+
+Build OpenSBI
+
[PATCH v4 3/7] net: macb: Add phy address to read it from device tree
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index e7c93d4747..16d1597b10 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -531,6 +531,12 @@ static int macb_phy_find(struct macb_device *macb, const
char *name)
int i;
u16 phy_id;
+ phy_id = macb_mdio_read(macb, macb->phy_addr, MII_PHYSID1);
+ if (phy_id != 0x) {
+ printf("%s: PHY present at %d\n", name, macb->phy_addr);
+ return 0;
+ }
+
/* Search for PHY... */
for (i = 0; i < 32; i++) {
macb->phy_addr = i;
@@ -1310,6 +1316,7 @@ static int macb_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct macb_device *macb = dev_get_priv(dev);
+ struct ofnode_phandle_args phandle_args;
const char *phy_mode;
const char *compatible;
int ret;
@@ -1323,6 +1330,12 @@ static int macb_eth_probe(struct udevice *dev)
return -EINVAL;
}
+ /* Read phyaddr from DT */
+ if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ _args))
+ macb->phy_addr = ofnode_read_u32_default(phandle_args.node,
+"reg", -1);
+
compatible = dev_read_prop(dev, "compatible", NULL);
if (compatible) {
--
2.17.1
[PATCH v4 6/7] riscv: Add Microchip MPFS Icicle Kit support
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
only enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS + OpenSBI.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
board/microchip/mpfs_icicle/Kconfig | 24 ++
board/microchip/mpfs_icicle/mpfs_icicle.c | 97 ++-
configs/microchip_mpfs_icicle_defconfig | 9 ++-
include/configs/microchip_mpfs_icicle.h | 60 +-
4 files changed, 145 insertions(+), 45 deletions(-)
diff --git a/board/microchip/mpfs_icicle/Kconfig
b/board/microchip/mpfs_icicle/Kconfig
index bf8e1a13ec..f4e705a07b 100644
--- a/board/microchip/mpfs_icicle/Kconfig
+++ b/board/microchip/mpfs_icicle/Kconfig
@@ -20,7 +20,31 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select GENERIC_RISCV
select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
imply SMP
+ imply CLK_CCF
+ imply CLK_MPFS
imply SYS_NS16550
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_MMC
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply NET_RANDOM_ETHADDR
+ imply PHY_LIB
+ imply PHY_VITESSE
+ imply MMC
+ imply MMC_WRITE
+ imply MMC_SDHCI
+ imply MMC_SDHCI_CADENCE
endif
diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c
b/board/microchip/mpfs_icicle/mpfs_icicle.c
index 8381361ec3..420ea25ac2 100644
--- a/board/microchip/mpfs_icicle/mpfs_icicle.c
+++ b/board/microchip/mpfs_icicle/mpfs_icicle.c
@@ -6,10 +6,47 @@
#include
#include
+#include
#include
#include
-#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088)
+#define MPFS_SYS_SERVICE_CR((unsigned int *)0x37020050)
+#define MPFS_SYS_SERVICE_SR((unsigned int *)0x37020054)
+#define MPFS_SYS_SERVICE_MAILBOX ((unsigned char *)0x37020800)
+
+#define PERIPH_RESET_VALUE 0x1e8u
+#define SERVICE_CR_REQ 0x1u
+#define SERVICE_SR_BUSY0x2u
+
+static void read_device_serial_number(u8 *response, u8 response_size)
+{
+ u8 idx;
+ u8 *response_buf;
+ unsigned int val;
+
+ response_buf = (u8 *)response;
+
+ writel(SERVICE_CR_REQ, MPFS_SYS_SERVICE_CR);
+ /*
+* REQ bit will remain set till the system controller starts
+* processing.
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_CR);
+ } while (SERVICE_CR_REQ == (val & SERVICE_CR_REQ));
+
+ /*
+* Once system controller starts processing the busy bit will
+* go high and service is completed when busy bit is gone low
+*/
+ do {
+ val = readl(MPFS_SYS_SERVICE_SR);
+ } while (SERVICE_SR_BUSY == (val & SERVICE_SR_BUSY));
+
+ for (idx = 0; idx < response_size; idx++)
+ response_buf[idx] = readb(MPFS_SYS_SERVICE_MAILBOX + idx);
+}
int board_init(void)
{
@@ -22,10 +59,64 @@ int board_early_init_f(void)
{
unsigned int val;
- /* Reset uart peripheral */
+ /* Reset uart, mmc peripheral */
val = readl(MPFS_SYSREG_SOFT_RESET);
- val = (val & ~(1u << 5u));
+ val = (val & ~(PERIPH_RESET_VALUE));
writel(val, MPFS_SYSREG_SOFT_RESET);
return 0;
}
+
+int board_late_init(void)
+{
+ u32 ret;
+ u32 node;
+ u8 idx;
+ u8 device_serial_number[16] = { 0 };
+ unsigned char mac_addr[6];
+ char icicle_mac_addr[20];
+ void *blob = (void *)gd->fdt_blob;
+
+ node = fdt_path_offset(blob, "ethernet0");
+ if (node < 0) {
+ printf("No ethernet0 path offset\n");
+ return -ENODEV;
+ }
+
+ ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr,
6);
+ if (ret) {
+ printf("No local-mac-address property\n");
+ return -EINVAL;
+ }
+
+ read_device_serial_number(device_serial_number, 16);
+
+ /* Update MAC address with device serial number */
+ mac_addr[0] = 0x00;
+ mac_addr[1] = 0x04;
+ mac_addr[2] = 0xA3;
+ mac_addr[3] = device_serial_number[2];
+ mac_addr[4] = device_serial_number[1];
+ mac_addr[5] = device_serial_number[0];
+
+ ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
+ if (ret) {
+ printf("Error setting local-mac-address property\n");
+ return -ENODEV;
+
[PATCH v4 5/7] riscv: dts: Add device tree for Microchip Icicle Kit
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
3 files changed, 436 insertions(+)
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
create mode 100644 arch/riscv/dts/microchip-mpfs-icicle-kit.dts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..01331b0aa1 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
new file mode 100644
index 00..f60283fb6b
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020 Microchip Technology Inc.
+ * Padmarao Begari
+ */
+
+/ {
+ aliases {
+ cpu1 =
+ cpu2 =
+ cpu3 =
+ cpu4 =
+ };
+};
diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 00..bf5d65740a
--- /dev/null
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,421 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip,pfsoc-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "Microchip PolarFire-SoC";
+ compatible = "microchip,polarfire-soc";
+
+ aliases {
+ serial0 =
+ ethernet0 =
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpucomplex: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ timebase-frequency = ;
+ cpu0: cpu@0 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,e51", "sifive,rocket0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ reg = <0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu0intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = < CLK_CPU>;
+ compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <32>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <32>;
+ mmu-type = "riscv,sv39";
+ reg = <1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ status = "okay";
+ operating-points = <
+ /* kHz uV */
+ 60 110
+ 30 95
+ 15 75
+ >;
+ cpu1intc: interrupt-controller {
+ #interrupt-cells = <1>;
+
