Re: [PATCH 2/2] ARM: dts: renesas: Switch to using upstream DT on 64bit Renesas SoCs
On 18/03/2024 14:59, Marek Vasut wrote: > Enable OF_UPSTREAM to use upstream DT and add renesas/ prefix to the > DEFAULT_DEVICE_TREE and OF_LIST. And thereby directly build DTB from > dts/upstream/src/ including *-u-boot.dtsi files from arch/$(ARCH)/dts/ > directory. > > The configuration update has been done using the following script: > ``` > sed -i '/^CONFIG_DEFAULT_DEVICE_TREE/ s@="@/@' `git grep -li renesas > configs` > sed -i '/^CONFIG_OF_LIST/ s@r8a@renesas/&@g' `git grep -li renesas configs` > ``` > > There are SoCs which are not included in this patch. The 32bit SoCs > require further infrastructure work. R8A779H0 is coming during the > next upstream DT synchronization cycle as it is not included in > current upstream DTs yet. > > Signed-off-by: Marek Vasut Reviewed-by: Paul Barker (for RZ/G2L only) Do we also plan to drop the corresponding .dts & .dtsi files from arch/arm/dts? Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH] doc: devicetree: Lets avoid short reference link names
On 02/03/2024 07:39, Paul Barker wrote: > On 01/03/2024 13:24, Sumit Garg wrote: >> Short reference link names like "dtspec", "dtrepo", "dttweaks" etc. >> interrupt the flow of the document text. Lets avoid them and instead >> expand in place for better readability. >> >> Suggested-by: Paul Barker >> Signed-off-by: Sumit Garg >> --- >> doc/develop/devicetree/control.rst | 24 >> 1 file changed, 12 insertions(+), 12 deletions(-) >> >> diff --git a/doc/develop/devicetree/control.rst >> b/doc/develop/devicetree/control.rst >> index c94d84192b71..4cc1457d4ea8 100644 >> --- a/doc/develop/devicetree/control.rst >> +++ b/doc/develop/devicetree/control.rst >> @@ -36,10 +36,10 @@ What is a Flattened Devicetree? >> --- >> >> An fdt can be specified in source format as a text file. To read about >> -the fdt syntax, take a look at the specification (dtspec_). >> +the fdt syntax, take a look at `the devicetree specification`_. >> >> -There is also a mailing list (dtlist_) for the compiler and associated >> -tools. >> +There is also a `devicetree compiler mailing list`_ for the compiler and >> +associated tools. >> >> In case you are wondering, OF stands for Open Firmware. This follows the >> convention used in Linux. >> @@ -89,7 +89,7 @@ Failing that, you could write one from scratch yourself! >> Resyncing with devicetree-rebasing >> -- >> >> -The devicetee-rebasing repository (dtrepo_) maintains a fork cum mirror >> copy of >> +The `devicetree-rebasing repository`_ maintains a fork cum mirror copy of >> devicetree files along with the bindings synced at every Linux kernel major >> release or intermediate release candidates. The U-Boot maintainers regularly >> sync the `dts/upstream/` subtree from the devicetree-rebasing repo whenever >> @@ -118,7 +118,7 @@ as `arch//dts/.dts`. To select that add `# >> CONFIG_OF_UPSTREAM is not >> set` and set `DEFAULT_DEVICE_TREE=` when prompted by Kconfig. >> >> This should include your CPU or SoC's devicetree file. On top of that any >> U-Boot >> -specific tweaks (see: dttweaks_) can be made for your board. >> +specific tweaks (see: :ref:`dttweaks`) can be made for your board. >> >> If `OF_EMBED` is selected by Kconfig, then it will be picked up and built >> into >> the U-Boot image (including u-boot.bin). This is suitable for debugging >> @@ -243,7 +243,7 @@ Dependencies >> >> The DT schema project must be installed in order to validate the DT schema >> binding documents and validate DTS files using the DT schema. For >> installation >> -instructions, refer to the DT schema project page (dtschema_). >> +instructions, refer to the `DT schema project page`_. >> >> Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be >> installed. Ensure they are in your PATH (~/.local/bin by default). >> @@ -333,10 +333,10 @@ used it before Linux (e.g. snow). The two projects >> developed in parallel >> and there are still some differences in the bindings for certain boards. >> While there has been discussion of having a separate repository for >> devicetree >> files, in practice the Linux kernel Git repository has become the place >> where >> -these are stored, with U-Boot taking copies via devicetree-rebasing repo >> -(see: dtrepo_) and adding tweaks with u-boot.dtsi files. >> +these are stored, with U-Boot taking copies via >> +`devicetree-rebasing repository`_ and adding tweaks with u-boot.dtsi files. >> >> -.. _dtspec: https://www.devicetree.org/specifications/ >> -.. _dtlist: https://www.spinics.net/lists/devicetree-compiler/ >> -.. _dtrepo: >> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git >> -.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main >> +.. _the devicetree specification: https://www.devicetree.org/specifications/ >> +.. _devicetree compiler mailing list: >> https://www.spinics.net/lists/devicetree-compiler/ >> +.. _devicetree-rebasing repository: >> https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git >> +.. _DT schema project page: >> https://github.com/devicetree-org/dt-schema/tree/main > > Reviewed-by: Paul Barker > There are no comments from anyone else, but this hasn't hit the next branch yet so I'm sending a gentle ping. -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 00/19] ARM: renesas: Rename R-Mobile to Renesas
On 27/02/2024 16:05, Marek Vasut wrote: > Rename R-Mobile to Renesas all over the place because the chips are > made by Renesas, while only a subset of them is from the R-Mobile line. > > Marek Vasut (19): > ARM: renesas: Drop remnants of R8A7740 support > ARM: renesas: Drop unused sh_sdhi.h > ARM: renesas: Drop unused mmc.h > ARM: renesas: Drop unused pfc-r8a7790.h > ARM: renesas: Rename rmobile_get_cpu_type() to renesas_get_cpu_type() > ARM: renesas: Rename rmobile_get_cpu_rev_*() to > renesas_get_cpu_rev_*() > ARM: renesas: Rename RMOBILE_CPU_TYPE_* to RENESAS_CPU_TYPE_* > ARM: renesas: Rename rmobile_cpuinfo_idx() to renesas_cpuinfo_idx() > ARM: renesas: Rename rmobile_cpuinfo[] to renesas_cpuinfo[] > ARM: renesas: Simplify weak symbols > ARM: renesas: Rename rmobile_get_prr() to renesas_get_prr() > ARM: renesas: Rename ARCH_RMOBILE_BOARD_STRING to > ARCH_RENESAS_BOARD_STRING > ARM: renesas: Rename CONFIG_ARCH_RMOBILE_EXTRAM_BOOT to > CONFIG_RENESAS_EXTRAM_BOOT > ARM: renesas: Rename rmobile.h to renesas.h > ARM: renesas: Rename ARCH_RMOBILE to ARCH_RENESAS > ARM: renesas: Rename arch-/mach-rmobile to arch-/mach-renesas > ARM: renesas: Post rename fix ups > mmc: renesas-sdhi: Rename rmobile_is_gen3_mmc0() to > rcar_is_gen3_mmc0() > git-mailrc: Add renesas entry and update rmobile entry > For every patch in the series: Reviewed-by: Paul Barker -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH] doc: devicetree: Lets avoid short reference link names
On 01/03/2024 13:24, Sumit Garg wrote: > Short reference link names like "dtspec", "dtrepo", "dttweaks" etc. > interrupt the flow of the document text. Lets avoid them and instead > expand in place for better readability. > > Suggested-by: Paul Barker > Signed-off-by: Sumit Garg > --- > doc/develop/devicetree/control.rst | 24 > 1 file changed, 12 insertions(+), 12 deletions(-) > > diff --git a/doc/develop/devicetree/control.rst > b/doc/develop/devicetree/control.rst > index c94d84192b71..4cc1457d4ea8 100644 > --- a/doc/develop/devicetree/control.rst > +++ b/doc/develop/devicetree/control.rst > @@ -36,10 +36,10 @@ What is a Flattened Devicetree? > --- > > An fdt can be specified in source format as a text file. To read about > -the fdt syntax, take a look at the specification (dtspec_). > +the fdt syntax, take a look at `the devicetree specification`_. > > -There is also a mailing list (dtlist_) for the compiler and associated > -tools. > +There is also a `devicetree compiler mailing list`_ for the compiler and > +associated tools. > > In case you are wondering, OF stands for Open Firmware. This follows the > convention used in Linux. > @@ -89,7 +89,7 @@ Failing that, you could write one from scratch yourself! > Resyncing with devicetree-rebasing > -- > > -The devicetee-rebasing repository (dtrepo_) maintains a fork cum mirror copy > of > +The `devicetree-rebasing repository`_ maintains a fork cum mirror copy of > devicetree files along with the bindings synced at every Linux kernel major > release or intermediate release candidates. The U-Boot maintainers regularly > sync the `dts/upstream/` subtree from the devicetree-rebasing repo whenever > @@ -118,7 +118,7 @@ as `arch//dts/.dts`. To select that add `# > CONFIG_OF_UPSTREAM is not > set` and set `DEFAULT_DEVICE_TREE=` when prompted by Kconfig. > > This should include your CPU or SoC's devicetree file. On top of that any > U-Boot > -specific tweaks (see: dttweaks_) can be made for your board. > +specific tweaks (see: :ref:`dttweaks`) can be made for your board. > > If `OF_EMBED` is selected by Kconfig, then it will be picked up and built > into > the U-Boot image (including u-boot.bin). This is suitable for debugging > @@ -243,7 +243,7 @@ Dependencies > > The DT schema project must be installed in order to validate the DT schema > binding documents and validate DTS files using the DT schema. For > installation > -instructions, refer to the DT schema project page (dtschema_). > +instructions, refer to the `DT schema project page`_. > > Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be > installed. Ensure they are in your PATH (~/.local/bin by default). > @@ -333,10 +333,10 @@ used it before Linux (e.g. snow). The two projects > developed in parallel > and there are still some differences in the bindings for certain boards. > While there has been discussion of having a separate repository for > devicetree > files, in practice the Linux kernel Git repository has become the place where > -these are stored, with U-Boot taking copies via devicetree-rebasing repo > -(see: dtrepo_) and adding tweaks with u-boot.dtsi files. > +these are stored, with U-Boot taking copies via > +`devicetree-rebasing repository`_ and adding tweaks with u-boot.dtsi files. > > -.. _dtspec: https://www.devicetree.org/specifications/ > -.. _dtlist: https://www.spinics.net/lists/devicetree-compiler/ > -.. _dtrepo: > https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git > -.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main > +.. _the devicetree specification: https://www.devicetree.org/specifications/ > +.. _devicetree compiler mailing list: > https://www.spinics.net/lists/devicetree-compiler/ > +.. _devicetree-rebasing repository: > https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git > +.. _DT schema project page: > https://github.com/devicetree-org/dt-schema/tree/main Reviewed-by: Paul Barker -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH v6 08/11] doc: devicetree: Updates for devicetree-rebasing subtree
On 28/02/2024 09:20, Sumit Garg wrote: > Hi Paul, > > On Wed, 28 Feb 2024 at 03:08, Paul Barker > wrote: >> >> Hi Sumit, >> >> On 22/02/2024 09:36, Sumit Garg wrote: >>> Encourage SoC/board maintainers to migrate to using devicetree-rebasing >>> subtree and maintain a regular sync with Linux kernel devicetree files >>> and bindings. >>> >>> Along with that add documentation regarding how to run DT bindings >>> schema checks. >>> >>> Signed-off-by: Sumit Garg >>> --- >>> >>> Changes in v6: >>> - Incorporate documentation review comments from Paul. >>> >> >> I have just a couple of tidy up suggestions for the links in this >> document - these let us avoid short reference names like `dtrepo` or >> `dttweaks` appearing in the document itself where they interrupt the >> flow of the text. > > Although these are following the same pattern as `dtspec` and `dtlist` > , your suggestion sounds reasonable. However, I would just like to > avoid sending a newer version just for these since this patch-set is > already a dependency for others [1] [2]. > > If you agree then I can send a follow up patch to get rid of all the > short reference names in this document. > > [1] https://patchwork.ozlabs.org/project/uboot/list/?series=396399 > [2] https://patchwork.ozlabs.org/project/uboot/list/?series=396742 Please go ahead and fix this as a follow up patch. I don't see any reason to hold up this series. -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH v6 08/11] doc: devicetree: Updates for devicetree-rebasing subtree
schema. For > installation > +instructions, refer to the DT schema project page (dtschema_). instructions, refer to the `DT schema project page`_. > + > +Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be > +installed. Ensure they are in your PATH (~/.local/bin by default). > + > +You should also install yamllint (used by dtschema when present). On Debian/ > +Ubuntu systems:: > + > +apt install yamllint > + > +Running checks > +~~ > + > +In order to perform validation of DTB files, use the ``dtbs_check`` target:: > + > +make dtbs_check > + > +It is also possible to run checks with a subset of matching schema files by > +setting the ``DT_SCHEMA_FILES`` variable to 1 or more specific schema files > or > +patterns (partial match of a fixed string). Each file or pattern should be > +separated by ':'. > + > +:: > + > +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml:rtc.yaml > +make dtbs_check DT_SCHEMA_FILES=/gpio/ > +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml > + > + > Relocation, SPL and TPL > --- > > @@ -260,8 +333,10 @@ used it before Linux (e.g. snow). The two projects > developed in parallel > and there are still some differences in the bindings for certain boards. > While there has been discussion of having a separate repository for > devicetree > files, in practice the Linux kernel Git repository has become the place where > -these are stored, with U-Boot taking copies and adding tweaks with > u-boot.dtsi > -files. > +these are stored, with U-Boot taking copies via devicetree-rebasing repo these are stored, with U-Boot taking copies via the `devicetree-rebasing repository`_ > +(see: dtrepo_) and adding tweaks with u-boot.dtsi files. and adding tweaks with u-boot.dtsi files. > > .. _dtspec: https://www.devicetree.org/specifications/ > .. _dtlist: https://www.spinics.net/lists/devicetree-compiler/ > +.. _dtrepo: > https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git .. _devicetree-rebasing repository: https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git > +.. _dtschema: https://github.com/devicetree-org/dt-schema/tree/main .. _DT schema project page: https://github.com/devicetree-org/dt-schema/tree/main Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
[PATCH v3 7/8] pmic: raa215300: Bind sysreset driver
If SYSRESET support is enabled for the RAA215300 PMIC, we need to bind
the raa215300_sysreset driver as a child device of the PMIC.
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
drivers/power/pmic/raa215300.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
index b93a0d3a084a..a581a1f6dc15 100644
--- a/drivers/power/pmic/raa215300.c
+++ b/drivers/power/pmic/raa215300.c
@@ -29,6 +29,15 @@ static const struct udevice_id raa215300_ids[] = {
static int raa215300_bind(struct udevice *dev)
{
+ if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
+ struct driver *drv =
lists_driver_lookup_name("raa215300_sysreset");
+ if (!drv)
+ return -ENOENT;
+
+ return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
+ NULL);
+ }
+
return 0;
}
--
2.44.0
[PATCH v3 8/8] board: rzg2l: Support reset via Renesas RAA215300 PMIC
With the SYSRESET subsystem enabled we do not need to implement
reset_cpu() in the board directory.
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
board/renesas/rzg2l/rzg2l.c | 8
configs/renesas_rzg2l_smarc_defconfig | 2 ++
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
index 73201a8c69e5..0f6d6e7f514f 100644
--- a/board/renesas/rzg2l/rzg2l.c
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -56,11 +56,3 @@ int board_init(void)
{
return 0;
}
-
-void reset_cpu(void)
-{
- /*
-* TODO: Implement reset support once TrustedFirmware supports
-* the appropriate call.
-*/
-}
diff --git a/configs/renesas_rzg2l_smarc_defconfig
b/configs/renesas_rzg2l_smarc_defconfig
index 2cab79329db4..21365a21fe8c 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RAA215300=y
--
2.44.0
[PATCH v3 6/8] sysreset: Support reset via Renesas RAA215300 PMIC
This patch adds support for resetting a board via the RAA215300 PMIC.
Note that the RAA215300 documentation names the available reset types
differently to u-boot:
* A "warm" reset via the RAA215300 PMIC will fully reset the SoC
(CPU & GPIOs), so this corresponds to SYSRESET_COLD.
* A "cold" reset via the RAA215300 PMIC will cycle all power supply
rails, so this corresponds to SYSRESET_POWER.
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
drivers/sysreset/Kconfig | 6 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_raa215300.c | 58 +++
3 files changed, 65 insertions(+)
create mode 100644 drivers/sysreset/sysreset_raa215300.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 0e52f996283c..49c0787b26d8 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -229,6 +229,12 @@ config SYSRESET_MPC83XX
help
Reboot support for NXP MPC83xx SoCs.
+config SYSRESET_RAA215300
+ bool "Support sysreset via Renesas RAA215300 PMIC"
+ depends on PMIC_RAA215300
+ help
+ Add support for the system reboot via the Renesas RAA215300 PMIC.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index c9f1c625aebb..e0e732205df3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
+obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_raa215300.c
b/drivers/sysreset/sysreset_raa215300.c
new file mode 100644
index ..32dfcb0aec84
--- /dev/null
+++ b/drivers/sysreset/sysreset_raa215300.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+
+#define RAA215300_REG_SWRESET 0x6D
+#define RAA215300_COLD_RESET BIT(0)
+#define RAA215300_WARM_RESET BIT(1)
+
+static int raa215300_sysreset_request(struct udevice *dev, enum sysreset_t
type)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ret;
+ u8 val;
+
+ /*
+* The RAA215300 documentation names the available reset types
+* differently to u-boot:
+*
+* - A "warm" reset via the RAA215300 PMIC will fully reset the SoC
+* (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
+*
+* - A "cold" reset via the RAA215300 PMIC will cycle all power supply
+* rails, so this corresponds to SYSRESET_POWER.
+*/
+ switch (type) {
+ case SYSRESET_COLD:
+ val = RAA215300_WARM_RESET;
+ break;
+
+ case SYSRESET_POWER:
+ val = RAA215300_COLD_RESET;
+ break;
+
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ ret = pmic_reg_write(pmic, RAA215300_REG_SWRESET, val);
+ if (ret)
+ return ret;
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops raa215300_sysreset_ops = {
+ .request = raa215300_sysreset_request,
+};
+
+U_BOOT_DRIVER(raa215300_sysreset) = {
+ .name = "raa215300_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = _sysreset_ops,
+};
--
2.44.0
[PATCH v3 5/8] board: rzg2l: Enable access to Renesas RAA215300 PMIC
Enable the appropriate PMIC driver as well as the `pmic` command. Signed-off-by: Paul Barker --- configs/renesas_rzg2l_smarc_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index ad46297c6619..2cab79329db4 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_PMIC=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -49,6 +50,8 @@ CONFIG_DM_I2C=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RAA215300=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -- 2.44.0
[PATCH v3 4/8] pmic: Add Renesas RAA215300 PMIC driver
The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.
The raa215300_bind() function is added as a stub, binding of the
sysreset driver will be added in a later patch.
Additional features of this PMIC (such as reset control) may be
supported by future patches.
Signed-off-by: Paul Barker
---
drivers/power/pmic/Kconfig | 9
drivers/power/pmic/Makefile| 1 +
drivers/power/pmic/raa215300.c | 41 ++
3 files changed, 51 insertions(+)
create mode 100644 drivers/power/pmic/raa215300.c
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 454a6e0cf87a..9b61b18e11fd 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -404,6 +404,15 @@ config PMIC_TPS65219
help
The TPS65219 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+config PMIC_RAA215300
+ bool "Renesas RAA215300 PMIC driver"
+ depends on DM_PMIC
+ help
+ The Renesas RAA215300 PMIC driver includes RTC support, system reset
+ support and several voltage regulators. For now, this driver simply
+ allows register access and will bind the sysreset driver
+ (CONFIG_SYSRESET_RAA215300) if it is enabled.
endif
config PMIC_TPS65217
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 55ee614364be..a2d59deeed8b 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
+obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
new file mode 100644
index ..b93a0d3a084a
--- /dev/null
+++ b/drivers/power/pmic/raa215300.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define RAA215300_REG_COUNT 0x80
+
+static int raa215300_reg_count(struct udevice *dev)
+{
+ return RAA215300_REG_COUNT;
+}
+
+static struct dm_pmic_ops raa215300_ops = {
+ .reg_count = raa215300_reg_count,
+ .read = dm_i2c_read,
+ .write = dm_i2c_write,
+};
+
+static const struct udevice_id raa215300_ids[] = {
+ { .compatible = "renesas,raa215300" },
+ { /* sentinel */ }
+};
+
+static int raa215300_bind(struct udevice *dev)
+{
+ return 0;
+}
+
+U_BOOT_DRIVER(raa215300_pmic) = {
+ .name = "raa215300_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = raa215300_ids,
+ .bind = raa215300_bind,
+ .ops = _ops,
+};
--
2.44.0
[PATCH v3 3/8] i2c: rzg2l: Add I2C driver for RZ/G2L family
This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC, also known as the RIIC module. This patch is based on both the u-boot driver in the Renesas RZ BSP 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit 0dd3ee311255). Support for deblocking the I2C bus is included as this may be needed after triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC asserts the reset line before the SoC completes the I2C write transaction with obvious bus locking effects). If the SDA line is observed to be low during initialisation, we automatically attempt to deblock. [1]: https://github.com/renesas-rz/renesas-u-boot-cip Signed-off-by: Paul Barker Reviewed-by: Marek Vasut --- arch/arm/mach-rmobile/Kconfig | 1 + configs/renesas_rzg2l_smarc_defconfig | 2 + drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/rz_riic.c | 624 ++ 5 files changed, 635 insertions(+) create mode 100644 drivers/i2c/rz_riic.c diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 2bb96749fc0d..38ede6e0b5b5 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -78,6 +78,7 @@ config RZG2L imply RENESAS_SDHI imply RZG2L_GPIO imply SCIF_CONSOLE + imply SYS_I2C_RZ_RIIC imply SYS_MALLOC_F help Enable support for the Renesas RZ/G2L family of SoCs. Currently diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index e45579ae6b98..ad46297c6619 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_EXT2=y @@ -44,6 +45,7 @@ CONFIG_CLK=y CONFIG_CLK_RENESAS=y # CONFIG_CLK_RCAR_GEN3 is not set CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 4f42200f3923..d2a3a13493aa 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP have several I2C ports and all are provided, controlled by the device tree. +config SYS_I2C_RZ_RIIC + bool "Renesas RZ/G2L RIIC driver" + depends on RZG2L && DM_I2C + help + Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC + family. + config SYS_I2C_SANDBOX bool "Sandbox I2C driver" depends on SANDBOX && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index a96a8c7e955e..692f63bafd02 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o +obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c new file mode 100644 index ..5f3f8d1b24b7 --- /dev/null +++ b/drivers/i2c/rz_riic.c @@ -0,0 +1,624 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L I2C (RIIC) driver + * + * Copyright (C) 2021-2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RIIC_ICCR1 0x00 +#define RIIC_ICCR2 0x04 +#define RIIC_ICMR1 0x08 +#define RIIC_ICMR2 0x0c +#define RIIC_ICMR3 0x10 +#define RIIC_ICFER 0x14 +#define RIIC_ICSER 0x18 +#define RIIC_ICIER 0x1c +#define RIIC_ICSR1 0x20 +#define RIIC_ICSR2 0x24 +#define RIIC_ICSAR00x28 +#define RIIC_ICBRL 0x34 +#define RIIC_ICBRH 0x38 +#define RIIC_ICDRT 0x3c +#define RIIC_ICDRR 0x40 + +/* ICCR1 */ +#define ICCR1_ICE BIT(7) +#define ICCR1_IICRST BIT(6) +#define ICCR1_CLO BIT(5) +#define ICCR1_SOWP BIT(4) +#define ICCR1_SCLO BIT(3) +#define ICCR1_SDAO BIT(2) +#define ICCR1_SCLI BIT(1) +#define ICCR1_SDAI BIT(0) + +/* ICCR2 */ +#define ICCR2_BBSY BIT(7) +#define ICCR2_MST BIT(6) +#define ICCR2_TRS BIT(5) +#define ICCR2_SP BIT(3) +#define ICCR2_RS BIT(2) +#define ICCR2_ST BIT(1) + +/* ICMR1 */ +#define ICMR1_MTWP BIT(7) +#define ICMR1_CKS_MASK GENMASK(6, 4) +#define ICMR1_BCWP BIT(3) +#define ICMR1_BC_MASK GENMASK(2, 0) + +#define ICMR1_CKS(x) (((x) << 4) & ICMR1_CKS_MASK) +#define ICMR1_BC(x)((x) & ICMR1_BC_MASK) + +/* ICMR2 */ +#define ICMR2_DLCS BIT(7) +#define ICMR2_SDDL_MASKGENMASK(6, 4) +#define ICMR2_TMOH
[PATCH v3 2/8] arm: dts: rzg2l: Sync with Linux v6.7
Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.7 (commit 0dd3ee311255).
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
arch/arm/dts/r9a07g044.dtsi | 16 -
arch/arm/dts/r9a07g044l2-smarc.dts| 21 +++
arch/arm/dts/rz-smarc-common.dtsi | 18 +-
arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 +++
arch/arm/dts/rzg2l-smarc-som.dtsi | 22 ++--
arch/arm/dts/rzg2l-smarc.dtsi | 43 +--
6 files changed, 118 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
index 232910e07444..66f68fc2b241 100644
--- a/arch/arm/dts/r9a07g044.dtsi
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -223,20 +223,20 @@
,
;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
- "tgiv0", "tgie0", "tgif0",
- "tgia1", "tgib1", "tgiv1", "tgiu1",
- "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
- "tgiv3",
+ "tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
- "tgiv4",
+ "tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
- "tgiv6",
+ "tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
- "tgiv7",
+ "tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
- "tgiv8", "tgiu8";
+ "tciv8", "tciu8";
clocks = < CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <>;
resets = < R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts
b/arch/arm/dts/r9a07g044l2-smarc.dts
index bc2af6c92ccd..568d49cfe44a 100644
--- a/arch/arm/dts/r9a07g044l2-smarc.dts
+++ b/arch/arm/dts/r9a07g044l2-smarc.dts
@@ -6,6 +6,27 @@
*/
/dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
+ */
+#define PMOD_MTU3 0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm/dts/rz-smarc-common.dtsi
b/arch/arm/dts/rz-smarc-common.dtsi
index 3962d47b3e59..b7a3e6caa386 100644
--- a/arch/arm/dts/rz-smarc-common.dtsi
+++ b/arch/arm/dts/rz-smarc-common.dtsi
@@ -32,12 +32,6 @@
stdout-path = "serial0:115200n8";
};
- audio_mclock: audio_mclock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -55,7 +49,7 @@
};
codec_dai: simple-audio-card,codec {
- clocks = <_mclock&g
[PATCH v3 1/8] clk: renesas: Confirm all clock & reset changes on RZ/G2L
When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.
Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().
This change is needed for reliable initialization of the I2C driver
which is added in a following patch.
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
drivers/clk/renesas/rzg2l-cpg.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index e54508c35ce2..dba009997a81 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -23,10 +23,18 @@
#include
#include
#include
+#include
#include "rzg2l-cpg.h"
+/*
+ * Monitor registers for both clock and reset signals are offset by 0x180 from
+ * the corresponding control registers.
+ */
#define CLK_MON_R(reg) (0x180 + (reg))
+#define RST_MON_R(reg) (0x180 + (reg))
+
+#define CPG_TIMEOUT_MSEC 100
static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int
id);
static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char
*name);
@@ -83,9 +91,9 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
value |= BIT(mod_clk->bit);
writel(value, data->base + mod_clk->off);
- if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
-value, (value & BIT(mod_clk->bit)),
-10)) {
+ if (enable && wait_for_bit_32(data->base + CLK_MON_R(mod_clk->off),
+ BIT(mod_clk->bit), enable,
+ CPG_TIMEOUT_MSEC, false)) {
dev_err(clk->dev, "Timeout\n");
return -ETIMEDOUT;
}
@@ -420,7 +428,8 @@ static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl,
bool asserted)
value |= BIT(rst->bit);
writel(value, data->base + rst->off);
- return 0;
+ return wait_for_bit_32(data->base + RST_MON_R(rst->off), BIT(rst->bit),
+ asserted, CPG_TIMEOUT_MSEC, false);
}
static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)
--
2.44.0
[PATCH v3 0/8] Add i2c and reset support for Renesas RZ/G2L
This patch series extends the support for the Renesas RZ/G2L SMARC EVK board (based on the R9A07G044L2 SoC) to include the following new features: * I2C bus support, including automatic deblocking if SDA is stuck low due to another device on the board. * Basic PMIC support, with the ability to read, write & dump PMIC registers. * Support for requesting system reset (SYSRESET_COLD or SYSRESET_POWER) via the PMIC. Along the way we fix the CPG driver to confirm all clock & reset changes before returning, and update the device tree to align with Linux 6.7. This series has been tested on RZ/G2L hardware, and the full u-boot GitLab CI pipeline has been executed in our internal GitLab instance. Changes from v2: * Split the addition of RZ/G2L PMIC support into two patches: one to add the PMIC driver and one to modify the defconfig. * Collected Marek's Reviewed-by tags. Changes from v1: * Rebased on U-Boot v2024.04-rc2 and re-tested. * Sync with Linux v6.7 instead of v6.6. * Add raa215300_bind() as a stub in patch 4. * Split up the addition of sysreset support into 3 patches: patch 5 adds the driver, patch 6 binds it with the pmic driver and patch 7 enables sysreset for the RZ/G2L. Paul Barker (8): clk: renesas: Confirm all clock & reset changes on RZ/G2L arm: dts: rzg2l: Sync with Linux v6.7 i2c: rzg2l: Add I2C driver for RZ/G2L family pmic: Add Renesas RAA215300 PMIC driver board: rzg2l: Enable access to Renesas RAA215300 PMIC sysreset: Support reset via Renesas RAA215300 PMIC pmic: raa215300: Bind sysreset driver board: rzg2l: Support reset via Renesas RAA215300 PMIC arch/arm/dts/r9a07g044.dtsi | 16 +- arch/arm/dts/r9a07g044l2-smarc.dts| 21 + arch/arm/dts/rz-smarc-common.dtsi | 18 +- arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 + arch/arm/dts/rzg2l-smarc-som.dtsi | 22 +- arch/arm/dts/rzg2l-smarc.dtsi | 43 +- arch/arm/mach-rmobile/Kconfig | 1 + board/renesas/rzg2l/rzg2l.c | 8 - configs/renesas_rzg2l_smarc_defconfig | 7 + drivers/clk/renesas/rzg2l-cpg.c | 17 +- drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/rz_riic.c | 624 ++ drivers/power/pmic/Kconfig| 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/raa215300.c| 50 ++ drivers/sysreset/Kconfig | 6 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_raa215300.c | 58 ++ 19 files changed, 896 insertions(+), 34 deletions(-) create mode 100644 drivers/i2c/rz_riic.c create mode 100644 drivers/power/pmic/raa215300.c create mode 100644 drivers/sysreset/sysreset_raa215300.c base-commit: d49fa3defa50c6d3f04acbb52fd486c13c14ab6a -- 2.44.0
Re: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family
On 26/02/2024 17:43, Biju Das wrote: > > >> -Original Message- >> From: U-Boot On Behalf Of Paul Barker >> Sent: Monday, February 26, 2024 3:06 PM >> To: Marek Vasut ; Nobuhiro Iwamatsu >> >> Cc: Paul Barker ; u-boot@lists.denx.de >> Subject: [PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family >> >> This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC, >> also known as the RIIC module. >> >> This patch is based on both the u-boot driver in the Renesas RZ BSP >> 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit >> 0dd3ee311255). >> >> Support for deblocking the I2C bus is included as this may be needed after >> triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC >> asserts the reset line before the SoC completes the I2C write transaction >> with obvious bus locking effects). If the SDA line is observed to be low >> during initialisation, we automatically attempt to deblock. >> >> [1]: >> >> Signed-off-by: Paul Barker >> eviewed-by: Marek Vasut > > Typo. R is missing in the Rb tag. Good catch - I pasted it right in the first patch but messed it up here somehow. Hopefully Marek can fix this when applying if there's nothing else that needs changing. > > Also change log is missing. The changelog is in the cover letter [1]. [1]: https://lore.kernel.org/u-boot/20240226150536.1690-1-paul.barker...@bp.renesas.com/ Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
[PATCH v2 7/7] board: rzg2l: Support reset via Renesas RAA215300 PMIC
With the SYSRESET subsystem enabled we do not need to implement
reset_cpu() in the board directory.
Signed-off-by: Paul Barker
---
board/renesas/rzg2l/rzg2l.c | 8
configs/renesas_rzg2l_smarc_defconfig | 2 ++
2 files changed, 2 insertions(+), 8 deletions(-)
diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
index 73201a8c69e5..0f6d6e7f514f 100644
--- a/board/renesas/rzg2l/rzg2l.c
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -56,11 +56,3 @@ int board_init(void)
{
return 0;
}
-
-void reset_cpu(void)
-{
- /*
-* TODO: Implement reset support once TrustedFirmware supports
-* the appropriate call.
-*/
-}
diff --git a/configs/renesas_rzg2l_smarc_defconfig
b/configs/renesas_rzg2l_smarc_defconfig
index 2cab79329db4..21365a21fe8c 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RAA215300=y
--
2.43.2
[PATCH v2 6/7] pmic: raa215300: Bind sysreset driver
If SYSRESET support is enabled for the RAA215300 PMIC, we need to bind
the raa215300_sysreset driver as a child device of the PMIC.
Signed-off-by: Paul Barker
---
drivers/power/pmic/raa215300.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
index b93a0d3a084a..a581a1f6dc15 100644
--- a/drivers/power/pmic/raa215300.c
+++ b/drivers/power/pmic/raa215300.c
@@ -29,6 +29,15 @@ static const struct udevice_id raa215300_ids[] = {
static int raa215300_bind(struct udevice *dev)
{
+ if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
+ struct driver *drv =
lists_driver_lookup_name("raa215300_sysreset");
+ if (!drv)
+ return -ENOENT;
+
+ return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
+ NULL);
+ }
+
return 0;
}
--
2.43.2
[PATCH v2 4/7] pmic: Add Renesas RAA215300 PMIC driver
The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.
The raa215300_bind() function is added as a stub, binding of the
sysreset driver will be added in a later patch.
Additional features of this PMIC (such as reset control) may be
supported by future patches.
Signed-off-by: Paul Barker
---
configs/renesas_rzg2l_smarc_defconfig | 3 ++
drivers/power/pmic/Kconfig| 9 ++
drivers/power/pmic/Makefile | 1 +
drivers/power/pmic/raa215300.c| 41 +++
4 files changed, 54 insertions(+)
create mode 100644 drivers/power/pmic/raa215300.c
diff --git a/configs/renesas_rzg2l_smarc_defconfig
b/configs/renesas_rzg2l_smarc_defconfig
index ad46297c6619..2cab79329db4 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -49,6 +50,8 @@ CONFIG_DM_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RAA215300=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 454a6e0cf87a..9b61b18e11fd 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -404,6 +404,15 @@ config PMIC_TPS65219
help
The TPS65219 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+config PMIC_RAA215300
+ bool "Renesas RAA215300 PMIC driver"
+ depends on DM_PMIC
+ help
+ The Renesas RAA215300 PMIC driver includes RTC support, system reset
+ support and several voltage regulators. For now, this driver simply
+ allows register access and will bind the sysreset driver
+ (CONFIG_SYSRESET_RAA215300) if it is enabled.
endif
config PMIC_TPS65217
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 55ee614364be..a2d59deeed8b 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
+obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
new file mode 100644
index ..b93a0d3a084a
--- /dev/null
+++ b/drivers/power/pmic/raa215300.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define RAA215300_REG_COUNT 0x80
+
+static int raa215300_reg_count(struct udevice *dev)
+{
+ return RAA215300_REG_COUNT;
+}
+
+static struct dm_pmic_ops raa215300_ops = {
+ .reg_count = raa215300_reg_count,
+ .read = dm_i2c_read,
+ .write = dm_i2c_write,
+};
+
+static const struct udevice_id raa215300_ids[] = {
+ { .compatible = "renesas,raa215300" },
+ { /* sentinel */ }
+};
+
+static int raa215300_bind(struct udevice *dev)
+{
+ return 0;
+}
+
+U_BOOT_DRIVER(raa215300_pmic) = {
+ .name = "raa215300_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = raa215300_ids,
+ .bind = raa215300_bind,
+ .ops = _ops,
+};
--
2.43.2
[PATCH v2 5/7] sysreset: Support reset via Renesas RAA215300 PMIC
This patch adds support for resetting a board via the RAA215300 PMIC.
Note that the RAA215300 documentation names the available reset types
differently to u-boot:
* A "warm" reset via the RAA215300 PMIC will fully reset the SoC
(CPU & GPIOs), so this corresponds to SYSRESET_COLD.
* A "cold" reset via the RAA215300 PMIC will cycle all power supply
rails, so this corresponds to SYSRESET_POWER.
Signed-off-by: Paul Barker
---
drivers/sysreset/Kconfig | 6 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_raa215300.c | 58 +++
3 files changed, 65 insertions(+)
create mode 100644 drivers/sysreset/sysreset_raa215300.c
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 0e52f996283c..49c0787b26d8 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -229,6 +229,12 @@ config SYSRESET_MPC83XX
help
Reboot support for NXP MPC83xx SoCs.
+config SYSRESET_RAA215300
+ bool "Support sysreset via Renesas RAA215300 PMIC"
+ depends on PMIC_RAA215300
+ help
+ Add support for the system reboot via the Renesas RAA215300 PMIC.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index c9f1c625aebb..e0e732205df3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
+obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_raa215300.c
b/drivers/sysreset/sysreset_raa215300.c
new file mode 100644
index ..32dfcb0aec84
--- /dev/null
+++ b/drivers/sysreset/sysreset_raa215300.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+
+#define RAA215300_REG_SWRESET 0x6D
+#define RAA215300_COLD_RESET BIT(0)
+#define RAA215300_WARM_RESET BIT(1)
+
+static int raa215300_sysreset_request(struct udevice *dev, enum sysreset_t
type)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ret;
+ u8 val;
+
+ /*
+* The RAA215300 documentation names the available reset types
+* differently to u-boot:
+*
+* - A "warm" reset via the RAA215300 PMIC will fully reset the SoC
+* (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
+*
+* - A "cold" reset via the RAA215300 PMIC will cycle all power supply
+* rails, so this corresponds to SYSRESET_POWER.
+*/
+ switch (type) {
+ case SYSRESET_COLD:
+ val = RAA215300_WARM_RESET;
+ break;
+
+ case SYSRESET_POWER:
+ val = RAA215300_COLD_RESET;
+ break;
+
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ ret = pmic_reg_write(pmic, RAA215300_REG_SWRESET, val);
+ if (ret)
+ return ret;
+
+ return -EINPROGRESS;
+}
+
+static struct sysreset_ops raa215300_sysreset_ops = {
+ .request = raa215300_sysreset_request,
+};
+
+U_BOOT_DRIVER(raa215300_sysreset) = {
+ .name = "raa215300_sysreset",
+ .id = UCLASS_SYSRESET,
+ .ops = _sysreset_ops,
+};
--
2.43.2
[PATCH v2 3/7] i2c: rzg2l: Add I2C driver for RZ/G2L family
This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC, also known as the RIIC module. This patch is based on both the u-boot driver in the Renesas RZ BSP 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.7 driver (commit 0dd3ee311255). Support for deblocking the I2C bus is included as this may be needed after triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC asserts the reset line before the SoC completes the I2C write transaction with obvious bus locking effects). If the SDA line is observed to be low during initialisation, we automatically attempt to deblock. [1]: https://github.com/renesas-rz/renesas-u-boot-cip Signed-off-by: Paul Barker eviewed-by: Marek Vasut --- arch/arm/mach-rmobile/Kconfig | 1 + configs/renesas_rzg2l_smarc_defconfig | 2 + drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/rz_riic.c | 624 ++ 5 files changed, 635 insertions(+) create mode 100644 drivers/i2c/rz_riic.c diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 2bb96749fc0d..38ede6e0b5b5 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -78,6 +78,7 @@ config RZG2L imply RENESAS_SDHI imply RZG2L_GPIO imply SCIF_CONSOLE + imply SYS_I2C_RZ_RIIC imply SYS_MALLOC_F help Enable support for the Renesas RZ/G2L family of SoCs. Currently diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index e45579ae6b98..ad46297c6619 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -24,6 +24,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_EXT2=y @@ -44,6 +45,7 @@ CONFIG_CLK=y CONFIG_CLK_RENESAS=y # CONFIG_CLK_RCAR_GEN3 is not set CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 4f42200f3923..d2a3a13493aa 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP have several I2C ports and all are provided, controlled by the device tree. +config SYS_I2C_RZ_RIIC + bool "Renesas RZ/G2L RIIC driver" + depends on RZG2L && DM_I2C + help + Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC + family. + config SYS_I2C_SANDBOX bool "Sandbox I2C driver" depends on SANDBOX && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index a96a8c7e955e..692f63bafd02 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o +obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c new file mode 100644 index ..5f3f8d1b24b7 --- /dev/null +++ b/drivers/i2c/rz_riic.c @@ -0,0 +1,624 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L I2C (RIIC) driver + * + * Copyright (C) 2021-2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RIIC_ICCR1 0x00 +#define RIIC_ICCR2 0x04 +#define RIIC_ICMR1 0x08 +#define RIIC_ICMR2 0x0c +#define RIIC_ICMR3 0x10 +#define RIIC_ICFER 0x14 +#define RIIC_ICSER 0x18 +#define RIIC_ICIER 0x1c +#define RIIC_ICSR1 0x20 +#define RIIC_ICSR2 0x24 +#define RIIC_ICSAR00x28 +#define RIIC_ICBRL 0x34 +#define RIIC_ICBRH 0x38 +#define RIIC_ICDRT 0x3c +#define RIIC_ICDRR 0x40 + +/* ICCR1 */ +#define ICCR1_ICE BIT(7) +#define ICCR1_IICRST BIT(6) +#define ICCR1_CLO BIT(5) +#define ICCR1_SOWP BIT(4) +#define ICCR1_SCLO BIT(3) +#define ICCR1_SDAO BIT(2) +#define ICCR1_SCLI BIT(1) +#define ICCR1_SDAI BIT(0) + +/* ICCR2 */ +#define ICCR2_BBSY BIT(7) +#define ICCR2_MST BIT(6) +#define ICCR2_TRS BIT(5) +#define ICCR2_SP BIT(3) +#define ICCR2_RS BIT(2) +#define ICCR2_ST BIT(1) + +/* ICMR1 */ +#define ICMR1_MTWP BIT(7) +#define ICMR1_CKS_MASK GENMASK(6, 4) +#define ICMR1_BCWP BIT(3) +#define ICMR1_BC_MASK GENMASK(2, 0) + +#define ICMR1_CKS(x) (((x) << 4) & ICMR1_CKS_MASK) +#define ICMR1_BC(x)((x) & ICMR1_BC_MASK) + +/* ICMR2 */ +#define ICMR2_DLCS BIT(7) +#define ICMR2_SDDL_MASKGENMASK(6, 4) +#define ICMR2_TMOH
[PATCH v2 2/7] arm: dts: rzg2l: Sync with Linux v6.7
Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.7 (commit 0dd3ee311255).
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
arch/arm/dts/r9a07g044.dtsi | 16 -
arch/arm/dts/r9a07g044l2-smarc.dts| 21 +++
arch/arm/dts/rz-smarc-common.dtsi | 18 +-
arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 +++
arch/arm/dts/rzg2l-smarc-som.dtsi | 22 ++--
arch/arm/dts/rzg2l-smarc.dtsi | 43 +--
6 files changed, 118 insertions(+), 22 deletions(-)
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
index 232910e07444..66f68fc2b241 100644
--- a/arch/arm/dts/r9a07g044.dtsi
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -223,20 +223,20 @@
,
;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
- "tgiv0", "tgie0", "tgif0",
- "tgia1", "tgib1", "tgiv1", "tgiu1",
- "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
- "tgiv3",
+ "tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
- "tgiv4",
+ "tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
- "tgiv6",
+ "tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
- "tgiv7",
+ "tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
- "tgiv8", "tgiu8";
+ "tciv8", "tciu8";
clocks = < CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <>;
resets = < R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts
b/arch/arm/dts/r9a07g044l2-smarc.dts
index bc2af6c92ccd..568d49cfe44a 100644
--- a/arch/arm/dts/r9a07g044l2-smarc.dts
+++ b/arch/arm/dts/r9a07g044l2-smarc.dts
@@ -6,6 +6,27 @@
*/
/dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
+ */
+#define PMOD_MTU3 0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm/dts/rz-smarc-common.dtsi
b/arch/arm/dts/rz-smarc-common.dtsi
index 3962d47b3e59..b7a3e6caa386 100644
--- a/arch/arm/dts/rz-smarc-common.dtsi
+++ b/arch/arm/dts/rz-smarc-common.dtsi
@@ -32,12 +32,6 @@
stdout-path = "serial0:115200n8";
};
- audio_mclock: audio_mclock {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <11289600>;
- };
-
snd_rzg2l: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -55,7 +49,7 @@
};
codec_dai: simple-audio-card,codec {
- clocks = <_mclock&g
[PATCH v2 1/7] clk: renesas: Confirm all clock & reset changes on RZ/G2L
When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.
Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().
This change is needed for reliable initialization of the I2C driver
which is added in a following patch.
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
drivers/clk/renesas/rzg2l-cpg.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index e54508c35ce2..dba009997a81 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -23,10 +23,18 @@
#include
#include
#include
+#include
#include "rzg2l-cpg.h"
+/*
+ * Monitor registers for both clock and reset signals are offset by 0x180 from
+ * the corresponding control registers.
+ */
#define CLK_MON_R(reg) (0x180 + (reg))
+#define RST_MON_R(reg) (0x180 + (reg))
+
+#define CPG_TIMEOUT_MSEC 100
static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int
id);
static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char
*name);
@@ -83,9 +91,9 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
value |= BIT(mod_clk->bit);
writel(value, data->base + mod_clk->off);
- if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
-value, (value & BIT(mod_clk->bit)),
-10)) {
+ if (enable && wait_for_bit_32(data->base + CLK_MON_R(mod_clk->off),
+ BIT(mod_clk->bit), enable,
+ CPG_TIMEOUT_MSEC, false)) {
dev_err(clk->dev, "Timeout\n");
return -ETIMEDOUT;
}
@@ -420,7 +428,8 @@ static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl,
bool asserted)
value |= BIT(rst->bit);
writel(value, data->base + rst->off);
- return 0;
+ return wait_for_bit_32(data->base + RST_MON_R(rst->off), BIT(rst->bit),
+ asserted, CPG_TIMEOUT_MSEC, false);
}
static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)
--
2.43.2
[PATCH v2 0/7] Add i2c and reset support for Renesas RZ/G2L
This patch series extends the support for the Renesas RZ/G2L SMARC EVK board (based on the R9A07G044L2 SoC) to include the following new features: * I2C bus support, including automatic deblocking if SDA is stuck low due to another device on the board. * Basic PMIC support, with the ability to read, write & dump PMIC registers. * Support for requesting system reset (SYSRESET_COLD or SYSRESET_POWER) via the PMIC. Along the way we fix the CPG driver to confirm all clock & reset changes before returning, and update the device tree to align with Linux 6.7. This series has been tested on RZ/G2L hardware, and the full u-boot GitLab CI pipeline has been executed in our internal GitLab instance. Changes from v1: * Rebased on U-Boot v2024.04-rc2 and re-tested. * Sync with Linux v6.7 instead of v6.6. * Add raa215300_bind() as a stub in patch 4. * Split up the addition of sysreset support into 3 patches: patch 5 adds the driver, patch 6 binds it with the pmic driver and patch 7 enables sysreset for the RZ/G2L. Paul Barker (7): clk: renesas: Confirm all clock & reset changes on RZ/G2L arm: dts: rzg2l: Sync with Linux v6.7 i2c: rzg2l: Add I2C driver for RZ/G2L family pmic: Add Renesas RAA215300 PMIC driver sysreset: Support reset via Renesas RAA215300 PMIC pmic: raa215300: Bind sysreset driver board: rzg2l: Support reset via Renesas RAA215300 PMIC arch/arm/dts/r9a07g044.dtsi | 16 +- arch/arm/dts/r9a07g044l2-smarc.dts| 21 + arch/arm/dts/rz-smarc-common.dtsi | 18 +- arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 + arch/arm/dts/rzg2l-smarc-som.dtsi | 22 +- arch/arm/dts/rzg2l-smarc.dtsi | 43 +- arch/arm/mach-rmobile/Kconfig | 1 + board/renesas/rzg2l/rzg2l.c | 8 - configs/renesas_rzg2l_smarc_defconfig | 7 + drivers/clk/renesas/rzg2l-cpg.c | 17 +- drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/rz_riic.c | 624 ++ drivers/power/pmic/Kconfig| 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/raa215300.c| 50 ++ drivers/sysreset/Kconfig | 6 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_raa215300.c | 58 ++ 19 files changed, 896 insertions(+), 34 deletions(-) create mode 100644 drivers/i2c/rz_riic.c create mode 100644 drivers/power/pmic/raa215300.c create mode 100644 drivers/sysreset/sysreset_raa215300.c base-commit: 37345abb97ef0dd9c50a03b2a72617612dcae585 -- 2.43.2
Re: [PATCH 1/3] mmc: Convert hs400_tuning flag from u8 to bool
On 20/02/2024 11:27, Marek Vasut wrote: > On 2/20/24 11:57, Paul Barker wrote: >> On 20/02/2024 08:37, Marek Vasut wrote: >>> This hs400_tuning is a flag, make it bool. No functional change. >>> This will be useful in the following patch, which adds another >>> more generic flag, where the compiler can better use the space >>> now reserved for the u8 to store more flags in it. >> >> The minimum size for a bool is one byte so there likely won't be any >> improvement in struct size from using bool instead of u8 for >> `hs400_tuning` here and `tuning` added in the next patch. I still think >> it's a good change to make though, bool is the right type for an on/off >> flag. > > The compiler does not do boolean packing in structures ? The compiler will only pack booleans if you explicitly say that only one bit of memory is needed, e.g.: bool tuning:1; bool hs400_tuning:1; Otherwise the assumption is that you may wish to take the address of each field and so each one must have a distinct address in memory. Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH] mmc: Drop unused mmc_send_tuning() cmd_error parameter
On 20/02/2024 11:26, Marek Vasut wrote:
> On 2/20/24 11:50, Paul Barker wrote:
>> On 20/02/2024 08:36, Marek Vasut wrote:
>>> The cmd_error parameter is not used, remove it.
>>> [snip]
>>>
>>> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
>>> index 5a0c61daed5..296aaee7331 100644
>>> --- a/drivers/mmc/mtk-sd.c
>>> +++ b/drivers/mmc/mtk-sd.c
>>> @@ -1131,7 +1131,7 @@ static int hs400_tune_response(struct udevice *dev,
>>> u32 opcode)
>>> i << PAD_CMD_TUNE_RX_DLY3_S);
>>>
>>> for (j = 0; j < 3; j++) {
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> cmd_delay |= (1 << i);
>>> } else {
>>> @@ -1181,7 +1181,7 @@ static int msdc_tune_response(struct udevice *dev,
>>> u32 opcode)
>>> i << MSDC_PAD_TUNE_CMDRDLY_S);
>>>
>>> for (j = 0; j < 3; j++) {
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> rise_delay |= (1 << i);
>>> } else {
>>> @@ -1203,7 +1203,7 @@ static int msdc_tune_response(struct udevice *dev,
>>> u32 opcode)
>>> i << MSDC_PAD_TUNE_CMDRDLY_S);
>>>
>>> for (j = 0; j < 3; j++) {
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err) {
>>> fall_delay |= (1 << i);
>>> } else {
>>> @@ -1238,7 +1238,7 @@ skip_fall:
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
>>> i << MSDC_PAD_TUNE_CMDRRDLY_S);
>>>
>>> - mmc_send_tuning(mmc, opcode, _err);
>>> + cmd_err = mmc_send_tuning(mmc, opcode);
>>> if (!cmd_err)
>>> internal_delay |= (1 << i);
>>> }
>>> @@ -1264,7 +1264,6 @@ static int msdc_tune_data(struct udevice *dev, u32
>>> opcode)
>>> struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
>>> u8 final_delay, final_maxlen;
>>> void __iomem *tune_reg = >base->pad_tune;
>>> - int cmd_err;
>>> int i, ret;
>>>
>>> if (host->dev_comp->pad_tune0)
>>> @@ -1277,10 +1276,10 @@ static int msdc_tune_data(struct udevice *dev, u32
>>> opcode)
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>>> i << MSDC_PAD_TUNE_DATRRDLY_S);
>>>
>>> - ret = mmc_send_tuning(mmc, opcode, _err);
>>> + ret = mmc_send_tuning(mmc, opcode);
>>> if (!ret) {
>>> rise_delay |= (1 << i);
>>> - } else if (cmd_err) {
>>> + } else {
>>> /* in this case, retune response is needed */
>>> ret = msdc_tune_response(dev, opcode);
>>> if (ret)
>>> @@ -1300,10 +1299,10 @@ static int msdc_tune_data(struct udevice *dev, u32
>>> opcode)
>>> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
>>> i << MSDC_PAD_TUNE_DATRRDLY_S);
>>>
>>> - ret = mmc_send_tuning(mmc, opcode, _err);
>>> + ret = mmc_send_tuning(mmc, opcode);
>>> if (!ret) {
>>> fall_delay |= (1 << i);
>>> - } else if (cmd_err) {
>>> + } else {
>>> /* in this case, retune response is needed */
>>> ret = msdc_tune_response(dev, opcode);
>>> if (ret)
>>
>> This driver (mtk-sd.c) seems to be the only one that really uses the
>> `cmd_error` parameter.
>>
>> Looking at the implementation of mmc_send_tuning() in Linux, this
>> parameter is used so that a caller can differentiate between a command
>> error and a data error. I don't know enough details about MMC to
>> understand the distinction, but I assume there is some reason for this.
>> So I wonder if the mtk-sd driver will still work if those error paths
>> are taken for data errors and not just command errors. Has this change
>> been tested on some board which uses this driver?
>
> Not by me, so far this driver used uninitialized error value and assumed
> it was initialized as far as I can tell, so it is likely already broken.
+To: Ryder Lee, Weijie Gao, Chunfeng Yun
+Cc: gss_mtk_uboot_upstr...@mediatek.com
Do you have any input as ARM MEDIATEK maintainers?
--
Paul Barker
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Re: [PATCH] mmc: renesas-sdhi: Stop transmission in case tuning block transfer fails
On 20/02/2024 08:38, Marek Vasut wrote:
> The current code uses the state of tuning block received by SCC to
> determine whether or not to send transmission stop command. This is
> not correct. Use the state of tuning block transfer to determine
> whether or not to send transmission stop command instead, because
> the transmission stop command has to be sent in case the tuning
> block transfer failed.
>
> This requires two changes, separate variable to store and check the
> state of tuning block received by SCC, and another separate variable
> to store and check return value from transmission stop command.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Hai Pham
> Cc: Jaehoon Chung
> Cc: Nobuhiro Iwamatsu
> Cc: Paul Barker
> Cc: Peng Fan
> Cc: Sean Anderson
> Cc: Tom Rini
> Cc: Yoshihiro Shimoda
> ---
> drivers/mmc/renesas-sdhi.c | 14 +++---
> 1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index 316b75b35fe..c4d0733b621 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -568,8 +568,8 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint
> opcode)
> struct mmc *mmc = upriv->mmc;
> unsigned int tap_num;
> unsigned int taps = 0;
> - int i, ret = 0;
> - u32 caps;
> + int i, ret = 0, sret;
> + u32 caps, reg;
>
> /* Only supported on Renesas RCar */
> if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
> @@ -612,8 +612,8 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint
> opcode)
> if (ret == 0)
> taps |= BIT(i);
>
> - ret = renesas_sdhi_compare_scc_data(priv);
> - if (ret == 0)
> + reg = renesas_sdhi_compare_scc_data(priv);
> + if (reg == 0)
> priv->smpcmp |= BIT(i);
>
> mdelay(1);
> @@ -624,9 +624,9 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint
> opcode)
>* eMMC.
>*/
> if (ret && (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
> - ret = mmc_send_stop_transmission(mmc, false);
> - if (ret < 0)
> - dev_dbg(dev, "Tuning abort fail (%d)\n", ret);
> + sret = mmc_send_stop_transmission(mmc, false);
> + if (sret < 0)
> + dev_dbg(dev, "Tuning abort fail (%d)\n", sret);
> }
> }
>
Reviewed-by: Paul Barker
Tested-by: Paul Barker
(tested on RZ/G2L with commit ad50a8151387 from
https://source.denx.de/u-boot/custodians/u-boot-sh)
--
Paul Barker
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Re: [PATCH] mmc: tmio: Check INFO1 for completion during DMA transfer
On 20/02/2024 08:38, Marek Vasut wrote:
> In case a CRC error occurs during DMA transfer, the transfer completion
> flag is not set in TMIO_SD_DMA_INFO1 and the transfer would eventually
> time out. The timeout could be very long in case the transfer consists
> of a large amount of blocks, the base timeout is 10 seconds and every
> block adds 100 us more.
>
> In case a CRC error does occur, a completion flag is set in a different
> register, TMIO_SD_INFO1. Use this other completion flag to detect DMA
> transfer ended and stop waiting for TMIO_SD_DMA_INFO1 completion flag.
> This reduces the lengthy timeout in case of an error. The unconditional
> check of TMIO_SD_DMA_INFO2 register for DMA related errors must not be
> skipped in any case to actually recognize the DMA error and report it.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Hai Pham
> Cc: Jaehoon Chung
> Cc: Nobuhiro Iwamatsu
> Cc: Paul Barker
> Cc: Peng Fan
> Cc: Sean Anderson
> Cc: Tom Rini
> Cc: Yoshihiro Shimoda
> ---
> drivers/mmc/tmio-common.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c
> index 890c496b535..719c4830bc3 100644
> --- a/drivers/mmc/tmio-common.c
> +++ b/drivers/mmc/tmio-common.c
> @@ -299,7 +299,13 @@ static int tmio_sd_dma_wait_for_irq(struct udevice *dev,
> u32 flag,
> struct tmio_sd_priv *priv = dev_get_priv(dev);
> long wait = 100 + 10 * blocks;
>
> - while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
> + for (;;) {
> + if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)
> + break;
> +
> + if (tmio_sd_readl(priv, TMIO_SD_INFO1) & TMIO_SD_INFO1_CMP)
> + break;
> +
> if (wait-- < 0) {
> dev_err(dev, "timeout during DMA\n");
> return -ETIMEDOUT;
Reviewed-by: Paul Barker
Tested-by: Paul Barker
(tested on RZ/G2L with commit ad50a8151387 from
https://source.denx.de/u-boot/custodians/u-boot-sh)
--
Paul Barker
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Re: [PATCH 3/3] mmc: renesas-sdhi: Do not access SCC during tuning in send_cmd callback
On 20/02/2024 08:37, Marek Vasut wrote: > Do not access SCC when sending commands during tuning operation as that > will disrupt the tuning operation. The tuning operation is adjusting the > SCC settings itself in execute_tuning callback. > > When renesas_sdhi_execute_tuning() is called by the MMC core code, a loop > which consists of renesas_sdhi_prepare_tuning(), mmc_send_tuning() and > renesas_sdhi_compare_scc_data() iterates over each SCC tuning tap. > > The renesas_sdhi_prepare_tuning() configures the SCC tuning tap number into > hardware, mmc_send_tuning() triggers transfer of tuning block which depends > on the bus mode for which the bus is currently being tuned, this information > is supplied by the MMC core code, and finally renesas_sdhi_compare_scc_data() > tests the received tuning block for validity. > > Because renesas_sdhi_prepare_tuning() configures the SCC tuning tap into > the hardware to fit the tuning operation, mmc_send_tuning() which triggers > command transfer using renesas_sdhi_send_cmd() must not manipulate with > the SCC in any way. Currently renesas_sdhi_send_cmd() does unconditionally > call renesas_sdhi_check_scc_error(), which may adjust the SCC tuning tap > position by writing RENESAS_SDHI_SCC_TAPSET, which would overwrite the > required tuning configuration set by renesas_sdhi_prepare_tuning() and > disrupt the tuning operation. > > Fix this by skipping the renesas_sdhi_check_scc_error() call in case the > MMC subsystem is in tuning state. This way, the SCC settings are left > unmodified by command transfer during tuning operation. > > Signed-off-by: Marek Vasut > --- > Cc: Hai Pham > Cc: Jaehoon Chung > Cc: Nobuhiro Iwamatsu > Cc: Paul Barker > Cc: Peng Fan > Cc: Sean Anderson > Cc: Tom Rini > Cc: Yoshihiro Shimoda > --- > drivers/mmc/renesas-sdhi.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c > index 9770b6bb5e1..316b75b35fe 100644 > --- a/drivers/mmc/renesas-sdhi.c > +++ b/drivers/mmc/renesas-sdhi.c > @@ -798,9 +798,12 @@ static int renesas_sdhi_send_cmd(struct udevice *dev, > struct mmc_cmd *cmd, > #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \ > CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ > CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) > + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); > struct tmio_sd_priv *priv = dev_get_priv(dev); > + struct mmc *mmc = upriv->mmc; > > - renesas_sdhi_check_scc_error(dev); > + if (!mmc->tuning) > + renesas_sdhi_check_scc_error(dev); > > if (cmd->cmdidx == MMC_CMD_SEND_STATUS) > renesas_sdhi_adjust_hs400_mode_enable(priv); Reviewed-by: Paul Barker Tested-by: Paul Barker (tested on RZ/G2L with commit ad50a8151387 from https://source.denx.de/u-boot/custodians/u-boot-sh) -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 2/3] mmc: Add generic tuning flag
On 20/02/2024 08:37, Marek Vasut wrote:
> Set generic mmc->tuning flag when performing tuning to indicate
> this condition to drivers. Drivers may use this to bypass various
> checks during tuning.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Hai Pham
> Cc: Jaehoon Chung
> Cc: Nobuhiro Iwamatsu
> Cc: Paul Barker
> Cc: Peng Fan
> Cc: Sean Anderson
> Cc: Tom Rini
> Cc: Yoshihiro Shimoda
> ---
> drivers/mmc/mmc-uclass.c | 8 +++-
> include/mmc.h| 1 +
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
> index 328456831dd..304bd5eaee2 100644
> --- a/drivers/mmc/mmc-uclass.c
> +++ b/drivers/mmc/mmc-uclass.c
> @@ -124,7 +124,13 @@ static int dm_mmc_execute_tuning(struct udevice *dev,
> uint opcode)
>
> int mmc_execute_tuning(struct mmc *mmc, uint opcode)
> {
> - return dm_mmc_execute_tuning(mmc->dev, opcode);
> + int ret;
> +
> + mmc->tuning = true;
> + ret = dm_mmc_execute_tuning(mmc->dev, opcode);
> + mmc->tuning = false;
> +
> + return ret;
> }
> #endif
>
> diff --git a/include/mmc.h b/include/mmc.h
> index 92cffc6a19a..47ccf5f45a1 100644
> --- a/include/mmc.h
> +++ b/include/mmc.h
> @@ -736,6 +736,7 @@ struct mmc {
> * accessing the boot partitions
> */
> u32 quirks;
> + bool tuning;
> bool hs400_tuning;
>
> enum bus_mode user_speed_mode; /* input speed mode from user */
Reviewed-by: Paul Barker
Tested-by: Paul Barker
(tested on RZ/G2L with commit ad50a8151387 from
https://source.denx.de/u-boot/custodians/u-boot-sh)
--
Paul Barker
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Re: [PATCH 1/3] mmc: Convert hs400_tuning flag from u8 to bool
On 20/02/2024 08:37, Marek Vasut wrote: > This hs400_tuning is a flag, make it bool. No functional change. > This will be useful in the following patch, which adds another > more generic flag, where the compiler can better use the space > now reserved for the u8 to store more flags in it. The minimum size for a bool is one byte so there likely won't be any improvement in struct size from using bool instead of u8 for `hs400_tuning` here and `tuning` added in the next patch. I still think it's a good change to make though, bool is the right type for an on/off flag. So I think the commit message needs a little clarification. Other than that, Reviewed-by: Paul Barker Tested-by: Paul Barker (tested on RZ/G2L with commit ad50a8151387 from https://source.denx.de/u-boot/custodians/u-boot-sh) Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH] mmc: Drop unused mmc_send_tuning() cmd_error parameter
On 20/02/2024 08:36, Marek Vasut wrote:
> The cmd_error parameter is not used, remove it.
> [snip]
>
> diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
> index 5a0c61daed5..296aaee7331 100644
> --- a/drivers/mmc/mtk-sd.c
> +++ b/drivers/mmc/mtk-sd.c
> @@ -1131,7 +1131,7 @@ static int hs400_tune_response(struct udevice *dev, u32
> opcode)
> i << PAD_CMD_TUNE_RX_DLY3_S);
>
> for (j = 0; j < 3; j++) {
> - mmc_send_tuning(mmc, opcode, _err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
> if (!cmd_err) {
> cmd_delay |= (1 << i);
> } else {
> @@ -1181,7 +1181,7 @@ static int msdc_tune_response(struct udevice *dev, u32
> opcode)
> i << MSDC_PAD_TUNE_CMDRDLY_S);
>
> for (j = 0; j < 3; j++) {
> - mmc_send_tuning(mmc, opcode, _err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
> if (!cmd_err) {
> rise_delay |= (1 << i);
> } else {
> @@ -1203,7 +1203,7 @@ static int msdc_tune_response(struct udevice *dev, u32
> opcode)
> i << MSDC_PAD_TUNE_CMDRDLY_S);
>
> for (j = 0; j < 3; j++) {
> - mmc_send_tuning(mmc, opcode, _err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
> if (!cmd_err) {
> fall_delay |= (1 << i);
> } else {
> @@ -1238,7 +1238,7 @@ skip_fall:
> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M,
> i << MSDC_PAD_TUNE_CMDRRDLY_S);
>
> - mmc_send_tuning(mmc, opcode, _err);
> + cmd_err = mmc_send_tuning(mmc, opcode);
> if (!cmd_err)
> internal_delay |= (1 << i);
> }
> @@ -1264,7 +1264,6 @@ static int msdc_tune_data(struct udevice *dev, u32
> opcode)
> struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, };
> u8 final_delay, final_maxlen;
> void __iomem *tune_reg = >base->pad_tune;
> - int cmd_err;
> int i, ret;
>
> if (host->dev_comp->pad_tune0)
> @@ -1277,10 +1276,10 @@ static int msdc_tune_data(struct udevice *dev, u32
> opcode)
> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
> i << MSDC_PAD_TUNE_DATRRDLY_S);
>
> - ret = mmc_send_tuning(mmc, opcode, _err);
> + ret = mmc_send_tuning(mmc, opcode);
> if (!ret) {
> rise_delay |= (1 << i);
> - } else if (cmd_err) {
> + } else {
> /* in this case, retune response is needed */
> ret = msdc_tune_response(dev, opcode);
> if (ret)
> @@ -1300,10 +1299,10 @@ static int msdc_tune_data(struct udevice *dev, u32
> opcode)
> clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M,
> i << MSDC_PAD_TUNE_DATRRDLY_S);
>
> - ret = mmc_send_tuning(mmc, opcode, _err);
> + ret = mmc_send_tuning(mmc, opcode);
> if (!ret) {
> fall_delay |= (1 << i);
> - } else if (cmd_err) {
> + } else {
> /* in this case, retune response is needed */
> ret = msdc_tune_response(dev, opcode);
> if (ret)
This driver (mtk-sd.c) seems to be the only one that really uses the
`cmd_error` parameter.
Looking at the implementation of mmc_send_tuning() in Linux, this
parameter is used so that a caller can differentiate between a command
error and a data error. I don't know enough details about MMC to
understand the distinction, but I assume there is some reason for this.
So I wonder if the mtk-sd driver will still work if those error paths
are taken for data errors and not just command errors. Has this change
been tested on some board which uses this driver?
Thanks,
--
Paul Barker
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Re: [PATCH 3/5] i2c: rzg2l: Add I2C driver for RZ/G2L family
On 02/12/2023 18:18, Marek Vasut wrote: > On 11/19/23 21:48, Paul Barker wrote: >> On Sun, Nov 19, 2023 at 09:15:36PM +0100, Marek Vasut wrote: >>> On 11/15/23 18:40, Paul Barker wrote: >>>> This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) >>>> SoC, also known as the RIIC module. >>>> >>>> This patch is based on both the u-boot driver in the Renesas RZ BSP >>>> 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.6 driver >>>> (commit ffc253263a13). >>>> >>>> Support for deblocking the I2C bus is included as this may be needed >>>> after triggering a reset via the Power Management IC (PMIC) over I2C >>>> (the PMIC asserts the reset line before the SoC completes the I2C write >>>> transaction with obvious bus locking effects). If the SDA line is >>>> observed to be low during initialisation, we automatically attempt to >>>> deblock. >>>> >>>> [1]: https://github.com/renesas-rz/renesas-u-boot-cip >>>> >>>> Signed-off-by: Paul Barker >>> >>> The driver seems very similar to drivers/i2c/rcar_iic.c , can there be some >>> code reuse ? >> >> My initial idea was to extend the R-Car iic driver but I quickly saw >> that would be very messy. All the registers and bits are in different >> places, the calculations are different (particularly in regard to >> setting bus speed) and the read/write process has more edge cases for >> the RZ/G2L. The bus recovery mechanism we use also doesn't exist on >> previous R-Car SoCs. >> >> The Linux drivers for these modules are also separate, see >> drivers/i2c/busses/i2c-sh_mobile.c (for R-Car and earlier SoCs) and >> drivers/i2c/busses/i2c-riic.c (for RZ/G2L) in the Linux kernel. > > Ah, I thought some of the registers were the same, but indeed the RZG > core is much more extensive. > > You should either use devm_clk_*() in probe() or implement .remove > callback. With that fixed: > > Reviewed-by: Marek Vasut > > And sorry for the delayed reply. Here's an even more delayed reply from me! I've been busy on other work but getting back to u-boot now. Using devm_clk_get() in the probe function for this driver doesn't seem to be needed. The `struct clk` is stored in a `struct riic_priv`, this is allocated and freed automatically for each device as we set `priv_auto` in the driver definition. Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH v5 08/11] doc: devicetree: Updates for devicetree-rebasing subtree
On 14/02/2024 13:32, Sumit Garg wrote: > On Wed, 14 Feb 2024 at 03:01, Paul Barker > wrote: >> On 02/02/2024 13:05, Sumit Garg wrote: >>> +Dependencies >>> + >>> + >>> +The DT schema project must be installed in order to validate the DT schema >>> +binding documents and validate DTS files using the DT schema. The DT schema >>> +project can be installed with pip:: >>> + >>> +pip3 install dtschema >> >> Unfortunately this won't work on recent distro versions, e.g. on Debian >> 12 I get: >> >> error: externally-managed-environment >> >> × This environment is externally managed >> ╰─> To install Python packages system-wide, try apt install >> python3-xyz, where xyz is the package you are trying to >> install. >> >> If you wish to install a non-Debian-packaged Python package, >> create a virtual environment using python3 -m venv path/to/venv. >> Then use path/to/venv/bin/python and path/to/venv/bin/pip. Make >> sure you have python3-full installed. >> >> If you wish to install a non-Debian packaged Python application, >> it may be easiest to use pipx install xyz, which will manage a >> virtual environment for you. Make sure you have pipx installed. >> >> See /usr/share/doc/python3.11/README.venv for more information. >> >> note: If you believe this is a mistake, please contact your Python >> installation or OS distribution provider. You can override this, at the >> risk of breaking your Python installation or OS, by passing >> --break-system-packages. >> hint: See PEP 668 for the detailed specification. >> >> I don't have a good solution to recommend here - there's no consensus on >> how to install Python tools for use in development. You could use >> `pipx`, you could create a virtualenv, and I'm sure there are other >> options as well. Perhaps we just need to leave it up to the reader to >> find out how to install dtschema on their system. > > I suppose you haven't installed python3-pip package [1] on your Debian > 12. BTW, `pip3` is being used as the common way to install dtschema > [2]. Also, every user may not be aware about python virtual > environments. So it's better to provide the commonly used pip3 option > for installation. The python3-pip package is installed, it's the pip3 program that is printing the error message I saw. This is the new behaviour in Debian 12, also seen in rolling distributions like Arch Linux and OpenSuSE Tumbleweed since the middle of last year. There is a good guide to this from Python=>Speed [1] and more detail in the Python packaging spec [2]. Sadly it's something we now have to live with in recent Linux distro releases, and I expect all distros will enable this in upcoming releases. [1]: https://pythonspeed.com/articles/externally-managed-environment-pep-668/ [2]: https://packaging.python.org/en/latest/specifications/externally-managed-environments/#externally-managed-environments Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 2/2] doc: Rework the gcc section to reflect general build instructions
On 15/02/2024 21:10, Tom Rini wrote:
> The first big issue is that the "gcc" file talked a lot about the
> general build requirements as well, but was titled in a gcc-centric
> manner. Solve this by renaming the file to compile.rst and more fully
> reflecting that it is general build instructions. Next, add a section
> about the prebuilt toolchains that are recommended (as they are the ones
> we use in CI), and update a few places to reference these vendor-neutral
> tools.
>
> Next, we can include the reproducible builds section directly in the
> compile instructions rather than as a small standalone file.
>
> Finally, we update the sandbox document to reflect both the name change
> as well as what is specifically required to build sandbox.
>
> Signed-off-by: Tom Rini
> ---
> Cc: Heinrich Schuchardt
> ---
> doc/arch/sandbox/sandbox.rst | 5 ++-
> doc/build/{gcc.rst => compile.rst} | 64 ++
> doc/build/index.rst| 3 +-
> doc/build/reproducible.rst | 27 -
> 4 files changed, 61 insertions(+), 38 deletions(-)
> rename doc/build/{gcc.rst => compile.rst} (73%)
> delete mode 100644 doc/build/reproducible.rst
>
> diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst
> index 5f8db126657f..f2ed5a25c115 100644
> --- a/doc/arch/sandbox/sandbox.rst
> +++ b/doc/arch/sandbox/sandbox.rst
> @@ -39,11 +39,12 @@ integers can only be built on 64-bit hosts.
>
> Note that standalone/API support is not available at present.
>
> -
> Prerequisites
> -
>
> -Install the dependencies noted in :doc:`../../build/gcc`.
> +In addition to the normal dependencies shows in the :doc:`general build
> +instructions <../../build/compile>` to enable display support SDL2 libraries
> +need to be available.
I find this a little unclear. Perhaps:
To enable display support, SDL2 libraries need to be available in
addition to the normal dependencies shown in the :doc:`general build
instructions <../../build/compile>`.
>
>
> Basic Operation
> diff --git a/doc/build/gcc.rst b/doc/build/compile.rst
> similarity index 73%
> rename from doc/build/gcc.rst
> rename to doc/build/compile.rst
> index 3c6465772729..ef9c8545835a 100644
> --- a/doc/build/gcc.rst
> +++ b/doc/build/compile.rst
> @@ -1,11 +1,19 @@
> -Building with GCC
> -=
> +Building U-Boot
> +===
>
> Dependencies
>
>
> -For building U-Boot you need a GCC compiler for your host platform. If you
> -are not building on the target platform you further need a GCC cross
> compiler.
> +For building U-Boot you need the general build tools such as `make` and a C
> +compiler for your host platform. Next, if you are not building on the same
> +architecture as the target platform you further need a C cross compiler.
> +Furthermore, some target platforms require additional host tools to be
> present
> +and their package names may vary slightly dependinng on the naming scheme
> used
s/dependinng/depending/
Thanks,
--
Paul Barker
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Re: [PATCH 1/2] doc: Update our clang documentation to reflect current status
On 15/02/2024 21:10, Tom Rini wrote: > First, since this document was written the biggest challenges at the > time are simply not applicable anymore. Second, we need to list the > challenges which are preventing more platforms from being able to be > built with Clang today. Next, we update the general wording to be host > distribution agnostic. Finally, the section about xenguest_arm64 issues > is not present anymore. > > Signed-off-by: Tom Rini > --- > Cc: Mark Kettenis > This does leave the FreeBSD section unchanged and should likely be > looked at again by someone with a BSD build machine available. > --- > doc/build/clang.rst | 85 +++-- > 1 file changed, 21 insertions(+), 64 deletions(-) > > diff --git a/doc/build/clang.rst b/doc/build/clang.rst > index 09bb988e9236..d8c554982567 100644 > --- a/doc/build/clang.rst > +++ b/doc/build/clang.rst > @@ -1,34 +1,27 @@ > Building with Clang > === > > -The biggest problem when trying to compile U-Boot with Clang is that almost > all > -archs rely on storing gd in a global register and the Clang 3.5 user manual > -states: "Clang does not support global register variables; this is unlikely > to > -be implemented soon because it requires additional LLVM backend support." > - > -The ARM backend can be instructed not to use the r9 and x18 registers using > --ffixed-r9 or -ffixed-x18 respectively. As global registers themselves are > not > -supported inline assembly is needed to get and set the r9 or x18 value. This > -leads to larger code then strictly necessary, but at least works. > - > -Debian based > - > - > -Required packages can be installed via apt, e.g. > - > -.. code-block:: bash > - > -sudo apt-get install clang > - > -We make use of the CROSS_COMPILE variable to derive the build target which is > -passed as the --target parameter to clang. > - > -The CROSS_COMPILE variable further determines the paths to other build > -tools. As assembler we use the binary pointed to by '$(CROSS_COMPILE)as' > -instead of the LLVM integrated assembler (IAS). > - > -Here is an example demonstrating building U-Boot for the Raspberry Pi 2 > -using clang: > +In general terms, U-Boot support building with Clang as the C compiler and s/support/supports/ > +building and booting our "sandbox" target is part of CI. Are you saying that building the sandbox target with Clang then booting it is part of CI? I think this sentence needs re-wording to make it a little clearer. Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH v5 08/11] doc: devicetree: Updates for devicetree-rebasing subtree
T schema > +binding documents and validate DTS files using the DT schema. The DT schema > +project can be installed with pip:: > + > +pip3 install dtschema Unfortunately this won't work on recent distro versions, e.g. on Debian 12 I get: error: externally-managed-environment × This environment is externally managed ╰─> To install Python packages system-wide, try apt install python3-xyz, where xyz is the package you are trying to install. If you wish to install a non-Debian-packaged Python package, create a virtual environment using python3 -m venv path/to/venv. Then use path/to/venv/bin/python and path/to/venv/bin/pip. Make sure you have python3-full installed. If you wish to install a non-Debian packaged Python application, it may be easiest to use pipx install xyz, which will manage a virtual environment for you. Make sure you have pipx installed. See /usr/share/doc/python3.11/README.venv for more information. note: If you believe this is a mistake, please contact your Python installation or OS distribution provider. You can override this, at the risk of breaking your Python installation or OS, by passing --break-system-packages. hint: See PEP 668 for the detailed specification. I don't have a good solution to recommend here - there's no consensus on how to install Python tools for use in development. You could use `pipx`, you could create a virtualenv, and I'm sure there are other options as well. Perhaps we just need to leave it up to the reader to find out how to install dtschema on their system. > + > +Note that 'dtschema' installation requires 'swig' and Python development > files > +installed first. Please, refer to the GCC build documentation for > installation > +instructions :doc:`../../build/gcc`. > + > +Several executables (dt-doc-validate, dt-mk-schema, dt-validate) will be > +installed. Ensure they are in your PATH (~/.local/bin by default). > + > +Recommended is also to install yamllint (used by dtschema when present). On "You should also install yamllint" > +Debian/Ubuntu systems:: > + > +apt install yamllint > + > +Running checks > +~~ > + > +In order to perform validation of DTB files, use the ``dtbs_check`` target:: > + > +make dtbs_check > + > +It is also possible to run checks with a subset of matching schema files by > +setting the ``DT_SCHEMA_FILES`` variable to 1 or more specific schema files > or > +patterns (partial match of a fixed string). Each file or pattern should be > +separated by ':'. > + > +:: > + > +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml:rtc.yaml > +make dtbs_check DT_SCHEMA_FILES=/gpio/ > +make dtbs_check DT_SCHEMA_FILES=trivial-devices.yaml > + > + > Relocation, SPL and TPL > ------- > > @@ -260,8 +336,9 @@ used it before Linux (e.g. snow). The two projects > developed in parallel > and there are still some differences in the bindings for certain boards. > While there has been discussion of having a separate repository for > devicetree > files, in practice the Linux kernel Git repository has become the place where > -these are stored, with U-Boot taking copies and adding tweaks with > u-boot.dtsi > -files. > +these are stored, with U-Boot taking copies via devicetree-rebasing repo > +(see: dtrepo_) and adding tweaks with u-boot.dtsi files. > > .. _dtspec: https://www.devicetree.org/specifications/ > .. _dtlist: https://www.spinics.net/lists/devicetree-compiler/ > +.. _dtrepo: > https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git Thanks, -- Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 3/3] ARM: renesas: Enable LTO on R-Car
On 11/02/2024 17:34, Marek Vasut wrote: > Enable LTO globally on Renesas R-Car platforms. This has been enabled > on a subset of boards already, but at this point it is safe to enable > it globally. This saves units or tens of kiB from the resulting build. > > Signed-off-by: Marek Vasut > --- > Cc: Niklas Söderlund > Cc: Paul Barker > --- > arch/arm/Kconfig | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 2/3] ARM: renesas: Set R-Car Gen2 board size limit to 512 kiB
On 11/02/2024 17:34, Marek Vasut wrote: > The maximum size of u-boot.img on R-Car Gen2 is 0x8 or 512 kiB, > set the limit to avoid overflows as new functionality gets pulled in. > > Signed-off-by: Marek Vasut > --- > Cc: Niklas Söderlund > Cc: Paul Barker > --- > Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 1/3] ARM: renesas: Disable EFI on R-Car Gen2
On 11/02/2024 17:34, Marek Vasut wrote: > These systems are unlikely to use EFI as this functionality has not been > enabled until it got pulled in by Kconfig default. This functionality > does add some 60-70 kiB to the u-boot.img size, which overflows the size > limit. Disable it. > > Signed-off-by: Marek Vasut > --- > Cc: Niklas Söderlund > Cc: Paul Barker > --- > configs/alt_defconfig | 2 ++ > configs/blanche_defconfig | 2 ++ > configs/gose_defconfig| 2 ++ > configs/koelsch_defconfig | 2 ++ > configs/lager_defconfig | 2 ++ > configs/porter_defconfig | 2 ++ > configs/silk_defconfig| 2 ++ > configs/stout_defconfig | 2 ++ > 8 files changed, 16 insertions(+) Reviewed-by: Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH v2] net: phy: Use PHY MDIO address from DT if available
On 28/01/2024 01:19, Marek Vasut wrote: > In case the PHY is fully described in DT, use PHY MDIO address > from DT directly instead of always using auto-detection. This > also fixes the behavior of 'mdio list' in such DT setup, which > now prints the PHY connected to the MAC correctly. > > Signed-off-by: Marek Vasut > --- > Cc: Joe Hershberger > Cc: Paul Barker > Cc: Ramon Fried > --- > V2: This patch is generic replacement for > - net: ravb: Use PHY MDIO address from DT if available > - net: sh_eth: Use PHY MDIO address from DT if available > --- > drivers/net/phy/ethernet_id.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c > index 877a51c3d00..6cb1fd4453e 100644 > --- a/drivers/net/phy/ethernet_id.c > +++ b/drivers/net/phy/ethernet_id.c > @@ -71,6 +71,9 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, > struct udevice *dev, > } > } > > + if (phyaddr == -1) > + phyaddr = ofnode_read_u32_default(phandle_args.node, "reg", -1); > + > id = vendor << 16 | device; > phydev = phy_device_create(bus, phyaddr, id, false); > if (phydev) Reviewed-by: Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 3/3] ARM: renesas: Drop include common.h
On 21/01/2024 17:31, Marek Vasut wrote: > The header file is not necessary in either of those files, > remove it as common.h is going away. > > Include missing asm/arch/rmobile.h in board/renesas/rcar-common/v3-common.c > to prevent build failure of r8a77970_eagle r8a779a0_falcon r8a77980_v3hsk > and r8a77970_v3msk . > > Include missing asm/u-boot.h in falcon.c and grpeach.c to fix build failure > due to missing definition of struct bd_info . Include errno.h in grpeach.c > to fix build error due to missing definition of EINVAL. > > Signed-off-by: Marek Vasut > --- > Cc: Adam Ford > Cc: Paul Barker > --- > board/renesas/alt/alt.c | 1 - > board/renesas/alt/alt_spl.c | 1 - > board/renesas/alt/qos.c | 1 - > board/renesas/blanche/blanche.c | 1 - > board/renesas/blanche/qos.c | 1 - > board/renesas/draak/draak.c | 1 - > board/renesas/falcon/falcon.c | 2 +- > board/renesas/gose/gose.c | 1 - > board/renesas/gose/gose_spl.c | 1 - > board/renesas/gose/qos.c | 1 - > board/renesas/grpeach/grpeach.c | 3 ++- > board/renesas/koelsch/koelsch.c | 1 - > board/renesas/koelsch/koelsch_spl.c | 1 - > board/renesas/koelsch/qos.c | 1 - > board/renesas/lager/lager.c | 1 - > board/renesas/lager/lager_spl.c | 1 - > board/renesas/lager/qos.c | 1 - > board/renesas/porter/porter.c | 1 - > board/renesas/porter/porter_spl.c | 1 - > board/renesas/porter/qos.c| 1 - > board/renesas/r2dplus/r2dplus.c | 1 - > board/renesas/rcar-common/common.c| 1 - > board/renesas/rcar-common/gen3-spl.c | 1 - > board/renesas/rcar-common/v3-common.c | 2 +- > board/renesas/salvator-x/salvator-x.c | 1 - > board/renesas/silk/qos.c | 1 - > board/renesas/silk/silk.c | 1 - > board/renesas/silk/silk_spl.c | 1 - > board/renesas/spider/spider.c | 1 - > board/renesas/stout/cpld.c| 1 - > board/renesas/stout/qos.c | 1 - > board/renesas/stout/stout.c | 1 - > board/renesas/stout/stout_spl.c | 1 - > board/renesas/ulcb/cpld.c | 1 - > board/renesas/ulcb/ulcb.c | 1 - > board/renesas/v3hsk/cpld.c| 1 - > board/renesas/v3msk/cpld.c| 1 - > board/renesas/whitehawk/whitehawk.c | 1 - > 38 files changed, 4 insertions(+), 38 deletions(-) > > diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c > index 85fbaf0b28b..be77cade01b 100644 > --- a/board/renesas/alt/alt.c > +++ b/board/renesas/alt/alt.c > @@ -5,7 +5,6 @@ > * Copyright (C) 2014, 2015 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/board/renesas/alt/alt_spl.c b/board/renesas/alt/alt_spl.c > index cdaa04e4f4c..fc9dac55e6a 100644 > --- a/board/renesas/alt/alt_spl.c > +++ b/board/renesas/alt/alt_spl.c > @@ -5,7 +5,6 @@ > * Copyright (C) 2018 Marek Vasut > */ > > -#include > #include > #include > #include > diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c > index 2f657505ceb..38dfa647e81 100644 > --- a/board/renesas/alt/qos.c > +++ b/board/renesas/alt/qos.c > @@ -6,7 +6,6 @@ > * > */ > > -#include > #include > #include > #include > diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c > index 8e1ae29e221..c6ecea2afcf 100644 > --- a/board/renesas/blanche/blanche.c > +++ b/board/renesas/blanche/blanche.c > @@ -6,7 +6,6 @@ > * Copyright (C) 2016 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/board/renesas/blanche/qos.c b/board/renesas/blanche/qos.c > index e3ad83ee0c2..3134b36a443 100644 > --- a/board/renesas/blanche/qos.c > +++ b/board/renesas/blanche/qos.c > @@ -5,7 +5,6 @@ > * Copyright (C) 2016 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c > index 1ed72d34a74..06a3a832984 100644 > --- a/board/renesas/draak/draak.c > +++ b/board/renesas/draak/draak.c > @@ -6,7 +6,6 @@ > * Copyright (C) 2017 Marek Vasut > */ > > -#include > #include > #include > #include > diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c > index 0aa0f1afcbf..cd86bb3108c 100644 > --- a/board/renesas/falcon/falcon.c > +++ b/board/renesas/falcon/falcon.c > @@ -6,7 +6,6 @@ > * Copyright (C) 2020 Renesas Electronics Corp. > */ > >
Re: [PATCH 2/3] pinctrl: renesas: Drop include common.h
On 21/01/2024 17:31, Marek Vasut wrote: > The header file is not necessary in either of those files, > remove it as common.h is going away. > > Signed-off-by: Marek Vasut > --- > Cc: Paul Barker > --- > drivers/pinctrl/renesas/pfc-r8a7790.c | 1 - > drivers/pinctrl/renesas/pfc-r8a7791.c | 1 - > drivers/pinctrl/renesas/pfc-r8a7792.c | 1 - > drivers/pinctrl/renesas/pfc-r8a7794.c | 1 - > drivers/pinctrl/renesas/pfc-r8a77951.c | 1 - > drivers/pinctrl/renesas/pfc-r8a7796.c | 1 - > drivers/pinctrl/renesas/pfc-r8a77965.c | 1 - > drivers/pinctrl/renesas/pfc-r8a77970.c | 1 - > drivers/pinctrl/renesas/pfc-r8a77980.c | 1 - > drivers/pinctrl/renesas/pfc-r8a77990.c | 1 - > drivers/pinctrl/renesas/pfc-r8a77995.c | 1 - > drivers/pinctrl/renesas/pfc-r8a779a0.c | 1 - > drivers/pinctrl/renesas/pfc-r8a779f0.c | 1 - > drivers/pinctrl/renesas/pfc-r8a779g0.c | 1 - > drivers/pinctrl/renesas/pfc.c | 1 - > drivers/pinctrl/renesas/pinctrl-rza1.c | 1 - > 16 files changed, 16 deletions(-) > > diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c > b/drivers/pinctrl/renesas/pfc-r8a7790.c > index 7203648bbc8..e1811c4c908 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a7790.c > +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c > @@ -8,7 +8,6 @@ > * Copyright (C) 2012 Kuninori Morimoto > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c > b/drivers/pinctrl/renesas/pfc-r8a7791.c > index b25453ed285..fa94a51e5e7 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a7791.c > +++ b/drivers/pinctrl/renesas/pfc-r8a7791.c > @@ -6,7 +6,6 @@ > * Copyright (C) 2014-2017 Cogent Embedded, Inc. > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c > b/drivers/pinctrl/renesas/pfc-r8a7792.c > index 08f1f97af6e..7c1e6d40749 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a7792.c > +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c > @@ -6,7 +6,6 @@ > * Copyright (C) 2016 Cogent Embedded, Inc., > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c > b/drivers/pinctrl/renesas/pfc-r8a7794.c > index e5d125ceca0..29eab2610c1 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a7794.c > +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c > @@ -7,7 +7,6 @@ > * Copyright (C) 2015-2017 Cogent Embedded, Inc. > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c > b/drivers/pinctrl/renesas/pfc-r8a77951.c > index 5d1c81c3eae..81568ae4a5e 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a77951.c > +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c > @@ -5,7 +5,6 @@ > * Copyright (C) 2015-2019 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c > b/drivers/pinctrl/renesas/pfc-r8a7796.c > index 163d1805dfb..3de43febbd3 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a7796.c > +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c > @@ -11,7 +11,6 @@ > * Copyright (C) 2015 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c > b/drivers/pinctrl/renesas/pfc-r8a77965.c > index 377143d3918..3a6813cee61 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a77965.c > +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c > @@ -12,7 +12,6 @@ > * Copyright (C) 2015 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c > b/drivers/pinctrl/renesas/pfc-r8a77970.c > index 1cc6fa4f3fc..3c9c060d245 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a77970.c > +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c > @@ -12,7 +12,6 @@ > * Copyright (C) 2015 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c > b/drivers/pinctrl/renesas/pfc-r8a77980.c > index 523faa0ac8f..14a4b4dc731 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a77980.c > +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c > @@ -12,7 +12,6 @@ > * Copyright (C) 2015 Renesas Electronics Corporation > */ > > -#include > #include > #include > #include > diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c > b/drivers/pinctrl/renesas/pfc-r8a77990.c > index 215a19ef9cd..e3a9c5e053d 100644 > --- a/drivers/pinctrl/renesas/pfc-r8a77990.c > +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c > @@
Re: [PATCH 1/3] clk: renesas: Drop include common.h
On 21/01/2024 17:31, Marek Vasut wrote: > The header file is not necessary in either of those files, > remove it as common.h is going away. > > Signed-off-by: Marek Vasut > --- > Cc: Lukasz Majewski > Cc: Paul Barker > Cc: Sean Anderson > --- > drivers/clk/renesas/clk-rcar-gen2.c | 1 - > drivers/clk/renesas/clk-rcar-gen3.c | 1 - > drivers/clk/renesas/r8a774a1-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a774b1-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a774c0-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a774e1-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a7790-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a7791-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a7792-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a7794-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a7796-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a77965-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a77970-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a77980-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a77995-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a779f0-cpg-mssr.c | 1 - > drivers/clk/renesas/r8a779g0-cpg-mssr.c | 1 - > drivers/clk/renesas/r9a06g032-clocks.c | 1 - > drivers/clk/renesas/rcar-cpg-lib.c | 1 - > drivers/clk/renesas/renesas-cpg-mssr.c | 1 - > 23 files changed, 23 deletions(-) > > diff --git a/drivers/clk/renesas/clk-rcar-gen2.c > b/drivers/clk/renesas/clk-rcar-gen2.c > index 850d6411190..66ffef96b69 100644 > --- a/drivers/clk/renesas/clk-rcar-gen2.c > +++ b/drivers/clk/renesas/clk-rcar-gen2.c > @@ -10,7 +10,6 @@ > * Copyright (C) 2016 Glider bvba > */ > > -#include > #include > #include > #include > diff --git a/drivers/clk/renesas/clk-rcar-gen3.c > b/drivers/clk/renesas/clk-rcar-gen3.c > index 0d274bb986e..196903e406c 100644 > --- a/drivers/clk/renesas/clk-rcar-gen3.c > +++ b/drivers/clk/renesas/clk-rcar-gen3.c > @@ -10,7 +10,6 @@ > * Copyright (C) 2016 Glider bvba > */ > > -#include > #include > #include > #include > diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > index 6f94906cc99..d23041a8026 100644 > --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c > @@ -9,7 +9,6 @@ > * Copyright (C) 2016 Glider bvba > */ > > -#include > #include > #include > > diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c > b/drivers/clk/renesas/r8a774b1-cpg-mssr.c > index 1a794980319..81d7dfe5421 100644 > --- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c > @@ -9,7 +9,6 @@ > * Copyright (C) 2016 Glider bvba > */ > > -#include > #include > #include > > diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c > b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > index ec8ce6ad7d6..f92fd25c0f7 100644 > --- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c > @@ -10,7 +10,6 @@ > * Copyright (C) 2015 Renesas Electronics Corp. > */ > > -#include > #include > #include > #include > diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c > b/drivers/clk/renesas/r8a774e1-cpg-mssr.c > index 6a8fe92b975..7c7cb7b6a05 100644 > --- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c > @@ -9,7 +9,6 @@ > * Copyright (C) 2015 Glider bvba > */ > > -#include > #include > #include > #include > diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c > b/drivers/clk/renesas/r8a7790-cpg-mssr.c > index 686f2af0052..190b68ee7d3 100644 > --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c > @@ -9,7 +9,6 @@ > * Copyright (C) 2013 Ideas On Board SPRL > */ > > -#include > #include > #include > #include > diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c > b/drivers/clk/renesas/r8a7791-cpg-mssr.c > index dcb0fd85c52..30711bf8921 100644 > --- a/drivers/clk/renesas/r8a7791-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c > @@ -9,7 +9,6 @@ > * Copyright (C) 2013 Ideas On Board SPRL > */ > > -#include > #include > #include > #include > diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c > b/drivers/clk/renesas/r8a7792-cpg-mssr.c > index 496e51aa73f..623981e9c38 100644 > --- a/drivers/clk/renesas/r8a7792-cpg-mssr.c > +++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c > @@ -9,7 +9,6 @@ > * Copyright (C) 2013 Ideas On Board SPRL > */ > > -#include >
Re: [PATCH 3/3] net: ravb: Use PHY MDIO address from DT if available
On 21/01/2024 17:29, Marek Vasut wrote: > In case the PHY is fully described in DT, use PHY MDIO address > from DT directly instead of always using auto-detection. This > also fixes the behavior of 'mdio list' in such DT setup, which > now prints the PHY connected to the MAC correctly. > > Signed-off-by: Marek Vasut > --- > Cc: Joe Hershberger > Cc: Paul Barker > Cc: Ramon Fried > --- > drivers/net/sh_eth.c | 10 -- > 1 file changed, 8 insertions(+), 2 deletions(-) I think the commit summaries are mixed up here - this patch says 'ravb' but changes 'sh_eth.c' and vice-versa with the other patch. > > diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c > index 7b1f59dc498..5e2e3054ecf 100644 > --- a/drivers/net/sh_eth.c > +++ b/drivers/net/sh_eth.c > @@ -12,6 +12,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -597,11 +598,16 @@ static int sh_eth_phy_config(struct udevice *dev) > struct sh_ether_priv *priv = dev_get_priv(dev); > struct eth_pdata *pdata = dev_get_plat(dev); > struct sh_eth_dev *eth = >shdev; > - int ret = 0; > struct sh_eth_info *port_info = >port_info[eth->port]; > struct phy_device *phydev; > + int phy_addr; > + int ret = 0; > + > + phy_addr = eth_phy_get_addr(dev); > + if (phy_addr < 0) > + phy_addr = -1; > > - phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface); > + phydev = phy_connect(priv->bus, phy_addr, dev, pdata->phy_interface); > if (!phydev) > return -ENODEV; > I have a local patch to handle (phy_addr < 0) in phy_connect_phy_id() and lookup the address there. I think that's the better place to handle this as it's a universal fix for all users of CONFIG_PHY_ETHERNET_ID. Unfortunately I've been distracted by some higher priority work but I'm hoping to get back to this soon. I can do some quick testing with that patch and send it this week if that's helpful. Thanks, Paul OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH] ARM: renesas: whitehawk: Drop extra leading space
On 21/01/2024 17:33, Marek Vasut wrote:
> Drop leading space in front of a comment. No functional change.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: Paul Barker
> ---
> board/renesas/whitehawk/whitehawk.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/board/renesas/whitehawk/whitehawk.c
> b/board/renesas/whitehawk/whitehawk.c
> index 3423ebd2995..a72f5e0a7a5 100644
> --- a/board/renesas/whitehawk/whitehawk.c
> +++ b/board/renesas/whitehawk/whitehawk.c
> @@ -31,7 +31,7 @@ static void init_generic_timer(void)
>
> static void init_gic_v3(void)
> {
> - /* GIC v3 power on */
> + /* GIC v3 power on */
> writel(BIT(1), GICR_LPI_PWRR);
>
> /* Wait till the WAKER_CA_BIT changes to 0 */
Simple enough.
Reviewed-by: Paul Barker
OpenPGP_0x27F4B3459F002257.asc
Description: OpenPGP public key
OpenPGP_signature.asc
Description: OpenPGP digital signature
Re: [PATCH 01/11] dt-bindings: power: Add R8A779H0 V4M SYSC power domain definitions
On 21/01/2024 17:41, Marek Vasut wrote: > From: Duy Nguyen > > Add power domain indices for R-Car V4M (R8A779H0). > > Signed-off-by: Duy Nguyen > Signed-off-by: Hai Pham > --- > Cc: Paul Barker > --- > include/dt-bindings/power/r8a779h0-sysc.h | 49 +++ > 1 file changed, 49 insertions(+) > create mode 100644 include/dt-bindings/power/r8a779h0-sysc.h We should reference the corresponding Linux kernel patch via lore.kernel.org if this isn't in the mainline kernel yet. Also, as a general series comment: I'd prefer to see a cover letter to say which interfaces and key features are supported on the V4M by this series. Is this enough to boot Linux from at least one interface (SDHI, Ethernet, etc)? Thanks, Paul OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 02/11] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions
On 21/01/2024 17:41, Marek Vasut wrote: > From: Duy Nguyen > > Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car > V4M (R8A779H0) SoC. > > Signed-off-by: Duy Nguyen > Signed-off-by: Hai Pham > --- > Cc: Paul Barker > --- > include/dt-bindings/clock/r8a779h0-cpg-mssr.h | 100 ++ > 1 file changed, 100 insertions(+) > create mode 100644 include/dt-bindings/clock/r8a779h0-cpg-mssr.h We should reference the corresponding Linux kernel patch via lore.kernel.org if this isn't in the mainline kernel yet. Thanks, Paul OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 03/11] clk: renesas: Add R8A779H0 V4M clock tables
On 21/01/2024 17:41, Marek Vasut wrote: > From: Hai Pham > > Add clock tables for R8A779H0 V4M SoC. > > Signed-off-by: Hai Pham > --- > Cc: Lukasz Majewski > Cc: Paul Barker > Cc: Sean Anderson > --- > drivers/clk/renesas/Kconfig | 6 + > drivers/clk/renesas/Makefile| 1 + > drivers/clk/renesas/r8a779h0-cpg-mssr.c | 294 > drivers/clk/renesas/rcar-gen3-cpg.h | 1 + > 4 files changed, 302 insertions(+) > create mode 100644 drivers/clk/renesas/r8a779h0-cpg-mssr.c How does this relate to the Linux kernel clk patch sent by Geert [1]? If this patch is based on that, then we should have a link to that patch in the commit message (since it hasn't appeared in a mainline kernel release yet). [1]: https://lore.kernel.org/all/0eb04b570d65d67de72069167e16d49e189dec54.1704726960.git.geert+rene...@glider.be/ Thanks, Paul OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 06/11] mtd: spi: renesas: Add R8A779H0 V4M support
On 21/01/2024 17:41, Marek Vasut wrote: > From: Hai Pham > > Support RPC SPI on R8A779H0 V4M SoC. > > Signed-off-by: Hai Pham > --- > Cc: Jagan Teki > Cc: Paul Barker > --- > drivers/spi/renesas_rpc_spi.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c > index 51c37d72eb6..3eb14061c81 100644 > --- a/drivers/spi/renesas_rpc_spi.c > +++ b/drivers/spi/renesas_rpc_spi.c > @@ -215,7 +215,8 @@ static u32 rpc_spi_get_strobe_delay(void) > if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && > rmobile_get_cpu_rev_integer() == 1) > return RPC_PHYCNT_STRTIM(6); > else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 || > - cpu_type == RMOBILE_CPU_TYPE_R8A779G0) > + cpu_type == RMOBILE_CPU_TYPE_R8A779G0 || > + cpu_type == RMOBILE_CPU_TYPE_R8A779H0) > return RPC_PHYCNT_STRTIM2(15); > else > #endif Reviewed-by: Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 07/11] ARM: renesas: Add R8A779H0 V4M Kconfig entry and PRR ID
On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham
>
> Add Kconfig entry and PRR ID to support R8A779H0 V4M SoC.
>
> Signed-off-by: Hai Pham
> ---
> Cc: Paul Barker
> ---
> arch/arm/mach-rmobile/Kconfig.rcar4 | 6 ++
> arch/arm/mach-rmobile/cpu_info.c | 1 +
> arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
> 3 files changed, 8 insertions(+)
>
> diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4
> b/arch/arm/mach-rmobile/Kconfig.rcar4
> index d4f93c89cac..3c8d683974c 100644
> --- a/arch/arm/mach-rmobile/Kconfig.rcar4
> +++ b/arch/arm/mach-rmobile/Kconfig.rcar4
> @@ -20,6 +20,12 @@ config R8A779G0
> imply CLK_R8A779G0
> imply PINCTRL_PFC_R8A779G0
>
> +config R8A779H0
> + bool "Renesas SoC R8A779H0"
> + select GICV3
> + imply CLK_R8A779H0
> + imply PINCTRL_PFC_R8A779H0
> +
> endmenu
>
> choice
> diff --git a/arch/arm/mach-rmobile/cpu_info.c
> b/arch/arm/mach-rmobile/cpu_info.c
> index 895c0f5336b..3d5d5ba79a9 100644
> --- a/arch/arm/mach-rmobile/cpu_info.c
> +++ b/arch/arm/mach-rmobile/cpu_info.c
> @@ -78,6 +78,7 @@ static const struct {
> { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" },
> { RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" },
> { RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" },
> + { RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" },
> { 0x0, "CPU" },
> };
>
> diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h
> b/arch/arm/mach-rmobile/include/mach/rmobile.h
> index 88b8b78671b..f0216210ba9 100644
> --- a/arch/arm/mach-rmobile/include/mach/rmobile.h
> +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
> @@ -43,6 +43,7 @@
> #define RMOBILE_CPU_TYPE_R8A779A00x59
> #define RMOBILE_CPU_TYPE_R8A779F00x5A
> #define RMOBILE_CPU_TYPE_R8A779G00x5C
> +#define RMOBILE_CPU_TYPE_R8A779H00x5D
> #define RMOBILE_CPU_TYPE_R9A07G044L 0x9A070440
>
> #ifndef __ASSEMBLY__
Reviewed-by: Paul Barker
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Re: [PATCH 09/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M DT extras
On 21/01/2024 17:41, Marek Vasut wrote:
> From: Hai Pham
>
> Add Renesas R8A779H0 V4M DT extras for U-Boot.
>
> Signed-off-by: Hai Pham
> ---
> Cc: Paul Barker
> ---
> arch/arm/dts/r8a779h0-u-boot.dtsi | 27 +++
> 1 file changed, 27 insertions(+)
> create mode 100644 arch/arm/dts/r8a779h0-u-boot.dtsi
>
> diff --git a/arch/arm/dts/r8a779h0-u-boot.dtsi
> b/arch/arm/dts/r8a779h0-u-boot.dtsi
> new file mode 100644
> index 000..b2f7e054eef
> --- /dev/null
> +++ b/arch/arm/dts/r8a779h0-u-boot.dtsi
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source extras for U-Boot on R-Car R8A779H0 SoC
> + *
> + * Copyright (C) 2023 Renesas Electronics Corp.
> + */
> +
> +#include "r8a779x-u-boot.dtsi"
> +/ {
> + soc {
> + rpc: spi@ee20 {
> + compatible = "renesas,r8a779h0-rpc-if",
> "renesas,rcar-gen4-rpc-if";
> + reg = <0 0xee20 0 0x200>, <0 0x0800 0
> 0x0400>;
> + interrupts = ;
> + clocks = < CPG_MOD 629>;
> + power-domains = < R8A779H0_PD_ALWAYS_ON>;
> + resets = < 629>;
> + bank-width = <2>;
> + num-cs = <1>;
> + status = "disabled";
> + };
Either the commit message or a comment should give some idea why this
node is in a -u-boot.dtsi file instead of the r8a779h0.dtsi file itself.
Thanks,
Paul
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Re: [PATCH 08/11] ARM: dts: renesas: Add Renesas R8A779H0 V4M SoC support
On 21/01/2024 17:41, Marek Vasut wrote: > From: Hai Pham > > Add initial support for the Renesas R8A779H0 (R-Car V4M) SoC. > > Signed-off-by: Hai Pham > --- > Cc: Paul Barker > --- > arch/arm/dts/r8a779h0.dtsi | 461 + > 1 file changed, 461 insertions(+) > create mode 100644 arch/arm/dts/r8a779h0.dtsi Is this a sync from the Linux kernel? If so we should say which commit the dtsi file is taken from. Thanks, Paul OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 10/11] ARM: dts: renesas: Add Renesas Gray Hawk boards support
On 21/01/2024 17:41, Marek Vasut wrote: > From: Hai Pham > > Initial support for the Renesas Gray Hawk CPU and BreakOut boards. > > Signed-off-by: Hai Pham > --- > Cc: Paul Barker > --- > arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi | 165 ++ > arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi | 15 ++ > arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi | 15 ++ > arch/arm/dts/r8a779h0-gray-hawk.dts | 25 +++ > 4 files changed, 220 insertions(+) > create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-cpu.dtsi > create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-csi-dsi.dtsi > create mode 100644 arch/arm/dts/r8a779h0-gray-hawk-ethernet.dtsi > create mode 100644 arch/arm/dts/r8a779h0-gray-hawk.dts Is this a sync from the Linux kernel? If so we should say which commit the dts/dtsi files are taken from. Thanks, Paul OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 11/11] ARM: renesas: Add Renesas R8A779H0 V4M Gray Hawk board code
On 21/01/2024 17:41, Marek Vasut wrote: > diff --git a/board/renesas/grayhawk/MAINTAINERS > b/board/renesas/grayhawk/MAINTAINERS > new file mode 100644 > index 000..b3532141ce7 > --- /dev/null > +++ b/board/renesas/grayhawk/MAINTAINERS > @@ -0,0 +1,7 @@ > +GRAYHAWK BOARD > +M: Marek Vasut > +S: Maintained > +F: arch/arm/dts/r8a779h0* > +F: board/renesas/grayhawk/ > +F: configs/r8a779h0_grayhawk_defconfig > +F: include/configs/grayhawk.h You could use the following here to catch everything with 'r8a779h0' or 'grayhawk' in the filename: N: r8a779h0 N: grayhawk Otherwise, LGTM. Reviewed-by: Paul Barker OpenPGP_0x27F4B3459F002257.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH 5/5] sysreset: Support reset via Renesas RAA215300 PMIC
On Sun, Nov 19, 2023 at 09:17:40PM +0100, Marek Vasut wrote:
> On 11/15/23 18:40, Paul Barker wrote:
> > This patch allows us to reset the RZ/G2L board via the RAA215300 PMIC.
> >
> > Note that the RAA215300 documentation names the available reset types
> > differently to u-boot:
> >
> >- A "warm" reset via the RAA215300 PMIC will fully reset the SoC
> > (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
> >
> >- A "cold" reset via the RAA215300 PMIC will cycle all power supply
> > rails, so this corresponds to SYSRESET_POWER.
> >
> > Signed-off-by: Paul Barker
> > ---
> > board/renesas/rzg2l/rzg2l.c | 8
> > configs/renesas_rzg2l_smarc_defconfig | 2 +
> > drivers/power/pmic/raa215300.c| 17
> > drivers/sysreset/Kconfig | 6 +++
> > drivers/sysreset/Makefile | 1 +
> > drivers/sysreset/sysreset_raa215300.c | 58 +++
> > 6 files changed, 84 insertions(+), 8 deletions(-)
> > create mode 100644 drivers/sysreset/sysreset_raa215300.c
> >
> > diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
> > index 73201a8c69e5..0f6d6e7f514f 100644
> > --- a/board/renesas/rzg2l/rzg2l.c
> > +++ b/board/renesas/rzg2l/rzg2l.c
> > @@ -56,11 +56,3 @@ int board_init(void)
> > {
> > return 0;
> > }
> > -
> > -void reset_cpu(void)
> > -{
> > - /*
> > -* TODO: Implement reset support once TrustedFirmware supports
> > -* the appropriate call.
> > -*/
> > -}
>
> Board change -- separate patch please.
Ok, this makes sense. I'll move this and the defconfig change into a
separate patch.
>
> > diff --git a/configs/renesas_rzg2l_smarc_defconfig
> > b/configs/renesas_rzg2l_smarc_defconfig
> > index b62eae4ee0a4..ba96e746df9e 100644
> > --- a/configs/renesas_rzg2l_smarc_defconfig
> > +++ b/configs/renesas_rzg2l_smarc_defconfig
> > @@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
> > CONFIG_DM_REGULATOR=y
> > CONFIG_DM_REGULATOR_FIXED=y
> > CONFIG_DM_REGULATOR_GPIO=y
> > +CONFIG_SYSRESET=y
> > +CONFIG_SYSRESET_RAA215300=y
> > diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
> > index 9c0b720994b2..7f68f95f25cf 100644
> > --- a/drivers/power/pmic/raa215300.c
> > +++ b/drivers/power/pmic/raa215300.c
> > @@ -27,9 +27,26 @@ static const struct udevice_id raa215300_ids[] = {
> > { /* sentinel */ }
> > };
> > +static int raa215300_bind(struct udevice *dev)
> > +{
> > + struct driver *drv;
> > +
> > + if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
> > + drv = lists_driver_lookup_name("raa215300_sysreset");
> > + if (!drv)
> > + return -ENOENT;
> > +
> > + return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
> > + NULL);
> > + }
> > +
> > + return 0;
> > +}
>
> Driver change should be squashed in 4/5.
Moving this to the previous patch doesn't make sense to me - the
sysreset driver needs to exist for this check to be meaningful.
Conversely, adding the sysreset driver first then the pmic driver
wouldn't make sense since the sysreset driver depends on the pmic
driver. This seemed the neatest way to do things to me.
Thanks,
Paul
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Re: [PATCH 3/5] i2c: rzg2l: Add I2C driver for RZ/G2L family
On Sun, Nov 19, 2023 at 09:15:36PM +0100, Marek Vasut wrote: > On 11/15/23 18:40, Paul Barker wrote: > > This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) > > SoC, also known as the RIIC module. > > > > This patch is based on both the u-boot driver in the Renesas RZ BSP > > 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.6 driver > > (commit ffc253263a13). > > > > Support for deblocking the I2C bus is included as this may be needed > > after triggering a reset via the Power Management IC (PMIC) over I2C > > (the PMIC asserts the reset line before the SoC completes the I2C write > > transaction with obvious bus locking effects). If the SDA line is > > observed to be low during initialisation, we automatically attempt to > > deblock. > > > > [1]: https://github.com/renesas-rz/renesas-u-boot-cip > > > > Signed-off-by: Paul Barker > > The driver seems very similar to drivers/i2c/rcar_iic.c , can there be some > code reuse ? My initial idea was to extend the R-Car iic driver but I quickly saw that would be very messy. All the registers and bits are in different places, the calculations are different (particularly in regard to setting bus speed) and the read/write process has more edge cases for the RZ/G2L. The bus recovery mechanism we use also doesn't exist on previous R-Car SoCs. The Linux drivers for these modules are also separate, see drivers/i2c/busses/i2c-sh_mobile.c (for R-Car and earlier SoCs) and drivers/i2c/busses/i2c-riic.c (for RZ/G2L) in the Linux kernel. Thanks, Paul signature.asc Description: PGP signature
Re: [PATCH v2] net: designware: Add bitbang feature for designware driver
On Fri, Nov 17, 2023 at 10:04:53AM +0800, Jim Liu wrote:
> Add bb_miiphy_bus function for designware bitbang feature.
>
> Signed-off-by: Jim Liu
> ---
> Changes for v2:
>- add bitbang delay dts read
>- modify printf to debug
> ---
> drivers/net/designware.c | 105 +++
> drivers/net/designware.h | 5 ++
> 2 files changed, 110 insertions(+)
>
> diff --git a/drivers/net/designware.c b/drivers/net/designware.c
> index a174344b3e..e86f96fc1a 100644
> --- a/drivers/net/designware.c
> +++ b/drivers/net/designware.c
> @@ -767,6 +767,31 @@ int designware_eth_probe(struct udevice *dev)
> priv->bus = miiphy_get_dev_by_name(dev->name);
> priv->dev = dev;
>
> +#if defined(CONFIG_BITBANGMII) && CONFIG_IS_ENABLED(DM_GPIO)
> + if (dev_read_bool(dev, "snps,bitbang-mii")) {
> + debug("\n%s: use bitbang mii..\n", dev->name);
> + ret = gpio_request_by_name(dev, "snps,mdc-gpio", 0,
> +>mdc_gpio, GPIOD_IS_OUT |
> GPIOD_IS_OUT_ACTIVE);
> + if (ret) {
> + printf("no mdc-gpio\n");
> + return ret;
> + }
> + ret = gpio_request_by_name(dev, "snps,mdio-gpio", 0,
> +>mdio_gpio, GPIOD_IS_OUT |
> GPIOD_IS_OUT_ACTIVE);
> + if (ret) {
> + printf("no mdio-gpio\n");
> + return ret;
> + }
> +
> + priv->bb_delay = dev_read_u32_default(dev,
> "snps,bitbang-delay", 1);
> +
> + bb_miiphy_buses[0].priv = priv;
> + sprintf(bb_miiphy_buses[0].name, dev->name);
If designware_eth_probe() is called for multiple Ethernet interfaces
then only the last interface to be probed will have a working MDIO bus.
We should either support multiple buses here or raise an error if there
is an attempt to probe a second interface.
(I spotted the same issue in the ravb driver while extending it to
support a board with two Ethernet interfaces)
Thanks,
Paul
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[PATCH 5/5] sysreset: Support reset via Renesas RAA215300 PMIC
This patch allows us to reset the RZ/G2L board via the RAA215300 PMIC.
Note that the RAA215300 documentation names the available reset types
differently to u-boot:
- A "warm" reset via the RAA215300 PMIC will fully reset the SoC
(CPU & GPIOs), so this corresponds to SYSRESET_COLD.
- A "cold" reset via the RAA215300 PMIC will cycle all power supply
rails, so this corresponds to SYSRESET_POWER.
Signed-off-by: Paul Barker
---
board/renesas/rzg2l/rzg2l.c | 8
configs/renesas_rzg2l_smarc_defconfig | 2 +
drivers/power/pmic/raa215300.c| 17
drivers/sysreset/Kconfig | 6 +++
drivers/sysreset/Makefile | 1 +
drivers/sysreset/sysreset_raa215300.c | 58 +++
6 files changed, 84 insertions(+), 8 deletions(-)
create mode 100644 drivers/sysreset/sysreset_raa215300.c
diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
index 73201a8c69e5..0f6d6e7f514f 100644
--- a/board/renesas/rzg2l/rzg2l.c
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -56,11 +56,3 @@ int board_init(void)
{
return 0;
}
-
-void reset_cpu(void)
-{
- /*
-* TODO: Implement reset support once TrustedFirmware supports
-* the appropriate call.
-*/
-}
diff --git a/configs/renesas_rzg2l_smarc_defconfig
b/configs/renesas_rzg2l_smarc_defconfig
index b62eae4ee0a4..ba96e746df9e 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -55,3 +55,5 @@ CONFIG_PMIC_RAA215300=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_RAA215300=y
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
index 9c0b720994b2..7f68f95f25cf 100644
--- a/drivers/power/pmic/raa215300.c
+++ b/drivers/power/pmic/raa215300.c
@@ -27,9 +27,26 @@ static const struct udevice_id raa215300_ids[] = {
{ /* sentinel */ }
};
+static int raa215300_bind(struct udevice *dev)
+{
+ struct driver *drv;
+
+ if (IS_ENABLED(CONFIG_SYSRESET_RAA215300)) {
+ drv = lists_driver_lookup_name("raa215300_sysreset");
+ if (!drv)
+ return -ENOENT;
+
+ return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev),
+ NULL);
+ }
+
+ return 0;
+}
+
U_BOOT_DRIVER(raa215300_pmic) = {
.name = "raa215300_pmic",
.id = UCLASS_PMIC,
.of_match = raa215300_ids,
+ .bind = raa215300_bind,
.ops = _ops,
};
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index 0e52f996283c..49c0787b26d8 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -229,6 +229,12 @@ config SYSRESET_MPC83XX
help
Reboot support for NXP MPC83xx SoCs.
+config SYSRESET_RAA215300
+ bool "Support sysreset via Renesas RAA215300 PMIC"
+ depends on PMIC_RAA215300
+ help
+ Add support for the system reboot via the Renesas RAA215300 PMIC.
+
endif
endmenu
diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index c9f1c625aebb..e0e732205df3 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -27,4 +27,5 @@ obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_AT91) += sysreset_at91.o
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
+obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
diff --git a/drivers/sysreset/sysreset_raa215300.c
b/drivers/sysreset/sysreset_raa215300.c
new file mode 100644
index ..32dfcb0aec84
--- /dev/null
+++ b/drivers/sysreset/sysreset_raa215300.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+
+#define RAA215300_REG_SWRESET 0x6D
+#define RAA215300_COLD_RESET BIT(0)
+#define RAA215300_WARM_RESET BIT(1)
+
+static int raa215300_sysreset_request(struct udevice *dev, enum sysreset_t
type)
+{
+ struct udevice *pmic = dev_get_parent(dev);
+ int ret;
+ u8 val;
+
+ /*
+* The RAA215300 documentation names the available reset types
+* differently to u-boot:
+*
+* - A "warm" reset via the RAA215300 PMIC will fully reset the SoC
+* (CPU & GPIOs), so this corresponds to SYSRESET_COLD.
+*
+* - A "cold" reset via the RAA215300 PMIC will cycle all power supply
+* rails, so this corresponds to SYSRESET_POWER.
+*/
+ switch (type) {
+ case SYSRESET_COLD:
+ val = RAA215300_WARM_RESET;
+ break;
+
+ case SYSRESET_POWER:
+ val = RAA215300_COLD_RESET;
+ break;
+
[PATCH 4/5] pmic: Add Renesas RAA215300 PMIC driver
The RZ/G2L SMARC module is powered via a Renesas RAA215300 PMIC which
provides several voltage converters, a real time clock (RTC) and reset
control. A basic driver is implemented for this device so that we can
read, write and dump the PMIC registers.
Additional features of this PMIC (such as reset control) may be
supported by future patches.
Signed-off-by: Paul Barker
---
configs/renesas_rzg2l_smarc_defconfig | 3 +++
drivers/power/pmic/Kconfig| 9 +++
drivers/power/pmic/Makefile | 1 +
drivers/power/pmic/raa215300.c| 35 +++
4 files changed, 48 insertions(+)
create mode 100644 drivers/power/pmic/raa215300.c
diff --git a/configs/renesas_rzg2l_smarc_defconfig
b/configs/renesas_rzg2l_smarc_defconfig
index acf9e6a9f4f5..b62eae4ee0a4 100644
--- a/configs/renesas_rzg2l_smarc_defconfig
+++ b/configs/renesas_rzg2l_smarc_defconfig
@@ -27,6 +27,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+CONFIG_CMD_PMIC=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
@@ -49,6 +50,8 @@ CONFIG_DM_I2C=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RAA215300=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 454a6e0cf87a..9b61b18e11fd 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -404,6 +404,15 @@ config PMIC_TPS65219
help
The TPS65219 is a PMIC containing a bunch of SMPS & LDOs.
This driver binds the pmic children.
+
+config PMIC_RAA215300
+ bool "Renesas RAA215300 PMIC driver"
+ depends on DM_PMIC
+ help
+ The Renesas RAA215300 PMIC driver includes RTC support, system reset
+ support and several voltage regulators. For now, this driver simply
+ allows register access and will bind the sysreset driver
+ (CONFIG_SYSRESET_RAA215300) if it is enabled.
endif
config PMIC_TPS65217
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index 55ee614364be..a2d59deeed8b 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o
obj-$(CONFIG_PMIC_TPS65217) += pmic_tps65217.o
obj-$(CONFIG_PMIC_TPS65219) += tps65219.o
obj-$(CONFIG_PMIC_TPS65941) += tps65941.o
+obj-$(CONFIG_PMIC_RAA215300) += raa215300.o
obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
ifeq ($(CONFIG_$(SPL_)POWER_LEGACY),y)
diff --git a/drivers/power/pmic/raa215300.c b/drivers/power/pmic/raa215300.c
new file mode 100644
index ..9c0b720994b2
--- /dev/null
+++ b/drivers/power/pmic/raa215300.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define RAA215300_REG_COUNT 0x80
+
+static int raa215300_reg_count(struct udevice *dev)
+{
+ return RAA215300_REG_COUNT;
+}
+
+static struct dm_pmic_ops raa215300_ops = {
+ .reg_count = raa215300_reg_count,
+ .read = dm_i2c_read,
+ .write = dm_i2c_write,
+};
+
+static const struct udevice_id raa215300_ids[] = {
+ { .compatible = "renesas,raa215300" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(raa215300_pmic) = {
+ .name = "raa215300_pmic",
+ .id = UCLASS_PMIC,
+ .of_match = raa215300_ids,
+ .ops = _ops,
+};
--
2.39.2
[PATCH 3/5] i2c: rzg2l: Add I2C driver for RZ/G2L family
This driver supports the I2C module on the Renesas RZ/G2L (R9A07G044) SoC, also known as the RIIC module. This patch is based on both the u-boot driver in the Renesas RZ BSP 3.0.5 release [1] (commit 7fcc1fdc2534), and the Linux v6.6 driver (commit ffc253263a13). Support for deblocking the I2C bus is included as this may be needed after triggering a reset via the Power Management IC (PMIC) over I2C (the PMIC asserts the reset line before the SoC completes the I2C write transaction with obvious bus locking effects). If the SDA line is observed to be low during initialisation, we automatically attempt to deblock. [1]: https://github.com/renesas-rz/renesas-u-boot-cip Signed-off-by: Paul Barker --- arch/arm/mach-rmobile/Kconfig | 1 + configs/renesas_rzg2l_smarc_defconfig | 2 + drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/rz_riic.c | 626 ++ 5 files changed, 637 insertions(+) create mode 100644 drivers/i2c/rz_riic.c diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 2bb96749fc0d..38ede6e0b5b5 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -78,6 +78,7 @@ config RZG2L imply RENESAS_SDHI imply RZG2L_GPIO imply SCIF_CONSOLE + imply SYS_I2C_RZ_RIIC imply SYS_MALLOC_F help Enable support for the Renesas RZ/G2L family of SoCs. Currently diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index e17d22695787..acf9e6a9f4f5 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=2068 CONFIG_CMD_CLK=y CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_EXT2=y @@ -44,6 +45,7 @@ CONFIG_CLK=y CONFIG_CLK_RENESAS=y # CONFIG_CLK_RCAR_GEN3 is not set CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 4f42200f3923..d2a3a13493aa 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -524,6 +524,13 @@ config SYS_I2C_ROCKCHIP have several I2C ports and all are provided, controlled by the device tree. +config SYS_I2C_RZ_RIIC + bool "Renesas RZ/G2L RIIC driver" + depends on RZG2L && DM_I2C + help + Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC + family. + config SYS_I2C_SANDBOX bool "Sandbox I2C driver" depends on SANDBOX && DM_I2C diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index a96a8c7e955e..692f63bafd02 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_SYS_I2C_QUP) += qup_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o +obj-$(CONFIG_SYS_I2C_RZ_RIIC) += rz_riic.o obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o diff --git a/drivers/i2c/rz_riic.c b/drivers/i2c/rz_riic.c new file mode 100644 index ..734ed084f666 --- /dev/null +++ b/drivers/i2c/rz_riic.c @@ -0,0 +1,626 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * RZ/G2L I2C (RIIC) driver + * + * Copyright (C) 2021-2023 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RIIC_ICCR1 0x00 +#define RIIC_ICCR2 0x04 +#define RIIC_ICMR1 0x08 +#define RIIC_ICMR2 0x0c +#define RIIC_ICMR3 0x10 +#define RIIC_ICFER 0x14 +#define RIIC_ICSER 0x18 +#define RIIC_ICIER 0x1c +#define RIIC_ICSR1 0x20 +#define RIIC_ICSR2 0x24 +#define RIIC_ICSAR00x28 +#define RIIC_ICBRL 0x34 +#define RIIC_ICBRH 0x38 +#define RIIC_ICDRT 0x3c +#define RIIC_ICDRR 0x40 + +/* ICCR1 */ +#define ICCR1_ICE BIT(7) +#define ICCR1_IICRST BIT(6) +#define ICCR1_CLO BIT(5) +#define ICCR1_SOWP BIT(4) +#define ICCR1_SCLO BIT(3) +#define ICCR1_SDAO BIT(2) +#define ICCR1_SCLI BIT(1) +#define ICCR1_SDAI BIT(0) + +/* ICCR2 */ +#define ICCR2_BBSY BIT(7) +#define ICCR2_MST BIT(6) +#define ICCR2_TRS BIT(5) +#define ICCR2_SP BIT(3) +#define ICCR2_RS BIT(2) +#define ICCR2_ST BIT(1) + +/* ICMR1 */ +#define ICMR1_MTWP BIT(7) +#define ICMR1_CKS_MASK GENMASK(6, 4) +#define ICMR1_BCWP BIT(3) +#define ICMR1_BC_MASK GENMASK(2, 0) + +#define ICMR1_CKS(x) (((x) << 4) & ICMR1_CKS_MASK) +#define ICMR1_BC(x)((x) & ICMR1_BC_MASK) + +/* ICMR2 */ +#define ICMR2_DLCS BIT(7) +#define ICMR2_SDDL_MASKGENMASK(6, 4) +#define ICMR2_TMOH BIT(2) +#define I
[PATCH 2/5] arm: dts: rzg2l: Sync with Linux v6.6
Pull in the recent changes to the RZ/G2L device tree and related dtsi
files so that we're aligned with Linux v6.6 (commit ffc253263a13).
Signed-off-by: Paul Barker
---
arch/arm/dts/r9a07g044.dtsi | 16
arch/arm/dts/r9a07g044l2-smarc.dts| 21 +
arch/arm/dts/rz-smarc-common.dtsi | 4 ++--
arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20
arch/arm/dts/rzg2l-smarc-som.dtsi | 22 --
arch/arm/dts/rzg2l-smarc.dtsi | 23 ---
6 files changed, 91 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
index 232910e07444..66f68fc2b241 100644
--- a/arch/arm/dts/r9a07g044.dtsi
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -223,20 +223,20 @@
,
;
interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
- "tgiv0", "tgie0", "tgif0",
- "tgia1", "tgib1", "tgiv1", "tgiu1",
- "tgia2", "tgib2", "tgiv2", "tgiu2",
+ "tciv0", "tgie0", "tgif0",
+ "tgia1", "tgib1", "tciv1", "tciu1",
+ "tgia2", "tgib2", "tciv2", "tciu2",
"tgia3", "tgib3", "tgic3", "tgid3",
- "tgiv3",
+ "tciv3",
"tgia4", "tgib4", "tgic4", "tgid4",
- "tgiv4",
+ "tciv4",
"tgiu5", "tgiv5", "tgiw5",
"tgia6", "tgib6", "tgic6", "tgid6",
- "tgiv6",
+ "tciv6",
"tgia7", "tgib7", "tgic7", "tgid7",
- "tgiv7",
+ "tciv7",
"tgia8", "tgib8", "tgic8", "tgid8",
- "tgiv8", "tgiu8";
+ "tciv8", "tciu8";
clocks = < CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
power-domains = <>;
resets = < R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/arch/arm/dts/r9a07g044l2-smarc.dts
b/arch/arm/dts/r9a07g044l2-smarc.dts
index bc2af6c92ccd..568d49cfe44a 100644
--- a/arch/arm/dts/r9a07g044l2-smarc.dts
+++ b/arch/arm/dts/r9a07g044l2-smarc.dts
@@ -6,6 +6,27 @@
*/
/dts-v1/;
+
+/* Enable SCIF2 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0 1
+
+/*
+ * To enable MTU3a PWM on PMOD0,
+ * Disable PMOD1_SER0 by setting "#define PMOD1_SER0 0" above and
+ * enable PMOD_MTU3 by setting "#define PMOD_MTU3 1" below.
+ */
+#define PMOD_MTU3 0
+
+#if (PMOD_MTU3 && PMOD1_SER0)
+#error "Cannot set as PMOD_MTU3 and PMOD1_SER0 are mutually exclusive "
+#endif
+
+#define MTU3_COUNTER_Z_PHASE_SIGNAL0
+
+#if (!PMOD_MTU3 && MTU3_COUNTER_Z_PHASE_SIGNAL)
+#error "Cannot set 1 to MTU3_COUNTER_Z_PHASE_SIGNAL as PMOD_MTU3=0"
+#endif
+
#include "r9a07g044l2.dtsi"
#include "rzg2l-smarc-som.dtsi"
#include "rzg2l-smarc-pinfunction.dtsi"
diff --git a/arch/arm/dts/rz-smarc-common.dtsi
b/arch/arm/dts/rz-smarc-common.dtsi
index 3962d47b3e59..a7594ba3a998 100644
--- a/arch/arm/dts/rz-smarc-common.dtsi
+++ b/arch/arm/dts/rz-smarc-common.dtsi
@@ -78,11 +78,11 @@
};
};
-_clk1{
+_clk1 {
clock-frequency = <11289600>;
};
-_clk2{
+_clk2 {
clock-frequency = <12288000>;
};
diff --git a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
index 9085d8c76ce1..18c526c7a4cf 100644
--- a/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
+++ b/arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
@@ -53,6 +53,26 @@
; /* SCL */
};
+ mtu3_pins: mtu3 {
+ mtu3-ext-clk-input-pin {
+ pinmu
[PATCH 1/5] clk: renesas: Confirm all clock & reset changes on RZ/G2L
When enabling/disabling a clock or reset signal, confirm that the change
has completed before returning from the function. A somewhat arbitrary
100ms timeout is defined to ensure that the system doesn't lock up in
the case of an error.
Since we need to dynamically determine if we're waiting for a 0 bit or a
1 bit, it's easier to use wait_for_bit_32() than readl_poll_timeout().
This change is needed for reliable initialization of the I2C driver
which is added in a following patch.
Fixes: 1918ff5c95be ("clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver")
Signed-off-by: Paul Barker
---
drivers/clk/renesas/rzg2l-cpg.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index e54508c35ce2..dba009997a81 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -23,10 +23,18 @@
#include
#include
#include
+#include
#include "rzg2l-cpg.h"
+/*
+ * Monitor registers for both clock and reset signals are offset by 0x180 from
+ * the corresponding control registers.
+ */
#define CLK_MON_R(reg) (0x180 + (reg))
+#define RST_MON_R(reg) (0x180 + (reg))
+
+#define CPG_TIMEOUT_MSEC 100
static ulong rzg2l_cpg_clk_get_rate_by_id(struct udevice *dev, unsigned int
id);
static ulong rzg2l_cpg_clk_get_rate_by_name(struct udevice *dev, const char
*name);
@@ -83,9 +91,9 @@ static int rzg2l_cpg_clk_set(struct clk *clk, bool enable)
value |= BIT(mod_clk->bit);
writel(value, data->base + mod_clk->off);
- if (enable && readl_poll_timeout(data->base + CLK_MON_R(mod_clk->off),
-value, (value & BIT(mod_clk->bit)),
-10)) {
+ if (enable && wait_for_bit_32(data->base + CLK_MON_R(mod_clk->off),
+ BIT(mod_clk->bit), enable,
+ CPG_TIMEOUT_MSEC, false)) {
dev_err(clk->dev, "Timeout\n");
return -ETIMEDOUT;
}
@@ -420,7 +428,8 @@ static int rzg2l_cpg_rst_set(struct reset_ctl *reset_ctl,
bool asserted)
value |= BIT(rst->bit);
writel(value, data->base + rst->off);
- return 0;
+ return wait_for_bit_32(data->base + RST_MON_R(rst->off), BIT(rst->bit),
+ asserted, CPG_TIMEOUT_MSEC, false);
}
static int rzg2l_cpg_rst_assert(struct reset_ctl *reset_ctl)
--
2.39.2
[PATCH 0/5] Add i2c and reset support for Renesas RZ/G2L
This patch series extends the support for the Renesas RZ/G2L SMARC EVK board (based on the R9A07G044L2 SoC) to include the following new features: * I2C bus support, including automatic deblocking if SDA is stuck low due to another device on the board. * Basic PMIC support, with the ability to read, write & dump PMIC registers. * Support for requesting system reset (SYSRESET_COLD or SYSRESET_POWER) via the PMIC. Along the way we fix the CPG driver to confirm all clock & reset changes before returning, and update the device tree to align with Linux 6.6. This series has been tested on RZ/G2L hardware, and the full u-boot GitLab CI pipeline has been executed in our internal GitLab instance. Paul Barker (5): clk: renesas: Confirm all clock & reset changes on RZ/G2L arm: dts: rzg2l: Sync with Linux v6.6 i2c: rzg2l: Add I2C driver for RZ/G2L family pmic: Add Renesas RAA215300 PMIC driver sysreset: Support reset via Renesas RAA215300 PMIC arch/arm/dts/r9a07g044.dtsi | 16 +- arch/arm/dts/r9a07g044l2-smarc.dts| 21 + arch/arm/dts/rz-smarc-common.dtsi | 4 +- arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 20 + arch/arm/dts/rzg2l-smarc-som.dtsi | 22 +- arch/arm/dts/rzg2l-smarc.dtsi | 23 +- arch/arm/mach-rmobile/Kconfig | 1 + board/renesas/rzg2l/rzg2l.c | 8 - configs/renesas_rzg2l_smarc_defconfig | 7 + drivers/clk/renesas/rzg2l-cpg.c | 17 +- drivers/i2c/Kconfig | 7 + drivers/i2c/Makefile | 1 + drivers/i2c/rz_riic.c | 626 ++ drivers/power/pmic/Kconfig| 9 + drivers/power/pmic/Makefile | 1 + drivers/power/pmic/raa215300.c| 52 ++ drivers/sysreset/Kconfig | 6 + drivers/sysreset/Makefile | 1 + drivers/sysreset/sysreset_raa215300.c | 58 ++ 19 files changed, 873 insertions(+), 27 deletions(-) create mode 100644 drivers/i2c/rz_riic.c create mode 100644 drivers/power/pmic/raa215300.c create mode 100644 drivers/sysreset/sysreset_raa215300.c base-commit: 92b27528d777ce85362af45e7d2974a6c856219b -- 2.39.2
[PATCH] sysreset: Fix unsupported request return values
The description of the sysreset request method in says that
the return value should be -EPROTONOSUPPORT if the requested reset type
is not supported by this device.
Signed-off-by: Paul Barker
---
drivers/sysreset/poweroff_gpio.c | 2 +-
drivers/sysreset/sysreset_psci.c | 2 +-
drivers/sysreset/sysreset_sandbox.c | 4 ++--
drivers/sysreset/sysreset_watchdog.c | 2 +-
drivers/sysreset/sysreset_x86.c | 2 +-
test/dm/sysreset.c | 6 +++---
6 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/sysreset/poweroff_gpio.c b/drivers/sysreset/poweroff_gpio.c
index a5c24fd85bca..ad04e4b1a85e 100644
--- a/drivers/sysreset/poweroff_gpio.c
+++ b/drivers/sysreset/poweroff_gpio.c
@@ -33,7 +33,7 @@ static int poweroff_gpio_request(struct udevice *dev, enum
sysreset_t type)
int r;
if (type != SYSRESET_POWER_OFF)
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
debug("GPIO poweroff\n");
diff --git a/drivers/sysreset/sysreset_psci.c b/drivers/sysreset/sysreset_psci.c
index a8a41528a849..aa09d0b88271 100644
--- a/drivers/sysreset/sysreset_psci.c
+++ b/drivers/sysreset/sysreset_psci.c
@@ -25,7 +25,7 @@ static int psci_sysreset_request(struct udevice *dev, enum
sysreset_t type)
psci_sys_poweroff();
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
diff --git a/drivers/sysreset/sysreset_sandbox.c
b/drivers/sysreset/sysreset_sandbox.c
index f485a1352993..c12eda81d03e 100644
--- a/drivers/sysreset/sysreset_sandbox.c
+++ b/drivers/sysreset/sysreset_sandbox.c
@@ -21,7 +21,7 @@ static int sandbox_warm_sysreset_request(struct udevice *dev,
state->last_sysreset = type;
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
@@ -70,7 +70,7 @@ static int sandbox_sysreset_request(struct udevice *dev, enum
sysreset_t type)
return -EACCES;
sandbox_exit();
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
if (!state->sysreset_allowed[type])
return -EACCES;
diff --git a/drivers/sysreset/sysreset_watchdog.c
b/drivers/sysreset/sysreset_watchdog.c
index ceada2e47b54..6db5aa75b541 100644
--- a/drivers/sysreset/sysreset_watchdog.c
+++ b/drivers/sysreset/sysreset_watchdog.c
@@ -29,7 +29,7 @@ static int wdt_reboot_request(struct udevice *dev, enum
sysreset_t type)
return ret;
break;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
return -EINPROGRESS;
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index 4936fdb76c72..dc772b5ff9e3 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -87,7 +87,7 @@ static int x86_sysreset_request(struct udevice *dev, enum
sysreset_t type)
return ret;
return -EINPROGRESS;
default:
- return -ENOSYS;
+ return -EPROTONOSUPPORT;
}
outb(value, IO_PORT_RESET);
diff --git a/test/dm/sysreset.c b/test/dm/sysreset.c
index 691683c56740..5aa69e046186 100644
--- a/test/dm/sysreset.c
+++ b/test/dm/sysreset.c
@@ -27,8 +27,8 @@ static int dm_test_sysreset_base(struct unit_test_state *uts)
/* Device 1 is the warm sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 1, ));
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_WARM));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_COLD));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_POWER));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_COLD));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_POWER));
state->sysreset_allowed[SYSRESET_WARM] = true;
ut_asserteq(-EINPROGRESS, sysreset_request(dev, SYSRESET_WARM));
@@ -36,7 +36,7 @@ static int dm_test_sysreset_base(struct unit_test_state *uts)
/* Device 2 is the cold sysreset device */
ut_assertok(uclass_get_device(UCLASS_SYSRESET, 2, ));
- ut_asserteq(-ENOSYS, sysreset_request(dev, SYSRESET_WARM));
+ ut_asserteq(-EPROTONOSUPPORT, sysreset_request(dev, SYSRESET_WARM));
state->sysreset_allowed[SYSRESET_COLD] = false;
ut_asserteq(-EACCES, sysreset_request(dev, SYSRESET_COLD));
state->sysreset_allowed[SYSRESET_COLD] = true;
base-commit: e17d174773e9ba9447596708e702b7382e47a6cf
--
2.39.2
Re: [PATCH] mmc: renesas-sdhi: Disable clock after tuning reset when possible
On Sun, Nov 05, 2023 at 11:42:45PM +0100, Marek Vasut wrote:
> Currently the renesas_sdhi_reset_tuning() unconditionally leaves SDHI
> clock enabled after the tuning reset. This is not always necessary.
>
> After the driver performed tuning reset at the end of probe function,
> or in the unlikely case that tuning failed during regular operation,
> the SDHI clock can be disabled after the tuning reset. The following
> set_ios call would reconfigure the clock as needed.
>
> In case of regular set_ios call which requires a tuning reset, keep
> the clock enabled or disabled according to the mmc->clk_disable state.
>
> With this in place, the controllers which have not been accessed via
> block subsystem after boot are left in quiescent state. However, if an
> MMC device is used e.g. for environment storage, that controller would
> be accessed during the environment load and left active, including its
> clock which would still be generated. This is due to the design of the
> MMC subsystem, which does not deinit a controller after it was started
> once, the controller is only deinited in case of mmc rescan, or before
> OS boot.
>
> Signed-off-by: Marek Vasut
> ---
> Note: To address the part where MMC device has been inited once and
> is never deinited until rescan or OS boot, it would likely be
> necessary to implement something like runtime PM, possibly
> based on the cyclic framework. Basically, keep track of when
> the MMC was accessed last, and if certain time elapsed, deinit
> the MMC. This could also be used to handle card detect polling
> at the same time.
> ---
> Cc: Jaehoon Chung
> Cc: Nobuhiro Iwamatsu
> Cc: Paul Barker
> Cc: Peng Fan
> ---
> drivers/mmc/renesas-sdhi.c | 14 ++
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
> index 8cd501c5f7c..97aaf1e4ec3 100644
> --- a/drivers/mmc/renesas-sdhi.c
> +++ b/drivers/mmc/renesas-sdhi.c
> @@ -318,7 +318,7 @@ static unsigned int renesas_sdhi_init_tuning(struct
> tmio_sd_priv *priv)
> RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
> }
>
> -static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
> +static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv, bool
> clk_disable)
> {
> u32 reg;
>
> @@ -350,6 +350,12 @@ static void renesas_sdhi_reset_tuning(struct
> tmio_sd_priv *priv)
> reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
> reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
> tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
> +
> + if (clk_disable) {
> + reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
> + reg &= ~TMIO_SD_CLKCTL_SCLKEN;
> + tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
> + }
> }
>
> static int renesas_sdhi_hs400(struct udevice *dev)
> @@ -629,7 +635,7 @@ int renesas_sdhi_execute_tuning(struct udevice *dev, uint
> opcode)
> out:
> if (ret < 0) {
> dev_warn(dev, "Tuning procedure failed\n");
> - renesas_sdhi_reset_tuning(priv);
> + renesas_sdhi_reset_tuning(priv, true);
> }
>
> return ret;
> @@ -668,7 +674,7 @@ static int renesas_sdhi_set_ios(struct udevice *dev)
> (mmc->selected_mode != UHS_SDR104) &&
> (mmc->selected_mode != MMC_HS_200) &&
> (mmc->selected_mode != MMC_HS_400)) {
> - renesas_sdhi_reset_tuning(priv);
> + renesas_sdhi_reset_tuning(priv, mmc->clk_disable);
> }
> #endif
>
> @@ -1095,7 +1101,7 @@ static int renesas_sdhi_probe(struct udevice *dev)
> CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
> CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
> if (priv->caps & TMIO_SD_CAP_RCAR_UHS)
> - renesas_sdhi_reset_tuning(priv);
> + renesas_sdhi_reset_tuning(priv, true);
> #endif
> return 0;
Reviewed-by: Paul Barker
Tested-by: Paul Barker
(on RZ/G2L SMARC EVK)
Thanks,
Paul
signature.asc
Description: PGP signature
Re: [PATCH 2/8] arm: mach-rmobile: Drop
On Thu, Nov 02, 2023 at 07:54:37AM +, Biju Das wrote: > Hi Paul, > > Thanks for the patch. > > > Subject: [PATCH 2/8] arm: mach-rmobile: Drop > > > > For most source files we can just drop . We need to add an > > include for in a couple of places. Also sort the include > > list in memmap-gen3.c while we're here. > > Why only sorting memmap-gen3.c? why not sorting all the files touching here? That was the only file where I needed to add a new include and it wasn't already sorted. Thanks, Paul signature.asc Description: PGP signature
[PATCH 8/8] board: rzg2l: Drop
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker --- board/renesas/rzg2l/rzg2l.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c index 755747e665cb..73201a8c69e5 100644 --- a/board/renesas/rzg2l/rzg2l.c +++ b/board/renesas/rzg2l/rzg2l.c @@ -4,7 +4,6 @@ * Copyright (C) 2023 Renesas Electronics Corporation */ -#include #include #include -- 2.39.2
[PATCH 7/8] clk: rzg2l: Drop
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker --- drivers/clk/renesas/r9a07g044-cpg.c | 1 - drivers/clk/renesas/rzg2l-cpg.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c index 2336028a7367..c8baad1a6c8d 100644 --- a/drivers/clk/renesas/r9a07g044-cpg.c +++ b/drivers/clk/renesas/r9a07g044-cpg.c @@ -5,7 +5,6 @@ * Copyright (C) 2021-2023 Renesas Electronics Corp. */ -#include #include #include #include diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index 3295ebb90ba2..e54508c35ce2 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -11,7 +11,6 @@ * Copyright (C) 2015 Renesas Electronics Corp. */ -#include #include #include #include -- 2.39.2
[PATCH 6/8] gpio: rzg2l: Drop
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker --- drivers/gpio/rzg2l-gpio.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpio/rzg2l-gpio.c b/drivers/gpio/rzg2l-gpio.c index 7c908d05475a..2477af7874b8 100644 --- a/drivers/gpio/rzg2l-gpio.c +++ b/drivers/gpio/rzg2l-gpio.c @@ -5,7 +5,6 @@ * Copyright (C) 2021-2023 Renesas Electronics Corp. */ -#include #include #include #include -- 2.39.2
[PATCH 5/8] mmc: renesas-sdhi: Drop
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker --- drivers/mmc/renesas-sdhi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index 865efdd32184..8cd501c5f7c7 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -3,7 +3,6 @@ * Copyright (C) 2018 Marek Vasut */ -#include #include #include #include -- 2.39.2
[PATCH 4/8] pinctrl: rzg2l: Drop
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker --- drivers/pinctrl/renesas/rzg2l-pfc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c b/drivers/pinctrl/renesas/rzg2l-pfc.c index 7b045f75d3f9..e88ec1c18373 100644 --- a/drivers/pinctrl/renesas/rzg2l-pfc.c +++ b/drivers/pinctrl/renesas/rzg2l-pfc.c @@ -5,7 +5,6 @@ * Copyright (C) 2021-2023 Renesas Electronics Corp. */ -#include #include #include #include -- 2.39.2
[PATCH 3/8] serial: sh: Drop
In line with changes elsewhere, drop inclusion of the common header. Signed-off-by: Paul Barker --- drivers/serial/serial_sh.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index c034ab54e152..e4cc4ee42603 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -6,7 +6,6 @@ * Copyright (C) 2002 - 2008 Paul Mundt */ -#include #include #include #include -- 2.39.2
[PATCH 2/8] arm: mach-rmobile: Drop
For most source files we can just drop . We need to add an include for in a couple of places. Also sort the include list in memmap-gen3.c while we're here. Signed-off-by: Paul Barker --- arch/arm/mach-rmobile/board.c| 2 +- arch/arm/mach-rmobile/cpu_info-r8a7740.c | 2 +- arch/arm/mach-rmobile/cpu_info-rcar.c| 2 +- arch/arm/mach-rmobile/cpu_info-rzg.c | 2 +- arch/arm/mach-rmobile/cpu_info-rzg2l.c | 1 - arch/arm/mach-rmobile/cpu_info.c | 2 +- arch/arm/mach-rmobile/emac.c | 1 - arch/arm/mach-rmobile/memmap-gen3.c | 4 ++-- arch/arm/mach-rmobile/memmap-rzg2l.c | 2 +- arch/arm/mach-rmobile/pfc-r8a7740.c | 2 +- arch/arm/mach-rmobile/psci-r8a779a0.c| 1 - 11 files changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-rmobile/board.c index a10371f74e0c..79c7e02671f2 100644 --- a/arch/arm/mach-rmobile/board.c +++ b/arch/arm/mach-rmobile/board.c @@ -3,7 +3,7 @@ * (C) Copyright 2012 Nobuhiro Iwamatsu * (C) Copyright 2012 Renesas Solutions Corp. */ -#include + #include #include diff --git a/arch/arm/mach-rmobile/cpu_info-r8a7740.c b/arch/arm/mach-rmobile/cpu_info-r8a7740.c index dcbe25f37ab9..5a94235c4b9e 100644 --- a/arch/arm/mach-rmobile/cpu_info-r8a7740.c +++ b/arch/arm/mach-rmobile/cpu_info-r8a7740.c @@ -3,7 +3,7 @@ * (C) Copyright 2012 Nobuhiro Iwamatsu * (C) Copyright 2012 Renesas Solutions Corp. */ -#include + #include u32 rmobile_get_cpu_type(void) diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c index 8fc4cd7f9de8..b9d8b5e57b5a 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-rmobile/cpu_info-rcar.c @@ -4,7 +4,7 @@ * * Copyright (C) 2013,2014 Renesas Electronics Corporation */ -#include + #include #define PRR_MASK 0x7fff diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c b/arch/arm/mach-rmobile/cpu_info-rzg.c index 1c18fd06f0b6..4ade4bc02198 100644 --- a/arch/arm/mach-rmobile/cpu_info-rzg.c +++ b/arch/arm/mach-rmobile/cpu_info-rzg.c @@ -3,7 +3,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation * */ -#include + #include /* If the firmware passed a device tree, use it for soc identification. */ diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-rmobile/cpu_info-rzg2l.c index de4892ee901e..f69649dc7eaf 100644 --- a/arch/arm/mach-rmobile/cpu_info-rzg2l.c +++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c @@ -4,7 +4,6 @@ * */ -#include #include #include diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 6804b1da2cda..895c0f5336b6 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -3,7 +3,7 @@ * (C) Copyright 2012 Nobuhiro Iwamatsu * (C) Copyright 2012-2021 Renesas Solutions Corp. */ -#include + #include #include #include diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-rmobile/emac.c index cb9bce0cf23b..95651626da4a 100644 --- a/arch/arm/mach-rmobile/emac.c +++ b/arch/arm/mach-rmobile/emac.c @@ -6,7 +6,6 @@ * Copyright (C) 2012 Nobuhiro Iwamatsu */ -#include #include #include #include diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-rmobile/memmap-gen3.c index a68eb806b353..4dff9e07629d 100644 --- a/arch/arm/mach-rmobile/memmap-gen3.c +++ b/arch/arm/mach-rmobile/memmap-gen3.c @@ -5,10 +5,10 @@ * Copyright (C) 2017 Marek Vasut */ -#include -#include #include #include +#include +#include #define GEN3_NR_REGIONS 16 diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c b/arch/arm/mach-rmobile/memmap-rzg2l.c index a08d0ea08fc0..9934a775220b 100644 --- a/arch/arm/mach-rmobile/memmap-rzg2l.c +++ b/arch/arm/mach-rmobile/memmap-rzg2l.c @@ -6,9 +6,9 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ -#include #include #include +#include #include #define RZG2L_NR_REGIONS 16 diff --git a/arch/arm/mach-rmobile/pfc-r8a7740.c b/arch/arm/mach-rmobile/pfc-r8a7740.c index 5d42a68266b1..4f4847699b07 100644 --- a/arch/arm/mach-rmobile/pfc-r8a7740.c +++ b/arch/arm/mach-rmobile/pfc-r8a7740.c @@ -18,7 +18,7 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include + #include #include #include diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-rmobile/psci-r8a779a0.c index 6a85eb22cac2..b6c49e731f9d 100644 --- a/arch/arm/mach-rmobile/psci-r8a779a0.c +++ b/arch/arm/mach-rmobile/psci-r8a779a0.c @@ -6,7 +6,6 @@ * */ -#include #include #include #include -- 2.39.2
[PATCH 1/8] arm: armv8: mmu: Prepare for common.h removal
If won't be included before , we need to
ensure that we have the required type definitions.
Signed-off-by: Paul Barker
---
arch/arm/include/asm/armv8/mmu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 19a9e112a434..4f0adb07325f 100644
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -118,6 +118,8 @@
#define HCR_EL2_E2H_BIT34
#ifndef __ASSEMBLY__
+#include
+
static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
{
asm volatile("dsb sy");
base-commit: a803f87202aa48974bdff4d8100464a8288931e4
--
2.39.2
Re: [PATCH] mmc: tmio: Disable 1/1024 clock divider on Renesas R-Car platforms
On Sun, Oct 22, 2023 at 11:40:43PM +0200, Marek Vasut wrote:
> The R-Car Gen3 SD_CLK_CTRL register does not use BIT(16) to implement
> divider 1/1024, instead BIT(16) is reserved bit and divider 1/1024 is
> not supported. The divider 1/1024 is specific to Socionext variant of
> the IP, as is indicated by Linux commit:
>
> 0196c8db8363 ("mmc: tmio: move tmio_mmc_set_clock() to platform hook")
> "
> Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer
> versions of UniPhier SoC variants use bit 16 for 1/1024.
> "
>
> Do not set the TMIO_SD_CAP_DIV1024 on Renesas R-Car platforms even if
> the IP VERSION register does exist, and indicates IP version is newer
> or equal to version 1.0 . The IP version 1.0 or newer does not imply
> presence of the 1/1024 divider.
>
> Since the TMIO driver is used exactly by two supported platforms, that
> is Renesas R-Car and Socionext UniPhier, it is OK to check whether the
> TMIO_SD_CAP_RCAR capability is not set to identify the UniPhier platform
> and add the capability only on that platform.
>
> Fixes: 58c35b17aa8f ("mmc: matsushita-common: Always check controller
> version")
> Signed-off-by: Marek Vasut
I've confirmed that the 1/1024 divider doesn't exist in the RZ/G2L
datasheet.
Acked-by: Paul Barker
signature.asc
Description: PGP signature
[PATCH] mmc: renesas-sdhi: Fix error handling in rzg2l_sdhi_setup
We should ensure that reset_free() is called in the error path.
Signed-off-by: Paul Barker
Fixes: 93c811b7331b ("mmc: renesas-sdhi: Initialize module on RZ/G2L")
---
drivers/mmc/renesas-sdhi.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 1ea6e1066f2b..865efdd32184 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -998,7 +998,7 @@ static int rzg2l_sdhi_setup(struct udevice *dev)
ret = reset_get_by_index(dev, 0, );
if (ret < 0) {
dev_err(dev, "failed to get reset line\n");
- goto err_reset;
+ goto err_get_reset;
}
ret = reset_deassert();
@@ -1016,6 +1016,8 @@ static int rzg2l_sdhi_setup(struct udevice *dev)
err_tmio_probe:
reset_assert();
err_reset:
+ reset_free();
+err_get_reset:
clk_disable();
err_aclk:
clk_disable();
base-commit: 9a0cf3993f71043ba08c315572c54622de42d447
--
2.39.2
[PATCH v4 2/2] serial: sh: Add RZ/G2L SCIF support
Extend the existing driver to support the SCIF serial ports on the
Renesas RZ/G2L (R9A07G044) SoC. This also requires us to ensure that if
there is a reset signal defined in the device tree, it is de-asserted
before we try to talk to the SCIF module.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
Tested-by: Marek Vasut
# R-Car H3 Salvator-XS
v3->v4:
* Fix support for devices that don't define a SCI/SCIF module reset in
the device tree.
v2->v3:
* Fixed sorting in the include list and sh_serial_id[].
* Added Marek's Tested-by & Reviewed-by.
v1->v2:
* Moved handle_error() changes out to a separate patch earlier in the
series.
* Unconditionally de-assert the module reset during probe.
---
arch/arm/mach-rmobile/Kconfig | 1 +
drivers/serial/serial_sh.c| 15 +++
drivers/serial/serial_sh.h| 19 ++-
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 714eb4405bcf..2bb96749fc0d 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -77,6 +77,7 @@ config RZG2L
imply PINCTRL_RZG2L
imply RENESAS_SDHI
imply RZG2L_GPIO
+ imply SCIF_CONSOLE
imply SYS_MALLOC_F
help
Enable support for the Renesas RZ/G2L family of SoCs. Currently
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 9a698b19ccde..c034ab54e152 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -12,10 +12,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
#include "serial_sh.h"
@@ -199,12 +201,24 @@ static int sh_serial_probe(struct udevice *dev)
{
struct sh_serial_plat *plat = dev_get_plat(dev);
struct uart_port *priv = dev_get_priv(dev);
+ struct reset_ctl rst;
+ int ret;
priv->membase = (unsigned char *)plat->base;
priv->mapbase = plat->base;
priv->type = plat->type;
priv->clk_mode = plat->clk_mode;
+ /* De-assert the module reset if it is defined. */
+ ret = reset_get_by_index(dev, 0, );
+ if (!ret) {
+ ret = reset_deassert();
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset line\n");
+ return ret;
+ }
+ }
+
sh_serial_init_generic(priv);
return 0;
@@ -221,6 +235,7 @@ static const struct dm_serial_ops sh_serial_ops = {
static const struct udevice_id sh_serial_id[] ={
{.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
+ {.compatible = "renesas,scif-r9a07g044", .data = PORT_SCIFA},
{.compatible = "renesas,scifa", .data = PORT_SCIFA},
{.compatible = "renesas,hscif", .data = PORT_HSCIF},
{}
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 149ec1fe7397..58c2d22bc757 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -90,7 +90,7 @@ struct uart_port {
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_64) || \
- defined(CONFIG_R7S72100)
+ defined(CONFIG_R7S72100) || defined(CONFIG_RZG2L)
# if defined(CFG_SCIF_A)
# define SCIF_ORER0x0200
# else
@@ -312,6 +312,9 @@ static inline void sci_##name##_out(struct uart_port *port,\
sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
+#elif defined(CONFIG_RZG2L)
+#define SCIF_FNS(reg_name, reg_offset, reg_size) \
+ CPU_SCIF_FNS(reg_name, reg_offset, reg_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
@@ -387,6 +390,20 @@ SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
#else
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
+#elif defined(CONFIG_RZG2L)
+SCIF_FNS(SCSMR, 0x00, 16)
+SCIF_FNS(SCBRR, 0x02, 8)
+SCIF_FNS(SCSCR, 0x04, 16)
+SCIF_FNS(SCxTDR, 0x06, 8)
+SCIF_FNS(SCxSR, 0x08, 16)
+SCIF_FNS(SCxRDR, 0x0A, 8)
+SCIF_FNS(SCFCR, 0x0C, 16)
+SCIF_FNS(SCFDR, 0x0E, 16)
+SCIF_FNS(SCSPTR, 0x10, 16)
+SCIF_FNS(SCLSR, 0x12, 16)
+SCIF_FNS(SCSEMR, 0x14, 8)
+SCIF_FNS(SCxTCR, 0x16, 16)
+SCIF_FNS(DL, 0x00, 0)
#else
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
/* name off sz off sz off sz off sz off sz*/
--
2.39.2
[PATCH v4 1/2] serial: sh: Fix error handling
The current SCIF error handling is broken for the RZ/G2L. After a break
condition has been triggered, the current code is unable to clear the
error and serial port output never resumes.
The RZ/G2L datasheet says that most error conditions are cleared by
resetting the relevant error bits in the FSR & LSR registers to zero.
To clear framing errors on SCIF ports, the invalid data also needs to be
read out of the receive FIFO.
After reviewing datasheets for RZ/G2{H,M,N,E}, R-Car Gen4, R-Car Gen3
and even SH7751 SoCs, it's clear that this is the way to clear errors
for all of these SoCs.
While we're here, annotate the handle_error() function with a couple of
comments as the reads and writes themselves don't immediately make it
clear what we're doing.
Signed-off-by: Paul Barker
Tested-by: Chris Paterson
# HiHope RZ/G2M board
Tested-by: Marek Vasut
# R-Car H3 Salvator-XS
v3->v4:
* Don't assume that all the world is a SCIF - handle SCI ports
correctly as well.
v2->v3:
* Added Chris' and Marek's Tested-by.
v1->v2:
* New patch after discussion with Marek & further investigation.
---
drivers/serial/serial_sh.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 36263109e6b8..9a698b19ccde 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -79,10 +79,22 @@ sh_serial_setbrg_generic(struct uart_port *port, int clk,
int baudrate)
static void handle_error(struct uart_port *port)
{
- sci_in(port, SCxSR);
- sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
+ /*
+* Most errors are cleared by resetting the relevant error bits to zero
+* in the FSR & LSR registers. For each register, a read followed by a
+* write is needed according to the relevant datasheets.
+*/
+ unsigned short status = sci_in(port, SCxSR);
+ sci_out(port, SCxSR, status & ~SCxSR_ERRORS(port));
sci_in(port, SCLSR);
sci_out(port, SCLSR, 0x00);
+
+ /*
+* To clear framing errors, we also need to read and discard a
+* character.
+*/
+ if ((port->type != PORT_SCI) && (status & SCIF_FER))
+ sci_in(port, SCxRDR);
}
static int serial_raw_putc(struct uart_port *port, const char c)
--
2.39.2
[PATCH v4 0/2] Add support for the Renesas RZ/G2L SMARC EVK
These patches finish off initial support for the RZ/G2L SMARC Evaluation board kit (EVK). All patches which have already been merged are dropped, this is just the re-worked SCIF patches. These patches have been tested on an RZ/G2L as well as on the qemu 'r2d' machine to confirm that the serial port issue observed by Marek in v3 is fixed. Paul Barker (2): serial: sh: Fix error handling serial: sh: Add RZ/G2L SCIF support arch/arm/mach-rmobile/Kconfig | 1 + drivers/serial/serial_sh.c| 31 +-- drivers/serial/serial_sh.h| 19 ++- 3 files changed, 48 insertions(+), 3 deletions(-) base-commit: 9a0cf3993f71043ba08c315572c54622de42d447 -- 2.39.2
Re: Understanding how .config for uboot is generated in buildroot
On Tue, Oct 17, 2023 at 04:35:20PM +1100, Ignatius Rivaldi wrote: > Hi all, > > When I edit the config file in BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE in a > buildroot recipe, how does the config statements from that file got > converted into .config file in u-boot? > > The background is that we're using a custom buildroot config file at here: > https://github.com/kubos/kubos-linux-build/tree/master to build u-boot for > a space grade computer. When I added a new config statement > (CONFIG_SD_SWITCH=y) in the BR2_TARGET_UBOOT_CUSTOM_CONFIG_FILE, it doesn't > write the config statement to the .config file in the uboot build repo. > > Unfortunately the company that owns that has been acquired several times > and all the engineers there already left, so I can't just ask them You're probably better off asking this on the buildroot mailing list. See https://lists.buildroot.org/mailman/listinfo/buildroot. Best regards, Paul signature.asc Description: PGP signature
[PATCH v3 21/21] board: rzg2l: Add RZ/G2L SMARC EVK board
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC
carrier board.
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a
devicetree blob to the bootloader as an argument in the same was
previous R-Car gen3/gen4 SoCs. This blob contains a compatible string
which can be used to identify the particular SoC we are running on and
this is used to select the appropriate device tree to load.
The configuration renesas_rzg2l_smarc_defconfig is added to support
building for this target. In the future this defconfig will be extended
to support other SoCs and evaluation boards from the RZ/G2L family.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
v2->v3:
* Move memmap-rzg2l.c changes to an earlier patch.
* Drop __weak attributes on board_init() & reset_cpu().
v1->v2:
* Move dram_init() & dram_init_banksize() to memmap-rzg2l.c
* Add a TODO note for reset support.
arch/arm/mach-rmobile/Kconfig.rzg2l | 14 ++
board/renesas/rzg2l/Kconfig | 18 +++
board/renesas/rzg2l/MAINTAINERS | 6 +++
board/renesas/rzg2l/Makefile | 4 ++
board/renesas/rzg2l/rzg2l.c | 67 +++
configs/renesas_rzg2l_smarc_defconfig | 52 +
include/configs/rzg2l-smarc.h | 14 ++
7 files changed, 175 insertions(+)
create mode 100644 board/renesas/rzg2l/Kconfig
create mode 100644 board/renesas/rzg2l/MAINTAINERS
create mode 100644 board/renesas/rzg2l/Makefile
create mode 100644 board/renesas/rzg2l/rzg2l.c
create mode 100644 configs/renesas_rzg2l_smarc_defconfig
create mode 100644 include/configs/rzg2l-smarc.h
diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l
b/arch/arm/mach-rmobile/Kconfig.rzg2l
index 039d6b0a45aa..dc30bdf3e5c2 100644
--- a/arch/arm/mach-rmobile/Kconfig.rzg2l
+++ b/arch/arm/mach-rmobile/Kconfig.rzg2l
@@ -9,6 +9,20 @@ config R9A07G044L
help
Enable support for the Renesas R9A07G044L (RZ/G2L) SoC.
+choice
+ prompt "Renesas RZ/G2L Family Board selection"
+ default TARGET_RZG2L_SMARC_EVK
+
+config TARGET_RZG2L_SMARC_EVK
+ bool "Renesas RZ/G2L SMARC EVK"
+ imply R9A07G044L
+ help
+ Enable support for the RZ/G2L SMARC evaluation board.
+
+source "board/renesas/rzg2l/Kconfig"
+
+endchoice
+
config MULTI_DTB_FIT_UNCOMPRESS_SZ
default 0x8 if TARGET_RZG2L_SMARC_EVK
diff --git a/board/renesas/rzg2l/Kconfig b/board/renesas/rzg2l/Kconfig
new file mode 100644
index ..1335fc7ae806
--- /dev/null
+++ b/board/renesas/rzg2l/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+if TARGET_RZG2L_SMARC_EVK
+
+config SYS_SOC
+ default "rmobile"
+
+config SYS_BOARD
+ default "rzg2l"
+
+config SYS_VENDOR
+ default "renesas"
+
+config SYS_CONFIG_NAME
+ default "rzg2l-smarc"
+
+endif
diff --git a/board/renesas/rzg2l/MAINTAINERS b/board/renesas/rzg2l/MAINTAINERS
new file mode 100644
index ..0a51391c1fc9
--- /dev/null
+++ b/board/renesas/rzg2l/MAINTAINERS
@@ -0,0 +1,6 @@
+RENESAS RZG2L BOARD FAMILY
+M: Paul Barker
+S: Supported
+F: arch/arm/dts/rz-smarc-common.dtsi
+N: rzg2l
+N: r9a07g044
diff --git a/board/renesas/rzg2l/Makefile b/board/renesas/rzg2l/Makefile
new file mode 100644
index ..466935fc8158
--- /dev/null
+++ b/board/renesas/rzg2l/Makefile
@@ -0,0 +1,4 @@
+# Copyright (C) 2023 Renesas Electronics Corporation
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := rzg2l.o
diff --git a/board/renesas/rzg2l/rzg2l.c b/board/renesas/rzg2l/rzg2l.c
new file mode 100644
index ..755747e665cb
--- /dev/null
+++ b/board/renesas/rzg2l/rzg2l.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * RZ/G2L board support.
+ * Copyright (C) 2023 Renesas Electronics Corporation
+ */
+
+#include
+#include
+#include
+
+#if IS_ENABLED(CONFIG_MULTI_DTB_FIT)
+/* If the firmware passed a device tree, use it for board identification. */
+extern u64 rcar_atf_boot_args[];
+
+static bool is_rzg2l_board(const char *board_name)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ return fdt_node_check_compatible(atf_fdt_blob, 0, board_name) == 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) != FDT_MAGIC)
+ return -1;
+
+ if (is_rzg2l_board("renesas,r9a07g044l2"))
+ return strcmp(name, "r9a07g044l2-smarc");
+
+ return -1;
+}
+#endif
+
+static void apply_atf_overlay(void *fdt_blob)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC)
+
[PATCH v3 20/21] arm: dts: Import RZ/G2L SMARC EVK device tree
The Renesas RZ/G2L SMARC Evaluation Board Kit consists of the RZ/G2L
System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC
carrier board.
This patch is based on the corresponding Linux v6.5 device tree
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
---
v2->v3: No changes.
v1->v2:
* Added the exact Linux commit we imported from.
* Add Marek's Reivewed-by.
arch/arm/dts/Makefile |3 +
arch/arm/dts/r9a07g044.dtsi | 1273 +
arch/arm/dts/r9a07g044l2-smarc.dts| 18 +
arch/arm/dts/r9a07g044l2.dtsi | 13 +
arch/arm/dts/rz-smarc-common.dtsi | 183 +++
arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 137 +++
arch/arm/dts/rzg2l-smarc-som.dtsi | 353 ++
arch/arm/dts/rzg2l-smarc.dtsi | 144 +++
8 files changed, 2124 insertions(+)
create mode 100644 arch/arm/dts/r9a07g044.dtsi
create mode 100644 arch/arm/dts/r9a07g044l2-smarc.dts
create mode 100644 arch/arm/dts/r9a07g044l2.dtsi
create mode 100644 arch/arm/dts/rz-smarc-common.dtsi
create mode 100644 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi
create mode 100644 arch/arm/dts/rzg2l-smarc-som.dtsi
create mode 100644 arch/arm/dts/rzg2l-smarc.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6e9c5f07999d..11270532d429 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1120,6 +1120,9 @@ dtb-$(CONFIG_RCAR_GEN4) += \
r8a779f0-spider-u-boot.dtb \
r8a779g0-white-hawk-u-boot.dtb
+dtb-$(CONFIG_TARGET_RZG2L) += \
+ r9a07g044l2-smarc.dts
+
ifdef CONFIG_RCAR_64
DTC_FLAGS += -R 4 -p 0x1000
endif
diff --git a/arch/arm/dts/r9a07g044.dtsi b/arch/arm/dts/r9a07g044.dtsi
new file mode 100644
index ..232910e07444
--- /dev/null
+++ b/arch/arm/dts/r9a07g044.dtsi
@@ -0,0 +1,1273 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a07g044";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ audio_clk1: audio1-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio2-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it */
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board */
+ clock-frequency = <0>;
+ };
+
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-15000 {
+ opp-hz = /bits/ 64 <15000>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <30>;
+ };
+ opp-3 {
+ opp-hz = /bits/ 64 <3>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <30>;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <30>;
+ };
+ opp-12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <110>;
+ clock-latency-ns = <30>;
+ opp-suspend;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <>;
+ };
+ core1 {
+ cpu = <>;
+ };
+ };
+
[PATCH v3 19/21] arm: rmobile: Support RZ/G2L memory map
The memory map for the RZ/G2L family differs from that of previous R-Car
Gen3/Gen4 SoCs.
A high level memory map can be seen in figure 5.2 (section 5.2.1) of the
RZ/G2L data sheet rev 1.30 published May 12, 2023. A summary is included
here (note that this is a 34-bit address space):
* 0x0__ - 0x0_0002_ SRAM area
* 0x0_0003_ - 0x0_0FFF_ Reserved area
* 0x0_1000_ - 0x0_1FFF_ I/O register area
* 0x0_2000_ - 0x0_2FFF_ SPI Multi area
* 0x0_3000_ - 0x0_3FFF_ Reserved area
* 0x0_4000_ - 0x1_3FFF_ DDR area (4 GiB)
* 0x1_4000_ - 0x3__ Reserved area
Within the DDR area, the first 128 MiB are reserved by TrustedFirmware.
The region from 0x43F0 to 0x47DF inclusive is protected for use
in TrustedFirmware/OP-TEE, but all other memory is included in the
memory map. This reservation is the same as used in R-Car
Gen3/Gen4 and RZ/G2{H,M,N,E} SoCs.
DRAM information is initialised based on the data in the fdt.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
---
v2->v3:
* Include dram_init() & dram_init_banksize() functions.
* Added Marek's Reviewed-by.
v1->v2:
* Improve commit message.
arch/arm/mach-rmobile/Makefile | 8 +-
arch/arm/mach-rmobile/memmap-rzg2l.c | 127 +++
2 files changed, 131 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/mach-rmobile/memmap-rzg2l.c
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 45d6a0e2a28a..ff8b0c7bae25 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -10,11 +10,11 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o memmap-gen3.o
-obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o
-obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o
+obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
+obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
-obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o
+obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o
ifneq ($(CONFIG_R8A779A0),)
obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o
diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c
b/arch/arm/mach-rmobile/memmap-rzg2l.c
new file mode 100644
index ..a08d0ea08fc0
--- /dev/null
+++ b/arch/arm/mach-rmobile/memmap-rzg2l.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RZ/G2L family memory map tables
+ *
+ * Copyright (C) 2017 Marek Vasut
+ * Copyright (C) 2023 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+#define RZG2L_NR_REGIONS 16
+
+/*
+ * RZ/G2L supports up to 4 GiB RAM starting at 0x4000, of
+ * which the first 128 MiB is reserved by TF-A.
+ */
+static struct mm_region rzg2l_mem_map[RZG2L_NR_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x4000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x4000UL,
+ .phys = 0x4000UL,
+ .size = 0x03F0UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x47E0UL,
+ .phys = 0x47E0UL,
+ .size = 0xF820UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rzg2l_mem_map;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define debug_memmap(i, map) \
+ debug("memmap %d: virt 0x%llx -> phys 0x%llx, size=0x%llx,
attrs=0x%llx\n", \
+ i, map[i].virt, map[i].phys, map[i].size, map[i].attrs)
+
+void enable_caches(void)
+{
+ unsigned int bank, i = 0;
+ u64 start, size;
+
+ /* Create map for register access */
+ rzg2l_mem_map[i].virt = 0x0ULL;
+ rzg2l_mem_map[i].phys = 0x0ULL;
+ rzg2l_mem_map[i].size = 0x4000ULL;
+ rzg2l_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN;
+ debug_memmap(i, rzg2l_mem_map);
+ i++;
+
+ /* Generate entries for DRAM in 32bit address space */
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+ start = gd->bd->bi_dram[bank].start;
+ size = gd->bd->bi_dram[bank].size;
+
+ /* Skip empty D
[PATCH v3 18/21] arm: rmobile: Add CPU detection for RZ/G2L
The ARM TrustedFirmware code for the Renesas RZ/G2L SoC family passes a
devicetree blob to the bootloader as an argument in the same was
previous R-Car Gen3/Gen4 SoCs. This blob contains a compatible string
which can be used to identify the particular SoC we are running on.
We do this as reading the DEVID & PRR registers from u-boot is not
sufficient to differentiate between the R9A07G044L (RZ/G2L) and
R9A07G044C (RZ/G2LC) SoCs. An additional read from offset 0x11861178 is
needed but this address is in the OTP region which can only be read from
the secure world (i.e. TrustedFirmware). So we have to rely on
TrustedFirmware to determine the SoC and pass this information to u-boot
via an fdt blob.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
---
v2->v3:
* Added Marek's Reviewed-by.
v1->v2:
* Improved commit message.
arch/arm/mach-rmobile/Makefile | 5 +-
arch/arm/mach-rmobile/cpu_info-rzg2l.c | 63
arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
3 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-rmobile/cpu_info-rzg2l.c
diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 4eddba53ed2a..45d6a0e2a28a 100644
--- a/arch/arm/mach-rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -10,8 +10,11 @@ obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
-obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o
+obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o
obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
+obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o
ifneq ($(CONFIG_R8A779A0),)
obj-$(CONFIG_ARMV8_PSCI) += psci-r8a779a0.o
diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c
b/arch/arm/mach-rmobile/cpu_info-rzg2l.c
new file mode 100644
index ..de4892ee901e
--- /dev/null
+++ b/arch/arm/mach-rmobile/cpu_info-rzg2l.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021,2023 Renesas Electronics Corporation
+ *
+ */
+
+#include
+#include
+#include
+
+#define SYSC_LSI_DEVID 0x11020A04
+
+/* If the firmware passed a device tree, use it for soc identification. */
+extern u64 rcar_atf_boot_args[];
+
+/* CPU information table */
+struct tfa_info {
+ const char *soc_name;
+ const char *cpu_name;
+ u32 cpu_type;
+};
+
+static const struct tfa_info tfa_info[] = {
+ { "renesas,r9a07g044l2", "R9A07G044L", RMOBILE_CPU_TYPE_R9A07G044L },
+};
+
+static const struct tfa_info invalid_tfa_info = { NULL, "(invalid)", 0 };
+
+static const struct tfa_info *get_tfa_info(void)
+{
+ void *atf_fdt_blob = (void *)(rcar_atf_boot_args[1]);
+
+ if (fdt_magic(atf_fdt_blob) == FDT_MAGIC) {
+ unsigned int i;
+ for (i = 0; i < ARRAY_SIZE(tfa_info); i++) {
+ if (!fdt_node_check_compatible(atf_fdt_blob, 0,
+ tfa_info[i].soc_name))
+ return _info[i];
+ }
+ }
+
+ return _tfa_info;
+}
+
+const u8 *rzg_get_cpu_name(void)
+{
+ return get_tfa_info()->cpu_name;
+}
+
+u32 rmobile_get_cpu_type(void)
+{
+ return get_tfa_info()->cpu_type;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+ return (readl(SYSC_LSI_DEVID) >> 28) + 1;
+}
+
+u32 rmobile_get_cpu_rev_fraction(void)
+{
+ return 0;
+}
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h
b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 053ad08add00..88b8b78671b2 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -43,6 +43,7 @@
#define RMOBILE_CPU_TYPE_R8A779A0 0x59
#define RMOBILE_CPU_TYPE_R8A779F0 0x5A
#define RMOBILE_CPU_TYPE_R8A779G0 0x5C
+#define RMOBILE_CPU_TYPE_R9A07G044L0x9A070440
#ifndef __ASSEMBLY__
#include
--
2.39.2
[PATCH v3 15/21] mmc: renesas-sdhi: Refactor probe function
Move the assignment of priv->quirks earlier in the function. This allows
us to drop the quirks local variable and makes it easier to maintain
clean error handling when we add RZ/G2L support in the next patch.
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
v2->v3:
* Added Marek's Reviewed-by.
v1->v2:
* New patch to support breaking out RZ/G2L-specific initialization
into its own function.
drivers/mmc/renesas-sdhi.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 8e716f74491f..1536c9782041 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -961,14 +961,14 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
static int renesas_sdhi_probe(struct udevice *dev)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
- u32 quirks = dev_get_driver_data(dev);
struct fdt_resource reg_res;
DECLARE_GLOBAL_DATA_PTR;
int ret;
priv->clk_get_rate = renesas_sdhi_clk_get_rate;
- if (quirks == RENESAS_GEN2_QUIRKS) {
+ priv->quirks = dev_get_driver_data(dev);
+ if (priv->quirks == RENESAS_GEN2_QUIRKS) {
ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
"reg", 0, _res);
if (ret < 0) {
@@ -978,7 +978,7 @@ static int renesas_sdhi_probe(struct udevice *dev)
}
if (fdt_resource_size(_res) == 0x100)
- quirks |= TMIO_SD_CAP_16BIT;
+ priv->quirks |= TMIO_SD_CAP_16BIT;
}
ret = clk_get_by_index(dev, 0, >clk);
@@ -1012,8 +1012,7 @@ static int renesas_sdhi_probe(struct udevice *dev)
goto err_clkh;
}
- priv->quirks = quirks;
- ret = tmio_sd_probe(dev, quirks);
+ ret = tmio_sd_probe(dev, priv->quirks);
if (ret)
goto err_tmio_probe;
--
2.39.2
[PATCH v3 17/21] arm: rmobile: Include in header
We don't want to rely on source files including before . Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Marek Vasut --- v2->v3: No changes. v1->v2: * Added Marek's Reviewed-by. arch/arm/mach-rmobile/include/mach/rmobile.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index d326d5545a6f..053ad08add00 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -45,6 +45,8 @@ #define RMOBILE_CPU_TYPE_R8A779G0 0x5C #ifndef __ASSEMBLY__ +#include + const u8 *rzg_get_cpu_name(void); u32 rmobile_get_cpu_type(void); u32 rmobile_get_cpu_rev_integer(void); -- 2.39.2
[PATCH v3 14/21] serial: sh: Add RZ/G2L SCIF support
Extend the existing driver to support the SCIF serial ports on the
Renesas RZ/G2L (R9A07G044) SoC. This also requires us to ensure that the
relevant reset signal is de-asserted before we try to talk to the SCIF
module.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
Tested-by: Marek Vasut
# R-Car H3 Salvator-XS
---
v2->v3:
* Fixed sorting in the include list and sh_serial_id[].
* Added Marek's Tested-by & Reviewed-by.
v1->v2:
* Moved handle_error() changes out to a separate patch earlier in the
series.
* Unconditionally de-assert the module reset during probe.
arch/arm/mach-rmobile/Kconfig | 1 +
drivers/serial/serial_sh.c| 17 +
drivers/serial/serial_sh.h| 19 ++-
3 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 714eb4405bcf..2bb96749fc0d 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -77,6 +77,7 @@ config RZG2L
imply PINCTRL_RZG2L
imply RENESAS_SDHI
imply RZG2L_GPIO
+ imply SCIF_CONSOLE
imply SYS_MALLOC_F
help
Enable support for the Renesas RZ/G2L family of SoCs. Currently
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 6ba3b15ff1f8..3890c6247b92 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -12,10 +12,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include
#include "serial_sh.h"
@@ -199,12 +201,26 @@ static int sh_serial_probe(struct udevice *dev)
{
struct sh_serial_plat *plat = dev_get_plat(dev);
struct uart_port *priv = dev_get_priv(dev);
+ struct reset_ctl rst;
+ int ret;
priv->membase = (unsigned char *)plat->base;
priv->mapbase = plat->base;
priv->type = plat->type;
priv->clk_mode = plat->clk_mode;
+ ret = reset_get_by_index(dev, 0, );
+ if (ret < 0) {
+ dev_err(dev, "failed to get reset line\n");
+ return ret;
+ }
+
+ ret = reset_deassert();
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset line\n");
+ return ret;
+ }
+
sh_serial_init_generic(priv);
return 0;
@@ -221,6 +237,7 @@ static const struct dm_serial_ops sh_serial_ops = {
static const struct udevice_id sh_serial_id[] ={
{.compatible = "renesas,sci", .data = PORT_SCI},
{.compatible = "renesas,scif", .data = PORT_SCIF},
+ {.compatible = "renesas,scif-r9a07g044", .data = PORT_SCIFA},
{.compatible = "renesas,scifa", .data = PORT_SCIFA},
{.compatible = "renesas,hscif", .data = PORT_HSCIF},
{}
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index 149ec1fe7397..58c2d22bc757 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -90,7 +90,7 @@ struct uart_port {
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
# define SCIF_ORER 0x0001 /* overrun error bit */
#elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_64) || \
- defined(CONFIG_R7S72100)
+ defined(CONFIG_R7S72100) || defined(CONFIG_RZG2L)
# if defined(CFG_SCIF_A)
# define SCIF_ORER0x0200
# else
@@ -312,6 +312,9 @@ static inline void sci_##name##_out(struct uart_port *port,\
sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
+#elif defined(CONFIG_RZG2L)
+#define SCIF_FNS(reg_name, reg_offset, reg_size) \
+ CPU_SCIF_FNS(reg_name, reg_offset, reg_size)
#else
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
@@ -387,6 +390,20 @@ SCIF_FNS(SCLSR, 0, 0, 0x14, 16)
#else
SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
#endif
+#elif defined(CONFIG_RZG2L)
+SCIF_FNS(SCSMR, 0x00, 16)
+SCIF_FNS(SCBRR, 0x02, 8)
+SCIF_FNS(SCSCR, 0x04, 16)
+SCIF_FNS(SCxTDR, 0x06, 8)
+SCIF_FNS(SCxSR, 0x08, 16)
+SCIF_FNS(SCxRDR, 0x0A, 8)
+SCIF_FNS(SCFCR, 0x0C, 16)
+SCIF_FNS(SCFDR, 0x0E, 16)
+SCIF_FNS(SCSPTR, 0x10, 16)
+SCIF_FNS(SCLSR, 0x12, 16)
+SCIF_FNS(SCSEMR, 0x14, 8)
+SCIF_FNS(SCxTCR, 0x16, 16)
+SCIF_FNS(DL, 0x00, 0)
#else
/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
/* name off sz off sz off sz off sz off sz*/
--
2.39.2
[PATCH v3 13/21] serial: sh: Sort includes
Tidy up the existing include list before we add more includes in the following patch. Signed-off-by: Paul Barker --- v2->v3: * New patch, required to keep the include list in order in the following patch. drivers/serial/serial_sh.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 2b650d458e71..6ba3b15ff1f8 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -7,16 +7,16 @@ */ #include -#include -#include -#include #include #include #include -#include -#include +#include +#include #include +#include +#include #include +#include #include "serial_sh.h" DECLARE_GLOBAL_DATA_PTR; -- 2.39.2
[PATCH v3 16/21] mmc: renesas-sdhi: Initialize module on RZ/G2L
On the Renesas RZ/G2L SoC family, we must ensure that the required clock
signals are enabled and the reset signal is de-asserted before we try to
communicate with the SDHI module.
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
---
v2->v3:
* Check the device's compatible string instead of checking for
CONFIG_RZG2L to determine whether to call rzg2l_sdhi_setup().
* Simplify error handling.
v1->v2:
* Move RZ/G2L specific setup to its own function.
drivers/mmc/renesas-sdhi.c | 74 +-
1 file changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c
index 1536c9782041..1ea6e1066f2b 100644
--- a/drivers/mmc/renesas-sdhi.c
+++ b/drivers/mmc/renesas-sdhi.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include "tmio-common.h"
@@ -958,6 +959,74 @@ static void renesas_sdhi_filter_caps(struct udevice *dev)
priv->needs_clkh_fallback = false;
}
+static int rzg2l_sdhi_setup(struct udevice *dev)
+{
+ struct tmio_sd_priv *priv = dev_get_priv(dev);
+ struct clk imclk2, aclk;
+ struct reset_ctl rst;
+ int ret;
+
+ /*
+* On members of the RZ/G2L SoC family, we need to enable
+* additional chip detect and bus clocks, then release the SDHI
+* module from reset.
+*/
+ ret = clk_get_by_name(dev, "cd", );
+ if (ret < 0) {
+ dev_err(dev, "failed to get imclk2 (chip detect clk)\n");
+ goto err_get_imclk2;
+ }
+
+ ret = clk_get_by_name(dev, "aclk", );
+ if (ret < 0) {
+ dev_err(dev, "failed to get aclk\n");
+ goto err_get_aclk;
+ }
+
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "failed to enable imclk2 (chip detect clk)\n");
+ goto err_imclk2;
+ }
+
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "failed to enable aclk\n");
+ goto err_aclk;
+ }
+
+ ret = reset_get_by_index(dev, 0, );
+ if (ret < 0) {
+ dev_err(dev, "failed to get reset line\n");
+ goto err_reset;
+ }
+
+ ret = reset_deassert();
+ if (ret < 0) {
+ dev_err(dev, "failed to de-assert reset line\n");
+ goto err_reset;
+ }
+
+ ret = tmio_sd_probe(dev, priv->quirks);
+ if (ret)
+ goto err_tmio_probe;
+
+ return 0;
+
+err_tmio_probe:
+ reset_assert();
+err_reset:
+ clk_disable();
+err_aclk:
+ clk_disable();
+err_imclk2:
+ clk_free();
+err_get_aclk:
+ clk_free();
+err_get_imclk2:
+ return ret;
+}
+
static int renesas_sdhi_probe(struct udevice *dev)
{
struct tmio_sd_priv *priv = dev_get_priv(dev);
@@ -1012,7 +1081,10 @@ static int renesas_sdhi_probe(struct udevice *dev)
goto err_clkh;
}
- ret = tmio_sd_probe(dev, priv->quirks);
+ if (device_is_compatible(dev, "renesas,sdhi-r9a07g044"))
+ ret = rzg2l_sdhi_setup(dev);
+ else
+ ret = tmio_sd_probe(dev, priv->quirks);
if (ret)
goto err_tmio_probe;
--
2.39.2
[PATCH v3 12/21] serial: sh: Fix error handling
The current SCIF error handling is broken for the RZ/G2L. After a break
condition has been triggered, the current code is unable to clear the
error and serial port output never resumes.
The RZ/G2L datasheet says that most error conditions are cleared by
resetting the relevant error bits in the FSR & LSR registers to zero.
To clear framing errors, the invalid data also needs to be read out of
the receive FIFO.
After reviewing datasheets for RZ/G2{H,M,N,E}, R-Car Gen4, R-Car Gen3
and even SH7751 SoCs, it's clear that this is the way to clear errors
for all of these SoCs.
While we're here, annotate the handle_error() function with a couple of
comments as the reads and writes themselves don't immediately make it
clear what we're doing.
Signed-off-by: Paul Barker
Tested-by: Chris Paterson
# HiHope RZ/G2M board
Tested-by: Marek Vasut
# R-Car H3 Salvator-XS
---
v2->v3:
* Added Chris' and Marek's Tested-by.
v1->v2:
* New patch after discussion with Marek & further investigation.
I've not put a `Fixes` tag on this, the error handling has been writing
ones to clear errors since at least 2007 so maybe it was originally
right for some board. It doesn't seem to apply to any of the current
users of the SCIF driver though.
drivers/serial/serial_sh.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c
index 5e543dbf3d58..2b650d458e71 100644
--- a/drivers/serial/serial_sh.c
+++ b/drivers/serial/serial_sh.c
@@ -79,10 +79,22 @@ sh_serial_setbrg_generic(struct uart_port *port, int clk,
int baudrate)
static void handle_error(struct uart_port *port)
{
- sci_in(port, SCxSR);
- sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
+ /*
+* Most errors are cleared by resetting the relevant error bits to zero
+* in the FSR & LSR registers. For each register, a read followed by a
+* write is needed according to the relevant datasheets.
+*/
+ unsigned short status = sci_in(port, SCxSR);
+ sci_out(port, SCxSR, status & ~SCIF_ERRORS);
sci_in(port, SCLSR);
sci_out(port, SCLSR, 0x00);
+
+ /*
+* To clear framing errors, we also need to read and discard a
+* character.
+*/
+ if (status & SCIF_FER)
+ sci_in(port, SCxRDR);
}
static int serial_raw_putc(struct uart_port *port, const char c)
--
2.39.2
[PATCH v3 11/21] gpio: Add RZ/G2L GPIO driver
This driver adds support for the gpio features of the GPIO/PFC module in
the Renesas RZ/G2L (R9A07G044) SoC.
The new `rzg2l-pfc-gpio` driver is bound to the same device tree node as
the `rzg2l-pfc-pinctrl` driver as the same hardware block provides both
GPIO and pin multiplexing features.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
---
v2->v3:
* New patch, split off from the pinctrl driver patch.
* Made CONFIG_RZG2L_GPIO depend on CONFIG_PINCTRL_RZG2L instead of the
other way around as this matches how the code is structured (the
pinctrl driver contains the common features and initialisation that
the GPIO driver depends on) and how the hardware works (you can
mux pins for non-GPIO functions without a GPIO driver, but you can't
use pins for GPIO without first being sure they're muxed correctly).
* The GPIO driver binding in rzg2l_pfc_bind() is moved after the
pinctrl driver binding and made conditional on CONFIG_RZG2L_GPIO.
* Fix indentation around rzg2l_gpio_set() to appease checkpatch.
* Copied Reviewed-by tags from the previous commit as there are only
minimal changes from what was previously reviewed.
arch/arm/mach-rmobile/Kconfig | 1 +
drivers/gpio/Kconfig| 7 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/rzg2l-gpio.c | 170
drivers/pinctrl/renesas/rzg2l-pfc.c | 24 +++-
5 files changed, 200 insertions(+), 3 deletions(-)
create mode 100644 drivers/gpio/rzg2l-gpio.c
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 35e902357144..714eb4405bcf 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -76,6 +76,7 @@ config RZG2L
imply MULTI_DTB_FIT_USER_DEFINED_AREA
imply PINCTRL_RZG2L
imply RENESAS_SDHI
+ imply RZG2L_GPIO
imply SYS_MALLOC_F
help
Enable support for the Renesas RZ/G2L family of SoCs. Currently
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 9bf6e428ded2..74baa98d3c15 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -659,4 +659,11 @@ config ADP5585_GPIO
help
Support ADP5585 GPIO expander.
+config RZG2L_GPIO
+ bool "Renesas RZ/G2L family GPIO driver"
+ depends on DM_GPIO && PINCTRL_RZG2L
+ help
+ Support the gpio functionality of the pin function controller (PFC)
+ on the Renesas RZ/G2L SoC family.
+
endif
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 64a36c472ebe..c8b3fd78141a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_SLG7XL45106_I2C_GPO) += gpio_slg7xl45106.o
obj-$(CONFIG_$(SPL_TPL_)TURRIS_OMNIA_MCU) += turris_omnia_mcu.o
obj-$(CONFIG_FTGPIO010)+= ftgpio010.o
obj-$(CONFIG_ADP5585_GPIO) += adp5585_gpio.o
+obj-$(CONFIG_RZG2L_GPIO) += rzg2l-gpio.o
diff --git a/drivers/gpio/rzg2l-gpio.c b/drivers/gpio/rzg2l-gpio.c
new file mode 100644
index ..7c908d05475a
--- /dev/null
+++ b/drivers/gpio/rzg2l-gpio.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L Pin Function Controller
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static void rzg2l_gpio_set(const struct rzg2l_pfc_data *data, u32 port, u8 pin,
+ bool value)
+{
+ if (value)
+ setbits_8(data->base + P(port), BIT(pin));
+ else
+ clrbits_8(data->base + P(port), BIT(pin));
+}
+
+static int rzg2l_gpio_get_value(struct udevice *dev, unsigned int offset)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+ u16 pm_state;
+
+ pm_state = (readw(data->base + PM(port)) >> (pin * 2)) & PM_MASK;
+ switch (pm_state) {
+ case PM_INPUT:
+ return !!(readb(data->base + PIN(port)) & BIT(pin));
+ case PM_OUTPUT:
+ case PM_OUTPUT_IEN:
+ return !!(readb(data->base + P(port)) & BIT(pin));
+ default:/* PM_HIGH_Z */
+ return 0;
+ }
+}
+
+static int rzg2l_gpio_set_value(struct udevice *dev, unsigned int offset,
+ int value)
+{
+ const struct rzg2l_pfc_data *data =
+ (const struct rzg2l_pfc_data *)dev_get_driver_data(dev);
+ const u32 port = RZG2L_PINMUX_TO_PORT(offset);
+ const u8 pin = RZG2L_PINMUX_TO_PIN(offset);
+
+ rzg2l_gpio_set(data, port, pin, (bool)value);
+ return 0;
+}
+
+static void rzg2
[PATCH v3 10/21] pinctrl: renesas: Add RZ/G2L PFC driver
This driver adds support for the pinctrl features of the GPIO/PFC module
in the Renesas RZ/G2L (R9A07G044) SoC.
A multi-function `rzg2l-pfc` driver is defined for UCLASS_NOP, which
binds the `rzg2l-pfc-pinctrl` UCLASS_PINCTRL driver dynamically. We also
define common macros and functions for the PFC in .
This makes it easy to add an additional UCLASS_GPIO driver for the GPIO
functionality of this module in a follow-up patch.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
---
v2->v3:
* Split GPIO driver into a separate patch which follows this one. This
required a bit more explanation in this commit message of why we
have a pair of drivers instead of just one and why we add a header
file.
* Added the exact Linux commit we referenced when developing the
driver.
* Fix SPDX header style to appease checkpatch in
.
* Added Marek's Reviewed-by.
v1->v2:
* Split GPIO into separate file.
* Drop unnecessary parenthesis in defines.
* Keep Kconfig list sorted.
* Drop pfc_enabled flag.
* Use const where possible.
* Use clrbits/setbits/clrsetbits functions.
* Return -ENOENT to skip invalid GPIO offsets.
* Include ofnode_parse_phandle_with_args() return code in err print.
* Use macro instal of port + 0x10.
* Add TODO comment re Ethernet PIN_CFG.
arch/arm/mach-rmobile/Kconfig | 1 +
drivers/pinctrl/renesas/Kconfig | 9 +
drivers/pinctrl/renesas/Makefile| 1 +
drivers/pinctrl/renesas/rzg2l-pfc.c | 607
include/renesas/rzg2l-pfc.h | 110 +
5 files changed, 728 insertions(+)
create mode 100644 drivers/pinctrl/renesas/rzg2l-pfc.c
create mode 100644 include/renesas/rzg2l-pfc.h
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index af1f99197d9f..35e902357144 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -74,6 +74,7 @@ config RZG2L
imply CLK_RZG2L
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
+ imply PINCTRL_RZG2L
imply RENESAS_SDHI
imply SYS_MALLOC_F
help
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 32f44e5bbd7d..4c8ec9fcf181 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -138,6 +138,15 @@ config PINCTRL_RZA1
help
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
+config PINCTRL_RZG2L
+ bool "Renesas RZ/G2L family pin control driver"
+ depends on PINCTRL
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ help
+ Support the pinctrl functionality of the pin function controller (PFC)
+ on the Renesas RZ/G2L SoC family.
+
endif
config PINCTRL_RZN1
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index f9a68794eb9c..cf7ec109681f 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
+obj-$(CONFIG_PINCTRL_RZG2L) += rzg2l-pfc.o
diff --git a/drivers/pinctrl/renesas/rzg2l-pfc.c
b/drivers/pinctrl/renesas/rzg2l-pfc.c
new file mode 100644
index ..ce4062ff3039
--- /dev/null
+++ b/drivers/pinctrl/renesas/rzg2l-pfc.c
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L Pin Function Controller
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct rzg2l_pfc_driver_data {
+ uint num_dedicated_pins;
+ uint num_ports;
+ const u32 *gpio_configs;
+};
+
+struct rzg2l_dedicated_configs {
+ const char *name;
+ u32 config;
+};
+
+/*
+ * We need to ensure that the module clock is enabled and all resets are
+ * de-asserted before using either the gpio or pinctrl functionality. Error
+ * handling can be quite simple here as if the PFC cannot be enabled then we
+ * will not be able to progress with the boot anyway.
+ */
+int rzg2l_pfc_enable(struct udevice *dev)
+{
+ struct reset_ctl_bulk rsts;
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, );
+ if (ret < 0) {
+ dev_err(dev, "failed to get gpio module clock\n");
+ return ret;
+ }
+
+ ret = clk_enable();
+ if (ret < 0) {
+ dev_err(dev, "failed to enable gpio module clock\n");
+ return ret;
+ }
+
+ ret = reset_get_bulk(dev, );
+ if (ret < 0) {
+
[PATCH v3 09/21] cmd: gpio: Skip output on -ENOENT
On the Renesas RZ/G2L SoC family, valid GPIO numbers are not contiguous.
This is determined by the device tree, where a fixed number of bits are
used for the 'pin' number within a 'port', even though not all ports
have the same number of pins. The device tree can't be changed here
without breaking backwards compatibility in Linux, which we don't want
to do.
To avoid printing a status for each of these invalid GPIO numbers when
a user executes `gpio status -a`, we allow gpio_get_function() to return
-ENOENT when the given offset does not refer to a valid GPIO pin and we
skip printing anything if this occurs.
Signed-off-by: Paul Barker
Reviewed-by: Marek Vasut
---
v2->v3:
* Simply error path in gpio_get_description().
* Added Marek's Reviewed-by.
v1->v2:
* New patch to simplify `gpio status -a` output.
cmd/gpio.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/cmd/gpio.c b/cmd/gpio.c
index f4565982ecd9..dab6f7097aec 100644
--- a/cmd/gpio.c
+++ b/cmd/gpio.c
@@ -17,6 +17,7 @@
#endif
#include
#include
+#include
__weak int name_to_gpio(const char *name)
{
@@ -69,7 +70,8 @@ static void gpio_get_description(struct udevice *dev, const
char *bank_name,
printf("%s\n", buf);
return;
err:
- printf("Error %d\n", ret);
+ if (ret != -ENOENT)
+ printf("Error %d\n", ret);
}
static int do_gpio_status(bool all, const char *gpio_name)
--
2.39.2
[PATCH v3 07/21] clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver
This driver provides clock and reset control for the Renesas R9A07G044L
(RZ/G2L) and R9A07G044C (RZ/G2LC) SoC. It consists of two parts:
* driver code which is applicable to all SoCs in the RZ/G2L family.
* static data describing the clocks and resets which are specific to the
R9A07G044{L,C} SoCs. The identifier r9a07g044 (without a final letter)
is used to indicate that both SoCs are supported.
clk_set_rate() and clk_get_rate() are implemented only for the clocks
that are actually used in u-boot.
The CPG driver is marked with DM_FLAG_PRE_RELOC to ensure that its bind
function is called before the SCIF (serial port) driver is probed. This
is required so that we can de-assert the relevant reset signal during
the serial driver probe function.
This patch is based on the corresponding Linux v6.5 driver
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).
Signed-off-by: Paul Barker
Reviewed-by: Biju Das
Reviewed-by: Lad Prabhakar
Reviewed-by: Marek Vasut
---
v2->v3:
* Added Marek's Reviewed-by.
v1->v2:
* Added the exact Linux commit we imported from.
* Sorted imply statements under config RZG2L.
* Note that this CPG driver will also be used for the RZ/G2LC.
* Clarify the way we use `r9a07g044` in the code.
* Fix use of brackets in definitions & expressions.
* Fix comment block style.
* Fix mixed tabs/spaces usage.
* Use const where possible for variables.
arch/arm/mach-rmobile/Kconfig | 1 +
arch/arm/mach-rmobile/Kconfig.rzg2l | 1 +
drivers/clk/renesas/Kconfig | 9 +
drivers/clk/renesas/Makefile| 2 +
drivers/clk/renesas/r9a07g044-cpg.c | 384 +
drivers/clk/renesas/rzg2l-cpg.c | 505
drivers/clk/renesas/rzg2l-cpg.h | 319 ++
7 files changed, 1221 insertions(+)
create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.c
create mode 100644 drivers/clk/renesas/rzg2l-cpg.h
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 1d8d26d8367f..c5419e8d69c0 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -70,6 +70,7 @@ config RZG2L
prompt "Renesas RZ/G2L Family ARM SoCs"
select GICV3
select RCAR_64
+ imply CLK_RZG2L
imply MULTI_DTB_FIT
imply MULTI_DTB_FIT_USER_DEFINED_AREA
imply RENESAS_SDHI
diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l
b/arch/arm/mach-rmobile/Kconfig.rzg2l
index eda04df5c619..039d6b0a45aa 100644
--- a/arch/arm/mach-rmobile/Kconfig.rzg2l
+++ b/arch/arm/mach-rmobile/Kconfig.rzg2l
@@ -5,6 +5,7 @@ if RZG2L
config R9A07G044L
bool "Renesas R9A07G044L SoC"
+ imply CLK_R9A07G044
help
Enable support for the Renesas R9A07G044L (RZ/G2L) SoC.
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 437a82cd48be..927d62cf99a3 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -156,3 +156,12 @@ config CLK_R9A06G032
depends on CLK_RENESAS
help
Enable this to support the clocks on Renesas R9A06G032 SoC.
+
+config CLK_RZG2L
+ bool "Renesas RZ/G2L family clock support"
+ depends on CLK_RENESAS
+ select DM_RESET
+
+config CLK_R9A07G044
+ bool "RZ/G2L (R9A07G044L) clock support"
+ depends on CLK_RZG2L
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 48373e61b901..df7e225e9ca4 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -23,3 +23,5 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
+obj-$(CONFIG_CLK_RZG2L) += rzg2l-cpg.o
+obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c
b/drivers/clk/renesas/r9a07g044-cpg.c
new file mode 100644
index ..2336028a7367
--- /dev/null
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -0,0 +1,384 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/G2L CPG driver
+ *
+ * Copyright (C) 2021-2023 Renesas Electronics Corp.
+ */
+
+#include
+#include
+#include
+#include
+
+#include "rzg2l-cpg.h"
+
+/* Divider tables */
+static const struct clk_div_table dtable_1_8[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_1_32[] = {
+ {0, 1},
+ {1, 2},
+ {2, 4},
+ {3, 8},
+ {4, 32},
+ {0, 0},
+};
+
+static const struct clk_div_table dtable_16_128[] = {
+ {0, 16},
+ {1, 32},
+ {2, 64},
+ {3, 128},
+ {0, 0},
+};
+
+/* Mux clock tables */
+static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
+static const char * const sel_pll5_4[] = { ".pll5_fout
[PATCH v3 08/21] arm: rmobile: Restrict PINCTRL_PFC selection to R-Car gen3/gen4
The RZ/G2L family uses CONFIG_RCAR_64 but does not share a common PFC driver with the R-Car gen3 & gen4 boards. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Marek Vasut --- v2->v3: No changes. v1->v2: * Added Marek's Reviewed-by. arch/arm/mach-rmobile/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index c5419e8d69c0..af1f99197d9f 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -9,7 +9,6 @@ config RCAR_64 select PHY select PINCONF select PINCTRL - select PINCTRL_PFC select POSITION_INDEPENDENT imply CMD_FS_UUID imply CMD_GPT @@ -29,6 +28,7 @@ config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" select RCAR_64 select SUPPORT_SPL + select PINCTRL_PFC imply SPL imply SPL_BOARD_INIT imply SPL_GZIP @@ -43,6 +43,7 @@ config RCAR_GEN3 config RCAR_GEN4 bool "Renesas ARM SoCs R-Car Gen4 (64bit)" select RCAR_64 + select PINCTRL_PFC config RZA1 prompt "Renesas ARM SoCs RZ/A1 (32bit)" -- 2.39.2
[PATCH v3 06/21] arm: rmobile: Add basic R9A07G044L SoC support
Add a config option for the R9A07G044L SoC used in the RZ/G2L so that we can make use of this in the subsequent driver patches. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Marek Vasut --- v2->v3: * Added Marek's Reviewed-by. v1->v2: * Reword config R9A07G044L description to improve clarity. arch/arm/mach-rmobile/Kconfig.rzg2l | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l index 37ff6cd34160..eda04df5c619 100644 --- a/arch/arm/mach-rmobile/Kconfig.rzg2l +++ b/arch/arm/mach-rmobile/Kconfig.rzg2l @@ -3,6 +3,11 @@ if RZG2L +config R9A07G044L + bool "Renesas R9A07G044L SoC" + help + Enable support for the Renesas R9A07G044L (RZ/G2L) SoC. + config MULTI_DTB_FIT_UNCOMPRESS_SZ default 0x8 if TARGET_RZG2L_SMARC_EVK -- 2.39.2
[PATCH v3 05/21] arm: rmobile: Add basic RZ/G2L family support
The Renesas RZ/G2L family includes the following ARM SoCs: * RZ/G2L (r9a07g044l) * RZ/G2LC (r9a07g044c) * RZ/G2UL (r9a07g043u) * RZ/V2L (r9a07g054l) Support for individual SoCs and evaluation boards will be added in separate patches. Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Marek Vasut --- v2->v3: No changes. v1->v2: * Sorted select/imply statements under config RZG2L. * Expanded help message for config RZG2L. * Added Marek's Reviewed-by. arch/arm/mach-rmobile/Kconfig| 15 +++ arch/arm/mach-rmobile/Kconfig.rzg2l | 12 arch/arm/mach-rmobile/include/mach/rmobile.h | 2 ++ arch/arm/mach-rmobile/include/mach/rzg2l.h | 13 + 4 files changed, 42 insertions(+) create mode 100644 arch/arm/mach-rmobile/Kconfig.rzg2l create mode 100644 arch/arm/mach-rmobile/include/mach/rzg2l.h diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 3061ccd34c8b..1d8d26d8367f 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -66,6 +66,20 @@ config RZN1 select SYSRESET_SYSCON imply CMD_DM +config RZG2L + prompt "Renesas RZ/G2L Family ARM SoCs" + select GICV3 + select RCAR_64 + imply MULTI_DTB_FIT + imply MULTI_DTB_FIT_USER_DEFINED_AREA + imply RENESAS_SDHI + imply SYS_MALLOC_F + help + Enable support for the Renesas RZ/G2L family of SoCs. Currently + support is only included for the RZ/G2L itself (based on the R9A07G044 + SoC). Support for additional SoCs in this family (RZ/G2LC, RZ/G2UL, + RZ/V2L & RZ/Five) is not yet available. + endchoice config SYS_SOC @@ -75,5 +89,6 @@ source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.64" source "arch/arm/mach-rmobile/Kconfig.rza1" source "arch/arm/mach-rmobile/Kconfig.rzn1" +source "arch/arm/mach-rmobile/Kconfig.rzg2l" endif diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-rmobile/Kconfig.rzg2l new file mode 100644 index ..37ff6cd34160 --- /dev/null +++ b/arch/arm/mach-rmobile/Kconfig.rzg2l @@ -0,0 +1,12 @@ +# Copyright (C) 2023 Renesas Electronics Corporation +# SPDX-License-Identifier: GPL-2.0+ + +if RZG2L + +config MULTI_DTB_FIT_UNCOMPRESS_SZ + default 0x8 if TARGET_RZG2L_SMARC_EVK + +config MULTI_DTB_FIT_USER_DEF_ADDR + default 0x4900 if TARGET_RZG2L_SMARC_EVK + +endif diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h index a14c2aad0a68..d326d5545a6f 100644 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ b/arch/arm/mach-rmobile/include/mach/rmobile.h @@ -19,6 +19,8 @@ #elif defined(CONFIG_RCAR_GEN4) #include #elif defined(CONFIG_R7S72100) +#elif defined(CONFIG_RZG2L) +#include #else #error "SOC Name not defined" #endif diff --git a/arch/arm/mach-rmobile/include/mach/rzg2l.h b/arch/arm/mach-rmobile/include/mach/rzg2l.h new file mode 100644 index ..057df5cb9d46 --- /dev/null +++ b/arch/arm/mach-rmobile/include/mach/rzg2l.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * RZ/G2L SoC Family support. + * Copyright (C) 2023 Renesas Electronics Corporation + */ + +#ifndef __ASM_ARCH_RZG2L_H +#define __ASM_ARCH_RZG2L_H + +#define GICD_BASE 0x1190 +#define GICR_BASE 0x1196 + +#endif /* __ASM_ARCH_RZG2L_H */ -- 2.39.2
[PATCH v3 04/21] dt-bindings: Add RZ/G2L IRQC bindings
Import bindings for the Interrupt Controller (IRQC) module in the Renesas RZ/G2L SoC family. This patch is based on the dt-bindings in Linux v6.5 (commit 52e12027d50affbf60c6c9c64db8017391b0c22e). Signed-off-by: Paul Barker Reviewed-by: Biju Das Reviewed-by: Lad Prabhakar Reviewed-by: Marek Vasut --- v2->v3: No changes. v1->v2: * Added the exact Linux commit we imported from. * Add Marek's Reivewed-by. .../interrupt-controller/irqc-rzg2l.h | 25 +++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h new file mode 100644 index ..34ce778885a1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family IRQC bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_IRQC_RZG2L_H +#define __DT_BINDINGS_IRQC_RZG2L_H + +/* NMI maps to SPI0 */ +#define RZG2L_NMI 0 + +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + +#endif /* __DT_BINDINGS_IRQC_RZG2L_H */ -- 2.39.2
[PATCH v3 00/21] Add support for the Renesas RZ/G2L SMARC EVK
These patches add initial support for the RZ/G2L SMARC Evaluation board kit (EVK), consisting of the RZ/G2L System-on-Module (SOM) based on the R9A07G044L2 SoC, and a common SMARC carrier board. Support is included for the CPG (clock & reset control module), PFC (pinctrl & gpio module), SDHI (eMMC & SD card interfaces) & SCIF (serial port) modules. Enough functionality is included to boot a modern Linux kernel from the eMMC or SD card interfaces. Further work will follow in time to add support for other interfaces on the RZ/G2L (such as Ethernet) and other SoCs in the RZ/G2L family (including the RZ/G2UL, RZ/G2LC, RZ/V2L & RZ/Five). See individual patches for details of the changes since v2 of this series. Paul Barker (21): serial: sh: Fix compile error when lacking HSCIF support dt-bindings: Add RZ/G2L CPG bindings dt-bindings: Add RZ/G2L PFC bindings dt-bindings: Add RZ/G2L IRQC bindings arm: rmobile: Add basic RZ/G2L family support arm: rmobile: Add basic R9A07G044L SoC support clk: renesas: Add RZ/G2L & RZ/G2LC CPG driver arm: rmobile: Restrict PINCTRL_PFC selection to R-Car gen3/gen4 cmd: gpio: Skip output on -ENOENT pinctrl: renesas: Add RZ/G2L PFC driver gpio: Add RZ/G2L GPIO driver serial: sh: Fix error handling serial: sh: Sort includes serial: sh: Add RZ/G2L SCIF support mmc: renesas-sdhi: Refactor probe function mmc: renesas-sdhi: Initialize module on RZ/G2L arm: rmobile: Include in header arm: rmobile: Add CPU detection for RZ/G2L arm: rmobile: Support RZ/G2L memory map arm: dts: Import RZ/G2L SMARC EVK device tree board: rzg2l: Add RZ/G2L SMARC EVK board arch/arm/dts/Makefile |3 + arch/arm/dts/r9a07g044.dtsi | 1273 + arch/arm/dts/r9a07g044l2-smarc.dts| 18 + arch/arm/dts/r9a07g044l2.dtsi | 13 + arch/arm/dts/rz-smarc-common.dtsi | 183 +++ arch/arm/dts/rzg2l-smarc-pinfunction.dtsi | 137 ++ arch/arm/dts/rzg2l-smarc-som.dtsi | 353 + arch/arm/dts/rzg2l-smarc.dtsi | 144 ++ arch/arm/mach-rmobile/Kconfig | 22 +- arch/arm/mach-rmobile/Kconfig.rzg2l | 32 + arch/arm/mach-rmobile/Makefile|5 +- arch/arm/mach-rmobile/cpu_info-rzg2l.c| 63 + arch/arm/mach-rmobile/include/mach/rmobile.h |5 + arch/arm/mach-rmobile/include/mach/rzg2l.h| 13 + arch/arm/mach-rmobile/memmap-rzg2l.c | 127 ++ board/renesas/rzg2l/Kconfig | 18 + board/renesas/rzg2l/MAINTAINERS |6 + board/renesas/rzg2l/Makefile |4 + board/renesas/rzg2l/rzg2l.c | 67 + cmd/gpio.c|4 +- configs/renesas_rzg2l_smarc_defconfig | 52 + drivers/clk/renesas/Kconfig |9 + drivers/clk/renesas/Makefile |2 + drivers/clk/renesas/r9a07g044-cpg.c | 384 + drivers/clk/renesas/rzg2l-cpg.c | 505 +++ drivers/clk/renesas/rzg2l-cpg.h | 319 + drivers/gpio/Kconfig |7 + drivers/gpio/Makefile |1 + drivers/gpio/rzg2l-gpio.c | 170 +++ drivers/mmc/renesas-sdhi.c| 81 +- drivers/pinctrl/renesas/Kconfig |9 + drivers/pinctrl/renesas/Makefile |1 + drivers/pinctrl/renesas/rzg2l-pfc.c | 625 drivers/serial/serial_sh.c| 45 +- drivers/serial/serial_sh.h| 19 +- include/configs/rzg2l-smarc.h | 14 + include/dt-bindings/clock/r9a07g044-cpg.h | 220 +++ .../interrupt-controller/irqc-rzg2l.h | 25 + include/dt-bindings/pinctrl/rzg2l-pinctrl.h | 23 + include/renesas/rzg2l-pfc.h | 110 ++ 40 files changed, 5095 insertions(+), 16 deletions(-) create mode 100644 arch/arm/dts/r9a07g044.dtsi create mode 100644 arch/arm/dts/r9a07g044l2-smarc.dts create mode 100644 arch/arm/dts/r9a07g044l2.dtsi create mode 100644 arch/arm/dts/rz-smarc-common.dtsi create mode 100644 arch/arm/dts/rzg2l-smarc-pinfunction.dtsi create mode 100644 arch/arm/dts/rzg2l-smarc-som.dtsi create mode 100644 arch/arm/dts/rzg2l-smarc.dtsi create mode 100644 arch/arm/mach-rmobile/Kconfig.rzg2l create mode 100644 arch/arm/mach-rmobile/cpu_info-rzg2l.c create mode 100644 arch/arm/mach-rmobile/include/mach/rzg2l.h create mode 100644 arch/arm/mach-rmobile/memmap-rzg2l.c create mode 100644 board/renesas/rzg2l/Kconfig create mode 100644 board/renesas/rzg2l/MAINTAINERS create mode 100644 board/renesas/rzg2l/Makefile create mode 100644 board/renesas/rzg2l/rzg2l.c create mode 100644 configs/renesas_rzg2l_smarc_defconfig create mode 100644 drivers/clk/renesas/r9a07g044-cpg.c create mode 100644 drivers/clk/renesas/rzg2l-cpg.c create
